2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/list.h>
25 #include <linux/slab.h>
26 #include <linux/pci.h>
27 #include <linux/acpi.h>
29 #include <linux/firmware.h>
30 #include <drm/amdgpu_drm.h>
32 #include "cgs_linux.h"
34 #include "amdgpu_ucode.h"
36 struct amdgpu_cgs_device
{
37 struct cgs_device base
;
38 struct amdgpu_device
*adev
;
41 #define CGS_FUNC_ADEV \
42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev
45 static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device
*cgs_device
,
46 enum cgs_gpu_mem_type type
,
47 uint64_t size
, uint64_t align
,
48 uint64_t min_offset
, uint64_t max_offset
,
55 struct amdgpu_bo
*obj
;
56 struct ttm_placement placement
;
57 struct ttm_place place
;
59 if (min_offset
> max_offset
) {
64 /* fail if the alignment is not a power of 2 */
65 if (((align
!= 1) && (align
& (align
- 1)))
66 || size
== 0 || align
== 0)
71 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB
:
72 case CGS_GPU_MEM_TYPE__VISIBLE_FB
:
73 flags
= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
74 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
;
75 domain
= AMDGPU_GEM_DOMAIN_VRAM
;
76 if (max_offset
> adev
->mc
.real_vram_size
)
78 place
.fpfn
= min_offset
>> PAGE_SHIFT
;
79 place
.lpfn
= max_offset
>> PAGE_SHIFT
;
80 place
.flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_UNCACHED
|
83 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB
:
84 case CGS_GPU_MEM_TYPE__INVISIBLE_FB
:
85 flags
= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
86 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
;
87 domain
= AMDGPU_GEM_DOMAIN_VRAM
;
88 if (adev
->mc
.visible_vram_size
< adev
->mc
.real_vram_size
) {
90 max(min_offset
, adev
->mc
.visible_vram_size
) >> PAGE_SHIFT
;
92 min(max_offset
, adev
->mc
.real_vram_size
) >> PAGE_SHIFT
;
93 place
.flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_UNCACHED
|
98 case CGS_GPU_MEM_TYPE__GART_CACHEABLE
:
99 domain
= AMDGPU_GEM_DOMAIN_GTT
;
100 place
.fpfn
= min_offset
>> PAGE_SHIFT
;
101 place
.lpfn
= max_offset
>> PAGE_SHIFT
;
102 place
.flags
= TTM_PL_FLAG_CACHED
| TTM_PL_FLAG_TT
;
104 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
:
105 flags
= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
106 domain
= AMDGPU_GEM_DOMAIN_GTT
;
107 place
.fpfn
= min_offset
>> PAGE_SHIFT
;
108 place
.lpfn
= max_offset
>> PAGE_SHIFT
;
109 place
.flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_TT
|
110 TTM_PL_FLAG_UNCACHED
;
119 placement
.placement
= &place
;
120 placement
.num_placement
= 1;
121 placement
.busy_placement
= &place
;
122 placement
.num_busy_placement
= 1;
124 ret
= amdgpu_bo_create_restricted(adev
, size
, PAGE_SIZE
,
126 NULL
, &placement
, NULL
,
129 DRM_ERROR("(%d) bo create failed\n", ret
);
132 *handle
= (cgs_handle_t
)obj
;
137 static int amdgpu_cgs_free_gpu_mem(struct cgs_device
*cgs_device
, cgs_handle_t handle
)
139 struct amdgpu_bo
*obj
= (struct amdgpu_bo
*)handle
;
142 int r
= amdgpu_bo_reserve(obj
, true);
143 if (likely(r
== 0)) {
144 amdgpu_bo_kunmap(obj
);
145 amdgpu_bo_unpin(obj
);
146 amdgpu_bo_unreserve(obj
);
148 amdgpu_bo_unref(&obj
);
154 static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device
*cgs_device
, cgs_handle_t handle
,
158 u64 min_offset
, max_offset
;
159 struct amdgpu_bo
*obj
= (struct amdgpu_bo
*)handle
;
161 WARN_ON_ONCE(obj
->placement
.num_placement
> 1);
163 min_offset
= obj
->placements
[0].fpfn
<< PAGE_SHIFT
;
164 max_offset
= obj
->placements
[0].lpfn
<< PAGE_SHIFT
;
166 r
= amdgpu_bo_reserve(obj
, true);
167 if (unlikely(r
!= 0))
169 r
= amdgpu_bo_pin_restricted(obj
, obj
->prefered_domains
,
170 min_offset
, max_offset
, mcaddr
);
171 amdgpu_bo_unreserve(obj
);
175 static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device
*cgs_device
, cgs_handle_t handle
)
178 struct amdgpu_bo
*obj
= (struct amdgpu_bo
*)handle
;
179 r
= amdgpu_bo_reserve(obj
, true);
180 if (unlikely(r
!= 0))
182 r
= amdgpu_bo_unpin(obj
);
183 amdgpu_bo_unreserve(obj
);
187 static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device
*cgs_device
, cgs_handle_t handle
,
191 struct amdgpu_bo
*obj
= (struct amdgpu_bo
*)handle
;
192 r
= amdgpu_bo_reserve(obj
, true);
193 if (unlikely(r
!= 0))
195 r
= amdgpu_bo_kmap(obj
, map
);
196 amdgpu_bo_unreserve(obj
);
200 static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device
*cgs_device
, cgs_handle_t handle
)
203 struct amdgpu_bo
*obj
= (struct amdgpu_bo
*)handle
;
204 r
= amdgpu_bo_reserve(obj
, true);
205 if (unlikely(r
!= 0))
207 amdgpu_bo_kunmap(obj
);
208 amdgpu_bo_unreserve(obj
);
212 static uint32_t amdgpu_cgs_read_register(struct cgs_device
*cgs_device
, unsigned offset
)
215 return RREG32(offset
);
218 static void amdgpu_cgs_write_register(struct cgs_device
*cgs_device
, unsigned offset
,
222 WREG32(offset
, value
);
225 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device
*cgs_device
,
226 enum cgs_ind_reg space
,
231 case CGS_IND_REG__MMIO
:
232 return RREG32_IDX(index
);
233 case CGS_IND_REG__PCIE
:
234 return RREG32_PCIE(index
);
235 case CGS_IND_REG__SMC
:
236 return RREG32_SMC(index
);
237 case CGS_IND_REG__UVD_CTX
:
238 return RREG32_UVD_CTX(index
);
239 case CGS_IND_REG__DIDT
:
240 return RREG32_DIDT(index
);
241 case CGS_IND_REG_GC_CAC
:
242 return RREG32_GC_CAC(index
);
243 case CGS_IND_REG_SE_CAC
:
244 return RREG32_SE_CAC(index
);
245 case CGS_IND_REG__AUDIO_ENDPT
:
246 DRM_ERROR("audio endpt register access not implemented.\n");
249 WARN(1, "Invalid indirect register space");
253 static void amdgpu_cgs_write_ind_register(struct cgs_device
*cgs_device
,
254 enum cgs_ind_reg space
,
255 unsigned index
, uint32_t value
)
259 case CGS_IND_REG__MMIO
:
260 return WREG32_IDX(index
, value
);
261 case CGS_IND_REG__PCIE
:
262 return WREG32_PCIE(index
, value
);
263 case CGS_IND_REG__SMC
:
264 return WREG32_SMC(index
, value
);
265 case CGS_IND_REG__UVD_CTX
:
266 return WREG32_UVD_CTX(index
, value
);
267 case CGS_IND_REG__DIDT
:
268 return WREG32_DIDT(index
, value
);
269 case CGS_IND_REG_GC_CAC
:
270 return WREG32_GC_CAC(index
, value
);
271 case CGS_IND_REG_SE_CAC
:
272 return WREG32_SE_CAC(index
, value
);
273 case CGS_IND_REG__AUDIO_ENDPT
:
274 DRM_ERROR("audio endpt register access not implemented.\n");
277 WARN(1, "Invalid indirect register space");
280 static int amdgpu_cgs_get_pci_resource(struct cgs_device
*cgs_device
,
281 enum cgs_resource_type resource_type
,
284 uint64_t *resource_base
)
288 if (resource_base
== NULL
)
291 switch (resource_type
) {
292 case CGS_RESOURCE_TYPE_MMIO
:
293 if (adev
->rmmio_size
== 0)
295 if ((offset
+ size
) > adev
->rmmio_size
)
297 *resource_base
= adev
->rmmio_base
;
299 case CGS_RESOURCE_TYPE_DOORBELL
:
300 if (adev
->doorbell
.size
== 0)
302 if ((offset
+ size
) > adev
->doorbell
.size
)
304 *resource_base
= adev
->doorbell
.base
;
306 case CGS_RESOURCE_TYPE_FB
:
307 case CGS_RESOURCE_TYPE_IO
:
308 case CGS_RESOURCE_TYPE_ROM
:
314 static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device
*cgs_device
,
315 unsigned table
, uint16_t *size
,
316 uint8_t *frev
, uint8_t *crev
)
321 if (amdgpu_atom_parse_data_header(
322 adev
->mode_info
.atom_context
, table
, size
,
323 frev
, crev
, &data_start
))
324 return (uint8_t*)adev
->mode_info
.atom_context
->bios
+
330 static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device
*cgs_device
, unsigned table
,
331 uint8_t *frev
, uint8_t *crev
)
335 if (amdgpu_atom_parse_cmd_header(
336 adev
->mode_info
.atom_context
, table
,
343 static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device
*cgs_device
, unsigned table
,
348 return amdgpu_atom_execute_table(
349 adev
->mode_info
.atom_context
, table
, args
);
352 struct cgs_irq_params
{
354 cgs_irq_source_set_func_t set
;
355 cgs_irq_handler_func_t handler
;
359 static int cgs_set_irq_state(struct amdgpu_device
*adev
,
360 struct amdgpu_irq_src
*src
,
362 enum amdgpu_interrupt_state state
)
364 struct cgs_irq_params
*irq_params
=
365 (struct cgs_irq_params
*)src
->data
;
368 if (!irq_params
->set
)
370 return irq_params
->set(irq_params
->private_data
,
376 static int cgs_process_irq(struct amdgpu_device
*adev
,
377 struct amdgpu_irq_src
*source
,
378 struct amdgpu_iv_entry
*entry
)
380 struct cgs_irq_params
*irq_params
=
381 (struct cgs_irq_params
*)source
->data
;
384 if (!irq_params
->handler
)
386 return irq_params
->handler(irq_params
->private_data
,
391 static const struct amdgpu_irq_src_funcs cgs_irq_funcs
= {
392 .set
= cgs_set_irq_state
,
393 .process
= cgs_process_irq
,
396 static int amdgpu_cgs_add_irq_source(void *cgs_device
,
400 cgs_irq_source_set_func_t set
,
401 cgs_irq_handler_func_t handler
,
406 struct cgs_irq_params
*irq_params
;
407 struct amdgpu_irq_src
*source
=
408 kzalloc(sizeof(struct amdgpu_irq_src
), GFP_KERNEL
);
412 kzalloc(sizeof(struct cgs_irq_params
), GFP_KERNEL
);
417 source
->num_types
= num_types
;
418 source
->funcs
= &cgs_irq_funcs
;
419 irq_params
->src_id
= src_id
;
420 irq_params
->set
= set
;
421 irq_params
->handler
= handler
;
422 irq_params
->private_data
= private_data
;
423 source
->data
= (void *)irq_params
;
424 ret
= amdgpu_irq_add_id(adev
, client_id
, src_id
, source
);
433 static int amdgpu_cgs_irq_get(void *cgs_device
, unsigned client_id
,
434 unsigned src_id
, unsigned type
)
438 if (!adev
->irq
.client
[client_id
].sources
)
441 return amdgpu_irq_get(adev
, adev
->irq
.client
[client_id
].sources
[src_id
], type
);
444 static int amdgpu_cgs_irq_put(void *cgs_device
, unsigned client_id
,
445 unsigned src_id
, unsigned type
)
449 if (!adev
->irq
.client
[client_id
].sources
)
452 return amdgpu_irq_put(adev
, adev
->irq
.client
[client_id
].sources
[src_id
], type
);
455 static int amdgpu_cgs_set_clockgating_state(struct cgs_device
*cgs_device
,
456 enum amd_ip_block_type block_type
,
457 enum amd_clockgating_state state
)
462 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
463 if (!adev
->ip_blocks
[i
].status
.valid
)
466 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
467 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state(
476 static int amdgpu_cgs_set_powergating_state(struct cgs_device
*cgs_device
,
477 enum amd_ip_block_type block_type
,
478 enum amd_powergating_state state
)
483 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
484 if (!adev
->ip_blocks
[i
].status
.valid
)
487 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
488 r
= adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state(
498 static uint32_t fw_type_convert(struct cgs_device
*cgs_device
, uint32_t fw_type
)
501 enum AMDGPU_UCODE_ID result
= AMDGPU_UCODE_ID_MAXIMUM
;
504 case CGS_UCODE_ID_SDMA0
:
505 result
= AMDGPU_UCODE_ID_SDMA0
;
507 case CGS_UCODE_ID_SDMA1
:
508 result
= AMDGPU_UCODE_ID_SDMA1
;
510 case CGS_UCODE_ID_CP_CE
:
511 result
= AMDGPU_UCODE_ID_CP_CE
;
513 case CGS_UCODE_ID_CP_PFP
:
514 result
= AMDGPU_UCODE_ID_CP_PFP
;
516 case CGS_UCODE_ID_CP_ME
:
517 result
= AMDGPU_UCODE_ID_CP_ME
;
519 case CGS_UCODE_ID_CP_MEC
:
520 case CGS_UCODE_ID_CP_MEC_JT1
:
521 result
= AMDGPU_UCODE_ID_CP_MEC1
;
523 case CGS_UCODE_ID_CP_MEC_JT2
:
524 /* for VI. JT2 should be the same as JT1, because:
525 1, MEC2 and MEC1 use exactly same FW.
526 2, JT2 is not pached but JT1 is.
528 if (adev
->asic_type
>= CHIP_TOPAZ
)
529 result
= AMDGPU_UCODE_ID_CP_MEC1
;
531 result
= AMDGPU_UCODE_ID_CP_MEC2
;
533 case CGS_UCODE_ID_RLC_G
:
534 result
= AMDGPU_UCODE_ID_RLC_G
;
536 case CGS_UCODE_ID_STORAGE
:
537 result
= AMDGPU_UCODE_ID_STORAGE
;
540 DRM_ERROR("Firmware type not supported\n");
545 static int amdgpu_cgs_rel_firmware(struct cgs_device
*cgs_device
, enum cgs_ucode_id type
)
548 if ((CGS_UCODE_ID_SMU
== type
) || (CGS_UCODE_ID_SMU_SK
== type
)) {
549 release_firmware(adev
->pm
.fw
);
553 /* cannot release other firmware because they are not created by cgs */
557 static uint16_t amdgpu_get_firmware_version(struct cgs_device
*cgs_device
,
558 enum cgs_ucode_id type
)
561 uint16_t fw_version
= 0;
564 case CGS_UCODE_ID_SDMA0
:
565 fw_version
= adev
->sdma
.instance
[0].fw_version
;
567 case CGS_UCODE_ID_SDMA1
:
568 fw_version
= adev
->sdma
.instance
[1].fw_version
;
570 case CGS_UCODE_ID_CP_CE
:
571 fw_version
= adev
->gfx
.ce_fw_version
;
573 case CGS_UCODE_ID_CP_PFP
:
574 fw_version
= adev
->gfx
.pfp_fw_version
;
576 case CGS_UCODE_ID_CP_ME
:
577 fw_version
= adev
->gfx
.me_fw_version
;
579 case CGS_UCODE_ID_CP_MEC
:
580 fw_version
= adev
->gfx
.mec_fw_version
;
582 case CGS_UCODE_ID_CP_MEC_JT1
:
583 fw_version
= adev
->gfx
.mec_fw_version
;
585 case CGS_UCODE_ID_CP_MEC_JT2
:
586 fw_version
= adev
->gfx
.mec_fw_version
;
588 case CGS_UCODE_ID_RLC_G
:
589 fw_version
= adev
->gfx
.rlc_fw_version
;
591 case CGS_UCODE_ID_STORAGE
:
594 DRM_ERROR("firmware type %d do not have version\n", type
);
600 static int amdgpu_cgs_enter_safe_mode(struct cgs_device
*cgs_device
,
605 if (adev
->gfx
.rlc
.funcs
->enter_safe_mode
== NULL
||
606 adev
->gfx
.rlc
.funcs
->exit_safe_mode
== NULL
)
610 adev
->gfx
.rlc
.funcs
->enter_safe_mode(adev
);
612 adev
->gfx
.rlc
.funcs
->exit_safe_mode(adev
);
617 static void amdgpu_cgs_lock_grbm_idx(struct cgs_device
*cgs_device
,
623 mutex_lock(&adev
->grbm_idx_mutex
);
625 mutex_unlock(&adev
->grbm_idx_mutex
);
628 static int amdgpu_cgs_get_firmware_info(struct cgs_device
*cgs_device
,
629 enum cgs_ucode_id type
,
630 struct cgs_firmware_info
*info
)
634 if ((CGS_UCODE_ID_SMU
!= type
) && (CGS_UCODE_ID_SMU_SK
!= type
)) {
637 const struct gfx_firmware_header_v1_0
*header
;
638 enum AMDGPU_UCODE_ID id
;
639 struct amdgpu_firmware_info
*ucode
;
641 id
= fw_type_convert(cgs_device
, type
);
642 ucode
= &adev
->firmware
.ucode
[id
];
643 if (ucode
->fw
== NULL
)
646 gpu_addr
= ucode
->mc_addr
;
647 header
= (const struct gfx_firmware_header_v1_0
*)ucode
->fw
->data
;
648 data_size
= le32_to_cpu(header
->header
.ucode_size_bytes
);
650 if ((type
== CGS_UCODE_ID_CP_MEC_JT1
) ||
651 (type
== CGS_UCODE_ID_CP_MEC_JT2
)) {
652 gpu_addr
+= ALIGN(le32_to_cpu(header
->header
.ucode_size_bytes
), PAGE_SIZE
);
653 data_size
= le32_to_cpu(header
->jt_size
) << 2;
656 info
->kptr
= ucode
->kaddr
;
657 info
->image_size
= data_size
;
658 info
->mc_addr
= gpu_addr
;
659 info
->version
= (uint16_t)le32_to_cpu(header
->header
.ucode_version
);
661 if (CGS_UCODE_ID_CP_MEC
== type
)
662 info
->image_size
= (header
->jt_offset
) << 2;
664 info
->fw_version
= amdgpu_get_firmware_version(cgs_device
, type
);
665 info
->feature_version
= (uint16_t)le32_to_cpu(header
->ucode_feature_version
);
667 char fw_name
[30] = {0};
670 uint32_t ucode_start_address
;
672 const struct smc_firmware_header_v1_0
*hdr
;
673 const struct common_firmware_header
*header
;
674 struct amdgpu_firmware_info
*ucode
= NULL
;
677 switch (adev
->asic_type
) {
679 if (((adev
->pdev
->device
== 0x6900) && (adev
->pdev
->revision
== 0x81)) ||
680 ((adev
->pdev
->device
== 0x6900) && (adev
->pdev
->revision
== 0x83)) ||
681 ((adev
->pdev
->device
== 0x6907) && (adev
->pdev
->revision
== 0x87))) {
682 info
->is_kicker
= true;
683 strcpy(fw_name
, "amdgpu/topaz_k_smc.bin");
685 strcpy(fw_name
, "amdgpu/topaz_smc.bin");
688 if (((adev
->pdev
->device
== 0x6939) && (adev
->pdev
->revision
== 0xf1)) ||
689 ((adev
->pdev
->device
== 0x6938) && (adev
->pdev
->revision
== 0xf1))) {
690 info
->is_kicker
= true;
691 strcpy(fw_name
, "amdgpu/tonga_k_smc.bin");
693 strcpy(fw_name
, "amdgpu/tonga_smc.bin");
696 strcpy(fw_name
, "amdgpu/fiji_smc.bin");
699 if (type
== CGS_UCODE_ID_SMU
) {
700 if (((adev
->pdev
->device
== 0x67ef) &&
701 ((adev
->pdev
->revision
== 0xe0) ||
702 (adev
->pdev
->revision
== 0xe2) ||
703 (adev
->pdev
->revision
== 0xe5))) ||
704 ((adev
->pdev
->device
== 0x67ff) &&
705 ((adev
->pdev
->revision
== 0xcf) ||
706 (adev
->pdev
->revision
== 0xef) ||
707 (adev
->pdev
->revision
== 0xff)))) {
708 info
->is_kicker
= true;
709 strcpy(fw_name
, "amdgpu/polaris11_k_smc.bin");
711 strcpy(fw_name
, "amdgpu/polaris11_smc.bin");
712 } else if (type
== CGS_UCODE_ID_SMU_SK
) {
713 strcpy(fw_name
, "amdgpu/polaris11_smc_sk.bin");
717 if (type
== CGS_UCODE_ID_SMU
) {
718 if ((adev
->pdev
->device
== 0x67df) &&
719 ((adev
->pdev
->revision
== 0xe0) ||
720 (adev
->pdev
->revision
== 0xe3) ||
721 (adev
->pdev
->revision
== 0xe4) ||
722 (adev
->pdev
->revision
== 0xe5) ||
723 (adev
->pdev
->revision
== 0xe7) ||
724 (adev
->pdev
->revision
== 0xef))) {
725 info
->is_kicker
= true;
726 strcpy(fw_name
, "amdgpu/polaris10_k_smc.bin");
728 strcpy(fw_name
, "amdgpu/polaris10_smc.bin");
729 } else if (type
== CGS_UCODE_ID_SMU_SK
) {
730 strcpy(fw_name
, "amdgpu/polaris10_smc_sk.bin");
734 strcpy(fw_name
, "amdgpu/polaris12_smc.bin");
737 if ((adev
->pdev
->device
== 0x687f) &&
738 ((adev
->pdev
->revision
== 0xc0) ||
739 (adev
->pdev
->revision
== 0xc1) ||
740 (adev
->pdev
->revision
== 0xc3)))
741 strcpy(fw_name
, "amdgpu/vega10_acg_smc.bin");
743 strcpy(fw_name
, "amdgpu/vega10_smc.bin");
746 DRM_ERROR("SMC firmware not supported\n");
750 err
= request_firmware(&adev
->pm
.fw
, fw_name
, adev
->dev
);
752 DRM_ERROR("Failed to request firmware\n");
756 err
= amdgpu_ucode_validate(adev
->pm
.fw
);
758 DRM_ERROR("Failed to load firmware \"%s\"", fw_name
);
759 release_firmware(adev
->pm
.fw
);
764 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
765 ucode
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SMC
];
766 ucode
->ucode_id
= AMDGPU_UCODE_ID_SMC
;
767 ucode
->fw
= adev
->pm
.fw
;
768 header
= (const struct common_firmware_header
*)ucode
->fw
->data
;
769 adev
->firmware
.fw_size
+=
770 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
774 hdr
= (const struct smc_firmware_header_v1_0
*) adev
->pm
.fw
->data
;
775 amdgpu_ucode_print_smc_hdr(&hdr
->header
);
776 adev
->pm
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
777 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
);
778 ucode_start_address
= le32_to_cpu(hdr
->ucode_start_addr
);
779 src
= (const uint8_t *)(adev
->pm
.fw
->data
+
780 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
782 info
->version
= adev
->pm
.fw_version
;
783 info
->image_size
= ucode_size
;
784 info
->ucode_start_address
= ucode_start_address
;
785 info
->kptr
= (void *)src
;
790 static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device
)
793 return amdgpu_sriov_vf(adev
);
796 static int amdgpu_cgs_query_system_info(struct cgs_device
*cgs_device
,
797 struct cgs_system_info
*sys_info
)
801 if (NULL
== sys_info
)
804 if (sizeof(struct cgs_system_info
) != sys_info
->size
)
807 switch (sys_info
->info_id
) {
808 case CGS_SYSTEM_INFO_ADAPTER_BDF_ID
:
809 sys_info
->value
= adev
->pdev
->devfn
| (adev
->pdev
->bus
->number
<< 8);
811 case CGS_SYSTEM_INFO_PCIE_GEN_INFO
:
812 sys_info
->value
= adev
->pm
.pcie_gen_mask
;
814 case CGS_SYSTEM_INFO_PCIE_MLW
:
815 sys_info
->value
= adev
->pm
.pcie_mlw_mask
;
817 case CGS_SYSTEM_INFO_PCIE_DEV
:
818 sys_info
->value
= adev
->pdev
->device
;
820 case CGS_SYSTEM_INFO_PCIE_REV
:
821 sys_info
->value
= adev
->pdev
->revision
;
823 case CGS_SYSTEM_INFO_CG_FLAGS
:
824 sys_info
->value
= adev
->cg_flags
;
826 case CGS_SYSTEM_INFO_PG_FLAGS
:
827 sys_info
->value
= adev
->pg_flags
;
829 case CGS_SYSTEM_INFO_GFX_CU_INFO
:
830 sys_info
->value
= adev
->gfx
.cu_info
.number
;
832 case CGS_SYSTEM_INFO_GFX_SE_INFO
:
833 sys_info
->value
= adev
->gfx
.config
.max_shader_engines
;
835 case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID
:
836 sys_info
->value
= adev
->pdev
->subsystem_device
;
838 case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID
:
839 sys_info
->value
= adev
->pdev
->subsystem_vendor
;
848 static int amdgpu_cgs_get_active_displays_info(struct cgs_device
*cgs_device
,
849 struct cgs_display_info
*info
)
852 struct amdgpu_crtc
*amdgpu_crtc
;
853 struct drm_device
*ddev
= adev
->ddev
;
854 struct drm_crtc
*crtc
;
855 uint32_t line_time_us
, vblank_lines
;
856 struct cgs_mode_info
*mode_info
;
861 mode_info
= info
->mode_info
;
863 /* if the displays are off, vblank time is max */
864 mode_info
->vblank_time_us
= 0xffffffff;
865 /* always set the reference clock */
866 mode_info
->ref_clock
= adev
->clock
.spll
.reference_freq
;
869 if (adev
->mode_info
.num_crtc
&& adev
->mode_info
.mode_config_initialized
) {
870 list_for_each_entry(crtc
,
871 &ddev
->mode_config
.crtc_list
, head
) {
872 amdgpu_crtc
= to_amdgpu_crtc(crtc
);
874 info
->active_display_mask
|= (1 << amdgpu_crtc
->crtc_id
);
875 info
->display_count
++;
877 if (mode_info
!= NULL
&&
878 crtc
->enabled
&& amdgpu_crtc
->enabled
&&
879 amdgpu_crtc
->hw_mode
.clock
) {
880 line_time_us
= (amdgpu_crtc
->hw_mode
.crtc_htotal
* 1000) /
881 amdgpu_crtc
->hw_mode
.clock
;
882 vblank_lines
= amdgpu_crtc
->hw_mode
.crtc_vblank_end
-
883 amdgpu_crtc
->hw_mode
.crtc_vdisplay
+
884 (amdgpu_crtc
->v_border
* 2);
885 mode_info
->vblank_time_us
= vblank_lines
* line_time_us
;
886 mode_info
->refresh_rate
= drm_mode_vrefresh(&amdgpu_crtc
->hw_mode
);
887 mode_info
->ref_clock
= adev
->clock
.spll
.reference_freq
;
897 static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device
*cgs_device
, bool enabled
)
901 adev
->pm
.dpm_enabled
= enabled
;
906 /** \brief evaluate acpi namespace object, handle or pathname must be valid
908 * \param info input/output arguments for the control method
912 #if defined(CONFIG_ACPI)
913 static int amdgpu_cgs_acpi_eval_object(struct cgs_device
*cgs_device
,
914 struct cgs_acpi_method_info
*info
)
918 struct acpi_object_list input
;
919 struct acpi_buffer output
= { ACPI_ALLOCATE_BUFFER
, NULL
};
920 union acpi_object
*params
, *obj
;
921 uint8_t name
[5] = {'\0'};
922 struct cgs_acpi_method_argument
*argument
;
927 handle
= ACPI_HANDLE(&adev
->pdev
->dev
);
931 memset(&input
, 0, sizeof(struct acpi_object_list
));
933 /* validate input info */
934 if (info
->size
!= sizeof(struct cgs_acpi_method_info
))
937 input
.count
= info
->input_count
;
938 if (info
->input_count
> 0) {
939 if (info
->pinput_argument
== NULL
)
941 argument
= info
->pinput_argument
;
942 for (i
= 0; i
< info
->input_count
; i
++) {
943 if (((argument
->type
== ACPI_TYPE_STRING
) ||
944 (argument
->type
== ACPI_TYPE_BUFFER
)) &&
945 (argument
->pointer
== NULL
))
951 if (info
->output_count
> 0) {
952 if (info
->poutput_argument
== NULL
)
954 argument
= info
->poutput_argument
;
955 for (i
= 0; i
< info
->output_count
; i
++) {
956 if (((argument
->type
== ACPI_TYPE_STRING
) ||
957 (argument
->type
== ACPI_TYPE_BUFFER
))
958 && (argument
->pointer
== NULL
))
964 /* The path name passed to acpi_evaluate_object should be null terminated */
965 if ((info
->field
& CGS_ACPI_FIELD_METHOD_NAME
) != 0) {
966 strncpy(name
, (char *)&(info
->name
), sizeof(uint32_t));
970 /* parse input parameters */
971 if (input
.count
> 0) {
972 input
.pointer
= params
=
973 kzalloc(sizeof(union acpi_object
) * input
.count
, GFP_KERNEL
);
977 argument
= info
->pinput_argument
;
979 for (i
= 0; i
< input
.count
; i
++) {
980 params
->type
= argument
->type
;
981 switch (params
->type
) {
982 case ACPI_TYPE_INTEGER
:
983 params
->integer
.value
= argument
->value
;
985 case ACPI_TYPE_STRING
:
986 params
->string
.length
= argument
->data_length
;
987 params
->string
.pointer
= argument
->pointer
;
989 case ACPI_TYPE_BUFFER
:
990 params
->buffer
.length
= argument
->data_length
;
991 params
->buffer
.pointer
= argument
->pointer
;
1001 /* parse output info */
1002 count
= info
->output_count
;
1003 argument
= info
->poutput_argument
;
1005 /* evaluate the acpi method */
1006 status
= acpi_evaluate_object(handle
, name
, &input
, &output
);
1008 if (ACPI_FAILURE(status
)) {
1013 /* return the output info */
1014 obj
= output
.pointer
;
1017 if ((obj
->type
!= ACPI_TYPE_PACKAGE
) ||
1018 (obj
->package
.count
!= count
)) {
1022 params
= obj
->package
.elements
;
1026 if (params
== NULL
) {
1031 for (i
= 0; i
< count
; i
++) {
1032 if (argument
->type
!= params
->type
) {
1036 switch (params
->type
) {
1037 case ACPI_TYPE_INTEGER
:
1038 argument
->value
= params
->integer
.value
;
1040 case ACPI_TYPE_STRING
:
1041 if ((params
->string
.length
!= argument
->data_length
) ||
1042 (params
->string
.pointer
== NULL
)) {
1046 strncpy(argument
->pointer
,
1047 params
->string
.pointer
,
1048 params
->string
.length
);
1050 case ACPI_TYPE_BUFFER
:
1051 if (params
->buffer
.pointer
== NULL
) {
1055 memcpy(argument
->pointer
,
1056 params
->buffer
.pointer
,
1057 argument
->data_length
);
1070 kfree((void *)input
.pointer
);
1074 static int amdgpu_cgs_acpi_eval_object(struct cgs_device
*cgs_device
,
1075 struct cgs_acpi_method_info
*info
)
1081 static int amdgpu_cgs_call_acpi_method(struct cgs_device
*cgs_device
,
1082 uint32_t acpi_method
,
1083 uint32_t acpi_function
,
1084 void *pinput
, void *poutput
,
1085 uint32_t output_count
,
1086 uint32_t input_size
,
1087 uint32_t output_size
)
1089 struct cgs_acpi_method_argument acpi_input
[2] = { {0}, {0} };
1090 struct cgs_acpi_method_argument acpi_output
= {0};
1091 struct cgs_acpi_method_info info
= {0};
1093 acpi_input
[0].type
= CGS_ACPI_TYPE_INTEGER
;
1094 acpi_input
[0].data_length
= sizeof(uint32_t);
1095 acpi_input
[0].value
= acpi_function
;
1097 acpi_input
[1].type
= CGS_ACPI_TYPE_BUFFER
;
1098 acpi_input
[1].data_length
= input_size
;
1099 acpi_input
[1].pointer
= pinput
;
1101 acpi_output
.type
= CGS_ACPI_TYPE_BUFFER
;
1102 acpi_output
.data_length
= output_size
;
1103 acpi_output
.pointer
= poutput
;
1105 info
.size
= sizeof(struct cgs_acpi_method_info
);
1106 info
.field
= CGS_ACPI_FIELD_METHOD_NAME
| CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT
;
1107 info
.input_count
= 2;
1108 info
.name
= acpi_method
;
1109 info
.pinput_argument
= acpi_input
;
1110 info
.output_count
= output_count
;
1111 info
.poutput_argument
= &acpi_output
;
1113 return amdgpu_cgs_acpi_eval_object(cgs_device
, &info
);
1116 static const struct cgs_ops amdgpu_cgs_ops
= {
1117 .alloc_gpu_mem
= amdgpu_cgs_alloc_gpu_mem
,
1118 .free_gpu_mem
= amdgpu_cgs_free_gpu_mem
,
1119 .gmap_gpu_mem
= amdgpu_cgs_gmap_gpu_mem
,
1120 .gunmap_gpu_mem
= amdgpu_cgs_gunmap_gpu_mem
,
1121 .kmap_gpu_mem
= amdgpu_cgs_kmap_gpu_mem
,
1122 .kunmap_gpu_mem
= amdgpu_cgs_kunmap_gpu_mem
,
1123 .read_register
= amdgpu_cgs_read_register
,
1124 .write_register
= amdgpu_cgs_write_register
,
1125 .read_ind_register
= amdgpu_cgs_read_ind_register
,
1126 .write_ind_register
= amdgpu_cgs_write_ind_register
,
1127 .get_pci_resource
= amdgpu_cgs_get_pci_resource
,
1128 .atom_get_data_table
= amdgpu_cgs_atom_get_data_table
,
1129 .atom_get_cmd_table_revs
= amdgpu_cgs_atom_get_cmd_table_revs
,
1130 .atom_exec_cmd_table
= amdgpu_cgs_atom_exec_cmd_table
,
1131 .get_firmware_info
= amdgpu_cgs_get_firmware_info
,
1132 .rel_firmware
= amdgpu_cgs_rel_firmware
,
1133 .set_powergating_state
= amdgpu_cgs_set_powergating_state
,
1134 .set_clockgating_state
= amdgpu_cgs_set_clockgating_state
,
1135 .get_active_displays_info
= amdgpu_cgs_get_active_displays_info
,
1136 .notify_dpm_enabled
= amdgpu_cgs_notify_dpm_enabled
,
1137 .call_acpi_method
= amdgpu_cgs_call_acpi_method
,
1138 .query_system_info
= amdgpu_cgs_query_system_info
,
1139 .is_virtualization_enabled
= amdgpu_cgs_is_virtualization_enabled
,
1140 .enter_safe_mode
= amdgpu_cgs_enter_safe_mode
,
1141 .lock_grbm_idx
= amdgpu_cgs_lock_grbm_idx
,
1144 static const struct cgs_os_ops amdgpu_cgs_os_ops
= {
1145 .add_irq_source
= amdgpu_cgs_add_irq_source
,
1146 .irq_get
= amdgpu_cgs_irq_get
,
1147 .irq_put
= amdgpu_cgs_irq_put
1150 struct cgs_device
*amdgpu_cgs_create_device(struct amdgpu_device
*adev
)
1152 struct amdgpu_cgs_device
*cgs_device
=
1153 kmalloc(sizeof(*cgs_device
), GFP_KERNEL
);
1156 DRM_ERROR("Couldn't allocate CGS device structure\n");
1160 cgs_device
->base
.ops
= &amdgpu_cgs_ops
;
1161 cgs_device
->base
.os_ops
= &amdgpu_cgs_os_ops
;
1162 cgs_device
->adev
= adev
;
1164 return (struct cgs_device
*)cgs_device
;
1167 void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device
)