2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
34 #include <linux/vga_switcheroo.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
37 #include "amdgpu_amdkfd.h"
40 * amdgpu_driver_unload_kms - Main unload function for KMS.
42 * @dev: drm dev pointer
44 * This is the main unload function for KMS (all asics).
45 * Returns 0 on success.
47 void amdgpu_driver_unload_kms(struct drm_device
*dev
)
49 struct amdgpu_device
*adev
= dev
->dev_private
;
54 if (adev
->rmmio
== NULL
)
57 if (amdgpu_sriov_vf(adev
))
58 amdgpu_virt_request_full_gpu(adev
, false);
60 if (amdgpu_device_is_px(dev
)) {
61 pm_runtime_get_sync(dev
->dev
);
62 pm_runtime_forbid(dev
->dev
);
65 amdgpu_amdkfd_device_fini(adev
);
67 amdgpu_acpi_fini(adev
);
69 amdgpu_device_fini(adev
);
73 dev
->dev_private
= NULL
;
77 * amdgpu_driver_load_kms - Main load function for KMS.
79 * @dev: drm dev pointer
80 * @flags: device flags
82 * This is the main load function for KMS (all asics).
83 * Returns 0 on success, error on failure.
85 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
87 struct amdgpu_device
*adev
;
90 #ifdef CONFIG_DRM_AMDGPU_SI
91 if (!amdgpu_si_support
) {
92 switch (flags
& AMD_ASIC_MASK
) {
99 "SI support provided by radeon.\n");
101 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
107 #ifdef CONFIG_DRM_AMDGPU_CIK
108 if (!amdgpu_cik_support
) {
109 switch (flags
& AMD_ASIC_MASK
) {
116 "CIK support provided by radeon.\n");
118 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
125 adev
= kzalloc(sizeof(struct amdgpu_device
), GFP_KERNEL
);
129 dev
->dev_private
= (void *)adev
;
131 if ((amdgpu_runtime_pm
!= 0) &&
133 (amdgpu_is_atpx_hybrid() ||
134 amdgpu_has_atpx_dgpu_power_cntl()) &&
135 ((flags
& AMD_IS_APU
) == 0) &&
136 !pci_is_thunderbolt_attached(dev
->pdev
))
139 /* amdgpu_device_init should report only fatal error
140 * like memory allocation failure or iomapping failure,
141 * or memory manager initialization failure, it must
142 * properly initialize the GPU MC controller and permit
145 r
= amdgpu_device_init(adev
, dev
, dev
->pdev
, flags
);
147 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
151 /* Call ACPI methods: require modeset init
152 * but failure is not fatal
155 acpi_status
= amdgpu_acpi_init(adev
);
157 dev_dbg(&dev
->pdev
->dev
,
158 "Error during ACPI methods call\n");
161 amdgpu_amdkfd_device_probe(adev
);
162 amdgpu_amdkfd_device_init(adev
);
164 if (amdgpu_device_is_px(dev
)) {
165 pm_runtime_use_autosuspend(dev
->dev
);
166 pm_runtime_set_autosuspend_delay(dev
->dev
, 5000);
167 pm_runtime_set_active(dev
->dev
);
168 pm_runtime_allow(dev
->dev
);
169 pm_runtime_mark_last_busy(dev
->dev
);
170 pm_runtime_put_autosuspend(dev
->dev
);
173 if (amdgpu_sriov_vf(adev
))
174 amdgpu_virt_release_full_gpu(adev
, true);
178 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
179 if (adev
->rmmio
&& amdgpu_device_is_px(dev
))
180 pm_runtime_put_noidle(dev
->dev
);
181 amdgpu_driver_unload_kms(dev
);
187 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware
*fw_info
,
188 struct drm_amdgpu_query_fw
*query_fw
,
189 struct amdgpu_device
*adev
)
191 switch (query_fw
->fw_type
) {
192 case AMDGPU_INFO_FW_VCE
:
193 fw_info
->ver
= adev
->vce
.fw_version
;
194 fw_info
->feature
= adev
->vce
.fb_version
;
196 case AMDGPU_INFO_FW_UVD
:
197 fw_info
->ver
= adev
->uvd
.fw_version
;
198 fw_info
->feature
= 0;
200 case AMDGPU_INFO_FW_GMC
:
201 fw_info
->ver
= adev
->mc
.fw_version
;
202 fw_info
->feature
= 0;
204 case AMDGPU_INFO_FW_GFX_ME
:
205 fw_info
->ver
= adev
->gfx
.me_fw_version
;
206 fw_info
->feature
= adev
->gfx
.me_feature_version
;
208 case AMDGPU_INFO_FW_GFX_PFP
:
209 fw_info
->ver
= adev
->gfx
.pfp_fw_version
;
210 fw_info
->feature
= adev
->gfx
.pfp_feature_version
;
212 case AMDGPU_INFO_FW_GFX_CE
:
213 fw_info
->ver
= adev
->gfx
.ce_fw_version
;
214 fw_info
->feature
= adev
->gfx
.ce_feature_version
;
216 case AMDGPU_INFO_FW_GFX_RLC
:
217 fw_info
->ver
= adev
->gfx
.rlc_fw_version
;
218 fw_info
->feature
= adev
->gfx
.rlc_feature_version
;
220 case AMDGPU_INFO_FW_GFX_MEC
:
221 if (query_fw
->index
== 0) {
222 fw_info
->ver
= adev
->gfx
.mec_fw_version
;
223 fw_info
->feature
= adev
->gfx
.mec_feature_version
;
224 } else if (query_fw
->index
== 1) {
225 fw_info
->ver
= adev
->gfx
.mec2_fw_version
;
226 fw_info
->feature
= adev
->gfx
.mec2_feature_version
;
230 case AMDGPU_INFO_FW_SMC
:
231 fw_info
->ver
= adev
->pm
.fw_version
;
232 fw_info
->feature
= 0;
234 case AMDGPU_INFO_FW_SDMA
:
235 if (query_fw
->index
>= adev
->sdma
.num_instances
)
237 fw_info
->ver
= adev
->sdma
.instance
[query_fw
->index
].fw_version
;
238 fw_info
->feature
= adev
->sdma
.instance
[query_fw
->index
].feature_version
;
240 case AMDGPU_INFO_FW_SOS
:
241 fw_info
->ver
= adev
->psp
.sos_fw_version
;
242 fw_info
->feature
= adev
->psp
.sos_feature_version
;
244 case AMDGPU_INFO_FW_ASD
:
245 fw_info
->ver
= adev
->psp
.asd_fw_version
;
246 fw_info
->feature
= adev
->psp
.asd_feature_version
;
255 * Userspace get information ioctl
258 * amdgpu_info_ioctl - answer a device specific request.
260 * @adev: amdgpu device pointer
261 * @data: request object
264 * This function is used to pass device specific parameters to the userspace
265 * drivers. Examples include: pci device id, pipeline parms, tiling params,
267 * Returns 0 on success, -EINVAL on failure.
269 static int amdgpu_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
271 struct amdgpu_device
*adev
= dev
->dev_private
;
272 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
273 struct drm_amdgpu_info
*info
= data
;
274 struct amdgpu_mode_info
*minfo
= &adev
->mode_info
;
275 void __user
*out
= (void __user
*)(uintptr_t)info
->return_pointer
;
276 uint32_t size
= info
->return_size
;
277 struct drm_crtc
*crtc
;
281 int ui32_size
= sizeof(ui32
);
283 if (!info
->return_size
|| !info
->return_pointer
)
285 if (amdgpu_kms_vram_lost(adev
, fpriv
))
288 switch (info
->query
) {
289 case AMDGPU_INFO_ACCEL_WORKING
:
290 ui32
= adev
->accel_working
;
291 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
292 case AMDGPU_INFO_CRTC_FROM_ID
:
293 for (i
= 0, found
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
294 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
295 if (crtc
&& crtc
->base
.id
== info
->mode_crtc
.id
) {
296 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
297 ui32
= amdgpu_crtc
->crtc_id
;
303 DRM_DEBUG_KMS("unknown crtc id %d\n", info
->mode_crtc
.id
);
306 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
307 case AMDGPU_INFO_HW_IP_INFO
: {
308 struct drm_amdgpu_info_hw_ip ip
= {};
309 enum amd_ip_block_type type
;
310 uint32_t ring_mask
= 0;
311 uint32_t ib_start_alignment
= 0;
312 uint32_t ib_size_alignment
= 0;
314 if (info
->query_hw_ip
.ip_instance
>= AMDGPU_HW_IP_INSTANCE_MAX_COUNT
)
317 switch (info
->query_hw_ip
.type
) {
318 case AMDGPU_HW_IP_GFX
:
319 type
= AMD_IP_BLOCK_TYPE_GFX
;
320 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
321 ring_mask
|= ((adev
->gfx
.gfx_ring
[i
].ready
? 1 : 0) << i
);
322 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
323 ib_size_alignment
= 8;
325 case AMDGPU_HW_IP_COMPUTE
:
326 type
= AMD_IP_BLOCK_TYPE_GFX
;
327 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
328 ring_mask
|= ((adev
->gfx
.compute_ring
[i
].ready
? 1 : 0) << i
);
329 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
330 ib_size_alignment
= 8;
332 case AMDGPU_HW_IP_DMA
:
333 type
= AMD_IP_BLOCK_TYPE_SDMA
;
334 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
335 ring_mask
|= ((adev
->sdma
.instance
[i
].ring
.ready
? 1 : 0) << i
);
336 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
337 ib_size_alignment
= 1;
339 case AMDGPU_HW_IP_UVD
:
340 type
= AMD_IP_BLOCK_TYPE_UVD
;
341 ring_mask
= adev
->uvd
.ring
.ready
? 1 : 0;
342 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
343 ib_size_alignment
= 16;
345 case AMDGPU_HW_IP_VCE
:
346 type
= AMD_IP_BLOCK_TYPE_VCE
;
347 for (i
= 0; i
< adev
->vce
.num_rings
; i
++)
348 ring_mask
|= ((adev
->vce
.ring
[i
].ready
? 1 : 0) << i
);
349 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
350 ib_size_alignment
= 1;
352 case AMDGPU_HW_IP_UVD_ENC
:
353 type
= AMD_IP_BLOCK_TYPE_UVD
;
354 for (i
= 0; i
< adev
->uvd
.num_enc_rings
; i
++)
355 ring_mask
|= ((adev
->uvd
.ring_enc
[i
].ready
? 1 : 0) << i
);
356 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
357 ib_size_alignment
= 1;
359 case AMDGPU_HW_IP_VCN_DEC
:
360 type
= AMD_IP_BLOCK_TYPE_VCN
;
361 ring_mask
= adev
->vcn
.ring_dec
.ready
? 1 : 0;
362 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
363 ib_size_alignment
= 16;
365 case AMDGPU_HW_IP_VCN_ENC
:
366 type
= AMD_IP_BLOCK_TYPE_VCN
;
367 for (i
= 0; i
< adev
->vcn
.num_enc_rings
; i
++)
368 ring_mask
|= ((adev
->vcn
.ring_enc
[i
].ready
? 1 : 0) << i
);
369 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
370 ib_size_alignment
= 1;
376 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
377 if (adev
->ip_blocks
[i
].version
->type
== type
&&
378 adev
->ip_blocks
[i
].status
.valid
) {
379 ip
.hw_ip_version_major
= adev
->ip_blocks
[i
].version
->major
;
380 ip
.hw_ip_version_minor
= adev
->ip_blocks
[i
].version
->minor
;
381 ip
.capabilities_flags
= 0;
382 ip
.available_rings
= ring_mask
;
383 ip
.ib_start_alignment
= ib_start_alignment
;
384 ip
.ib_size_alignment
= ib_size_alignment
;
388 return copy_to_user(out
, &ip
,
389 min((size_t)size
, sizeof(ip
))) ? -EFAULT
: 0;
391 case AMDGPU_INFO_HW_IP_COUNT
: {
392 enum amd_ip_block_type type
;
395 switch (info
->query_hw_ip
.type
) {
396 case AMDGPU_HW_IP_GFX
:
397 type
= AMD_IP_BLOCK_TYPE_GFX
;
399 case AMDGPU_HW_IP_COMPUTE
:
400 type
= AMD_IP_BLOCK_TYPE_GFX
;
402 case AMDGPU_HW_IP_DMA
:
403 type
= AMD_IP_BLOCK_TYPE_SDMA
;
405 case AMDGPU_HW_IP_UVD
:
406 type
= AMD_IP_BLOCK_TYPE_UVD
;
408 case AMDGPU_HW_IP_VCE
:
409 type
= AMD_IP_BLOCK_TYPE_VCE
;
411 case AMDGPU_HW_IP_UVD_ENC
:
412 type
= AMD_IP_BLOCK_TYPE_UVD
;
414 case AMDGPU_HW_IP_VCN_DEC
:
415 case AMDGPU_HW_IP_VCN_ENC
:
416 type
= AMD_IP_BLOCK_TYPE_VCN
;
422 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
423 if (adev
->ip_blocks
[i
].version
->type
== type
&&
424 adev
->ip_blocks
[i
].status
.valid
&&
425 count
< AMDGPU_HW_IP_INSTANCE_MAX_COUNT
)
428 return copy_to_user(out
, &count
, min(size
, 4u)) ? -EFAULT
: 0;
430 case AMDGPU_INFO_TIMESTAMP
:
431 ui64
= amdgpu_gfx_get_gpu_clock_counter(adev
);
432 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
433 case AMDGPU_INFO_FW_VERSION
: {
434 struct drm_amdgpu_info_firmware fw_info
;
437 /* We only support one instance of each IP block right now. */
438 if (info
->query_fw
.ip_instance
!= 0)
441 ret
= amdgpu_firmware_info(&fw_info
, &info
->query_fw
, adev
);
445 return copy_to_user(out
, &fw_info
,
446 min((size_t)size
, sizeof(fw_info
))) ? -EFAULT
: 0;
448 case AMDGPU_INFO_NUM_BYTES_MOVED
:
449 ui64
= atomic64_read(&adev
->num_bytes_moved
);
450 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
451 case AMDGPU_INFO_NUM_EVICTIONS
:
452 ui64
= atomic64_read(&adev
->num_evictions
);
453 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
454 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
:
455 ui64
= atomic64_read(&adev
->num_vram_cpu_page_faults
);
456 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
457 case AMDGPU_INFO_VRAM_USAGE
:
458 ui64
= amdgpu_vram_mgr_usage(&adev
->mman
.bdev
.man
[TTM_PL_VRAM
]);
459 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
460 case AMDGPU_INFO_VIS_VRAM_USAGE
:
461 ui64
= amdgpu_vram_mgr_vis_usage(&adev
->mman
.bdev
.man
[TTM_PL_VRAM
]);
462 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
463 case AMDGPU_INFO_GTT_USAGE
:
464 ui64
= amdgpu_gtt_mgr_usage(&adev
->mman
.bdev
.man
[TTM_PL_TT
]);
465 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
466 case AMDGPU_INFO_GDS_CONFIG
: {
467 struct drm_amdgpu_info_gds gds_info
;
469 memset(&gds_info
, 0, sizeof(gds_info
));
470 gds_info
.gds_gfx_partition_size
= adev
->gds
.mem
.gfx_partition_size
>> AMDGPU_GDS_SHIFT
;
471 gds_info
.compute_partition_size
= adev
->gds
.mem
.cs_partition_size
>> AMDGPU_GDS_SHIFT
;
472 gds_info
.gds_total_size
= adev
->gds
.mem
.total_size
>> AMDGPU_GDS_SHIFT
;
473 gds_info
.gws_per_gfx_partition
= adev
->gds
.gws
.gfx_partition_size
>> AMDGPU_GWS_SHIFT
;
474 gds_info
.gws_per_compute_partition
= adev
->gds
.gws
.cs_partition_size
>> AMDGPU_GWS_SHIFT
;
475 gds_info
.oa_per_gfx_partition
= adev
->gds
.oa
.gfx_partition_size
>> AMDGPU_OA_SHIFT
;
476 gds_info
.oa_per_compute_partition
= adev
->gds
.oa
.cs_partition_size
>> AMDGPU_OA_SHIFT
;
477 return copy_to_user(out
, &gds_info
,
478 min((size_t)size
, sizeof(gds_info
))) ? -EFAULT
: 0;
480 case AMDGPU_INFO_VRAM_GTT
: {
481 struct drm_amdgpu_info_vram_gtt vram_gtt
;
483 vram_gtt
.vram_size
= adev
->mc
.real_vram_size
;
484 vram_gtt
.vram_size
-= adev
->vram_pin_size
;
485 vram_gtt
.vram_cpu_accessible_size
= adev
->mc
.visible_vram_size
;
486 vram_gtt
.vram_cpu_accessible_size
-= (adev
->vram_pin_size
- adev
->invisible_pin_size
);
487 vram_gtt
.gtt_size
= adev
->mman
.bdev
.man
[TTM_PL_TT
].size
;
488 vram_gtt
.gtt_size
*= PAGE_SIZE
;
489 vram_gtt
.gtt_size
-= adev
->gart_pin_size
;
490 return copy_to_user(out
, &vram_gtt
,
491 min((size_t)size
, sizeof(vram_gtt
))) ? -EFAULT
: 0;
493 case AMDGPU_INFO_MEMORY
: {
494 struct drm_amdgpu_memory_info mem
;
496 memset(&mem
, 0, sizeof(mem
));
497 mem
.vram
.total_heap_size
= adev
->mc
.real_vram_size
;
498 mem
.vram
.usable_heap_size
=
499 adev
->mc
.real_vram_size
- adev
->vram_pin_size
;
500 mem
.vram
.heap_usage
=
501 amdgpu_vram_mgr_usage(&adev
->mman
.bdev
.man
[TTM_PL_VRAM
]);
502 mem
.vram
.max_allocation
= mem
.vram
.usable_heap_size
* 3 / 4;
504 mem
.cpu_accessible_vram
.total_heap_size
=
505 adev
->mc
.visible_vram_size
;
506 mem
.cpu_accessible_vram
.usable_heap_size
=
507 adev
->mc
.visible_vram_size
-
508 (adev
->vram_pin_size
- adev
->invisible_pin_size
);
509 mem
.cpu_accessible_vram
.heap_usage
=
510 amdgpu_vram_mgr_vis_usage(&adev
->mman
.bdev
.man
[TTM_PL_VRAM
]);
511 mem
.cpu_accessible_vram
.max_allocation
=
512 mem
.cpu_accessible_vram
.usable_heap_size
* 3 / 4;
514 mem
.gtt
.total_heap_size
= adev
->mman
.bdev
.man
[TTM_PL_TT
].size
;
515 mem
.gtt
.total_heap_size
*= PAGE_SIZE
;
516 mem
.gtt
.usable_heap_size
= mem
.gtt
.total_heap_size
517 - adev
->gart_pin_size
;
519 amdgpu_gtt_mgr_usage(&adev
->mman
.bdev
.man
[TTM_PL_TT
]);
520 mem
.gtt
.max_allocation
= mem
.gtt
.usable_heap_size
* 3 / 4;
522 return copy_to_user(out
, &mem
,
523 min((size_t)size
, sizeof(mem
)))
526 case AMDGPU_INFO_READ_MMR_REG
: {
527 unsigned n
, alloc_size
;
529 unsigned se_num
= (info
->read_mmr_reg
.instance
>>
530 AMDGPU_INFO_MMR_SE_INDEX_SHIFT
) &
531 AMDGPU_INFO_MMR_SE_INDEX_MASK
;
532 unsigned sh_num
= (info
->read_mmr_reg
.instance
>>
533 AMDGPU_INFO_MMR_SH_INDEX_SHIFT
) &
534 AMDGPU_INFO_MMR_SH_INDEX_MASK
;
536 /* set full masks if the userspace set all bits
537 * in the bitfields */
538 if (se_num
== AMDGPU_INFO_MMR_SE_INDEX_MASK
)
540 if (sh_num
== AMDGPU_INFO_MMR_SH_INDEX_MASK
)
543 regs
= kmalloc_array(info
->read_mmr_reg
.count
, sizeof(*regs
), GFP_KERNEL
);
546 alloc_size
= info
->read_mmr_reg
.count
* sizeof(*regs
);
548 for (i
= 0; i
< info
->read_mmr_reg
.count
; i
++)
549 if (amdgpu_asic_read_register(adev
, se_num
, sh_num
,
550 info
->read_mmr_reg
.dword_offset
+ i
,
552 DRM_DEBUG_KMS("unallowed offset %#x\n",
553 info
->read_mmr_reg
.dword_offset
+ i
);
557 n
= copy_to_user(out
, regs
, min(size
, alloc_size
));
559 return n
? -EFAULT
: 0;
561 case AMDGPU_INFO_DEV_INFO
: {
562 struct drm_amdgpu_info_device dev_info
= {};
564 dev_info
.device_id
= dev
->pdev
->device
;
565 dev_info
.chip_rev
= adev
->rev_id
;
566 dev_info
.external_rev
= adev
->external_rev_id
;
567 dev_info
.pci_rev
= dev
->pdev
->revision
;
568 dev_info
.family
= adev
->family
;
569 dev_info
.num_shader_engines
= adev
->gfx
.config
.max_shader_engines
;
570 dev_info
.num_shader_arrays_per_engine
= adev
->gfx
.config
.max_sh_per_se
;
571 /* return all clocks in KHz */
572 dev_info
.gpu_counter_freq
= amdgpu_asic_get_xclk(adev
) * 10;
573 if (adev
->pm
.dpm_enabled
) {
574 dev_info
.max_engine_clock
= amdgpu_dpm_get_sclk(adev
, false) * 10;
575 dev_info
.max_memory_clock
= amdgpu_dpm_get_mclk(adev
, false) * 10;
577 dev_info
.max_engine_clock
= adev
->clock
.default_sclk
* 10;
578 dev_info
.max_memory_clock
= adev
->clock
.default_mclk
* 10;
580 dev_info
.enabled_rb_pipes_mask
= adev
->gfx
.config
.backend_enable_mask
;
581 dev_info
.num_rb_pipes
= adev
->gfx
.config
.max_backends_per_se
*
582 adev
->gfx
.config
.max_shader_engines
;
583 dev_info
.num_hw_gfx_contexts
= adev
->gfx
.config
.max_hw_contexts
;
585 dev_info
.ids_flags
= 0;
586 if (adev
->flags
& AMD_IS_APU
)
587 dev_info
.ids_flags
|= AMDGPU_IDS_FLAGS_FUSION
;
588 if (amdgpu_sriov_vf(adev
))
589 dev_info
.ids_flags
|= AMDGPU_IDS_FLAGS_PREEMPTION
;
590 dev_info
.virtual_address_offset
= AMDGPU_VA_RESERVED_SIZE
;
591 dev_info
.virtual_address_max
= (uint64_t)adev
->vm_manager
.max_pfn
* AMDGPU_GPU_PAGE_SIZE
;
592 dev_info
.virtual_address_alignment
= max((int)PAGE_SIZE
, AMDGPU_GPU_PAGE_SIZE
);
593 dev_info
.pte_fragment_size
= (1 << adev
->vm_manager
.fragment_size
) * AMDGPU_GPU_PAGE_SIZE
;
594 dev_info
.gart_page_size
= AMDGPU_GPU_PAGE_SIZE
;
595 dev_info
.cu_active_number
= adev
->gfx
.cu_info
.number
;
596 dev_info
.cu_ao_mask
= adev
->gfx
.cu_info
.ao_cu_mask
;
597 dev_info
.ce_ram_size
= adev
->gfx
.ce_ram_size
;
598 memcpy(&dev_info
.cu_ao_bitmap
[0], &adev
->gfx
.cu_info
.ao_cu_bitmap
[0],
599 sizeof(adev
->gfx
.cu_info
.ao_cu_bitmap
));
600 memcpy(&dev_info
.cu_bitmap
[0], &adev
->gfx
.cu_info
.bitmap
[0],
601 sizeof(adev
->gfx
.cu_info
.bitmap
));
602 dev_info
.vram_type
= adev
->mc
.vram_type
;
603 dev_info
.vram_bit_width
= adev
->mc
.vram_width
;
604 dev_info
.vce_harvest_config
= adev
->vce
.harvest_config
;
605 dev_info
.gc_double_offchip_lds_buf
=
606 adev
->gfx
.config
.double_offchip_lds_buf
;
609 dev_info
.prim_buf_gpu_addr
= adev
->gfx
.ngg
.buf
[NGG_PRIM
].gpu_addr
;
610 dev_info
.prim_buf_size
= adev
->gfx
.ngg
.buf
[NGG_PRIM
].size
;
611 dev_info
.pos_buf_gpu_addr
= adev
->gfx
.ngg
.buf
[NGG_POS
].gpu_addr
;
612 dev_info
.pos_buf_size
= adev
->gfx
.ngg
.buf
[NGG_POS
].size
;
613 dev_info
.cntl_sb_buf_gpu_addr
= adev
->gfx
.ngg
.buf
[NGG_CNTL
].gpu_addr
;
614 dev_info
.cntl_sb_buf_size
= adev
->gfx
.ngg
.buf
[NGG_CNTL
].size
;
615 dev_info
.param_buf_gpu_addr
= adev
->gfx
.ngg
.buf
[NGG_PARAM
].gpu_addr
;
616 dev_info
.param_buf_size
= adev
->gfx
.ngg
.buf
[NGG_PARAM
].size
;
618 dev_info
.wave_front_size
= adev
->gfx
.cu_info
.wave_front_size
;
619 dev_info
.num_shader_visible_vgprs
= adev
->gfx
.config
.max_gprs
;
620 dev_info
.num_cu_per_sh
= adev
->gfx
.config
.max_cu_per_sh
;
621 dev_info
.num_tcc_blocks
= adev
->gfx
.config
.max_texture_channel_caches
;
622 dev_info
.gs_vgt_table_depth
= adev
->gfx
.config
.gs_vgt_table_depth
;
623 dev_info
.gs_prim_buffer_depth
= adev
->gfx
.config
.gs_prim_buffer_depth
;
624 dev_info
.max_gs_waves_per_vgt
= adev
->gfx
.config
.max_gs_threads
;
626 return copy_to_user(out
, &dev_info
,
627 min((size_t)size
, sizeof(dev_info
))) ? -EFAULT
: 0;
629 case AMDGPU_INFO_VCE_CLOCK_TABLE
: {
631 struct drm_amdgpu_info_vce_clock_table vce_clk_table
= {};
632 struct amd_vce_state
*vce_state
;
634 for (i
= 0; i
< AMDGPU_VCE_CLOCK_TABLE_ENTRIES
; i
++) {
635 vce_state
= amdgpu_dpm_get_vce_clock_state(adev
, i
);
637 vce_clk_table
.entries
[i
].sclk
= vce_state
->sclk
;
638 vce_clk_table
.entries
[i
].mclk
= vce_state
->mclk
;
639 vce_clk_table
.entries
[i
].eclk
= vce_state
->evclk
;
640 vce_clk_table
.num_valid_entries
++;
644 return copy_to_user(out
, &vce_clk_table
,
645 min((size_t)size
, sizeof(vce_clk_table
))) ? -EFAULT
: 0;
647 case AMDGPU_INFO_VBIOS
: {
648 uint32_t bios_size
= adev
->bios_size
;
650 switch (info
->vbios_info
.type
) {
651 case AMDGPU_INFO_VBIOS_SIZE
:
652 return copy_to_user(out
, &bios_size
,
653 min((size_t)size
, sizeof(bios_size
)))
655 case AMDGPU_INFO_VBIOS_IMAGE
: {
657 uint32_t bios_offset
= info
->vbios_info
.offset
;
659 if (bios_offset
>= bios_size
)
662 bios
= adev
->bios
+ bios_offset
;
663 return copy_to_user(out
, bios
,
664 min((size_t)size
, (size_t)(bios_size
- bios_offset
)))
668 DRM_DEBUG_KMS("Invalid request %d\n",
669 info
->vbios_info
.type
);
673 case AMDGPU_INFO_NUM_HANDLES
: {
674 struct drm_amdgpu_info_num_handles handle
;
676 switch (info
->query_hw_ip
.type
) {
677 case AMDGPU_HW_IP_UVD
:
678 /* Starting Polaris, we support unlimited UVD handles */
679 if (adev
->asic_type
< CHIP_POLARIS10
) {
680 handle
.uvd_max_handles
= adev
->uvd
.max_handles
;
681 handle
.uvd_used_handles
= amdgpu_uvd_used_handles(adev
);
683 return copy_to_user(out
, &handle
,
684 min((size_t)size
, sizeof(handle
))) ? -EFAULT
: 0;
694 case AMDGPU_INFO_SENSOR
: {
695 struct pp_gpu_power query
= {0};
696 int query_size
= sizeof(query
);
701 switch (info
->sensor_info
.type
) {
702 case AMDGPU_INFO_SENSOR_GFX_SCLK
:
703 /* get sclk in Mhz */
704 if (amdgpu_dpm_read_sensor(adev
,
705 AMDGPU_PP_SENSOR_GFX_SCLK
,
706 (void *)&ui32
, &ui32_size
)) {
711 case AMDGPU_INFO_SENSOR_GFX_MCLK
:
712 /* get mclk in Mhz */
713 if (amdgpu_dpm_read_sensor(adev
,
714 AMDGPU_PP_SENSOR_GFX_MCLK
,
715 (void *)&ui32
, &ui32_size
)) {
720 case AMDGPU_INFO_SENSOR_GPU_TEMP
:
721 /* get temperature in millidegrees C */
722 if (amdgpu_dpm_read_sensor(adev
,
723 AMDGPU_PP_SENSOR_GPU_TEMP
,
724 (void *)&ui32
, &ui32_size
)) {
728 case AMDGPU_INFO_SENSOR_GPU_LOAD
:
730 if (amdgpu_dpm_read_sensor(adev
,
731 AMDGPU_PP_SENSOR_GPU_LOAD
,
732 (void *)&ui32
, &ui32_size
)) {
736 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER
:
737 /* get average GPU power */
738 if (amdgpu_dpm_read_sensor(adev
,
739 AMDGPU_PP_SENSOR_GPU_POWER
,
740 (void *)&query
, &query_size
)) {
743 ui32
= query
.average_gpu_power
>> 8;
745 case AMDGPU_INFO_SENSOR_VDDNB
:
746 /* get VDDNB in millivolts */
747 if (amdgpu_dpm_read_sensor(adev
,
748 AMDGPU_PP_SENSOR_VDDNB
,
749 (void *)&ui32
, &ui32_size
)) {
753 case AMDGPU_INFO_SENSOR_VDDGFX
:
754 /* get VDDGFX in millivolts */
755 if (amdgpu_dpm_read_sensor(adev
,
756 AMDGPU_PP_SENSOR_VDDGFX
,
757 (void *)&ui32
, &ui32_size
)) {
762 DRM_DEBUG_KMS("Invalid request %d\n",
763 info
->sensor_info
.type
);
766 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
769 DRM_DEBUG_KMS("Invalid request %d\n", info
->query
);
777 * Outdated mess for old drm with Xorg being in charge (void function now).
780 * amdgpu_driver_lastclose_kms - drm callback for last close
782 * @dev: drm dev pointer
784 * Switch vga_switcheroo state after last close (all asics).
786 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
)
788 struct amdgpu_device
*adev
= dev
->dev_private
;
790 amdgpu_fbdev_restore_mode(adev
);
791 vga_switcheroo_process_delayed_switch();
794 bool amdgpu_kms_vram_lost(struct amdgpu_device
*adev
,
795 struct amdgpu_fpriv
*fpriv
)
797 return fpriv
->vram_lost_counter
!= atomic_read(&adev
->vram_lost_counter
);
801 * amdgpu_driver_open_kms - drm callback for open
803 * @dev: drm dev pointer
804 * @file_priv: drm file
806 * On device open, init vm on cayman+ (all asics).
807 * Returns 0 on success, error on failure.
809 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
811 struct amdgpu_device
*adev
= dev
->dev_private
;
812 struct amdgpu_fpriv
*fpriv
;
815 file_priv
->driver_priv
= NULL
;
817 r
= pm_runtime_get_sync(dev
->dev
);
821 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
822 if (unlikely(!fpriv
)) {
827 r
= amdgpu_vm_init(adev
, &fpriv
->vm
,
828 AMDGPU_VM_CONTEXT_GFX
);
834 fpriv
->prt_va
= amdgpu_vm_bo_add(adev
, &fpriv
->vm
, NULL
);
835 if (!fpriv
->prt_va
) {
837 amdgpu_vm_fini(adev
, &fpriv
->vm
);
842 if (amdgpu_sriov_vf(adev
)) {
843 r
= amdgpu_map_static_csa(adev
, &fpriv
->vm
, &fpriv
->csa_va
);
848 mutex_init(&fpriv
->bo_list_lock
);
849 idr_init(&fpriv
->bo_list_handles
);
851 amdgpu_ctx_mgr_init(&fpriv
->ctx_mgr
);
853 fpriv
->vram_lost_counter
= atomic_read(&adev
->vram_lost_counter
);
854 file_priv
->driver_priv
= fpriv
;
857 pm_runtime_mark_last_busy(dev
->dev
);
858 pm_runtime_put_autosuspend(dev
->dev
);
864 * amdgpu_driver_postclose_kms - drm callback for post close
866 * @dev: drm dev pointer
867 * @file_priv: drm file
869 * On device post close, tear down vm on cayman+ (all asics).
871 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
872 struct drm_file
*file_priv
)
874 struct amdgpu_device
*adev
= dev
->dev_private
;
875 struct amdgpu_fpriv
*fpriv
= file_priv
->driver_priv
;
876 struct amdgpu_bo_list
*list
;
882 pm_runtime_get_sync(dev
->dev
);
884 amdgpu_ctx_mgr_fini(&fpriv
->ctx_mgr
);
886 if (adev
->asic_type
!= CHIP_RAVEN
) {
887 amdgpu_uvd_free_handles(adev
, file_priv
);
888 amdgpu_vce_free_handles(adev
, file_priv
);
891 amdgpu_vm_bo_rmv(adev
, fpriv
->prt_va
);
893 if (amdgpu_sriov_vf(adev
)) {
894 /* TODO: how to handle reserve failure */
895 BUG_ON(amdgpu_bo_reserve(adev
->virt
.csa_obj
, true));
896 amdgpu_vm_bo_rmv(adev
, fpriv
->csa_va
);
897 fpriv
->csa_va
= NULL
;
898 amdgpu_bo_unreserve(adev
->virt
.csa_obj
);
901 amdgpu_vm_fini(adev
, &fpriv
->vm
);
903 idr_for_each_entry(&fpriv
->bo_list_handles
, list
, handle
)
904 amdgpu_bo_list_free(list
);
906 idr_destroy(&fpriv
->bo_list_handles
);
907 mutex_destroy(&fpriv
->bo_list_lock
);
910 file_priv
->driver_priv
= NULL
;
912 pm_runtime_mark_last_busy(dev
->dev
);
913 pm_runtime_put_autosuspend(dev
->dev
);
917 * VBlank related functions.
920 * amdgpu_get_vblank_counter_kms - get frame count
922 * @dev: drm dev pointer
923 * @pipe: crtc to get the frame count from
925 * Gets the frame count on the requested crtc (all asics).
926 * Returns frame count on success, -EINVAL on failure.
928 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
)
930 struct amdgpu_device
*adev
= dev
->dev_private
;
931 int vpos
, hpos
, stat
;
934 if (pipe
>= adev
->mode_info
.num_crtc
) {
935 DRM_ERROR("Invalid crtc %u\n", pipe
);
939 /* The hw increments its frame counter at start of vsync, not at start
940 * of vblank, as is required by DRM core vblank counter handling.
941 * Cook the hw count here to make it appear to the caller as if it
942 * incremented at start of vblank. We measure distance to start of
943 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
944 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
945 * result by 1 to give the proper appearance to caller.
947 if (adev
->mode_info
.crtcs
[pipe
]) {
948 /* Repeat readout if needed to provide stable result if
949 * we cross start of vsync during the queries.
952 count
= amdgpu_display_vblank_get_counter(adev
, pipe
);
953 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
954 * distance to start of vblank, instead of regular
955 * vertical scanout pos.
957 stat
= amdgpu_get_crtc_scanoutpos(
958 dev
, pipe
, GET_DISTANCE_TO_VBLANKSTART
,
959 &vpos
, &hpos
, NULL
, NULL
,
960 &adev
->mode_info
.crtcs
[pipe
]->base
.hwmode
);
961 } while (count
!= amdgpu_display_vblank_get_counter(adev
, pipe
));
963 if (((stat
& (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
)) !=
964 (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
))) {
965 DRM_DEBUG_VBL("Query failed! stat %d\n", stat
);
967 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
970 /* Bump counter if we are at >= leading edge of vblank,
971 * but before vsync where vpos would turn negative and
972 * the hw counter really increments.
978 /* Fallback to use value as is. */
979 count
= amdgpu_display_vblank_get_counter(adev
, pipe
);
980 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
987 * amdgpu_enable_vblank_kms - enable vblank interrupt
989 * @dev: drm dev pointer
990 * @pipe: crtc to enable vblank interrupt for
992 * Enable the interrupt on the requested crtc (all asics).
993 * Returns 0 on success, -EINVAL on failure.
995 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
)
997 struct amdgpu_device
*adev
= dev
->dev_private
;
998 int idx
= amdgpu_crtc_idx_to_irq_type(adev
, pipe
);
1000 return amdgpu_irq_get(adev
, &adev
->crtc_irq
, idx
);
1004 * amdgpu_disable_vblank_kms - disable vblank interrupt
1006 * @dev: drm dev pointer
1007 * @pipe: crtc to disable vblank interrupt for
1009 * Disable the interrupt on the requested crtc (all asics).
1011 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
)
1013 struct amdgpu_device
*adev
= dev
->dev_private
;
1014 int idx
= amdgpu_crtc_idx_to_irq_type(adev
, pipe
);
1016 amdgpu_irq_put(adev
, &adev
->crtc_irq
, idx
);
1019 const struct drm_ioctl_desc amdgpu_ioctls_kms
[] = {
1020 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE
, amdgpu_gem_create_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1021 DRM_IOCTL_DEF_DRV(AMDGPU_CTX
, amdgpu_ctx_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1022 DRM_IOCTL_DEF_DRV(AMDGPU_VM
, amdgpu_vm_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1023 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST
, amdgpu_bo_list_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1025 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP
, amdgpu_gem_mmap_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1026 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE
, amdgpu_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1027 DRM_IOCTL_DEF_DRV(AMDGPU_CS
, amdgpu_cs_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1028 DRM_IOCTL_DEF_DRV(AMDGPU_INFO
, amdgpu_info_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1029 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS
, amdgpu_cs_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1030 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES
, amdgpu_cs_wait_fences_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1031 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA
, amdgpu_gem_metadata_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1032 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA
, amdgpu_gem_va_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1033 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP
, amdgpu_gem_op_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1034 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR
, amdgpu_gem_userptr_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1036 const int amdgpu_max_kms_ioctl
= ARRAY_SIZE(amdgpu_ioctls_kms
);
1041 #if defined(CONFIG_DEBUG_FS)
1043 static int amdgpu_debugfs_firmware_info(struct seq_file
*m
, void *data
)
1045 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1046 struct drm_device
*dev
= node
->minor
->dev
;
1047 struct amdgpu_device
*adev
= dev
->dev_private
;
1048 struct drm_amdgpu_info_firmware fw_info
;
1049 struct drm_amdgpu_query_fw query_fw
;
1053 query_fw
.fw_type
= AMDGPU_INFO_FW_VCE
;
1054 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1057 seq_printf(m
, "VCE feature version: %u, firmware version: 0x%08x\n",
1058 fw_info
.feature
, fw_info
.ver
);
1061 query_fw
.fw_type
= AMDGPU_INFO_FW_UVD
;
1062 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1065 seq_printf(m
, "UVD feature version: %u, firmware version: 0x%08x\n",
1066 fw_info
.feature
, fw_info
.ver
);
1069 query_fw
.fw_type
= AMDGPU_INFO_FW_GMC
;
1070 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1073 seq_printf(m
, "MC feature version: %u, firmware version: 0x%08x\n",
1074 fw_info
.feature
, fw_info
.ver
);
1077 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_ME
;
1078 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1081 seq_printf(m
, "ME feature version: %u, firmware version: 0x%08x\n",
1082 fw_info
.feature
, fw_info
.ver
);
1085 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_PFP
;
1086 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1089 seq_printf(m
, "PFP feature version: %u, firmware version: 0x%08x\n",
1090 fw_info
.feature
, fw_info
.ver
);
1093 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_CE
;
1094 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1097 seq_printf(m
, "CE feature version: %u, firmware version: 0x%08x\n",
1098 fw_info
.feature
, fw_info
.ver
);
1101 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_RLC
;
1102 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1105 seq_printf(m
, "RLC feature version: %u, firmware version: 0x%08x\n",
1106 fw_info
.feature
, fw_info
.ver
);
1109 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_MEC
;
1111 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1114 seq_printf(m
, "MEC feature version: %u, firmware version: 0x%08x\n",
1115 fw_info
.feature
, fw_info
.ver
);
1118 if (adev
->asic_type
== CHIP_KAVERI
||
1119 (adev
->asic_type
> CHIP_TOPAZ
&& adev
->asic_type
!= CHIP_STONEY
)) {
1121 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1124 seq_printf(m
, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1125 fw_info
.feature
, fw_info
.ver
);
1129 query_fw
.fw_type
= AMDGPU_INFO_FW_SOS
;
1130 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1133 seq_printf(m
, "SOS feature version: %u, firmware version: 0x%08x\n",
1134 fw_info
.feature
, fw_info
.ver
);
1138 query_fw
.fw_type
= AMDGPU_INFO_FW_ASD
;
1139 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1142 seq_printf(m
, "ASD feature version: %u, firmware version: 0x%08x\n",
1143 fw_info
.feature
, fw_info
.ver
);
1146 query_fw
.fw_type
= AMDGPU_INFO_FW_SMC
;
1147 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1150 seq_printf(m
, "SMC feature version: %u, firmware version: 0x%08x\n",
1151 fw_info
.feature
, fw_info
.ver
);
1154 query_fw
.fw_type
= AMDGPU_INFO_FW_SDMA
;
1155 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1157 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
1160 seq_printf(m
, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1161 i
, fw_info
.feature
, fw_info
.ver
);
1167 static const struct drm_info_list amdgpu_firmware_info_list
[] = {
1168 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info
, 0, NULL
},
1172 int amdgpu_debugfs_firmware_init(struct amdgpu_device
*adev
)
1174 #if defined(CONFIG_DEBUG_FS)
1175 return amdgpu_debugfs_add_files(adev
, amdgpu_firmware_info_list
,
1176 ARRAY_SIZE(amdgpu_firmware_info_list
));