drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

   1 /*
   2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3  *                VA Linux Systems Inc., Fremont, California.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Original Authors:
  25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26  *
  27  * Kernel port Author: Dave Airlie
  28  */
  29
  30 #ifndef AMDGPU_MODE_H
  31 #define AMDGPU_MODE_H
  32
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_encoder.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fixed.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_fb_helper.h>
  40 #include <drm/drm_plane_helper.h>
  41 #include <drm/drm_fb_helper.h>
  42 #include <linux/i2c.h>
  43 #include <linux/i2c-algo-bit.h>
  44 #include <linux/hrtimer.h>
  45 #include "amdgpu_irq.h"
  46
  47 #include <drm/drm_dp_mst_helper.h>
  48 #include "modules/inc/mod_freesync.h"
  49
  50 struct amdgpu_bo;
  51 struct amdgpu_device;
  52 struct amdgpu_encoder;
  53 struct amdgpu_router;
  54 struct amdgpu_hpd;
  55
  56 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
  57 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
  58 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
  59 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
  60
  61 #define AMDGPU_MAX_HPD_PINS 6
  62 #define AMDGPU_MAX_CRTCS 6
  63 #define AMDGPU_MAX_AFMT_BLOCKS 9
  64
  65 enum amdgpu_rmx_type {
  66         RMX_OFF,
  67         RMX_FULL,
  68         RMX_CENTER,
  69         RMX_ASPECT
  70 };
  71
  72 enum amdgpu_underscan_type {
  73         UNDERSCAN_OFF,
  74         UNDERSCAN_ON,
  75         UNDERSCAN_AUTO,
  76 };
  77
  78 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
  79 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
  80
  81 enum amdgpu_hpd_id {
  82         AMDGPU_HPD_1 = 0,
  83         AMDGPU_HPD_2,
  84         AMDGPU_HPD_3,
  85         AMDGPU_HPD_4,
  86         AMDGPU_HPD_5,
  87         AMDGPU_HPD_6,
  88         AMDGPU_HPD_LAST,
  89         AMDGPU_HPD_NONE = 0xff,
  90 };
  91
  92 enum amdgpu_crtc_irq {
  93         AMDGPU_CRTC_IRQ_VBLANK1 = 0,
  94         AMDGPU_CRTC_IRQ_VBLANK2,
  95         AMDGPU_CRTC_IRQ_VBLANK3,
  96         AMDGPU_CRTC_IRQ_VBLANK4,
  97         AMDGPU_CRTC_IRQ_VBLANK5,
  98         AMDGPU_CRTC_IRQ_VBLANK6,
  99         AMDGPU_CRTC_IRQ_VLINE1,
 100         AMDGPU_CRTC_IRQ_VLINE2,
 101         AMDGPU_CRTC_IRQ_VLINE3,
 102         AMDGPU_CRTC_IRQ_VLINE4,
 103         AMDGPU_CRTC_IRQ_VLINE5,
 104         AMDGPU_CRTC_IRQ_VLINE6,
 105         AMDGPU_CRTC_IRQ_LAST,
 106         AMDGPU_CRTC_IRQ_NONE = 0xff
 107 };
 108
 109 enum amdgpu_pageflip_irq {
 110         AMDGPU_PAGEFLIP_IRQ_D1 = 0,
 111         AMDGPU_PAGEFLIP_IRQ_D2,
 112         AMDGPU_PAGEFLIP_IRQ_D3,
 113         AMDGPU_PAGEFLIP_IRQ_D4,
 114         AMDGPU_PAGEFLIP_IRQ_D5,
 115         AMDGPU_PAGEFLIP_IRQ_D6,
 116         AMDGPU_PAGEFLIP_IRQ_LAST,
 117         AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
 118 };
 119
 120 enum amdgpu_flip_status {
 121         AMDGPU_FLIP_NONE,
 122         AMDGPU_FLIP_PENDING,
 123         AMDGPU_FLIP_SUBMITTED
 124 };
 125
 126 #define AMDGPU_MAX_I2C_BUS 16
 127
 128 /* amdgpu gpio-based i2c
 129  * 1. "mask" reg and bits
 130  *    grabs the gpio pins for software use
 131  *    0=not held  1=held
 132  * 2. "a" reg and bits
 133  *    output pin value
 134  *    0=low 1=high
 135  * 3. "en" reg and bits
 136  *    sets the pin direction
 137  *    0=input 1=output
 138  * 4. "y" reg and bits
 139  *    input pin value
 140  *    0=low 1=high
 141  */
 142 struct amdgpu_i2c_bus_rec {
 143         bool valid;
 144         /* id used by atom */
 145         uint8_t i2c_id;
 146         /* id used by atom */
 147         enum amdgpu_hpd_id hpd;
 148         /* can be used with hw i2c engine */
 149         bool hw_capable;
 150         /* uses multi-media i2c engine */
 151         bool mm_i2c;
 152         /* regs and bits */
 153         uint32_t mask_clk_reg;
 154         uint32_t mask_data_reg;
 155         uint32_t a_clk_reg;
 156         uint32_t a_data_reg;
 157         uint32_t en_clk_reg;
 158         uint32_t en_data_reg;
 159         uint32_t y_clk_reg;
 160         uint32_t y_data_reg;
 161         uint32_t mask_clk_mask;
 162         uint32_t mask_data_mask;
 163         uint32_t a_clk_mask;
 164         uint32_t a_data_mask;
 165         uint32_t en_clk_mask;
 166         uint32_t en_data_mask;
 167         uint32_t y_clk_mask;
 168         uint32_t y_data_mask;
 169 };
 170
 171 #define AMDGPU_MAX_BIOS_CONNECTOR 16
 172
 173 /* pll flags */
 174 #define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
 175 #define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
 176 #define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
 177 #define AMDGPU_PLL_LEGACY               (1 << 3)
 178 #define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 179 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 180 #define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 181 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 182 #define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 183 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 184 #define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
 185 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 186 #define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
 187 #define AMDGPU_PLL_IS_LCD               (1 << 13)
 188 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 189
 190 struct amdgpu_pll {
 191         /* reference frequency */
 192         uint32_t reference_freq;
 193
 194         /* fixed dividers */
 195         uint32_t reference_div;
 196         uint32_t post_div;
 197
 198         /* pll in/out limits */
 199         uint32_t pll_in_min;
 200         uint32_t pll_in_max;
 201         uint32_t pll_out_min;
 202         uint32_t pll_out_max;
 203         uint32_t lcd_pll_out_min;
 204         uint32_t lcd_pll_out_max;
 205         uint32_t best_vco;
 206
 207         /* divider limits */
 208         uint32_t min_ref_div;
 209         uint32_t max_ref_div;
 210         uint32_t min_post_div;
 211         uint32_t max_post_div;
 212         uint32_t min_feedback_div;
 213         uint32_t max_feedback_div;
 214         uint32_t min_frac_feedback_div;
 215         uint32_t max_frac_feedback_div;
 216
 217         /* flags for the current clock */
 218         uint32_t flags;
 219
 220         /* pll id */
 221         uint32_t id;
 222 };
 223
 224 struct amdgpu_i2c_chan {
 225         struct i2c_adapter adapter;
 226         struct drm_device *dev;
 227         struct i2c_algo_bit_data bit;
 228         struct amdgpu_i2c_bus_rec rec;
 229         struct drm_dp_aux aux;
 230         bool has_aux;
 231         struct mutex mutex;
 232 };
 233
 234 struct amdgpu_fbdev;
 235
 236 struct amdgpu_afmt {
 237         bool enabled;
 238         int offset;
 239         bool last_buffer_filled_status;
 240         int id;
 241         struct amdgpu_audio_pin *pin;
 242 };
 243
 244 /*
 245  * Audio
 246  */
 247 struct amdgpu_audio_pin {
 248         int                     channels;
 249         int                     rate;
 250         int                     bits_per_sample;
 251         u8                      status_bits;
 252         u8                      category_code;
 253         u32                     offset;
 254         bool                    connected;
 255         u32                     id;
 256 };
 257
 258 struct amdgpu_audio {
 259         bool enabled;
 260         struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
 261         int num_pins;
 262 };
 263
 264 struct amdgpu_display_funcs {
 265         /* display watermarks */
 266         void (*bandwidth_update)(struct amdgpu_device *adev);
 267         /* get frame count */
 268         u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
 269         /* wait for vblank */
 270         void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
 271         /* set backlight level */
 272         void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
 273                                     u8 level);
 274         /* get backlight level */
 275         u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
 276         /* hotplug detect */
 277         bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
 278         void (*hpd_set_polarity)(struct amdgpu_device *adev,
 279                                  enum amdgpu_hpd_id hpd);
 280         u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
 281         /* pageflipping */
 282         void (*page_flip)(struct amdgpu_device *adev,
 283                           int crtc_id, u64 crtc_base, bool async);
 284         int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
 285                                         u32 *vbl, u32 *position);
 286         /* display topology setup */
 287         void (*add_encoder)(struct amdgpu_device *adev,
 288                             uint32_t encoder_enum,
 289                             uint32_t supported_device,
 290                             u16 caps);
 291         void (*add_connector)(struct amdgpu_device *adev,
 292                               uint32_t connector_id,
 293                               uint32_t supported_device,
 294                               int connector_type,
 295                               struct amdgpu_i2c_bus_rec *i2c_bus,
 296                               uint16_t connector_object_id,
 297                               struct amdgpu_hpd *hpd,
 298                               struct amdgpu_router *router);
 299         /* it is used to enter or exit into free sync mode */
 300         int (*notify_freesync)(struct drm_device *dev, void *data,
 301                                struct drm_file *filp);
 302         /* it is used to allow enablement of freesync mode */
 303         int (*set_freesync_property)(struct drm_connector *connector,
 304                                      struct drm_property *property,
 305                                      uint64_t val);
 306
 307
 308 };
 309
 310 struct amdgpu_framebuffer {
 311         struct drm_framebuffer base;
 312         struct drm_gem_object *obj;
 313 };
 314
 315 struct amdgpu_fbdev {
 316         struct drm_fb_helper helper;
 317         struct amdgpu_framebuffer rfb;
 318         struct list_head fbdev_list;
 319         struct amdgpu_device *adev;
 320 };
 321
 322 struct amdgpu_mode_info {
 323         struct atom_context *atom_context;
 324         struct card_info *atom_card_info;
 325         bool mode_config_initialized;
 326         struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
 327         struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
 328         /* DVI-I properties */
 329         struct drm_property *coherent_mode_property;
 330         /* DAC enable load detect */
 331         struct drm_property *load_detect_property;
 332         /* underscan */
 333         struct drm_property *underscan_property;
 334         struct drm_property *underscan_hborder_property;
 335         struct drm_property *underscan_vborder_property;
 336         /* audio */
 337         struct drm_property *audio_property;
 338         /* FMT dithering */
 339         struct drm_property *dither_property;
 340         /* hardcoded DFP edid from BIOS */
 341         struct edid *bios_hardcoded_edid;
 342         int bios_hardcoded_edid_size;
 343
 344         /* pointer to fbdev info structure */
 345         struct amdgpu_fbdev *rfbdev;
 346         /* firmware flags */
 347         u16 firmware_flags;
 348         /* pointer to backlight encoder */
 349         struct amdgpu_encoder *bl_encoder;
 350         struct amdgpu_audio     audio; /* audio stuff */
 351         int                     num_crtc; /* number of crtcs */
 352         int                     num_hpd; /* number of hpd pins */
 353         int                     num_dig; /* number of dig blocks */
 354         int                     disp_priority;
 355         const struct amdgpu_display_funcs *funcs;
 356 };
 357
 358 #define AMDGPU_MAX_BL_LEVEL 0xFF
 359
 360 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 361
 362 struct amdgpu_backlight_privdata {
 363         struct amdgpu_encoder *encoder;
 364         uint8_t negative;
 365 };
 366
 367 #endif
 368
 369 struct amdgpu_atom_ss {
 370         uint16_t percentage;
 371         uint16_t percentage_divider;
 372         uint8_t type;
 373         uint16_t step;
 374         uint8_t delay;
 375         uint8_t range;
 376         uint8_t refdiv;
 377         /* asic_ss */
 378         uint16_t rate;
 379         uint16_t amount;
 380 };
 381
 382 struct amdgpu_crtc {
 383         struct drm_crtc base;
 384         int crtc_id;
 385         bool enabled;
 386         bool can_tile;
 387         uint32_t crtc_offset;
 388         struct drm_gem_object *cursor_bo;
 389         uint64_t cursor_addr;
 390         int cursor_x;
 391         int cursor_y;
 392         int cursor_hot_x;
 393         int cursor_hot_y;
 394         int cursor_width;
 395         int cursor_height;
 396         int max_cursor_width;
 397         int max_cursor_height;
 398         enum amdgpu_rmx_type rmx_type;
 399         u8 h_border;
 400         u8 v_border;
 401         fixed20_12 vsc;
 402         fixed20_12 hsc;
 403         struct drm_display_mode native_mode;
 404         u32 pll_id;
 405         /* page flipping */
 406         struct amdgpu_flip_work *pflip_works;
 407         enum amdgpu_flip_status pflip_status;
 408         int deferred_flip_completion;
 409         /* pll sharing */
 410         struct amdgpu_atom_ss ss;
 411         bool ss_enabled;
 412         u32 adjusted_clock;
 413         int bpc;
 414         u32 pll_reference_div;
 415         u32 pll_post_div;
 416         u32 pll_flags;
 417         struct drm_encoder *encoder;
 418         struct drm_connector *connector;
 419         /* for dpm */
 420         u32 line_time;
 421         u32 wm_low;
 422         u32 wm_high;
 423         u32 lb_vblank_lead_lines;
 424         struct drm_display_mode hw_mode;
 425         /* for virtual dce */
 426         struct hrtimer vblank_timer;
 427         enum amdgpu_interrupt_state vsync_timer_enabled;
 428
 429         int otg_inst;
 430         uint32_t flip_flags;
 431         /* After Set Mode target will be non-NULL */
 432         struct dc_target *target;
 433 };
 434
 435 struct amdgpu_encoder_atom_dig {
 436         bool linkb;
 437         /* atom dig */
 438         bool coherent_mode;
 439         int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 440         /* atom lvds/edp */
 441         uint32_t lcd_misc;
 442         uint16_t panel_pwr_delay;
 443         uint32_t lcd_ss_id;
 444         /* panel mode */
 445         struct drm_display_mode native_mode;
 446         struct backlight_device *bl_dev;
 447         int dpms_mode;
 448         uint8_t backlight_level;
 449         int panel_mode;
 450         struct amdgpu_afmt *afmt;
 451 };
 452
 453 struct amdgpu_encoder {
 454         struct drm_encoder base;
 455         uint32_t encoder_enum;
 456         uint32_t encoder_id;
 457         uint32_t devices;
 458         uint32_t active_device;
 459         uint32_t flags;
 460         uint32_t pixel_clock;
 461         enum amdgpu_rmx_type rmx_type;
 462         enum amdgpu_underscan_type underscan_type;
 463         uint32_t underscan_hborder;
 464         uint32_t underscan_vborder;
 465         struct drm_display_mode native_mode;
 466         void *enc_priv;
 467         int audio_polling_active;
 468         bool is_ext_encoder;
 469         u16 caps;
 470 };
 471
 472 struct amdgpu_connector_atom_dig {
 473         /* displayport */
 474         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 475         u8 dp_sink_type;
 476         int dp_clock;
 477         int dp_lane_count;
 478         bool edp_on;
 479 };
 480
 481 struct amdgpu_gpio_rec {
 482         bool valid;
 483         u8 id;
 484         u32 reg;
 485         u32 mask;
 486         u32 shift;
 487 };
 488
 489 struct amdgpu_hpd {
 490         enum amdgpu_hpd_id hpd;
 491         u8 plugged_state;
 492         struct amdgpu_gpio_rec gpio;
 493 };
 494
 495 struct amdgpu_router {
 496         u32 router_id;
 497         struct amdgpu_i2c_bus_rec i2c_info;
 498         u8 i2c_addr;
 499         /* i2c mux */
 500         bool ddc_valid;
 501         u8 ddc_mux_type;
 502         u8 ddc_mux_control_pin;
 503         u8 ddc_mux_state;
 504         /* clock/data mux */
 505         bool cd_valid;
 506         u8 cd_mux_type;
 507         u8 cd_mux_control_pin;
 508         u8 cd_mux_state;
 509 };
 510
 511 enum amdgpu_connector_audio {
 512         AMDGPU_AUDIO_DISABLE = 0,
 513         AMDGPU_AUDIO_ENABLE = 1,
 514         AMDGPU_AUDIO_AUTO = 2
 515 };
 516
 517 enum amdgpu_connector_dither {
 518         AMDGPU_FMT_DITHER_DISABLE = 0,
 519         AMDGPU_FMT_DITHER_ENABLE = 1,
 520 };
 521
 522 struct amdgpu_dm_dp_aux {
 523         struct drm_dp_aux aux;
 524         uint32_t link_index;
 525 };
 526
 527 struct amdgpu_i2c_adapter {
 528         struct i2c_adapter base;
 529         struct amdgpu_display_manager *dm;
 530         uint32_t link_index;
 531 };
 532
 533 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
 534
 535 struct amdgpu_connector {
 536         struct drm_connector base;
 537         uint32_t connector_id;
 538         uint32_t devices;
 539         struct amdgpu_i2c_chan *ddc_bus;
 540         /* some systems have an hdmi and vga port with a shared ddc line */
 541         bool shared_ddc;
 542         bool use_digital;
 543         /* we need to mind the EDID between detect
 544            and get modes due to analog/digital/tvencoder */
 545         struct edid *edid;
 546         /* number of modes generated from EDID at 'dc_sink' */
 547         int num_modes;
 548         /* The 'old' sink - before an HPD.
 549          * The 'current' sink is in dc_link->sink. */
 550         const struct dc_sink *dc_sink;
 551         const struct dc_link *dc_link;
 552         const struct dc_sink *dc_em_sink;
 553         const struct dc_target *target;
 554         void *con_priv;
 555         bool dac_load_detect;
 556         bool detected_by_load; /* if the connection status was determined by load */
 557         uint16_t connector_object_id;
 558         struct amdgpu_hpd hpd;
 559         struct amdgpu_router router;
 560         struct amdgpu_i2c_chan *router_bus;
 561         enum amdgpu_connector_audio audio;
 562         enum amdgpu_connector_dither dither;
 563         unsigned pixelclock_for_modeset;
 564
 565         struct drm_dp_mst_topology_mgr mst_mgr;
 566         struct amdgpu_dm_dp_aux dm_dp_aux;
 567         struct drm_dp_mst_port *port;
 568         struct amdgpu_connector *mst_port;
 569         struct amdgpu_encoder *mst_encoder;
 570         struct semaphore mst_sem;
 571
 572         /* TODO see if we can merge with ddc_bus or make a dm_connector */
 573         struct amdgpu_i2c_adapter *i2c;
 574
 575         /* Monitor range limits */
 576         int min_vfreq ;
 577         int max_vfreq ;
 578         int pixel_clock_mhz;
 579
 580         /*freesync caps*/
 581         struct mod_freesync_caps caps;
 582
 583         struct mutex hpd_lock;
 584
 585 };
 586
 587 /* TODO: start to use this struct and remove same field from base one */
 588 struct amdgpu_mst_connector {
 589         struct amdgpu_connector base;
 590
 591         struct drm_dp_mst_topology_mgr mst_mgr;
 592         struct amdgpu_dm_dp_aux dm_dp_aux;
 593         struct drm_dp_mst_port *port;
 594         struct amdgpu_connector *mst_port;
 595         bool is_mst_connector;
 596         struct amdgpu_encoder *mst_encoder;
 597 };
 598
 599 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 600                                 ((em) == ATOM_ENCODER_MODE_DP_MST))
 601
 602 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
 603 #define DRM_SCANOUTPOS_VALID        (1 << 0)
 604 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
 605 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
 606 #define USE_REAL_VBLANKSTART            (1 << 30)
 607 #define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 608
 609 void amdgpu_link_encoder_connector(struct drm_device *dev);
 610
 611 struct drm_connector *
 612 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
 613 struct drm_connector *
 614 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
 615 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
 616                                     u32 pixel_clock);
 617
 618 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 619 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
 620
 621 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
 622
 623 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
 624
 625 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 626                                unsigned int flags, int *vpos, int *hpos,
 627                                ktime_t *stime, ktime_t *etime,
 628                                const struct drm_display_mode *mode);
 629
 630 int amdgpu_framebuffer_init(struct drm_device *dev,
 631                              struct amdgpu_framebuffer *rfb,
 632                              const struct drm_mode_fb_cmd2 *mode_cmd,
 633                              struct drm_gem_object *obj);
 634
 635 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 636
 637 void amdgpu_enc_destroy(struct drm_encoder *encoder);
 638 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 639 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 640                                         const struct drm_display_mode *mode,
 641                                         struct drm_display_mode *adjusted_mode);
 642 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
 643                              struct drm_display_mode *adjusted_mode);
 644 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
 645
 646 /* fbdev layer */
 647 int amdgpu_fbdev_init(struct amdgpu_device *adev);
 648 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
 649 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
 650 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
 651 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
 652 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
 653
 654 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
 655
 656
 657 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
 658
 659 /* amdgpu_display.c */
 660 void amdgpu_print_display_setup(struct drm_device *dev);
 661 int amdgpu_modeset_create_props(struct amdgpu_device *adev);
 662 int amdgpu_crtc_set_config(struct drm_mode_set *set,
 663                            struct drm_modeset_acquire_ctx *ctx);
 664 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
 665                                  struct drm_framebuffer *fb,
 666                                  struct drm_pending_vblank_event *event,
 667                                  uint32_t page_flip_flags, uint32_t target,
 668                                  struct drm_modeset_acquire_ctx *ctx);
 669 void amdgpu_crtc_cleanup_flip_ctx(struct amdgpu_flip_work *work,
 670                                   struct amdgpu_bo *new_abo);
 671 int amdgpu_crtc_prepare_flip(struct drm_crtc *crtc,
 672                              struct drm_framebuffer *fb,
 673                              struct drm_pending_vblank_event *event,
 674                              uint32_t page_flip_flags,
 675                              uint32_t target,
 676                              struct amdgpu_flip_work **work,
 677                              struct amdgpu_bo **new_abo);
 678
 679 void amdgpu_crtc_submit_flip(struct drm_crtc *crtc,
 680                              struct drm_framebuffer *fb,
 681                              struct amdgpu_flip_work *work,
 682                              struct amdgpu_bo *new_abo);
 683
 684 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
 685
 686 #endif