2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_display.h"
32 #include <linux/power_supply.h>
33 #include <linux/hwmon.h>
34 #include <linux/hwmon-sysfs.h>
35 #include <linux/nospec.h>
37 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
);
39 static const struct cg_flag_name clocks
[] = {
40 {AMD_CG_SUPPORT_GFX_MGCG
, "Graphics Medium Grain Clock Gating"},
41 {AMD_CG_SUPPORT_GFX_MGLS
, "Graphics Medium Grain memory Light Sleep"},
42 {AMD_CG_SUPPORT_GFX_CGCG
, "Graphics Coarse Grain Clock Gating"},
43 {AMD_CG_SUPPORT_GFX_CGLS
, "Graphics Coarse Grain memory Light Sleep"},
44 {AMD_CG_SUPPORT_GFX_CGTS
, "Graphics Coarse Grain Tree Shader Clock Gating"},
45 {AMD_CG_SUPPORT_GFX_CGTS_LS
, "Graphics Coarse Grain Tree Shader Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_CP_LS
, "Graphics Command Processor Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_RLC_LS
, "Graphics Run List Controller Light Sleep"},
48 {AMD_CG_SUPPORT_GFX_3D_CGCG
, "Graphics 3D Coarse Grain Clock Gating"},
49 {AMD_CG_SUPPORT_GFX_3D_CGLS
, "Graphics 3D Coarse Grain memory Light Sleep"},
50 {AMD_CG_SUPPORT_MC_LS
, "Memory Controller Light Sleep"},
51 {AMD_CG_SUPPORT_MC_MGCG
, "Memory Controller Medium Grain Clock Gating"},
52 {AMD_CG_SUPPORT_SDMA_LS
, "System Direct Memory Access Light Sleep"},
53 {AMD_CG_SUPPORT_SDMA_MGCG
, "System Direct Memory Access Medium Grain Clock Gating"},
54 {AMD_CG_SUPPORT_BIF_MGCG
, "Bus Interface Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_BIF_LS
, "Bus Interface Light Sleep"},
56 {AMD_CG_SUPPORT_UVD_MGCG
, "Unified Video Decoder Medium Grain Clock Gating"},
57 {AMD_CG_SUPPORT_VCE_MGCG
, "Video Compression Engine Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_HDP_LS
, "Host Data Path Light Sleep"},
59 {AMD_CG_SUPPORT_HDP_MGCG
, "Host Data Path Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_DRM_MGCG
, "Digital Right Management Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_DRM_LS
, "Digital Right Management Light Sleep"},
62 {AMD_CG_SUPPORT_ROM_MGCG
, "Rom Medium Grain Clock Gating"},
63 {AMD_CG_SUPPORT_DF_MGCG
, "Data Fabric Medium Grain Clock Gating"},
67 void amdgpu_pm_acpi_event_handler(struct amdgpu_device
*adev
)
69 if (adev
->pm
.dpm_enabled
) {
70 mutex_lock(&adev
->pm
.mutex
);
71 if (power_supply_is_system_supplied() > 0)
72 adev
->pm
.ac_power
= true;
74 adev
->pm
.ac_power
= false;
75 if (adev
->powerplay
.pp_funcs
->enable_bapm
)
76 amdgpu_dpm_enable_bapm(adev
, adev
->pm
.ac_power
);
77 mutex_unlock(&adev
->pm
.mutex
);
82 * DOC: power_dpm_state
84 * The power_dpm_state file is a legacy interface and is only provided for
85 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
86 * certain power related parameters. The file power_dpm_state is used for this.
87 * It accepts the following arguments:
97 * On older GPUs, the vbios provided a special power state for battery
98 * operation. Selecting battery switched to this state. This is no
99 * longer provided on newer GPUs so the option does nothing in that case.
103 * On older GPUs, the vbios provided a special power state for balanced
104 * operation. Selecting balanced switched to this state. This is no
105 * longer provided on newer GPUs so the option does nothing in that case.
109 * On older GPUs, the vbios provided a special power state for performance
110 * operation. Selecting performance switched to this state. This is no
111 * longer provided on newer GPUs so the option does nothing in that case.
115 static ssize_t
amdgpu_get_dpm_state(struct device
*dev
,
116 struct device_attribute
*attr
,
119 struct drm_device
*ddev
= dev_get_drvdata(dev
);
120 struct amdgpu_device
*adev
= ddev
->dev_private
;
121 enum amd_pm_state_type pm
;
123 if (adev
->powerplay
.pp_funcs
->get_current_power_state
)
124 pm
= amdgpu_dpm_get_current_power_state(adev
);
126 pm
= adev
->pm
.dpm
.user_state
;
128 return snprintf(buf
, PAGE_SIZE
, "%s\n",
129 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
130 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
133 static ssize_t
amdgpu_set_dpm_state(struct device
*dev
,
134 struct device_attribute
*attr
,
138 struct drm_device
*ddev
= dev_get_drvdata(dev
);
139 struct amdgpu_device
*adev
= ddev
->dev_private
;
140 enum amd_pm_state_type state
;
142 if (strncmp("battery", buf
, strlen("battery")) == 0)
143 state
= POWER_STATE_TYPE_BATTERY
;
144 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
145 state
= POWER_STATE_TYPE_BALANCED
;
146 else if (strncmp("performance", buf
, strlen("performance")) == 0)
147 state
= POWER_STATE_TYPE_PERFORMANCE
;
153 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
154 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
156 mutex_lock(&adev
->pm
.mutex
);
157 adev
->pm
.dpm
.user_state
= state
;
158 mutex_unlock(&adev
->pm
.mutex
);
160 /* Can't set dpm state when the card is off */
161 if (!(adev
->flags
& AMD_IS_PX
) ||
162 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
163 amdgpu_pm_compute_clocks(adev
);
171 * DOC: power_dpm_force_performance_level
173 * The amdgpu driver provides a sysfs API for adjusting certain power
174 * related parameters. The file power_dpm_force_performance_level is
175 * used for this. It accepts the following arguments:
195 * When auto is selected, the driver will attempt to dynamically select
196 * the optimal power profile for current conditions in the driver.
200 * When low is selected, the clocks are forced to the lowest power state.
204 * When high is selected, the clocks are forced to the highest power state.
208 * When manual is selected, the user can manually adjust which power states
209 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
210 * and pp_dpm_pcie files and adjust the power state transition heuristics
211 * via the pp_power_profile_mode sysfs file.
218 * When the profiling modes are selected, clock and power gating are
219 * disabled and the clocks are set for different profiling cases. This
220 * mode is recommended for profiling specific work loads where you do
221 * not want clock or power gating for clock fluctuation to interfere
222 * with your results. profile_standard sets the clocks to a fixed clock
223 * level which varies from asic to asic. profile_min_sclk forces the sclk
224 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
225 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
229 static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device
*dev
,
230 struct device_attribute
*attr
,
233 struct drm_device
*ddev
= dev_get_drvdata(dev
);
234 struct amdgpu_device
*adev
= ddev
->dev_private
;
235 enum amd_dpm_forced_level level
= 0xff;
237 if ((adev
->flags
& AMD_IS_PX
) &&
238 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
239 return snprintf(buf
, PAGE_SIZE
, "off\n");
241 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
242 level
= amdgpu_dpm_get_performance_level(adev
);
244 level
= adev
->pm
.dpm
.forced_level
;
246 return snprintf(buf
, PAGE_SIZE
, "%s\n",
247 (level
== AMD_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
248 (level
== AMD_DPM_FORCED_LEVEL_LOW
) ? "low" :
249 (level
== AMD_DPM_FORCED_LEVEL_HIGH
) ? "high" :
250 (level
== AMD_DPM_FORCED_LEVEL_MANUAL
) ? "manual" :
251 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
) ? "profile_standard" :
252 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) ? "profile_min_sclk" :
253 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) ? "profile_min_mclk" :
254 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) ? "profile_peak" :
258 static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device
*dev
,
259 struct device_attribute
*attr
,
263 struct drm_device
*ddev
= dev_get_drvdata(dev
);
264 struct amdgpu_device
*adev
= ddev
->dev_private
;
265 enum amd_dpm_forced_level level
;
266 enum amd_dpm_forced_level current_level
= 0xff;
269 /* Can't force performance level when the card is off */
270 if ((adev
->flags
& AMD_IS_PX
) &&
271 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
274 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
275 current_level
= amdgpu_dpm_get_performance_level(adev
);
277 if (strncmp("low", buf
, strlen("low")) == 0) {
278 level
= AMD_DPM_FORCED_LEVEL_LOW
;
279 } else if (strncmp("high", buf
, strlen("high")) == 0) {
280 level
= AMD_DPM_FORCED_LEVEL_HIGH
;
281 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
282 level
= AMD_DPM_FORCED_LEVEL_AUTO
;
283 } else if (strncmp("manual", buf
, strlen("manual")) == 0) {
284 level
= AMD_DPM_FORCED_LEVEL_MANUAL
;
285 } else if (strncmp("profile_exit", buf
, strlen("profile_exit")) == 0) {
286 level
= AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
;
287 } else if (strncmp("profile_standard", buf
, strlen("profile_standard")) == 0) {
288 level
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
;
289 } else if (strncmp("profile_min_sclk", buf
, strlen("profile_min_sclk")) == 0) {
290 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
;
291 } else if (strncmp("profile_min_mclk", buf
, strlen("profile_min_mclk")) == 0) {
292 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
;
293 } else if (strncmp("profile_peak", buf
, strlen("profile_peak")) == 0) {
294 level
= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
300 if (current_level
== level
)
303 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
304 mutex_lock(&adev
->pm
.mutex
);
305 if (adev
->pm
.dpm
.thermal_active
) {
307 mutex_unlock(&adev
->pm
.mutex
);
310 ret
= amdgpu_dpm_force_performance_level(adev
, level
);
314 adev
->pm
.dpm
.forced_level
= level
;
315 mutex_unlock(&adev
->pm
.mutex
);
322 static ssize_t
amdgpu_get_pp_num_states(struct device
*dev
,
323 struct device_attribute
*attr
,
326 struct drm_device
*ddev
= dev_get_drvdata(dev
);
327 struct amdgpu_device
*adev
= ddev
->dev_private
;
328 struct pp_states_info data
;
331 if (adev
->powerplay
.pp_funcs
->get_pp_num_states
)
332 amdgpu_dpm_get_pp_num_states(adev
, &data
);
334 buf_len
= snprintf(buf
, PAGE_SIZE
, "states: %d\n", data
.nums
);
335 for (i
= 0; i
< data
.nums
; i
++)
336 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
, "%d %s\n", i
,
337 (data
.states
[i
] == POWER_STATE_TYPE_INTERNAL_BOOT
) ? "boot" :
338 (data
.states
[i
] == POWER_STATE_TYPE_BATTERY
) ? "battery" :
339 (data
.states
[i
] == POWER_STATE_TYPE_BALANCED
) ? "balanced" :
340 (data
.states
[i
] == POWER_STATE_TYPE_PERFORMANCE
) ? "performance" : "default");
345 static ssize_t
amdgpu_get_pp_cur_state(struct device
*dev
,
346 struct device_attribute
*attr
,
349 struct drm_device
*ddev
= dev_get_drvdata(dev
);
350 struct amdgpu_device
*adev
= ddev
->dev_private
;
351 struct pp_states_info data
;
352 enum amd_pm_state_type pm
= 0;
355 if (adev
->powerplay
.pp_funcs
->get_current_power_state
356 && adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
357 pm
= amdgpu_dpm_get_current_power_state(adev
);
358 amdgpu_dpm_get_pp_num_states(adev
, &data
);
360 for (i
= 0; i
< data
.nums
; i
++) {
361 if (pm
== data
.states
[i
])
369 return snprintf(buf
, PAGE_SIZE
, "%d\n", i
);
372 static ssize_t
amdgpu_get_pp_force_state(struct device
*dev
,
373 struct device_attribute
*attr
,
376 struct drm_device
*ddev
= dev_get_drvdata(dev
);
377 struct amdgpu_device
*adev
= ddev
->dev_private
;
379 if (adev
->pp_force_state_enabled
)
380 return amdgpu_get_pp_cur_state(dev
, attr
, buf
);
382 return snprintf(buf
, PAGE_SIZE
, "\n");
385 static ssize_t
amdgpu_set_pp_force_state(struct device
*dev
,
386 struct device_attribute
*attr
,
390 struct drm_device
*ddev
= dev_get_drvdata(dev
);
391 struct amdgpu_device
*adev
= ddev
->dev_private
;
392 enum amd_pm_state_type state
= 0;
396 if (strlen(buf
) == 1)
397 adev
->pp_force_state_enabled
= false;
398 else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
&&
399 adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
400 struct pp_states_info data
;
402 ret
= kstrtoul(buf
, 0, &idx
);
403 if (ret
|| idx
>= ARRAY_SIZE(data
.states
)) {
407 idx
= array_index_nospec(idx
, ARRAY_SIZE(data
.states
));
409 amdgpu_dpm_get_pp_num_states(adev
, &data
);
410 state
= data
.states
[idx
];
411 /* only set user selected power states */
412 if (state
!= POWER_STATE_TYPE_INTERNAL_BOOT
&&
413 state
!= POWER_STATE_TYPE_DEFAULT
) {
414 amdgpu_dpm_dispatch_task(adev
,
415 AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
416 adev
->pp_force_state_enabled
= true;
426 * The amdgpu driver provides a sysfs API for uploading new powerplay
427 * tables. The file pp_table is used for this. Reading the file
428 * will dump the current power play table. Writing to the file
429 * will attempt to upload a new powerplay table and re-initialize
430 * powerplay using that new table.
434 static ssize_t
amdgpu_get_pp_table(struct device
*dev
,
435 struct device_attribute
*attr
,
438 struct drm_device
*ddev
= dev_get_drvdata(dev
);
439 struct amdgpu_device
*adev
= ddev
->dev_private
;
443 if (adev
->powerplay
.pp_funcs
->get_pp_table
)
444 size
= amdgpu_dpm_get_pp_table(adev
, &table
);
448 if (size
>= PAGE_SIZE
)
449 size
= PAGE_SIZE
- 1;
451 memcpy(buf
, table
, size
);
456 static ssize_t
amdgpu_set_pp_table(struct device
*dev
,
457 struct device_attribute
*attr
,
461 struct drm_device
*ddev
= dev_get_drvdata(dev
);
462 struct amdgpu_device
*adev
= ddev
->dev_private
;
464 if (adev
->powerplay
.pp_funcs
->set_pp_table
)
465 amdgpu_dpm_set_pp_table(adev
, buf
, count
);
471 * DOC: pp_od_clk_voltage
473 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
474 * in each power level within a power state. The pp_od_clk_voltage is used for
477 * < For Vega10 and previous ASICs >
479 * Reading the file will display:
481 * - a list of engine clock levels and voltages labeled OD_SCLK
483 * - a list of memory clock levels and voltages labeled OD_MCLK
485 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
487 * To manually adjust these settings, first select manual using
488 * power_dpm_force_performance_level. Enter a new value for each
489 * level by writing a string that contains "s/m level clock voltage" to
490 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
491 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
492 * 810 mV. When you have edited all of the states as needed, write
493 * "c" (commit) to the file to commit your changes. If you want to reset to the
494 * default power levels, write "r" (reset) to the file to reset them.
499 * Reading the file will display:
501 * - minimum and maximum engine clock labeled OD_SCLK
503 * - maximum memory clock labeled OD_MCLK
505 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
506 * They can be used to calibrate the sclk voltage curve.
508 * - a list of valid ranges for sclk, mclk, and voltage curve points
511 * To manually adjust these settings:
513 * - First select manual using power_dpm_force_performance_level
515 * - For clock frequency setting, enter a new value by writing a
516 * string that contains "s/m index clock" to the file. The index
517 * should be 0 if to set minimum clock. And 1 if to set maximum
518 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
519 * "m 1 800" will update maximum mclk to be 800Mhz.
521 * For sclk voltage curve, enter the new values by writing a
522 * string that contains "vc point clock voltage" to the file. The
523 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
524 * update point1 with clock set as 300Mhz and voltage as
525 * 600mV. "vc 2 1000 1000" will update point3 with clock set
526 * as 1000Mhz and voltage 1000mV.
528 * - When you have edited all of the states as needed, write "c" (commit)
529 * to the file to commit your changes
531 * - If you want to reset to the default power levels, write "r" (reset)
532 * to the file to reset them
536 static ssize_t
amdgpu_set_pp_od_clk_voltage(struct device
*dev
,
537 struct device_attribute
*attr
,
541 struct drm_device
*ddev
= dev_get_drvdata(dev
);
542 struct amdgpu_device
*adev
= ddev
->dev_private
;
544 uint32_t parameter_size
= 0;
549 const char delimiter
[3] = {' ', '\n', '\0'};
556 type
= PP_OD_EDIT_SCLK_VDDC_TABLE
;
557 else if (*buf
== 'm')
558 type
= PP_OD_EDIT_MCLK_VDDC_TABLE
;
560 type
= PP_OD_RESTORE_DEFAULT_TABLE
;
561 else if (*buf
== 'c')
562 type
= PP_OD_COMMIT_DPM_TABLE
;
563 else if (!strncmp(buf
, "vc", 2))
564 type
= PP_OD_EDIT_VDDC_CURVE
;
568 memcpy(buf_cpy
, buf
, count
+1);
572 if (type
== PP_OD_EDIT_VDDC_CURVE
)
574 while (isspace(*++tmp_str
));
577 sub_str
= strsep(&tmp_str
, delimiter
);
578 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
583 while (isspace(*tmp_str
))
587 if (adev
->powerplay
.pp_funcs
->odn_edit_dpm_table
)
588 ret
= amdgpu_dpm_odn_edit_dpm_table(adev
, type
,
589 parameter
, parameter_size
);
594 if (type
== PP_OD_COMMIT_DPM_TABLE
) {
595 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
596 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
606 static ssize_t
amdgpu_get_pp_od_clk_voltage(struct device
*dev
,
607 struct device_attribute
*attr
,
610 struct drm_device
*ddev
= dev_get_drvdata(dev
);
611 struct amdgpu_device
*adev
= ddev
->dev_private
;
614 if (adev
->powerplay
.pp_funcs
->print_clock_levels
) {
615 size
= amdgpu_dpm_print_clock_levels(adev
, OD_SCLK
, buf
);
616 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_MCLK
, buf
+size
);
617 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_VDDC_CURVE
, buf
+size
);
618 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_RANGE
, buf
+size
);
621 return snprintf(buf
, PAGE_SIZE
, "\n");
627 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
629 * The amdgpu driver provides a sysfs API for adjusting what power levels
630 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
631 * and pp_dpm_pcie are used for this.
633 * Reading back the files will show you the available power levels within
634 * the power state and the clock information for those levels.
636 * To manually adjust these states, first select manual using
637 * power_dpm_force_performance_level.
638 * Secondly,Enter a new value for each level by inputing a string that
639 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
640 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
643 static ssize_t
amdgpu_get_pp_dpm_sclk(struct device
*dev
,
644 struct device_attribute
*attr
,
647 struct drm_device
*ddev
= dev_get_drvdata(dev
);
648 struct amdgpu_device
*adev
= ddev
->dev_private
;
650 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
651 return amdgpu_dpm_print_clock_levels(adev
, PP_SCLK
, buf
);
653 return snprintf(buf
, PAGE_SIZE
, "\n");
657 * Worst case: 32 bits individually specified, in octal at 12 characters
658 * per line (+1 for \n).
660 #define AMDGPU_MASK_BUF_MAX (32 * 13)
662 static ssize_t
amdgpu_read_mask(const char *buf
, size_t count
, uint32_t *mask
)
666 char *sub_str
= NULL
;
668 char buf_cpy
[AMDGPU_MASK_BUF_MAX
+ 1];
669 const char delimiter
[3] = {' ', '\n', '\0'};
674 bytes
= min(count
, sizeof(buf_cpy
) - 1);
675 memcpy(buf_cpy
, buf
, bytes
);
676 buf_cpy
[bytes
] = '\0';
679 sub_str
= strsep(&tmp
, delimiter
);
680 if (strlen(sub_str
)) {
681 ret
= kstrtol(sub_str
, 0, &level
);
692 static ssize_t
amdgpu_set_pp_dpm_sclk(struct device
*dev
,
693 struct device_attribute
*attr
,
697 struct drm_device
*ddev
= dev_get_drvdata(dev
);
698 struct amdgpu_device
*adev
= ddev
->dev_private
;
702 ret
= amdgpu_read_mask(buf
, count
, &mask
);
706 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
707 amdgpu_dpm_force_clock_level(adev
, PP_SCLK
, mask
);
712 static ssize_t
amdgpu_get_pp_dpm_mclk(struct device
*dev
,
713 struct device_attribute
*attr
,
716 struct drm_device
*ddev
= dev_get_drvdata(dev
);
717 struct amdgpu_device
*adev
= ddev
->dev_private
;
719 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
720 return amdgpu_dpm_print_clock_levels(adev
, PP_MCLK
, buf
);
722 return snprintf(buf
, PAGE_SIZE
, "\n");
725 static ssize_t
amdgpu_set_pp_dpm_mclk(struct device
*dev
,
726 struct device_attribute
*attr
,
730 struct drm_device
*ddev
= dev_get_drvdata(dev
);
731 struct amdgpu_device
*adev
= ddev
->dev_private
;
735 ret
= amdgpu_read_mask(buf
, count
, &mask
);
739 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
740 amdgpu_dpm_force_clock_level(adev
, PP_MCLK
, mask
);
745 static ssize_t
amdgpu_get_pp_dpm_pcie(struct device
*dev
,
746 struct device_attribute
*attr
,
749 struct drm_device
*ddev
= dev_get_drvdata(dev
);
750 struct amdgpu_device
*adev
= ddev
->dev_private
;
752 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
753 return amdgpu_dpm_print_clock_levels(adev
, PP_PCIE
, buf
);
755 return snprintf(buf
, PAGE_SIZE
, "\n");
758 static ssize_t
amdgpu_set_pp_dpm_pcie(struct device
*dev
,
759 struct device_attribute
*attr
,
763 struct drm_device
*ddev
= dev_get_drvdata(dev
);
764 struct amdgpu_device
*adev
= ddev
->dev_private
;
768 ret
= amdgpu_read_mask(buf
, count
, &mask
);
772 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
773 amdgpu_dpm_force_clock_level(adev
, PP_PCIE
, mask
);
778 static ssize_t
amdgpu_get_pp_sclk_od(struct device
*dev
,
779 struct device_attribute
*attr
,
782 struct drm_device
*ddev
= dev_get_drvdata(dev
);
783 struct amdgpu_device
*adev
= ddev
->dev_private
;
786 if (adev
->powerplay
.pp_funcs
->get_sclk_od
)
787 value
= amdgpu_dpm_get_sclk_od(adev
);
789 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
792 static ssize_t
amdgpu_set_pp_sclk_od(struct device
*dev
,
793 struct device_attribute
*attr
,
797 struct drm_device
*ddev
= dev_get_drvdata(dev
);
798 struct amdgpu_device
*adev
= ddev
->dev_private
;
802 ret
= kstrtol(buf
, 0, &value
);
808 if (adev
->powerplay
.pp_funcs
->set_sclk_od
)
809 amdgpu_dpm_set_sclk_od(adev
, (uint32_t)value
);
811 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
812 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
814 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
815 amdgpu_pm_compute_clocks(adev
);
822 static ssize_t
amdgpu_get_pp_mclk_od(struct device
*dev
,
823 struct device_attribute
*attr
,
826 struct drm_device
*ddev
= dev_get_drvdata(dev
);
827 struct amdgpu_device
*adev
= ddev
->dev_private
;
830 if (adev
->powerplay
.pp_funcs
->get_mclk_od
)
831 value
= amdgpu_dpm_get_mclk_od(adev
);
833 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
836 static ssize_t
amdgpu_set_pp_mclk_od(struct device
*dev
,
837 struct device_attribute
*attr
,
841 struct drm_device
*ddev
= dev_get_drvdata(dev
);
842 struct amdgpu_device
*adev
= ddev
->dev_private
;
846 ret
= kstrtol(buf
, 0, &value
);
852 if (adev
->powerplay
.pp_funcs
->set_mclk_od
)
853 amdgpu_dpm_set_mclk_od(adev
, (uint32_t)value
);
855 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
856 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
858 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
859 amdgpu_pm_compute_clocks(adev
);
867 * DOC: pp_power_profile_mode
869 * The amdgpu driver provides a sysfs API for adjusting the heuristics
870 * related to switching between power levels in a power state. The file
871 * pp_power_profile_mode is used for this.
873 * Reading this file outputs a list of all of the predefined power profiles
874 * and the relevant heuristics settings for that profile.
876 * To select a profile or create a custom profile, first select manual using
877 * power_dpm_force_performance_level. Writing the number of a predefined
878 * profile to pp_power_profile_mode will enable those heuristics. To
879 * create a custom set of heuristics, write a string of numbers to the file
880 * starting with the number of the custom profile along with a setting
881 * for each heuristic parameter. Due to differences across asic families
882 * the heuristic parameters vary from family to family.
886 static ssize_t
amdgpu_get_pp_power_profile_mode(struct device
*dev
,
887 struct device_attribute
*attr
,
890 struct drm_device
*ddev
= dev_get_drvdata(dev
);
891 struct amdgpu_device
*adev
= ddev
->dev_private
;
893 if (adev
->powerplay
.pp_funcs
->get_power_profile_mode
)
894 return amdgpu_dpm_get_power_profile_mode(adev
, buf
);
896 return snprintf(buf
, PAGE_SIZE
, "\n");
900 static ssize_t
amdgpu_set_pp_power_profile_mode(struct device
*dev
,
901 struct device_attribute
*attr
,
906 struct drm_device
*ddev
= dev_get_drvdata(dev
);
907 struct amdgpu_device
*adev
= ddev
->dev_private
;
908 uint32_t parameter_size
= 0;
910 char *sub_str
, buf_cpy
[128];
914 long int profile_mode
= 0;
915 const char delimiter
[3] = {' ', '\n', '\0'};
919 ret
= kstrtol(tmp
, 0, &profile_mode
);
923 if (profile_mode
== PP_SMC_POWER_PROFILE_CUSTOM
) {
924 if (count
< 2 || count
> 127)
926 while (isspace(*++buf
))
928 memcpy(buf_cpy
, buf
, count
-i
);
931 sub_str
= strsep(&tmp_str
, delimiter
);
932 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
938 while (isspace(*tmp_str
))
942 parameter
[parameter_size
] = profile_mode
;
943 if (adev
->powerplay
.pp_funcs
->set_power_profile_mode
)
944 ret
= amdgpu_dpm_set_power_profile_mode(adev
, parameter
, parameter_size
);
955 * The amdgpu driver provides a sysfs API for reading how busy the GPU
956 * is as a percentage. The file gpu_busy_percent is used for this.
957 * The SMU firmware computes a percentage of load based on the
958 * aggregate activity level in the IP cores.
960 static ssize_t
amdgpu_get_busy_percent(struct device
*dev
,
961 struct device_attribute
*attr
,
964 struct drm_device
*ddev
= dev_get_drvdata(dev
);
965 struct amdgpu_device
*adev
= ddev
->dev_private
;
966 int r
, value
, size
= sizeof(value
);
968 /* sanity check PP is enabled */
969 if (!(adev
->powerplay
.pp_funcs
&&
970 adev
->powerplay
.pp_funcs
->read_sensor
))
973 /* read the IP busy sensor */
974 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
,
975 (void *)&value
, &size
);
979 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
982 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, amdgpu_get_dpm_state
, amdgpu_set_dpm_state
);
983 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
984 amdgpu_get_dpm_forced_performance_level
,
985 amdgpu_set_dpm_forced_performance_level
);
986 static DEVICE_ATTR(pp_num_states
, S_IRUGO
, amdgpu_get_pp_num_states
, NULL
);
987 static DEVICE_ATTR(pp_cur_state
, S_IRUGO
, amdgpu_get_pp_cur_state
, NULL
);
988 static DEVICE_ATTR(pp_force_state
, S_IRUGO
| S_IWUSR
,
989 amdgpu_get_pp_force_state
,
990 amdgpu_set_pp_force_state
);
991 static DEVICE_ATTR(pp_table
, S_IRUGO
| S_IWUSR
,
993 amdgpu_set_pp_table
);
994 static DEVICE_ATTR(pp_dpm_sclk
, S_IRUGO
| S_IWUSR
,
995 amdgpu_get_pp_dpm_sclk
,
996 amdgpu_set_pp_dpm_sclk
);
997 static DEVICE_ATTR(pp_dpm_mclk
, S_IRUGO
| S_IWUSR
,
998 amdgpu_get_pp_dpm_mclk
,
999 amdgpu_set_pp_dpm_mclk
);
1000 static DEVICE_ATTR(pp_dpm_pcie
, S_IRUGO
| S_IWUSR
,
1001 amdgpu_get_pp_dpm_pcie
,
1002 amdgpu_set_pp_dpm_pcie
);
1003 static DEVICE_ATTR(pp_sclk_od
, S_IRUGO
| S_IWUSR
,
1004 amdgpu_get_pp_sclk_od
,
1005 amdgpu_set_pp_sclk_od
);
1006 static DEVICE_ATTR(pp_mclk_od
, S_IRUGO
| S_IWUSR
,
1007 amdgpu_get_pp_mclk_od
,
1008 amdgpu_set_pp_mclk_od
);
1009 static DEVICE_ATTR(pp_power_profile_mode
, S_IRUGO
| S_IWUSR
,
1010 amdgpu_get_pp_power_profile_mode
,
1011 amdgpu_set_pp_power_profile_mode
);
1012 static DEVICE_ATTR(pp_od_clk_voltage
, S_IRUGO
| S_IWUSR
,
1013 amdgpu_get_pp_od_clk_voltage
,
1014 amdgpu_set_pp_od_clk_voltage
);
1015 static DEVICE_ATTR(gpu_busy_percent
, S_IRUGO
,
1016 amdgpu_get_busy_percent
, NULL
);
1018 static ssize_t
amdgpu_hwmon_show_temp(struct device
*dev
,
1019 struct device_attribute
*attr
,
1022 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1023 struct drm_device
*ddev
= adev
->ddev
;
1024 int r
, temp
, size
= sizeof(temp
);
1026 /* Can't get temperature when the card is off */
1027 if ((adev
->flags
& AMD_IS_PX
) &&
1028 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1031 /* sanity check PP is enabled */
1032 if (!(adev
->powerplay
.pp_funcs
&&
1033 adev
->powerplay
.pp_funcs
->read_sensor
))
1036 /* get the temperature */
1037 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
1038 (void *)&temp
, &size
);
1042 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1045 static ssize_t
amdgpu_hwmon_show_temp_thresh(struct device
*dev
,
1046 struct device_attribute
*attr
,
1049 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1050 int hyst
= to_sensor_dev_attr(attr
)->index
;
1054 temp
= adev
->pm
.dpm
.thermal
.min_temp
;
1056 temp
= adev
->pm
.dpm
.thermal
.max_temp
;
1058 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1061 static ssize_t
amdgpu_hwmon_get_pwm1_enable(struct device
*dev
,
1062 struct device_attribute
*attr
,
1065 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1068 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1071 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1073 return sprintf(buf
, "%i\n", pwm_mode
);
1076 static ssize_t
amdgpu_hwmon_set_pwm1_enable(struct device
*dev
,
1077 struct device_attribute
*attr
,
1081 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1085 /* Can't adjust fan when the card is off */
1086 if ((adev
->flags
& AMD_IS_PX
) &&
1087 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1090 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1093 err
= kstrtoint(buf
, 10, &value
);
1097 amdgpu_dpm_set_fan_control_mode(adev
, value
);
1102 static ssize_t
amdgpu_hwmon_get_pwm1_min(struct device
*dev
,
1103 struct device_attribute
*attr
,
1106 return sprintf(buf
, "%i\n", 0);
1109 static ssize_t
amdgpu_hwmon_get_pwm1_max(struct device
*dev
,
1110 struct device_attribute
*attr
,
1113 return sprintf(buf
, "%i\n", 255);
1116 static ssize_t
amdgpu_hwmon_set_pwm1(struct device
*dev
,
1117 struct device_attribute
*attr
,
1118 const char *buf
, size_t count
)
1120 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1125 /* Can't adjust fan when the card is off */
1126 if ((adev
->flags
& AMD_IS_PX
) &&
1127 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1130 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1131 if (pwm_mode
!= AMD_FAN_CTRL_MANUAL
) {
1132 pr_info("manual fan speed control should be enabled first\n");
1136 err
= kstrtou32(buf
, 10, &value
);
1140 value
= (value
* 100) / 255;
1142 if (adev
->powerplay
.pp_funcs
->set_fan_speed_percent
) {
1143 err
= amdgpu_dpm_set_fan_speed_percent(adev
, value
);
1151 static ssize_t
amdgpu_hwmon_get_pwm1(struct device
*dev
,
1152 struct device_attribute
*attr
,
1155 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1159 /* Can't adjust fan when the card is off */
1160 if ((adev
->flags
& AMD_IS_PX
) &&
1161 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1164 if (adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) {
1165 err
= amdgpu_dpm_get_fan_speed_percent(adev
, &speed
);
1170 speed
= (speed
* 255) / 100;
1172 return sprintf(buf
, "%i\n", speed
);
1175 static ssize_t
amdgpu_hwmon_get_fan1_input(struct device
*dev
,
1176 struct device_attribute
*attr
,
1179 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1183 /* Can't adjust fan when the card is off */
1184 if ((adev
->flags
& AMD_IS_PX
) &&
1185 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1188 if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1189 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &speed
);
1194 return sprintf(buf
, "%i\n", speed
);
1197 static ssize_t
amdgpu_hwmon_get_fan1_min(struct device
*dev
,
1198 struct device_attribute
*attr
,
1201 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1203 u32 size
= sizeof(min_rpm
);
1206 if (!adev
->powerplay
.pp_funcs
->read_sensor
)
1209 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MIN_FAN_RPM
,
1210 (void *)&min_rpm
, &size
);
1214 return snprintf(buf
, PAGE_SIZE
, "%d\n", min_rpm
);
1217 static ssize_t
amdgpu_hwmon_get_fan1_max(struct device
*dev
,
1218 struct device_attribute
*attr
,
1221 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1223 u32 size
= sizeof(max_rpm
);
1226 if (!adev
->powerplay
.pp_funcs
->read_sensor
)
1229 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MAX_FAN_RPM
,
1230 (void *)&max_rpm
, &size
);
1234 return snprintf(buf
, PAGE_SIZE
, "%d\n", max_rpm
);
1237 static ssize_t
amdgpu_hwmon_get_fan1_target(struct device
*dev
,
1238 struct device_attribute
*attr
,
1241 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1245 /* Can't adjust fan when the card is off */
1246 if ((adev
->flags
& AMD_IS_PX
) &&
1247 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1250 if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1251 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &rpm
);
1256 return sprintf(buf
, "%i\n", rpm
);
1259 static ssize_t
amdgpu_hwmon_set_fan1_target(struct device
*dev
,
1260 struct device_attribute
*attr
,
1261 const char *buf
, size_t count
)
1263 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1268 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1269 if (pwm_mode
!= AMD_FAN_CTRL_MANUAL
)
1272 /* Can't adjust fan when the card is off */
1273 if ((adev
->flags
& AMD_IS_PX
) &&
1274 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1277 err
= kstrtou32(buf
, 10, &value
);
1281 if (adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
) {
1282 err
= amdgpu_dpm_set_fan_speed_rpm(adev
, value
);
1290 static ssize_t
amdgpu_hwmon_get_fan1_enable(struct device
*dev
,
1291 struct device_attribute
*attr
,
1294 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1297 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1300 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1302 return sprintf(buf
, "%i\n", pwm_mode
== AMD_FAN_CTRL_AUTO
? 0 : 1);
1305 static ssize_t
amdgpu_hwmon_set_fan1_enable(struct device
*dev
,
1306 struct device_attribute
*attr
,
1310 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1315 /* Can't adjust fan when the card is off */
1316 if ((adev
->flags
& AMD_IS_PX
) &&
1317 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1320 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1323 err
= kstrtoint(buf
, 10, &value
);
1328 pwm_mode
= AMD_FAN_CTRL_AUTO
;
1329 else if (value
== 1)
1330 pwm_mode
= AMD_FAN_CTRL_MANUAL
;
1334 amdgpu_dpm_set_fan_control_mode(adev
, pwm_mode
);
1339 static ssize_t
amdgpu_hwmon_show_vddgfx(struct device
*dev
,
1340 struct device_attribute
*attr
,
1343 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1344 struct drm_device
*ddev
= adev
->ddev
;
1346 int r
, size
= sizeof(vddgfx
);
1348 /* Can't get voltage when the card is off */
1349 if ((adev
->flags
& AMD_IS_PX
) &&
1350 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1353 /* sanity check PP is enabled */
1354 if (!(adev
->powerplay
.pp_funcs
&&
1355 adev
->powerplay
.pp_funcs
->read_sensor
))
1358 /* get the voltage */
1359 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
,
1360 (void *)&vddgfx
, &size
);
1364 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddgfx
);
1367 static ssize_t
amdgpu_hwmon_show_vddgfx_label(struct device
*dev
,
1368 struct device_attribute
*attr
,
1371 return snprintf(buf
, PAGE_SIZE
, "vddgfx\n");
1374 static ssize_t
amdgpu_hwmon_show_vddnb(struct device
*dev
,
1375 struct device_attribute
*attr
,
1378 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1379 struct drm_device
*ddev
= adev
->ddev
;
1381 int r
, size
= sizeof(vddnb
);
1383 /* only APUs have vddnb */
1384 if (!(adev
->flags
& AMD_IS_APU
))
1387 /* Can't get voltage when the card is off */
1388 if ((adev
->flags
& AMD_IS_PX
) &&
1389 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1392 /* sanity check PP is enabled */
1393 if (!(adev
->powerplay
.pp_funcs
&&
1394 adev
->powerplay
.pp_funcs
->read_sensor
))
1397 /* get the voltage */
1398 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
,
1399 (void *)&vddnb
, &size
);
1403 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddnb
);
1406 static ssize_t
amdgpu_hwmon_show_vddnb_label(struct device
*dev
,
1407 struct device_attribute
*attr
,
1410 return snprintf(buf
, PAGE_SIZE
, "vddnb\n");
1413 static ssize_t
amdgpu_hwmon_show_power_avg(struct device
*dev
,
1414 struct device_attribute
*attr
,
1417 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1418 struct drm_device
*ddev
= adev
->ddev
;
1420 int r
, size
= sizeof(u32
);
1423 /* Can't get power when the card is off */
1424 if ((adev
->flags
& AMD_IS_PX
) &&
1425 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1428 /* sanity check PP is enabled */
1429 if (!(adev
->powerplay
.pp_funcs
&&
1430 adev
->powerplay
.pp_funcs
->read_sensor
))
1433 /* get the voltage */
1434 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
,
1435 (void *)&query
, &size
);
1439 /* convert to microwatts */
1440 uw
= (query
>> 8) * 1000000 + (query
& 0xff) * 1000;
1442 return snprintf(buf
, PAGE_SIZE
, "%u\n", uw
);
1445 static ssize_t
amdgpu_hwmon_show_power_cap_min(struct device
*dev
,
1446 struct device_attribute
*attr
,
1449 return sprintf(buf
, "%i\n", 0);
1452 static ssize_t
amdgpu_hwmon_show_power_cap_max(struct device
*dev
,
1453 struct device_attribute
*attr
,
1456 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1459 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1460 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, true);
1461 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1463 return snprintf(buf
, PAGE_SIZE
, "\n");
1467 static ssize_t
amdgpu_hwmon_show_power_cap(struct device
*dev
,
1468 struct device_attribute
*attr
,
1471 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1474 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1475 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, false);
1476 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1478 return snprintf(buf
, PAGE_SIZE
, "\n");
1483 static ssize_t
amdgpu_hwmon_set_power_cap(struct device
*dev
,
1484 struct device_attribute
*attr
,
1488 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1492 err
= kstrtou32(buf
, 10, &value
);
1496 value
= value
/ 1000000; /* convert to Watt */
1497 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->set_power_limit
) {
1498 err
= adev
->powerplay
.pp_funcs
->set_power_limit(adev
->powerplay
.pp_handle
, value
);
1512 * The amdgpu driver exposes the following sensor interfaces:
1514 * - GPU temperature (via the on-die sensor)
1518 * - Northbridge voltage (APUs only)
1524 * hwmon interfaces for GPU temperature:
1526 * - temp1_input: the on die GPU temperature in millidegrees Celsius
1528 * - temp1_crit: temperature critical max value in millidegrees Celsius
1530 * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1532 * hwmon interfaces for GPU voltage:
1534 * - in0_input: the voltage on the GPU in millivolts
1536 * - in1_input: the voltage on the Northbridge in millivolts
1538 * hwmon interfaces for GPU power:
1540 * - power1_average: average power used by the GPU in microWatts
1542 * - power1_cap_min: minimum cap supported in microWatts
1544 * - power1_cap_max: maximum cap supported in microWatts
1546 * - power1_cap: selected power cap in microWatts
1548 * hwmon interfaces for GPU fan:
1550 * - pwm1: pulse width modulation fan level (0-255)
1552 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1554 * - pwm1_min: pulse width modulation fan control minimum level (0)
1556 * - pwm1_max: pulse width modulation fan control maximum level (255)
1558 * - fan1_min: an minimum value Unit: revolution/min (RPM)
1560 * - fan1_max: an maxmum value Unit: revolution/max (RPM)
1562 * - fan1_input: fan speed in RPM
1564 * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
1566 * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
1568 * You can use hwmon tools like sensors to view this information on your system.
1572 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, 0);
1573 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 0);
1574 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 1);
1575 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1
, amdgpu_hwmon_set_pwm1
, 0);
1576 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1_enable
, amdgpu_hwmon_set_pwm1_enable
, 0);
1577 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, amdgpu_hwmon_get_pwm1_min
, NULL
, 0);
1578 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, amdgpu_hwmon_get_pwm1_max
, NULL
, 0);
1579 static SENSOR_DEVICE_ATTR(fan1_input
, S_IRUGO
, amdgpu_hwmon_get_fan1_input
, NULL
, 0);
1580 static SENSOR_DEVICE_ATTR(fan1_min
, S_IRUGO
, amdgpu_hwmon_get_fan1_min
, NULL
, 0);
1581 static SENSOR_DEVICE_ATTR(fan1_max
, S_IRUGO
, amdgpu_hwmon_get_fan1_max
, NULL
, 0);
1582 static SENSOR_DEVICE_ATTR(fan1_target
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_fan1_target
, amdgpu_hwmon_set_fan1_target
, 0);
1583 static SENSOR_DEVICE_ATTR(fan1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_fan1_enable
, amdgpu_hwmon_set_fan1_enable
, 0);
1584 static SENSOR_DEVICE_ATTR(in0_input
, S_IRUGO
, amdgpu_hwmon_show_vddgfx
, NULL
, 0);
1585 static SENSOR_DEVICE_ATTR(in0_label
, S_IRUGO
, amdgpu_hwmon_show_vddgfx_label
, NULL
, 0);
1586 static SENSOR_DEVICE_ATTR(in1_input
, S_IRUGO
, amdgpu_hwmon_show_vddnb
, NULL
, 0);
1587 static SENSOR_DEVICE_ATTR(in1_label
, S_IRUGO
, amdgpu_hwmon_show_vddnb_label
, NULL
, 0);
1588 static SENSOR_DEVICE_ATTR(power1_average
, S_IRUGO
, amdgpu_hwmon_show_power_avg
, NULL
, 0);
1589 static SENSOR_DEVICE_ATTR(power1_cap_max
, S_IRUGO
, amdgpu_hwmon_show_power_cap_max
, NULL
, 0);
1590 static SENSOR_DEVICE_ATTR(power1_cap_min
, S_IRUGO
, amdgpu_hwmon_show_power_cap_min
, NULL
, 0);
1591 static SENSOR_DEVICE_ATTR(power1_cap
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_show_power_cap
, amdgpu_hwmon_set_power_cap
, 0);
1593 static struct attribute
*hwmon_attributes
[] = {
1594 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
1595 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
1596 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
1597 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
1598 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
1599 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
1600 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
1601 &sensor_dev_attr_fan1_input
.dev_attr
.attr
,
1602 &sensor_dev_attr_fan1_min
.dev_attr
.attr
,
1603 &sensor_dev_attr_fan1_max
.dev_attr
.attr
,
1604 &sensor_dev_attr_fan1_target
.dev_attr
.attr
,
1605 &sensor_dev_attr_fan1_enable
.dev_attr
.attr
,
1606 &sensor_dev_attr_in0_input
.dev_attr
.attr
,
1607 &sensor_dev_attr_in0_label
.dev_attr
.attr
,
1608 &sensor_dev_attr_in1_input
.dev_attr
.attr
,
1609 &sensor_dev_attr_in1_label
.dev_attr
.attr
,
1610 &sensor_dev_attr_power1_average
.dev_attr
.attr
,
1611 &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
,
1612 &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
,
1613 &sensor_dev_attr_power1_cap
.dev_attr
.attr
,
1617 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
1618 struct attribute
*attr
, int index
)
1620 struct device
*dev
= kobj_to_dev(kobj
);
1621 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1622 umode_t effective_mode
= attr
->mode
;
1624 /* Skip fan attributes if fan is not present */
1625 if (adev
->pm
.no_fan
&& (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
1626 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
1627 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1628 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
1629 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
1630 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
1631 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
1632 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
1633 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
1636 /* Skip limit attributes if DPM is not enabled */
1637 if (!adev
->pm
.dpm_enabled
&&
1638 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
1639 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
1640 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
1641 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
1642 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1643 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
1644 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
1645 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
1646 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
1647 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
1648 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
1651 /* mask fan attributes if we have no bindings for this asic to expose */
1652 if ((!adev
->powerplay
.pp_funcs
->get_fan_speed_percent
&&
1653 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
1654 (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
&&
1655 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
1656 effective_mode
&= ~S_IRUGO
;
1658 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
1659 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
1660 (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
&&
1661 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
1662 effective_mode
&= ~S_IWUSR
;
1664 if ((adev
->flags
& AMD_IS_APU
) &&
1665 (attr
== &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
||
1666 attr
== &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
||
1667 attr
== &sensor_dev_attr_power1_cap
.dev_attr
.attr
))
1670 /* hide max/min values if we can't both query and manage the fan */
1671 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
1672 !adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) &&
1673 (!adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
&&
1674 !adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) &&
1675 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1676 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
1679 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
&&
1680 !adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) &&
1681 (attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
1682 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
))
1685 /* only APUs have vddnb */
1686 if (!(adev
->flags
& AMD_IS_APU
) &&
1687 (attr
== &sensor_dev_attr_in1_input
.dev_attr
.attr
||
1688 attr
== &sensor_dev_attr_in1_label
.dev_attr
.attr
))
1691 return effective_mode
;
1694 static const struct attribute_group hwmon_attrgroup
= {
1695 .attrs
= hwmon_attributes
,
1696 .is_visible
= hwmon_attributes_visible
,
1699 static const struct attribute_group
*hwmon_groups
[] = {
1704 void amdgpu_dpm_thermal_work_handler(struct work_struct
*work
)
1706 struct amdgpu_device
*adev
=
1707 container_of(work
, struct amdgpu_device
,
1708 pm
.dpm
.thermal
.work
);
1709 /* switch to the thermal state */
1710 enum amd_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
1711 int temp
, size
= sizeof(temp
);
1713 if (!adev
->pm
.dpm_enabled
)
1716 if (adev
->powerplay
.pp_funcs
&&
1717 adev
->powerplay
.pp_funcs
->read_sensor
&&
1718 !amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
1719 (void *)&temp
, &size
)) {
1720 if (temp
< adev
->pm
.dpm
.thermal
.min_temp
)
1721 /* switch back the user state */
1722 dpm_state
= adev
->pm
.dpm
.user_state
;
1724 if (adev
->pm
.dpm
.thermal
.high_to_low
)
1725 /* switch back the user state */
1726 dpm_state
= adev
->pm
.dpm
.user_state
;
1728 mutex_lock(&adev
->pm
.mutex
);
1729 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
1730 adev
->pm
.dpm
.thermal_active
= true;
1732 adev
->pm
.dpm
.thermal_active
= false;
1733 adev
->pm
.dpm
.state
= dpm_state
;
1734 mutex_unlock(&adev
->pm
.mutex
);
1736 amdgpu_pm_compute_clocks(adev
);
1739 static struct amdgpu_ps
*amdgpu_dpm_pick_power_state(struct amdgpu_device
*adev
,
1740 enum amd_pm_state_type dpm_state
)
1743 struct amdgpu_ps
*ps
;
1745 bool single_display
= (adev
->pm
.dpm
.new_active_crtc_count
< 2) ?
1748 /* check if the vblank period is too short to adjust the mclk */
1749 if (single_display
&& adev
->powerplay
.pp_funcs
->vblank_too_short
) {
1750 if (amdgpu_dpm_vblank_too_short(adev
))
1751 single_display
= false;
1754 /* certain older asics have a separare 3D performance state,
1755 * so try that first if the user selected performance
1757 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
1758 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
1759 /* balanced states don't exist at the moment */
1760 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
1761 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1764 /* Pick the best power state based on current conditions */
1765 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
1766 ps
= &adev
->pm
.dpm
.ps
[i
];
1767 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
1768 switch (dpm_state
) {
1770 case POWER_STATE_TYPE_BATTERY
:
1771 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
1772 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1779 case POWER_STATE_TYPE_BALANCED
:
1780 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
1781 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1788 case POWER_STATE_TYPE_PERFORMANCE
:
1789 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
1790 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1797 /* internal states */
1798 case POWER_STATE_TYPE_INTERNAL_UVD
:
1799 if (adev
->pm
.dpm
.uvd_ps
)
1800 return adev
->pm
.dpm
.uvd_ps
;
1803 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1804 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
1807 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1808 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
1811 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1812 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
1815 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1816 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
1819 case POWER_STATE_TYPE_INTERNAL_BOOT
:
1820 return adev
->pm
.dpm
.boot_ps
;
1821 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1822 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
1825 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1826 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
1829 case POWER_STATE_TYPE_INTERNAL_ULV
:
1830 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
1833 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1834 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
1841 /* use a fallback state if we didn't match */
1842 switch (dpm_state
) {
1843 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1844 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
1845 goto restart_search
;
1846 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1847 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1848 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1849 if (adev
->pm
.dpm
.uvd_ps
) {
1850 return adev
->pm
.dpm
.uvd_ps
;
1852 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1853 goto restart_search
;
1855 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1856 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
1857 goto restart_search
;
1858 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1859 dpm_state
= POWER_STATE_TYPE_BATTERY
;
1860 goto restart_search
;
1861 case POWER_STATE_TYPE_BATTERY
:
1862 case POWER_STATE_TYPE_BALANCED
:
1863 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1864 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1865 goto restart_search
;
1873 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device
*adev
)
1875 struct amdgpu_ps
*ps
;
1876 enum amd_pm_state_type dpm_state
;
1880 /* if dpm init failed */
1881 if (!adev
->pm
.dpm_enabled
)
1884 if (adev
->pm
.dpm
.user_state
!= adev
->pm
.dpm
.state
) {
1885 /* add other state override checks here */
1886 if ((!adev
->pm
.dpm
.thermal_active
) &&
1887 (!adev
->pm
.dpm
.uvd_active
))
1888 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.user_state
;
1890 dpm_state
= adev
->pm
.dpm
.state
;
1892 ps
= amdgpu_dpm_pick_power_state(adev
, dpm_state
);
1894 adev
->pm
.dpm
.requested_ps
= ps
;
1898 if (amdgpu_dpm
== 1 && adev
->powerplay
.pp_funcs
->print_power_state
) {
1899 printk("switching from power state:\n");
1900 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.current_ps
);
1901 printk("switching to power state:\n");
1902 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.requested_ps
);
1905 /* update whether vce is active */
1906 ps
->vce_active
= adev
->pm
.dpm
.vce_active
;
1907 if (adev
->powerplay
.pp_funcs
->display_configuration_changed
)
1908 amdgpu_dpm_display_configuration_changed(adev
);
1910 ret
= amdgpu_dpm_pre_set_power_state(adev
);
1914 if (adev
->powerplay
.pp_funcs
->check_state_equal
) {
1915 if (0 != amdgpu_dpm_check_state_equal(adev
, adev
->pm
.dpm
.current_ps
, adev
->pm
.dpm
.requested_ps
, &equal
))
1922 amdgpu_dpm_set_power_state(adev
);
1923 amdgpu_dpm_post_set_power_state(adev
);
1925 adev
->pm
.dpm
.current_active_crtcs
= adev
->pm
.dpm
.new_active_crtcs
;
1926 adev
->pm
.dpm
.current_active_crtc_count
= adev
->pm
.dpm
.new_active_crtc_count
;
1928 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
1929 if (adev
->pm
.dpm
.thermal_active
) {
1930 enum amd_dpm_forced_level level
= adev
->pm
.dpm
.forced_level
;
1931 /* force low perf level for thermal */
1932 amdgpu_dpm_force_performance_level(adev
, AMD_DPM_FORCED_LEVEL_LOW
);
1933 /* save the user's level */
1934 adev
->pm
.dpm
.forced_level
= level
;
1936 /* otherwise, user selected level */
1937 amdgpu_dpm_force_performance_level(adev
, adev
->pm
.dpm
.forced_level
);
1942 void amdgpu_dpm_enable_uvd(struct amdgpu_device
*adev
, bool enable
)
1944 if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
1945 /* enable/disable UVD */
1946 mutex_lock(&adev
->pm
.mutex
);
1947 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_UVD
, !enable
);
1948 mutex_unlock(&adev
->pm
.mutex
);
1952 void amdgpu_dpm_enable_vce(struct amdgpu_device
*adev
, bool enable
)
1954 if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
1955 /* enable/disable VCE */
1956 mutex_lock(&adev
->pm
.mutex
);
1957 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_VCE
, !enable
);
1958 mutex_unlock(&adev
->pm
.mutex
);
1962 void amdgpu_pm_print_power_states(struct amdgpu_device
*adev
)
1966 if (adev
->powerplay
.pp_funcs
->print_power_state
== NULL
)
1969 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++)
1970 amdgpu_dpm_print_power_state(adev
, &adev
->pm
.dpm
.ps
[i
]);
1974 int amdgpu_pm_sysfs_init(struct amdgpu_device
*adev
)
1978 if (adev
->pm
.sysfs_initialized
)
1981 if (adev
->pm
.dpm_enabled
== 0)
1984 adev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(adev
->dev
,
1987 if (IS_ERR(adev
->pm
.int_hwmon_dev
)) {
1988 ret
= PTR_ERR(adev
->pm
.int_hwmon_dev
);
1990 "Unable to register hwmon device: %d\n", ret
);
1994 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_state
);
1996 DRM_ERROR("failed to create device file for dpm state\n");
1999 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2001 DRM_ERROR("failed to create device file for dpm state\n");
2006 ret
= device_create_file(adev
->dev
, &dev_attr_pp_num_states
);
2008 DRM_ERROR("failed to create device file pp_num_states\n");
2011 ret
= device_create_file(adev
->dev
, &dev_attr_pp_cur_state
);
2013 DRM_ERROR("failed to create device file pp_cur_state\n");
2016 ret
= device_create_file(adev
->dev
, &dev_attr_pp_force_state
);
2018 DRM_ERROR("failed to create device file pp_force_state\n");
2021 ret
= device_create_file(adev
->dev
, &dev_attr_pp_table
);
2023 DRM_ERROR("failed to create device file pp_table\n");
2027 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2029 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2032 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2034 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2037 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
2039 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2042 ret
= device_create_file(adev
->dev
, &dev_attr_pp_sclk_od
);
2044 DRM_ERROR("failed to create device file pp_sclk_od\n");
2047 ret
= device_create_file(adev
->dev
, &dev_attr_pp_mclk_od
);
2049 DRM_ERROR("failed to create device file pp_mclk_od\n");
2052 ret
= device_create_file(adev
->dev
,
2053 &dev_attr_pp_power_profile_mode
);
2055 DRM_ERROR("failed to create device file "
2056 "pp_power_profile_mode\n");
2059 ret
= device_create_file(adev
->dev
,
2060 &dev_attr_pp_od_clk_voltage
);
2062 DRM_ERROR("failed to create device file "
2063 "pp_od_clk_voltage\n");
2066 ret
= device_create_file(adev
->dev
,
2067 &dev_attr_gpu_busy_percent
);
2069 DRM_ERROR("failed to create device file "
2070 "gpu_busy_level\n");
2073 ret
= amdgpu_debugfs_pm_init(adev
);
2075 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2079 adev
->pm
.sysfs_initialized
= true;
2084 void amdgpu_pm_sysfs_fini(struct amdgpu_device
*adev
)
2086 if (adev
->pm
.dpm_enabled
== 0)
2089 if (adev
->pm
.int_hwmon_dev
)
2090 hwmon_device_unregister(adev
->pm
.int_hwmon_dev
);
2091 device_remove_file(adev
->dev
, &dev_attr_power_dpm_state
);
2092 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2094 device_remove_file(adev
->dev
, &dev_attr_pp_num_states
);
2095 device_remove_file(adev
->dev
, &dev_attr_pp_cur_state
);
2096 device_remove_file(adev
->dev
, &dev_attr_pp_force_state
);
2097 device_remove_file(adev
->dev
, &dev_attr_pp_table
);
2099 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2100 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2101 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
2102 device_remove_file(adev
->dev
, &dev_attr_pp_sclk_od
);
2103 device_remove_file(adev
->dev
, &dev_attr_pp_mclk_od
);
2104 device_remove_file(adev
->dev
,
2105 &dev_attr_pp_power_profile_mode
);
2106 device_remove_file(adev
->dev
,
2107 &dev_attr_pp_od_clk_voltage
);
2108 device_remove_file(adev
->dev
, &dev_attr_gpu_busy_percent
);
2111 void amdgpu_pm_compute_clocks(struct amdgpu_device
*adev
)
2115 if (!adev
->pm
.dpm_enabled
)
2118 if (adev
->mode_info
.num_crtc
)
2119 amdgpu_display_bandwidth_update(adev
);
2121 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
2122 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2123 if (ring
&& ring
->ready
)
2124 amdgpu_fence_wait_empty(ring
);
2127 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
2128 if (!amdgpu_device_has_dc_support(adev
)) {
2129 mutex_lock(&adev
->pm
.mutex
);
2130 amdgpu_dpm_get_active_displays(adev
);
2131 adev
->pm
.pm_display_cfg
.num_display
= adev
->pm
.dpm
.new_active_crtc_count
;
2132 adev
->pm
.pm_display_cfg
.vrefresh
= amdgpu_dpm_get_vrefresh(adev
);
2133 adev
->pm
.pm_display_cfg
.min_vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
2134 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2135 if (adev
->pm
.pm_display_cfg
.vrefresh
> 120)
2136 adev
->pm
.pm_display_cfg
.min_vblank_time
= 0;
2137 if (adev
->powerplay
.pp_funcs
->display_configuration_change
)
2138 adev
->powerplay
.pp_funcs
->display_configuration_change(
2139 adev
->powerplay
.pp_handle
,
2140 &adev
->pm
.pm_display_cfg
);
2141 mutex_unlock(&adev
->pm
.mutex
);
2143 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
, NULL
);
2145 mutex_lock(&adev
->pm
.mutex
);
2146 amdgpu_dpm_get_active_displays(adev
);
2147 amdgpu_dpm_change_power_state_locked(adev
);
2148 mutex_unlock(&adev
->pm
.mutex
);
2155 #if defined(CONFIG_DEBUG_FS)
2157 static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m
, struct amdgpu_device
*adev
)
2164 /* sanity check PP is enabled */
2165 if (!(adev
->powerplay
.pp_funcs
&&
2166 adev
->powerplay
.pp_funcs
->read_sensor
))
2170 size
= sizeof(value
);
2171 seq_printf(m
, "GFX Clocks and Power:\n");
2172 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
, (void *)&value
, &size
))
2173 seq_printf(m
, "\t%u MHz (MCLK)\n", value
/100);
2174 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
, (void *)&value
, &size
))
2175 seq_printf(m
, "\t%u MHz (SCLK)\n", value
/100);
2176 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK
, (void *)&value
, &size
))
2177 seq_printf(m
, "\t%u MHz (PSTATE_SCLK)\n", value
/100);
2178 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK
, (void *)&value
, &size
))
2179 seq_printf(m
, "\t%u MHz (PSTATE_MCLK)\n", value
/100);
2180 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
, (void *)&value
, &size
))
2181 seq_printf(m
, "\t%u mV (VDDGFX)\n", value
);
2182 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
, (void *)&value
, &size
))
2183 seq_printf(m
, "\t%u mV (VDDNB)\n", value
);
2184 size
= sizeof(uint32_t);
2185 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
, (void *)&query
, &size
))
2186 seq_printf(m
, "\t%u.%u W (average GPU)\n", query
>> 8, query
& 0xff);
2187 size
= sizeof(value
);
2188 seq_printf(m
, "\n");
2191 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
, (void *)&value
, &size
))
2192 seq_printf(m
, "GPU Temperature: %u C\n", value
/1000);
2195 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
, (void *)&value
, &size
))
2196 seq_printf(m
, "GPU Load: %u %%\n", value
);
2197 seq_printf(m
, "\n");
2199 /* SMC feature mask */
2200 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK
, (void *)&value64
, &size
))
2201 seq_printf(m
, "SMC Feature Mask: 0x%016llx\n", value64
);
2204 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_POWER
, (void *)&value
, &size
)) {
2206 seq_printf(m
, "UVD: Disabled\n");
2208 seq_printf(m
, "UVD: Enabled\n");
2209 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
2210 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
2211 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
2212 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
2215 seq_printf(m
, "\n");
2218 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_POWER
, (void *)&value
, &size
)) {
2220 seq_printf(m
, "VCE: Disabled\n");
2222 seq_printf(m
, "VCE: Enabled\n");
2223 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_ECCLK
, (void *)&value
, &size
))
2224 seq_printf(m
, "\t%u MHz (ECCLK)\n", value
/100);
2231 static void amdgpu_parse_cg_state(struct seq_file
*m
, u32 flags
)
2235 for (i
= 0; clocks
[i
].flag
; i
++)
2236 seq_printf(m
, "\t%s: %s\n", clocks
[i
].name
,
2237 (flags
& clocks
[i
].flag
) ? "On" : "Off");
2240 static int amdgpu_debugfs_pm_info(struct seq_file
*m
, void *data
)
2242 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2243 struct drm_device
*dev
= node
->minor
->dev
;
2244 struct amdgpu_device
*adev
= dev
->dev_private
;
2245 struct drm_device
*ddev
= adev
->ddev
;
2248 amdgpu_device_ip_get_clockgating_state(adev
, &flags
);
2249 seq_printf(m
, "Clock Gating Flags Mask: 0x%x\n", flags
);
2250 amdgpu_parse_cg_state(m
, flags
);
2251 seq_printf(m
, "\n");
2253 if (!adev
->pm
.dpm_enabled
) {
2254 seq_printf(m
, "dpm not enabled\n");
2257 if ((adev
->flags
& AMD_IS_PX
) &&
2258 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
2259 seq_printf(m
, "PX asic powered off\n");
2260 } else if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
) {
2261 mutex_lock(&adev
->pm
.mutex
);
2262 if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
)
2263 adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level(adev
, m
);
2265 seq_printf(m
, "Debugfs support not implemented for this asic\n");
2266 mutex_unlock(&adev
->pm
.mutex
);
2268 return amdgpu_debugfs_pm_info_pp(m
, adev
);
2274 static const struct drm_info_list amdgpu_pm_info_list
[] = {
2275 {"amdgpu_pm_info", amdgpu_debugfs_pm_info
, 0, NULL
},
2279 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
)
2281 #if defined(CONFIG_DEBUG_FS)
2282 return amdgpu_debugfs_add_files(adev
, amdgpu_pm_info_list
, ARRAY_SIZE(amdgpu_pm_info_list
));