2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
31 #include <linux/power_supply.h>
32 #include <linux/hwmon.h>
33 #include <linux/hwmon-sysfs.h>
34 #include <linux/nospec.h>
36 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
);
38 static const struct cg_flag_name clocks
[] = {
39 {AMD_CG_SUPPORT_GFX_MGCG
, "Graphics Medium Grain Clock Gating"},
40 {AMD_CG_SUPPORT_GFX_MGLS
, "Graphics Medium Grain memory Light Sleep"},
41 {AMD_CG_SUPPORT_GFX_CGCG
, "Graphics Coarse Grain Clock Gating"},
42 {AMD_CG_SUPPORT_GFX_CGLS
, "Graphics Coarse Grain memory Light Sleep"},
43 {AMD_CG_SUPPORT_GFX_CGTS
, "Graphics Coarse Grain Tree Shader Clock Gating"},
44 {AMD_CG_SUPPORT_GFX_CGTS_LS
, "Graphics Coarse Grain Tree Shader Light Sleep"},
45 {AMD_CG_SUPPORT_GFX_CP_LS
, "Graphics Command Processor Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_RLC_LS
, "Graphics Run List Controller Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_3D_CGCG
, "Graphics 3D Coarse Grain Clock Gating"},
48 {AMD_CG_SUPPORT_GFX_3D_CGLS
, "Graphics 3D Coarse Grain memory Light Sleep"},
49 {AMD_CG_SUPPORT_MC_LS
, "Memory Controller Light Sleep"},
50 {AMD_CG_SUPPORT_MC_MGCG
, "Memory Controller Medium Grain Clock Gating"},
51 {AMD_CG_SUPPORT_SDMA_LS
, "System Direct Memory Access Light Sleep"},
52 {AMD_CG_SUPPORT_SDMA_MGCG
, "System Direct Memory Access Medium Grain Clock Gating"},
53 {AMD_CG_SUPPORT_BIF_MGCG
, "Bus Interface Medium Grain Clock Gating"},
54 {AMD_CG_SUPPORT_BIF_LS
, "Bus Interface Light Sleep"},
55 {AMD_CG_SUPPORT_UVD_MGCG
, "Unified Video Decoder Medium Grain Clock Gating"},
56 {AMD_CG_SUPPORT_VCE_MGCG
, "Video Compression Engine Medium Grain Clock Gating"},
57 {AMD_CG_SUPPORT_HDP_LS
, "Host Data Path Light Sleep"},
58 {AMD_CG_SUPPORT_HDP_MGCG
, "Host Data Path Medium Grain Clock Gating"},
59 {AMD_CG_SUPPORT_DRM_MGCG
, "Digital Right Management Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_DRM_LS
, "Digital Right Management Light Sleep"},
61 {AMD_CG_SUPPORT_ROM_MGCG
, "Rom Medium Grain Clock Gating"},
62 {AMD_CG_SUPPORT_DF_MGCG
, "Data Fabric Medium Grain Clock Gating"},
66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device
*adev
)
68 if (adev
->pm
.dpm_enabled
) {
69 mutex_lock(&adev
->pm
.mutex
);
70 if (power_supply_is_system_supplied() > 0)
71 adev
->pm
.ac_power
= true;
73 adev
->pm
.ac_power
= false;
74 if (adev
->powerplay
.pp_funcs
->enable_bapm
)
75 amdgpu_dpm_enable_bapm(adev
, adev
->pm
.ac_power
);
76 mutex_unlock(&adev
->pm
.mutex
);
81 * DOC: power_dpm_state
83 * The power_dpm_state file is a legacy interface and is only provided for
84 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
85 * certain power related parameters. The file power_dpm_state is used for this.
86 * It accepts the following arguments:
96 * On older GPUs, the vbios provided a special power state for battery
97 * operation. Selecting battery switched to this state. This is no
98 * longer provided on newer GPUs so the option does nothing in that case.
102 * On older GPUs, the vbios provided a special power state for balanced
103 * operation. Selecting balanced switched to this state. This is no
104 * longer provided on newer GPUs so the option does nothing in that case.
108 * On older GPUs, the vbios provided a special power state for performance
109 * operation. Selecting performance switched to this state. This is no
110 * longer provided on newer GPUs so the option does nothing in that case.
114 static ssize_t
amdgpu_get_dpm_state(struct device
*dev
,
115 struct device_attribute
*attr
,
118 struct drm_device
*ddev
= dev_get_drvdata(dev
);
119 struct amdgpu_device
*adev
= ddev
->dev_private
;
120 enum amd_pm_state_type pm
;
122 if (adev
->powerplay
.pp_funcs
->get_current_power_state
)
123 pm
= amdgpu_dpm_get_current_power_state(adev
);
125 pm
= adev
->pm
.dpm
.user_state
;
127 return snprintf(buf
, PAGE_SIZE
, "%s\n",
128 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
129 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
132 static ssize_t
amdgpu_set_dpm_state(struct device
*dev
,
133 struct device_attribute
*attr
,
137 struct drm_device
*ddev
= dev_get_drvdata(dev
);
138 struct amdgpu_device
*adev
= ddev
->dev_private
;
139 enum amd_pm_state_type state
;
141 if (strncmp("battery", buf
, strlen("battery")) == 0)
142 state
= POWER_STATE_TYPE_BATTERY
;
143 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
144 state
= POWER_STATE_TYPE_BALANCED
;
145 else if (strncmp("performance", buf
, strlen("performance")) == 0)
146 state
= POWER_STATE_TYPE_PERFORMANCE
;
152 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
153 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
155 mutex_lock(&adev
->pm
.mutex
);
156 adev
->pm
.dpm
.user_state
= state
;
157 mutex_unlock(&adev
->pm
.mutex
);
159 /* Can't set dpm state when the card is off */
160 if (!(adev
->flags
& AMD_IS_PX
) ||
161 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
162 amdgpu_pm_compute_clocks(adev
);
170 * DOC: power_dpm_force_performance_level
172 * The amdgpu driver provides a sysfs API for adjusting certain power
173 * related parameters. The file power_dpm_force_performance_level is
174 * used for this. It accepts the following arguments:
194 * When auto is selected, the driver will attempt to dynamically select
195 * the optimal power profile for current conditions in the driver.
199 * When low is selected, the clocks are forced to the lowest power state.
203 * When high is selected, the clocks are forced to the highest power state.
207 * When manual is selected, the user can manually adjust which power states
208 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
209 * and pp_dpm_pcie files and adjust the power state transition heuristics
210 * via the pp_power_profile_mode sysfs file.
217 * When the profiling modes are selected, clock and power gating are
218 * disabled and the clocks are set for different profiling cases. This
219 * mode is recommended for profiling specific work loads where you do
220 * not want clock or power gating for clock fluctuation to interfere
221 * with your results. profile_standard sets the clocks to a fixed clock
222 * level which varies from asic to asic. profile_min_sclk forces the sclk
223 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
224 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
228 static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device
*dev
,
229 struct device_attribute
*attr
,
232 struct drm_device
*ddev
= dev_get_drvdata(dev
);
233 struct amdgpu_device
*adev
= ddev
->dev_private
;
234 enum amd_dpm_forced_level level
= 0xff;
236 if ((adev
->flags
& AMD_IS_PX
) &&
237 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
238 return snprintf(buf
, PAGE_SIZE
, "off\n");
240 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
241 level
= amdgpu_dpm_get_performance_level(adev
);
243 level
= adev
->pm
.dpm
.forced_level
;
245 return snprintf(buf
, PAGE_SIZE
, "%s\n",
246 (level
== AMD_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
247 (level
== AMD_DPM_FORCED_LEVEL_LOW
) ? "low" :
248 (level
== AMD_DPM_FORCED_LEVEL_HIGH
) ? "high" :
249 (level
== AMD_DPM_FORCED_LEVEL_MANUAL
) ? "manual" :
250 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
) ? "profile_standard" :
251 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) ? "profile_min_sclk" :
252 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) ? "profile_min_mclk" :
253 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) ? "profile_peak" :
257 static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device
*dev
,
258 struct device_attribute
*attr
,
262 struct drm_device
*ddev
= dev_get_drvdata(dev
);
263 struct amdgpu_device
*adev
= ddev
->dev_private
;
264 enum amd_dpm_forced_level level
;
265 enum amd_dpm_forced_level current_level
= 0xff;
268 /* Can't force performance level when the card is off */
269 if ((adev
->flags
& AMD_IS_PX
) &&
270 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
273 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
274 current_level
= amdgpu_dpm_get_performance_level(adev
);
276 if (strncmp("low", buf
, strlen("low")) == 0) {
277 level
= AMD_DPM_FORCED_LEVEL_LOW
;
278 } else if (strncmp("high", buf
, strlen("high")) == 0) {
279 level
= AMD_DPM_FORCED_LEVEL_HIGH
;
280 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
281 level
= AMD_DPM_FORCED_LEVEL_AUTO
;
282 } else if (strncmp("manual", buf
, strlen("manual")) == 0) {
283 level
= AMD_DPM_FORCED_LEVEL_MANUAL
;
284 } else if (strncmp("profile_exit", buf
, strlen("profile_exit")) == 0) {
285 level
= AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
;
286 } else if (strncmp("profile_standard", buf
, strlen("profile_standard")) == 0) {
287 level
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
;
288 } else if (strncmp("profile_min_sclk", buf
, strlen("profile_min_sclk")) == 0) {
289 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
;
290 } else if (strncmp("profile_min_mclk", buf
, strlen("profile_min_mclk")) == 0) {
291 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
;
292 } else if (strncmp("profile_peak", buf
, strlen("profile_peak")) == 0) {
293 level
= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
299 if (current_level
== level
)
302 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
303 mutex_lock(&adev
->pm
.mutex
);
304 if (adev
->pm
.dpm
.thermal_active
) {
306 mutex_unlock(&adev
->pm
.mutex
);
309 ret
= amdgpu_dpm_force_performance_level(adev
, level
);
313 adev
->pm
.dpm
.forced_level
= level
;
314 mutex_unlock(&adev
->pm
.mutex
);
321 static ssize_t
amdgpu_get_pp_num_states(struct device
*dev
,
322 struct device_attribute
*attr
,
325 struct drm_device
*ddev
= dev_get_drvdata(dev
);
326 struct amdgpu_device
*adev
= ddev
->dev_private
;
327 struct pp_states_info data
;
330 if (adev
->powerplay
.pp_funcs
->get_pp_num_states
)
331 amdgpu_dpm_get_pp_num_states(adev
, &data
);
333 buf_len
= snprintf(buf
, PAGE_SIZE
, "states: %d\n", data
.nums
);
334 for (i
= 0; i
< data
.nums
; i
++)
335 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
, "%d %s\n", i
,
336 (data
.states
[i
] == POWER_STATE_TYPE_INTERNAL_BOOT
) ? "boot" :
337 (data
.states
[i
] == POWER_STATE_TYPE_BATTERY
) ? "battery" :
338 (data
.states
[i
] == POWER_STATE_TYPE_BALANCED
) ? "balanced" :
339 (data
.states
[i
] == POWER_STATE_TYPE_PERFORMANCE
) ? "performance" : "default");
344 static ssize_t
amdgpu_get_pp_cur_state(struct device
*dev
,
345 struct device_attribute
*attr
,
348 struct drm_device
*ddev
= dev_get_drvdata(dev
);
349 struct amdgpu_device
*adev
= ddev
->dev_private
;
350 struct pp_states_info data
;
351 enum amd_pm_state_type pm
= 0;
354 if (adev
->powerplay
.pp_funcs
->get_current_power_state
355 && adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
356 pm
= amdgpu_dpm_get_current_power_state(adev
);
357 amdgpu_dpm_get_pp_num_states(adev
, &data
);
359 for (i
= 0; i
< data
.nums
; i
++) {
360 if (pm
== data
.states
[i
])
368 return snprintf(buf
, PAGE_SIZE
, "%d\n", i
);
371 static ssize_t
amdgpu_get_pp_force_state(struct device
*dev
,
372 struct device_attribute
*attr
,
375 struct drm_device
*ddev
= dev_get_drvdata(dev
);
376 struct amdgpu_device
*adev
= ddev
->dev_private
;
378 if (adev
->pp_force_state_enabled
)
379 return amdgpu_get_pp_cur_state(dev
, attr
, buf
);
381 return snprintf(buf
, PAGE_SIZE
, "\n");
384 static ssize_t
amdgpu_set_pp_force_state(struct device
*dev
,
385 struct device_attribute
*attr
,
389 struct drm_device
*ddev
= dev_get_drvdata(dev
);
390 struct amdgpu_device
*adev
= ddev
->dev_private
;
391 enum amd_pm_state_type state
= 0;
395 if (strlen(buf
) == 1)
396 adev
->pp_force_state_enabled
= false;
397 else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
&&
398 adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
399 struct pp_states_info data
;
401 ret
= kstrtoul(buf
, 0, &idx
);
402 if (ret
|| idx
>= ARRAY_SIZE(data
.states
)) {
406 idx
= array_index_nospec(idx
, ARRAY_SIZE(data
.states
));
408 amdgpu_dpm_get_pp_num_states(adev
, &data
);
409 state
= data
.states
[idx
];
410 /* only set user selected power states */
411 if (state
!= POWER_STATE_TYPE_INTERNAL_BOOT
&&
412 state
!= POWER_STATE_TYPE_DEFAULT
) {
413 amdgpu_dpm_dispatch_task(adev
,
414 AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
415 adev
->pp_force_state_enabled
= true;
425 * The amdgpu driver provides a sysfs API for uploading new powerplay
426 * tables. The file pp_table is used for this. Reading the file
427 * will dump the current power play table. Writing to the file
428 * will attempt to upload a new powerplay table and re-initialize
429 * powerplay using that new table.
433 static ssize_t
amdgpu_get_pp_table(struct device
*dev
,
434 struct device_attribute
*attr
,
437 struct drm_device
*ddev
= dev_get_drvdata(dev
);
438 struct amdgpu_device
*adev
= ddev
->dev_private
;
442 if (adev
->powerplay
.pp_funcs
->get_pp_table
)
443 size
= amdgpu_dpm_get_pp_table(adev
, &table
);
447 if (size
>= PAGE_SIZE
)
448 size
= PAGE_SIZE
- 1;
450 memcpy(buf
, table
, size
);
455 static ssize_t
amdgpu_set_pp_table(struct device
*dev
,
456 struct device_attribute
*attr
,
460 struct drm_device
*ddev
= dev_get_drvdata(dev
);
461 struct amdgpu_device
*adev
= ddev
->dev_private
;
463 if (adev
->powerplay
.pp_funcs
->set_pp_table
)
464 amdgpu_dpm_set_pp_table(adev
, buf
, count
);
470 * DOC: pp_od_clk_voltage
472 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
473 * in each power level within a power state. The pp_od_clk_voltage is used for
476 * Reading the file will display:
478 * - a list of engine clock levels and voltages labeled OD_SCLK
480 * - a list of memory clock levels and voltages labeled OD_MCLK
482 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
484 * To manually adjust these settings, first select manual using
485 * power_dpm_force_performance_level. Enter a new value for each
486 * level by writing a string that contains "s/m level clock voltage" to
487 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
488 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
489 * 810 mV. When you have edited all of the states as needed, write
490 * "c" (commit) to the file to commit your changes. If you want to reset to the
491 * default power levels, write "r" (reset) to the file to reset them.
495 static ssize_t
amdgpu_set_pp_od_clk_voltage(struct device
*dev
,
496 struct device_attribute
*attr
,
500 struct drm_device
*ddev
= dev_get_drvdata(dev
);
501 struct amdgpu_device
*adev
= ddev
->dev_private
;
503 uint32_t parameter_size
= 0;
508 const char delimiter
[3] = {' ', '\n', '\0'};
515 type
= PP_OD_EDIT_SCLK_VDDC_TABLE
;
516 else if (*buf
== 'm')
517 type
= PP_OD_EDIT_MCLK_VDDC_TABLE
;
519 type
= PP_OD_RESTORE_DEFAULT_TABLE
;
520 else if (*buf
== 'c')
521 type
= PP_OD_COMMIT_DPM_TABLE
;
525 memcpy(buf_cpy
, buf
, count
+1);
529 while (isspace(*++tmp_str
));
532 sub_str
= strsep(&tmp_str
, delimiter
);
533 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
538 while (isspace(*tmp_str
))
542 if (adev
->powerplay
.pp_funcs
->odn_edit_dpm_table
)
543 ret
= amdgpu_dpm_odn_edit_dpm_table(adev
, type
,
544 parameter
, parameter_size
);
549 if (type
== PP_OD_COMMIT_DPM_TABLE
) {
550 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
551 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
561 static ssize_t
amdgpu_get_pp_od_clk_voltage(struct device
*dev
,
562 struct device_attribute
*attr
,
565 struct drm_device
*ddev
= dev_get_drvdata(dev
);
566 struct amdgpu_device
*adev
= ddev
->dev_private
;
569 if (adev
->powerplay
.pp_funcs
->print_clock_levels
) {
570 size
= amdgpu_dpm_print_clock_levels(adev
, OD_SCLK
, buf
);
571 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_MCLK
, buf
+size
);
572 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_RANGE
, buf
+size
);
575 return snprintf(buf
, PAGE_SIZE
, "\n");
581 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
583 * The amdgpu driver provides a sysfs API for adjusting what power levels
584 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
585 * and pp_dpm_pcie are used for this.
587 * Reading back the files will show you the available power levels within
588 * the power state and the clock information for those levels.
590 * To manually adjust these states, first select manual using
591 * power_dpm_force_performance_level.
592 * Secondly,Enter a new value for each level by inputing a string that
593 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
594 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
597 static ssize_t
amdgpu_get_pp_dpm_sclk(struct device
*dev
,
598 struct device_attribute
*attr
,
601 struct drm_device
*ddev
= dev_get_drvdata(dev
);
602 struct amdgpu_device
*adev
= ddev
->dev_private
;
604 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
605 return amdgpu_dpm_print_clock_levels(adev
, PP_SCLK
, buf
);
607 return snprintf(buf
, PAGE_SIZE
, "\n");
611 * Worst case: 32 bits individually specified, in octal at 12 characters
612 * per line (+1 for \n).
614 #define AMDGPU_MASK_BUF_MAX (32 * 13)
616 static ssize_t
amdgpu_read_mask(const char *buf
, size_t count
, uint32_t *mask
)
620 char *sub_str
= NULL
;
622 char buf_cpy
[AMDGPU_MASK_BUF_MAX
+ 1];
623 const char delimiter
[3] = {' ', '\n', '\0'};
628 bytes
= min(count
, sizeof(buf_cpy
) - 1);
629 memcpy(buf_cpy
, buf
, bytes
);
630 buf_cpy
[bytes
] = '\0';
633 sub_str
= strsep(&tmp
, delimiter
);
634 if (strlen(sub_str
)) {
635 ret
= kstrtol(sub_str
, 0, &level
);
646 static ssize_t
amdgpu_set_pp_dpm_sclk(struct device
*dev
,
647 struct device_attribute
*attr
,
651 struct drm_device
*ddev
= dev_get_drvdata(dev
);
652 struct amdgpu_device
*adev
= ddev
->dev_private
;
656 ret
= amdgpu_read_mask(buf
, count
, &mask
);
660 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
661 amdgpu_dpm_force_clock_level(adev
, PP_SCLK
, mask
);
666 static ssize_t
amdgpu_get_pp_dpm_mclk(struct device
*dev
,
667 struct device_attribute
*attr
,
670 struct drm_device
*ddev
= dev_get_drvdata(dev
);
671 struct amdgpu_device
*adev
= ddev
->dev_private
;
673 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
674 return amdgpu_dpm_print_clock_levels(adev
, PP_MCLK
, buf
);
676 return snprintf(buf
, PAGE_SIZE
, "\n");
679 static ssize_t
amdgpu_set_pp_dpm_mclk(struct device
*dev
,
680 struct device_attribute
*attr
,
684 struct drm_device
*ddev
= dev_get_drvdata(dev
);
685 struct amdgpu_device
*adev
= ddev
->dev_private
;
689 ret
= amdgpu_read_mask(buf
, count
, &mask
);
693 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
694 amdgpu_dpm_force_clock_level(adev
, PP_MCLK
, mask
);
699 static ssize_t
amdgpu_get_pp_dpm_pcie(struct device
*dev
,
700 struct device_attribute
*attr
,
703 struct drm_device
*ddev
= dev_get_drvdata(dev
);
704 struct amdgpu_device
*adev
= ddev
->dev_private
;
706 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
707 return amdgpu_dpm_print_clock_levels(adev
, PP_PCIE
, buf
);
709 return snprintf(buf
, PAGE_SIZE
, "\n");
712 static ssize_t
amdgpu_set_pp_dpm_pcie(struct device
*dev
,
713 struct device_attribute
*attr
,
717 struct drm_device
*ddev
= dev_get_drvdata(dev
);
718 struct amdgpu_device
*adev
= ddev
->dev_private
;
722 ret
= amdgpu_read_mask(buf
, count
, &mask
);
726 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
727 amdgpu_dpm_force_clock_level(adev
, PP_PCIE
, mask
);
732 static ssize_t
amdgpu_get_pp_sclk_od(struct device
*dev
,
733 struct device_attribute
*attr
,
736 struct drm_device
*ddev
= dev_get_drvdata(dev
);
737 struct amdgpu_device
*adev
= ddev
->dev_private
;
740 if (adev
->powerplay
.pp_funcs
->get_sclk_od
)
741 value
= amdgpu_dpm_get_sclk_od(adev
);
743 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
746 static ssize_t
amdgpu_set_pp_sclk_od(struct device
*dev
,
747 struct device_attribute
*attr
,
751 struct drm_device
*ddev
= dev_get_drvdata(dev
);
752 struct amdgpu_device
*adev
= ddev
->dev_private
;
756 ret
= kstrtol(buf
, 0, &value
);
762 if (adev
->powerplay
.pp_funcs
->set_sclk_od
)
763 amdgpu_dpm_set_sclk_od(adev
, (uint32_t)value
);
765 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
766 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
768 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
769 amdgpu_pm_compute_clocks(adev
);
776 static ssize_t
amdgpu_get_pp_mclk_od(struct device
*dev
,
777 struct device_attribute
*attr
,
780 struct drm_device
*ddev
= dev_get_drvdata(dev
);
781 struct amdgpu_device
*adev
= ddev
->dev_private
;
784 if (adev
->powerplay
.pp_funcs
->get_mclk_od
)
785 value
= amdgpu_dpm_get_mclk_od(adev
);
787 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
790 static ssize_t
amdgpu_set_pp_mclk_od(struct device
*dev
,
791 struct device_attribute
*attr
,
795 struct drm_device
*ddev
= dev_get_drvdata(dev
);
796 struct amdgpu_device
*adev
= ddev
->dev_private
;
800 ret
= kstrtol(buf
, 0, &value
);
806 if (adev
->powerplay
.pp_funcs
->set_mclk_od
)
807 amdgpu_dpm_set_mclk_od(adev
, (uint32_t)value
);
809 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
810 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
812 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
813 amdgpu_pm_compute_clocks(adev
);
821 * DOC: pp_power_profile_mode
823 * The amdgpu driver provides a sysfs API for adjusting the heuristics
824 * related to switching between power levels in a power state. The file
825 * pp_power_profile_mode is used for this.
827 * Reading this file outputs a list of all of the predefined power profiles
828 * and the relevant heuristics settings for that profile.
830 * To select a profile or create a custom profile, first select manual using
831 * power_dpm_force_performance_level. Writing the number of a predefined
832 * profile to pp_power_profile_mode will enable those heuristics. To
833 * create a custom set of heuristics, write a string of numbers to the file
834 * starting with the number of the custom profile along with a setting
835 * for each heuristic parameter. Due to differences across asic families
836 * the heuristic parameters vary from family to family.
840 static ssize_t
amdgpu_get_pp_power_profile_mode(struct device
*dev
,
841 struct device_attribute
*attr
,
844 struct drm_device
*ddev
= dev_get_drvdata(dev
);
845 struct amdgpu_device
*adev
= ddev
->dev_private
;
847 if (adev
->powerplay
.pp_funcs
->get_power_profile_mode
)
848 return amdgpu_dpm_get_power_profile_mode(adev
, buf
);
850 return snprintf(buf
, PAGE_SIZE
, "\n");
854 static ssize_t
amdgpu_set_pp_power_profile_mode(struct device
*dev
,
855 struct device_attribute
*attr
,
860 struct drm_device
*ddev
= dev_get_drvdata(dev
);
861 struct amdgpu_device
*adev
= ddev
->dev_private
;
862 uint32_t parameter_size
= 0;
864 char *sub_str
, buf_cpy
[128];
868 long int profile_mode
= 0;
869 const char delimiter
[3] = {' ', '\n', '\0'};
873 ret
= kstrtol(tmp
, 0, &profile_mode
);
877 if (profile_mode
== PP_SMC_POWER_PROFILE_CUSTOM
) {
878 if (count
< 2 || count
> 127)
880 while (isspace(*++buf
))
882 memcpy(buf_cpy
, buf
, count
-i
);
885 sub_str
= strsep(&tmp_str
, delimiter
);
886 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
892 while (isspace(*tmp_str
))
896 parameter
[parameter_size
] = profile_mode
;
897 if (adev
->powerplay
.pp_funcs
->set_power_profile_mode
)
898 ret
= amdgpu_dpm_set_power_profile_mode(adev
, parameter
, parameter_size
);
909 * The amdgpu driver provides a sysfs API for reading how busy the GPU
910 * is as a percentage. The file gpu_busy_percent is used for this.
911 * The SMU firmware computes a percentage of load based on the
912 * aggregate activity level in the IP cores.
914 static ssize_t
amdgpu_get_busy_percent(struct device
*dev
,
915 struct device_attribute
*attr
,
918 struct drm_device
*ddev
= dev_get_drvdata(dev
);
919 struct amdgpu_device
*adev
= ddev
->dev_private
;
920 int r
, value
, size
= sizeof(value
);
922 /* sanity check PP is enabled */
923 if (!(adev
->powerplay
.pp_funcs
&&
924 adev
->powerplay
.pp_funcs
->read_sensor
))
927 /* read the IP busy sensor */
928 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
,
929 (void *)&value
, &size
);
933 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
936 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, amdgpu_get_dpm_state
, amdgpu_set_dpm_state
);
937 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
938 amdgpu_get_dpm_forced_performance_level
,
939 amdgpu_set_dpm_forced_performance_level
);
940 static DEVICE_ATTR(pp_num_states
, S_IRUGO
, amdgpu_get_pp_num_states
, NULL
);
941 static DEVICE_ATTR(pp_cur_state
, S_IRUGO
, amdgpu_get_pp_cur_state
, NULL
);
942 static DEVICE_ATTR(pp_force_state
, S_IRUGO
| S_IWUSR
,
943 amdgpu_get_pp_force_state
,
944 amdgpu_set_pp_force_state
);
945 static DEVICE_ATTR(pp_table
, S_IRUGO
| S_IWUSR
,
947 amdgpu_set_pp_table
);
948 static DEVICE_ATTR(pp_dpm_sclk
, S_IRUGO
| S_IWUSR
,
949 amdgpu_get_pp_dpm_sclk
,
950 amdgpu_set_pp_dpm_sclk
);
951 static DEVICE_ATTR(pp_dpm_mclk
, S_IRUGO
| S_IWUSR
,
952 amdgpu_get_pp_dpm_mclk
,
953 amdgpu_set_pp_dpm_mclk
);
954 static DEVICE_ATTR(pp_dpm_pcie
, S_IRUGO
| S_IWUSR
,
955 amdgpu_get_pp_dpm_pcie
,
956 amdgpu_set_pp_dpm_pcie
);
957 static DEVICE_ATTR(pp_sclk_od
, S_IRUGO
| S_IWUSR
,
958 amdgpu_get_pp_sclk_od
,
959 amdgpu_set_pp_sclk_od
);
960 static DEVICE_ATTR(pp_mclk_od
, S_IRUGO
| S_IWUSR
,
961 amdgpu_get_pp_mclk_od
,
962 amdgpu_set_pp_mclk_od
);
963 static DEVICE_ATTR(pp_power_profile_mode
, S_IRUGO
| S_IWUSR
,
964 amdgpu_get_pp_power_profile_mode
,
965 amdgpu_set_pp_power_profile_mode
);
966 static DEVICE_ATTR(pp_od_clk_voltage
, S_IRUGO
| S_IWUSR
,
967 amdgpu_get_pp_od_clk_voltage
,
968 amdgpu_set_pp_od_clk_voltage
);
969 static DEVICE_ATTR(gpu_busy_percent
, S_IRUGO
,
970 amdgpu_get_busy_percent
, NULL
);
972 static ssize_t
amdgpu_hwmon_show_temp(struct device
*dev
,
973 struct device_attribute
*attr
,
976 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
977 struct drm_device
*ddev
= adev
->ddev
;
978 int r
, temp
, size
= sizeof(temp
);
980 /* Can't get temperature when the card is off */
981 if ((adev
->flags
& AMD_IS_PX
) &&
982 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
985 /* sanity check PP is enabled */
986 if (!(adev
->powerplay
.pp_funcs
&&
987 adev
->powerplay
.pp_funcs
->read_sensor
))
990 /* get the temperature */
991 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
992 (void *)&temp
, &size
);
996 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
999 static ssize_t
amdgpu_hwmon_show_temp_thresh(struct device
*dev
,
1000 struct device_attribute
*attr
,
1003 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1004 int hyst
= to_sensor_dev_attr(attr
)->index
;
1008 temp
= adev
->pm
.dpm
.thermal
.min_temp
;
1010 temp
= adev
->pm
.dpm
.thermal
.max_temp
;
1012 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1015 static ssize_t
amdgpu_hwmon_get_pwm1_enable(struct device
*dev
,
1016 struct device_attribute
*attr
,
1019 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1022 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1025 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1027 return sprintf(buf
, "%i\n", pwm_mode
);
1030 static ssize_t
amdgpu_hwmon_set_pwm1_enable(struct device
*dev
,
1031 struct device_attribute
*attr
,
1035 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1039 /* Can't adjust fan when the card is off */
1040 if ((adev
->flags
& AMD_IS_PX
) &&
1041 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1044 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1047 err
= kstrtoint(buf
, 10, &value
);
1051 amdgpu_dpm_set_fan_control_mode(adev
, value
);
1056 static ssize_t
amdgpu_hwmon_get_pwm1_min(struct device
*dev
,
1057 struct device_attribute
*attr
,
1060 return sprintf(buf
, "%i\n", 0);
1063 static ssize_t
amdgpu_hwmon_get_pwm1_max(struct device
*dev
,
1064 struct device_attribute
*attr
,
1067 return sprintf(buf
, "%i\n", 255);
1070 static ssize_t
amdgpu_hwmon_set_pwm1(struct device
*dev
,
1071 struct device_attribute
*attr
,
1072 const char *buf
, size_t count
)
1074 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1078 /* Can't adjust fan when the card is off */
1079 if ((adev
->flags
& AMD_IS_PX
) &&
1080 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1083 err
= kstrtou32(buf
, 10, &value
);
1087 value
= (value
* 100) / 255;
1089 if (adev
->powerplay
.pp_funcs
->set_fan_speed_percent
) {
1090 err
= amdgpu_dpm_set_fan_speed_percent(adev
, value
);
1098 static ssize_t
amdgpu_hwmon_get_pwm1(struct device
*dev
,
1099 struct device_attribute
*attr
,
1102 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1106 /* Can't adjust fan when the card is off */
1107 if ((adev
->flags
& AMD_IS_PX
) &&
1108 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1111 if (adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) {
1112 err
= amdgpu_dpm_get_fan_speed_percent(adev
, &speed
);
1117 speed
= (speed
* 255) / 100;
1119 return sprintf(buf
, "%i\n", speed
);
1122 static ssize_t
amdgpu_hwmon_get_fan1_input(struct device
*dev
,
1123 struct device_attribute
*attr
,
1126 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1130 /* Can't adjust fan when the card is off */
1131 if ((adev
->flags
& AMD_IS_PX
) &&
1132 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1135 if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1136 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &speed
);
1141 return sprintf(buf
, "%i\n", speed
);
1144 static ssize_t
amdgpu_hwmon_show_vddgfx(struct device
*dev
,
1145 struct device_attribute
*attr
,
1148 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1149 struct drm_device
*ddev
= adev
->ddev
;
1151 int r
, size
= sizeof(vddgfx
);
1153 /* Can't get voltage when the card is off */
1154 if ((adev
->flags
& AMD_IS_PX
) &&
1155 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1158 /* sanity check PP is enabled */
1159 if (!(adev
->powerplay
.pp_funcs
&&
1160 adev
->powerplay
.pp_funcs
->read_sensor
))
1163 /* get the voltage */
1164 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
,
1165 (void *)&vddgfx
, &size
);
1169 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddgfx
);
1172 static ssize_t
amdgpu_hwmon_show_vddgfx_label(struct device
*dev
,
1173 struct device_attribute
*attr
,
1176 return snprintf(buf
, PAGE_SIZE
, "vddgfx\n");
1179 static ssize_t
amdgpu_hwmon_show_vddnb(struct device
*dev
,
1180 struct device_attribute
*attr
,
1183 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1184 struct drm_device
*ddev
= adev
->ddev
;
1186 int r
, size
= sizeof(vddnb
);
1188 /* only APUs have vddnb */
1189 if (!(adev
->flags
& AMD_IS_APU
))
1192 /* Can't get voltage when the card is off */
1193 if ((adev
->flags
& AMD_IS_PX
) &&
1194 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1197 /* sanity check PP is enabled */
1198 if (!(adev
->powerplay
.pp_funcs
&&
1199 adev
->powerplay
.pp_funcs
->read_sensor
))
1202 /* get the voltage */
1203 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
,
1204 (void *)&vddnb
, &size
);
1208 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddnb
);
1211 static ssize_t
amdgpu_hwmon_show_vddnb_label(struct device
*dev
,
1212 struct device_attribute
*attr
,
1215 return snprintf(buf
, PAGE_SIZE
, "vddnb\n");
1218 static ssize_t
amdgpu_hwmon_show_power_avg(struct device
*dev
,
1219 struct device_attribute
*attr
,
1222 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1223 struct drm_device
*ddev
= adev
->ddev
;
1225 int r
, size
= sizeof(u32
);
1228 /* Can't get power when the card is off */
1229 if ((adev
->flags
& AMD_IS_PX
) &&
1230 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1233 /* sanity check PP is enabled */
1234 if (!(adev
->powerplay
.pp_funcs
&&
1235 adev
->powerplay
.pp_funcs
->read_sensor
))
1238 /* get the voltage */
1239 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
,
1240 (void *)&query
, &size
);
1244 /* convert to microwatts */
1245 uw
= (query
>> 8) * 1000000 + (query
& 0xff) * 1000;
1247 return snprintf(buf
, PAGE_SIZE
, "%u\n", uw
);
1250 static ssize_t
amdgpu_hwmon_show_power_cap_min(struct device
*dev
,
1251 struct device_attribute
*attr
,
1254 return sprintf(buf
, "%i\n", 0);
1257 static ssize_t
amdgpu_hwmon_show_power_cap_max(struct device
*dev
,
1258 struct device_attribute
*attr
,
1261 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1264 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1265 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, true);
1266 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1268 return snprintf(buf
, PAGE_SIZE
, "\n");
1272 static ssize_t
amdgpu_hwmon_show_power_cap(struct device
*dev
,
1273 struct device_attribute
*attr
,
1276 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1279 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1280 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, false);
1281 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1283 return snprintf(buf
, PAGE_SIZE
, "\n");
1288 static ssize_t
amdgpu_hwmon_set_power_cap(struct device
*dev
,
1289 struct device_attribute
*attr
,
1293 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1297 err
= kstrtou32(buf
, 10, &value
);
1301 value
= value
/ 1000000; /* convert to Watt */
1302 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->set_power_limit
) {
1303 err
= adev
->powerplay
.pp_funcs
->set_power_limit(adev
->powerplay
.pp_handle
, value
);
1317 * The amdgpu driver exposes the following sensor interfaces:
1319 * - GPU temperature (via the on-die sensor)
1323 * - Northbridge voltage (APUs only)
1329 * hwmon interfaces for GPU temperature:
1331 * - temp1_input: the on die GPU temperature in millidegrees Celsius
1333 * - temp1_crit: temperature critical max value in millidegrees Celsius
1335 * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1337 * hwmon interfaces for GPU voltage:
1339 * - in0_input: the voltage on the GPU in millivolts
1341 * - in1_input: the voltage on the Northbridge in millivolts
1343 * hwmon interfaces for GPU power:
1345 * - power1_average: average power used by the GPU in microWatts
1347 * - power1_cap_min: minimum cap supported in microWatts
1349 * - power1_cap_max: maximum cap supported in microWatts
1351 * - power1_cap: selected power cap in microWatts
1353 * hwmon interfaces for GPU fan:
1355 * - pwm1: pulse width modulation fan level (0-255)
1357 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1359 * - pwm1_min: pulse width modulation fan control minimum level (0)
1361 * - pwm1_max: pulse width modulation fan control maximum level (255)
1363 * - fan1_input: fan speed in RPM
1365 * You can use hwmon tools like sensors to view this information on your system.
1369 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, 0);
1370 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 0);
1371 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 1);
1372 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1
, amdgpu_hwmon_set_pwm1
, 0);
1373 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1_enable
, amdgpu_hwmon_set_pwm1_enable
, 0);
1374 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, amdgpu_hwmon_get_pwm1_min
, NULL
, 0);
1375 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, amdgpu_hwmon_get_pwm1_max
, NULL
, 0);
1376 static SENSOR_DEVICE_ATTR(fan1_input
, S_IRUGO
, amdgpu_hwmon_get_fan1_input
, NULL
, 0);
1377 static SENSOR_DEVICE_ATTR(in0_input
, S_IRUGO
, amdgpu_hwmon_show_vddgfx
, NULL
, 0);
1378 static SENSOR_DEVICE_ATTR(in0_label
, S_IRUGO
, amdgpu_hwmon_show_vddgfx_label
, NULL
, 0);
1379 static SENSOR_DEVICE_ATTR(in1_input
, S_IRUGO
, amdgpu_hwmon_show_vddnb
, NULL
, 0);
1380 static SENSOR_DEVICE_ATTR(in1_label
, S_IRUGO
, amdgpu_hwmon_show_vddnb_label
, NULL
, 0);
1381 static SENSOR_DEVICE_ATTR(power1_average
, S_IRUGO
, amdgpu_hwmon_show_power_avg
, NULL
, 0);
1382 static SENSOR_DEVICE_ATTR(power1_cap_max
, S_IRUGO
, amdgpu_hwmon_show_power_cap_max
, NULL
, 0);
1383 static SENSOR_DEVICE_ATTR(power1_cap_min
, S_IRUGO
, amdgpu_hwmon_show_power_cap_min
, NULL
, 0);
1384 static SENSOR_DEVICE_ATTR(power1_cap
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_show_power_cap
, amdgpu_hwmon_set_power_cap
, 0);
1386 static struct attribute
*hwmon_attributes
[] = {
1387 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
1388 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
1389 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
1390 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
1391 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
1392 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
1393 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
1394 &sensor_dev_attr_fan1_input
.dev_attr
.attr
,
1395 &sensor_dev_attr_in0_input
.dev_attr
.attr
,
1396 &sensor_dev_attr_in0_label
.dev_attr
.attr
,
1397 &sensor_dev_attr_in1_input
.dev_attr
.attr
,
1398 &sensor_dev_attr_in1_label
.dev_attr
.attr
,
1399 &sensor_dev_attr_power1_average
.dev_attr
.attr
,
1400 &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
,
1401 &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
,
1402 &sensor_dev_attr_power1_cap
.dev_attr
.attr
,
1406 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
1407 struct attribute
*attr
, int index
)
1409 struct device
*dev
= kobj_to_dev(kobj
);
1410 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1411 umode_t effective_mode
= attr
->mode
;
1414 /* Skip fan attributes if fan is not present */
1415 if (adev
->pm
.no_fan
&& (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
1416 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
1417 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1418 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
1419 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
))
1422 /* Skip limit attributes if DPM is not enabled */
1423 if (!adev
->pm
.dpm_enabled
&&
1424 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
1425 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
1426 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
1427 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
1428 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1429 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
1432 /* mask fan attributes if we have no bindings for this asic to expose */
1433 if ((!adev
->powerplay
.pp_funcs
->get_fan_speed_percent
&&
1434 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
1435 (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
&&
1436 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
1437 effective_mode
&= ~S_IRUGO
;
1439 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
1440 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
1441 (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
&&
1442 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
1443 effective_mode
&= ~S_IWUSR
;
1445 if ((adev
->flags
& AMD_IS_APU
) &&
1446 (attr
== &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
||
1447 attr
== &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
||
1448 attr
== &sensor_dev_attr_power1_cap
.dev_attr
.attr
))
1451 /* hide max/min values if we can't both query and manage the fan */
1452 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
1453 !adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) &&
1454 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1455 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
1458 /* only APUs have vddnb */
1459 if (!(adev
->flags
& AMD_IS_APU
) &&
1460 (attr
== &sensor_dev_attr_in1_input
.dev_attr
.attr
||
1461 attr
== &sensor_dev_attr_in1_label
.dev_attr
.attr
))
1464 return effective_mode
;
1467 static const struct attribute_group hwmon_attrgroup
= {
1468 .attrs
= hwmon_attributes
,
1469 .is_visible
= hwmon_attributes_visible
,
1472 static const struct attribute_group
*hwmon_groups
[] = {
1477 void amdgpu_dpm_thermal_work_handler(struct work_struct
*work
)
1479 struct amdgpu_device
*adev
=
1480 container_of(work
, struct amdgpu_device
,
1481 pm
.dpm
.thermal
.work
);
1482 /* switch to the thermal state */
1483 enum amd_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
1484 int temp
, size
= sizeof(temp
);
1486 if (!adev
->pm
.dpm_enabled
)
1489 if (adev
->powerplay
.pp_funcs
&&
1490 adev
->powerplay
.pp_funcs
->read_sensor
&&
1491 !amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
1492 (void *)&temp
, &size
)) {
1493 if (temp
< adev
->pm
.dpm
.thermal
.min_temp
)
1494 /* switch back the user state */
1495 dpm_state
= adev
->pm
.dpm
.user_state
;
1497 if (adev
->pm
.dpm
.thermal
.high_to_low
)
1498 /* switch back the user state */
1499 dpm_state
= adev
->pm
.dpm
.user_state
;
1501 mutex_lock(&adev
->pm
.mutex
);
1502 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
1503 adev
->pm
.dpm
.thermal_active
= true;
1505 adev
->pm
.dpm
.thermal_active
= false;
1506 adev
->pm
.dpm
.state
= dpm_state
;
1507 mutex_unlock(&adev
->pm
.mutex
);
1509 amdgpu_pm_compute_clocks(adev
);
1512 static struct amdgpu_ps
*amdgpu_dpm_pick_power_state(struct amdgpu_device
*adev
,
1513 enum amd_pm_state_type dpm_state
)
1516 struct amdgpu_ps
*ps
;
1518 bool single_display
= (adev
->pm
.dpm
.new_active_crtc_count
< 2) ?
1521 /* check if the vblank period is too short to adjust the mclk */
1522 if (single_display
&& adev
->powerplay
.pp_funcs
->vblank_too_short
) {
1523 if (amdgpu_dpm_vblank_too_short(adev
))
1524 single_display
= false;
1527 /* certain older asics have a separare 3D performance state,
1528 * so try that first if the user selected performance
1530 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
1531 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
1532 /* balanced states don't exist at the moment */
1533 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
1534 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1537 /* Pick the best power state based on current conditions */
1538 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
1539 ps
= &adev
->pm
.dpm
.ps
[i
];
1540 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
1541 switch (dpm_state
) {
1543 case POWER_STATE_TYPE_BATTERY
:
1544 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
1545 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1552 case POWER_STATE_TYPE_BALANCED
:
1553 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
1554 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1561 case POWER_STATE_TYPE_PERFORMANCE
:
1562 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
1563 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1570 /* internal states */
1571 case POWER_STATE_TYPE_INTERNAL_UVD
:
1572 if (adev
->pm
.dpm
.uvd_ps
)
1573 return adev
->pm
.dpm
.uvd_ps
;
1576 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1577 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
1580 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1581 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
1584 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1585 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
1588 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1589 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
1592 case POWER_STATE_TYPE_INTERNAL_BOOT
:
1593 return adev
->pm
.dpm
.boot_ps
;
1594 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1595 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
1598 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1599 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
1602 case POWER_STATE_TYPE_INTERNAL_ULV
:
1603 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
1606 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1607 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
1614 /* use a fallback state if we didn't match */
1615 switch (dpm_state
) {
1616 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1617 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
1618 goto restart_search
;
1619 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1620 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1621 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1622 if (adev
->pm
.dpm
.uvd_ps
) {
1623 return adev
->pm
.dpm
.uvd_ps
;
1625 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1626 goto restart_search
;
1628 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1629 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
1630 goto restart_search
;
1631 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1632 dpm_state
= POWER_STATE_TYPE_BATTERY
;
1633 goto restart_search
;
1634 case POWER_STATE_TYPE_BATTERY
:
1635 case POWER_STATE_TYPE_BALANCED
:
1636 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1637 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1638 goto restart_search
;
1646 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device
*adev
)
1648 struct amdgpu_ps
*ps
;
1649 enum amd_pm_state_type dpm_state
;
1653 /* if dpm init failed */
1654 if (!adev
->pm
.dpm_enabled
)
1657 if (adev
->pm
.dpm
.user_state
!= adev
->pm
.dpm
.state
) {
1658 /* add other state override checks here */
1659 if ((!adev
->pm
.dpm
.thermal_active
) &&
1660 (!adev
->pm
.dpm
.uvd_active
))
1661 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.user_state
;
1663 dpm_state
= adev
->pm
.dpm
.state
;
1665 ps
= amdgpu_dpm_pick_power_state(adev
, dpm_state
);
1667 adev
->pm
.dpm
.requested_ps
= ps
;
1671 if (amdgpu_dpm
== 1 && adev
->powerplay
.pp_funcs
->print_power_state
) {
1672 printk("switching from power state:\n");
1673 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.current_ps
);
1674 printk("switching to power state:\n");
1675 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.requested_ps
);
1678 /* update whether vce is active */
1679 ps
->vce_active
= adev
->pm
.dpm
.vce_active
;
1680 if (adev
->powerplay
.pp_funcs
->display_configuration_changed
)
1681 amdgpu_dpm_display_configuration_changed(adev
);
1683 ret
= amdgpu_dpm_pre_set_power_state(adev
);
1687 if (adev
->powerplay
.pp_funcs
->check_state_equal
) {
1688 if (0 != amdgpu_dpm_check_state_equal(adev
, adev
->pm
.dpm
.current_ps
, adev
->pm
.dpm
.requested_ps
, &equal
))
1695 amdgpu_dpm_set_power_state(adev
);
1696 amdgpu_dpm_post_set_power_state(adev
);
1698 adev
->pm
.dpm
.current_active_crtcs
= adev
->pm
.dpm
.new_active_crtcs
;
1699 adev
->pm
.dpm
.current_active_crtc_count
= adev
->pm
.dpm
.new_active_crtc_count
;
1701 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
1702 if (adev
->pm
.dpm
.thermal_active
) {
1703 enum amd_dpm_forced_level level
= adev
->pm
.dpm
.forced_level
;
1704 /* force low perf level for thermal */
1705 amdgpu_dpm_force_performance_level(adev
, AMD_DPM_FORCED_LEVEL_LOW
);
1706 /* save the user's level */
1707 adev
->pm
.dpm
.forced_level
= level
;
1709 /* otherwise, user selected level */
1710 amdgpu_dpm_force_performance_level(adev
, adev
->pm
.dpm
.forced_level
);
1715 void amdgpu_dpm_enable_uvd(struct amdgpu_device
*adev
, bool enable
)
1717 if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
1718 /* enable/disable UVD */
1719 mutex_lock(&adev
->pm
.mutex
);
1720 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_UVD
, !enable
);
1721 mutex_unlock(&adev
->pm
.mutex
);
1724 mutex_lock(&adev
->pm
.mutex
);
1725 adev
->pm
.dpm
.uvd_active
= true;
1726 adev
->pm
.dpm
.state
= POWER_STATE_TYPE_INTERNAL_UVD
;
1727 mutex_unlock(&adev
->pm
.mutex
);
1729 mutex_lock(&adev
->pm
.mutex
);
1730 adev
->pm
.dpm
.uvd_active
= false;
1731 mutex_unlock(&adev
->pm
.mutex
);
1733 amdgpu_pm_compute_clocks(adev
);
1737 void amdgpu_dpm_enable_vce(struct amdgpu_device
*adev
, bool enable
)
1739 if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
1740 /* enable/disable VCE */
1741 mutex_lock(&adev
->pm
.mutex
);
1742 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_VCE
, !enable
);
1743 mutex_unlock(&adev
->pm
.mutex
);
1746 mutex_lock(&adev
->pm
.mutex
);
1747 adev
->pm
.dpm
.vce_active
= true;
1748 /* XXX select vce level based on ring/task */
1749 adev
->pm
.dpm
.vce_level
= AMD_VCE_LEVEL_AC_ALL
;
1750 mutex_unlock(&adev
->pm
.mutex
);
1751 amdgpu_device_ip_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1752 AMD_CG_STATE_UNGATE
);
1753 amdgpu_device_ip_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1754 AMD_PG_STATE_UNGATE
);
1755 amdgpu_pm_compute_clocks(adev
);
1757 amdgpu_device_ip_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1759 amdgpu_device_ip_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1761 mutex_lock(&adev
->pm
.mutex
);
1762 adev
->pm
.dpm
.vce_active
= false;
1763 mutex_unlock(&adev
->pm
.mutex
);
1764 amdgpu_pm_compute_clocks(adev
);
1770 void amdgpu_pm_print_power_states(struct amdgpu_device
*adev
)
1774 if (adev
->powerplay
.pp_funcs
->print_power_state
== NULL
)
1777 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++)
1778 amdgpu_dpm_print_power_state(adev
, &adev
->pm
.dpm
.ps
[i
]);
1782 int amdgpu_pm_sysfs_init(struct amdgpu_device
*adev
)
1786 if (adev
->pm
.sysfs_initialized
)
1789 if (adev
->pm
.dpm_enabled
== 0)
1792 adev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(adev
->dev
,
1795 if (IS_ERR(adev
->pm
.int_hwmon_dev
)) {
1796 ret
= PTR_ERR(adev
->pm
.int_hwmon_dev
);
1798 "Unable to register hwmon device: %d\n", ret
);
1802 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_state
);
1804 DRM_ERROR("failed to create device file for dpm state\n");
1807 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1809 DRM_ERROR("failed to create device file for dpm state\n");
1814 ret
= device_create_file(adev
->dev
, &dev_attr_pp_num_states
);
1816 DRM_ERROR("failed to create device file pp_num_states\n");
1819 ret
= device_create_file(adev
->dev
, &dev_attr_pp_cur_state
);
1821 DRM_ERROR("failed to create device file pp_cur_state\n");
1824 ret
= device_create_file(adev
->dev
, &dev_attr_pp_force_state
);
1826 DRM_ERROR("failed to create device file pp_force_state\n");
1829 ret
= device_create_file(adev
->dev
, &dev_attr_pp_table
);
1831 DRM_ERROR("failed to create device file pp_table\n");
1835 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
1837 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1840 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
1842 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1845 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
1847 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1850 ret
= device_create_file(adev
->dev
, &dev_attr_pp_sclk_od
);
1852 DRM_ERROR("failed to create device file pp_sclk_od\n");
1855 ret
= device_create_file(adev
->dev
, &dev_attr_pp_mclk_od
);
1857 DRM_ERROR("failed to create device file pp_mclk_od\n");
1860 ret
= device_create_file(adev
->dev
,
1861 &dev_attr_pp_power_profile_mode
);
1863 DRM_ERROR("failed to create device file "
1864 "pp_power_profile_mode\n");
1867 ret
= device_create_file(adev
->dev
,
1868 &dev_attr_pp_od_clk_voltage
);
1870 DRM_ERROR("failed to create device file "
1871 "pp_od_clk_voltage\n");
1874 ret
= device_create_file(adev
->dev
,
1875 &dev_attr_gpu_busy_percent
);
1877 DRM_ERROR("failed to create device file "
1878 "gpu_busy_level\n");
1881 ret
= amdgpu_debugfs_pm_init(adev
);
1883 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1887 adev
->pm
.sysfs_initialized
= true;
1892 void amdgpu_pm_sysfs_fini(struct amdgpu_device
*adev
)
1894 if (adev
->pm
.dpm_enabled
== 0)
1897 if (adev
->pm
.int_hwmon_dev
)
1898 hwmon_device_unregister(adev
->pm
.int_hwmon_dev
);
1899 device_remove_file(adev
->dev
, &dev_attr_power_dpm_state
);
1900 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1902 device_remove_file(adev
->dev
, &dev_attr_pp_num_states
);
1903 device_remove_file(adev
->dev
, &dev_attr_pp_cur_state
);
1904 device_remove_file(adev
->dev
, &dev_attr_pp_force_state
);
1905 device_remove_file(adev
->dev
, &dev_attr_pp_table
);
1907 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
1908 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
1909 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
1910 device_remove_file(adev
->dev
, &dev_attr_pp_sclk_od
);
1911 device_remove_file(adev
->dev
, &dev_attr_pp_mclk_od
);
1912 device_remove_file(adev
->dev
,
1913 &dev_attr_pp_power_profile_mode
);
1914 device_remove_file(adev
->dev
,
1915 &dev_attr_pp_od_clk_voltage
);
1916 device_remove_file(adev
->dev
, &dev_attr_gpu_busy_percent
);
1919 void amdgpu_pm_compute_clocks(struct amdgpu_device
*adev
)
1923 if (!adev
->pm
.dpm_enabled
)
1926 if (adev
->mode_info
.num_crtc
)
1927 amdgpu_display_bandwidth_update(adev
);
1929 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
1930 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1931 if (ring
&& ring
->ready
)
1932 amdgpu_fence_wait_empty(ring
);
1935 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1936 if (!amdgpu_device_has_dc_support(adev
)) {
1937 mutex_lock(&adev
->pm
.mutex
);
1938 amdgpu_dpm_get_active_displays(adev
);
1939 adev
->pm
.pm_display_cfg
.num_display
= adev
->pm
.dpm
.new_active_crtc_count
;
1940 adev
->pm
.pm_display_cfg
.vrefresh
= amdgpu_dpm_get_vrefresh(adev
);
1941 adev
->pm
.pm_display_cfg
.min_vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
1942 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1943 if (adev
->pm
.pm_display_cfg
.vrefresh
> 120)
1944 adev
->pm
.pm_display_cfg
.min_vblank_time
= 0;
1945 if (adev
->powerplay
.pp_funcs
->display_configuration_change
)
1946 adev
->powerplay
.pp_funcs
->display_configuration_change(
1947 adev
->powerplay
.pp_handle
,
1948 &adev
->pm
.pm_display_cfg
);
1949 mutex_unlock(&adev
->pm
.mutex
);
1951 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
, NULL
);
1953 mutex_lock(&adev
->pm
.mutex
);
1954 amdgpu_dpm_get_active_displays(adev
);
1955 amdgpu_dpm_change_power_state_locked(adev
);
1956 mutex_unlock(&adev
->pm
.mutex
);
1963 #if defined(CONFIG_DEBUG_FS)
1965 static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m
, struct amdgpu_device
*adev
)
1971 /* sanity check PP is enabled */
1972 if (!(adev
->powerplay
.pp_funcs
&&
1973 adev
->powerplay
.pp_funcs
->read_sensor
))
1977 size
= sizeof(value
);
1978 seq_printf(m
, "GFX Clocks and Power:\n");
1979 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
, (void *)&value
, &size
))
1980 seq_printf(m
, "\t%u MHz (MCLK)\n", value
/100);
1981 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
, (void *)&value
, &size
))
1982 seq_printf(m
, "\t%u MHz (SCLK)\n", value
/100);
1983 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK
, (void *)&value
, &size
))
1984 seq_printf(m
, "\t%u MHz (PSTATE_SCLK)\n", value
/100);
1985 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK
, (void *)&value
, &size
))
1986 seq_printf(m
, "\t%u MHz (PSTATE_MCLK)\n", value
/100);
1987 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
, (void *)&value
, &size
))
1988 seq_printf(m
, "\t%u mV (VDDGFX)\n", value
);
1989 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
, (void *)&value
, &size
))
1990 seq_printf(m
, "\t%u mV (VDDNB)\n", value
);
1991 size
= sizeof(uint32_t);
1992 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
, (void *)&query
, &size
))
1993 seq_printf(m
, "\t%u.%u W (average GPU)\n", query
>> 8, query
& 0xff);
1994 size
= sizeof(value
);
1995 seq_printf(m
, "\n");
1998 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
, (void *)&value
, &size
))
1999 seq_printf(m
, "GPU Temperature: %u C\n", value
/1000);
2002 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
, (void *)&value
, &size
))
2003 seq_printf(m
, "GPU Load: %u %%\n", value
);
2004 seq_printf(m
, "\n");
2007 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_POWER
, (void *)&value
, &size
)) {
2009 seq_printf(m
, "UVD: Disabled\n");
2011 seq_printf(m
, "UVD: Enabled\n");
2012 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
2013 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
2014 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
2015 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
2018 seq_printf(m
, "\n");
2021 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_POWER
, (void *)&value
, &size
)) {
2023 seq_printf(m
, "VCE: Disabled\n");
2025 seq_printf(m
, "VCE: Enabled\n");
2026 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_ECCLK
, (void *)&value
, &size
))
2027 seq_printf(m
, "\t%u MHz (ECCLK)\n", value
/100);
2034 static void amdgpu_parse_cg_state(struct seq_file
*m
, u32 flags
)
2038 for (i
= 0; clocks
[i
].flag
; i
++)
2039 seq_printf(m
, "\t%s: %s\n", clocks
[i
].name
,
2040 (flags
& clocks
[i
].flag
) ? "On" : "Off");
2043 static int amdgpu_debugfs_pm_info(struct seq_file
*m
, void *data
)
2045 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2046 struct drm_device
*dev
= node
->minor
->dev
;
2047 struct amdgpu_device
*adev
= dev
->dev_private
;
2048 struct drm_device
*ddev
= adev
->ddev
;
2051 amdgpu_device_ip_get_clockgating_state(adev
, &flags
);
2052 seq_printf(m
, "Clock Gating Flags Mask: 0x%x\n", flags
);
2053 amdgpu_parse_cg_state(m
, flags
);
2054 seq_printf(m
, "\n");
2056 if (!adev
->pm
.dpm_enabled
) {
2057 seq_printf(m
, "dpm not enabled\n");
2060 if ((adev
->flags
& AMD_IS_PX
) &&
2061 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
2062 seq_printf(m
, "PX asic powered off\n");
2063 } else if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
) {
2064 mutex_lock(&adev
->pm
.mutex
);
2065 if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
)
2066 adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level(adev
, m
);
2068 seq_printf(m
, "Debugfs support not implemented for this asic\n");
2069 mutex_unlock(&adev
->pm
.mutex
);
2071 return amdgpu_debugfs_pm_info_pp(m
, adev
);
2077 static const struct drm_info_list amdgpu_pm_info_list
[] = {
2078 {"amdgpu_pm_info", amdgpu_debugfs_pm_info
, 0, NULL
},
2082 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
)
2084 #if defined(CONFIG_DEBUG_FS)
2085 return amdgpu_debugfs_add_files(adev
, amdgpu_pm_info_list
, ARRAY_SIZE(amdgpu_pm_info_list
));