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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include "drmP.h"
25 #include "amdgpu.h"
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
28 #include "cikd.h"
29 #include "cik.h"
30 #include "atom.h"
31 #include "amdgpu_ucode.h"
32 #include "clearstate_ci.h"
33
34 #include "dce/dce_8_0_d.h"
35 #include "dce/dce_8_0_sh_mask.h"
36
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
39
40 #include "gca/gfx_7_0_d.h"
41 #include "gca/gfx_7_2_enum.h"
42 #include "gca/gfx_7_2_sh_mask.h"
43
44 #include "gmc/gmc_7_0_d.h"
45 #include "gmc/gmc_7_0_sh_mask.h"
46
47 #include "oss/oss_2_0_d.h"
48 #include "oss/oss_2_0_sh_mask.h"
49
50 #define GFX7_NUM_GFX_RINGS 1
51 #define GFX7_NUM_COMPUTE_RINGS 8
52
53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
56
57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58 MODULE_FIRMWARE("radeon/bonaire_me.bin");
59 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
62
63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64 MODULE_FIRMWARE("radeon/hawaii_me.bin");
65 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68
69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70 MODULE_FIRMWARE("radeon/kaveri_me.bin");
71 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
75
76 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77 MODULE_FIRMWARE("radeon/kabini_me.bin");
78 MODULE_FIRMWARE("radeon/kabini_ce.bin");
79 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80 MODULE_FIRMWARE("radeon/kabini_mec.bin");
81
82 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83 MODULE_FIRMWARE("radeon/mullins_me.bin");
84 MODULE_FIRMWARE("radeon/mullins_ce.bin");
85 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86 MODULE_FIRMWARE("radeon/mullins_mec.bin");
87
88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
89 {
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
106 };
107
108 static const u32 spectre_rlc_save_restore_register_list[] =
109 {
110 (0x0e00 << 16) | (0xc12c >> 2),
111 0x00000000,
112 (0x0e00 << 16) | (0xc140 >> 2),
113 0x00000000,
114 (0x0e00 << 16) | (0xc150 >> 2),
115 0x00000000,
116 (0x0e00 << 16) | (0xc15c >> 2),
117 0x00000000,
118 (0x0e00 << 16) | (0xc168 >> 2),
119 0x00000000,
120 (0x0e00 << 16) | (0xc170 >> 2),
121 0x00000000,
122 (0x0e00 << 16) | (0xc178 >> 2),
123 0x00000000,
124 (0x0e00 << 16) | (0xc204 >> 2),
125 0x00000000,
126 (0x0e00 << 16) | (0xc2b4 >> 2),
127 0x00000000,
128 (0x0e00 << 16) | (0xc2b8 >> 2),
129 0x00000000,
130 (0x0e00 << 16) | (0xc2bc >> 2),
131 0x00000000,
132 (0x0e00 << 16) | (0xc2c0 >> 2),
133 0x00000000,
134 (0x0e00 << 16) | (0x8228 >> 2),
135 0x00000000,
136 (0x0e00 << 16) | (0x829c >> 2),
137 0x00000000,
138 (0x0e00 << 16) | (0x869c >> 2),
139 0x00000000,
140 (0x0600 << 16) | (0x98f4 >> 2),
141 0x00000000,
142 (0x0e00 << 16) | (0x98f8 >> 2),
143 0x00000000,
144 (0x0e00 << 16) | (0x9900 >> 2),
145 0x00000000,
146 (0x0e00 << 16) | (0xc260 >> 2),
147 0x00000000,
148 (0x0e00 << 16) | (0x90e8 >> 2),
149 0x00000000,
150 (0x0e00 << 16) | (0x3c000 >> 2),
151 0x00000000,
152 (0x0e00 << 16) | (0x3c00c >> 2),
153 0x00000000,
154 (0x0e00 << 16) | (0x8c1c >> 2),
155 0x00000000,
156 (0x0e00 << 16) | (0x9700 >> 2),
157 0x00000000,
158 (0x0e00 << 16) | (0xcd20 >> 2),
159 0x00000000,
160 (0x4e00 << 16) | (0xcd20 >> 2),
161 0x00000000,
162 (0x5e00 << 16) | (0xcd20 >> 2),
163 0x00000000,
164 (0x6e00 << 16) | (0xcd20 >> 2),
165 0x00000000,
166 (0x7e00 << 16) | (0xcd20 >> 2),
167 0x00000000,
168 (0x8e00 << 16) | (0xcd20 >> 2),
169 0x00000000,
170 (0x9e00 << 16) | (0xcd20 >> 2),
171 0x00000000,
172 (0xae00 << 16) | (0xcd20 >> 2),
173 0x00000000,
174 (0xbe00 << 16) | (0xcd20 >> 2),
175 0x00000000,
176 (0x0e00 << 16) | (0x89bc >> 2),
177 0x00000000,
178 (0x0e00 << 16) | (0x8900 >> 2),
179 0x00000000,
180 0x3,
181 (0x0e00 << 16) | (0xc130 >> 2),
182 0x00000000,
183 (0x0e00 << 16) | (0xc134 >> 2),
184 0x00000000,
185 (0x0e00 << 16) | (0xc1fc >> 2),
186 0x00000000,
187 (0x0e00 << 16) | (0xc208 >> 2),
188 0x00000000,
189 (0x0e00 << 16) | (0xc264 >> 2),
190 0x00000000,
191 (0x0e00 << 16) | (0xc268 >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc26c >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc270 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc274 >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc278 >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc27c >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc280 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc284 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc288 >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc28c >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc290 >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc294 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0xc298 >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0xc29c >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0xc2a0 >> 2),
220 0x00000000,
221 (0x0e00 << 16) | (0xc2a4 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0xc2a8 >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0xc2ac >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc2b0 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0x301d0 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0x30238 >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0x30250 >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x30254 >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x30258 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0x3025c >> 2),
240 0x00000000,
241 (0x4e00 << 16) | (0xc900 >> 2),
242 0x00000000,
243 (0x5e00 << 16) | (0xc900 >> 2),
244 0x00000000,
245 (0x6e00 << 16) | (0xc900 >> 2),
246 0x00000000,
247 (0x7e00 << 16) | (0xc900 >> 2),
248 0x00000000,
249 (0x8e00 << 16) | (0xc900 >> 2),
250 0x00000000,
251 (0x9e00 << 16) | (0xc900 >> 2),
252 0x00000000,
253 (0xae00 << 16) | (0xc900 >> 2),
254 0x00000000,
255 (0xbe00 << 16) | (0xc900 >> 2),
256 0x00000000,
257 (0x4e00 << 16) | (0xc904 >> 2),
258 0x00000000,
259 (0x5e00 << 16) | (0xc904 >> 2),
260 0x00000000,
261 (0x6e00 << 16) | (0xc904 >> 2),
262 0x00000000,
263 (0x7e00 << 16) | (0xc904 >> 2),
264 0x00000000,
265 (0x8e00 << 16) | (0xc904 >> 2),
266 0x00000000,
267 (0x9e00 << 16) | (0xc904 >> 2),
268 0x00000000,
269 (0xae00 << 16) | (0xc904 >> 2),
270 0x00000000,
271 (0xbe00 << 16) | (0xc904 >> 2),
272 0x00000000,
273 (0x4e00 << 16) | (0xc908 >> 2),
274 0x00000000,
275 (0x5e00 << 16) | (0xc908 >> 2),
276 0x00000000,
277 (0x6e00 << 16) | (0xc908 >> 2),
278 0x00000000,
279 (0x7e00 << 16) | (0xc908 >> 2),
280 0x00000000,
281 (0x8e00 << 16) | (0xc908 >> 2),
282 0x00000000,
283 (0x9e00 << 16) | (0xc908 >> 2),
284 0x00000000,
285 (0xae00 << 16) | (0xc908 >> 2),
286 0x00000000,
287 (0xbe00 << 16) | (0xc908 >> 2),
288 0x00000000,
289 (0x4e00 << 16) | (0xc90c >> 2),
290 0x00000000,
291 (0x5e00 << 16) | (0xc90c >> 2),
292 0x00000000,
293 (0x6e00 << 16) | (0xc90c >> 2),
294 0x00000000,
295 (0x7e00 << 16) | (0xc90c >> 2),
296 0x00000000,
297 (0x8e00 << 16) | (0xc90c >> 2),
298 0x00000000,
299 (0x9e00 << 16) | (0xc90c >> 2),
300 0x00000000,
301 (0xae00 << 16) | (0xc90c >> 2),
302 0x00000000,
303 (0xbe00 << 16) | (0xc90c >> 2),
304 0x00000000,
305 (0x4e00 << 16) | (0xc910 >> 2),
306 0x00000000,
307 (0x5e00 << 16) | (0xc910 >> 2),
308 0x00000000,
309 (0x6e00 << 16) | (0xc910 >> 2),
310 0x00000000,
311 (0x7e00 << 16) | (0xc910 >> 2),
312 0x00000000,
313 (0x8e00 << 16) | (0xc910 >> 2),
314 0x00000000,
315 (0x9e00 << 16) | (0xc910 >> 2),
316 0x00000000,
317 (0xae00 << 16) | (0xc910 >> 2),
318 0x00000000,
319 (0xbe00 << 16) | (0xc910 >> 2),
320 0x00000000,
321 (0x0e00 << 16) | (0xc99c >> 2),
322 0x00000000,
323 (0x0e00 << 16) | (0x9834 >> 2),
324 0x00000000,
325 (0x0000 << 16) | (0x30f00 >> 2),
326 0x00000000,
327 (0x0001 << 16) | (0x30f00 >> 2),
328 0x00000000,
329 (0x0000 << 16) | (0x30f04 >> 2),
330 0x00000000,
331 (0x0001 << 16) | (0x30f04 >> 2),
332 0x00000000,
333 (0x0000 << 16) | (0x30f08 >> 2),
334 0x00000000,
335 (0x0001 << 16) | (0x30f08 >> 2),
336 0x00000000,
337 (0x0000 << 16) | (0x30f0c >> 2),
338 0x00000000,
339 (0x0001 << 16) | (0x30f0c >> 2),
340 0x00000000,
341 (0x0600 << 16) | (0x9b7c >> 2),
342 0x00000000,
343 (0x0e00 << 16) | (0x8a14 >> 2),
344 0x00000000,
345 (0x0e00 << 16) | (0x8a18 >> 2),
346 0x00000000,
347 (0x0600 << 16) | (0x30a00 >> 2),
348 0x00000000,
349 (0x0e00 << 16) | (0x8bf0 >> 2),
350 0x00000000,
351 (0x0e00 << 16) | (0x8bcc >> 2),
352 0x00000000,
353 (0x0e00 << 16) | (0x8b24 >> 2),
354 0x00000000,
355 (0x0e00 << 16) | (0x30a04 >> 2),
356 0x00000000,
357 (0x0600 << 16) | (0x30a10 >> 2),
358 0x00000000,
359 (0x0600 << 16) | (0x30a14 >> 2),
360 0x00000000,
361 (0x0600 << 16) | (0x30a18 >> 2),
362 0x00000000,
363 (0x0600 << 16) | (0x30a2c >> 2),
364 0x00000000,
365 (0x0e00 << 16) | (0xc700 >> 2),
366 0x00000000,
367 (0x0e00 << 16) | (0xc704 >> 2),
368 0x00000000,
369 (0x0e00 << 16) | (0xc708 >> 2),
370 0x00000000,
371 (0x0e00 << 16) | (0xc768 >> 2),
372 0x00000000,
373 (0x0400 << 16) | (0xc770 >> 2),
374 0x00000000,
375 (0x0400 << 16) | (0xc774 >> 2),
376 0x00000000,
377 (0x0400 << 16) | (0xc778 >> 2),
378 0x00000000,
379 (0x0400 << 16) | (0xc77c >> 2),
380 0x00000000,
381 (0x0400 << 16) | (0xc780 >> 2),
382 0x00000000,
383 (0x0400 << 16) | (0xc784 >> 2),
384 0x00000000,
385 (0x0400 << 16) | (0xc788 >> 2),
386 0x00000000,
387 (0x0400 << 16) | (0xc78c >> 2),
388 0x00000000,
389 (0x0400 << 16) | (0xc798 >> 2),
390 0x00000000,
391 (0x0400 << 16) | (0xc79c >> 2),
392 0x00000000,
393 (0x0400 << 16) | (0xc7a0 >> 2),
394 0x00000000,
395 (0x0400 << 16) | (0xc7a4 >> 2),
396 0x00000000,
397 (0x0400 << 16) | (0xc7a8 >> 2),
398 0x00000000,
399 (0x0400 << 16) | (0xc7ac >> 2),
400 0x00000000,
401 (0x0400 << 16) | (0xc7b0 >> 2),
402 0x00000000,
403 (0x0400 << 16) | (0xc7b4 >> 2),
404 0x00000000,
405 (0x0e00 << 16) | (0x9100 >> 2),
406 0x00000000,
407 (0x0e00 << 16) | (0x3c010 >> 2),
408 0x00000000,
409 (0x0e00 << 16) | (0x92a8 >> 2),
410 0x00000000,
411 (0x0e00 << 16) | (0x92ac >> 2),
412 0x00000000,
413 (0x0e00 << 16) | (0x92b4 >> 2),
414 0x00000000,
415 (0x0e00 << 16) | (0x92b8 >> 2),
416 0x00000000,
417 (0x0e00 << 16) | (0x92bc >> 2),
418 0x00000000,
419 (0x0e00 << 16) | (0x92c0 >> 2),
420 0x00000000,
421 (0x0e00 << 16) | (0x92c4 >> 2),
422 0x00000000,
423 (0x0e00 << 16) | (0x92c8 >> 2),
424 0x00000000,
425 (0x0e00 << 16) | (0x92cc >> 2),
426 0x00000000,
427 (0x0e00 << 16) | (0x92d0 >> 2),
428 0x00000000,
429 (0x0e00 << 16) | (0x8c00 >> 2),
430 0x00000000,
431 (0x0e00 << 16) | (0x8c04 >> 2),
432 0x00000000,
433 (0x0e00 << 16) | (0x8c20 >> 2),
434 0x00000000,
435 (0x0e00 << 16) | (0x8c38 >> 2),
436 0x00000000,
437 (0x0e00 << 16) | (0x8c3c >> 2),
438 0x00000000,
439 (0x0e00 << 16) | (0xae00 >> 2),
440 0x00000000,
441 (0x0e00 << 16) | (0x9604 >> 2),
442 0x00000000,
443 (0x0e00 << 16) | (0xac08 >> 2),
444 0x00000000,
445 (0x0e00 << 16) | (0xac0c >> 2),
446 0x00000000,
447 (0x0e00 << 16) | (0xac10 >> 2),
448 0x00000000,
449 (0x0e00 << 16) | (0xac14 >> 2),
450 0x00000000,
451 (0x0e00 << 16) | (0xac58 >> 2),
452 0x00000000,
453 (0x0e00 << 16) | (0xac68 >> 2),
454 0x00000000,
455 (0x0e00 << 16) | (0xac6c >> 2),
456 0x00000000,
457 (0x0e00 << 16) | (0xac70 >> 2),
458 0x00000000,
459 (0x0e00 << 16) | (0xac74 >> 2),
460 0x00000000,
461 (0x0e00 << 16) | (0xac78 >> 2),
462 0x00000000,
463 (0x0e00 << 16) | (0xac7c >> 2),
464 0x00000000,
465 (0x0e00 << 16) | (0xac80 >> 2),
466 0x00000000,
467 (0x0e00 << 16) | (0xac84 >> 2),
468 0x00000000,
469 (0x0e00 << 16) | (0xac88 >> 2),
470 0x00000000,
471 (0x0e00 << 16) | (0xac8c >> 2),
472 0x00000000,
473 (0x0e00 << 16) | (0x970c >> 2),
474 0x00000000,
475 (0x0e00 << 16) | (0x9714 >> 2),
476 0x00000000,
477 (0x0e00 << 16) | (0x9718 >> 2),
478 0x00000000,
479 (0x0e00 << 16) | (0x971c >> 2),
480 0x00000000,
481 (0x0e00 << 16) | (0x31068 >> 2),
482 0x00000000,
483 (0x4e00 << 16) | (0x31068 >> 2),
484 0x00000000,
485 (0x5e00 << 16) | (0x31068 >> 2),
486 0x00000000,
487 (0x6e00 << 16) | (0x31068 >> 2),
488 0x00000000,
489 (0x7e00 << 16) | (0x31068 >> 2),
490 0x00000000,
491 (0x8e00 << 16) | (0x31068 >> 2),
492 0x00000000,
493 (0x9e00 << 16) | (0x31068 >> 2),
494 0x00000000,
495 (0xae00 << 16) | (0x31068 >> 2),
496 0x00000000,
497 (0xbe00 << 16) | (0x31068 >> 2),
498 0x00000000,
499 (0x0e00 << 16) | (0xcd10 >> 2),
500 0x00000000,
501 (0x0e00 << 16) | (0xcd14 >> 2),
502 0x00000000,
503 (0x0e00 << 16) | (0x88b0 >> 2),
504 0x00000000,
505 (0x0e00 << 16) | (0x88b4 >> 2),
506 0x00000000,
507 (0x0e00 << 16) | (0x88b8 >> 2),
508 0x00000000,
509 (0x0e00 << 16) | (0x88bc >> 2),
510 0x00000000,
511 (0x0400 << 16) | (0x89c0 >> 2),
512 0x00000000,
513 (0x0e00 << 16) | (0x88c4 >> 2),
514 0x00000000,
515 (0x0e00 << 16) | (0x88c8 >> 2),
516 0x00000000,
517 (0x0e00 << 16) | (0x88d0 >> 2),
518 0x00000000,
519 (0x0e00 << 16) | (0x88d4 >> 2),
520 0x00000000,
521 (0x0e00 << 16) | (0x88d8 >> 2),
522 0x00000000,
523 (0x0e00 << 16) | (0x8980 >> 2),
524 0x00000000,
525 (0x0e00 << 16) | (0x30938 >> 2),
526 0x00000000,
527 (0x0e00 << 16) | (0x3093c >> 2),
528 0x00000000,
529 (0x0e00 << 16) | (0x30940 >> 2),
530 0x00000000,
531 (0x0e00 << 16) | (0x89a0 >> 2),
532 0x00000000,
533 (0x0e00 << 16) | (0x30900 >> 2),
534 0x00000000,
535 (0x0e00 << 16) | (0x30904 >> 2),
536 0x00000000,
537 (0x0e00 << 16) | (0x89b4 >> 2),
538 0x00000000,
539 (0x0e00 << 16) | (0x3c210 >> 2),
540 0x00000000,
541 (0x0e00 << 16) | (0x3c214 >> 2),
542 0x00000000,
543 (0x0e00 << 16) | (0x3c218 >> 2),
544 0x00000000,
545 (0x0e00 << 16) | (0x8904 >> 2),
546 0x00000000,
547 0x5,
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
553 };
554
555 static const u32 kalindi_rlc_save_restore_register_list[] =
556 {
557 (0x0e00 << 16) | (0xc12c >> 2),
558 0x00000000,
559 (0x0e00 << 16) | (0xc140 >> 2),
560 0x00000000,
561 (0x0e00 << 16) | (0xc150 >> 2),
562 0x00000000,
563 (0x0e00 << 16) | (0xc15c >> 2),
564 0x00000000,
565 (0x0e00 << 16) | (0xc168 >> 2),
566 0x00000000,
567 (0x0e00 << 16) | (0xc170 >> 2),
568 0x00000000,
569 (0x0e00 << 16) | (0xc204 >> 2),
570 0x00000000,
571 (0x0e00 << 16) | (0xc2b4 >> 2),
572 0x00000000,
573 (0x0e00 << 16) | (0xc2b8 >> 2),
574 0x00000000,
575 (0x0e00 << 16) | (0xc2bc >> 2),
576 0x00000000,
577 (0x0e00 << 16) | (0xc2c0 >> 2),
578 0x00000000,
579 (0x0e00 << 16) | (0x8228 >> 2),
580 0x00000000,
581 (0x0e00 << 16) | (0x829c >> 2),
582 0x00000000,
583 (0x0e00 << 16) | (0x869c >> 2),
584 0x00000000,
585 (0x0600 << 16) | (0x98f4 >> 2),
586 0x00000000,
587 (0x0e00 << 16) | (0x98f8 >> 2),
588 0x00000000,
589 (0x0e00 << 16) | (0x9900 >> 2),
590 0x00000000,
591 (0x0e00 << 16) | (0xc260 >> 2),
592 0x00000000,
593 (0x0e00 << 16) | (0x90e8 >> 2),
594 0x00000000,
595 (0x0e00 << 16) | (0x3c000 >> 2),
596 0x00000000,
597 (0x0e00 << 16) | (0x3c00c >> 2),
598 0x00000000,
599 (0x0e00 << 16) | (0x8c1c >> 2),
600 0x00000000,
601 (0x0e00 << 16) | (0x9700 >> 2),
602 0x00000000,
603 (0x0e00 << 16) | (0xcd20 >> 2),
604 0x00000000,
605 (0x4e00 << 16) | (0xcd20 >> 2),
606 0x00000000,
607 (0x5e00 << 16) | (0xcd20 >> 2),
608 0x00000000,
609 (0x6e00 << 16) | (0xcd20 >> 2),
610 0x00000000,
611 (0x7e00 << 16) | (0xcd20 >> 2),
612 0x00000000,
613 (0x0e00 << 16) | (0x89bc >> 2),
614 0x00000000,
615 (0x0e00 << 16) | (0x8900 >> 2),
616 0x00000000,
617 0x3,
618 (0x0e00 << 16) | (0xc130 >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0xc134 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xc1fc >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xc208 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xc264 >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xc268 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xc26c >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xc270 >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xc274 >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0xc28c >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0xc290 >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc294 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc298 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc2a0 >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc2a4 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc2a8 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc2ac >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0x301d0 >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0x30238 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0x30250 >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0x30254 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x30258 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x3025c >> 2),
663 0x00000000,
664 (0x4e00 << 16) | (0xc900 >> 2),
665 0x00000000,
666 (0x5e00 << 16) | (0xc900 >> 2),
667 0x00000000,
668 (0x6e00 << 16) | (0xc900 >> 2),
669 0x00000000,
670 (0x7e00 << 16) | (0xc900 >> 2),
671 0x00000000,
672 (0x4e00 << 16) | (0xc904 >> 2),
673 0x00000000,
674 (0x5e00 << 16) | (0xc904 >> 2),
675 0x00000000,
676 (0x6e00 << 16) | (0xc904 >> 2),
677 0x00000000,
678 (0x7e00 << 16) | (0xc904 >> 2),
679 0x00000000,
680 (0x4e00 << 16) | (0xc908 >> 2),
681 0x00000000,
682 (0x5e00 << 16) | (0xc908 >> 2),
683 0x00000000,
684 (0x6e00 << 16) | (0xc908 >> 2),
685 0x00000000,
686 (0x7e00 << 16) | (0xc908 >> 2),
687 0x00000000,
688 (0x4e00 << 16) | (0xc90c >> 2),
689 0x00000000,
690 (0x5e00 << 16) | (0xc90c >> 2),
691 0x00000000,
692 (0x6e00 << 16) | (0xc90c >> 2),
693 0x00000000,
694 (0x7e00 << 16) | (0xc90c >> 2),
695 0x00000000,
696 (0x4e00 << 16) | (0xc910 >> 2),
697 0x00000000,
698 (0x5e00 << 16) | (0xc910 >> 2),
699 0x00000000,
700 (0x6e00 << 16) | (0xc910 >> 2),
701 0x00000000,
702 (0x7e00 << 16) | (0xc910 >> 2),
703 0x00000000,
704 (0x0e00 << 16) | (0xc99c >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0x9834 >> 2),
707 0x00000000,
708 (0x0000 << 16) | (0x30f00 >> 2),
709 0x00000000,
710 (0x0000 << 16) | (0x30f04 >> 2),
711 0x00000000,
712 (0x0000 << 16) | (0x30f08 >> 2),
713 0x00000000,
714 (0x0000 << 16) | (0x30f0c >> 2),
715 0x00000000,
716 (0x0600 << 16) | (0x9b7c >> 2),
717 0x00000000,
718 (0x0e00 << 16) | (0x8a14 >> 2),
719 0x00000000,
720 (0x0e00 << 16) | (0x8a18 >> 2),
721 0x00000000,
722 (0x0600 << 16) | (0x30a00 >> 2),
723 0x00000000,
724 (0x0e00 << 16) | (0x8bf0 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0x8bcc >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0x8b24 >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0x30a04 >> 2),
731 0x00000000,
732 (0x0600 << 16) | (0x30a10 >> 2),
733 0x00000000,
734 (0x0600 << 16) | (0x30a14 >> 2),
735 0x00000000,
736 (0x0600 << 16) | (0x30a18 >> 2),
737 0x00000000,
738 (0x0600 << 16) | (0x30a2c >> 2),
739 0x00000000,
740 (0x0e00 << 16) | (0xc700 >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0xc704 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0xc708 >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0xc768 >> 2),
747 0x00000000,
748 (0x0400 << 16) | (0xc770 >> 2),
749 0x00000000,
750 (0x0400 << 16) | (0xc774 >> 2),
751 0x00000000,
752 (0x0400 << 16) | (0xc798 >> 2),
753 0x00000000,
754 (0x0400 << 16) | (0xc79c >> 2),
755 0x00000000,
756 (0x0e00 << 16) | (0x9100 >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x3c010 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x8c00 >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c04 >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x8c20 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0x8c38 >> 2),
767 0x00000000,
768 (0x0e00 << 16) | (0x8c3c >> 2),
769 0x00000000,
770 (0x0e00 << 16) | (0xae00 >> 2),
771 0x00000000,
772 (0x0e00 << 16) | (0x9604 >> 2),
773 0x00000000,
774 (0x0e00 << 16) | (0xac08 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0xac0c >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0xac10 >> 2),
779 0x00000000,
780 (0x0e00 << 16) | (0xac14 >> 2),
781 0x00000000,
782 (0x0e00 << 16) | (0xac58 >> 2),
783 0x00000000,
784 (0x0e00 << 16) | (0xac68 >> 2),
785 0x00000000,
786 (0x0e00 << 16) | (0xac6c >> 2),
787 0x00000000,
788 (0x0e00 << 16) | (0xac70 >> 2),
789 0x00000000,
790 (0x0e00 << 16) | (0xac74 >> 2),
791 0x00000000,
792 (0x0e00 << 16) | (0xac78 >> 2),
793 0x00000000,
794 (0x0e00 << 16) | (0xac7c >> 2),
795 0x00000000,
796 (0x0e00 << 16) | (0xac80 >> 2),
797 0x00000000,
798 (0x0e00 << 16) | (0xac84 >> 2),
799 0x00000000,
800 (0x0e00 << 16) | (0xac88 >> 2),
801 0x00000000,
802 (0x0e00 << 16) | (0xac8c >> 2),
803 0x00000000,
804 (0x0e00 << 16) | (0x970c >> 2),
805 0x00000000,
806 (0x0e00 << 16) | (0x9714 >> 2),
807 0x00000000,
808 (0x0e00 << 16) | (0x9718 >> 2),
809 0x00000000,
810 (0x0e00 << 16) | (0x971c >> 2),
811 0x00000000,
812 (0x0e00 << 16) | (0x31068 >> 2),
813 0x00000000,
814 (0x4e00 << 16) | (0x31068 >> 2),
815 0x00000000,
816 (0x5e00 << 16) | (0x31068 >> 2),
817 0x00000000,
818 (0x6e00 << 16) | (0x31068 >> 2),
819 0x00000000,
820 (0x7e00 << 16) | (0x31068 >> 2),
821 0x00000000,
822 (0x0e00 << 16) | (0xcd10 >> 2),
823 0x00000000,
824 (0x0e00 << 16) | (0xcd14 >> 2),
825 0x00000000,
826 (0x0e00 << 16) | (0x88b0 >> 2),
827 0x00000000,
828 (0x0e00 << 16) | (0x88b4 >> 2),
829 0x00000000,
830 (0x0e00 << 16) | (0x88b8 >> 2),
831 0x00000000,
832 (0x0e00 << 16) | (0x88bc >> 2),
833 0x00000000,
834 (0x0400 << 16) | (0x89c0 >> 2),
835 0x00000000,
836 (0x0e00 << 16) | (0x88c4 >> 2),
837 0x00000000,
838 (0x0e00 << 16) | (0x88c8 >> 2),
839 0x00000000,
840 (0x0e00 << 16) | (0x88d0 >> 2),
841 0x00000000,
842 (0x0e00 << 16) | (0x88d4 >> 2),
843 0x00000000,
844 (0x0e00 << 16) | (0x88d8 >> 2),
845 0x00000000,
846 (0x0e00 << 16) | (0x8980 >> 2),
847 0x00000000,
848 (0x0e00 << 16) | (0x30938 >> 2),
849 0x00000000,
850 (0x0e00 << 16) | (0x3093c >> 2),
851 0x00000000,
852 (0x0e00 << 16) | (0x30940 >> 2),
853 0x00000000,
854 (0x0e00 << 16) | (0x89a0 >> 2),
855 0x00000000,
856 (0x0e00 << 16) | (0x30900 >> 2),
857 0x00000000,
858 (0x0e00 << 16) | (0x30904 >> 2),
859 0x00000000,
860 (0x0e00 << 16) | (0x89b4 >> 2),
861 0x00000000,
862 (0x0e00 << 16) | (0x3e1fc >> 2),
863 0x00000000,
864 (0x0e00 << 16) | (0x3c210 >> 2),
865 0x00000000,
866 (0x0e00 << 16) | (0x3c214 >> 2),
867 0x00000000,
868 (0x0e00 << 16) | (0x3c218 >> 2),
869 0x00000000,
870 (0x0e00 << 16) | (0x8904 >> 2),
871 0x00000000,
872 0x5,
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
878 };
879
880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
885
886 /*
887 * Core functions
888 */
889 /**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899 {
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973 out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992 }
993
994 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
995 {
996 release_firmware(adev->gfx.pfp_fw);
997 adev->gfx.pfp_fw = NULL;
998 release_firmware(adev->gfx.me_fw);
999 adev->gfx.me_fw = NULL;
1000 release_firmware(adev->gfx.ce_fw);
1001 adev->gfx.ce_fw = NULL;
1002 release_firmware(adev->gfx.mec_fw);
1003 adev->gfx.mec_fw = NULL;
1004 release_firmware(adev->gfx.mec2_fw);
1005 adev->gfx.mec2_fw = NULL;
1006 release_firmware(adev->gfx.rlc_fw);
1007 adev->gfx.rlc_fw = NULL;
1008 }
1009
1010 /**
1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1012 *
1013 * @adev: amdgpu_device pointer
1014 *
1015 * Starting with SI, the tiling setup is done globally in a
1016 * set of 32 tiling modes. Rather than selecting each set of
1017 * parameters per surface as on older asics, we just select
1018 * which index in the tiling table we want to use, and the
1019 * surface uses those parameters (CIK).
1020 */
1021 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1022 {
1023 const u32 num_tile_mode_states =
1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1025 const u32 num_secondary_tile_mode_states =
1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1027 u32 reg_offset, split_equal_to_row_size;
1028 uint32_t *tile, *macrotile;
1029
1030 tile = adev->gfx.config.tile_mode_array;
1031 macrotile = adev->gfx.config.macrotile_mode_array;
1032
1033 switch (adev->gfx.config.mem_row_size_in_kb) {
1034 case 1:
1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1036 break;
1037 case 2:
1038 default:
1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1040 break;
1041 case 4:
1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1043 break;
1044 }
1045
1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1047 tile[reg_offset] = 0;
1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1049 macrotile[reg_offset] = 0;
1050
1051 switch (adev->asic_type) {
1052 case CHIP_BONAIRE:
1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1072 TILE_SPLIT(split_equal_to_row_size));
1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1079 TILE_SPLIT(split_equal_to_row_size));
1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1155
1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163 NUM_BANKS(ADDR_SURF_16_BANK));
1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167 NUM_BANKS(ADDR_SURF_16_BANK));
1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_4_BANK));
1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191 NUM_BANKS(ADDR_SURF_16_BANK));
1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1195 NUM_BANKS(ADDR_SURF_16_BANK));
1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1203 NUM_BANKS(ADDR_SURF_16_BANK));
1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1207 NUM_BANKS(ADDR_SURF_8_BANK));
1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211 NUM_BANKS(ADDR_SURF_4_BANK));
1212
1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1216 if (reg_offset != 7)
1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1218 break;
1219 case CHIP_HAWAII:
1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1239 TILE_SPLIT(split_equal_to_row_size));
1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1243 TILE_SPLIT(split_equal_to_row_size));
1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1247 TILE_SPLIT(split_equal_to_row_size));
1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1251 TILE_SPLIT(split_equal_to_row_size));
1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1338
1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342 NUM_BANKS(ADDR_SURF_16_BANK));
1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346 NUM_BANKS(ADDR_SURF_16_BANK));
1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_16_BANK));
1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1358 NUM_BANKS(ADDR_SURF_8_BANK));
1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_4_BANK));
1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_4_BANK));
1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_16_BANK));
1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_16_BANK));
1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1382 NUM_BANKS(ADDR_SURF_8_BANK));
1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1386 NUM_BANKS(ADDR_SURF_16_BANK));
1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1390 NUM_BANKS(ADDR_SURF_8_BANK));
1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1394 NUM_BANKS(ADDR_SURF_4_BANK));
1395
1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1399 if (reg_offset != 7)
1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1401 break;
1402 case CHIP_KABINI:
1403 case CHIP_KAVERI:
1404 case CHIP_MULLINS:
1405 default:
1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415 PIPE_CONFIG(ADDR_SURF_P2) |
1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P2) |
1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 PIPE_CONFIG(ADDR_SURF_P2) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1425 TILE_SPLIT(split_equal_to_row_size));
1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1427 PIPE_CONFIG(ADDR_SURF_P2) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430 PIPE_CONFIG(ADDR_SURF_P2) |
1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1432 TILE_SPLIT(split_equal_to_row_size));
1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1435 PIPE_CONFIG(ADDR_SURF_P2));
1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452 PIPE_CONFIG(ADDR_SURF_P2) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1465 PIPE_CONFIG(ADDR_SURF_P2) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472 PIPE_CONFIG(ADDR_SURF_P2) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1476 PIPE_CONFIG(ADDR_SURF_P2) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1480 PIPE_CONFIG(ADDR_SURF_P2) |
1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1485 PIPE_CONFIG(ADDR_SURF_P2) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1489 PIPE_CONFIG(ADDR_SURF_P2) |
1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1493 PIPE_CONFIG(ADDR_SURF_P2) |
1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P2) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500 PIPE_CONFIG(ADDR_SURF_P2) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1504 PIPE_CONFIG(ADDR_SURF_P2) |
1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1508
1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1524 NUM_BANKS(ADDR_SURF_8_BANK));
1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1528 NUM_BANKS(ADDR_SURF_8_BANK));
1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532 NUM_BANKS(ADDR_SURF_8_BANK));
1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536 NUM_BANKS(ADDR_SURF_8_BANK));
1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548 NUM_BANKS(ADDR_SURF_16_BANK));
1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1552 NUM_BANKS(ADDR_SURF_16_BANK));
1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1556 NUM_BANKS(ADDR_SURF_16_BANK));
1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1560 NUM_BANKS(ADDR_SURF_16_BANK));
1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1564 NUM_BANKS(ADDR_SURF_8_BANK));
1565
1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1569 if (reg_offset != 7)
1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1571 break;
1572 }
1573 }
1574
1575 /**
1576 * gfx_v7_0_select_se_sh - select which SE, SH to address
1577 *
1578 * @adev: amdgpu_device pointer
1579 * @se_num: shader engine to address
1580 * @sh_num: sh block to address
1581 *
1582 * Select which SE, SH combinations to address. Certain
1583 * registers are instanced per SE or SH. 0xffffffff means
1584 * broadcast to all SEs or SHs (CIK).
1585 */
1586 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1587 {
1588 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1589
1590 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1591 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1592 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1593 else if (se_num == 0xffffffff)
1594 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1595 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1596 else if (sh_num == 0xffffffff)
1597 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1598 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1599 else
1600 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1601 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1602 WREG32(mmGRBM_GFX_INDEX, data);
1603 }
1604
1605 /**
1606 * gfx_v7_0_create_bitmask - create a bitmask
1607 *
1608 * @bit_width: length of the mask
1609 *
1610 * create a variable length bit mask (CIK).
1611 * Returns the bitmask.
1612 */
1613 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1614 {
1615 return (u32)((1ULL << bit_width) - 1);
1616 }
1617
1618 /**
1619 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1620 *
1621 * @adev: amdgpu_device pointer
1622 *
1623 * Calculates the bitmask of enabled RBs (CIK).
1624 * Returns the enabled RB bitmask.
1625 */
1626 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1627 {
1628 u32 data, mask;
1629
1630 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1631 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1632
1633 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1634 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1635
1636 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1637 adev->gfx.config.max_sh_per_se);
1638
1639 return (~data) & mask;
1640 }
1641
1642 /**
1643 * gfx_v7_0_setup_rb - setup the RBs on the asic
1644 *
1645 * @adev: amdgpu_device pointer
1646 * @se_num: number of SEs (shader engines) for the asic
1647 * @sh_per_se: number of SH blocks per SE for the asic
1648 *
1649 * Configures per-SE/SH RB registers (CIK).
1650 */
1651 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1652 {
1653 int i, j;
1654 u32 data;
1655 u32 active_rbs = 0;
1656 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1657 adev->gfx.config.max_sh_per_se;
1658
1659 mutex_lock(&adev->grbm_idx_mutex);
1660 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1661 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1662 gfx_v7_0_select_se_sh(adev, i, j);
1663 data = gfx_v7_0_get_rb_active_bitmap(adev);
1664 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1665 rb_bitmap_width_per_sh);
1666 }
1667 }
1668 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1669 mutex_unlock(&adev->grbm_idx_mutex);
1670
1671 adev->gfx.config.backend_enable_mask = active_rbs;
1672 adev->gfx.config.num_rbs = hweight32(active_rbs);
1673 }
1674
1675 /**
1676 * gmc_v7_0_init_compute_vmid - gart enable
1677 *
1678 * @rdev: amdgpu_device pointer
1679 *
1680 * Initialize compute vmid sh_mem registers
1681 *
1682 */
1683 #define DEFAULT_SH_MEM_BASES (0x6000)
1684 #define FIRST_COMPUTE_VMID (8)
1685 #define LAST_COMPUTE_VMID (16)
1686 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1687 {
1688 int i;
1689 uint32_t sh_mem_config;
1690 uint32_t sh_mem_bases;
1691
1692 /*
1693 * Configure apertures:
1694 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1695 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1696 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1697 */
1698 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1699 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1700 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1701 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1702 mutex_lock(&adev->srbm_mutex);
1703 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1704 cik_srbm_select(adev, 0, 0, 0, i);
1705 /* CP and shaders */
1706 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1707 WREG32(mmSH_MEM_APE1_BASE, 1);
1708 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1709 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1710 }
1711 cik_srbm_select(adev, 0, 0, 0, 0);
1712 mutex_unlock(&adev->srbm_mutex);
1713 }
1714
1715 /**
1716 * gfx_v7_0_gpu_init - setup the 3D engine
1717 *
1718 * @adev: amdgpu_device pointer
1719 *
1720 * Configures the 3D engine and tiling configuration
1721 * registers so that the 3D engine is usable.
1722 */
1723 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1724 {
1725 u32 tmp, sh_mem_cfg;
1726 int i;
1727
1728 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1729
1730 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1731 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1732 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1733
1734 gfx_v7_0_tiling_mode_table_init(adev);
1735
1736 gfx_v7_0_setup_rb(adev);
1737 gfx_v7_0_get_cu_info(adev);
1738
1739 /* set HW defaults for 3D engine */
1740 WREG32(mmCP_MEQ_THRESHOLDS,
1741 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1742 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1743
1744 mutex_lock(&adev->grbm_idx_mutex);
1745 /*
1746 * making sure that the following register writes will be broadcasted
1747 * to all the shaders
1748 */
1749 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1750
1751 /* XXX SH_MEM regs */
1752 /* where to put LDS, scratch, GPUVM in FSA64 space */
1753 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1754 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1755
1756 mutex_lock(&adev->srbm_mutex);
1757 for (i = 0; i < 16; i++) {
1758 cik_srbm_select(adev, 0, 0, 0, i);
1759 /* CP and shaders */
1760 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1761 WREG32(mmSH_MEM_APE1_BASE, 1);
1762 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1763 WREG32(mmSH_MEM_BASES, 0);
1764 }
1765 cik_srbm_select(adev, 0, 0, 0, 0);
1766 mutex_unlock(&adev->srbm_mutex);
1767
1768 gmc_v7_0_init_compute_vmid(adev);
1769
1770 WREG32(mmSX_DEBUG_1, 0x20);
1771
1772 WREG32(mmTA_CNTL_AUX, 0x00010000);
1773
1774 tmp = RREG32(mmSPI_CONFIG_CNTL);
1775 tmp |= 0x03000000;
1776 WREG32(mmSPI_CONFIG_CNTL, tmp);
1777
1778 WREG32(mmSQ_CONFIG, 1);
1779
1780 WREG32(mmDB_DEBUG, 0);
1781
1782 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1783 tmp |= 0x00000400;
1784 WREG32(mmDB_DEBUG2, tmp);
1785
1786 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1787 tmp |= 0x00020200;
1788 WREG32(mmDB_DEBUG3, tmp);
1789
1790 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1791 tmp |= 0x00018208;
1792 WREG32(mmCB_HW_CONTROL, tmp);
1793
1794 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1795
1796 WREG32(mmPA_SC_FIFO_SIZE,
1797 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1798 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1799 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1800 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1801
1802 WREG32(mmVGT_NUM_INSTANCES, 1);
1803
1804 WREG32(mmCP_PERFMON_CNTL, 0);
1805
1806 WREG32(mmSQ_CONFIG, 0);
1807
1808 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1809 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1810 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1811
1812 WREG32(mmVGT_CACHE_INVALIDATION,
1813 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1814 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1815
1816 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1817 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1818
1819 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1820 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1821 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1822 mutex_unlock(&adev->grbm_idx_mutex);
1823
1824 udelay(50);
1825 }
1826
1827 /*
1828 * GPU scratch registers helpers function.
1829 */
1830 /**
1831 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1832 *
1833 * @adev: amdgpu_device pointer
1834 *
1835 * Set up the number and offset of the CP scratch registers.
1836 * NOTE: use of CP scratch registers is a legacy inferface and
1837 * is not used by default on newer asics (r6xx+). On newer asics,
1838 * memory buffers are used for fences rather than scratch regs.
1839 */
1840 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1841 {
1842 int i;
1843
1844 adev->gfx.scratch.num_reg = 7;
1845 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1846 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1847 adev->gfx.scratch.free[i] = true;
1848 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1849 }
1850 }
1851
1852 /**
1853 * gfx_v7_0_ring_test_ring - basic gfx ring test
1854 *
1855 * @adev: amdgpu_device pointer
1856 * @ring: amdgpu_ring structure holding ring information
1857 *
1858 * Allocate a scratch register and write to it using the gfx ring (CIK).
1859 * Provides a basic gfx ring test to verify that the ring is working.
1860 * Used by gfx_v7_0_cp_gfx_resume();
1861 * Returns 0 on success, error on failure.
1862 */
1863 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1864 {
1865 struct amdgpu_device *adev = ring->adev;
1866 uint32_t scratch;
1867 uint32_t tmp = 0;
1868 unsigned i;
1869 int r;
1870
1871 r = amdgpu_gfx_scratch_get(adev, &scratch);
1872 if (r) {
1873 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1874 return r;
1875 }
1876 WREG32(scratch, 0xCAFEDEAD);
1877 r = amdgpu_ring_alloc(ring, 3);
1878 if (r) {
1879 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1880 amdgpu_gfx_scratch_free(adev, scratch);
1881 return r;
1882 }
1883 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1884 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1885 amdgpu_ring_write(ring, 0xDEADBEEF);
1886 amdgpu_ring_commit(ring);
1887
1888 for (i = 0; i < adev->usec_timeout; i++) {
1889 tmp = RREG32(scratch);
1890 if (tmp == 0xDEADBEEF)
1891 break;
1892 DRM_UDELAY(1);
1893 }
1894 if (i < adev->usec_timeout) {
1895 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1896 } else {
1897 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1898 ring->idx, scratch, tmp);
1899 r = -EINVAL;
1900 }
1901 amdgpu_gfx_scratch_free(adev, scratch);
1902 return r;
1903 }
1904
1905 /**
1906 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
1907 *
1908 * @adev: amdgpu_device pointer
1909 * @ridx: amdgpu ring index
1910 *
1911 * Emits an hdp flush on the cp.
1912 */
1913 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1914 {
1915 u32 ref_and_mask;
1916 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
1917
1918 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1919 switch (ring->me) {
1920 case 1:
1921 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1922 break;
1923 case 2:
1924 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1925 break;
1926 default:
1927 return;
1928 }
1929 } else {
1930 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1931 }
1932
1933 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1934 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1935 WAIT_REG_MEM_FUNCTION(3) | /* == */
1936 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
1937 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1938 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1939 amdgpu_ring_write(ring, ref_and_mask);
1940 amdgpu_ring_write(ring, ref_and_mask);
1941 amdgpu_ring_write(ring, 0x20); /* poll interval */
1942 }
1943
1944 /**
1945 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1946 *
1947 * @adev: amdgpu_device pointer
1948 * @ridx: amdgpu ring index
1949 *
1950 * Emits an hdp invalidate on the cp.
1951 */
1952 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1953 {
1954 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1955 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1956 WRITE_DATA_DST_SEL(0) |
1957 WR_CONFIRM));
1958 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1959 amdgpu_ring_write(ring, 0);
1960 amdgpu_ring_write(ring, 1);
1961 }
1962
1963 /**
1964 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1965 *
1966 * @adev: amdgpu_device pointer
1967 * @fence: amdgpu fence object
1968 *
1969 * Emits a fence sequnce number on the gfx ring and flushes
1970 * GPU caches.
1971 */
1972 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
1973 u64 seq, unsigned flags)
1974 {
1975 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1976 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1977 /* Workaround for cache flush problems. First send a dummy EOP
1978 * event down the pipe with seq one below.
1979 */
1980 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1981 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1982 EOP_TC_ACTION_EN |
1983 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1984 EVENT_INDEX(5)));
1985 amdgpu_ring_write(ring, addr & 0xfffffffc);
1986 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1987 DATA_SEL(1) | INT_SEL(0));
1988 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1989 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1990
1991 /* Then send the real EOP event down the pipe. */
1992 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1993 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1994 EOP_TC_ACTION_EN |
1995 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1996 EVENT_INDEX(5)));
1997 amdgpu_ring_write(ring, addr & 0xfffffffc);
1998 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1999 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2000 amdgpu_ring_write(ring, lower_32_bits(seq));
2001 amdgpu_ring_write(ring, upper_32_bits(seq));
2002 }
2003
2004 /**
2005 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2006 *
2007 * @adev: amdgpu_device pointer
2008 * @fence: amdgpu fence object
2009 *
2010 * Emits a fence sequnce number on the compute ring and flushes
2011 * GPU caches.
2012 */
2013 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2014 u64 addr, u64 seq,
2015 unsigned flags)
2016 {
2017 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2018 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2019
2020 /* RELEASE_MEM - flush caches, send int */
2021 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2022 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2023 EOP_TC_ACTION_EN |
2024 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2025 EVENT_INDEX(5)));
2026 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2027 amdgpu_ring_write(ring, addr & 0xfffffffc);
2028 amdgpu_ring_write(ring, upper_32_bits(addr));
2029 amdgpu_ring_write(ring, lower_32_bits(seq));
2030 amdgpu_ring_write(ring, upper_32_bits(seq));
2031 }
2032
2033 /*
2034 * IB stuff
2035 */
2036 /**
2037 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2038 *
2039 * @ring: amdgpu_ring structure holding ring information
2040 * @ib: amdgpu indirect buffer object
2041 *
2042 * Emits an DE (drawing engine) or CE (constant engine) IB
2043 * on the gfx ring. IBs are usually generated by userspace
2044 * acceleration drivers and submitted to the kernel for
2045 * sheduling on the ring. This function schedules the IB
2046 * on the gfx ring for execution by the GPU.
2047 */
2048 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2049 struct amdgpu_ib *ib,
2050 unsigned vm_id, bool ctx_switch)
2051 {
2052 u32 header, control = 0;
2053 u32 next_rptr = ring->wptr + 5;
2054
2055 if (ctx_switch)
2056 next_rptr += 2;
2057
2058 next_rptr += 4;
2059 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2060 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2061 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2062 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2063 amdgpu_ring_write(ring, next_rptr);
2064
2065 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2066 if (ctx_switch) {
2067 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2068 amdgpu_ring_write(ring, 0);
2069 }
2070
2071 if (ib->flags & AMDGPU_IB_FLAG_CE)
2072 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2073 else
2074 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2075
2076 control |= ib->length_dw | (vm_id << 24);
2077
2078 amdgpu_ring_write(ring, header);
2079 amdgpu_ring_write(ring,
2080 #ifdef __BIG_ENDIAN
2081 (2 << 0) |
2082 #endif
2083 (ib->gpu_addr & 0xFFFFFFFC));
2084 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2085 amdgpu_ring_write(ring, control);
2086 }
2087
2088 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2089 struct amdgpu_ib *ib,
2090 unsigned vm_id, bool ctx_switch)
2091 {
2092 u32 header, control = 0;
2093 u32 next_rptr = ring->wptr + 5;
2094
2095 control |= INDIRECT_BUFFER_VALID;
2096 next_rptr += 4;
2097 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2098 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2099 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2100 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2101 amdgpu_ring_write(ring, next_rptr);
2102
2103 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2104
2105 control |= ib->length_dw | (vm_id << 24);
2106
2107 amdgpu_ring_write(ring, header);
2108 amdgpu_ring_write(ring,
2109 #ifdef __BIG_ENDIAN
2110 (2 << 0) |
2111 #endif
2112 (ib->gpu_addr & 0xFFFFFFFC));
2113 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2114 amdgpu_ring_write(ring, control);
2115 }
2116
2117 /**
2118 * gfx_v7_0_ring_test_ib - basic ring IB test
2119 *
2120 * @ring: amdgpu_ring structure holding ring information
2121 *
2122 * Allocate an IB and execute it on the gfx ring (CIK).
2123 * Provides a basic gfx ring test to verify that IBs are working.
2124 * Returns 0 on success, error on failure.
2125 */
2126 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2127 {
2128 struct amdgpu_device *adev = ring->adev;
2129 struct amdgpu_ib ib;
2130 struct fence *f = NULL;
2131 uint32_t scratch;
2132 uint32_t tmp = 0;
2133 unsigned i;
2134 int r;
2135
2136 r = amdgpu_gfx_scratch_get(adev, &scratch);
2137 if (r) {
2138 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2139 return r;
2140 }
2141 WREG32(scratch, 0xCAFEDEAD);
2142 memset(&ib, 0, sizeof(ib));
2143 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2144 if (r) {
2145 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
2146 goto err1;
2147 }
2148 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2149 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2150 ib.ptr[2] = 0xDEADBEEF;
2151 ib.length_dw = 3;
2152
2153 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
2154 if (r)
2155 goto err2;
2156
2157 r = fence_wait(f, false);
2158 if (r) {
2159 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2160 goto err2;
2161 }
2162 for (i = 0; i < adev->usec_timeout; i++) {
2163 tmp = RREG32(scratch);
2164 if (tmp == 0xDEADBEEF)
2165 break;
2166 DRM_UDELAY(1);
2167 }
2168 if (i < adev->usec_timeout) {
2169 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2170 ring->idx, i);
2171 goto err2;
2172 } else {
2173 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2174 scratch, tmp);
2175 r = -EINVAL;
2176 }
2177
2178 err2:
2179 fence_put(f);
2180 amdgpu_ib_free(adev, &ib, NULL);
2181 fence_put(f);
2182 err1:
2183 amdgpu_gfx_scratch_free(adev, scratch);
2184 return r;
2185 }
2186
2187 /*
2188 * CP.
2189 * On CIK, gfx and compute now have independant command processors.
2190 *
2191 * GFX
2192 * Gfx consists of a single ring and can process both gfx jobs and
2193 * compute jobs. The gfx CP consists of three microengines (ME):
2194 * PFP - Pre-Fetch Parser
2195 * ME - Micro Engine
2196 * CE - Constant Engine
2197 * The PFP and ME make up what is considered the Drawing Engine (DE).
2198 * The CE is an asynchronous engine used for updating buffer desciptors
2199 * used by the DE so that they can be loaded into cache in parallel
2200 * while the DE is processing state update packets.
2201 *
2202 * Compute
2203 * The compute CP consists of two microengines (ME):
2204 * MEC1 - Compute MicroEngine 1
2205 * MEC2 - Compute MicroEngine 2
2206 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2207 * The queues are exposed to userspace and are programmed directly
2208 * by the compute runtime.
2209 */
2210 /**
2211 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2212 *
2213 * @adev: amdgpu_device pointer
2214 * @enable: enable or disable the MEs
2215 *
2216 * Halts or unhalts the gfx MEs.
2217 */
2218 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2219 {
2220 int i;
2221
2222 if (enable) {
2223 WREG32(mmCP_ME_CNTL, 0);
2224 } else {
2225 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2226 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2227 adev->gfx.gfx_ring[i].ready = false;
2228 }
2229 udelay(50);
2230 }
2231
2232 /**
2233 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2234 *
2235 * @adev: amdgpu_device pointer
2236 *
2237 * Loads the gfx PFP, ME, and CE ucode.
2238 * Returns 0 for success, -EINVAL if the ucode is not available.
2239 */
2240 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2241 {
2242 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2243 const struct gfx_firmware_header_v1_0 *ce_hdr;
2244 const struct gfx_firmware_header_v1_0 *me_hdr;
2245 const __le32 *fw_data;
2246 unsigned i, fw_size;
2247
2248 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2249 return -EINVAL;
2250
2251 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2252 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2253 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2254
2255 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2256 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2257 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2258 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2259 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2260 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2261 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2262 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2263 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2264
2265 gfx_v7_0_cp_gfx_enable(adev, false);
2266
2267 /* PFP */
2268 fw_data = (const __le32 *)
2269 (adev->gfx.pfp_fw->data +
2270 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2271 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2272 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2273 for (i = 0; i < fw_size; i++)
2274 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2275 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2276
2277 /* CE */
2278 fw_data = (const __le32 *)
2279 (adev->gfx.ce_fw->data +
2280 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2281 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2282 WREG32(mmCP_CE_UCODE_ADDR, 0);
2283 for (i = 0; i < fw_size; i++)
2284 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2285 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2286
2287 /* ME */
2288 fw_data = (const __le32 *)
2289 (adev->gfx.me_fw->data +
2290 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2291 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2292 WREG32(mmCP_ME_RAM_WADDR, 0);
2293 for (i = 0; i < fw_size; i++)
2294 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2295 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2296
2297 return 0;
2298 }
2299
2300 /**
2301 * gfx_v7_0_cp_gfx_start - start the gfx ring
2302 *
2303 * @adev: amdgpu_device pointer
2304 *
2305 * Enables the ring and loads the clear state context and other
2306 * packets required to init the ring.
2307 * Returns 0 for success, error for failure.
2308 */
2309 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2310 {
2311 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2312 const struct cs_section_def *sect = NULL;
2313 const struct cs_extent_def *ext = NULL;
2314 int r, i;
2315
2316 /* init the CP */
2317 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2318 WREG32(mmCP_ENDIAN_SWAP, 0);
2319 WREG32(mmCP_DEVICE_ID, 1);
2320
2321 gfx_v7_0_cp_gfx_enable(adev, true);
2322
2323 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2324 if (r) {
2325 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2326 return r;
2327 }
2328
2329 /* init the CE partitions. CE only used for gfx on CIK */
2330 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2331 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2332 amdgpu_ring_write(ring, 0x8000);
2333 amdgpu_ring_write(ring, 0x8000);
2334
2335 /* clear state buffer */
2336 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2337 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2338
2339 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2340 amdgpu_ring_write(ring, 0x80000000);
2341 amdgpu_ring_write(ring, 0x80000000);
2342
2343 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2344 for (ext = sect->section; ext->extent != NULL; ++ext) {
2345 if (sect->id == SECT_CONTEXT) {
2346 amdgpu_ring_write(ring,
2347 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2348 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2349 for (i = 0; i < ext->reg_count; i++)
2350 amdgpu_ring_write(ring, ext->extent[i]);
2351 }
2352 }
2353 }
2354
2355 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2356 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2357 switch (adev->asic_type) {
2358 case CHIP_BONAIRE:
2359 amdgpu_ring_write(ring, 0x16000012);
2360 amdgpu_ring_write(ring, 0x00000000);
2361 break;
2362 case CHIP_KAVERI:
2363 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2364 amdgpu_ring_write(ring, 0x00000000);
2365 break;
2366 case CHIP_KABINI:
2367 case CHIP_MULLINS:
2368 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2369 amdgpu_ring_write(ring, 0x00000000);
2370 break;
2371 case CHIP_HAWAII:
2372 amdgpu_ring_write(ring, 0x3a00161a);
2373 amdgpu_ring_write(ring, 0x0000002e);
2374 break;
2375 default:
2376 amdgpu_ring_write(ring, 0x00000000);
2377 amdgpu_ring_write(ring, 0x00000000);
2378 break;
2379 }
2380
2381 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2382 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2383
2384 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2385 amdgpu_ring_write(ring, 0);
2386
2387 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2388 amdgpu_ring_write(ring, 0x00000316);
2389 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2390 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2391
2392 amdgpu_ring_commit(ring);
2393
2394 return 0;
2395 }
2396
2397 /**
2398 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2399 *
2400 * @adev: amdgpu_device pointer
2401 *
2402 * Program the location and size of the gfx ring buffer
2403 * and test it to make sure it's working.
2404 * Returns 0 for success, error for failure.
2405 */
2406 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2407 {
2408 struct amdgpu_ring *ring;
2409 u32 tmp;
2410 u32 rb_bufsz;
2411 u64 rb_addr, rptr_addr;
2412 int r;
2413
2414 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2415 if (adev->asic_type != CHIP_HAWAII)
2416 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2417
2418 /* Set the write pointer delay */
2419 WREG32(mmCP_RB_WPTR_DELAY, 0);
2420
2421 /* set the RB to use vmid 0 */
2422 WREG32(mmCP_RB_VMID, 0);
2423
2424 WREG32(mmSCRATCH_ADDR, 0);
2425
2426 /* ring 0 - compute and gfx */
2427 /* Set ring buffer size */
2428 ring = &adev->gfx.gfx_ring[0];
2429 rb_bufsz = order_base_2(ring->ring_size / 8);
2430 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2431 #ifdef __BIG_ENDIAN
2432 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2433 #endif
2434 WREG32(mmCP_RB0_CNTL, tmp);
2435
2436 /* Initialize the ring buffer's read and write pointers */
2437 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2438 ring->wptr = 0;
2439 WREG32(mmCP_RB0_WPTR, ring->wptr);
2440
2441 /* set the wb address wether it's enabled or not */
2442 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2443 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2444 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2445
2446 /* scratch register shadowing is no longer supported */
2447 WREG32(mmSCRATCH_UMSK, 0);
2448
2449 mdelay(1);
2450 WREG32(mmCP_RB0_CNTL, tmp);
2451
2452 rb_addr = ring->gpu_addr >> 8;
2453 WREG32(mmCP_RB0_BASE, rb_addr);
2454 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2455
2456 /* start the ring */
2457 gfx_v7_0_cp_gfx_start(adev);
2458 ring->ready = true;
2459 r = amdgpu_ring_test_ring(ring);
2460 if (r) {
2461 ring->ready = false;
2462 return r;
2463 }
2464
2465 return 0;
2466 }
2467
2468 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2469 {
2470 return ring->adev->wb.wb[ring->rptr_offs];
2471 }
2472
2473 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2474 {
2475 struct amdgpu_device *adev = ring->adev;
2476
2477 return RREG32(mmCP_RB0_WPTR);
2478 }
2479
2480 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2481 {
2482 struct amdgpu_device *adev = ring->adev;
2483
2484 WREG32(mmCP_RB0_WPTR, ring->wptr);
2485 (void)RREG32(mmCP_RB0_WPTR);
2486 }
2487
2488 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2489 {
2490 return ring->adev->wb.wb[ring->rptr_offs];
2491 }
2492
2493 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2494 {
2495 /* XXX check if swapping is necessary on BE */
2496 return ring->adev->wb.wb[ring->wptr_offs];
2497 }
2498
2499 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2500 {
2501 struct amdgpu_device *adev = ring->adev;
2502
2503 /* XXX check if swapping is necessary on BE */
2504 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2505 WDOORBELL32(ring->doorbell_index, ring->wptr);
2506 }
2507
2508 /**
2509 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2510 *
2511 * @adev: amdgpu_device pointer
2512 * @enable: enable or disable the MEs
2513 *
2514 * Halts or unhalts the compute MEs.
2515 */
2516 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2517 {
2518 int i;
2519
2520 if (enable) {
2521 WREG32(mmCP_MEC_CNTL, 0);
2522 } else {
2523 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2524 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2525 adev->gfx.compute_ring[i].ready = false;
2526 }
2527 udelay(50);
2528 }
2529
2530 /**
2531 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2532 *
2533 * @adev: amdgpu_device pointer
2534 *
2535 * Loads the compute MEC1&2 ucode.
2536 * Returns 0 for success, -EINVAL if the ucode is not available.
2537 */
2538 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2539 {
2540 const struct gfx_firmware_header_v1_0 *mec_hdr;
2541 const __le32 *fw_data;
2542 unsigned i, fw_size;
2543
2544 if (!adev->gfx.mec_fw)
2545 return -EINVAL;
2546
2547 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2548 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2549 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2550 adev->gfx.mec_feature_version = le32_to_cpu(
2551 mec_hdr->ucode_feature_version);
2552
2553 gfx_v7_0_cp_compute_enable(adev, false);
2554
2555 /* MEC1 */
2556 fw_data = (const __le32 *)
2557 (adev->gfx.mec_fw->data +
2558 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2559 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2560 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2561 for (i = 0; i < fw_size; i++)
2562 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2563 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2564
2565 if (adev->asic_type == CHIP_KAVERI) {
2566 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2567
2568 if (!adev->gfx.mec2_fw)
2569 return -EINVAL;
2570
2571 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2572 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2573 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2574 adev->gfx.mec2_feature_version = le32_to_cpu(
2575 mec2_hdr->ucode_feature_version);
2576
2577 /* MEC2 */
2578 fw_data = (const __le32 *)
2579 (adev->gfx.mec2_fw->data +
2580 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2581 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2582 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2583 for (i = 0; i < fw_size; i++)
2584 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2585 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2586 }
2587
2588 return 0;
2589 }
2590
2591 /**
2592 * gfx_v7_0_cp_compute_fini - stop the compute queues
2593 *
2594 * @adev: amdgpu_device pointer
2595 *
2596 * Stop the compute queues and tear down the driver queue
2597 * info.
2598 */
2599 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2600 {
2601 int i, r;
2602
2603 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2604 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2605
2606 if (ring->mqd_obj) {
2607 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2608 if (unlikely(r != 0))
2609 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2610
2611 amdgpu_bo_unpin(ring->mqd_obj);
2612 amdgpu_bo_unreserve(ring->mqd_obj);
2613
2614 amdgpu_bo_unref(&ring->mqd_obj);
2615 ring->mqd_obj = NULL;
2616 }
2617 }
2618 }
2619
2620 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2621 {
2622 int r;
2623
2624 if (adev->gfx.mec.hpd_eop_obj) {
2625 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2626 if (unlikely(r != 0))
2627 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2628 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2629 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2630
2631 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2632 adev->gfx.mec.hpd_eop_obj = NULL;
2633 }
2634 }
2635
2636 #define MEC_HPD_SIZE 2048
2637
2638 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2639 {
2640 int r;
2641 u32 *hpd;
2642
2643 /*
2644 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2645 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2646 * Nonetheless, we assign only 1 pipe because all other pipes will
2647 * be handled by KFD
2648 */
2649 adev->gfx.mec.num_mec = 1;
2650 adev->gfx.mec.num_pipe = 1;
2651 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2652
2653 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2654 r = amdgpu_bo_create(adev,
2655 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2656 PAGE_SIZE, true,
2657 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2658 &adev->gfx.mec.hpd_eop_obj);
2659 if (r) {
2660 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2661 return r;
2662 }
2663 }
2664
2665 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2666 if (unlikely(r != 0)) {
2667 gfx_v7_0_mec_fini(adev);
2668 return r;
2669 }
2670 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2671 &adev->gfx.mec.hpd_eop_gpu_addr);
2672 if (r) {
2673 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2674 gfx_v7_0_mec_fini(adev);
2675 return r;
2676 }
2677 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2678 if (r) {
2679 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2680 gfx_v7_0_mec_fini(adev);
2681 return r;
2682 }
2683
2684 /* clear memory. Not sure if this is required or not */
2685 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2686
2687 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2688 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2689
2690 return 0;
2691 }
2692
2693 struct hqd_registers
2694 {
2695 u32 cp_mqd_base_addr;
2696 u32 cp_mqd_base_addr_hi;
2697 u32 cp_hqd_active;
2698 u32 cp_hqd_vmid;
2699 u32 cp_hqd_persistent_state;
2700 u32 cp_hqd_pipe_priority;
2701 u32 cp_hqd_queue_priority;
2702 u32 cp_hqd_quantum;
2703 u32 cp_hqd_pq_base;
2704 u32 cp_hqd_pq_base_hi;
2705 u32 cp_hqd_pq_rptr;
2706 u32 cp_hqd_pq_rptr_report_addr;
2707 u32 cp_hqd_pq_rptr_report_addr_hi;
2708 u32 cp_hqd_pq_wptr_poll_addr;
2709 u32 cp_hqd_pq_wptr_poll_addr_hi;
2710 u32 cp_hqd_pq_doorbell_control;
2711 u32 cp_hqd_pq_wptr;
2712 u32 cp_hqd_pq_control;
2713 u32 cp_hqd_ib_base_addr;
2714 u32 cp_hqd_ib_base_addr_hi;
2715 u32 cp_hqd_ib_rptr;
2716 u32 cp_hqd_ib_control;
2717 u32 cp_hqd_iq_timer;
2718 u32 cp_hqd_iq_rptr;
2719 u32 cp_hqd_dequeue_request;
2720 u32 cp_hqd_dma_offload;
2721 u32 cp_hqd_sema_cmd;
2722 u32 cp_hqd_msg_type;
2723 u32 cp_hqd_atomic0_preop_lo;
2724 u32 cp_hqd_atomic0_preop_hi;
2725 u32 cp_hqd_atomic1_preop_lo;
2726 u32 cp_hqd_atomic1_preop_hi;
2727 u32 cp_hqd_hq_scheduler0;
2728 u32 cp_hqd_hq_scheduler1;
2729 u32 cp_mqd_control;
2730 };
2731
2732 struct bonaire_mqd
2733 {
2734 u32 header;
2735 u32 dispatch_initiator;
2736 u32 dimensions[3];
2737 u32 start_idx[3];
2738 u32 num_threads[3];
2739 u32 pipeline_stat_enable;
2740 u32 perf_counter_enable;
2741 u32 pgm[2];
2742 u32 tba[2];
2743 u32 tma[2];
2744 u32 pgm_rsrc[2];
2745 u32 vmid;
2746 u32 resource_limits;
2747 u32 static_thread_mgmt01[2];
2748 u32 tmp_ring_size;
2749 u32 static_thread_mgmt23[2];
2750 u32 restart[3];
2751 u32 thread_trace_enable;
2752 u32 reserved1;
2753 u32 user_data[16];
2754 u32 vgtcs_invoke_count[2];
2755 struct hqd_registers queue_state;
2756 u32 dequeue_cntr;
2757 u32 interrupt_queue[64];
2758 };
2759
2760 /**
2761 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2762 *
2763 * @adev: amdgpu_device pointer
2764 *
2765 * Program the compute queues and test them to make sure they
2766 * are working.
2767 * Returns 0 for success, error for failure.
2768 */
2769 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2770 {
2771 int r, i, j;
2772 u32 tmp;
2773 bool use_doorbell = true;
2774 u64 hqd_gpu_addr;
2775 u64 mqd_gpu_addr;
2776 u64 eop_gpu_addr;
2777 u64 wb_gpu_addr;
2778 u32 *buf;
2779 struct bonaire_mqd *mqd;
2780
2781 gfx_v7_0_cp_compute_enable(adev, true);
2782
2783 /* fix up chicken bits */
2784 tmp = RREG32(mmCP_CPF_DEBUG);
2785 tmp |= (1 << 23);
2786 WREG32(mmCP_CPF_DEBUG, tmp);
2787
2788 /* init the pipes */
2789 mutex_lock(&adev->srbm_mutex);
2790 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2791 int me = (i < 4) ? 1 : 2;
2792 int pipe = (i < 4) ? i : (i - 4);
2793
2794 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2795
2796 cik_srbm_select(adev, me, pipe, 0, 0);
2797
2798 /* write the EOP addr */
2799 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2800 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2801
2802 /* set the VMID assigned */
2803 WREG32(mmCP_HPD_EOP_VMID, 0);
2804
2805 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2806 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2807 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2808 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2809 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2810 }
2811 cik_srbm_select(adev, 0, 0, 0, 0);
2812 mutex_unlock(&adev->srbm_mutex);
2813
2814 /* init the queues. Just two for now. */
2815 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2816 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2817
2818 if (ring->mqd_obj == NULL) {
2819 r = amdgpu_bo_create(adev,
2820 sizeof(struct bonaire_mqd),
2821 PAGE_SIZE, true,
2822 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2823 &ring->mqd_obj);
2824 if (r) {
2825 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2826 return r;
2827 }
2828 }
2829
2830 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2831 if (unlikely(r != 0)) {
2832 gfx_v7_0_cp_compute_fini(adev);
2833 return r;
2834 }
2835 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2836 &mqd_gpu_addr);
2837 if (r) {
2838 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2839 gfx_v7_0_cp_compute_fini(adev);
2840 return r;
2841 }
2842 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2843 if (r) {
2844 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2845 gfx_v7_0_cp_compute_fini(adev);
2846 return r;
2847 }
2848
2849 /* init the mqd struct */
2850 memset(buf, 0, sizeof(struct bonaire_mqd));
2851
2852 mqd = (struct bonaire_mqd *)buf;
2853 mqd->header = 0xC0310800;
2854 mqd->static_thread_mgmt01[0] = 0xffffffff;
2855 mqd->static_thread_mgmt01[1] = 0xffffffff;
2856 mqd->static_thread_mgmt23[0] = 0xffffffff;
2857 mqd->static_thread_mgmt23[1] = 0xffffffff;
2858
2859 mutex_lock(&adev->srbm_mutex);
2860 cik_srbm_select(adev, ring->me,
2861 ring->pipe,
2862 ring->queue, 0);
2863
2864 /* disable wptr polling */
2865 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2866 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2867 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2868
2869 /* enable doorbell? */
2870 mqd->queue_state.cp_hqd_pq_doorbell_control =
2871 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2872 if (use_doorbell)
2873 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2874 else
2875 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2876 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2877 mqd->queue_state.cp_hqd_pq_doorbell_control);
2878
2879 /* disable the queue if it's active */
2880 mqd->queue_state.cp_hqd_dequeue_request = 0;
2881 mqd->queue_state.cp_hqd_pq_rptr = 0;
2882 mqd->queue_state.cp_hqd_pq_wptr= 0;
2883 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2884 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2885 for (j = 0; j < adev->usec_timeout; j++) {
2886 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2887 break;
2888 udelay(1);
2889 }
2890 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2891 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2892 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2893 }
2894
2895 /* set the pointer to the MQD */
2896 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2897 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2898 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2899 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2900 /* set MQD vmid to 0 */
2901 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2902 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2903 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2904
2905 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2906 hqd_gpu_addr = ring->gpu_addr >> 8;
2907 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2908 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2909 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2910 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2911
2912 /* set up the HQD, this is similar to CP_RB0_CNTL */
2913 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2914 mqd->queue_state.cp_hqd_pq_control &=
2915 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2916 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2917
2918 mqd->queue_state.cp_hqd_pq_control |=
2919 order_base_2(ring->ring_size / 8);
2920 mqd->queue_state.cp_hqd_pq_control |=
2921 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2922 #ifdef __BIG_ENDIAN
2923 mqd->queue_state.cp_hqd_pq_control |=
2924 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2925 #endif
2926 mqd->queue_state.cp_hqd_pq_control &=
2927 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2928 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2929 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2930 mqd->queue_state.cp_hqd_pq_control |=
2931 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2932 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2933 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2934
2935 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2936 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2937 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2938 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2939 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2940 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2941 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2942
2943 /* set the wb address wether it's enabled or not */
2944 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2945 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2946 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2947 upper_32_bits(wb_gpu_addr) & 0xffff;
2948 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2949 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2950 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2951 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2952
2953 /* enable the doorbell if requested */
2954 if (use_doorbell) {
2955 mqd->queue_state.cp_hqd_pq_doorbell_control =
2956 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2957 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2958 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2959 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2960 (ring->doorbell_index <<
2961 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2962 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2963 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2964 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2965 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2966 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2967
2968 } else {
2969 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2970 }
2971 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2972 mqd->queue_state.cp_hqd_pq_doorbell_control);
2973
2974 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2975 ring->wptr = 0;
2976 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2977 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2978 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2979
2980 /* set the vmid for the queue */
2981 mqd->queue_state.cp_hqd_vmid = 0;
2982 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2983
2984 /* activate the queue */
2985 mqd->queue_state.cp_hqd_active = 1;
2986 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2987
2988 cik_srbm_select(adev, 0, 0, 0, 0);
2989 mutex_unlock(&adev->srbm_mutex);
2990
2991 amdgpu_bo_kunmap(ring->mqd_obj);
2992 amdgpu_bo_unreserve(ring->mqd_obj);
2993
2994 ring->ready = true;
2995 r = amdgpu_ring_test_ring(ring);
2996 if (r)
2997 ring->ready = false;
2998 }
2999
3000 return 0;
3001 }
3002
3003 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3004 {
3005 gfx_v7_0_cp_gfx_enable(adev, enable);
3006 gfx_v7_0_cp_compute_enable(adev, enable);
3007 }
3008
3009 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3010 {
3011 int r;
3012
3013 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3014 if (r)
3015 return r;
3016 r = gfx_v7_0_cp_compute_load_microcode(adev);
3017 if (r)
3018 return r;
3019
3020 return 0;
3021 }
3022
3023 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3024 bool enable)
3025 {
3026 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3027
3028 if (enable)
3029 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3030 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3031 else
3032 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3033 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3034 WREG32(mmCP_INT_CNTL_RING0, tmp);
3035 }
3036
3037 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3038 {
3039 int r;
3040
3041 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3042
3043 r = gfx_v7_0_cp_load_microcode(adev);
3044 if (r)
3045 return r;
3046
3047 r = gfx_v7_0_cp_gfx_resume(adev);
3048 if (r)
3049 return r;
3050 r = gfx_v7_0_cp_compute_resume(adev);
3051 if (r)
3052 return r;
3053
3054 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3055
3056 return 0;
3057 }
3058
3059 /**
3060 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3061 *
3062 * @ring: the ring to emmit the commands to
3063 *
3064 * Sync the command pipeline with the PFP. E.g. wait for everything
3065 * to be completed.
3066 */
3067 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3068 {
3069 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3070 uint32_t seq = ring->fence_drv.sync_seq;
3071 uint64_t addr = ring->fence_drv.gpu_addr;
3072
3073 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3074 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3075 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3076 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3077 amdgpu_ring_write(ring, addr & 0xfffffffc);
3078 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3079 amdgpu_ring_write(ring, seq);
3080 amdgpu_ring_write(ring, 0xffffffff);
3081 amdgpu_ring_write(ring, 4); /* poll interval */
3082
3083 if (usepfp) {
3084 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3085 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3086 amdgpu_ring_write(ring, 0);
3087 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3088 amdgpu_ring_write(ring, 0);
3089 }
3090 }
3091
3092 /*
3093 * vm
3094 * VMID 0 is the physical GPU addresses as used by the kernel.
3095 * VMIDs 1-15 are used for userspace clients and are handled
3096 * by the amdgpu vm/hsa code.
3097 */
3098 /**
3099 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3100 *
3101 * @adev: amdgpu_device pointer
3102 *
3103 * Update the page table base and flush the VM TLB
3104 * using the CP (CIK).
3105 */
3106 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3107 unsigned vm_id, uint64_t pd_addr)
3108 {
3109 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3110
3111 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3112 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3113 WRITE_DATA_DST_SEL(0)));
3114 if (vm_id < 8) {
3115 amdgpu_ring_write(ring,
3116 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3117 } else {
3118 amdgpu_ring_write(ring,
3119 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3120 }
3121 amdgpu_ring_write(ring, 0);
3122 amdgpu_ring_write(ring, pd_addr >> 12);
3123
3124 /* bits 0-15 are the VM contexts0-15 */
3125 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3126 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3127 WRITE_DATA_DST_SEL(0)));
3128 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3129 amdgpu_ring_write(ring, 0);
3130 amdgpu_ring_write(ring, 1 << vm_id);
3131
3132 /* wait for the invalidate to complete */
3133 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3134 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3135 WAIT_REG_MEM_FUNCTION(0) | /* always */
3136 WAIT_REG_MEM_ENGINE(0))); /* me */
3137 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3138 amdgpu_ring_write(ring, 0);
3139 amdgpu_ring_write(ring, 0); /* ref */
3140 amdgpu_ring_write(ring, 0); /* mask */
3141 amdgpu_ring_write(ring, 0x20); /* poll interval */
3142
3143 /* compute doesn't have PFP */
3144 if (usepfp) {
3145 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3146 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3147 amdgpu_ring_write(ring, 0x0);
3148
3149 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3150 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3151 amdgpu_ring_write(ring, 0);
3152 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3153 amdgpu_ring_write(ring, 0);
3154 }
3155 }
3156
3157 /*
3158 * RLC
3159 * The RLC is a multi-purpose microengine that handles a
3160 * variety of functions.
3161 */
3162 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3163 {
3164 int r;
3165
3166 /* save restore block */
3167 if (adev->gfx.rlc.save_restore_obj) {
3168 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3169 if (unlikely(r != 0))
3170 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3171 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3172 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3173
3174 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3175 adev->gfx.rlc.save_restore_obj = NULL;
3176 }
3177
3178 /* clear state block */
3179 if (adev->gfx.rlc.clear_state_obj) {
3180 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3181 if (unlikely(r != 0))
3182 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3183 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3184 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3185
3186 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3187 adev->gfx.rlc.clear_state_obj = NULL;
3188 }
3189
3190 /* clear state block */
3191 if (adev->gfx.rlc.cp_table_obj) {
3192 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3193 if (unlikely(r != 0))
3194 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3195 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3196 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3197
3198 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3199 adev->gfx.rlc.cp_table_obj = NULL;
3200 }
3201 }
3202
3203 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3204 {
3205 const u32 *src_ptr;
3206 volatile u32 *dst_ptr;
3207 u32 dws, i;
3208 const struct cs_section_def *cs_data;
3209 int r;
3210
3211 /* allocate rlc buffers */
3212 if (adev->flags & AMD_IS_APU) {
3213 if (adev->asic_type == CHIP_KAVERI) {
3214 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3215 adev->gfx.rlc.reg_list_size =
3216 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3217 } else {
3218 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3219 adev->gfx.rlc.reg_list_size =
3220 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3221 }
3222 }
3223 adev->gfx.rlc.cs_data = ci_cs_data;
3224 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3225 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3226
3227 src_ptr = adev->gfx.rlc.reg_list;
3228 dws = adev->gfx.rlc.reg_list_size;
3229 dws += (5 * 16) + 48 + 48 + 64;
3230
3231 cs_data = adev->gfx.rlc.cs_data;
3232
3233 if (src_ptr) {
3234 /* save restore block */
3235 if (adev->gfx.rlc.save_restore_obj == NULL) {
3236 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3237 AMDGPU_GEM_DOMAIN_VRAM,
3238 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3239 NULL, NULL,
3240 &adev->gfx.rlc.save_restore_obj);
3241 if (r) {
3242 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3243 return r;
3244 }
3245 }
3246
3247 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3248 if (unlikely(r != 0)) {
3249 gfx_v7_0_rlc_fini(adev);
3250 return r;
3251 }
3252 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3253 &adev->gfx.rlc.save_restore_gpu_addr);
3254 if (r) {
3255 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3256 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3257 gfx_v7_0_rlc_fini(adev);
3258 return r;
3259 }
3260
3261 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3262 if (r) {
3263 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3264 gfx_v7_0_rlc_fini(adev);
3265 return r;
3266 }
3267 /* write the sr buffer */
3268 dst_ptr = adev->gfx.rlc.sr_ptr;
3269 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3270 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3271 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3272 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3273 }
3274
3275 if (cs_data) {
3276 /* clear state block */
3277 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3278
3279 if (adev->gfx.rlc.clear_state_obj == NULL) {
3280 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3281 AMDGPU_GEM_DOMAIN_VRAM,
3282 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3283 NULL, NULL,
3284 &adev->gfx.rlc.clear_state_obj);
3285 if (r) {
3286 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3287 gfx_v7_0_rlc_fini(adev);
3288 return r;
3289 }
3290 }
3291 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3292 if (unlikely(r != 0)) {
3293 gfx_v7_0_rlc_fini(adev);
3294 return r;
3295 }
3296 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3297 &adev->gfx.rlc.clear_state_gpu_addr);
3298 if (r) {
3299 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3300 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3301 gfx_v7_0_rlc_fini(adev);
3302 return r;
3303 }
3304
3305 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3306 if (r) {
3307 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3308 gfx_v7_0_rlc_fini(adev);
3309 return r;
3310 }
3311 /* set up the cs buffer */
3312 dst_ptr = adev->gfx.rlc.cs_ptr;
3313 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3314 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3315 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3316 }
3317
3318 if (adev->gfx.rlc.cp_table_size) {
3319 if (adev->gfx.rlc.cp_table_obj == NULL) {
3320 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3321 AMDGPU_GEM_DOMAIN_VRAM,
3322 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3323 NULL, NULL,
3324 &adev->gfx.rlc.cp_table_obj);
3325 if (r) {
3326 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3327 gfx_v7_0_rlc_fini(adev);
3328 return r;
3329 }
3330 }
3331
3332 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3333 if (unlikely(r != 0)) {
3334 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3335 gfx_v7_0_rlc_fini(adev);
3336 return r;
3337 }
3338 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3339 &adev->gfx.rlc.cp_table_gpu_addr);
3340 if (r) {
3341 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3342 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3343 gfx_v7_0_rlc_fini(adev);
3344 return r;
3345 }
3346 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3347 if (r) {
3348 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3349 gfx_v7_0_rlc_fini(adev);
3350 return r;
3351 }
3352
3353 gfx_v7_0_init_cp_pg_table(adev);
3354
3355 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3356 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3357
3358 }
3359
3360 return 0;
3361 }
3362
3363 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3364 {
3365 u32 tmp;
3366
3367 tmp = RREG32(mmRLC_LB_CNTL);
3368 if (enable)
3369 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3370 else
3371 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3372 WREG32(mmRLC_LB_CNTL, tmp);
3373 }
3374
3375 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3376 {
3377 u32 i, j, k;
3378 u32 mask;
3379
3380 mutex_lock(&adev->grbm_idx_mutex);
3381 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3382 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3383 gfx_v7_0_select_se_sh(adev, i, j);
3384 for (k = 0; k < adev->usec_timeout; k++) {
3385 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3386 break;
3387 udelay(1);
3388 }
3389 }
3390 }
3391 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3392 mutex_unlock(&adev->grbm_idx_mutex);
3393
3394 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3395 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3396 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3397 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3398 for (k = 0; k < adev->usec_timeout; k++) {
3399 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3400 break;
3401 udelay(1);
3402 }
3403 }
3404
3405 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3406 {
3407 u32 tmp;
3408
3409 tmp = RREG32(mmRLC_CNTL);
3410 if (tmp != rlc)
3411 WREG32(mmRLC_CNTL, rlc);
3412 }
3413
3414 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3415 {
3416 u32 data, orig;
3417
3418 orig = data = RREG32(mmRLC_CNTL);
3419
3420 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3421 u32 i;
3422
3423 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3424 WREG32(mmRLC_CNTL, data);
3425
3426 for (i = 0; i < adev->usec_timeout; i++) {
3427 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3428 break;
3429 udelay(1);
3430 }
3431
3432 gfx_v7_0_wait_for_rlc_serdes(adev);
3433 }
3434
3435 return orig;
3436 }
3437
3438 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3439 {
3440 u32 tmp, i, mask;
3441
3442 tmp = 0x1 | (1 << 1);
3443 WREG32(mmRLC_GPR_REG2, tmp);
3444
3445 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3446 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3447 for (i = 0; i < adev->usec_timeout; i++) {
3448 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3449 break;
3450 udelay(1);
3451 }
3452
3453 for (i = 0; i < adev->usec_timeout; i++) {
3454 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3455 break;
3456 udelay(1);
3457 }
3458 }
3459
3460 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3461 {
3462 u32 tmp;
3463
3464 tmp = 0x1 | (0 << 1);
3465 WREG32(mmRLC_GPR_REG2, tmp);
3466 }
3467
3468 /**
3469 * gfx_v7_0_rlc_stop - stop the RLC ME
3470 *
3471 * @adev: amdgpu_device pointer
3472 *
3473 * Halt the RLC ME (MicroEngine) (CIK).
3474 */
3475 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3476 {
3477 WREG32(mmRLC_CNTL, 0);
3478
3479 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3480
3481 gfx_v7_0_wait_for_rlc_serdes(adev);
3482 }
3483
3484 /**
3485 * gfx_v7_0_rlc_start - start the RLC ME
3486 *
3487 * @adev: amdgpu_device pointer
3488 *
3489 * Unhalt the RLC ME (MicroEngine) (CIK).
3490 */
3491 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3492 {
3493 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3494
3495 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3496
3497 udelay(50);
3498 }
3499
3500 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3501 {
3502 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3503
3504 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3505 WREG32(mmGRBM_SOFT_RESET, tmp);
3506 udelay(50);
3507 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3508 WREG32(mmGRBM_SOFT_RESET, tmp);
3509 udelay(50);
3510 }
3511
3512 /**
3513 * gfx_v7_0_rlc_resume - setup the RLC hw
3514 *
3515 * @adev: amdgpu_device pointer
3516 *
3517 * Initialize the RLC registers, load the ucode,
3518 * and start the RLC (CIK).
3519 * Returns 0 for success, -EINVAL if the ucode is not available.
3520 */
3521 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3522 {
3523 const struct rlc_firmware_header_v1_0 *hdr;
3524 const __le32 *fw_data;
3525 unsigned i, fw_size;
3526 u32 tmp;
3527
3528 if (!adev->gfx.rlc_fw)
3529 return -EINVAL;
3530
3531 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3532 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3533 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3534 adev->gfx.rlc_feature_version = le32_to_cpu(
3535 hdr->ucode_feature_version);
3536
3537 gfx_v7_0_rlc_stop(adev);
3538
3539 /* disable CG */
3540 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3541 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3542
3543 gfx_v7_0_rlc_reset(adev);
3544
3545 gfx_v7_0_init_pg(adev);
3546
3547 WREG32(mmRLC_LB_CNTR_INIT, 0);
3548 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3549
3550 mutex_lock(&adev->grbm_idx_mutex);
3551 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3552 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3553 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3554 WREG32(mmRLC_LB_CNTL, 0x80000004);
3555 mutex_unlock(&adev->grbm_idx_mutex);
3556
3557 WREG32(mmRLC_MC_CNTL, 0);
3558 WREG32(mmRLC_UCODE_CNTL, 0);
3559
3560 fw_data = (const __le32 *)
3561 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3562 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3563 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3564 for (i = 0; i < fw_size; i++)
3565 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3566 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3567
3568 /* XXX - find out what chips support lbpw */
3569 gfx_v7_0_enable_lbpw(adev, false);
3570
3571 if (adev->asic_type == CHIP_BONAIRE)
3572 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3573
3574 gfx_v7_0_rlc_start(adev);
3575
3576 return 0;
3577 }
3578
3579 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3580 {
3581 u32 data, orig, tmp, tmp2;
3582
3583 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3584
3585 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3586 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3587
3588 tmp = gfx_v7_0_halt_rlc(adev);
3589
3590 mutex_lock(&adev->grbm_idx_mutex);
3591 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3592 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3593 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3594 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3595 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3596 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3597 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3598 mutex_unlock(&adev->grbm_idx_mutex);
3599
3600 gfx_v7_0_update_rlc(adev, tmp);
3601
3602 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3603 } else {
3604 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3605
3606 RREG32(mmCB_CGTT_SCLK_CTRL);
3607 RREG32(mmCB_CGTT_SCLK_CTRL);
3608 RREG32(mmCB_CGTT_SCLK_CTRL);
3609 RREG32(mmCB_CGTT_SCLK_CTRL);
3610
3611 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3612 }
3613
3614 if (orig != data)
3615 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3616
3617 }
3618
3619 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3620 {
3621 u32 data, orig, tmp = 0;
3622
3623 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3624 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3625 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3626 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3627 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3628 if (orig != data)
3629 WREG32(mmCP_MEM_SLP_CNTL, data);
3630 }
3631 }
3632
3633 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3634 data |= 0x00000001;
3635 data &= 0xfffffffd;
3636 if (orig != data)
3637 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3638
3639 tmp = gfx_v7_0_halt_rlc(adev);
3640
3641 mutex_lock(&adev->grbm_idx_mutex);
3642 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3643 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3644 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3645 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3646 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3647 WREG32(mmRLC_SERDES_WR_CTRL, data);
3648 mutex_unlock(&adev->grbm_idx_mutex);
3649
3650 gfx_v7_0_update_rlc(adev, tmp);
3651
3652 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3653 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3654 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3655 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3656 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3657 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3658 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3659 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3660 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3661 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3662 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3663 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3664 if (orig != data)
3665 WREG32(mmCGTS_SM_CTRL_REG, data);
3666 }
3667 } else {
3668 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3669 data |= 0x00000003;
3670 if (orig != data)
3671 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3672
3673 data = RREG32(mmRLC_MEM_SLP_CNTL);
3674 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3675 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3676 WREG32(mmRLC_MEM_SLP_CNTL, data);
3677 }
3678
3679 data = RREG32(mmCP_MEM_SLP_CNTL);
3680 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3681 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3682 WREG32(mmCP_MEM_SLP_CNTL, data);
3683 }
3684
3685 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3686 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3687 if (orig != data)
3688 WREG32(mmCGTS_SM_CTRL_REG, data);
3689
3690 tmp = gfx_v7_0_halt_rlc(adev);
3691
3692 mutex_lock(&adev->grbm_idx_mutex);
3693 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3694 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3695 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3696 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3697 WREG32(mmRLC_SERDES_WR_CTRL, data);
3698 mutex_unlock(&adev->grbm_idx_mutex);
3699
3700 gfx_v7_0_update_rlc(adev, tmp);
3701 }
3702 }
3703
3704 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3705 bool enable)
3706 {
3707 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3708 /* order matters! */
3709 if (enable) {
3710 gfx_v7_0_enable_mgcg(adev, true);
3711 gfx_v7_0_enable_cgcg(adev, true);
3712 } else {
3713 gfx_v7_0_enable_cgcg(adev, false);
3714 gfx_v7_0_enable_mgcg(adev, false);
3715 }
3716 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3717 }
3718
3719 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3720 bool enable)
3721 {
3722 u32 data, orig;
3723
3724 orig = data = RREG32(mmRLC_PG_CNTL);
3725 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3726 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3727 else
3728 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3729 if (orig != data)
3730 WREG32(mmRLC_PG_CNTL, data);
3731 }
3732
3733 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3734 bool enable)
3735 {
3736 u32 data, orig;
3737
3738 orig = data = RREG32(mmRLC_PG_CNTL);
3739 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3740 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3741 else
3742 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3743 if (orig != data)
3744 WREG32(mmRLC_PG_CNTL, data);
3745 }
3746
3747 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3748 {
3749 u32 data, orig;
3750
3751 orig = data = RREG32(mmRLC_PG_CNTL);
3752 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3753 data &= ~0x8000;
3754 else
3755 data |= 0x8000;
3756 if (orig != data)
3757 WREG32(mmRLC_PG_CNTL, data);
3758 }
3759
3760 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3761 {
3762 u32 data, orig;
3763
3764 orig = data = RREG32(mmRLC_PG_CNTL);
3765 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3766 data &= ~0x2000;
3767 else
3768 data |= 0x2000;
3769 if (orig != data)
3770 WREG32(mmRLC_PG_CNTL, data);
3771 }
3772
3773 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3774 {
3775 const __le32 *fw_data;
3776 volatile u32 *dst_ptr;
3777 int me, i, max_me = 4;
3778 u32 bo_offset = 0;
3779 u32 table_offset, table_size;
3780
3781 if (adev->asic_type == CHIP_KAVERI)
3782 max_me = 5;
3783
3784 if (adev->gfx.rlc.cp_table_ptr == NULL)
3785 return;
3786
3787 /* write the cp table buffer */
3788 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3789 for (me = 0; me < max_me; me++) {
3790 if (me == 0) {
3791 const struct gfx_firmware_header_v1_0 *hdr =
3792 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3793 fw_data = (const __le32 *)
3794 (adev->gfx.ce_fw->data +
3795 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3796 table_offset = le32_to_cpu(hdr->jt_offset);
3797 table_size = le32_to_cpu(hdr->jt_size);
3798 } else if (me == 1) {
3799 const struct gfx_firmware_header_v1_0 *hdr =
3800 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3801 fw_data = (const __le32 *)
3802 (adev->gfx.pfp_fw->data +
3803 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3804 table_offset = le32_to_cpu(hdr->jt_offset);
3805 table_size = le32_to_cpu(hdr->jt_size);
3806 } else if (me == 2) {
3807 const struct gfx_firmware_header_v1_0 *hdr =
3808 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3809 fw_data = (const __le32 *)
3810 (adev->gfx.me_fw->data +
3811 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3812 table_offset = le32_to_cpu(hdr->jt_offset);
3813 table_size = le32_to_cpu(hdr->jt_size);
3814 } else if (me == 3) {
3815 const struct gfx_firmware_header_v1_0 *hdr =
3816 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3817 fw_data = (const __le32 *)
3818 (adev->gfx.mec_fw->data +
3819 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3820 table_offset = le32_to_cpu(hdr->jt_offset);
3821 table_size = le32_to_cpu(hdr->jt_size);
3822 } else {
3823 const struct gfx_firmware_header_v1_0 *hdr =
3824 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3825 fw_data = (const __le32 *)
3826 (adev->gfx.mec2_fw->data +
3827 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3828 table_offset = le32_to_cpu(hdr->jt_offset);
3829 table_size = le32_to_cpu(hdr->jt_size);
3830 }
3831
3832 for (i = 0; i < table_size; i ++) {
3833 dst_ptr[bo_offset + i] =
3834 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3835 }
3836
3837 bo_offset += table_size;
3838 }
3839 }
3840
3841 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3842 bool enable)
3843 {
3844 u32 data, orig;
3845
3846 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3847 orig = data = RREG32(mmRLC_PG_CNTL);
3848 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3849 if (orig != data)
3850 WREG32(mmRLC_PG_CNTL, data);
3851
3852 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3853 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3854 if (orig != data)
3855 WREG32(mmRLC_AUTO_PG_CTRL, data);
3856 } else {
3857 orig = data = RREG32(mmRLC_PG_CNTL);
3858 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3859 if (orig != data)
3860 WREG32(mmRLC_PG_CNTL, data);
3861
3862 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3863 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3864 if (orig != data)
3865 WREG32(mmRLC_AUTO_PG_CTRL, data);
3866
3867 data = RREG32(mmDB_RENDER_CONTROL);
3868 }
3869 }
3870
3871 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3872 {
3873 u32 data, mask;
3874
3875 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3876 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3877
3878 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3879 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3880
3881 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3882
3883 return (~data) & mask;
3884 }
3885
3886 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3887 {
3888 u32 tmp;
3889
3890 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3891
3892 tmp = RREG32(mmRLC_MAX_PG_CU);
3893 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3894 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3895 WREG32(mmRLC_MAX_PG_CU, tmp);
3896 }
3897
3898 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3899 bool enable)
3900 {
3901 u32 data, orig;
3902
3903 orig = data = RREG32(mmRLC_PG_CNTL);
3904 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3905 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3906 else
3907 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3908 if (orig != data)
3909 WREG32(mmRLC_PG_CNTL, data);
3910 }
3911
3912 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3913 bool enable)
3914 {
3915 u32 data, orig;
3916
3917 orig = data = RREG32(mmRLC_PG_CNTL);
3918 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3919 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3920 else
3921 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3922 if (orig != data)
3923 WREG32(mmRLC_PG_CNTL, data);
3924 }
3925
3926 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3927 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3928
3929 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3930 {
3931 u32 data, orig;
3932 u32 i;
3933
3934 if (adev->gfx.rlc.cs_data) {
3935 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3936 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3937 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3938 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3939 } else {
3940 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3941 for (i = 0; i < 3; i++)
3942 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3943 }
3944 if (adev->gfx.rlc.reg_list) {
3945 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3946 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3947 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3948 }
3949
3950 orig = data = RREG32(mmRLC_PG_CNTL);
3951 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3952 if (orig != data)
3953 WREG32(mmRLC_PG_CNTL, data);
3954
3955 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3956 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3957
3958 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3959 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3960 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3961 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3962
3963 data = 0x10101010;
3964 WREG32(mmRLC_PG_DELAY, data);
3965
3966 data = RREG32(mmRLC_PG_DELAY_2);
3967 data &= ~0xff;
3968 data |= 0x3;
3969 WREG32(mmRLC_PG_DELAY_2, data);
3970
3971 data = RREG32(mmRLC_AUTO_PG_CTRL);
3972 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3973 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3974 WREG32(mmRLC_AUTO_PG_CTRL, data);
3975
3976 }
3977
3978 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3979 {
3980 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3981 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3982 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3983 }
3984
3985 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3986 {
3987 u32 count = 0;
3988 const struct cs_section_def *sect = NULL;
3989 const struct cs_extent_def *ext = NULL;
3990
3991 if (adev->gfx.rlc.cs_data == NULL)
3992 return 0;
3993
3994 /* begin clear state */
3995 count += 2;
3996 /* context control state */
3997 count += 3;
3998
3999 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4000 for (ext = sect->section; ext->extent != NULL; ++ext) {
4001 if (sect->id == SECT_CONTEXT)
4002 count += 2 + ext->reg_count;
4003 else
4004 return 0;
4005 }
4006 }
4007 /* pa_sc_raster_config/pa_sc_raster_config1 */
4008 count += 4;
4009 /* end clear state */
4010 count += 2;
4011 /* clear state */
4012 count += 2;
4013
4014 return count;
4015 }
4016
4017 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4018 volatile u32 *buffer)
4019 {
4020 u32 count = 0, i;
4021 const struct cs_section_def *sect = NULL;
4022 const struct cs_extent_def *ext = NULL;
4023
4024 if (adev->gfx.rlc.cs_data == NULL)
4025 return;
4026 if (buffer == NULL)
4027 return;
4028
4029 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4030 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4031
4032 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4033 buffer[count++] = cpu_to_le32(0x80000000);
4034 buffer[count++] = cpu_to_le32(0x80000000);
4035
4036 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4037 for (ext = sect->section; ext->extent != NULL; ++ext) {
4038 if (sect->id == SECT_CONTEXT) {
4039 buffer[count++] =
4040 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4041 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4042 for (i = 0; i < ext->reg_count; i++)
4043 buffer[count++] = cpu_to_le32(ext->extent[i]);
4044 } else {
4045 return;
4046 }
4047 }
4048 }
4049
4050 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4051 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4052 switch (adev->asic_type) {
4053 case CHIP_BONAIRE:
4054 buffer[count++] = cpu_to_le32(0x16000012);
4055 buffer[count++] = cpu_to_le32(0x00000000);
4056 break;
4057 case CHIP_KAVERI:
4058 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4059 buffer[count++] = cpu_to_le32(0x00000000);
4060 break;
4061 case CHIP_KABINI:
4062 case CHIP_MULLINS:
4063 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4064 buffer[count++] = cpu_to_le32(0x00000000);
4065 break;
4066 case CHIP_HAWAII:
4067 buffer[count++] = cpu_to_le32(0x3a00161a);
4068 buffer[count++] = cpu_to_le32(0x0000002e);
4069 break;
4070 default:
4071 buffer[count++] = cpu_to_le32(0x00000000);
4072 buffer[count++] = cpu_to_le32(0x00000000);
4073 break;
4074 }
4075
4076 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4077 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4078
4079 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4080 buffer[count++] = cpu_to_le32(0);
4081 }
4082
4083 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4084 {
4085 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4086 AMD_PG_SUPPORT_GFX_SMG |
4087 AMD_PG_SUPPORT_GFX_DMG |
4088 AMD_PG_SUPPORT_CP |
4089 AMD_PG_SUPPORT_GDS |
4090 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4091 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4092 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4093 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4094 gfx_v7_0_init_gfx_cgpg(adev);
4095 gfx_v7_0_enable_cp_pg(adev, true);
4096 gfx_v7_0_enable_gds_pg(adev, true);
4097 }
4098 gfx_v7_0_init_ao_cu_mask(adev);
4099 gfx_v7_0_update_gfx_pg(adev, true);
4100 }
4101 }
4102
4103 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4104 {
4105 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4106 AMD_PG_SUPPORT_GFX_SMG |
4107 AMD_PG_SUPPORT_GFX_DMG |
4108 AMD_PG_SUPPORT_CP |
4109 AMD_PG_SUPPORT_GDS |
4110 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4111 gfx_v7_0_update_gfx_pg(adev, false);
4112 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4113 gfx_v7_0_enable_cp_pg(adev, false);
4114 gfx_v7_0_enable_gds_pg(adev, false);
4115 }
4116 }
4117 }
4118
4119 /**
4120 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4121 *
4122 * @adev: amdgpu_device pointer
4123 *
4124 * Fetches a GPU clock counter snapshot (SI).
4125 * Returns the 64 bit clock counter snapshot.
4126 */
4127 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4128 {
4129 uint64_t clock;
4130
4131 mutex_lock(&adev->gfx.gpu_clock_mutex);
4132 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4133 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4134 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4135 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4136 return clock;
4137 }
4138
4139 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4140 uint32_t vmid,
4141 uint32_t gds_base, uint32_t gds_size,
4142 uint32_t gws_base, uint32_t gws_size,
4143 uint32_t oa_base, uint32_t oa_size)
4144 {
4145 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4146 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4147
4148 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4149 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4150
4151 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4152 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4153
4154 /* GDS Base */
4155 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4156 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4157 WRITE_DATA_DST_SEL(0)));
4158 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4159 amdgpu_ring_write(ring, 0);
4160 amdgpu_ring_write(ring, gds_base);
4161
4162 /* GDS Size */
4163 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4164 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4165 WRITE_DATA_DST_SEL(0)));
4166 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4167 amdgpu_ring_write(ring, 0);
4168 amdgpu_ring_write(ring, gds_size);
4169
4170 /* GWS */
4171 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4172 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4173 WRITE_DATA_DST_SEL(0)));
4174 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4175 amdgpu_ring_write(ring, 0);
4176 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4177
4178 /* OA */
4179 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4180 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4181 WRITE_DATA_DST_SEL(0)));
4182 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4183 amdgpu_ring_write(ring, 0);
4184 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4185 }
4186
4187 static int gfx_v7_0_early_init(void *handle)
4188 {
4189 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4190
4191 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4192 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4193 gfx_v7_0_set_ring_funcs(adev);
4194 gfx_v7_0_set_irq_funcs(adev);
4195 gfx_v7_0_set_gds_init(adev);
4196
4197 return 0;
4198 }
4199
4200 static int gfx_v7_0_late_init(void *handle)
4201 {
4202 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4203 int r;
4204
4205 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4206 if (r)
4207 return r;
4208
4209 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4210 if (r)
4211 return r;
4212
4213 return 0;
4214 }
4215
4216 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4217 {
4218 u32 gb_addr_config;
4219 u32 mc_shared_chmap, mc_arb_ramcfg;
4220 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4221 u32 tmp;
4222
4223 switch (adev->asic_type) {
4224 case CHIP_BONAIRE:
4225 adev->gfx.config.max_shader_engines = 2;
4226 adev->gfx.config.max_tile_pipes = 4;
4227 adev->gfx.config.max_cu_per_sh = 7;
4228 adev->gfx.config.max_sh_per_se = 1;
4229 adev->gfx.config.max_backends_per_se = 2;
4230 adev->gfx.config.max_texture_channel_caches = 4;
4231 adev->gfx.config.max_gprs = 256;
4232 adev->gfx.config.max_gs_threads = 32;
4233 adev->gfx.config.max_hw_contexts = 8;
4234
4235 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4236 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4237 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4238 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4239 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4240 break;
4241 case CHIP_HAWAII:
4242 adev->gfx.config.max_shader_engines = 4;
4243 adev->gfx.config.max_tile_pipes = 16;
4244 adev->gfx.config.max_cu_per_sh = 11;
4245 adev->gfx.config.max_sh_per_se = 1;
4246 adev->gfx.config.max_backends_per_se = 4;
4247 adev->gfx.config.max_texture_channel_caches = 16;
4248 adev->gfx.config.max_gprs = 256;
4249 adev->gfx.config.max_gs_threads = 32;
4250 adev->gfx.config.max_hw_contexts = 8;
4251
4252 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4253 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4254 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4255 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4256 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4257 break;
4258 case CHIP_KAVERI:
4259 adev->gfx.config.max_shader_engines = 1;
4260 adev->gfx.config.max_tile_pipes = 4;
4261 if ((adev->pdev->device == 0x1304) ||
4262 (adev->pdev->device == 0x1305) ||
4263 (adev->pdev->device == 0x130C) ||
4264 (adev->pdev->device == 0x130F) ||
4265 (adev->pdev->device == 0x1310) ||
4266 (adev->pdev->device == 0x1311) ||
4267 (adev->pdev->device == 0x131C)) {
4268 adev->gfx.config.max_cu_per_sh = 8;
4269 adev->gfx.config.max_backends_per_se = 2;
4270 } else if ((adev->pdev->device == 0x1309) ||
4271 (adev->pdev->device == 0x130A) ||
4272 (adev->pdev->device == 0x130D) ||
4273 (adev->pdev->device == 0x1313) ||
4274 (adev->pdev->device == 0x131D)) {
4275 adev->gfx.config.max_cu_per_sh = 6;
4276 adev->gfx.config.max_backends_per_se = 2;
4277 } else if ((adev->pdev->device == 0x1306) ||
4278 (adev->pdev->device == 0x1307) ||
4279 (adev->pdev->device == 0x130B) ||
4280 (adev->pdev->device == 0x130E) ||
4281 (adev->pdev->device == 0x1315) ||
4282 (adev->pdev->device == 0x131B)) {
4283 adev->gfx.config.max_cu_per_sh = 4;
4284 adev->gfx.config.max_backends_per_se = 1;
4285 } else {
4286 adev->gfx.config.max_cu_per_sh = 3;
4287 adev->gfx.config.max_backends_per_se = 1;
4288 }
4289 adev->gfx.config.max_sh_per_se = 1;
4290 adev->gfx.config.max_texture_channel_caches = 4;
4291 adev->gfx.config.max_gprs = 256;
4292 adev->gfx.config.max_gs_threads = 16;
4293 adev->gfx.config.max_hw_contexts = 8;
4294
4295 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4296 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4297 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4298 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4299 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4300 break;
4301 case CHIP_KABINI:
4302 case CHIP_MULLINS:
4303 default:
4304 adev->gfx.config.max_shader_engines = 1;
4305 adev->gfx.config.max_tile_pipes = 2;
4306 adev->gfx.config.max_cu_per_sh = 2;
4307 adev->gfx.config.max_sh_per_se = 1;
4308 adev->gfx.config.max_backends_per_se = 1;
4309 adev->gfx.config.max_texture_channel_caches = 2;
4310 adev->gfx.config.max_gprs = 256;
4311 adev->gfx.config.max_gs_threads = 16;
4312 adev->gfx.config.max_hw_contexts = 8;
4313
4314 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4315 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4316 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4317 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4318 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4319 break;
4320 }
4321
4322 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4323 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4324 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4325
4326 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4327 adev->gfx.config.mem_max_burst_length_bytes = 256;
4328 if (adev->flags & AMD_IS_APU) {
4329 /* Get memory bank mapping mode. */
4330 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4331 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4332 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4333
4334 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4335 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4336 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4337
4338 /* Validate settings in case only one DIMM installed. */
4339 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4340 dimm00_addr_map = 0;
4341 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4342 dimm01_addr_map = 0;
4343 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4344 dimm10_addr_map = 0;
4345 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4346 dimm11_addr_map = 0;
4347
4348 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4349 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4350 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4351 adev->gfx.config.mem_row_size_in_kb = 2;
4352 else
4353 adev->gfx.config.mem_row_size_in_kb = 1;
4354 } else {
4355 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4356 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4357 if (adev->gfx.config.mem_row_size_in_kb > 4)
4358 adev->gfx.config.mem_row_size_in_kb = 4;
4359 }
4360 /* XXX use MC settings? */
4361 adev->gfx.config.shader_engine_tile_size = 32;
4362 adev->gfx.config.num_gpus = 1;
4363 adev->gfx.config.multi_gpu_tile_size = 64;
4364
4365 /* fix up row size */
4366 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4367 switch (adev->gfx.config.mem_row_size_in_kb) {
4368 case 1:
4369 default:
4370 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4371 break;
4372 case 2:
4373 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4374 break;
4375 case 4:
4376 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4377 break;
4378 }
4379 adev->gfx.config.gb_addr_config = gb_addr_config;
4380 }
4381
4382 static int gfx_v7_0_sw_init(void *handle)
4383 {
4384 struct amdgpu_ring *ring;
4385 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4386 int i, r;
4387
4388 /* EOP Event */
4389 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4390 if (r)
4391 return r;
4392
4393 /* Privileged reg */
4394 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4395 if (r)
4396 return r;
4397
4398 /* Privileged inst */
4399 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4400 if (r)
4401 return r;
4402
4403 gfx_v7_0_scratch_init(adev);
4404
4405 r = gfx_v7_0_init_microcode(adev);
4406 if (r) {
4407 DRM_ERROR("Failed to load gfx firmware!\n");
4408 return r;
4409 }
4410
4411 r = gfx_v7_0_rlc_init(adev);
4412 if (r) {
4413 DRM_ERROR("Failed to init rlc BOs!\n");
4414 return r;
4415 }
4416
4417 /* allocate mec buffers */
4418 r = gfx_v7_0_mec_init(adev);
4419 if (r) {
4420 DRM_ERROR("Failed to init MEC BOs!\n");
4421 return r;
4422 }
4423
4424 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4425 ring = &adev->gfx.gfx_ring[i];
4426 ring->ring_obj = NULL;
4427 sprintf(ring->name, "gfx");
4428 r = amdgpu_ring_init(adev, ring, 1024,
4429 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4430 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4431 AMDGPU_RING_TYPE_GFX);
4432 if (r)
4433 return r;
4434 }
4435
4436 /* set up the compute queues */
4437 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4438 unsigned irq_type;
4439
4440 /* max 32 queues per MEC */
4441 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4442 DRM_ERROR("Too many (%d) compute rings!\n", i);
4443 break;
4444 }
4445 ring = &adev->gfx.compute_ring[i];
4446 ring->ring_obj = NULL;
4447 ring->use_doorbell = true;
4448 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4449 ring->me = 1; /* first MEC */
4450 ring->pipe = i / 8;
4451 ring->queue = i % 8;
4452 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4453 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4454 /* type-2 packets are deprecated on MEC, use type-3 instead */
4455 r = amdgpu_ring_init(adev, ring, 1024,
4456 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4457 &adev->gfx.eop_irq, irq_type,
4458 AMDGPU_RING_TYPE_COMPUTE);
4459 if (r)
4460 return r;
4461 }
4462
4463 /* reserve GDS, GWS and OA resource for gfx */
4464 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4465 PAGE_SIZE, true,
4466 AMDGPU_GEM_DOMAIN_GDS, 0,
4467 NULL, NULL, &adev->gds.gds_gfx_bo);
4468 if (r)
4469 return r;
4470
4471 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4472 PAGE_SIZE, true,
4473 AMDGPU_GEM_DOMAIN_GWS, 0,
4474 NULL, NULL, &adev->gds.gws_gfx_bo);
4475 if (r)
4476 return r;
4477
4478 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4479 PAGE_SIZE, true,
4480 AMDGPU_GEM_DOMAIN_OA, 0,
4481 NULL, NULL, &adev->gds.oa_gfx_bo);
4482 if (r)
4483 return r;
4484
4485 adev->gfx.ce_ram_size = 0x8000;
4486
4487 gfx_v7_0_gpu_early_init(adev);
4488
4489 return r;
4490 }
4491
4492 static int gfx_v7_0_sw_fini(void *handle)
4493 {
4494 int i;
4495 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4496
4497 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4498 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4499 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4500
4501 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4502 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4503 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4504 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4505
4506 gfx_v7_0_cp_compute_fini(adev);
4507 gfx_v7_0_rlc_fini(adev);
4508 gfx_v7_0_mec_fini(adev);
4509 gfx_v7_0_free_microcode(adev);
4510
4511 return 0;
4512 }
4513
4514 static int gfx_v7_0_hw_init(void *handle)
4515 {
4516 int r;
4517 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4518
4519 gfx_v7_0_gpu_init(adev);
4520
4521 /* init rlc */
4522 r = gfx_v7_0_rlc_resume(adev);
4523 if (r)
4524 return r;
4525
4526 r = gfx_v7_0_cp_resume(adev);
4527 if (r)
4528 return r;
4529
4530 return r;
4531 }
4532
4533 static int gfx_v7_0_hw_fini(void *handle)
4534 {
4535 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4536
4537 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4538 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4539 gfx_v7_0_cp_enable(adev, false);
4540 gfx_v7_0_rlc_stop(adev);
4541 gfx_v7_0_fini_pg(adev);
4542
4543 return 0;
4544 }
4545
4546 static int gfx_v7_0_suspend(void *handle)
4547 {
4548 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4549
4550 return gfx_v7_0_hw_fini(adev);
4551 }
4552
4553 static int gfx_v7_0_resume(void *handle)
4554 {
4555 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4556
4557 return gfx_v7_0_hw_init(adev);
4558 }
4559
4560 static bool gfx_v7_0_is_idle(void *handle)
4561 {
4562 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4563
4564 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4565 return false;
4566 else
4567 return true;
4568 }
4569
4570 static int gfx_v7_0_wait_for_idle(void *handle)
4571 {
4572 unsigned i;
4573 u32 tmp;
4574 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4575
4576 for (i = 0; i < adev->usec_timeout; i++) {
4577 /* read MC_STATUS */
4578 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4579
4580 if (!tmp)
4581 return 0;
4582 udelay(1);
4583 }
4584 return -ETIMEDOUT;
4585 }
4586
4587 static int gfx_v7_0_soft_reset(void *handle)
4588 {
4589 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4590 u32 tmp;
4591 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4592
4593 /* GRBM_STATUS */
4594 tmp = RREG32(mmGRBM_STATUS);
4595 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4596 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4597 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4598 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4599 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4600 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4601 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4602 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4603
4604 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4605 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4606 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4607 }
4608
4609 /* GRBM_STATUS2 */
4610 tmp = RREG32(mmGRBM_STATUS2);
4611 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4612 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4613
4614 /* SRBM_STATUS */
4615 tmp = RREG32(mmSRBM_STATUS);
4616 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4617 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4618
4619 if (grbm_soft_reset || srbm_soft_reset) {
4620 /* disable CG/PG */
4621 gfx_v7_0_fini_pg(adev);
4622 gfx_v7_0_update_cg(adev, false);
4623
4624 /* stop the rlc */
4625 gfx_v7_0_rlc_stop(adev);
4626
4627 /* Disable GFX parsing/prefetching */
4628 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4629
4630 /* Disable MEC parsing/prefetching */
4631 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4632
4633 if (grbm_soft_reset) {
4634 tmp = RREG32(mmGRBM_SOFT_RESET);
4635 tmp |= grbm_soft_reset;
4636 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4637 WREG32(mmGRBM_SOFT_RESET, tmp);
4638 tmp = RREG32(mmGRBM_SOFT_RESET);
4639
4640 udelay(50);
4641
4642 tmp &= ~grbm_soft_reset;
4643 WREG32(mmGRBM_SOFT_RESET, tmp);
4644 tmp = RREG32(mmGRBM_SOFT_RESET);
4645 }
4646
4647 if (srbm_soft_reset) {
4648 tmp = RREG32(mmSRBM_SOFT_RESET);
4649 tmp |= srbm_soft_reset;
4650 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4651 WREG32(mmSRBM_SOFT_RESET, tmp);
4652 tmp = RREG32(mmSRBM_SOFT_RESET);
4653
4654 udelay(50);
4655
4656 tmp &= ~srbm_soft_reset;
4657 WREG32(mmSRBM_SOFT_RESET, tmp);
4658 tmp = RREG32(mmSRBM_SOFT_RESET);
4659 }
4660 /* Wait a little for things to settle down */
4661 udelay(50);
4662 }
4663 return 0;
4664 }
4665
4666 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4667 enum amdgpu_interrupt_state state)
4668 {
4669 u32 cp_int_cntl;
4670
4671 switch (state) {
4672 case AMDGPU_IRQ_STATE_DISABLE:
4673 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4674 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4675 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4676 break;
4677 case AMDGPU_IRQ_STATE_ENABLE:
4678 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4679 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4680 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4681 break;
4682 default:
4683 break;
4684 }
4685 }
4686
4687 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4688 int me, int pipe,
4689 enum amdgpu_interrupt_state state)
4690 {
4691 u32 mec_int_cntl, mec_int_cntl_reg;
4692
4693 /*
4694 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4695 * handles the setting of interrupts for this specific pipe. All other
4696 * pipes' interrupts are set by amdkfd.
4697 */
4698
4699 if (me == 1) {
4700 switch (pipe) {
4701 case 0:
4702 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4703 break;
4704 default:
4705 DRM_DEBUG("invalid pipe %d\n", pipe);
4706 return;
4707 }
4708 } else {
4709 DRM_DEBUG("invalid me %d\n", me);
4710 return;
4711 }
4712
4713 switch (state) {
4714 case AMDGPU_IRQ_STATE_DISABLE:
4715 mec_int_cntl = RREG32(mec_int_cntl_reg);
4716 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4717 WREG32(mec_int_cntl_reg, mec_int_cntl);
4718 break;
4719 case AMDGPU_IRQ_STATE_ENABLE:
4720 mec_int_cntl = RREG32(mec_int_cntl_reg);
4721 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4722 WREG32(mec_int_cntl_reg, mec_int_cntl);
4723 break;
4724 default:
4725 break;
4726 }
4727 }
4728
4729 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4730 struct amdgpu_irq_src *src,
4731 unsigned type,
4732 enum amdgpu_interrupt_state state)
4733 {
4734 u32 cp_int_cntl;
4735
4736 switch (state) {
4737 case AMDGPU_IRQ_STATE_DISABLE:
4738 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4739 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4740 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4741 break;
4742 case AMDGPU_IRQ_STATE_ENABLE:
4743 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4744 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4745 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4746 break;
4747 default:
4748 break;
4749 }
4750
4751 return 0;
4752 }
4753
4754 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4755 struct amdgpu_irq_src *src,
4756 unsigned type,
4757 enum amdgpu_interrupt_state state)
4758 {
4759 u32 cp_int_cntl;
4760
4761 switch (state) {
4762 case AMDGPU_IRQ_STATE_DISABLE:
4763 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4764 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4765 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4766 break;
4767 case AMDGPU_IRQ_STATE_ENABLE:
4768 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4769 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4770 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4771 break;
4772 default:
4773 break;
4774 }
4775
4776 return 0;
4777 }
4778
4779 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4780 struct amdgpu_irq_src *src,
4781 unsigned type,
4782 enum amdgpu_interrupt_state state)
4783 {
4784 switch (type) {
4785 case AMDGPU_CP_IRQ_GFX_EOP:
4786 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4787 break;
4788 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4789 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4790 break;
4791 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4792 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4793 break;
4794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4795 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4796 break;
4797 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4798 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4799 break;
4800 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4801 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4802 break;
4803 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4804 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4805 break;
4806 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4807 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4808 break;
4809 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4810 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4811 break;
4812 default:
4813 break;
4814 }
4815 return 0;
4816 }
4817
4818 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4819 struct amdgpu_irq_src *source,
4820 struct amdgpu_iv_entry *entry)
4821 {
4822 u8 me_id, pipe_id;
4823 struct amdgpu_ring *ring;
4824 int i;
4825
4826 DRM_DEBUG("IH: CP EOP\n");
4827 me_id = (entry->ring_id & 0x0c) >> 2;
4828 pipe_id = (entry->ring_id & 0x03) >> 0;
4829 switch (me_id) {
4830 case 0:
4831 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4832 break;
4833 case 1:
4834 case 2:
4835 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4836 ring = &adev->gfx.compute_ring[i];
4837 if ((ring->me == me_id) && (ring->pipe == pipe_id))
4838 amdgpu_fence_process(ring);
4839 }
4840 break;
4841 }
4842 return 0;
4843 }
4844
4845 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4846 struct amdgpu_irq_src *source,
4847 struct amdgpu_iv_entry *entry)
4848 {
4849 DRM_ERROR("Illegal register access in command stream\n");
4850 schedule_work(&adev->reset_work);
4851 return 0;
4852 }
4853
4854 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4855 struct amdgpu_irq_src *source,
4856 struct amdgpu_iv_entry *entry)
4857 {
4858 DRM_ERROR("Illegal instruction in command stream\n");
4859 // XXX soft reset the gfx block only
4860 schedule_work(&adev->reset_work);
4861 return 0;
4862 }
4863
4864 static int gfx_v7_0_set_clockgating_state(void *handle,
4865 enum amd_clockgating_state state)
4866 {
4867 bool gate = false;
4868 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4869
4870 if (state == AMD_CG_STATE_GATE)
4871 gate = true;
4872
4873 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4874 /* order matters! */
4875 if (gate) {
4876 gfx_v7_0_enable_mgcg(adev, true);
4877 gfx_v7_0_enable_cgcg(adev, true);
4878 } else {
4879 gfx_v7_0_enable_cgcg(adev, false);
4880 gfx_v7_0_enable_mgcg(adev, false);
4881 }
4882 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4883
4884 return 0;
4885 }
4886
4887 static int gfx_v7_0_set_powergating_state(void *handle,
4888 enum amd_powergating_state state)
4889 {
4890 bool gate = false;
4891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4892
4893 if (state == AMD_PG_STATE_GATE)
4894 gate = true;
4895
4896 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4897 AMD_PG_SUPPORT_GFX_SMG |
4898 AMD_PG_SUPPORT_GFX_DMG |
4899 AMD_PG_SUPPORT_CP |
4900 AMD_PG_SUPPORT_GDS |
4901 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4902 gfx_v7_0_update_gfx_pg(adev, gate);
4903 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4904 gfx_v7_0_enable_cp_pg(adev, gate);
4905 gfx_v7_0_enable_gds_pg(adev, gate);
4906 }
4907 }
4908
4909 return 0;
4910 }
4911
4912 const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
4913 .name = "gfx_v7_0",
4914 .early_init = gfx_v7_0_early_init,
4915 .late_init = gfx_v7_0_late_init,
4916 .sw_init = gfx_v7_0_sw_init,
4917 .sw_fini = gfx_v7_0_sw_fini,
4918 .hw_init = gfx_v7_0_hw_init,
4919 .hw_fini = gfx_v7_0_hw_fini,
4920 .suspend = gfx_v7_0_suspend,
4921 .resume = gfx_v7_0_resume,
4922 .is_idle = gfx_v7_0_is_idle,
4923 .wait_for_idle = gfx_v7_0_wait_for_idle,
4924 .soft_reset = gfx_v7_0_soft_reset,
4925 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4926 .set_powergating_state = gfx_v7_0_set_powergating_state,
4927 };
4928
4929 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4930 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
4931 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4932 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4933 .parse_cs = NULL,
4934 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
4935 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
4936 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4937 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4938 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4939 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4940 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4941 .test_ring = gfx_v7_0_ring_test_ring,
4942 .test_ib = gfx_v7_0_ring_test_ib,
4943 .insert_nop = amdgpu_ring_insert_nop,
4944 .pad_ib = amdgpu_ring_generic_pad_ib,
4945 };
4946
4947 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4948 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
4949 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
4950 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
4951 .parse_cs = NULL,
4952 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
4953 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
4954 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4955 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4956 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4957 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4958 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4959 .test_ring = gfx_v7_0_ring_test_ring,
4960 .test_ib = gfx_v7_0_ring_test_ib,
4961 .insert_nop = amdgpu_ring_insert_nop,
4962 .pad_ib = amdgpu_ring_generic_pad_ib,
4963 };
4964
4965 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4966 {
4967 int i;
4968
4969 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4970 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
4971 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4972 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
4973 }
4974
4975 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
4976 .set = gfx_v7_0_set_eop_interrupt_state,
4977 .process = gfx_v7_0_eop_irq,
4978 };
4979
4980 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
4981 .set = gfx_v7_0_set_priv_reg_fault_state,
4982 .process = gfx_v7_0_priv_reg_irq,
4983 };
4984
4985 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
4986 .set = gfx_v7_0_set_priv_inst_fault_state,
4987 .process = gfx_v7_0_priv_inst_irq,
4988 };
4989
4990 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
4991 {
4992 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4993 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
4994
4995 adev->gfx.priv_reg_irq.num_types = 1;
4996 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
4997
4998 adev->gfx.priv_inst_irq.num_types = 1;
4999 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5000 }
5001
5002 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5003 {
5004 /* init asci gds info */
5005 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5006 adev->gds.gws.total_size = 64;
5007 adev->gds.oa.total_size = 16;
5008
5009 if (adev->gds.mem.total_size == 64 * 1024) {
5010 adev->gds.mem.gfx_partition_size = 4096;
5011 adev->gds.mem.cs_partition_size = 4096;
5012
5013 adev->gds.gws.gfx_partition_size = 4;
5014 adev->gds.gws.cs_partition_size = 4;
5015
5016 adev->gds.oa.gfx_partition_size = 4;
5017 adev->gds.oa.cs_partition_size = 1;
5018 } else {
5019 adev->gds.mem.gfx_partition_size = 1024;
5020 adev->gds.mem.cs_partition_size = 1024;
5021
5022 adev->gds.gws.gfx_partition_size = 16;
5023 adev->gds.gws.cs_partition_size = 16;
5024
5025 adev->gds.oa.gfx_partition_size = 4;
5026 adev->gds.oa.cs_partition_size = 4;
5027 }
5028 }
5029
5030
5031 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5032 {
5033 int i, j, k, counter, active_cu_number = 0;
5034 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5035 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5036
5037 memset(cu_info, 0, sizeof(*cu_info));
5038
5039 mutex_lock(&adev->grbm_idx_mutex);
5040 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5041 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5042 mask = 1;
5043 ao_bitmap = 0;
5044 counter = 0;
5045 gfx_v7_0_select_se_sh(adev, i, j);
5046 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5047 cu_info->bitmap[i][j] = bitmap;
5048
5049 for (k = 0; k < 16; k ++) {
5050 if (bitmap & mask) {
5051 if (counter < 2)
5052 ao_bitmap |= mask;
5053 counter ++;
5054 }
5055 mask <<= 1;
5056 }
5057 active_cu_number += counter;
5058 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5059 }
5060 }
5061 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5062 mutex_unlock(&adev->grbm_idx_mutex);
5063
5064 cu_info->number = active_cu_number;
5065 cu_info->ao_cu_mask = ao_cu_mask;
5066 }
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