2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
27 #include "link_encoder.h"
28 #include "stream_encoder.h"
31 #include "include/irq_service_interface.h"
32 #include "../virtual/virtual_stream_encoder.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "irq/dce110/irq_service_dce110.h"
36 #include "dce/dce_link_encoder.h"
37 #include "dce/dce_stream_encoder.h"
38 #include "dce110/dce110_mem_input.h"
39 #include "dce110/dce110_mem_input_v.h"
40 #include "dce110/dce110_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce110/dce110_opp.h"
43 #include "dce/dce_clock_source.h"
44 #include "dce/dce_audio.h"
45 #include "dce/dce_hwseq.h"
46 #include "dce100/dce100_hw_sequencer.h"
48 #include "reg_helper.h"
50 #include "dce/dce_10_0_d.h"
51 #include "dce/dce_10_0_sh_mask.h"
53 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
54 #include "gmc/gmc_8_2_d.h"
55 #include "gmc/gmc_8_2_sh_mask.h"
58 #ifndef mmDP_DPHY_INTERNAL_CTRL
59 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
60 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
61 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
62 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
63 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
64 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
65 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
66 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
67 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
68 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
71 #ifndef mmBIOS_SCRATCH_2
72 #define mmBIOS_SCRATCH_2 0x05CB
73 #define mmBIOS_SCRATCH_6 0x05CF
76 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
77 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
78 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
79 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
80 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
81 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
82 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
83 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
84 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
87 #ifndef mmDP_DPHY_FAST_TRAINING
88 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
89 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
90 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
91 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
92 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
93 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
94 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
95 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
98 static const struct dce110_timing_generator_offsets dce100_tg_offsets
[] = {
100 .crtc
= (mmCRTC0_CRTC_CONTROL
- mmCRTC_CONTROL
),
101 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
104 .crtc
= (mmCRTC1_CRTC_CONTROL
- mmCRTC_CONTROL
),
105 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
108 .crtc
= (mmCRTC2_CRTC_CONTROL
- mmCRTC_CONTROL
),
109 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
112 .crtc
= (mmCRTC3_CRTC_CONTROL
- mmCRTC_CONTROL
),
113 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
116 .crtc
= (mmCRTC4_CRTC_CONTROL
- mmCRTC_CONTROL
),
117 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
120 .crtc
= (mmCRTC5_CRTC_CONTROL
- mmCRTC_CONTROL
),
121 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
125 static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets
[] = {
127 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
128 .dmif
= (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
129 - mmDPG_WATERMARK_MASK_CONTROL
),
130 .pipe
= (mmPIPE0_DMIF_BUFFER_CONTROL
131 - mmPIPE0_DMIF_BUFFER_CONTROL
),
134 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
135 .dmif
= (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
136 - mmDPG_WATERMARK_MASK_CONTROL
),
137 .pipe
= (mmPIPE1_DMIF_BUFFER_CONTROL
138 - mmPIPE0_DMIF_BUFFER_CONTROL
),
141 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
142 .dmif
= (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
143 - mmDPG_WATERMARK_MASK_CONTROL
),
144 .pipe
= (mmPIPE2_DMIF_BUFFER_CONTROL
145 - mmPIPE0_DMIF_BUFFER_CONTROL
),
148 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
149 .dmif
= (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
150 - mmDPG_WATERMARK_MASK_CONTROL
),
151 .pipe
= (mmPIPE3_DMIF_BUFFER_CONTROL
152 - mmPIPE0_DMIF_BUFFER_CONTROL
),
155 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
156 .dmif
= (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
157 - mmDPG_WATERMARK_MASK_CONTROL
),
158 .pipe
= (mmPIPE4_DMIF_BUFFER_CONTROL
159 - mmPIPE0_DMIF_BUFFER_CONTROL
),
162 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
163 .dmif
= (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
164 - mmDPG_WATERMARK_MASK_CONTROL
),
165 .pipe
= (mmPIPE5_DMIF_BUFFER_CONTROL
166 - mmPIPE0_DMIF_BUFFER_CONTROL
),
171 static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets
[] = {
173 .dcp_offset
= (mmDCP0_CUR_CONTROL
- mmCUR_CONTROL
),
176 .dcp_offset
= (mmDCP1_CUR_CONTROL
- mmCUR_CONTROL
),
179 .dcp_offset
= (mmDCP2_CUR_CONTROL
- mmCUR_CONTROL
),
182 .dcp_offset
= (mmDCP3_CUR_CONTROL
- mmCUR_CONTROL
),
185 .dcp_offset
= (mmDCP4_CUR_CONTROL
- mmCUR_CONTROL
),
188 .dcp_offset
= (mmDCP5_CUR_CONTROL
- mmCUR_CONTROL
),
194 /* set register offset */
195 #define SR(reg_name)\
196 .reg_name = mm ## reg_name
198 /* set register offset with instance */
199 #define SRI(reg_name, block, id)\
200 .reg_name = mm ## block ## id ## _ ## reg_name
203 #define transform_regs(id)\
205 XFM_COMMON_REG_LIST_DCE100(id)\
208 static const struct dce_transform_registers xfm_regs
[] = {
217 static const struct dce_transform_shift xfm_shift
= {
218 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT
)
221 static const struct dce_transform_mask xfm_mask
= {
222 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK
)
225 #define aux_regs(id)\
230 static const struct dce110_link_enc_aux_registers link_enc_aux_regs
[] = {
239 #define hpd_regs(id)\
244 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs
[] = {
253 #define link_regs(id)\
255 LE_DCE110_REG_LIST(id)\
258 static const struct dce110_link_enc_registers link_enc_regs
[] = {
268 #define stream_enc_regs(id)\
270 SE_COMMON_REG_LIST_DCE_BASE(id),\
274 static const struct dce110_stream_enc_registers stream_enc_regs
[] = {
284 static const struct dce_stream_encoder_shift se_shift
= {
285 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT
)
288 static const struct dce_stream_encoder_mask se_mask
= {
289 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK
)
292 #define audio_regs(id)\
294 AUD_COMMON_REG_LIST(id)\
297 static const struct dce_audio_registers audio_regs
[] = {
307 static const struct dce_audio_shift audio_shift
= {
308 AUD_COMMON_MASK_SH_LIST(__SHIFT
)
311 static const struct dce_aduio_mask audio_mask
= {
312 AUD_COMMON_MASK_SH_LIST(_MASK
)
315 #define clk_src_regs(id)\
317 CS_COMMON_REG_LIST_DCE_100_110(id),\
320 static const struct dce110_clk_src_regs clk_src_regs
[] = {
326 static const struct dce110_clk_src_shift cs_shift
= {
327 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
330 static const struct dce110_clk_src_mask cs_mask
= {
331 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
336 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
338 static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets
[] = {
340 .fmt_offset
= (mmFMT0_FMT_CONTROL
- mmFMT_CONTROL
),
341 .dcfe_offset
= (mmCRTC0_DCFE_MEM_PWR_CTRL
- DCFE_MEM_PWR_CTRL_REG_BASE
),
342 .dcp_offset
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
344 { .fmt_offset
= (mmFMT1_FMT_CONTROL
- mmFMT0_FMT_CONTROL
),
345 .dcfe_offset
= (mmCRTC1_DCFE_MEM_PWR_CTRL
- DCFE_MEM_PWR_CTRL_REG_BASE
),
346 .dcp_offset
= (mmDCP1_GRPH_CONTROL
- mmDCP0_GRPH_CONTROL
),
348 { .fmt_offset
= (mmFMT2_FMT_CONTROL
- mmFMT0_FMT_CONTROL
),
349 .dcfe_offset
= (mmCRTC2_DCFE_MEM_PWR_CTRL
- DCFE_MEM_PWR_CTRL_REG_BASE
),
350 .dcp_offset
= (mmDCP2_GRPH_CONTROL
- mmDCP0_GRPH_CONTROL
),
353 .fmt_offset
= (mmFMT3_FMT_CONTROL
- mmFMT0_FMT_CONTROL
),
354 .dcfe_offset
= (mmCRTC3_DCFE_MEM_PWR_CTRL
- DCFE_MEM_PWR_CTRL_REG_BASE
),
355 .dcp_offset
= (mmDCP3_GRPH_CONTROL
- mmDCP0_GRPH_CONTROL
),
357 { .fmt_offset
= (mmFMT4_FMT_CONTROL
- mmFMT0_FMT_CONTROL
),
358 .dcfe_offset
= (mmCRTC4_DCFE_MEM_PWR_CTRL
- DCFE_MEM_PWR_CTRL_REG_BASE
),
359 .dcp_offset
= (mmDCP4_GRPH_CONTROL
- mmDCP0_GRPH_CONTROL
),
361 { .fmt_offset
= (mmFMT5_FMT_CONTROL
- mmFMT0_FMT_CONTROL
),
362 .dcfe_offset
= (mmCRTC5_DCFE_MEM_PWR_CTRL
- DCFE_MEM_PWR_CTRL_REG_BASE
),
363 .dcp_offset
= (mmDCP5_GRPH_CONTROL
- mmDCP0_GRPH_CONTROL
),
367 static const struct bios_registers bios_regs
= {
368 .BIOS_SCRATCH_6
= mmBIOS_SCRATCH_6
371 static const struct resource_caps res_cap
= {
372 .num_timing_generator
= 6,
374 .num_stream_encoder
= 6,
379 #define REG(reg) mm ## reg
381 #ifndef mmCC_DC_HDMI_STRAPS
382 #define mmCC_DC_HDMI_STRAPS 0x1918
383 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
384 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
385 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
386 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
389 static void read_dce_straps(
390 struct dc_context
*ctx
,
391 struct resource_straps
*straps
)
393 REG_GET_2(CC_DC_HDMI_STRAPS
,
394 HDMI_DISABLE
, &straps
->hdmi_disable
,
395 AUDIO_STREAM_NUMBER
, &straps
->audio_stream_number
);
397 REG_GET(DC_PINSTRAPS
, DC_PINSTRAPS_AUDIO
, &straps
->dc_pinstraps_audio
);
400 static struct audio
*create_audio(
401 struct dc_context
*ctx
, unsigned int inst
)
403 return dce_audio_create(ctx
, inst
,
404 &audio_regs
[inst
], &audio_shift
, &audio_mask
);
407 static struct timing_generator
*dce100_timing_generator_create(
408 struct dc_context
*ctx
,
410 const struct dce110_timing_generator_offsets
*offsets
)
412 struct dce110_timing_generator
*tg110
=
413 dm_alloc(sizeof(struct dce110_timing_generator
));
418 if (dce110_timing_generator_construct(tg110
, ctx
, instance
,
427 static struct stream_encoder
*dce100_stream_encoder_create(
428 enum engine_id eng_id
,
429 struct dc_context
*ctx
)
431 struct dce110_stream_encoder
*enc110
=
432 dm_alloc(sizeof(struct dce110_stream_encoder
));
437 if (dce110_stream_encoder_construct(
438 enc110
, ctx
, ctx
->dc_bios
, eng_id
,
439 &stream_enc_regs
[eng_id
], &se_shift
, &se_mask
))
440 return &enc110
->base
;
447 #define SRII(reg_name, block, id)\
448 .reg_name[id] = mm ## block ## id ## _ ## reg_name
450 static const struct dce_hwseq_registers hwseq_reg
= {
451 HWSEQ_DCE10_REG_LIST()
454 static const struct dce_hwseq_shift hwseq_shift
= {
455 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT
)
458 static const struct dce_hwseq_mask hwseq_mask
= {
459 HWSEQ_DCE10_MASK_SH_LIST(_MASK
)
462 static struct dce_hwseq
*dce100_hwseq_create(
463 struct dc_context
*ctx
)
465 struct dce_hwseq
*hws
= dm_alloc(sizeof(struct dce_hwseq
));
469 hws
->regs
= &hwseq_reg
;
470 hws
->shifts
= &hwseq_shift
;
471 hws
->masks
= &hwseq_mask
;
476 static const struct resource_create_funcs res_create_funcs
= {
477 .read_dce_straps
= read_dce_straps
,
478 .create_audio
= create_audio
,
479 .create_stream_encoder
= dce100_stream_encoder_create
,
480 .create_hwseq
= dce100_hwseq_create
,
483 #define mi_inst_regs(id) { \
484 MI_DCE8_REG_LIST(id), \
485 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
487 static const struct dce_mem_input_registers mi_regs
[] = {
496 static const struct dce_mem_input_shift mi_shifts
= {
497 MI_DCE8_MASK_SH_LIST(__SHIFT
),
498 .ENABLE
= MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
501 static const struct dce_mem_input_mask mi_masks
= {
502 MI_DCE8_MASK_SH_LIST(_MASK
),
503 .ENABLE
= MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
506 static struct mem_input
*dce100_mem_input_create(
507 struct dc_context
*ctx
,
509 const struct dce110_mem_input_reg_offsets
*offset
)
511 struct dce110_mem_input
*mem_input110
=
512 dm_alloc(sizeof(struct dce110_mem_input
));
517 if (dce110_mem_input_construct(mem_input110
, ctx
, inst
, offset
)) {
518 struct mem_input
*mi
= &mem_input110
->base
;
520 mi
->regs
= &mi_regs
[inst
];
521 mi
->shifts
= &mi_shifts
;
522 mi
->masks
= &mi_masks
;
523 mi
->wa
.single_head_rdreq_dmif_limit
= 2;
528 dm_free(mem_input110
);
532 static void dce100_transform_destroy(struct transform
**xfm
)
534 dm_free(TO_DCE_TRANSFORM(*xfm
));
538 static struct transform
*dce100_transform_create(
539 struct dc_context
*ctx
,
542 struct dce_transform
*transform
=
543 dm_alloc(sizeof(struct dce_transform
));
548 if (dce_transform_construct(transform
, ctx
, inst
,
549 &xfm_regs
[inst
], &xfm_shift
, &xfm_mask
)) {
550 return &transform
->base
;
558 static struct input_pixel_processor
*dce100_ipp_create(
559 struct dc_context
*ctx
,
561 const struct dce110_ipp_reg_offsets
*offsets
)
563 struct dce110_ipp
*ipp
=
564 dm_alloc(sizeof(struct dce110_ipp
));
569 if (dce110_ipp_construct(ipp
, ctx
, inst
, offsets
))
577 struct link_encoder
*dce100_link_encoder_create(
578 const struct encoder_init_data
*enc_init_data
)
580 struct dce110_link_encoder
*enc110
=
581 dm_alloc(sizeof(struct dce110_link_encoder
));
586 if (dce110_link_encoder_construct(
589 &link_enc_regs
[enc_init_data
->transmitter
],
590 &link_enc_aux_regs
[enc_init_data
->channel
- 1],
591 &link_enc_hpd_regs
[enc_init_data
->hpd_source
])) {
593 enc110
->base
.features
.ycbcr420_supported
= false;
594 enc110
->base
.features
.max_hdmi_pixel_clock
= 300000;
595 return &enc110
->base
;
603 struct output_pixel_processor
*dce100_opp_create(
604 struct dc_context
*ctx
,
606 const struct dce110_opp_reg_offsets
*offset
)
608 struct dce110_opp
*opp
=
609 dm_alloc(sizeof(struct dce110_opp
));
614 if (dce110_opp_construct(opp
,
623 void dce100_opp_destroy(struct output_pixel_processor
**opp
)
625 struct dce110_opp
*dce110_opp
;
630 dce110_opp
= FROM_DCE11_OPP(*opp
);
632 dm_free(dce110_opp
->regamma
.coeff128_dx
);
633 dm_free(dce110_opp
->regamma
.coeff128_oem
);
634 dm_free(dce110_opp
->regamma
.coeff128
);
635 dm_free(dce110_opp
->regamma
.axis_x_1025
);
636 dm_free(dce110_opp
->regamma
.axis_x_256
);
637 dm_free(dce110_opp
->regamma
.coordinates_x
);
638 dm_free(dce110_opp
->regamma
.rgb_regamma
);
639 dm_free(dce110_opp
->regamma
.rgb_resulted
);
640 dm_free(dce110_opp
->regamma
.rgb_oem
);
641 dm_free(dce110_opp
->regamma
.rgb_user
);
647 struct clock_source
*dce100_clock_source_create(
648 struct dc_context
*ctx
,
649 struct dc_bios
*bios
,
650 enum clock_source_id id
,
651 const struct dce110_clk_src_regs
*regs
,
654 struct dce110_clk_src
*clk_src
=
655 dm_alloc(sizeof(struct dce110_clk_src
));
660 if (dce110_clk_src_construct(clk_src
, ctx
, bios
, id
,
661 regs
, &cs_shift
, &cs_mask
)) {
662 clk_src
->base
.dp_clk_src
= dp_clk_src
;
663 return &clk_src
->base
;
670 void dce100_clock_source_destroy(struct clock_source
**clk_src
)
672 dm_free(TO_DCE110_CLK_SRC(*clk_src
));
676 static void destruct(struct dce110_resource_pool
*pool
)
680 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
681 if (pool
->base
.opps
[i
] != NULL
)
682 dce100_opp_destroy(&pool
->base
.opps
[i
]);
684 if (pool
->base
.transforms
[i
] != NULL
)
685 dce100_transform_destroy(&pool
->base
.transforms
[i
]);
687 if (pool
->base
.ipps
[i
] != NULL
)
688 dce110_ipp_destroy(&pool
->base
.ipps
[i
]);
690 if (pool
->base
.mis
[i
] != NULL
) {
691 dm_free(TO_DCE110_MEM_INPUT(pool
->base
.mis
[i
]));
692 pool
->base
.mis
[i
] = NULL
;
695 if (pool
->base
.timing_generators
[i
] != NULL
) {
696 dm_free(DCE110TG_FROM_TG(pool
->base
.timing_generators
[i
]));
697 pool
->base
.timing_generators
[i
] = NULL
;
701 for (i
= 0; i
< pool
->base
.stream_enc_count
; i
++) {
702 if (pool
->base
.stream_enc
[i
] != NULL
)
703 dm_free(DCE110STRENC_FROM_STRENC(pool
->base
.stream_enc
[i
]));
706 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
707 if (pool
->base
.clock_sources
[i
] != NULL
)
708 dce100_clock_source_destroy(&pool
->base
.clock_sources
[i
]);
711 if (pool
->base
.dp_clock_source
!= NULL
)
712 dce100_clock_source_destroy(&pool
->base
.dp_clock_source
);
714 for (i
= 0; i
< pool
->base
.audio_count
; i
++) {
715 if (pool
->base
.audios
[i
] != NULL
)
716 dce_aud_destroy(&pool
->base
.audios
[i
]);
719 if (pool
->base
.display_clock
!= NULL
)
720 pool
->base
.display_clock
->funcs
->destroy(
721 &pool
->base
.display_clock
);
722 pool
->base
.display_clock
= NULL
;
724 if (pool
->base
.irqs
!= NULL
)
725 dal_irq_service_destroy(&pool
->base
.irqs
);
728 static enum dc_status
validate_mapped_resource(
729 const struct core_dc
*dc
,
730 struct validate_context
*context
)
732 enum dc_status status
= DC_OK
;
735 for (i
= 0; i
< context
->target_count
; i
++) {
736 struct core_target
*target
= context
->targets
[i
];
738 for (j
= 0; j
< target
->public.stream_count
; j
++) {
739 struct core_stream
*stream
=
740 DC_STREAM_TO_CORE(target
->public.streams
[j
]);
741 struct core_link
*link
= stream
->sink
->link
;
743 if (resource_is_stream_unchanged(dc
->current_context
, stream
))
746 for (k
= 0; k
< MAX_PIPES
; k
++) {
747 struct pipe_ctx
*pipe_ctx
=
748 &context
->res_ctx
.pipe_ctx
[k
];
750 if (context
->res_ctx
.pipe_ctx
[k
].stream
!= stream
)
753 if (!pipe_ctx
->tg
->funcs
->validate_timing(
754 pipe_ctx
->tg
, &stream
->public.timing
))
755 return DC_FAIL_CONTROLLER_VALIDATE
;
757 status
= dce110_resource_build_pipe_hw_param(pipe_ctx
);
762 if (!link
->link_enc
->funcs
->validate_output_with_stream(
765 return DC_FAIL_ENC_VALIDATE
;
767 /* TODO: validate audio ASIC caps, encoder */
768 status
= dc_link_validate_mode_timing(stream
,
770 &stream
->public.timing
);
775 resource_build_info_frame(pipe_ctx
);
777 /* do not need to validate non root pipes */
786 enum dc_status
dce100_validate_bandwidth(
787 const struct core_dc
*dc
,
788 struct validate_context
*context
)
790 /* TODO implement when needed but for now hardcode max value*/
791 context
->bw_results
.dispclk_khz
= 681000;
796 static bool dce100_validate_surface_sets(
797 const struct dc_validation_set set
[],
802 for (i
= 0; i
< set_count
; i
++) {
803 if (set
[i
].surface_count
== 0)
806 if (set
[i
].surface_count
> 1)
809 if (set
[i
].surfaces
[0]->clip_rect
.width
810 != set
[i
].target
->streams
[0]->src
.width
811 || set
[i
].surfaces
[0]->clip_rect
.height
812 != set
[i
].target
->streams
[0]->src
.height
)
814 if (set
[i
].surfaces
[0]->format
815 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
822 enum dc_status
dce100_validate_with_context(
823 const struct core_dc
*dc
,
824 const struct dc_validation_set set
[],
826 struct validate_context
*context
)
828 struct dc_context
*dc_ctx
= dc
->ctx
;
829 enum dc_status result
= DC_ERROR_UNEXPECTED
;
832 if (!dce100_validate_surface_sets(set
, set_count
))
833 return DC_FAIL_SURFACE_VALIDATE
;
835 context
->res_ctx
.pool
= dc
->res_pool
;
837 for (i
= 0; i
< set_count
; i
++) {
838 context
->targets
[i
] = DC_TARGET_TO_CORE(set
[i
].target
);
839 dc_target_retain(&context
->targets
[i
]->public);
840 context
->target_count
++;
843 result
= resource_map_pool_resources(dc
, context
);
846 result
= resource_map_clock_resources(dc
, context
);
848 if (!resource_validate_attach_surfaces(
849 set
, set_count
, dc
->current_context
, context
)) {
850 DC_ERROR("Failed to attach surface to target!\n");
851 return DC_FAIL_ATTACH_SURFACES
;
855 result
= validate_mapped_resource(dc
, context
);
858 result
= resource_build_scaling_params_for_context(dc
, context
);
861 result
= dce100_validate_bandwidth(dc
, context
);
866 enum dc_status
dce100_validate_guaranteed(
867 const struct core_dc
*dc
,
868 const struct dc_target
*dc_target
,
869 struct validate_context
*context
)
871 enum dc_status result
= DC_ERROR_UNEXPECTED
;
873 context
->res_ctx
.pool
= dc
->res_pool
;
875 context
->targets
[0] = DC_TARGET_TO_CORE(dc_target
);
876 dc_target_retain(&context
->targets
[0]->public);
877 context
->target_count
++;
879 result
= resource_map_pool_resources(dc
, context
);
882 result
= resource_map_clock_resources(dc
, context
);
885 result
= validate_mapped_resource(dc
, context
);
887 if (result
== DC_OK
) {
888 validate_guaranteed_copy_target(
889 context
, dc
->public.caps
.max_targets
);
890 result
= resource_build_scaling_params_for_context(dc
, context
);
894 result
= dce100_validate_bandwidth(dc
, context
);
899 static void dce100_destroy_resource_pool(struct resource_pool
**pool
)
901 struct dce110_resource_pool
*dce110_pool
= TO_DCE110_RES_POOL(*pool
);
903 destruct(dce110_pool
);
904 dm_free(dce110_pool
);
908 static const struct resource_funcs dce100_res_pool_funcs
= {
909 .destroy
= dce100_destroy_resource_pool
,
910 .link_enc_create
= dce100_link_encoder_create
,
911 .validate_with_context
= dce100_validate_with_context
,
912 .validate_guaranteed
= dce100_validate_guaranteed
,
913 .validate_bandwidth
= dce100_validate_bandwidth
916 static bool construct(
917 uint8_t num_virtual_links
,
919 struct dce110_resource_pool
*pool
)
922 struct dc_context
*ctx
= dc
->ctx
;
923 struct firmware_info info
;
925 struct dm_pp_static_clock_info static_clk_info
= {0};
927 ctx
->dc_bios
->regs
= &bios_regs
;
929 pool
->base
.res_cap
= &res_cap
;
930 pool
->base
.funcs
= &dce100_res_pool_funcs
;
931 pool
->base
.underlay_pipe_index
= -1;
935 if ((bp
->funcs
->get_firmware_info(bp
, &info
) == BP_RESULT_OK
) &&
936 info
.external_clock_source_frequency_for_dp
!= 0) {
937 pool
->base
.dp_clock_source
=
938 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_EXTERNAL
, NULL
, true);
940 pool
->base
.clock_sources
[0] =
941 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL0
, &clk_src_regs
[0], false);
942 pool
->base
.clock_sources
[1] =
943 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL1
, &clk_src_regs
[1], false);
944 pool
->base
.clock_sources
[2] =
945 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL2
, &clk_src_regs
[2], false);
946 pool
->base
.clk_src_count
= 3;
949 pool
->base
.dp_clock_source
=
950 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL0
, &clk_src_regs
[0], true);
952 pool
->base
.clock_sources
[0] =
953 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL1
, &clk_src_regs
[1], false);
954 pool
->base
.clock_sources
[1] =
955 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL2
, &clk_src_regs
[2], false);
956 pool
->base
.clk_src_count
= 2;
959 if (pool
->base
.dp_clock_source
== NULL
) {
960 dm_error("DC: failed to create dp clock source!\n");
962 goto res_create_fail
;
965 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
966 if (pool
->base
.clock_sources
[i
] == NULL
) {
967 dm_error("DC: failed to create clock sources!\n");
969 goto res_create_fail
;
973 pool
->base
.display_clock
= dal_display_clock_dce110_create(ctx
);
974 if (pool
->base
.display_clock
== NULL
) {
975 dm_error("DC: failed to create display clock!\n");
977 goto res_create_fail
;
981 /* get static clock information for PPLIB or firmware, save
984 if (dm_pp_get_static_clocks(ctx
, &static_clk_info
)) {
985 enum clocks_state max_clocks_state
=
986 dce110_resource_convert_clock_state_pp_to_dc(
987 static_clk_info
.max_clocks_state
);
989 pool
->base
.display_clock
->funcs
->store_max_clocks_state(
990 pool
->base
.display_clock
, max_clocks_state
);
993 struct irq_service_init_data init_data
;
994 init_data
.ctx
= dc
->ctx
;
995 pool
->base
.irqs
= dal_irq_service_dce110_create(&init_data
);
996 if (!pool
->base
.irqs
)
997 goto res_create_fail
;
1000 /*************************************************
1001 * Resource + asic cap harcoding *
1002 *************************************************/
1003 pool
->base
.underlay_pipe_index
= -1;
1004 pool
->base
.pipe_count
= res_cap
.num_timing_generator
;
1005 dc
->public.caps
.max_downscale_ratio
= 200;
1006 dc
->public.caps
.i2c_speed_in_khz
= 40;
1008 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
1009 pool
->base
.timing_generators
[i
] =
1010 dce100_timing_generator_create(
1013 &dce100_tg_offsets
[i
]);
1014 if (pool
->base
.timing_generators
[i
] == NULL
) {
1015 BREAK_TO_DEBUGGER();
1016 dm_error("DC: failed to create tg!\n");
1017 goto res_create_fail
;
1020 pool
->base
.mis
[i
] = dce100_mem_input_create(ctx
, i
,
1021 &dce100_mi_reg_offsets
[i
]);
1022 if (pool
->base
.mis
[i
] == NULL
) {
1023 BREAK_TO_DEBUGGER();
1025 "DC: failed to create memory input!\n");
1026 goto res_create_fail
;
1029 pool
->base
.ipps
[i
] = dce100_ipp_create(ctx
, i
,
1030 &dce100_ipp_reg_offsets
[i
]);
1031 if (pool
->base
.ipps
[i
] == NULL
) {
1032 BREAK_TO_DEBUGGER();
1034 "DC: failed to create input pixel processor!\n");
1035 goto res_create_fail
;
1038 pool
->base
.transforms
[i
] = dce100_transform_create(ctx
, i
);
1039 if (pool
->base
.transforms
[i
] == NULL
) {
1040 BREAK_TO_DEBUGGER();
1042 "DC: failed to create transform!\n");
1043 goto res_create_fail
;
1046 pool
->base
.opps
[i
] = dce100_opp_create(ctx
, i
, &dce100_opp_reg_offsets
[i
]);
1047 if (pool
->base
.opps
[i
] == NULL
) {
1048 BREAK_TO_DEBUGGER();
1050 "DC: failed to create output pixel processor!\n");
1051 goto res_create_fail
;
1055 if (!resource_construct(num_virtual_links
, dc
, &pool
->base
,
1057 goto res_create_fail
;
1059 /* Create hardware sequencer */
1060 if (!dce100_hw_sequencer_construct(dc
))
1061 goto res_create_fail
;
1071 struct resource_pool
*dce100_create_resource_pool(
1072 uint8_t num_virtual_links
,
1075 struct dce110_resource_pool
*pool
=
1076 dm_alloc(sizeof(struct dce110_resource_pool
));
1081 if (construct(num_virtual_links
, dc
, pool
))
1084 BREAK_TO_DEBUGGER();