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drm/amd/display: safeguard compressor api
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "resource.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35
36 #ifdef ENABLE_FBC
37 #include "dce110_compressor.h"
38 #endif
39
40 #include "bios/bios_parser_helper.h"
41 #include "timing_generator.h"
42 #include "mem_input.h"
43 #include "opp.h"
44 #include "ipp.h"
45 #include "transform.h"
46 #include "stream_encoder.h"
47 #include "link_encoder.h"
48 #include "clock_source.h"
49 #include "abm.h"
50 #include "audio.h"
51 #include "dce/dce_hwseq.h"
52 #include "reg_helper.h"
53
54 /* include DCE11 register header files */
55 #include "dce/dce_11_0_d.h"
56 #include "dce/dce_11_0_sh_mask.h"
57 #include "custom_float.h"
58
59 struct dce110_hw_seq_reg_offsets {
60 uint32_t crtc;
61 };
62
63 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
64 {
65 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
66 },
67 {
68 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
69 },
70 {
71 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
72 },
73 {
74 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
75 }
76 };
77
78 #define HW_REG_BLND(reg, id)\
79 (reg + reg_offsets[id].blnd)
80
81 #define HW_REG_CRTC(reg, id)\
82 (reg + reg_offsets[id].crtc)
83
84 #define MAX_WATERMARK 0xFFFF
85 #define SAFE_NBP_MARK 0x7FFF
86
87 /*******************************************************************************
88 * Private definitions
89 ******************************************************************************/
90 /***************************PIPE_CONTROL***********************************/
91 static void dce110_init_pte(struct dc_context *ctx)
92 {
93 uint32_t addr;
94 uint32_t value = 0;
95 uint32_t chunk_int = 0;
96 uint32_t chunk_mul = 0;
97
98 addr = mmUNP_DVMM_PTE_CONTROL;
99 value = dm_read_reg(ctx, addr);
100
101 set_reg_field_value(
102 value,
103 0,
104 DVMM_PTE_CONTROL,
105 DVMM_USE_SINGLE_PTE);
106
107 set_reg_field_value(
108 value,
109 1,
110 DVMM_PTE_CONTROL,
111 DVMM_PTE_BUFFER_MODE0);
112
113 set_reg_field_value(
114 value,
115 1,
116 DVMM_PTE_CONTROL,
117 DVMM_PTE_BUFFER_MODE1);
118
119 dm_write_reg(ctx, addr, value);
120
121 addr = mmDVMM_PTE_REQ;
122 value = dm_read_reg(ctx, addr);
123
124 chunk_int = get_reg_field_value(
125 value,
126 DVMM_PTE_REQ,
127 HFLIP_PTEREQ_PER_CHUNK_INT);
128
129 chunk_mul = get_reg_field_value(
130 value,
131 DVMM_PTE_REQ,
132 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
133
134 if (chunk_int != 0x4 || chunk_mul != 0x4) {
135
136 set_reg_field_value(
137 value,
138 255,
139 DVMM_PTE_REQ,
140 MAX_PTEREQ_TO_ISSUE);
141
142 set_reg_field_value(
143 value,
144 4,
145 DVMM_PTE_REQ,
146 HFLIP_PTEREQ_PER_CHUNK_INT);
147
148 set_reg_field_value(
149 value,
150 4,
151 DVMM_PTE_REQ,
152 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
153
154 dm_write_reg(ctx, addr, value);
155 }
156 }
157 /**************************************************************************/
158
159 static void enable_display_pipe_clock_gating(
160 struct dc_context *ctx,
161 bool clock_gating)
162 {
163 /*TODO*/
164 }
165
166 static bool dce110_enable_display_power_gating(
167 struct core_dc *dc,
168 uint8_t controller_id,
169 struct dc_bios *dcb,
170 enum pipe_gating_control power_gating)
171 {
172 enum bp_result bp_result = BP_RESULT_OK;
173 enum bp_pipe_control_action cntl;
174 struct dc_context *ctx = dc->ctx;
175 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
176
177 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
178 return true;
179
180 if (power_gating == PIPE_GATING_CONTROL_INIT)
181 cntl = ASIC_PIPE_INIT;
182 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
183 cntl = ASIC_PIPE_ENABLE;
184 else
185 cntl = ASIC_PIPE_DISABLE;
186
187 if (controller_id == underlay_idx)
188 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
189
190 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
191
192 bp_result = dcb->funcs->enable_disp_power_gating(
193 dcb, controller_id + 1, cntl);
194
195 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
196 * by default when command table is called
197 *
198 * Bios parser accepts controller_id = 6 as indicative of
199 * underlay pipe in dce110. But we do not support more
200 * than 3.
201 */
202 if (controller_id < CONTROLLER_ID_MAX - 1)
203 dm_write_reg(ctx,
204 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
205 0);
206 }
207
208 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
209 dce110_init_pte(ctx);
210
211 if (bp_result == BP_RESULT_OK)
212 return true;
213 else
214 return false;
215 }
216
217 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
218 const struct dc_surface *surface)
219 {
220 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
221
222 switch (surface->format) {
223 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
224 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
225 prescale_params->scale = 0x2020;
226 break;
227 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
228 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
229 prescale_params->scale = 0x2008;
230 break;
231 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
232 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
233 prescale_params->scale = 0x2000;
234 break;
235 default:
236 ASSERT(false);
237 break;
238 }
239 }
240
241 static bool dce110_set_input_transfer_func(
242 struct pipe_ctx *pipe_ctx,
243 const struct dc_surface *surface)
244 {
245 struct input_pixel_processor *ipp = pipe_ctx->ipp;
246 const struct dc_transfer_func *tf = NULL;
247 struct ipp_prescale_params prescale_params = { 0 };
248 bool result = true;
249
250 if (ipp == NULL)
251 return false;
252
253 if (surface->in_transfer_func)
254 tf = surface->in_transfer_func;
255
256 build_prescale_params(&prescale_params, surface);
257 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
258
259 if (surface->gamma_correction && dce_use_lut(surface))
260 ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction);
261
262 if (tf == NULL) {
263 /* Default case if no input transfer function specified */
264 ipp->funcs->ipp_set_degamma(ipp,
265 IPP_DEGAMMA_MODE_HW_sRGB);
266 } else if (tf->type == TF_TYPE_PREDEFINED) {
267 switch (tf->tf) {
268 case TRANSFER_FUNCTION_SRGB:
269 ipp->funcs->ipp_set_degamma(ipp,
270 IPP_DEGAMMA_MODE_HW_sRGB);
271 break;
272 case TRANSFER_FUNCTION_BT709:
273 ipp->funcs->ipp_set_degamma(ipp,
274 IPP_DEGAMMA_MODE_HW_xvYCC);
275 break;
276 case TRANSFER_FUNCTION_LINEAR:
277 ipp->funcs->ipp_set_degamma(ipp,
278 IPP_DEGAMMA_MODE_BYPASS);
279 break;
280 case TRANSFER_FUNCTION_PQ:
281 result = false;
282 break;
283 default:
284 result = false;
285 break;
286 }
287 } else if (tf->type == TF_TYPE_BYPASS) {
288 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
289 } else {
290 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
291 result = false;
292 }
293
294 return result;
295 }
296
297 static bool convert_to_custom_float(
298 struct pwl_result_data *rgb_resulted,
299 struct curve_points *arr_points,
300 uint32_t hw_points_num)
301 {
302 struct custom_float_format fmt;
303
304 struct pwl_result_data *rgb = rgb_resulted;
305
306 uint32_t i = 0;
307
308 fmt.exponenta_bits = 6;
309 fmt.mantissa_bits = 12;
310 fmt.sign = true;
311
312 if (!convert_to_custom_float_format(
313 arr_points[0].x,
314 &fmt,
315 &arr_points[0].custom_float_x)) {
316 BREAK_TO_DEBUGGER();
317 return false;
318 }
319
320 if (!convert_to_custom_float_format(
321 arr_points[0].offset,
322 &fmt,
323 &arr_points[0].custom_float_offset)) {
324 BREAK_TO_DEBUGGER();
325 return false;
326 }
327
328 if (!convert_to_custom_float_format(
329 arr_points[0].slope,
330 &fmt,
331 &arr_points[0].custom_float_slope)) {
332 BREAK_TO_DEBUGGER();
333 return false;
334 }
335
336 fmt.mantissa_bits = 10;
337 fmt.sign = false;
338
339 if (!convert_to_custom_float_format(
340 arr_points[1].x,
341 &fmt,
342 &arr_points[1].custom_float_x)) {
343 BREAK_TO_DEBUGGER();
344 return false;
345 }
346
347 if (!convert_to_custom_float_format(
348 arr_points[1].y,
349 &fmt,
350 &arr_points[1].custom_float_y)) {
351 BREAK_TO_DEBUGGER();
352 return false;
353 }
354
355 if (!convert_to_custom_float_format(
356 arr_points[2].slope,
357 &fmt,
358 &arr_points[2].custom_float_slope)) {
359 BREAK_TO_DEBUGGER();
360 return false;
361 }
362
363 fmt.mantissa_bits = 12;
364 fmt.sign = true;
365
366 while (i != hw_points_num) {
367 if (!convert_to_custom_float_format(
368 rgb->red,
369 &fmt,
370 &rgb->red_reg)) {
371 BREAK_TO_DEBUGGER();
372 return false;
373 }
374
375 if (!convert_to_custom_float_format(
376 rgb->green,
377 &fmt,
378 &rgb->green_reg)) {
379 BREAK_TO_DEBUGGER();
380 return false;
381 }
382
383 if (!convert_to_custom_float_format(
384 rgb->blue,
385 &fmt,
386 &rgb->blue_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(
392 rgb->delta_red,
393 &fmt,
394 &rgb->delta_red_reg)) {
395 BREAK_TO_DEBUGGER();
396 return false;
397 }
398
399 if (!convert_to_custom_float_format(
400 rgb->delta_green,
401 &fmt,
402 &rgb->delta_green_reg)) {
403 BREAK_TO_DEBUGGER();
404 return false;
405 }
406
407 if (!convert_to_custom_float_format(
408 rgb->delta_blue,
409 &fmt,
410 &rgb->delta_blue_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 ++rgb;
416 ++i;
417 }
418
419 return true;
420 }
421
422 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
423 *output_tf, struct pwl_params *regamma_params)
424 {
425 struct curve_points *arr_points;
426 struct pwl_result_data *rgb_resulted;
427 struct pwl_result_data *rgb;
428 struct pwl_result_data *rgb_plus_1;
429 struct fixed31_32 y_r;
430 struct fixed31_32 y_g;
431 struct fixed31_32 y_b;
432 struct fixed31_32 y1_min;
433 struct fixed31_32 y3_max;
434
435 int32_t segment_start, segment_end;
436 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
437
438 if (output_tf == NULL || regamma_params == NULL ||
439 output_tf->type == TF_TYPE_BYPASS)
440 return false;
441
442 arr_points = regamma_params->arr_points;
443 rgb_resulted = regamma_params->rgb_resulted;
444 hw_points = 0;
445
446 memset(regamma_params, 0, sizeof(struct pwl_params));
447
448 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
449 /* 16 segments
450 * segments are from 2^-11 to 2^5
451 */
452 segment_start = -11;
453 segment_end = 5;
454
455 seg_distr[0] = 2;
456 seg_distr[1] = 2;
457 seg_distr[2] = 2;
458 seg_distr[3] = 2;
459 seg_distr[4] = 2;
460 seg_distr[5] = 2;
461 seg_distr[6] = 3;
462 seg_distr[7] = 4;
463 seg_distr[8] = 4;
464 seg_distr[9] = 4;
465 seg_distr[10] = 4;
466 seg_distr[11] = 5;
467 seg_distr[12] = 5;
468 seg_distr[13] = 5;
469 seg_distr[14] = 5;
470 seg_distr[15] = 5;
471
472 } else {
473 /* 10 segments
474 * segment is from 2^-10 to 2^0
475 */
476 segment_start = -10;
477 segment_end = 0;
478
479 seg_distr[0] = 3;
480 seg_distr[1] = 4;
481 seg_distr[2] = 4;
482 seg_distr[3] = 4;
483 seg_distr[4] = 4;
484 seg_distr[5] = 4;
485 seg_distr[6] = 4;
486 seg_distr[7] = 4;
487 seg_distr[8] = 5;
488 seg_distr[9] = 5;
489 seg_distr[10] = -1;
490 seg_distr[11] = -1;
491 seg_distr[12] = -1;
492 seg_distr[13] = -1;
493 seg_distr[14] = -1;
494 seg_distr[15] = -1;
495 }
496
497 for (k = 0; k < 16; k++) {
498 if (seg_distr[k] != -1)
499 hw_points += (1 << seg_distr[k]);
500 }
501
502 j = 0;
503 for (k = 0; k < (segment_end - segment_start); k++) {
504 increment = 32 / (1 << seg_distr[k]);
505 start_index = (segment_start + k + 25) * 32;
506 for (i = start_index; i < start_index + 32; i += increment) {
507 if (j == hw_points - 1)
508 break;
509 rgb_resulted[j].red = output_tf->tf_pts.red[i];
510 rgb_resulted[j].green = output_tf->tf_pts.green[i];
511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
512 j++;
513 }
514 }
515
516 /* last point */
517 start_index = (segment_end + 25) * 32;
518 rgb_resulted[hw_points - 1].red =
519 output_tf->tf_pts.red[start_index];
520 rgb_resulted[hw_points - 1].green =
521 output_tf->tf_pts.green[start_index];
522 rgb_resulted[hw_points - 1].blue =
523 output_tf->tf_pts.blue[start_index];
524
525 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
526 dal_fixed31_32_from_int(segment_start));
527 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
528 dal_fixed31_32_from_int(segment_end));
529 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
530 dal_fixed31_32_from_int(segment_end));
531
532 y_r = rgb_resulted[0].red;
533 y_g = rgb_resulted[0].green;
534 y_b = rgb_resulted[0].blue;
535
536 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
537
538 arr_points[0].y = y1_min;
539 arr_points[0].slope = dal_fixed31_32_div(
540 arr_points[0].y,
541 arr_points[0].x);
542
543 y_r = rgb_resulted[hw_points - 1].red;
544 y_g = rgb_resulted[hw_points - 1].green;
545 y_b = rgb_resulted[hw_points - 1].blue;
546
547 /* see comment above, m_arrPoints[1].y should be the Y value for the
548 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
549 */
550 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
551
552 arr_points[1].y = y3_max;
553 arr_points[2].y = y3_max;
554
555 arr_points[1].slope = dal_fixed31_32_zero;
556 arr_points[2].slope = dal_fixed31_32_zero;
557
558 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
559 /* for PQ, we want to have a straight line from last HW X point,
560 * and the slope to be such that we hit 1.0 at 10000 nits.
561 */
562 const struct fixed31_32 end_value =
563 dal_fixed31_32_from_int(125);
564
565 arr_points[1].slope = dal_fixed31_32_div(
566 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
567 dal_fixed31_32_sub(end_value, arr_points[1].x));
568 arr_points[2].slope = dal_fixed31_32_div(
569 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
570 dal_fixed31_32_sub(end_value, arr_points[1].x));
571 }
572
573 regamma_params->hw_points_num = hw_points;
574
575 i = 1;
576 for (k = 0; k < 16 && i < 16; k++) {
577 if (seg_distr[k] != -1) {
578 regamma_params->arr_curve_points[k].segments_num =
579 seg_distr[k];
580 regamma_params->arr_curve_points[i].offset =
581 regamma_params->arr_curve_points[k].
582 offset + (1 << seg_distr[k]);
583 }
584 i++;
585 }
586
587 if (seg_distr[k] != -1)
588 regamma_params->arr_curve_points[k].segments_num =
589 seg_distr[k];
590
591 rgb = rgb_resulted;
592 rgb_plus_1 = rgb_resulted + 1;
593
594 i = 1;
595
596 while (i != hw_points + 1) {
597 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
598 rgb_plus_1->red = rgb->red;
599 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
600 rgb_plus_1->green = rgb->green;
601 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
602 rgb_plus_1->blue = rgb->blue;
603
604 rgb->delta_red = dal_fixed31_32_sub(
605 rgb_plus_1->red,
606 rgb->red);
607 rgb->delta_green = dal_fixed31_32_sub(
608 rgb_plus_1->green,
609 rgb->green);
610 rgb->delta_blue = dal_fixed31_32_sub(
611 rgb_plus_1->blue,
612 rgb->blue);
613
614 ++rgb_plus_1;
615 ++rgb;
616 ++i;
617 }
618
619 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
620
621 return true;
622 }
623
624 static bool dce110_set_output_transfer_func(
625 struct pipe_ctx *pipe_ctx,
626 const struct dc_stream *stream)
627 {
628 struct output_pixel_processor *opp = pipe_ctx->opp;
629
630 opp->funcs->opp_power_on_regamma_lut(opp, true);
631 opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
632
633 if (stream->out_transfer_func &&
634 stream->out_transfer_func->type ==
635 TF_TYPE_PREDEFINED &&
636 stream->out_transfer_func->tf ==
637 TRANSFER_FUNCTION_SRGB) {
638 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
639 } else if (dce110_translate_regamma_to_hw_format(
640 stream->out_transfer_func, &opp->regamma_params)) {
641 opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params);
642 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
643 } else {
644 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
645 }
646
647 opp->funcs->opp_power_on_regamma_lut(opp, false);
648
649 return true;
650 }
651
652 static enum dc_status bios_parser_crtc_source_select(
653 struct pipe_ctx *pipe_ctx)
654 {
655 struct dc_bios *dcb;
656 /* call VBIOS table to set CRTC source for the HW
657 * encoder block
658 * note: video bios clears all FMT setting here. */
659 struct bp_crtc_source_select crtc_source_select = {0};
660 const struct dc_sink *sink = pipe_ctx->stream->sink;
661
662 crtc_source_select.engine_id = pipe_ctx->stream_enc->id;
663 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
664 /*TODO: Need to un-hardcode color depth, dp_audio and account for
665 * the case where signal and sink signal is different (translator
666 * encoder)*/
667 crtc_source_select.signal = pipe_ctx->stream->signal;
668 crtc_source_select.enable_dp_audio = false;
669 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
670 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
671
672 dcb = sink->ctx->dc_bios;
673
674 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
675 dcb,
676 &crtc_source_select)) {
677 return DC_ERROR_UNEXPECTED;
678 }
679
680 return DC_OK;
681 }
682
683 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
684 {
685 ASSERT(pipe_ctx->stream);
686
687 if (pipe_ctx->stream_enc == NULL)
688 return; /* this is not root pipe */
689
690 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
691 pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
692 pipe_ctx->stream_enc,
693 &pipe_ctx->encoder_info_frame);
694 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
695 pipe_ctx->stream_enc->funcs->update_dp_info_packets(
696 pipe_ctx->stream_enc,
697 &pipe_ctx->encoder_info_frame);
698 }
699
700 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
701 {
702 enum dc_lane_count lane_count =
703 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
704
705 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
706 struct dc_link *link = pipe_ctx->stream->sink->link;
707
708 /* 1. update AVI info frame (HDMI, DP)
709 * we always need to update info frame
710 */
711 uint32_t active_total_with_borders;
712 uint32_t early_control = 0;
713 struct timing_generator *tg = pipe_ctx->tg;
714
715 /* TODOFPGA may change to hwss.update_info_frame */
716 dce110_update_info_frame(pipe_ctx);
717 /* enable early control to avoid corruption on DP monitor*/
718 active_total_with_borders =
719 timing->h_addressable
720 + timing->h_border_left
721 + timing->h_border_right;
722
723 if (lane_count != 0)
724 early_control = active_total_with_borders % lane_count;
725
726 if (early_control == 0)
727 early_control = lane_count;
728
729 tg->funcs->set_early_control(tg, early_control);
730
731 /* enable audio only within mode set */
732 if (pipe_ctx->audio != NULL) {
733 if (dc_is_dp_signal(pipe_ctx->stream->signal))
734 pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc);
735 }
736
737 /* For MST, there are multiply stream go to only one link.
738 * connect DIG back_end to front_end while enable_stream and
739 * disconnect them during disable_stream
740 * BY this, it is logic clean to separate stream and link */
741 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
742 pipe_ctx->stream_enc->id, true);
743
744 }
745
746 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
747 {
748 struct dc_stream *stream = pipe_ctx->stream;
749 struct dc_link *link = stream->sink->link;
750
751 if (pipe_ctx->audio) {
752 pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio);
753
754 if (dc_is_dp_signal(pipe_ctx->stream->signal))
755 pipe_ctx->stream_enc->funcs->dp_audio_disable(
756 pipe_ctx->stream_enc);
757 else
758 pipe_ctx->stream_enc->funcs->hdmi_audio_disable(
759 pipe_ctx->stream_enc);
760
761 pipe_ctx->audio = NULL;
762
763 /* TODO: notify audio driver for if audio modes list changed
764 * add audio mode list change flag */
765 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
766 * stream->stream_engine_id);
767 */
768 }
769
770 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
771 pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets(
772 pipe_ctx->stream_enc);
773
774 if (dc_is_dp_signal(pipe_ctx->stream->signal))
775 pipe_ctx->stream_enc->funcs->stop_dp_info_packets(
776 pipe_ctx->stream_enc);
777
778 pipe_ctx->stream_enc->funcs->audio_mute_control(
779 pipe_ctx->stream_enc, true);
780
781
782 /* blank at encoder level */
783 if (dc_is_dp_signal(pipe_ctx->stream->signal))
784 pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc);
785
786 link->link_enc->funcs->connect_dig_be_to_fe(
787 link->link_enc,
788 pipe_ctx->stream_enc->id,
789 false);
790
791 }
792
793 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
794 struct dc_link_settings *link_settings)
795 {
796 struct encoder_unblank_param params = { { 0 } };
797
798 /* only 3 items below are used by unblank */
799 params.pixel_clk_khz =
800 pipe_ctx->stream->timing.pix_clk_khz;
801 params.link_settings.link_rate = link_settings->link_rate;
802 pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, &params);
803 }
804
805
806 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
807 {
808 if (pipe_ctx != NULL && pipe_ctx->stream_enc != NULL)
809 pipe_ctx->stream_enc->funcs->set_avmute(pipe_ctx->stream_enc, enable);
810 }
811
812 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
813 {
814 switch (crtc_id) {
815 case CONTROLLER_ID_D0:
816 return DTO_SOURCE_ID0;
817 case CONTROLLER_ID_D1:
818 return DTO_SOURCE_ID1;
819 case CONTROLLER_ID_D2:
820 return DTO_SOURCE_ID2;
821 case CONTROLLER_ID_D3:
822 return DTO_SOURCE_ID3;
823 case CONTROLLER_ID_D4:
824 return DTO_SOURCE_ID4;
825 case CONTROLLER_ID_D5:
826 return DTO_SOURCE_ID5;
827 default:
828 return DTO_SOURCE_UNKNOWN;
829 }
830 }
831
832 static void build_audio_output(
833 const struct pipe_ctx *pipe_ctx,
834 struct audio_output *audio_output)
835 {
836 const struct dc_stream *stream = pipe_ctx->stream;
837 audio_output->engine_id = pipe_ctx->stream_enc->id;
838
839 audio_output->signal = pipe_ctx->stream->signal;
840
841 /* audio_crtc_info */
842
843 audio_output->crtc_info.h_total =
844 stream->timing.h_total;
845
846 /*
847 * Audio packets are sent during actual CRTC blank physical signal, we
848 * need to specify actual active signal portion
849 */
850 audio_output->crtc_info.h_active =
851 stream->timing.h_addressable
852 + stream->timing.h_border_left
853 + stream->timing.h_border_right;
854
855 audio_output->crtc_info.v_active =
856 stream->timing.v_addressable
857 + stream->timing.v_border_top
858 + stream->timing.v_border_bottom;
859
860 audio_output->crtc_info.pixel_repetition = 1;
861
862 audio_output->crtc_info.interlaced =
863 stream->timing.flags.INTERLACE;
864
865 audio_output->crtc_info.refresh_rate =
866 (stream->timing.pix_clk_khz*1000)/
867 (stream->timing.h_total*stream->timing.v_total);
868
869 audio_output->crtc_info.color_depth =
870 stream->timing.display_color_depth;
871
872 audio_output->crtc_info.requested_pixel_clock =
873 pipe_ctx->pix_clk_params.requested_pix_clk;
874
875 audio_output->crtc_info.calculated_pixel_clock =
876 pipe_ctx->pix_clk_params.requested_pix_clk;
877
878 /*for HDMI, audio ACR is with deep color ratio factor*/
879 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
880 audio_output->crtc_info.requested_pixel_clock ==
881 stream->timing.pix_clk_khz) {
882 if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
883 audio_output->crtc_info.requested_pixel_clock =
884 audio_output->crtc_info.requested_pixel_clock/2;
885 audio_output->crtc_info.calculated_pixel_clock =
886 pipe_ctx->pix_clk_params.requested_pix_clk/2;
887
888 }
889 }
890
891 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
892 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
893 audio_output->pll_info.dp_dto_source_clock_in_khz =
894 pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
895 pipe_ctx->dis_clk);
896 }
897
898 audio_output->pll_info.feed_back_divider =
899 pipe_ctx->pll_settings.feedback_divider;
900
901 audio_output->pll_info.dto_source =
902 translate_to_dto_source(
903 pipe_ctx->pipe_idx + 1);
904
905 /* TODO hard code to enable for now. Need get from stream */
906 audio_output->pll_info.ss_enabled = true;
907
908 audio_output->pll_info.ss_percentage =
909 pipe_ctx->pll_settings.ss_percentage;
910 }
911
912 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
913 struct tg_color *color)
914 {
915 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
916
917 switch (pipe_ctx->scl_data.format) {
918 case PIXEL_FORMAT_ARGB8888:
919 /* set boarder color to red */
920 color->color_r_cr = color_value;
921 break;
922
923 case PIXEL_FORMAT_ARGB2101010:
924 /* set boarder color to blue */
925 color->color_b_cb = color_value;
926 break;
927 case PIXEL_FORMAT_420BPP8:
928 /* set boarder color to green */
929 color->color_g_y = color_value;
930 break;
931 case PIXEL_FORMAT_420BPP10:
932 /* set boarder color to yellow */
933 color->color_g_y = color_value;
934 color->color_r_cr = color_value;
935 break;
936 case PIXEL_FORMAT_FP16:
937 /* set boarder color to white */
938 color->color_r_cr = color_value;
939 color->color_b_cb = color_value;
940 color->color_g_y = color_value;
941 break;
942 default:
943 break;
944 }
945 }
946
947 static void program_scaler(const struct core_dc *dc,
948 const struct pipe_ctx *pipe_ctx)
949 {
950 struct tg_color color = {0};
951
952 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
953 /* TOFPGA */
954 if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL)
955 return;
956 #endif
957
958 if (dc->public.debug.surface_visual_confirm)
959 get_surface_visual_confirm_color(pipe_ctx, &color);
960 else
961 color_space_to_black_color(dc,
962 pipe_ctx->stream->output_color_space,
963 &color);
964
965 pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth(
966 pipe_ctx->xfm,
967 pipe_ctx->scl_data.lb_params.depth,
968 &pipe_ctx->stream->bit_depth_params);
969
970 if (pipe_ctx->tg->funcs->set_overscan_blank_color)
971 pipe_ctx->tg->funcs->set_overscan_blank_color(
972 pipe_ctx->tg,
973 &color);
974
975 pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm,
976 &pipe_ctx->scl_data);
977 }
978
979 static enum dc_status dce110_prog_pixclk_crtc_otg(
980 struct pipe_ctx *pipe_ctx,
981 struct validate_context *context,
982 struct core_dc *dc)
983 {
984 struct dc_stream *stream = pipe_ctx->stream;
985 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
986 pipe_ctx[pipe_ctx->pipe_idx];
987 struct tg_color black_color = {0};
988
989 if (!pipe_ctx_old->stream) {
990
991 /* program blank color */
992 color_space_to_black_color(dc,
993 stream->output_color_space, &black_color);
994 pipe_ctx->tg->funcs->set_blank_color(
995 pipe_ctx->tg,
996 &black_color);
997
998 /*
999 * Must blank CRTC after disabling power gating and before any
1000 * programming, otherwise CRTC will be hung in bad state
1001 */
1002 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
1003
1004 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1005 pipe_ctx->clock_source,
1006 &pipe_ctx->pix_clk_params,
1007 &pipe_ctx->pll_settings)) {
1008 BREAK_TO_DEBUGGER();
1009 return DC_ERROR_UNEXPECTED;
1010 }
1011
1012 pipe_ctx->tg->funcs->program_timing(
1013 pipe_ctx->tg,
1014 &stream->timing,
1015 true);
1016
1017 pipe_ctx->tg->funcs->set_static_screen_control(
1018 pipe_ctx->tg,
1019 0x182);
1020 }
1021
1022 if (!pipe_ctx_old->stream) {
1023 if (false == pipe_ctx->tg->funcs->enable_crtc(
1024 pipe_ctx->tg)) {
1025 BREAK_TO_DEBUGGER();
1026 return DC_ERROR_UNEXPECTED;
1027 }
1028 }
1029
1030
1031
1032 return DC_OK;
1033 }
1034
1035 static enum dc_status apply_single_controller_ctx_to_hw(
1036 struct pipe_ctx *pipe_ctx,
1037 struct validate_context *context,
1038 struct core_dc *dc)
1039 {
1040 struct dc_stream *stream = pipe_ctx->stream;
1041 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
1042 pipe_ctx[pipe_ctx->pipe_idx];
1043
1044 /* */
1045 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1046
1047 pipe_ctx->opp->funcs->opp_set_dyn_expansion(
1048 pipe_ctx->opp,
1049 COLOR_SPACE_YCBCR601,
1050 stream->timing.display_color_depth,
1051 pipe_ctx->stream->signal);
1052
1053 /* FPGA does not program backend */
1054 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1055 pipe_ctx->opp->funcs->opp_program_fmt(
1056 pipe_ctx->opp,
1057 &stream->bit_depth_params,
1058 &stream->clamping);
1059 return DC_OK;
1060 }
1061 /* TODO: move to stream encoder */
1062 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1063 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1064 BREAK_TO_DEBUGGER();
1065 return DC_ERROR_UNEXPECTED;
1066 }
1067
1068 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1069 stream->sink->link->link_enc->funcs->setup(
1070 stream->sink->link->link_enc,
1071 pipe_ctx->stream->signal);
1072
1073 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1074 pipe_ctx->stream_enc->funcs->setup_stereo_sync(
1075 pipe_ctx->stream_enc,
1076 pipe_ctx->tg->inst,
1077 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1078
1079
1080 /*vbios crtc_source_selection and encoder_setup will override fmt_C*/
1081 pipe_ctx->opp->funcs->opp_program_fmt(
1082 pipe_ctx->opp,
1083 &stream->bit_depth_params,
1084 &stream->clamping);
1085
1086 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1087 pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
1088 pipe_ctx->stream_enc,
1089 &stream->timing,
1090 stream->output_color_space);
1091
1092 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1093 pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute(
1094 pipe_ctx->stream_enc,
1095 &stream->timing,
1096 stream->phy_pix_clk,
1097 pipe_ctx->audio != NULL);
1098
1099 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1100 pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute(
1101 pipe_ctx->stream_enc,
1102 &stream->timing,
1103 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1104 true : false);
1105
1106 resource_build_info_frame(pipe_ctx);
1107 dce110_update_info_frame(pipe_ctx);
1108 if (!pipe_ctx_old->stream) {
1109 core_link_enable_stream(pipe_ctx);
1110
1111
1112 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1113 dce110_unblank_stream(pipe_ctx,
1114 &stream->sink->link->cur_link_settings);
1115 }
1116
1117 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1118 /* program_scaler and allocate_mem_input are not new asic */
1119 if ((!pipe_ctx_old ||
1120 memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data,
1121 sizeof(struct scaler_data)) != 0) &&
1122 pipe_ctx->surface) {
1123 program_scaler(dc, pipe_ctx);
1124 }
1125
1126 /* mst support - use total stream count */
1127 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1128 if (pipe_ctx->mi->funcs->allocate_mem_input != NULL)
1129 #endif
1130 pipe_ctx->mi->funcs->allocate_mem_input(
1131 pipe_ctx->mi,
1132 stream->timing.h_total,
1133 stream->timing.v_total,
1134 stream->timing.pix_clk_khz,
1135 context->stream_count);
1136
1137 pipe_ctx->stream->sink->link->psr_enabled = false;
1138
1139 return DC_OK;
1140 }
1141
1142 /******************************************************************************/
1143
1144 static void power_down_encoders(struct core_dc *dc)
1145 {
1146 int i;
1147
1148 for (i = 0; i < dc->link_count; i++) {
1149 dc->links[i]->link_enc->funcs->disable_output(
1150 dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
1151 }
1152 }
1153
1154 static void power_down_controllers(struct core_dc *dc)
1155 {
1156 int i;
1157
1158 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1159 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1160 dc->res_pool->timing_generators[i]);
1161 }
1162 }
1163
1164 static void power_down_clock_sources(struct core_dc *dc)
1165 {
1166 int i;
1167
1168 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1169 dc->res_pool->dp_clock_source) == false)
1170 dm_error("Failed to power down pll! (dp clk src)\n");
1171
1172 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1173 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1174 dc->res_pool->clock_sources[i]) == false)
1175 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1176 }
1177 }
1178
1179 static void power_down_all_hw_blocks(struct core_dc *dc)
1180 {
1181 power_down_encoders(dc);
1182
1183 power_down_controllers(dc);
1184
1185 power_down_clock_sources(dc);
1186
1187 #ifdef ENABLE_FBC
1188 if (dc->fbc_compressor)
1189 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1190 #endif
1191 }
1192
1193 static void disable_vga_and_power_gate_all_controllers(
1194 struct core_dc *dc)
1195 {
1196 int i;
1197 struct timing_generator *tg;
1198 struct dc_context *ctx = dc->ctx;
1199
1200 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1201 tg = dc->res_pool->timing_generators[i];
1202
1203 if (tg->funcs->disable_vga)
1204 tg->funcs->disable_vga(tg);
1205
1206 /* Enable CLOCK gating for each pipe BEFORE controller
1207 * powergating. */
1208 enable_display_pipe_clock_gating(ctx,
1209 true);
1210
1211 dc->hwss.power_down_front_end(dc, i);
1212 }
1213 }
1214
1215 /**
1216 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1217 * 1. Power down all DC HW blocks
1218 * 2. Disable VGA engine on all controllers
1219 * 3. Enable power gating for controller
1220 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1221 */
1222 void dce110_enable_accelerated_mode(struct core_dc *dc)
1223 {
1224 power_down_all_hw_blocks(dc);
1225
1226 disable_vga_and_power_gate_all_controllers(dc);
1227 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1228 }
1229
1230 static uint32_t compute_pstate_blackout_duration(
1231 struct bw_fixed blackout_duration,
1232 const struct dc_stream *stream)
1233 {
1234 uint32_t total_dest_line_time_ns;
1235 uint32_t pstate_blackout_duration_ns;
1236
1237 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1238
1239 total_dest_line_time_ns = 1000000UL *
1240 stream->timing.h_total /
1241 stream->timing.pix_clk_khz +
1242 pstate_blackout_duration_ns;
1243
1244 return total_dest_line_time_ns;
1245 }
1246
1247 void dce110_set_displaymarks(
1248 const struct core_dc *dc,
1249 struct validate_context *context)
1250 {
1251 uint8_t i, num_pipes;
1252 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1253
1254 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1255 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1256 uint32_t total_dest_line_time_ns;
1257
1258 if (pipe_ctx->stream == NULL)
1259 continue;
1260
1261 total_dest_line_time_ns = compute_pstate_blackout_duration(
1262 dc->bw_vbios.blackout_duration, pipe_ctx->stream);
1263 pipe_ctx->mi->funcs->mem_input_program_display_marks(
1264 pipe_ctx->mi,
1265 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1266 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1267 context->bw.dce.urgent_wm_ns[num_pipes],
1268 total_dest_line_time_ns);
1269 if (i == underlay_idx) {
1270 num_pipes++;
1271 pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks(
1272 pipe_ctx->mi,
1273 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1274 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1275 context->bw.dce.urgent_wm_ns[num_pipes],
1276 total_dest_line_time_ns);
1277 }
1278 num_pipes++;
1279 }
1280 }
1281
1282 static void set_safe_displaymarks(
1283 struct resource_context *res_ctx,
1284 const struct resource_pool *pool)
1285 {
1286 int i;
1287 int underlay_idx = pool->underlay_pipe_index;
1288 struct dce_watermarks max_marks = {
1289 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1290 struct dce_watermarks nbp_marks = {
1291 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1292
1293 for (i = 0; i < MAX_PIPES; i++) {
1294 if (res_ctx->pipe_ctx[i].stream == NULL)
1295 continue;
1296
1297 res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks(
1298 res_ctx->pipe_ctx[i].mi,
1299 nbp_marks,
1300 max_marks,
1301 max_marks,
1302 MAX_WATERMARK);
1303 if (i == underlay_idx)
1304 res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks(
1305 res_ctx->pipe_ctx[i].mi,
1306 nbp_marks,
1307 max_marks,
1308 max_marks,
1309 MAX_WATERMARK);
1310 }
1311 }
1312
1313 static void switch_dp_clock_sources(
1314 const struct core_dc *dc,
1315 struct resource_context *res_ctx)
1316 {
1317 uint8_t i;
1318 for (i = 0; i < MAX_PIPES; i++) {
1319 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1320
1321 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1322 continue;
1323
1324 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1325 struct clock_source *clk_src =
1326 resource_find_used_clk_src_for_sharing(
1327 res_ctx, pipe_ctx);
1328
1329 if (clk_src &&
1330 clk_src != pipe_ctx->clock_source) {
1331 resource_unreference_clock_source(
1332 res_ctx, dc->res_pool,
1333 &pipe_ctx->clock_source);
1334 pipe_ctx->clock_source = clk_src;
1335 resource_reference_clock_source(
1336 res_ctx, dc->res_pool, clk_src);
1337
1338 dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
1339 }
1340 }
1341 }
1342 }
1343
1344 /*******************************************************************************
1345 * Public functions
1346 ******************************************************************************/
1347
1348 static void reset_single_pipe_hw_ctx(
1349 const struct core_dc *dc,
1350 struct pipe_ctx *pipe_ctx,
1351 struct validate_context *context)
1352 {
1353 core_link_disable_stream(pipe_ctx);
1354 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
1355 if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) {
1356 dm_error("DC: failed to blank crtc!\n");
1357 BREAK_TO_DEBUGGER();
1358 }
1359 pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
1360 pipe_ctx->mi->funcs->free_mem_input(
1361 pipe_ctx->mi, context->stream_count);
1362 resource_unreference_clock_source(&context->res_ctx, dc->res_pool,
1363 &pipe_ctx->clock_source);
1364
1365 dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx->pipe_idx);
1366
1367 pipe_ctx->stream = NULL;
1368 }
1369
1370 static void set_drr(struct pipe_ctx **pipe_ctx,
1371 int num_pipes, int vmin, int vmax)
1372 {
1373 int i = 0;
1374 struct drr_params params = {0};
1375
1376 params.vertical_total_max = vmax;
1377 params.vertical_total_min = vmin;
1378
1379 /* TODO: If multiple pipes are to be supported, you need
1380 * some GSL stuff
1381 */
1382
1383 for (i = 0; i < num_pipes; i++) {
1384 pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
1385 }
1386 }
1387
1388 static void get_position(struct pipe_ctx **pipe_ctx,
1389 int num_pipes,
1390 struct crtc_position *position)
1391 {
1392 int i = 0;
1393
1394 /* TODO: handle pipes > 1
1395 */
1396 for (i = 0; i < num_pipes; i++)
1397 pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
1398 }
1399
1400 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1401 int num_pipes, const struct dc_static_screen_events *events)
1402 {
1403 unsigned int i;
1404 unsigned int value = 0;
1405
1406 if (events->overlay_update)
1407 value |= 0x100;
1408 if (events->surface_update)
1409 value |= 0x80;
1410 if (events->cursor_update)
1411 value |= 0x2;
1412
1413 #ifdef ENABLE_FBC
1414 value |= 0x84;
1415 #endif
1416
1417 for (i = 0; i < num_pipes; i++)
1418 pipe_ctx[i]->tg->funcs->
1419 set_static_screen_control(pipe_ctx[i]->tg, value);
1420 }
1421
1422 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1423 * may not be programmed yet.
1424 * TODO: after mode set, pre_mode_set = false,
1425 * may read PLL register to get pixel clock
1426 */
1427 static uint32_t get_max_pixel_clock_for_all_paths(
1428 struct core_dc *dc,
1429 struct validate_context *context,
1430 bool pre_mode_set)
1431 {
1432 uint32_t max_pix_clk = 0;
1433 int i;
1434
1435 if (!pre_mode_set) {
1436 /* TODO: read ASIC register to get pixel clock */
1437 ASSERT(0);
1438 }
1439
1440 for (i = 0; i < MAX_PIPES; i++) {
1441 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1442
1443 if (pipe_ctx->stream == NULL)
1444 continue;
1445
1446 /* do not check under lay */
1447 if (pipe_ctx->top_pipe)
1448 continue;
1449
1450 if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk)
1451 max_pix_clk =
1452 pipe_ctx->pix_clk_params.requested_pix_clk;
1453 }
1454
1455 if (max_pix_clk == 0)
1456 ASSERT(0);
1457
1458 return max_pix_clk;
1459 }
1460
1461 /* Find clock state based on clock requested. if clock value is 0, simply
1462 * set clock state as requested without finding clock state by clock value
1463 *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock.
1464 *
1465 * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value
1466 * etc support for dcn1.0
1467 */
1468 static void apply_min_clocks(
1469 struct core_dc *dc,
1470 struct validate_context *context,
1471 enum dm_pp_clocks_state *clocks_state,
1472 bool pre_mode_set)
1473 {
1474 struct state_dependent_clocks req_clocks = {0};
1475 struct pipe_ctx *pipe_ctx;
1476 int i;
1477
1478 for (i = 0; i < MAX_PIPES; i++) {
1479 pipe_ctx = &context->res_ctx.pipe_ctx[i];
1480 if (pipe_ctx->dis_clk != NULL)
1481 break;
1482 }
1483
1484 if (!pre_mode_set) {
1485 /* set clock_state without verification */
1486 if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
1487 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1488 pipe_ctx->dis_clk, *clocks_state);
1489 return;
1490 }
1491
1492 /* TODO: This is incorrect. Figure out how to fix. */
1493 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1494 pipe_ctx->dis_clk,
1495 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1496 pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz,
1497 pre_mode_set,
1498 false);
1499
1500 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1501 pipe_ctx->dis_clk,
1502 DM_PP_CLOCK_TYPE_PIXELCLK,
1503 pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1504 pre_mode_set,
1505 false);
1506
1507 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1508 pipe_ctx->dis_clk,
1509 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1510 pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1511 pre_mode_set,
1512 false);
1513 return;
1514 }
1515
1516 /* get the required state based on state dependent clocks:
1517 * display clock and pixel clock
1518 */
1519 req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1520
1521 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1522 dc, context, true);
1523
1524 if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) {
1525 *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state(
1526 pipe_ctx->dis_clk, &req_clocks);
1527 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1528 pipe_ctx->dis_clk, *clocks_state);
1529 } else {
1530 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1531 pipe_ctx->dis_clk,
1532 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1533 req_clocks.display_clk_khz,
1534 pre_mode_set,
1535 false);
1536
1537 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1538 pipe_ctx->dis_clk,
1539 DM_PP_CLOCK_TYPE_PIXELCLK,
1540 req_clocks.pixel_clk_khz,
1541 pre_mode_set,
1542 false);
1543
1544 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1545 pipe_ctx->dis_clk,
1546 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1547 req_clocks.pixel_clk_khz,
1548 pre_mode_set,
1549 false);
1550 }
1551 }
1552
1553 static enum dc_status apply_ctx_to_hw_fpga(
1554 struct core_dc *dc,
1555 struct validate_context *context)
1556 {
1557 enum dc_status status = DC_ERROR_UNEXPECTED;
1558 int i;
1559
1560 for (i = 0; i < MAX_PIPES; i++) {
1561 struct pipe_ctx *pipe_ctx_old =
1562 &dc->current_context->res_ctx.pipe_ctx[i];
1563 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1564
1565 if (pipe_ctx->stream == NULL)
1566 continue;
1567
1568 if (pipe_ctx->stream == pipe_ctx_old->stream)
1569 continue;
1570
1571 status = apply_single_controller_ctx_to_hw(
1572 pipe_ctx,
1573 context,
1574 dc);
1575
1576 if (status != DC_OK)
1577 return status;
1578 }
1579
1580 return DC_OK;
1581 }
1582
1583 static void reset_hw_ctx_wrap(
1584 struct core_dc *dc,
1585 struct validate_context *context)
1586 {
1587 int i;
1588
1589 /* Reset old context */
1590 /* look up the targets that have been removed since last commit */
1591 for (i = 0; i < MAX_PIPES; i++) {
1592 struct pipe_ctx *pipe_ctx_old =
1593 &dc->current_context->res_ctx.pipe_ctx[i];
1594 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1595
1596 /* Note: We need to disable output if clock sources change,
1597 * since bios does optimization and doesn't apply if changing
1598 * PHY when not already disabled.
1599 */
1600
1601 /* Skip underlay pipe since it will be handled in commit surface*/
1602 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1603 continue;
1604
1605 if (!pipe_ctx->stream ||
1606 pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1607 reset_single_pipe_hw_ctx(
1608 dc, pipe_ctx_old, dc->current_context);
1609 }
1610 }
1611
1612
1613 enum dc_status dce110_apply_ctx_to_hw(
1614 struct core_dc *dc,
1615 struct validate_context *context)
1616 {
1617 struct dc_bios *dcb = dc->ctx->dc_bios;
1618 enum dc_status status;
1619 int i;
1620 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1621
1622 /* Reset old context */
1623 /* look up the targets that have been removed since last commit */
1624 dc->hwss.reset_hw_ctx_wrap(dc, context);
1625
1626 /* Skip applying if no targets */
1627 if (context->stream_count <= 0)
1628 return DC_OK;
1629
1630 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1631 apply_ctx_to_hw_fpga(dc, context);
1632 return DC_OK;
1633 }
1634
1635 /* Apply new context */
1636 dcb->funcs->set_scratch_critical_state(dcb, true);
1637
1638 /* below is for real asic only */
1639 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1640 struct pipe_ctx *pipe_ctx_old =
1641 &dc->current_context->res_ctx.pipe_ctx[i];
1642 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1643
1644 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1645 continue;
1646
1647 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1648 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1649 dce_crtc_switch_to_clk_src(dc->hwseq,
1650 pipe_ctx->clock_source, i);
1651 continue;
1652 }
1653
1654 dc->hwss.enable_display_power_gating(
1655 dc, i, dc->ctx->dc_bios,
1656 PIPE_GATING_CONTROL_DISABLE);
1657 }
1658
1659 set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1660
1661 #ifdef ENABLE_FBC
1662 if (dc->fbc_compressor)
1663 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1664 #endif
1665 /*TODO: when pplib works*/
1666 apply_min_clocks(dc, context, &clocks_state, true);
1667
1668 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1669 if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1670 if (context->bw.dcn.calc_clk.fclk_khz
1671 > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
1672 struct dm_pp_clock_for_voltage_req clock;
1673
1674 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1675 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1676 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1677 dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1678 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1679 }
1680 if (context->bw.dcn.calc_clk.dcfclk_khz
1681 > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
1682 struct dm_pp_clock_for_voltage_req clock;
1683
1684 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1685 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1686 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1687 dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1688 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1689 }
1690 if (context->bw.dcn.calc_clk.dispclk_khz
1691 > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
1692 dc->res_pool->display_clock->funcs->set_clock(
1693 dc->res_pool->display_clock,
1694 context->bw.dcn.calc_clk.dispclk_khz);
1695 dc->current_context->bw.dcn.cur_clk.dispclk_khz =
1696 context->bw.dcn.calc_clk.dispclk_khz;
1697 context->bw.dcn.cur_clk.dispclk_khz =
1698 context->bw.dcn.calc_clk.dispclk_khz;
1699 }
1700 } else
1701 #endif
1702 if (context->bw.dce.dispclk_khz
1703 > dc->current_context->bw.dce.dispclk_khz) {
1704 dc->res_pool->display_clock->funcs->set_clock(
1705 dc->res_pool->display_clock,
1706 context->bw.dce.dispclk_khz * 115 / 100);
1707 }
1708 /* program audio wall clock. use HDMI as clock source if HDMI
1709 * audio active. Otherwise, use DP as clock source
1710 * first, loop to find any HDMI audio, if not, loop find DP audio
1711 */
1712 /* Setup audio rate clock source */
1713 /* Issue:
1714 * Audio lag happened on DP monitor when unplug a HDMI monitor
1715 *
1716 * Cause:
1717 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1718 * is set to either dto0 or dto1, audio should work fine.
1719 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1720 * set to dto0 will cause audio lag.
1721 *
1722 * Solution:
1723 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1724 * find first available pipe with audio, setup audio wall DTO per topology
1725 * instead of per pipe.
1726 */
1727 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1728 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1729
1730 if (pipe_ctx->stream == NULL)
1731 continue;
1732
1733 if (pipe_ctx->top_pipe)
1734 continue;
1735
1736 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1737 continue;
1738
1739 if (pipe_ctx->audio != NULL) {
1740 struct audio_output audio_output;
1741
1742 build_audio_output(pipe_ctx, &audio_output);
1743
1744 pipe_ctx->audio->funcs->wall_dto_setup(
1745 pipe_ctx->audio,
1746 pipe_ctx->stream->signal,
1747 &audio_output.crtc_info,
1748 &audio_output.pll_info);
1749 break;
1750 }
1751 }
1752
1753 /* no HDMI audio is found, try DP audio */
1754 if (i == dc->res_pool->pipe_count) {
1755 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1756 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1757
1758 if (pipe_ctx->stream == NULL)
1759 continue;
1760
1761 if (pipe_ctx->top_pipe)
1762 continue;
1763
1764 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1765 continue;
1766
1767 if (pipe_ctx->audio != NULL) {
1768 struct audio_output audio_output;
1769
1770 build_audio_output(pipe_ctx, &audio_output);
1771
1772 pipe_ctx->audio->funcs->wall_dto_setup(
1773 pipe_ctx->audio,
1774 pipe_ctx->stream->signal,
1775 &audio_output.crtc_info,
1776 &audio_output.pll_info);
1777 break;
1778 }
1779 }
1780 }
1781
1782 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1783 struct pipe_ctx *pipe_ctx_old =
1784 &dc->current_context->res_ctx.pipe_ctx[i];
1785 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1786
1787 if (pipe_ctx->stream == NULL)
1788 continue;
1789
1790 if (pipe_ctx->stream == pipe_ctx_old->stream)
1791 continue;
1792
1793 if (pipe_ctx->stream && pipe_ctx_old->stream
1794 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1795 continue;
1796
1797 if (pipe_ctx->top_pipe)
1798 continue;
1799
1800 if (context->res_ctx.pipe_ctx[i].audio != NULL) {
1801
1802 struct audio_output audio_output;
1803
1804 build_audio_output(pipe_ctx, &audio_output);
1805
1806 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1807 pipe_ctx->stream_enc->funcs->dp_audio_setup(
1808 pipe_ctx->stream_enc,
1809 pipe_ctx->audio->inst,
1810 &pipe_ctx->stream->audio_info);
1811 else
1812 pipe_ctx->stream_enc->funcs->hdmi_audio_setup(
1813 pipe_ctx->stream_enc,
1814 pipe_ctx->audio->inst,
1815 &pipe_ctx->stream->audio_info,
1816 &audio_output.crtc_info);
1817
1818 pipe_ctx->audio->funcs->az_configure(
1819 pipe_ctx->audio,
1820 pipe_ctx->stream->signal,
1821 &audio_output.crtc_info,
1822 &pipe_ctx->stream->audio_info);
1823 }
1824
1825 status = apply_single_controller_ctx_to_hw(
1826 pipe_ctx,
1827 context,
1828 dc);
1829
1830 if (dc->hwss.power_on_front_end)
1831 dc->hwss.power_on_front_end(dc, pipe_ctx, context);
1832
1833 if (DC_OK != status)
1834 return status;
1835 }
1836
1837 dc->hwss.set_bandwidth(dc, context, true);
1838
1839 /* to save power */
1840 apply_min_clocks(dc, context, &clocks_state, false);
1841
1842 dcb->funcs->set_scratch_critical_state(dcb, false);
1843
1844 switch_dp_clock_sources(dc, &context->res_ctx);
1845
1846
1847 return DC_OK;
1848 }
1849
1850 /*******************************************************************************
1851 * Front End programming
1852 ******************************************************************************/
1853 static void set_default_colors(struct pipe_ctx *pipe_ctx)
1854 {
1855 struct default_adjustment default_adjust = { 0 };
1856
1857 default_adjust.force_hw_default = false;
1858 if (pipe_ctx->surface == NULL)
1859 default_adjust.in_color_space = COLOR_SPACE_SRGB;
1860 else
1861 default_adjust.in_color_space =
1862 pipe_ctx->surface->color_space;
1863 if (pipe_ctx->stream == NULL)
1864 default_adjust.out_color_space = COLOR_SPACE_SRGB;
1865 else
1866 default_adjust.out_color_space =
1867 pipe_ctx->stream->output_color_space;
1868 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
1869 default_adjust.surface_pixel_format = pipe_ctx->scl_data.format;
1870
1871 /* display color depth */
1872 default_adjust.color_depth =
1873 pipe_ctx->stream->timing.display_color_depth;
1874
1875 /* Lb color depth */
1876 default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth;
1877
1878 pipe_ctx->opp->funcs->opp_set_csc_default(
1879 pipe_ctx->opp, &default_adjust);
1880 }
1881
1882
1883 /*******************************************************************************
1884 * In order to turn on/off specific surface we will program
1885 * Blender + CRTC
1886 *
1887 * In case that we have two surfaces and they have a different visibility
1888 * we can't turn off the CRTC since it will turn off the entire display
1889 *
1890 * |----------------------------------------------- |
1891 * |bottom pipe|curr pipe | | |
1892 * |Surface |Surface | Blender | CRCT |
1893 * |visibility |visibility | Configuration| |
1894 * |------------------------------------------------|
1895 * | off | off | CURRENT_PIPE | blank |
1896 * | off | on | CURRENT_PIPE | unblank |
1897 * | on | off | OTHER_PIPE | unblank |
1898 * | on | on | BLENDING | unblank |
1899 * -------------------------------------------------|
1900 *
1901 ******************************************************************************/
1902 static void program_surface_visibility(const struct core_dc *dc,
1903 struct pipe_ctx *pipe_ctx)
1904 {
1905 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
1906 bool blank_target = false;
1907
1908 if (pipe_ctx->bottom_pipe) {
1909
1910 /* For now we are supporting only two pipes */
1911 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
1912
1913 if (pipe_ctx->bottom_pipe->surface->visible) {
1914 if (pipe_ctx->surface->visible)
1915 blender_mode = BLND_MODE_BLENDING;
1916 else
1917 blender_mode = BLND_MODE_OTHER_PIPE;
1918
1919 } else if (!pipe_ctx->surface->visible)
1920 blank_target = true;
1921
1922 } else if (!pipe_ctx->surface->visible)
1923 blank_target = true;
1924
1925 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
1926 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target);
1927
1928 }
1929
1930 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1931 {
1932 struct xfm_grph_csc_adjustment adjust;
1933 memset(&adjust, 0, sizeof(adjust));
1934 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1935
1936
1937 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1938 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1939 adjust.temperature_matrix[0] =
1940 pipe_ctx->stream->
1941 gamut_remap_matrix.matrix[0];
1942 adjust.temperature_matrix[1] =
1943 pipe_ctx->stream->
1944 gamut_remap_matrix.matrix[1];
1945 adjust.temperature_matrix[2] =
1946 pipe_ctx->stream->
1947 gamut_remap_matrix.matrix[2];
1948 adjust.temperature_matrix[3] =
1949 pipe_ctx->stream->
1950 gamut_remap_matrix.matrix[4];
1951 adjust.temperature_matrix[4] =
1952 pipe_ctx->stream->
1953 gamut_remap_matrix.matrix[5];
1954 adjust.temperature_matrix[5] =
1955 pipe_ctx->stream->
1956 gamut_remap_matrix.matrix[6];
1957 adjust.temperature_matrix[6] =
1958 pipe_ctx->stream->
1959 gamut_remap_matrix.matrix[8];
1960 adjust.temperature_matrix[7] =
1961 pipe_ctx->stream->
1962 gamut_remap_matrix.matrix[9];
1963 adjust.temperature_matrix[8] =
1964 pipe_ctx->stream->
1965 gamut_remap_matrix.matrix[10];
1966 }
1967
1968 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
1969 }
1970
1971 /**
1972 * TODO REMOVE, USE UPDATE INSTEAD
1973 */
1974 static void set_plane_config(
1975 const struct core_dc *dc,
1976 struct pipe_ctx *pipe_ctx,
1977 struct resource_context *res_ctx)
1978 {
1979 struct mem_input *mi = pipe_ctx->mi;
1980 struct dc_surface *surface = pipe_ctx->surface;
1981 struct xfm_grph_csc_adjustment adjust;
1982 struct out_csc_color_matrix tbl_entry;
1983 unsigned int i;
1984
1985 memset(&adjust, 0, sizeof(adjust));
1986 memset(&tbl_entry, 0, sizeof(tbl_entry));
1987 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1988
1989 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
1990
1991 set_default_colors(pipe_ctx);
1992 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
1993 == true) {
1994 tbl_entry.color_space =
1995 pipe_ctx->stream->output_color_space;
1996
1997 for (i = 0; i < 12; i++)
1998 tbl_entry.regval[i] =
1999 pipe_ctx->stream->csc_color_matrix.matrix[i];
2000
2001 pipe_ctx->opp->funcs->opp_set_csc_adjustment
2002 (pipe_ctx->opp, &tbl_entry);
2003 }
2004
2005 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2006 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2007 adjust.temperature_matrix[0] =
2008 pipe_ctx->stream->
2009 gamut_remap_matrix.matrix[0];
2010 adjust.temperature_matrix[1] =
2011 pipe_ctx->stream->
2012 gamut_remap_matrix.matrix[1];
2013 adjust.temperature_matrix[2] =
2014 pipe_ctx->stream->
2015 gamut_remap_matrix.matrix[2];
2016 adjust.temperature_matrix[3] =
2017 pipe_ctx->stream->
2018 gamut_remap_matrix.matrix[4];
2019 adjust.temperature_matrix[4] =
2020 pipe_ctx->stream->
2021 gamut_remap_matrix.matrix[5];
2022 adjust.temperature_matrix[5] =
2023 pipe_ctx->stream->
2024 gamut_remap_matrix.matrix[6];
2025 adjust.temperature_matrix[6] =
2026 pipe_ctx->stream->
2027 gamut_remap_matrix.matrix[8];
2028 adjust.temperature_matrix[7] =
2029 pipe_ctx->stream->
2030 gamut_remap_matrix.matrix[9];
2031 adjust.temperature_matrix[8] =
2032 pipe_ctx->stream->
2033 gamut_remap_matrix.matrix[10];
2034 }
2035
2036 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
2037
2038 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2039 program_scaler(dc, pipe_ctx);
2040
2041 program_surface_visibility(dc, pipe_ctx);
2042
2043 mi->funcs->mem_input_program_surface_config(
2044 mi,
2045 surface->format,
2046 &surface->tiling_info,
2047 &surface->plane_size,
2048 surface->rotation,
2049 NULL,
2050 false);
2051 if (mi->funcs->set_blank)
2052 mi->funcs->set_blank(mi, pipe_ctx->surface->visible);
2053
2054 if (dc->public.config.gpu_vm_support)
2055 mi->funcs->mem_input_program_pte_vm(
2056 pipe_ctx->mi,
2057 surface->format,
2058 &surface->tiling_info,
2059 surface->rotation);
2060 }
2061
2062 static void update_plane_addr(const struct core_dc *dc,
2063 struct pipe_ctx *pipe_ctx)
2064 {
2065 struct dc_surface *surface = pipe_ctx->surface;
2066
2067 if (surface == NULL)
2068 return;
2069
2070 pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
2071 pipe_ctx->mi,
2072 &surface->address,
2073 surface->flip_immediate);
2074
2075 surface->status.requested_address = surface->address;
2076 }
2077
2078 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2079 {
2080 struct dc_surface *surface = pipe_ctx->surface;
2081
2082 if (surface == NULL)
2083 return;
2084
2085 surface->status.is_flip_pending =
2086 pipe_ctx->mi->funcs->mem_input_is_flip_pending(
2087 pipe_ctx->mi);
2088
2089 if (surface->status.is_flip_pending && !surface->visible)
2090 pipe_ctx->mi->current_address = pipe_ctx->mi->request_address;
2091
2092 surface->status.current_address = pipe_ctx->mi->current_address;
2093 if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2094 pipe_ctx->tg->funcs->is_stereo_left_eye) {
2095 surface->status.is_right_eye =\
2096 !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
2097 }
2098 }
2099
2100 void dce110_power_down(struct core_dc *dc)
2101 {
2102 power_down_all_hw_blocks(dc);
2103 disable_vga_and_power_gate_all_controllers(dc);
2104 }
2105
2106 static bool wait_for_reset_trigger_to_occur(
2107 struct dc_context *dc_ctx,
2108 struct timing_generator *tg)
2109 {
2110 bool rc = false;
2111
2112 /* To avoid endless loop we wait at most
2113 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2114 const uint32_t frames_to_wait_on_triggered_reset = 10;
2115 uint32_t i;
2116
2117 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2118
2119 if (!tg->funcs->is_counter_moving(tg)) {
2120 DC_ERROR("TG counter is not moving!\n");
2121 break;
2122 }
2123
2124 if (tg->funcs->did_triggered_reset_occur(tg)) {
2125 rc = true;
2126 /* usually occurs at i=1 */
2127 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2128 i);
2129 break;
2130 }
2131
2132 /* Wait for one frame. */
2133 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2134 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2135 }
2136
2137 if (false == rc)
2138 DC_ERROR("GSL: Timeout on reset trigger!\n");
2139
2140 return rc;
2141 }
2142
2143 /* Enable timing synchronization for a group of Timing Generators. */
2144 static void dce110_enable_timing_synchronization(
2145 struct core_dc *dc,
2146 int group_index,
2147 int group_size,
2148 struct pipe_ctx *grouped_pipes[])
2149 {
2150 struct dc_context *dc_ctx = dc->ctx;
2151 struct dcp_gsl_params gsl_params = { 0 };
2152 int i;
2153
2154 DC_SYNC_INFO("GSL: Setting-up...\n");
2155
2156 /* Designate a single TG in the group as a master.
2157 * Since HW doesn't care which one, we always assign
2158 * the 1st one in the group. */
2159 gsl_params.gsl_group = 0;
2160 gsl_params.gsl_master = grouped_pipes[0]->tg->inst;
2161
2162 for (i = 0; i < group_size; i++)
2163 grouped_pipes[i]->tg->funcs->setup_global_swap_lock(
2164 grouped_pipes[i]->tg, &gsl_params);
2165
2166 /* Reset slave controllers on master VSync */
2167 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2168
2169 for (i = 1 /* skip the master */; i < group_size; i++)
2170 grouped_pipes[i]->tg->funcs->enable_reset_trigger(
2171 grouped_pipes[i]->tg, gsl_params.gsl_group);
2172
2173
2174
2175 for (i = 1 /* skip the master */; i < group_size; i++) {
2176 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2177 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg);
2178 /* Regardless of success of the wait above, remove the reset or
2179 * the driver will start timing out on Display requests. */
2180 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2181 grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg);
2182 }
2183
2184
2185 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2186 * is that the sync'ed displays will not drift out of sync over time*/
2187 DC_SYNC_INFO("GSL: Restoring register states.\n");
2188 for (i = 0; i < group_size; i++)
2189 grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg);
2190
2191 DC_SYNC_INFO("GSL: Set-up complete.\n");
2192 }
2193
2194 static void init_hw(struct core_dc *dc)
2195 {
2196 int i;
2197 struct dc_bios *bp;
2198 struct transform *xfm;
2199 struct abm *abm;
2200
2201 bp = dc->ctx->dc_bios;
2202 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2203 xfm = dc->res_pool->transforms[i];
2204 xfm->funcs->transform_reset(xfm);
2205
2206 dc->hwss.enable_display_power_gating(
2207 dc, i, bp,
2208 PIPE_GATING_CONTROL_INIT);
2209 dc->hwss.enable_display_power_gating(
2210 dc, i, bp,
2211 PIPE_GATING_CONTROL_DISABLE);
2212 dc->hwss.enable_display_pipe_clock_gating(
2213 dc->ctx,
2214 true);
2215 }
2216
2217 dce_clock_gating_power_up(dc->hwseq, false);
2218 /***************************************/
2219
2220 for (i = 0; i < dc->link_count; i++) {
2221 /****************************************/
2222 /* Power up AND update implementation according to the
2223 * required signal (which may be different from the
2224 * default signal on connector). */
2225 struct dc_link *link = dc->links[i];
2226 link->link_enc->funcs->hw_init(link->link_enc);
2227 }
2228
2229 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2230 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2231
2232 tg->funcs->disable_vga(tg);
2233
2234 /* Blank controller using driver code instead of
2235 * command table. */
2236 tg->funcs->set_blank(tg, true);
2237 hwss_wait_for_blank_complete(tg);
2238 }
2239
2240 for (i = 0; i < dc->res_pool->audio_count; i++) {
2241 struct audio *audio = dc->res_pool->audios[i];
2242 audio->funcs->hw_init(audio);
2243 }
2244
2245 abm = dc->res_pool->abm;
2246 if (abm != NULL) {
2247 abm->funcs->init_backlight(abm);
2248 abm->funcs->abm_init(abm);
2249 }
2250 #ifdef ENABLE_FBC
2251 if (dc->fbc_compressor)
2252 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2253 #endif
2254 }
2255
2256 void dce110_fill_display_configs(
2257 const struct validate_context *context,
2258 struct dm_pp_display_configuration *pp_display_cfg)
2259 {
2260 int j;
2261 int num_cfgs = 0;
2262
2263 for (j = 0; j < context->stream_count; j++) {
2264 int k;
2265
2266 const struct dc_stream *stream = context->streams[j];
2267 struct dm_pp_single_disp_config *cfg =
2268 &pp_display_cfg->disp_configs[num_cfgs];
2269 const struct pipe_ctx *pipe_ctx = NULL;
2270
2271 for (k = 0; k < MAX_PIPES; k++)
2272 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2273 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2274 break;
2275 }
2276
2277 ASSERT(pipe_ctx != NULL);
2278
2279 num_cfgs++;
2280 cfg->signal = pipe_ctx->stream->signal;
2281 cfg->pipe_idx = pipe_ctx->pipe_idx;
2282 cfg->src_height = stream->src.height;
2283 cfg->src_width = stream->src.width;
2284 cfg->ddi_channel_mapping =
2285 stream->sink->link->ddi_channel_mapping.raw;
2286 cfg->transmitter =
2287 stream->sink->link->link_enc->transmitter;
2288 cfg->link_settings.lane_count =
2289 stream->sink->link->cur_link_settings.lane_count;
2290 cfg->link_settings.link_rate =
2291 stream->sink->link->cur_link_settings.link_rate;
2292 cfg->link_settings.link_spread =
2293 stream->sink->link->cur_link_settings.link_spread;
2294 cfg->sym_clock = stream->phy_pix_clk;
2295 /* Round v_refresh*/
2296 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2297 cfg->v_refresh /= stream->timing.h_total;
2298 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2299 / stream->timing.v_total;
2300 }
2301
2302 pp_display_cfg->display_count = num_cfgs;
2303 }
2304
2305 uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
2306 {
2307 uint8_t j;
2308 uint32_t min_vertical_blank_time = -1;
2309
2310 for (j = 0; j < context->stream_count; j++) {
2311 struct dc_stream *stream = context->streams[j];
2312 uint32_t vertical_blank_in_pixels = 0;
2313 uint32_t vertical_blank_time = 0;
2314
2315 vertical_blank_in_pixels = stream->timing.h_total *
2316 (stream->timing.v_total
2317 - stream->timing.v_addressable);
2318
2319 vertical_blank_time = vertical_blank_in_pixels
2320 * 1000 / stream->timing.pix_clk_khz;
2321
2322 if (min_vertical_blank_time > vertical_blank_time)
2323 min_vertical_blank_time = vertical_blank_time;
2324 }
2325
2326 return min_vertical_blank_time;
2327 }
2328
2329 static int determine_sclk_from_bounding_box(
2330 const struct core_dc *dc,
2331 int required_sclk)
2332 {
2333 int i;
2334
2335 /*
2336 * Some asics do not give us sclk levels, so we just report the actual
2337 * required sclk
2338 */
2339 if (dc->sclk_lvls.num_levels == 0)
2340 return required_sclk;
2341
2342 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2343 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2344 return dc->sclk_lvls.clocks_in_khz[i];
2345 }
2346 /*
2347 * even maximum level could not satisfy requirement, this
2348 * is unexpected at this stage, should have been caught at
2349 * validation time
2350 */
2351 ASSERT(0);
2352 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2353 }
2354
2355 static void pplib_apply_display_requirements(
2356 struct core_dc *dc,
2357 struct validate_context *context)
2358 {
2359 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2360
2361 pp_display_cfg->all_displays_in_sync =
2362 context->bw.dce.all_displays_in_sync;
2363 pp_display_cfg->nb_pstate_switch_disable =
2364 context->bw.dce.nbp_state_change_enable == false;
2365 pp_display_cfg->cpu_cc6_disable =
2366 context->bw.dce.cpuc_state_change_enable == false;
2367 pp_display_cfg->cpu_pstate_disable =
2368 context->bw.dce.cpup_state_change_enable == false;
2369 pp_display_cfg->cpu_pstate_separation_time =
2370 context->bw.dce.blackout_recovery_time_us;
2371
2372 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2373 / MEMORY_TYPE_MULTIPLIER;
2374
2375 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2376 dc,
2377 context->bw.dce.sclk_khz);
2378
2379 pp_display_cfg->min_engine_clock_deep_sleep_khz
2380 = context->bw.dce.sclk_deep_sleep_khz;
2381
2382 pp_display_cfg->avail_mclk_switch_time_us =
2383 dce110_get_min_vblank_time_us(context);
2384 /* TODO: dce11.2*/
2385 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2386
2387 pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2388
2389 dce110_fill_display_configs(context, pp_display_cfg);
2390
2391 /* TODO: is this still applicable?*/
2392 if (pp_display_cfg->display_count == 1) {
2393 const struct dc_crtc_timing *timing =
2394 &context->streams[0]->timing;
2395
2396 pp_display_cfg->crtc_index =
2397 pp_display_cfg->disp_configs[0].pipe_idx;
2398 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2399 / timing->pix_clk_khz;
2400 }
2401
2402 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2403 struct dm_pp_display_configuration)) != 0)
2404 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2405
2406 dc->prev_display_config = *pp_display_cfg;
2407 }
2408
2409 static void dce110_set_bandwidth(
2410 struct core_dc *dc,
2411 struct validate_context *context,
2412 bool decrease_allowed)
2413 {
2414 dce110_set_displaymarks(dc, context);
2415
2416 if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) {
2417 dc->res_pool->display_clock->funcs->set_clock(
2418 dc->res_pool->display_clock,
2419 context->bw.dce.dispclk_khz * 115 / 100);
2420 dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2421 }
2422
2423 pplib_apply_display_requirements(dc, context);
2424 }
2425
2426 static void dce110_program_front_end_for_pipe(
2427 struct core_dc *dc, struct pipe_ctx *pipe_ctx)
2428 {
2429 struct mem_input *mi = pipe_ctx->mi;
2430 struct pipe_ctx *old_pipe = NULL;
2431 struct dc_surface *surface = pipe_ctx->surface;
2432 struct xfm_grph_csc_adjustment adjust;
2433 struct out_csc_color_matrix tbl_entry;
2434 unsigned int i;
2435
2436 memset(&tbl_entry, 0, sizeof(tbl_entry));
2437
2438 if (dc->current_context)
2439 old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2440
2441 memset(&adjust, 0, sizeof(adjust));
2442 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2443
2444 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2445
2446 set_default_colors(pipe_ctx);
2447 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2448 == true) {
2449 tbl_entry.color_space =
2450 pipe_ctx->stream->output_color_space;
2451
2452 for (i = 0; i < 12; i++)
2453 tbl_entry.regval[i] =
2454 pipe_ctx->stream->csc_color_matrix.matrix[i];
2455
2456 pipe_ctx->opp->funcs->opp_set_csc_adjustment
2457 (pipe_ctx->opp, &tbl_entry);
2458 }
2459
2460 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2461 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2462 adjust.temperature_matrix[0] =
2463 pipe_ctx->stream->
2464 gamut_remap_matrix.matrix[0];
2465 adjust.temperature_matrix[1] =
2466 pipe_ctx->stream->
2467 gamut_remap_matrix.matrix[1];
2468 adjust.temperature_matrix[2] =
2469 pipe_ctx->stream->
2470 gamut_remap_matrix.matrix[2];
2471 adjust.temperature_matrix[3] =
2472 pipe_ctx->stream->
2473 gamut_remap_matrix.matrix[4];
2474 adjust.temperature_matrix[4] =
2475 pipe_ctx->stream->
2476 gamut_remap_matrix.matrix[5];
2477 adjust.temperature_matrix[5] =
2478 pipe_ctx->stream->
2479 gamut_remap_matrix.matrix[6];
2480 adjust.temperature_matrix[6] =
2481 pipe_ctx->stream->
2482 gamut_remap_matrix.matrix[8];
2483 adjust.temperature_matrix[7] =
2484 pipe_ctx->stream->
2485 gamut_remap_matrix.matrix[9];
2486 adjust.temperature_matrix[8] =
2487 pipe_ctx->stream->
2488 gamut_remap_matrix.matrix[10];
2489 }
2490
2491 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
2492
2493 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2494
2495 program_scaler(dc, pipe_ctx);
2496
2497 mi->funcs->mem_input_program_surface_config(
2498 mi,
2499 surface->format,
2500 &surface->tiling_info,
2501 &surface->plane_size,
2502 surface->rotation,
2503 NULL,
2504 false);
2505 if (mi->funcs->set_blank)
2506 mi->funcs->set_blank(mi, pipe_ctx->surface->visible);
2507
2508 if (dc->public.config.gpu_vm_support)
2509 mi->funcs->mem_input_program_pte_vm(
2510 pipe_ctx->mi,
2511 surface->format,
2512 &surface->tiling_info,
2513 surface->rotation);
2514
2515 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2516 "Pipe:%d 0x%x: addr hi:0x%x, "
2517 "addr low:0x%x, "
2518 "src: %d, %d, %d,"
2519 " %d; dst: %d, %d, %d, %d;"
2520 "clip: %d, %d, %d, %d\n",
2521 pipe_ctx->pipe_idx,
2522 pipe_ctx->surface,
2523 pipe_ctx->surface->address.grph.addr.high_part,
2524 pipe_ctx->surface->address.grph.addr.low_part,
2525 pipe_ctx->surface->src_rect.x,
2526 pipe_ctx->surface->src_rect.y,
2527 pipe_ctx->surface->src_rect.width,
2528 pipe_ctx->surface->src_rect.height,
2529 pipe_ctx->surface->dst_rect.x,
2530 pipe_ctx->surface->dst_rect.y,
2531 pipe_ctx->surface->dst_rect.width,
2532 pipe_ctx->surface->dst_rect.height,
2533 pipe_ctx->surface->clip_rect.x,
2534 pipe_ctx->surface->clip_rect.y,
2535 pipe_ctx->surface->clip_rect.width,
2536 pipe_ctx->surface->clip_rect.height);
2537
2538 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2539 "Pipe %d: width, height, x, y\n"
2540 "viewport:%d, %d, %d, %d\n"
2541 "recout: %d, %d, %d, %d\n",
2542 pipe_ctx->pipe_idx,
2543 pipe_ctx->scl_data.viewport.width,
2544 pipe_ctx->scl_data.viewport.height,
2545 pipe_ctx->scl_data.viewport.x,
2546 pipe_ctx->scl_data.viewport.y,
2547 pipe_ctx->scl_data.recout.width,
2548 pipe_ctx->scl_data.recout.height,
2549 pipe_ctx->scl_data.recout.x,
2550 pipe_ctx->scl_data.recout.y);
2551 }
2552
2553 static void dce110_apply_ctx_for_surface(
2554 struct core_dc *dc,
2555 const struct dc_surface *surface,
2556 struct validate_context *context)
2557 {
2558 int i;
2559
2560 /* TODO remove when removing the surface reset workaroud*/
2561 if (!surface)
2562 return;
2563
2564 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2565 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2566
2567 if (pipe_ctx->surface != surface)
2568 continue;
2569
2570 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2571 program_surface_visibility(dc, pipe_ctx);
2572
2573 }
2574 }
2575
2576 static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
2577 {
2578 /* Do not power down fe when stream is active on dce*/
2579 if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream)
2580 return;
2581
2582 dc->hwss.enable_display_power_gating(
2583 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2584
2585 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2586 dc->res_pool->transforms[fe_idx]);
2587 }
2588
2589 static void dce110_wait_for_mpcc_disconnect(
2590 struct core_dc *dc,
2591 struct resource_pool *res_pool,
2592 struct pipe_ctx *pipe_ctx)
2593 {
2594 /* do nothing*/
2595 }
2596
2597 static const struct hw_sequencer_funcs dce110_funcs = {
2598 .program_gamut_remap = program_gamut_remap,
2599 .init_hw = init_hw,
2600 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2601 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2602 .set_plane_config = set_plane_config,
2603 .update_plane_addr = update_plane_addr,
2604 .update_pending_status = dce110_update_pending_status,
2605 .set_input_transfer_func = dce110_set_input_transfer_func,
2606 .set_output_transfer_func = dce110_set_output_transfer_func,
2607 .power_down = dce110_power_down,
2608 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2609 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2610 .update_info_frame = dce110_update_info_frame,
2611 .enable_stream = dce110_enable_stream,
2612 .disable_stream = dce110_disable_stream,
2613 .unblank_stream = dce110_unblank_stream,
2614 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2615 .enable_display_power_gating = dce110_enable_display_power_gating,
2616 .power_down_front_end = dce110_power_down_fe,
2617 .pipe_control_lock = dce_pipe_control_lock,
2618 .set_bandwidth = dce110_set_bandwidth,
2619 .set_drr = set_drr,
2620 .get_position = get_position,
2621 .set_static_screen_control = set_static_screen_control,
2622 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2623 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
2624 .setup_stereo = NULL,
2625 .set_avmute = dce110_set_avmute,
2626 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect
2627 };
2628
2629 bool dce110_hw_sequencer_construct(struct core_dc *dc)
2630 {
2631 dc->hwss = dce110_funcs;
2632
2633 return true;
2634 }
2635
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