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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "resource.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35
36 #ifdef ENABLE_FBC
37 #include "dce110_compressor.h"
38 #endif
39
40 #include "bios/bios_parser_helper.h"
41 #include "timing_generator.h"
42 #include "mem_input.h"
43 #include "opp.h"
44 #include "ipp.h"
45 #include "transform.h"
46 #include "stream_encoder.h"
47 #include "link_encoder.h"
48 #include "clock_source.h"
49 #include "abm.h"
50 #include "audio.h"
51 #include "dce/dce_hwseq.h"
52 #include "reg_helper.h"
53
54 /* include DCE11 register header files */
55 #include "dce/dce_11_0_d.h"
56 #include "dce/dce_11_0_sh_mask.h"
57 #include "custom_float.h"
58
59 struct dce110_hw_seq_reg_offsets {
60 uint32_t crtc;
61 };
62
63 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
64 {
65 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
66 },
67 {
68 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
69 },
70 {
71 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
72 },
73 {
74 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
75 }
76 };
77
78 #define HW_REG_BLND(reg, id)\
79 (reg + reg_offsets[id].blnd)
80
81 #define HW_REG_CRTC(reg, id)\
82 (reg + reg_offsets[id].crtc)
83
84 #define MAX_WATERMARK 0xFFFF
85 #define SAFE_NBP_MARK 0x7FFF
86
87 /*******************************************************************************
88 * Private definitions
89 ******************************************************************************/
90 /***************************PIPE_CONTROL***********************************/
91 static void dce110_init_pte(struct dc_context *ctx)
92 {
93 uint32_t addr;
94 uint32_t value = 0;
95 uint32_t chunk_int = 0;
96 uint32_t chunk_mul = 0;
97
98 addr = mmUNP_DVMM_PTE_CONTROL;
99 value = dm_read_reg(ctx, addr);
100
101 set_reg_field_value(
102 value,
103 0,
104 DVMM_PTE_CONTROL,
105 DVMM_USE_SINGLE_PTE);
106
107 set_reg_field_value(
108 value,
109 1,
110 DVMM_PTE_CONTROL,
111 DVMM_PTE_BUFFER_MODE0);
112
113 set_reg_field_value(
114 value,
115 1,
116 DVMM_PTE_CONTROL,
117 DVMM_PTE_BUFFER_MODE1);
118
119 dm_write_reg(ctx, addr, value);
120
121 addr = mmDVMM_PTE_REQ;
122 value = dm_read_reg(ctx, addr);
123
124 chunk_int = get_reg_field_value(
125 value,
126 DVMM_PTE_REQ,
127 HFLIP_PTEREQ_PER_CHUNK_INT);
128
129 chunk_mul = get_reg_field_value(
130 value,
131 DVMM_PTE_REQ,
132 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
133
134 if (chunk_int != 0x4 || chunk_mul != 0x4) {
135
136 set_reg_field_value(
137 value,
138 255,
139 DVMM_PTE_REQ,
140 MAX_PTEREQ_TO_ISSUE);
141
142 set_reg_field_value(
143 value,
144 4,
145 DVMM_PTE_REQ,
146 HFLIP_PTEREQ_PER_CHUNK_INT);
147
148 set_reg_field_value(
149 value,
150 4,
151 DVMM_PTE_REQ,
152 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
153
154 dm_write_reg(ctx, addr, value);
155 }
156 }
157 /**************************************************************************/
158
159 static void enable_display_pipe_clock_gating(
160 struct dc_context *ctx,
161 bool clock_gating)
162 {
163 /*TODO*/
164 }
165
166 static bool dce110_enable_display_power_gating(
167 struct core_dc *dc,
168 uint8_t controller_id,
169 struct dc_bios *dcb,
170 enum pipe_gating_control power_gating)
171 {
172 enum bp_result bp_result = BP_RESULT_OK;
173 enum bp_pipe_control_action cntl;
174 struct dc_context *ctx = dc->ctx;
175 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
176
177 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
178 return true;
179
180 if (power_gating == PIPE_GATING_CONTROL_INIT)
181 cntl = ASIC_PIPE_INIT;
182 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
183 cntl = ASIC_PIPE_ENABLE;
184 else
185 cntl = ASIC_PIPE_DISABLE;
186
187 if (controller_id == underlay_idx)
188 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
189
190 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
191
192 bp_result = dcb->funcs->enable_disp_power_gating(
193 dcb, controller_id + 1, cntl);
194
195 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
196 * by default when command table is called
197 *
198 * Bios parser accepts controller_id = 6 as indicative of
199 * underlay pipe in dce110. But we do not support more
200 * than 3.
201 */
202 if (controller_id < CONTROLLER_ID_MAX - 1)
203 dm_write_reg(ctx,
204 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
205 0);
206 }
207
208 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
209 dce110_init_pte(ctx);
210
211 if (bp_result == BP_RESULT_OK)
212 return true;
213 else
214 return false;
215 }
216
217 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
218 const struct dc_plane_state *plane_state)
219 {
220 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
221
222 switch (plane_state->format) {
223 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
224 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
225 prescale_params->scale = 0x2020;
226 break;
227 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
228 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
229 prescale_params->scale = 0x2008;
230 break;
231 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
232 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
233 prescale_params->scale = 0x2000;
234 break;
235 default:
236 ASSERT(false);
237 break;
238 }
239 }
240
241 static bool dce110_set_input_transfer_func(
242 struct pipe_ctx *pipe_ctx,
243 const struct dc_plane_state *plane_state)
244 {
245 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
246 const struct dc_transfer_func *tf = NULL;
247 struct ipp_prescale_params prescale_params = { 0 };
248 bool result = true;
249
250 if (ipp == NULL)
251 return false;
252
253 if (plane_state->in_transfer_func)
254 tf = plane_state->in_transfer_func;
255
256 build_prescale_params(&prescale_params, plane_state);
257 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
258
259 if (plane_state->gamma_correction && dce_use_lut(plane_state))
260 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
261
262 if (tf == NULL) {
263 /* Default case if no input transfer function specified */
264 ipp->funcs->ipp_set_degamma(ipp,
265 IPP_DEGAMMA_MODE_HW_sRGB);
266 } else if (tf->type == TF_TYPE_PREDEFINED) {
267 switch (tf->tf) {
268 case TRANSFER_FUNCTION_SRGB:
269 ipp->funcs->ipp_set_degamma(ipp,
270 IPP_DEGAMMA_MODE_HW_sRGB);
271 break;
272 case TRANSFER_FUNCTION_BT709:
273 ipp->funcs->ipp_set_degamma(ipp,
274 IPP_DEGAMMA_MODE_HW_xvYCC);
275 break;
276 case TRANSFER_FUNCTION_LINEAR:
277 ipp->funcs->ipp_set_degamma(ipp,
278 IPP_DEGAMMA_MODE_BYPASS);
279 break;
280 case TRANSFER_FUNCTION_PQ:
281 result = false;
282 break;
283 default:
284 result = false;
285 break;
286 }
287 } else if (tf->type == TF_TYPE_BYPASS) {
288 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
289 } else {
290 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
291 result = false;
292 }
293
294 return result;
295 }
296
297 static bool convert_to_custom_float(
298 struct pwl_result_data *rgb_resulted,
299 struct curve_points *arr_points,
300 uint32_t hw_points_num)
301 {
302 struct custom_float_format fmt;
303
304 struct pwl_result_data *rgb = rgb_resulted;
305
306 uint32_t i = 0;
307
308 fmt.exponenta_bits = 6;
309 fmt.mantissa_bits = 12;
310 fmt.sign = true;
311
312 if (!convert_to_custom_float_format(
313 arr_points[0].x,
314 &fmt,
315 &arr_points[0].custom_float_x)) {
316 BREAK_TO_DEBUGGER();
317 return false;
318 }
319
320 if (!convert_to_custom_float_format(
321 arr_points[0].offset,
322 &fmt,
323 &arr_points[0].custom_float_offset)) {
324 BREAK_TO_DEBUGGER();
325 return false;
326 }
327
328 if (!convert_to_custom_float_format(
329 arr_points[0].slope,
330 &fmt,
331 &arr_points[0].custom_float_slope)) {
332 BREAK_TO_DEBUGGER();
333 return false;
334 }
335
336 fmt.mantissa_bits = 10;
337 fmt.sign = false;
338
339 if (!convert_to_custom_float_format(
340 arr_points[1].x,
341 &fmt,
342 &arr_points[1].custom_float_x)) {
343 BREAK_TO_DEBUGGER();
344 return false;
345 }
346
347 if (!convert_to_custom_float_format(
348 arr_points[1].y,
349 &fmt,
350 &arr_points[1].custom_float_y)) {
351 BREAK_TO_DEBUGGER();
352 return false;
353 }
354
355 if (!convert_to_custom_float_format(
356 arr_points[2].slope,
357 &fmt,
358 &arr_points[2].custom_float_slope)) {
359 BREAK_TO_DEBUGGER();
360 return false;
361 }
362
363 fmt.mantissa_bits = 12;
364 fmt.sign = true;
365
366 while (i != hw_points_num) {
367 if (!convert_to_custom_float_format(
368 rgb->red,
369 &fmt,
370 &rgb->red_reg)) {
371 BREAK_TO_DEBUGGER();
372 return false;
373 }
374
375 if (!convert_to_custom_float_format(
376 rgb->green,
377 &fmt,
378 &rgb->green_reg)) {
379 BREAK_TO_DEBUGGER();
380 return false;
381 }
382
383 if (!convert_to_custom_float_format(
384 rgb->blue,
385 &fmt,
386 &rgb->blue_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(
392 rgb->delta_red,
393 &fmt,
394 &rgb->delta_red_reg)) {
395 BREAK_TO_DEBUGGER();
396 return false;
397 }
398
399 if (!convert_to_custom_float_format(
400 rgb->delta_green,
401 &fmt,
402 &rgb->delta_green_reg)) {
403 BREAK_TO_DEBUGGER();
404 return false;
405 }
406
407 if (!convert_to_custom_float_format(
408 rgb->delta_blue,
409 &fmt,
410 &rgb->delta_blue_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 ++rgb;
416 ++i;
417 }
418
419 return true;
420 }
421
422 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
423 *output_tf, struct pwl_params *regamma_params)
424 {
425 struct curve_points *arr_points;
426 struct pwl_result_data *rgb_resulted;
427 struct pwl_result_data *rgb;
428 struct pwl_result_data *rgb_plus_1;
429 struct fixed31_32 y_r;
430 struct fixed31_32 y_g;
431 struct fixed31_32 y_b;
432 struct fixed31_32 y1_min;
433 struct fixed31_32 y3_max;
434
435 int32_t segment_start, segment_end;
436 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
437
438 if (output_tf == NULL || regamma_params == NULL ||
439 output_tf->type == TF_TYPE_BYPASS)
440 return false;
441
442 arr_points = regamma_params->arr_points;
443 rgb_resulted = regamma_params->rgb_resulted;
444 hw_points = 0;
445
446 memset(regamma_params, 0, sizeof(struct pwl_params));
447
448 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
449 /* 16 segments
450 * segments are from 2^-11 to 2^5
451 */
452 segment_start = -11;
453 segment_end = 5;
454
455 seg_distr[0] = 2;
456 seg_distr[1] = 2;
457 seg_distr[2] = 2;
458 seg_distr[3] = 2;
459 seg_distr[4] = 2;
460 seg_distr[5] = 2;
461 seg_distr[6] = 3;
462 seg_distr[7] = 4;
463 seg_distr[8] = 4;
464 seg_distr[9] = 4;
465 seg_distr[10] = 4;
466 seg_distr[11] = 5;
467 seg_distr[12] = 5;
468 seg_distr[13] = 5;
469 seg_distr[14] = 5;
470 seg_distr[15] = 5;
471
472 } else {
473 /* 10 segments
474 * segment is from 2^-10 to 2^0
475 */
476 segment_start = -10;
477 segment_end = 0;
478
479 seg_distr[0] = 3;
480 seg_distr[1] = 4;
481 seg_distr[2] = 4;
482 seg_distr[3] = 4;
483 seg_distr[4] = 4;
484 seg_distr[5] = 4;
485 seg_distr[6] = 4;
486 seg_distr[7] = 4;
487 seg_distr[8] = 5;
488 seg_distr[9] = 5;
489 seg_distr[10] = -1;
490 seg_distr[11] = -1;
491 seg_distr[12] = -1;
492 seg_distr[13] = -1;
493 seg_distr[14] = -1;
494 seg_distr[15] = -1;
495 }
496
497 for (k = 0; k < 16; k++) {
498 if (seg_distr[k] != -1)
499 hw_points += (1 << seg_distr[k]);
500 }
501
502 j = 0;
503 for (k = 0; k < (segment_end - segment_start); k++) {
504 increment = 32 / (1 << seg_distr[k]);
505 start_index = (segment_start + k + 25) * 32;
506 for (i = start_index; i < start_index + 32; i += increment) {
507 if (j == hw_points - 1)
508 break;
509 rgb_resulted[j].red = output_tf->tf_pts.red[i];
510 rgb_resulted[j].green = output_tf->tf_pts.green[i];
511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
512 j++;
513 }
514 }
515
516 /* last point */
517 start_index = (segment_end + 25) * 32;
518 rgb_resulted[hw_points - 1].red =
519 output_tf->tf_pts.red[start_index];
520 rgb_resulted[hw_points - 1].green =
521 output_tf->tf_pts.green[start_index];
522 rgb_resulted[hw_points - 1].blue =
523 output_tf->tf_pts.blue[start_index];
524
525 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
526 dal_fixed31_32_from_int(segment_start));
527 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
528 dal_fixed31_32_from_int(segment_end));
529 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
530 dal_fixed31_32_from_int(segment_end));
531
532 y_r = rgb_resulted[0].red;
533 y_g = rgb_resulted[0].green;
534 y_b = rgb_resulted[0].blue;
535
536 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
537
538 arr_points[0].y = y1_min;
539 arr_points[0].slope = dal_fixed31_32_div(
540 arr_points[0].y,
541 arr_points[0].x);
542
543 y_r = rgb_resulted[hw_points - 1].red;
544 y_g = rgb_resulted[hw_points - 1].green;
545 y_b = rgb_resulted[hw_points - 1].blue;
546
547 /* see comment above, m_arrPoints[1].y should be the Y value for the
548 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
549 */
550 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
551
552 arr_points[1].y = y3_max;
553 arr_points[2].y = y3_max;
554
555 arr_points[1].slope = dal_fixed31_32_zero;
556 arr_points[2].slope = dal_fixed31_32_zero;
557
558 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
559 /* for PQ, we want to have a straight line from last HW X point,
560 * and the slope to be such that we hit 1.0 at 10000 nits.
561 */
562 const struct fixed31_32 end_value =
563 dal_fixed31_32_from_int(125);
564
565 arr_points[1].slope = dal_fixed31_32_div(
566 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
567 dal_fixed31_32_sub(end_value, arr_points[1].x));
568 arr_points[2].slope = dal_fixed31_32_div(
569 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
570 dal_fixed31_32_sub(end_value, arr_points[1].x));
571 }
572
573 regamma_params->hw_points_num = hw_points;
574
575 i = 1;
576 for (k = 0; k < 16 && i < 16; k++) {
577 if (seg_distr[k] != -1) {
578 regamma_params->arr_curve_points[k].segments_num =
579 seg_distr[k];
580 regamma_params->arr_curve_points[i].offset =
581 regamma_params->arr_curve_points[k].
582 offset + (1 << seg_distr[k]);
583 }
584 i++;
585 }
586
587 if (seg_distr[k] != -1)
588 regamma_params->arr_curve_points[k].segments_num =
589 seg_distr[k];
590
591 rgb = rgb_resulted;
592 rgb_plus_1 = rgb_resulted + 1;
593
594 i = 1;
595
596 while (i != hw_points + 1) {
597 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
598 rgb_plus_1->red = rgb->red;
599 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
600 rgb_plus_1->green = rgb->green;
601 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
602 rgb_plus_1->blue = rgb->blue;
603
604 rgb->delta_red = dal_fixed31_32_sub(
605 rgb_plus_1->red,
606 rgb->red);
607 rgb->delta_green = dal_fixed31_32_sub(
608 rgb_plus_1->green,
609 rgb->green);
610 rgb->delta_blue = dal_fixed31_32_sub(
611 rgb_plus_1->blue,
612 rgb->blue);
613
614 ++rgb_plus_1;
615 ++rgb;
616 ++i;
617 }
618
619 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
620
621 return true;
622 }
623
624 static bool dce110_set_output_transfer_func(
625 struct pipe_ctx *pipe_ctx,
626 const struct dc_stream_state *stream)
627 {
628 struct transform *xfm = pipe_ctx->plane_res.xfm;
629
630 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
631 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
632
633 if (stream->out_transfer_func &&
634 stream->out_transfer_func->type ==
635 TF_TYPE_PREDEFINED &&
636 stream->out_transfer_func->tf ==
637 TRANSFER_FUNCTION_SRGB) {
638 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
639 } else if (dce110_translate_regamma_to_hw_format(
640 stream->out_transfer_func, &xfm->regamma_params)) {
641 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
642 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
643 } else {
644 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
645 }
646
647 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
648
649 return true;
650 }
651
652 static enum dc_status bios_parser_crtc_source_select(
653 struct pipe_ctx *pipe_ctx)
654 {
655 struct dc_bios *dcb;
656 /* call VBIOS table to set CRTC source for the HW
657 * encoder block
658 * note: video bios clears all FMT setting here. */
659 struct bp_crtc_source_select crtc_source_select = {0};
660 const struct dc_sink *sink = pipe_ctx->stream->sink;
661
662 crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
663 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
664 /*TODO: Need to un-hardcode color depth, dp_audio and account for
665 * the case where signal and sink signal is different (translator
666 * encoder)*/
667 crtc_source_select.signal = pipe_ctx->stream->signal;
668 crtc_source_select.enable_dp_audio = false;
669 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
670 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
671
672 dcb = sink->ctx->dc_bios;
673
674 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
675 dcb,
676 &crtc_source_select)) {
677 return DC_ERROR_UNEXPECTED;
678 }
679
680 return DC_OK;
681 }
682
683 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
684 {
685 ASSERT(pipe_ctx->stream);
686
687 if (pipe_ctx->stream_res.stream_enc == NULL)
688 return; /* this is not root pipe */
689
690 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
691 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
692 pipe_ctx->stream_res.stream_enc,
693 &pipe_ctx->encoder_info_frame);
694 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
695 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
696 pipe_ctx->stream_res.stream_enc,
697 &pipe_ctx->encoder_info_frame);
698 }
699
700 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
701 {
702 enum dc_lane_count lane_count =
703 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
704
705 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
706 struct dc_link *link = pipe_ctx->stream->sink->link;
707
708 /* 1. update AVI info frame (HDMI, DP)
709 * we always need to update info frame
710 */
711 uint32_t active_total_with_borders;
712 uint32_t early_control = 0;
713 struct timing_generator *tg = pipe_ctx->stream_res.tg;
714
715 /* TODOFPGA may change to hwss.update_info_frame */
716 dce110_update_info_frame(pipe_ctx);
717 /* enable early control to avoid corruption on DP monitor*/
718 active_total_with_borders =
719 timing->h_addressable
720 + timing->h_border_left
721 + timing->h_border_right;
722
723 if (lane_count != 0)
724 early_control = active_total_with_borders % lane_count;
725
726 if (early_control == 0)
727 early_control = lane_count;
728
729 tg->funcs->set_early_control(tg, early_control);
730
731 /* enable audio only within mode set */
732 if (pipe_ctx->audio != NULL) {
733 if (dc_is_dp_signal(pipe_ctx->stream->signal))
734 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
735 }
736
737 /* For MST, there are multiply stream go to only one link.
738 * connect DIG back_end to front_end while enable_stream and
739 * disconnect them during disable_stream
740 * BY this, it is logic clean to separate stream and link */
741 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
742 pipe_ctx->stream_res.stream_enc->id, true);
743
744 }
745
746 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
747 {
748 struct dc_stream_state *stream = pipe_ctx->stream;
749 struct dc_link *link = stream->sink->link;
750
751 if (pipe_ctx->audio) {
752 pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio);
753
754 if (dc_is_dp_signal(pipe_ctx->stream->signal))
755 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
756 pipe_ctx->stream_res.stream_enc);
757 else
758 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
759 pipe_ctx->stream_res.stream_enc);
760
761 pipe_ctx->audio = NULL;
762
763 /* TODO: notify audio driver for if audio modes list changed
764 * add audio mode list change flag */
765 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
766 * stream->stream_engine_id);
767 */
768 }
769
770 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
771 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
772 pipe_ctx->stream_res.stream_enc);
773
774 if (dc_is_dp_signal(pipe_ctx->stream->signal))
775 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
776 pipe_ctx->stream_res.stream_enc);
777
778 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
779 pipe_ctx->stream_res.stream_enc, true);
780
781
782 /* blank at encoder level */
783 if (dc_is_dp_signal(pipe_ctx->stream->signal))
784 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
785
786 link->link_enc->funcs->connect_dig_be_to_fe(
787 link->link_enc,
788 pipe_ctx->stream_res.stream_enc->id,
789 false);
790
791 }
792
793 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
794 struct dc_link_settings *link_settings)
795 {
796 struct encoder_unblank_param params = { { 0 } };
797
798 /* only 3 items below are used by unblank */
799 params.pixel_clk_khz =
800 pipe_ctx->stream->timing.pix_clk_khz;
801 params.link_settings.link_rate = link_settings->link_rate;
802 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
803 }
804
805
806 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
807 {
808 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
809 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
810 }
811
812 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
813 {
814 switch (crtc_id) {
815 case CONTROLLER_ID_D0:
816 return DTO_SOURCE_ID0;
817 case CONTROLLER_ID_D1:
818 return DTO_SOURCE_ID1;
819 case CONTROLLER_ID_D2:
820 return DTO_SOURCE_ID2;
821 case CONTROLLER_ID_D3:
822 return DTO_SOURCE_ID3;
823 case CONTROLLER_ID_D4:
824 return DTO_SOURCE_ID4;
825 case CONTROLLER_ID_D5:
826 return DTO_SOURCE_ID5;
827 default:
828 return DTO_SOURCE_UNKNOWN;
829 }
830 }
831
832 static void build_audio_output(
833 const struct pipe_ctx *pipe_ctx,
834 struct audio_output *audio_output)
835 {
836 const struct dc_stream_state *stream = pipe_ctx->stream;
837 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
838
839 audio_output->signal = pipe_ctx->stream->signal;
840
841 /* audio_crtc_info */
842
843 audio_output->crtc_info.h_total =
844 stream->timing.h_total;
845
846 /*
847 * Audio packets are sent during actual CRTC blank physical signal, we
848 * need to specify actual active signal portion
849 */
850 audio_output->crtc_info.h_active =
851 stream->timing.h_addressable
852 + stream->timing.h_border_left
853 + stream->timing.h_border_right;
854
855 audio_output->crtc_info.v_active =
856 stream->timing.v_addressable
857 + stream->timing.v_border_top
858 + stream->timing.v_border_bottom;
859
860 audio_output->crtc_info.pixel_repetition = 1;
861
862 audio_output->crtc_info.interlaced =
863 stream->timing.flags.INTERLACE;
864
865 audio_output->crtc_info.refresh_rate =
866 (stream->timing.pix_clk_khz*1000)/
867 (stream->timing.h_total*stream->timing.v_total);
868
869 audio_output->crtc_info.color_depth =
870 stream->timing.display_color_depth;
871
872 audio_output->crtc_info.requested_pixel_clock =
873 pipe_ctx->pix_clk_params.requested_pix_clk;
874
875 audio_output->crtc_info.calculated_pixel_clock =
876 pipe_ctx->pix_clk_params.requested_pix_clk;
877
878 /*for HDMI, audio ACR is with deep color ratio factor*/
879 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
880 audio_output->crtc_info.requested_pixel_clock ==
881 stream->timing.pix_clk_khz) {
882 if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
883 audio_output->crtc_info.requested_pixel_clock =
884 audio_output->crtc_info.requested_pixel_clock/2;
885 audio_output->crtc_info.calculated_pixel_clock =
886 pipe_ctx->pix_clk_params.requested_pix_clk/2;
887
888 }
889 }
890
891 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
892 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
893 audio_output->pll_info.dp_dto_source_clock_in_khz =
894 pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
895 pipe_ctx->dis_clk);
896 }
897
898 audio_output->pll_info.feed_back_divider =
899 pipe_ctx->pll_settings.feedback_divider;
900
901 audio_output->pll_info.dto_source =
902 translate_to_dto_source(
903 pipe_ctx->pipe_idx + 1);
904
905 /* TODO hard code to enable for now. Need get from stream */
906 audio_output->pll_info.ss_enabled = true;
907
908 audio_output->pll_info.ss_percentage =
909 pipe_ctx->pll_settings.ss_percentage;
910 }
911
912 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
913 struct tg_color *color)
914 {
915 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
916
917 switch (pipe_ctx->plane_res.scl_data.format) {
918 case PIXEL_FORMAT_ARGB8888:
919 /* set boarder color to red */
920 color->color_r_cr = color_value;
921 break;
922
923 case PIXEL_FORMAT_ARGB2101010:
924 /* set boarder color to blue */
925 color->color_b_cb = color_value;
926 break;
927 case PIXEL_FORMAT_420BPP8:
928 /* set boarder color to green */
929 color->color_g_y = color_value;
930 break;
931 case PIXEL_FORMAT_420BPP10:
932 /* set boarder color to yellow */
933 color->color_g_y = color_value;
934 color->color_r_cr = color_value;
935 break;
936 case PIXEL_FORMAT_FP16:
937 /* set boarder color to white */
938 color->color_r_cr = color_value;
939 color->color_b_cb = color_value;
940 color->color_g_y = color_value;
941 break;
942 default:
943 break;
944 }
945 }
946
947 static void program_scaler(const struct core_dc *dc,
948 const struct pipe_ctx *pipe_ctx)
949 {
950 struct tg_color color = {0};
951
952 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
953 /* TOFPGA */
954 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
955 return;
956 #endif
957
958 if (dc->public.debug.surface_visual_confirm)
959 get_surface_visual_confirm_color(pipe_ctx, &color);
960 else
961 color_space_to_black_color(dc,
962 pipe_ctx->stream->output_color_space,
963 &color);
964
965 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
966 pipe_ctx->plane_res.xfm,
967 pipe_ctx->plane_res.scl_data.lb_params.depth,
968 &pipe_ctx->stream->bit_depth_params);
969
970 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
971 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
972 pipe_ctx->stream_res.tg,
973 &color);
974
975 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
976 &pipe_ctx->plane_res.scl_data);
977 }
978
979 static enum dc_status dce110_prog_pixclk_crtc_otg(
980 struct pipe_ctx *pipe_ctx,
981 struct validate_context *context,
982 struct core_dc *dc)
983 {
984 struct dc_stream_state *stream = pipe_ctx->stream;
985 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
986 pipe_ctx[pipe_ctx->pipe_idx];
987 struct tg_color black_color = {0};
988
989 if (!pipe_ctx_old->stream) {
990
991 /* program blank color */
992 color_space_to_black_color(dc,
993 stream->output_color_space, &black_color);
994 pipe_ctx->stream_res.tg->funcs->set_blank_color(
995 pipe_ctx->stream_res.tg,
996 &black_color);
997
998 /*
999 * Must blank CRTC after disabling power gating and before any
1000 * programming, otherwise CRTC will be hung in bad state
1001 */
1002 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1003
1004 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1005 pipe_ctx->clock_source,
1006 &pipe_ctx->pix_clk_params,
1007 &pipe_ctx->pll_settings)) {
1008 BREAK_TO_DEBUGGER();
1009 return DC_ERROR_UNEXPECTED;
1010 }
1011
1012 pipe_ctx->stream_res.tg->funcs->program_timing(
1013 pipe_ctx->stream_res.tg,
1014 &stream->timing,
1015 true);
1016
1017 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1018 pipe_ctx->stream_res.tg,
1019 0x182);
1020 }
1021
1022 if (!pipe_ctx_old->stream) {
1023 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1024 pipe_ctx->stream_res.tg)) {
1025 BREAK_TO_DEBUGGER();
1026 return DC_ERROR_UNEXPECTED;
1027 }
1028 }
1029
1030
1031
1032 return DC_OK;
1033 }
1034
1035 static enum dc_status apply_single_controller_ctx_to_hw(
1036 struct pipe_ctx *pipe_ctx,
1037 struct validate_context *context,
1038 struct core_dc *dc)
1039 {
1040 struct dc_stream_state *stream = pipe_ctx->stream;
1041 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
1042 pipe_ctx[pipe_ctx->pipe_idx];
1043
1044 /* */
1045 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1046
1047 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1048 pipe_ctx->stream_res.opp,
1049 COLOR_SPACE_YCBCR601,
1050 stream->timing.display_color_depth,
1051 pipe_ctx->stream->signal);
1052
1053 /* FPGA does not program backend */
1054 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1055 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1056 pipe_ctx->stream_res.opp,
1057 &stream->bit_depth_params,
1058 &stream->clamping);
1059 return DC_OK;
1060 }
1061 /* TODO: move to stream encoder */
1062 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1063 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1064 BREAK_TO_DEBUGGER();
1065 return DC_ERROR_UNEXPECTED;
1066 }
1067
1068 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1069 stream->sink->link->link_enc->funcs->setup(
1070 stream->sink->link->link_enc,
1071 pipe_ctx->stream->signal);
1072
1073 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1074 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1075 pipe_ctx->stream_res.stream_enc,
1076 pipe_ctx->stream_res.tg->inst,
1077 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1078
1079
1080 /*vbios crtc_source_selection and encoder_setup will override fmt_C*/
1081 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1082 pipe_ctx->stream_res.opp,
1083 &stream->bit_depth_params,
1084 &stream->clamping);
1085
1086 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1087 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1088 pipe_ctx->stream_res.stream_enc,
1089 &stream->timing,
1090 stream->output_color_space);
1091
1092 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1093 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1094 pipe_ctx->stream_res.stream_enc,
1095 &stream->timing,
1096 stream->phy_pix_clk,
1097 pipe_ctx->audio != NULL);
1098
1099 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1100 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1101 pipe_ctx->stream_res.stream_enc,
1102 &stream->timing,
1103 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1104 true : false);
1105
1106 resource_build_info_frame(pipe_ctx);
1107 dce110_update_info_frame(pipe_ctx);
1108 if (!pipe_ctx_old->stream) {
1109 core_link_enable_stream(pipe_ctx);
1110
1111
1112 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1113 dce110_unblank_stream(pipe_ctx,
1114 &stream->sink->link->cur_link_settings);
1115 }
1116
1117 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1118 /* program_scaler and allocate_mem_input are not new asic */
1119 if ((!pipe_ctx_old ||
1120 memcmp(&pipe_ctx_old->plane_res.scl_data, &pipe_ctx->plane_res.scl_data,
1121 sizeof(struct scaler_data)) != 0) &&
1122 pipe_ctx->plane_state) {
1123 program_scaler(dc, pipe_ctx);
1124 }
1125
1126 /* mst support - use total stream count */
1127 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1128 if (pipe_ctx->plane_res.mi->funcs->allocate_mem_input != NULL)
1129 #endif
1130 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
1131 pipe_ctx->plane_res.mi,
1132 stream->timing.h_total,
1133 stream->timing.v_total,
1134 stream->timing.pix_clk_khz,
1135 context->stream_count);
1136
1137 pipe_ctx->stream->sink->link->psr_enabled = false;
1138
1139 return DC_OK;
1140 }
1141
1142 /******************************************************************************/
1143
1144 static void power_down_encoders(struct core_dc *dc)
1145 {
1146 int i;
1147
1148 for (i = 0; i < dc->link_count; i++) {
1149 dc->links[i]->link_enc->funcs->disable_output(
1150 dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
1151 }
1152 }
1153
1154 static void power_down_controllers(struct core_dc *dc)
1155 {
1156 int i;
1157
1158 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1159 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1160 dc->res_pool->timing_generators[i]);
1161 }
1162 }
1163
1164 static void power_down_clock_sources(struct core_dc *dc)
1165 {
1166 int i;
1167
1168 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1169 dc->res_pool->dp_clock_source) == false)
1170 dm_error("Failed to power down pll! (dp clk src)\n");
1171
1172 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1173 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1174 dc->res_pool->clock_sources[i]) == false)
1175 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1176 }
1177 }
1178
1179 static void power_down_all_hw_blocks(struct core_dc *dc)
1180 {
1181 power_down_encoders(dc);
1182
1183 power_down_controllers(dc);
1184
1185 power_down_clock_sources(dc);
1186
1187 #ifdef ENABLE_FBC
1188 if (dc->fbc_compressor)
1189 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1190 #endif
1191 }
1192
1193 static void disable_vga_and_power_gate_all_controllers(
1194 struct core_dc *dc)
1195 {
1196 int i;
1197 struct timing_generator *tg;
1198 struct dc_context *ctx = dc->ctx;
1199
1200 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1201 tg = dc->res_pool->timing_generators[i];
1202
1203 if (tg->funcs->disable_vga)
1204 tg->funcs->disable_vga(tg);
1205
1206 /* Enable CLOCK gating for each pipe BEFORE controller
1207 * powergating. */
1208 enable_display_pipe_clock_gating(ctx,
1209 true);
1210
1211 dc->hwss.power_down_front_end(dc, i);
1212 }
1213 }
1214
1215 /**
1216 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1217 * 1. Power down all DC HW blocks
1218 * 2. Disable VGA engine on all controllers
1219 * 3. Enable power gating for controller
1220 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1221 */
1222 void dce110_enable_accelerated_mode(struct core_dc *dc)
1223 {
1224 power_down_all_hw_blocks(dc);
1225
1226 disable_vga_and_power_gate_all_controllers(dc);
1227 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1228 }
1229
1230 static uint32_t compute_pstate_blackout_duration(
1231 struct bw_fixed blackout_duration,
1232 const struct dc_stream_state *stream)
1233 {
1234 uint32_t total_dest_line_time_ns;
1235 uint32_t pstate_blackout_duration_ns;
1236
1237 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1238
1239 total_dest_line_time_ns = 1000000UL *
1240 stream->timing.h_total /
1241 stream->timing.pix_clk_khz +
1242 pstate_blackout_duration_ns;
1243
1244 return total_dest_line_time_ns;
1245 }
1246
1247 void dce110_set_displaymarks(
1248 const struct core_dc *dc,
1249 struct validate_context *context)
1250 {
1251 uint8_t i, num_pipes;
1252 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1253
1254 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1255 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1256 uint32_t total_dest_line_time_ns;
1257
1258 if (pipe_ctx->stream == NULL)
1259 continue;
1260
1261 total_dest_line_time_ns = compute_pstate_blackout_duration(
1262 dc->bw_vbios.blackout_duration, pipe_ctx->stream);
1263 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1264 pipe_ctx->plane_res.mi,
1265 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1266 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1267 context->bw.dce.urgent_wm_ns[num_pipes],
1268 total_dest_line_time_ns);
1269 if (i == underlay_idx) {
1270 num_pipes++;
1271 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1272 pipe_ctx->plane_res.mi,
1273 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1274 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1275 context->bw.dce.urgent_wm_ns[num_pipes],
1276 total_dest_line_time_ns);
1277 }
1278 num_pipes++;
1279 }
1280 }
1281
1282 static void set_safe_displaymarks(
1283 struct resource_context *res_ctx,
1284 const struct resource_pool *pool)
1285 {
1286 int i;
1287 int underlay_idx = pool->underlay_pipe_index;
1288 struct dce_watermarks max_marks = {
1289 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1290 struct dce_watermarks nbp_marks = {
1291 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1292
1293 for (i = 0; i < MAX_PIPES; i++) {
1294 if (res_ctx->pipe_ctx[i].stream == NULL)
1295 continue;
1296
1297 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1298 res_ctx->pipe_ctx[i].plane_res.mi,
1299 nbp_marks,
1300 max_marks,
1301 max_marks,
1302 MAX_WATERMARK);
1303 if (i == underlay_idx)
1304 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1305 res_ctx->pipe_ctx[i].plane_res.mi,
1306 nbp_marks,
1307 max_marks,
1308 max_marks,
1309 MAX_WATERMARK);
1310 }
1311 }
1312
1313 static void switch_dp_clock_sources(
1314 const struct core_dc *dc,
1315 struct resource_context *res_ctx)
1316 {
1317 uint8_t i;
1318 for (i = 0; i < MAX_PIPES; i++) {
1319 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1320
1321 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1322 continue;
1323
1324 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1325 struct clock_source *clk_src =
1326 resource_find_used_clk_src_for_sharing(
1327 res_ctx, pipe_ctx);
1328
1329 if (clk_src &&
1330 clk_src != pipe_ctx->clock_source) {
1331 resource_unreference_clock_source(
1332 res_ctx, dc->res_pool,
1333 &pipe_ctx->clock_source);
1334 pipe_ctx->clock_source = clk_src;
1335 resource_reference_clock_source(
1336 res_ctx, dc->res_pool, clk_src);
1337
1338 dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
1339 }
1340 }
1341 }
1342 }
1343
1344 /*******************************************************************************
1345 * Public functions
1346 ******************************************************************************/
1347
1348 static void set_drr(struct pipe_ctx **pipe_ctx,
1349 int num_pipes, int vmin, int vmax)
1350 {
1351 int i = 0;
1352 struct drr_params params = {0};
1353
1354 params.vertical_total_max = vmax;
1355 params.vertical_total_min = vmin;
1356
1357 /* TODO: If multiple pipes are to be supported, you need
1358 * some GSL stuff
1359 */
1360
1361 for (i = 0; i < num_pipes; i++) {
1362 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1363 }
1364 }
1365
1366 static void get_position(struct pipe_ctx **pipe_ctx,
1367 int num_pipes,
1368 struct crtc_position *position)
1369 {
1370 int i = 0;
1371
1372 /* TODO: handle pipes > 1
1373 */
1374 for (i = 0; i < num_pipes; i++)
1375 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1376 }
1377
1378 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1379 int num_pipes, const struct dc_static_screen_events *events)
1380 {
1381 unsigned int i;
1382 unsigned int value = 0;
1383
1384 if (events->overlay_update)
1385 value |= 0x100;
1386 if (events->surface_update)
1387 value |= 0x80;
1388 if (events->cursor_update)
1389 value |= 0x2;
1390
1391 #ifdef ENABLE_FBC
1392 value |= 0x84;
1393 #endif
1394
1395 for (i = 0; i < num_pipes; i++)
1396 pipe_ctx[i]->stream_res.tg->funcs->
1397 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1398 }
1399
1400 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1401 * may not be programmed yet.
1402 * TODO: after mode set, pre_mode_set = false,
1403 * may read PLL register to get pixel clock
1404 */
1405 static uint32_t get_max_pixel_clock_for_all_paths(
1406 struct core_dc *dc,
1407 struct validate_context *context,
1408 bool pre_mode_set)
1409 {
1410 uint32_t max_pix_clk = 0;
1411 int i;
1412
1413 if (!pre_mode_set) {
1414 /* TODO: read ASIC register to get pixel clock */
1415 ASSERT(0);
1416 }
1417
1418 for (i = 0; i < MAX_PIPES; i++) {
1419 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1420
1421 if (pipe_ctx->stream == NULL)
1422 continue;
1423
1424 /* do not check under lay */
1425 if (pipe_ctx->top_pipe)
1426 continue;
1427
1428 if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk)
1429 max_pix_clk =
1430 pipe_ctx->pix_clk_params.requested_pix_clk;
1431 }
1432
1433 if (max_pix_clk == 0)
1434 ASSERT(0);
1435
1436 return max_pix_clk;
1437 }
1438
1439 /* Find clock state based on clock requested. if clock value is 0, simply
1440 * set clock state as requested without finding clock state by clock value
1441 *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock.
1442 *
1443 * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value
1444 * etc support for dcn1.0
1445 */
1446 static void apply_min_clocks(
1447 struct core_dc *dc,
1448 struct validate_context *context,
1449 enum dm_pp_clocks_state *clocks_state,
1450 bool pre_mode_set)
1451 {
1452 struct state_dependent_clocks req_clocks = {0};
1453 struct pipe_ctx *pipe_ctx;
1454 int i;
1455
1456 for (i = 0; i < MAX_PIPES; i++) {
1457 pipe_ctx = &context->res_ctx.pipe_ctx[i];
1458 if (pipe_ctx->dis_clk != NULL)
1459 break;
1460 }
1461
1462 if (!pre_mode_set) {
1463 /* set clock_state without verification */
1464 if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
1465 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1466 pipe_ctx->dis_clk, *clocks_state);
1467 return;
1468 }
1469
1470 /* TODO: This is incorrect. Figure out how to fix. */
1471 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1472 pipe_ctx->dis_clk,
1473 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1474 pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz,
1475 pre_mode_set,
1476 false);
1477
1478 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1479 pipe_ctx->dis_clk,
1480 DM_PP_CLOCK_TYPE_PIXELCLK,
1481 pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1482 pre_mode_set,
1483 false);
1484
1485 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1486 pipe_ctx->dis_clk,
1487 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1488 pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1489 pre_mode_set,
1490 false);
1491 return;
1492 }
1493
1494 /* get the required state based on state dependent clocks:
1495 * display clock and pixel clock
1496 */
1497 req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1498
1499 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1500 dc, context, true);
1501
1502 if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) {
1503 *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state(
1504 pipe_ctx->dis_clk, &req_clocks);
1505 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1506 pipe_ctx->dis_clk, *clocks_state);
1507 } else {
1508 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1509 pipe_ctx->dis_clk,
1510 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1511 req_clocks.display_clk_khz,
1512 pre_mode_set,
1513 false);
1514
1515 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1516 pipe_ctx->dis_clk,
1517 DM_PP_CLOCK_TYPE_PIXELCLK,
1518 req_clocks.pixel_clk_khz,
1519 pre_mode_set,
1520 false);
1521
1522 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1523 pipe_ctx->dis_clk,
1524 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1525 req_clocks.pixel_clk_khz,
1526 pre_mode_set,
1527 false);
1528 }
1529 }
1530
1531 #ifdef ENABLE_FBC
1532
1533 /*
1534 * Check if FBC can be enabled
1535 */
1536 static enum dc_status validate_fbc(struct core_dc *dc,
1537 struct validate_context *context)
1538 {
1539 struct pipe_ctx *pipe_ctx =
1540 &context->res_ctx.pipe_ctx[0];
1541
1542 ASSERT(dc->fbc_compressor);
1543
1544 /* FBC memory should be allocated */
1545 if (!dc->ctx->fbc_gpu_addr)
1546 return DC_ERROR_UNEXPECTED;
1547
1548 /* Only supports single display */
1549 if (context->stream_count != 1)
1550 return DC_ERROR_UNEXPECTED;
1551
1552 /* Only supports eDP */
1553 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1554 return DC_ERROR_UNEXPECTED;
1555
1556 /* PSR should not be enabled */
1557 if (pipe_ctx->stream->sink->link->psr_enabled)
1558 return DC_ERROR_UNEXPECTED;
1559
1560 return DC_OK;
1561 }
1562
1563 /*
1564 * Enable FBC
1565 */
1566 static enum dc_status enable_fbc(struct core_dc *dc,
1567 struct validate_context *context)
1568 {
1569 enum dc_status status = validate_fbc(dc, context);
1570
1571 if (status == DC_OK) {
1572 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1573 struct compr_addr_and_pitch_params params = {0, 0, 0};
1574 struct compressor *compr = dc->fbc_compressor;
1575 struct pipe_ctx *pipe_ctx =
1576 &context->res_ctx.pipe_ctx[0];
1577
1578 params.source_view_width =
1579 pipe_ctx->stream->timing.h_addressable;
1580 params.source_view_height =
1581 pipe_ctx->stream->timing.v_addressable;
1582
1583 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1584
1585 compr->funcs->surface_address_and_pitch(compr, &params);
1586 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1587
1588 compr->funcs->enable_fbc(compr, &params);
1589 }
1590 return status;
1591 }
1592 #endif
1593
1594 static enum dc_status apply_ctx_to_hw_fpga(
1595 struct core_dc *dc,
1596 struct validate_context *context)
1597 {
1598 enum dc_status status = DC_ERROR_UNEXPECTED;
1599 int i;
1600
1601 for (i = 0; i < MAX_PIPES; i++) {
1602 struct pipe_ctx *pipe_ctx_old =
1603 &dc->current_context->res_ctx.pipe_ctx[i];
1604 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1605
1606 if (pipe_ctx->stream == NULL)
1607 continue;
1608
1609 if (pipe_ctx->stream == pipe_ctx_old->stream)
1610 continue;
1611
1612 status = apply_single_controller_ctx_to_hw(
1613 pipe_ctx,
1614 context,
1615 dc);
1616
1617 if (status != DC_OK)
1618 return status;
1619 }
1620
1621 return DC_OK;
1622 }
1623
1624 static void dce110_reset_hw_ctx_wrap(
1625 struct core_dc *dc,
1626 struct validate_context *context)
1627 {
1628 int i;
1629
1630 /* Reset old context */
1631 /* look up the targets that have been removed since last commit */
1632 for (i = 0; i < MAX_PIPES; i++) {
1633 struct pipe_ctx *pipe_ctx_old =
1634 &dc->current_context->res_ctx.pipe_ctx[i];
1635 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1636
1637 /* Note: We need to disable output if clock sources change,
1638 * since bios does optimization and doesn't apply if changing
1639 * PHY when not already disabled.
1640 */
1641
1642 /* Skip underlay pipe since it will be handled in commit surface*/
1643 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1644 continue;
1645
1646 if (!pipe_ctx->stream ||
1647 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1648 core_link_disable_stream(pipe_ctx_old);
1649 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1650 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1651 dm_error("DC: failed to blank crtc!\n");
1652 BREAK_TO_DEBUGGER();
1653 }
1654 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1655 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1656 pipe_ctx_old->plane_res.mi, dc->current_context->stream_count);
1657 resource_unreference_clock_source(
1658 &dc->current_context->res_ctx, dc->res_pool,
1659 &pipe_ctx_old->clock_source);
1660
1661 dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
1662
1663 pipe_ctx_old->stream = NULL;
1664 }
1665 }
1666 }
1667
1668
1669 enum dc_status dce110_apply_ctx_to_hw(
1670 struct core_dc *dc,
1671 struct validate_context *context)
1672 {
1673 struct dc_bios *dcb = dc->ctx->dc_bios;
1674 enum dc_status status;
1675 int i;
1676 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1677
1678 /* Reset old context */
1679 /* look up the targets that have been removed since last commit */
1680 dc->hwss.reset_hw_ctx_wrap(dc, context);
1681
1682 /* Skip applying if no targets */
1683 if (context->stream_count <= 0)
1684 return DC_OK;
1685
1686 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1687 apply_ctx_to_hw_fpga(dc, context);
1688 return DC_OK;
1689 }
1690
1691 /* Apply new context */
1692 dcb->funcs->set_scratch_critical_state(dcb, true);
1693
1694 /* below is for real asic only */
1695 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1696 struct pipe_ctx *pipe_ctx_old =
1697 &dc->current_context->res_ctx.pipe_ctx[i];
1698 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1699
1700 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1701 continue;
1702
1703 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1704 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1705 dce_crtc_switch_to_clk_src(dc->hwseq,
1706 pipe_ctx->clock_source, i);
1707 continue;
1708 }
1709
1710 dc->hwss.enable_display_power_gating(
1711 dc, i, dc->ctx->dc_bios,
1712 PIPE_GATING_CONTROL_DISABLE);
1713 }
1714
1715 set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1716
1717 #ifdef ENABLE_FBC
1718 if (dc->fbc_compressor)
1719 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1720 #endif
1721 /*TODO: when pplib works*/
1722 apply_min_clocks(dc, context, &clocks_state, true);
1723
1724 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1725 if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1726 if (context->bw.dcn.calc_clk.fclk_khz
1727 > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
1728 struct dm_pp_clock_for_voltage_req clock;
1729
1730 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1731 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1732 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1733 dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1734 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1735 }
1736 if (context->bw.dcn.calc_clk.dcfclk_khz
1737 > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
1738 struct dm_pp_clock_for_voltage_req clock;
1739
1740 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1741 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1742 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1743 dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1744 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1745 }
1746 if (context->bw.dcn.calc_clk.dispclk_khz
1747 > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
1748 dc->res_pool->display_clock->funcs->set_clock(
1749 dc->res_pool->display_clock,
1750 context->bw.dcn.calc_clk.dispclk_khz);
1751 dc->current_context->bw.dcn.cur_clk.dispclk_khz =
1752 context->bw.dcn.calc_clk.dispclk_khz;
1753 context->bw.dcn.cur_clk.dispclk_khz =
1754 context->bw.dcn.calc_clk.dispclk_khz;
1755 }
1756 } else
1757 #endif
1758 if (context->bw.dce.dispclk_khz
1759 > dc->current_context->bw.dce.dispclk_khz) {
1760 dc->res_pool->display_clock->funcs->set_clock(
1761 dc->res_pool->display_clock,
1762 context->bw.dce.dispclk_khz * 115 / 100);
1763 }
1764 /* program audio wall clock. use HDMI as clock source if HDMI
1765 * audio active. Otherwise, use DP as clock source
1766 * first, loop to find any HDMI audio, if not, loop find DP audio
1767 */
1768 /* Setup audio rate clock source */
1769 /* Issue:
1770 * Audio lag happened on DP monitor when unplug a HDMI monitor
1771 *
1772 * Cause:
1773 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1774 * is set to either dto0 or dto1, audio should work fine.
1775 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1776 * set to dto0 will cause audio lag.
1777 *
1778 * Solution:
1779 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1780 * find first available pipe with audio, setup audio wall DTO per topology
1781 * instead of per pipe.
1782 */
1783 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1784 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1785
1786 if (pipe_ctx->stream == NULL)
1787 continue;
1788
1789 if (pipe_ctx->top_pipe)
1790 continue;
1791
1792 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1793 continue;
1794
1795 if (pipe_ctx->audio != NULL) {
1796 struct audio_output audio_output;
1797
1798 build_audio_output(pipe_ctx, &audio_output);
1799
1800 pipe_ctx->audio->funcs->wall_dto_setup(
1801 pipe_ctx->audio,
1802 pipe_ctx->stream->signal,
1803 &audio_output.crtc_info,
1804 &audio_output.pll_info);
1805 break;
1806 }
1807 }
1808
1809 /* no HDMI audio is found, try DP audio */
1810 if (i == dc->res_pool->pipe_count) {
1811 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1812 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1813
1814 if (pipe_ctx->stream == NULL)
1815 continue;
1816
1817 if (pipe_ctx->top_pipe)
1818 continue;
1819
1820 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1821 continue;
1822
1823 if (pipe_ctx->audio != NULL) {
1824 struct audio_output audio_output;
1825
1826 build_audio_output(pipe_ctx, &audio_output);
1827
1828 pipe_ctx->audio->funcs->wall_dto_setup(
1829 pipe_ctx->audio,
1830 pipe_ctx->stream->signal,
1831 &audio_output.crtc_info,
1832 &audio_output.pll_info);
1833 break;
1834 }
1835 }
1836 }
1837
1838 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1839 struct pipe_ctx *pipe_ctx_old =
1840 &dc->current_context->res_ctx.pipe_ctx[i];
1841 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1842
1843 if (pipe_ctx->stream == NULL)
1844 continue;
1845
1846 if (pipe_ctx->stream == pipe_ctx_old->stream)
1847 continue;
1848
1849 if (pipe_ctx->stream && pipe_ctx_old->stream
1850 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1851 continue;
1852
1853 if (pipe_ctx->top_pipe)
1854 continue;
1855
1856 if (context->res_ctx.pipe_ctx[i].audio != NULL) {
1857
1858 struct audio_output audio_output;
1859
1860 build_audio_output(pipe_ctx, &audio_output);
1861
1862 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1863 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1864 pipe_ctx->stream_res.stream_enc,
1865 pipe_ctx->audio->inst,
1866 &pipe_ctx->stream->audio_info);
1867 else
1868 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1869 pipe_ctx->stream_res.stream_enc,
1870 pipe_ctx->audio->inst,
1871 &pipe_ctx->stream->audio_info,
1872 &audio_output.crtc_info);
1873
1874 pipe_ctx->audio->funcs->az_configure(
1875 pipe_ctx->audio,
1876 pipe_ctx->stream->signal,
1877 &audio_output.crtc_info,
1878 &pipe_ctx->stream->audio_info);
1879 }
1880
1881 status = apply_single_controller_ctx_to_hw(
1882 pipe_ctx,
1883 context,
1884 dc);
1885
1886 if (dc->hwss.power_on_front_end)
1887 dc->hwss.power_on_front_end(dc, pipe_ctx, context);
1888
1889 if (DC_OK != status)
1890 return status;
1891 }
1892
1893 dc->hwss.set_bandwidth(dc, context, true);
1894
1895 /* to save power */
1896 apply_min_clocks(dc, context, &clocks_state, false);
1897
1898 dcb->funcs->set_scratch_critical_state(dcb, false);
1899
1900 switch_dp_clock_sources(dc, &context->res_ctx);
1901
1902 #ifdef ENABLE_FBC
1903 if (dc->fbc_compressor)
1904 enable_fbc(dc, context);
1905
1906 #endif
1907
1908 return DC_OK;
1909 }
1910
1911 /*******************************************************************************
1912 * Front End programming
1913 ******************************************************************************/
1914 static void set_default_colors(struct pipe_ctx *pipe_ctx)
1915 {
1916 struct default_adjustment default_adjust = { 0 };
1917
1918 default_adjust.force_hw_default = false;
1919 if (pipe_ctx->plane_state == NULL)
1920 default_adjust.in_color_space = COLOR_SPACE_SRGB;
1921 else
1922 default_adjust.in_color_space =
1923 pipe_ctx->plane_state->color_space;
1924 if (pipe_ctx->stream == NULL)
1925 default_adjust.out_color_space = COLOR_SPACE_SRGB;
1926 else
1927 default_adjust.out_color_space =
1928 pipe_ctx->stream->output_color_space;
1929 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
1930 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
1931
1932 /* display color depth */
1933 default_adjust.color_depth =
1934 pipe_ctx->stream->timing.display_color_depth;
1935
1936 /* Lb color depth */
1937 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
1938
1939 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
1940 pipe_ctx->plane_res.xfm, &default_adjust);
1941 }
1942
1943
1944 /*******************************************************************************
1945 * In order to turn on/off specific surface we will program
1946 * Blender + CRTC
1947 *
1948 * In case that we have two surfaces and they have a different visibility
1949 * we can't turn off the CRTC since it will turn off the entire display
1950 *
1951 * |----------------------------------------------- |
1952 * |bottom pipe|curr pipe | | |
1953 * |Surface |Surface | Blender | CRCT |
1954 * |visibility |visibility | Configuration| |
1955 * |------------------------------------------------|
1956 * | off | off | CURRENT_PIPE | blank |
1957 * | off | on | CURRENT_PIPE | unblank |
1958 * | on | off | OTHER_PIPE | unblank |
1959 * | on | on | BLENDING | unblank |
1960 * -------------------------------------------------|
1961 *
1962 ******************************************************************************/
1963 static void program_surface_visibility(const struct core_dc *dc,
1964 struct pipe_ctx *pipe_ctx)
1965 {
1966 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
1967 bool blank_target = false;
1968
1969 if (pipe_ctx->bottom_pipe) {
1970
1971 /* For now we are supporting only two pipes */
1972 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
1973
1974 if (pipe_ctx->bottom_pipe->plane_state->visible) {
1975 if (pipe_ctx->plane_state->visible)
1976 blender_mode = BLND_MODE_BLENDING;
1977 else
1978 blender_mode = BLND_MODE_OTHER_PIPE;
1979
1980 } else if (!pipe_ctx->plane_state->visible)
1981 blank_target = true;
1982
1983 } else if (!pipe_ctx->plane_state->visible)
1984 blank_target = true;
1985
1986 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
1987 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
1988
1989 }
1990
1991 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1992 {
1993 struct xfm_grph_csc_adjustment adjust;
1994 memset(&adjust, 0, sizeof(adjust));
1995 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1996
1997
1998 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1999 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2000 adjust.temperature_matrix[0] =
2001 pipe_ctx->stream->
2002 gamut_remap_matrix.matrix[0];
2003 adjust.temperature_matrix[1] =
2004 pipe_ctx->stream->
2005 gamut_remap_matrix.matrix[1];
2006 adjust.temperature_matrix[2] =
2007 pipe_ctx->stream->
2008 gamut_remap_matrix.matrix[2];
2009 adjust.temperature_matrix[3] =
2010 pipe_ctx->stream->
2011 gamut_remap_matrix.matrix[4];
2012 adjust.temperature_matrix[4] =
2013 pipe_ctx->stream->
2014 gamut_remap_matrix.matrix[5];
2015 adjust.temperature_matrix[5] =
2016 pipe_ctx->stream->
2017 gamut_remap_matrix.matrix[6];
2018 adjust.temperature_matrix[6] =
2019 pipe_ctx->stream->
2020 gamut_remap_matrix.matrix[8];
2021 adjust.temperature_matrix[7] =
2022 pipe_ctx->stream->
2023 gamut_remap_matrix.matrix[9];
2024 adjust.temperature_matrix[8] =
2025 pipe_ctx->stream->
2026 gamut_remap_matrix.matrix[10];
2027 }
2028
2029 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2030 }
2031
2032 /**
2033 * TODO REMOVE, USE UPDATE INSTEAD
2034 */
2035 static void set_plane_config(
2036 const struct core_dc *dc,
2037 struct pipe_ctx *pipe_ctx,
2038 struct resource_context *res_ctx)
2039 {
2040 struct mem_input *mi = pipe_ctx->plane_res.mi;
2041 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2042 struct xfm_grph_csc_adjustment adjust;
2043 struct out_csc_color_matrix tbl_entry;
2044 unsigned int i;
2045
2046 memset(&adjust, 0, sizeof(adjust));
2047 memset(&tbl_entry, 0, sizeof(tbl_entry));
2048 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2049
2050 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2051
2052 set_default_colors(pipe_ctx);
2053 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2054 == true) {
2055 tbl_entry.color_space =
2056 pipe_ctx->stream->output_color_space;
2057
2058 for (i = 0; i < 12; i++)
2059 tbl_entry.regval[i] =
2060 pipe_ctx->stream->csc_color_matrix.matrix[i];
2061
2062 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2063 (pipe_ctx->plane_res.xfm, &tbl_entry);
2064 }
2065
2066 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2067 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2068 adjust.temperature_matrix[0] =
2069 pipe_ctx->stream->
2070 gamut_remap_matrix.matrix[0];
2071 adjust.temperature_matrix[1] =
2072 pipe_ctx->stream->
2073 gamut_remap_matrix.matrix[1];
2074 adjust.temperature_matrix[2] =
2075 pipe_ctx->stream->
2076 gamut_remap_matrix.matrix[2];
2077 adjust.temperature_matrix[3] =
2078 pipe_ctx->stream->
2079 gamut_remap_matrix.matrix[4];
2080 adjust.temperature_matrix[4] =
2081 pipe_ctx->stream->
2082 gamut_remap_matrix.matrix[5];
2083 adjust.temperature_matrix[5] =
2084 pipe_ctx->stream->
2085 gamut_remap_matrix.matrix[6];
2086 adjust.temperature_matrix[6] =
2087 pipe_ctx->stream->
2088 gamut_remap_matrix.matrix[8];
2089 adjust.temperature_matrix[7] =
2090 pipe_ctx->stream->
2091 gamut_remap_matrix.matrix[9];
2092 adjust.temperature_matrix[8] =
2093 pipe_ctx->stream->
2094 gamut_remap_matrix.matrix[10];
2095 }
2096
2097 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2098
2099 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2100 program_scaler(dc, pipe_ctx);
2101
2102 program_surface_visibility(dc, pipe_ctx);
2103
2104 mi->funcs->mem_input_program_surface_config(
2105 mi,
2106 plane_state->format,
2107 &plane_state->tiling_info,
2108 &plane_state->plane_size,
2109 plane_state->rotation,
2110 NULL,
2111 false);
2112 if (mi->funcs->set_blank)
2113 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2114
2115 if (dc->public.config.gpu_vm_support)
2116 mi->funcs->mem_input_program_pte_vm(
2117 pipe_ctx->plane_res.mi,
2118 plane_state->format,
2119 &plane_state->tiling_info,
2120 plane_state->rotation);
2121 }
2122
2123 static void update_plane_addr(const struct core_dc *dc,
2124 struct pipe_ctx *pipe_ctx)
2125 {
2126 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2127
2128 if (plane_state == NULL)
2129 return;
2130
2131 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2132 pipe_ctx->plane_res.mi,
2133 &plane_state->address,
2134 plane_state->flip_immediate);
2135
2136 plane_state->status.requested_address = plane_state->address;
2137 }
2138
2139 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2140 {
2141 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2142
2143 if (plane_state == NULL)
2144 return;
2145
2146 plane_state->status.is_flip_pending =
2147 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2148 pipe_ctx->plane_res.mi);
2149
2150 if (plane_state->status.is_flip_pending && !plane_state->visible)
2151 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2152
2153 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2154 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2155 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2156 plane_state->status.is_right_eye =\
2157 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2158 }
2159 }
2160
2161 void dce110_power_down(struct core_dc *dc)
2162 {
2163 power_down_all_hw_blocks(dc);
2164 disable_vga_and_power_gate_all_controllers(dc);
2165 }
2166
2167 static bool wait_for_reset_trigger_to_occur(
2168 struct dc_context *dc_ctx,
2169 struct timing_generator *tg)
2170 {
2171 bool rc = false;
2172
2173 /* To avoid endless loop we wait at most
2174 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2175 const uint32_t frames_to_wait_on_triggered_reset = 10;
2176 uint32_t i;
2177
2178 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2179
2180 if (!tg->funcs->is_counter_moving(tg)) {
2181 DC_ERROR("TG counter is not moving!\n");
2182 break;
2183 }
2184
2185 if (tg->funcs->did_triggered_reset_occur(tg)) {
2186 rc = true;
2187 /* usually occurs at i=1 */
2188 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2189 i);
2190 break;
2191 }
2192
2193 /* Wait for one frame. */
2194 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2195 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2196 }
2197
2198 if (false == rc)
2199 DC_ERROR("GSL: Timeout on reset trigger!\n");
2200
2201 return rc;
2202 }
2203
2204 /* Enable timing synchronization for a group of Timing Generators. */
2205 static void dce110_enable_timing_synchronization(
2206 struct core_dc *dc,
2207 int group_index,
2208 int group_size,
2209 struct pipe_ctx *grouped_pipes[])
2210 {
2211 struct dc_context *dc_ctx = dc->ctx;
2212 struct dcp_gsl_params gsl_params = { 0 };
2213 int i;
2214
2215 DC_SYNC_INFO("GSL: Setting-up...\n");
2216
2217 /* Designate a single TG in the group as a master.
2218 * Since HW doesn't care which one, we always assign
2219 * the 1st one in the group. */
2220 gsl_params.gsl_group = 0;
2221 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2222
2223 for (i = 0; i < group_size; i++)
2224 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2225 grouped_pipes[i]->stream_res.tg, &gsl_params);
2226
2227 /* Reset slave controllers on master VSync */
2228 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2229
2230 for (i = 1 /* skip the master */; i < group_size; i++)
2231 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2232 grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
2233
2234
2235
2236 for (i = 1 /* skip the master */; i < group_size; i++) {
2237 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2238 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2239 /* Regardless of success of the wait above, remove the reset or
2240 * the driver will start timing out on Display requests. */
2241 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2242 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
2243 }
2244
2245
2246 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2247 * is that the sync'ed displays will not drift out of sync over time*/
2248 DC_SYNC_INFO("GSL: Restoring register states.\n");
2249 for (i = 0; i < group_size; i++)
2250 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2251
2252 DC_SYNC_INFO("GSL: Set-up complete.\n");
2253 }
2254
2255 static void init_hw(struct core_dc *dc)
2256 {
2257 int i;
2258 struct dc_bios *bp;
2259 struct transform *xfm;
2260 struct abm *abm;
2261
2262 bp = dc->ctx->dc_bios;
2263 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2264 xfm = dc->res_pool->transforms[i];
2265 xfm->funcs->transform_reset(xfm);
2266
2267 dc->hwss.enable_display_power_gating(
2268 dc, i, bp,
2269 PIPE_GATING_CONTROL_INIT);
2270 dc->hwss.enable_display_power_gating(
2271 dc, i, bp,
2272 PIPE_GATING_CONTROL_DISABLE);
2273 dc->hwss.enable_display_pipe_clock_gating(
2274 dc->ctx,
2275 true);
2276 }
2277
2278 dce_clock_gating_power_up(dc->hwseq, false);
2279 /***************************************/
2280
2281 for (i = 0; i < dc->link_count; i++) {
2282 /****************************************/
2283 /* Power up AND update implementation according to the
2284 * required signal (which may be different from the
2285 * default signal on connector). */
2286 struct dc_link *link = dc->links[i];
2287 link->link_enc->funcs->hw_init(link->link_enc);
2288 }
2289
2290 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2291 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2292
2293 tg->funcs->disable_vga(tg);
2294
2295 /* Blank controller using driver code instead of
2296 * command table. */
2297 tg->funcs->set_blank(tg, true);
2298 hwss_wait_for_blank_complete(tg);
2299 }
2300
2301 for (i = 0; i < dc->res_pool->audio_count; i++) {
2302 struct audio *audio = dc->res_pool->audios[i];
2303 audio->funcs->hw_init(audio);
2304 }
2305
2306 abm = dc->res_pool->abm;
2307 if (abm != NULL) {
2308 abm->funcs->init_backlight(abm);
2309 abm->funcs->abm_init(abm);
2310 }
2311 #ifdef ENABLE_FBC
2312 if (dc->fbc_compressor)
2313 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2314 #endif
2315
2316 }
2317
2318 void dce110_fill_display_configs(
2319 const struct validate_context *context,
2320 struct dm_pp_display_configuration *pp_display_cfg)
2321 {
2322 int j;
2323 int num_cfgs = 0;
2324
2325 for (j = 0; j < context->stream_count; j++) {
2326 int k;
2327
2328 const struct dc_stream_state *stream = context->streams[j];
2329 struct dm_pp_single_disp_config *cfg =
2330 &pp_display_cfg->disp_configs[num_cfgs];
2331 const struct pipe_ctx *pipe_ctx = NULL;
2332
2333 for (k = 0; k < MAX_PIPES; k++)
2334 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2335 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2336 break;
2337 }
2338
2339 ASSERT(pipe_ctx != NULL);
2340
2341 num_cfgs++;
2342 cfg->signal = pipe_ctx->stream->signal;
2343 cfg->pipe_idx = pipe_ctx->pipe_idx;
2344 cfg->src_height = stream->src.height;
2345 cfg->src_width = stream->src.width;
2346 cfg->ddi_channel_mapping =
2347 stream->sink->link->ddi_channel_mapping.raw;
2348 cfg->transmitter =
2349 stream->sink->link->link_enc->transmitter;
2350 cfg->link_settings.lane_count =
2351 stream->sink->link->cur_link_settings.lane_count;
2352 cfg->link_settings.link_rate =
2353 stream->sink->link->cur_link_settings.link_rate;
2354 cfg->link_settings.link_spread =
2355 stream->sink->link->cur_link_settings.link_spread;
2356 cfg->sym_clock = stream->phy_pix_clk;
2357 /* Round v_refresh*/
2358 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2359 cfg->v_refresh /= stream->timing.h_total;
2360 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2361 / stream->timing.v_total;
2362 }
2363
2364 pp_display_cfg->display_count = num_cfgs;
2365 }
2366
2367 uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
2368 {
2369 uint8_t j;
2370 uint32_t min_vertical_blank_time = -1;
2371
2372 for (j = 0; j < context->stream_count; j++) {
2373 struct dc_stream_state *stream = context->streams[j];
2374 uint32_t vertical_blank_in_pixels = 0;
2375 uint32_t vertical_blank_time = 0;
2376
2377 vertical_blank_in_pixels = stream->timing.h_total *
2378 (stream->timing.v_total
2379 - stream->timing.v_addressable);
2380
2381 vertical_blank_time = vertical_blank_in_pixels
2382 * 1000 / stream->timing.pix_clk_khz;
2383
2384 if (min_vertical_blank_time > vertical_blank_time)
2385 min_vertical_blank_time = vertical_blank_time;
2386 }
2387
2388 return min_vertical_blank_time;
2389 }
2390
2391 static int determine_sclk_from_bounding_box(
2392 const struct core_dc *dc,
2393 int required_sclk)
2394 {
2395 int i;
2396
2397 /*
2398 * Some asics do not give us sclk levels, so we just report the actual
2399 * required sclk
2400 */
2401 if (dc->sclk_lvls.num_levels == 0)
2402 return required_sclk;
2403
2404 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2405 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2406 return dc->sclk_lvls.clocks_in_khz[i];
2407 }
2408 /*
2409 * even maximum level could not satisfy requirement, this
2410 * is unexpected at this stage, should have been caught at
2411 * validation time
2412 */
2413 ASSERT(0);
2414 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2415 }
2416
2417 static void pplib_apply_display_requirements(
2418 struct core_dc *dc,
2419 struct validate_context *context)
2420 {
2421 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2422
2423 pp_display_cfg->all_displays_in_sync =
2424 context->bw.dce.all_displays_in_sync;
2425 pp_display_cfg->nb_pstate_switch_disable =
2426 context->bw.dce.nbp_state_change_enable == false;
2427 pp_display_cfg->cpu_cc6_disable =
2428 context->bw.dce.cpuc_state_change_enable == false;
2429 pp_display_cfg->cpu_pstate_disable =
2430 context->bw.dce.cpup_state_change_enable == false;
2431 pp_display_cfg->cpu_pstate_separation_time =
2432 context->bw.dce.blackout_recovery_time_us;
2433
2434 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2435 / MEMORY_TYPE_MULTIPLIER;
2436
2437 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2438 dc,
2439 context->bw.dce.sclk_khz);
2440
2441 pp_display_cfg->min_engine_clock_deep_sleep_khz
2442 = context->bw.dce.sclk_deep_sleep_khz;
2443
2444 pp_display_cfg->avail_mclk_switch_time_us =
2445 dce110_get_min_vblank_time_us(context);
2446 /* TODO: dce11.2*/
2447 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2448
2449 pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2450
2451 dce110_fill_display_configs(context, pp_display_cfg);
2452
2453 /* TODO: is this still applicable?*/
2454 if (pp_display_cfg->display_count == 1) {
2455 const struct dc_crtc_timing *timing =
2456 &context->streams[0]->timing;
2457
2458 pp_display_cfg->crtc_index =
2459 pp_display_cfg->disp_configs[0].pipe_idx;
2460 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2461 / timing->pix_clk_khz;
2462 }
2463
2464 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2465 struct dm_pp_display_configuration)) != 0)
2466 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2467
2468 dc->prev_display_config = *pp_display_cfg;
2469 }
2470
2471 static void dce110_set_bandwidth(
2472 struct core_dc *dc,
2473 struct validate_context *context,
2474 bool decrease_allowed)
2475 {
2476 dce110_set_displaymarks(dc, context);
2477
2478 if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) {
2479 dc->res_pool->display_clock->funcs->set_clock(
2480 dc->res_pool->display_clock,
2481 context->bw.dce.dispclk_khz * 115 / 100);
2482 dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2483 }
2484
2485 pplib_apply_display_requirements(dc, context);
2486 }
2487
2488 static void dce110_program_front_end_for_pipe(
2489 struct core_dc *dc, struct pipe_ctx *pipe_ctx)
2490 {
2491 struct mem_input *mi = pipe_ctx->plane_res.mi;
2492 struct pipe_ctx *old_pipe = NULL;
2493 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2494 struct xfm_grph_csc_adjustment adjust;
2495 struct out_csc_color_matrix tbl_entry;
2496 unsigned int i;
2497
2498 memset(&tbl_entry, 0, sizeof(tbl_entry));
2499
2500 if (dc->current_context)
2501 old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2502
2503 memset(&adjust, 0, sizeof(adjust));
2504 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2505
2506 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2507
2508 set_default_colors(pipe_ctx);
2509 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2510 == true) {
2511 tbl_entry.color_space =
2512 pipe_ctx->stream->output_color_space;
2513
2514 for (i = 0; i < 12; i++)
2515 tbl_entry.regval[i] =
2516 pipe_ctx->stream->csc_color_matrix.matrix[i];
2517
2518 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2519 (pipe_ctx->plane_res.xfm, &tbl_entry);
2520 }
2521
2522 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2523 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2524 adjust.temperature_matrix[0] =
2525 pipe_ctx->stream->
2526 gamut_remap_matrix.matrix[0];
2527 adjust.temperature_matrix[1] =
2528 pipe_ctx->stream->
2529 gamut_remap_matrix.matrix[1];
2530 adjust.temperature_matrix[2] =
2531 pipe_ctx->stream->
2532 gamut_remap_matrix.matrix[2];
2533 adjust.temperature_matrix[3] =
2534 pipe_ctx->stream->
2535 gamut_remap_matrix.matrix[4];
2536 adjust.temperature_matrix[4] =
2537 pipe_ctx->stream->
2538 gamut_remap_matrix.matrix[5];
2539 adjust.temperature_matrix[5] =
2540 pipe_ctx->stream->
2541 gamut_remap_matrix.matrix[6];
2542 adjust.temperature_matrix[6] =
2543 pipe_ctx->stream->
2544 gamut_remap_matrix.matrix[8];
2545 adjust.temperature_matrix[7] =
2546 pipe_ctx->stream->
2547 gamut_remap_matrix.matrix[9];
2548 adjust.temperature_matrix[8] =
2549 pipe_ctx->stream->
2550 gamut_remap_matrix.matrix[10];
2551 }
2552
2553 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2554
2555 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2556
2557 program_scaler(dc, pipe_ctx);
2558
2559 mi->funcs->mem_input_program_surface_config(
2560 mi,
2561 plane_state->format,
2562 &plane_state->tiling_info,
2563 &plane_state->plane_size,
2564 plane_state->rotation,
2565 NULL,
2566 false);
2567 if (mi->funcs->set_blank)
2568 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2569
2570 if (dc->public.config.gpu_vm_support)
2571 mi->funcs->mem_input_program_pte_vm(
2572 pipe_ctx->plane_res.mi,
2573 plane_state->format,
2574 &plane_state->tiling_info,
2575 plane_state->rotation);
2576
2577 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2578 "Pipe:%d 0x%x: addr hi:0x%x, "
2579 "addr low:0x%x, "
2580 "src: %d, %d, %d,"
2581 " %d; dst: %d, %d, %d, %d;"
2582 "clip: %d, %d, %d, %d\n",
2583 pipe_ctx->pipe_idx,
2584 pipe_ctx->plane_state,
2585 pipe_ctx->plane_state->address.grph.addr.high_part,
2586 pipe_ctx->plane_state->address.grph.addr.low_part,
2587 pipe_ctx->plane_state->src_rect.x,
2588 pipe_ctx->plane_state->src_rect.y,
2589 pipe_ctx->plane_state->src_rect.width,
2590 pipe_ctx->plane_state->src_rect.height,
2591 pipe_ctx->plane_state->dst_rect.x,
2592 pipe_ctx->plane_state->dst_rect.y,
2593 pipe_ctx->plane_state->dst_rect.width,
2594 pipe_ctx->plane_state->dst_rect.height,
2595 pipe_ctx->plane_state->clip_rect.x,
2596 pipe_ctx->plane_state->clip_rect.y,
2597 pipe_ctx->plane_state->clip_rect.width,
2598 pipe_ctx->plane_state->clip_rect.height);
2599
2600 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2601 "Pipe %d: width, height, x, y\n"
2602 "viewport:%d, %d, %d, %d\n"
2603 "recout: %d, %d, %d, %d\n",
2604 pipe_ctx->pipe_idx,
2605 pipe_ctx->plane_res.scl_data.viewport.width,
2606 pipe_ctx->plane_res.scl_data.viewport.height,
2607 pipe_ctx->plane_res.scl_data.viewport.x,
2608 pipe_ctx->plane_res.scl_data.viewport.y,
2609 pipe_ctx->plane_res.scl_data.recout.width,
2610 pipe_ctx->plane_res.scl_data.recout.height,
2611 pipe_ctx->plane_res.scl_data.recout.x,
2612 pipe_ctx->plane_res.scl_data.recout.y);
2613 }
2614
2615 static void dce110_apply_ctx_for_surface(
2616 struct core_dc *dc,
2617 const struct dc_plane_state *plane_state,
2618 struct validate_context *context)
2619 {
2620 int i;
2621
2622 if (!plane_state)
2623 return;
2624
2625 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2626 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2627
2628 if (pipe_ctx->plane_state != plane_state)
2629 continue;
2630
2631 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2632 program_surface_visibility(dc, pipe_ctx);
2633
2634 }
2635 }
2636
2637 static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
2638 {
2639 /* Do not power down fe when stream is active on dce*/
2640 if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream)
2641 return;
2642
2643 dc->hwss.enable_display_power_gating(
2644 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2645
2646 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2647 dc->res_pool->transforms[fe_idx]);
2648 }
2649
2650 static void dce110_wait_for_mpcc_disconnect(
2651 struct core_dc *dc,
2652 struct resource_pool *res_pool,
2653 struct pipe_ctx *pipe_ctx)
2654 {
2655 /* do nothing*/
2656 }
2657
2658 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2659 enum dc_color_space colorspace,
2660 uint16_t *matrix)
2661 {
2662 int i;
2663 struct out_csc_color_matrix tbl_entry;
2664
2665 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2666 == true) {
2667 enum dc_color_space color_space =
2668 pipe_ctx->stream->output_color_space;
2669
2670 //uint16_t matrix[12];
2671 for (i = 0; i < 12; i++)
2672 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2673
2674 tbl_entry.color_space = color_space;
2675 //tbl_entry.regval = matrix;
2676 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2677 }
2678 }
2679
2680 static const struct hw_sequencer_funcs dce110_funcs = {
2681 .program_gamut_remap = program_gamut_remap,
2682 .program_csc_matrix = program_csc_matrix,
2683 .init_hw = init_hw,
2684 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2685 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2686 .set_plane_config = set_plane_config,
2687 .update_plane_addr = update_plane_addr,
2688 .update_pending_status = dce110_update_pending_status,
2689 .set_input_transfer_func = dce110_set_input_transfer_func,
2690 .set_output_transfer_func = dce110_set_output_transfer_func,
2691 .power_down = dce110_power_down,
2692 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2693 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2694 .update_info_frame = dce110_update_info_frame,
2695 .enable_stream = dce110_enable_stream,
2696 .disable_stream = dce110_disable_stream,
2697 .unblank_stream = dce110_unblank_stream,
2698 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2699 .enable_display_power_gating = dce110_enable_display_power_gating,
2700 .power_down_front_end = dce110_power_down_fe,
2701 .pipe_control_lock = dce_pipe_control_lock,
2702 .set_bandwidth = dce110_set_bandwidth,
2703 .set_drr = set_drr,
2704 .get_position = get_position,
2705 .set_static_screen_control = set_static_screen_control,
2706 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2707 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
2708 .setup_stereo = NULL,
2709 .set_avmute = dce110_set_avmute,
2710 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect
2711 };
2712
2713 bool dce110_hw_sequencer_construct(struct core_dc *dc)
2714 {
2715 dc->hwss = dce110_funcs;
2716
2717 return true;
2718 }
2719
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