2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
37 #include "dce110_compressor.h"
40 #include "bios/bios_parser_helper.h"
41 #include "timing_generator.h"
42 #include "mem_input.h"
45 #include "transform.h"
46 #include "stream_encoder.h"
47 #include "link_encoder.h"
48 #include "clock_source.h"
51 #include "dce/dce_hwseq.h"
52 #include "reg_helper.h"
54 /* include DCE11 register header files */
55 #include "dce/dce_11_0_d.h"
56 #include "dce/dce_11_0_sh_mask.h"
57 #include "custom_float.h"
59 struct dce110_hw_seq_reg_offsets
{
63 static const struct dce110_hw_seq_reg_offsets reg_offsets
[] = {
65 .crtc
= (mmCRTC0_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
68 .crtc
= (mmCRTC1_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
71 .crtc
= (mmCRTC2_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
74 .crtc
= (mmCRTCV_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
78 #define HW_REG_BLND(reg, id)\
79 (reg + reg_offsets[id].blnd)
81 #define HW_REG_CRTC(reg, id)\
82 (reg + reg_offsets[id].crtc)
84 #define MAX_WATERMARK 0xFFFF
85 #define SAFE_NBP_MARK 0x7FFF
87 /*******************************************************************************
89 ******************************************************************************/
90 /***************************PIPE_CONTROL***********************************/
91 static void dce110_init_pte(struct dc_context
*ctx
)
95 uint32_t chunk_int
= 0;
96 uint32_t chunk_mul
= 0;
98 addr
= mmUNP_DVMM_PTE_CONTROL
;
99 value
= dm_read_reg(ctx
, addr
);
105 DVMM_USE_SINGLE_PTE
);
111 DVMM_PTE_BUFFER_MODE0
);
117 DVMM_PTE_BUFFER_MODE1
);
119 dm_write_reg(ctx
, addr
, value
);
121 addr
= mmDVMM_PTE_REQ
;
122 value
= dm_read_reg(ctx
, addr
);
124 chunk_int
= get_reg_field_value(
127 HFLIP_PTEREQ_PER_CHUNK_INT
);
129 chunk_mul
= get_reg_field_value(
132 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER
);
134 if (chunk_int
!= 0x4 || chunk_mul
!= 0x4) {
140 MAX_PTEREQ_TO_ISSUE
);
146 HFLIP_PTEREQ_PER_CHUNK_INT
);
152 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER
);
154 dm_write_reg(ctx
, addr
, value
);
157 /**************************************************************************/
159 static void enable_display_pipe_clock_gating(
160 struct dc_context
*ctx
,
166 static bool dce110_enable_display_power_gating(
168 uint8_t controller_id
,
170 enum pipe_gating_control power_gating
)
172 enum bp_result bp_result
= BP_RESULT_OK
;
173 enum bp_pipe_control_action cntl
;
174 struct dc_context
*ctx
= dc
->ctx
;
175 unsigned int underlay_idx
= dc
->res_pool
->underlay_pipe_index
;
177 if (IS_FPGA_MAXIMUS_DC(ctx
->dce_environment
))
180 if (power_gating
== PIPE_GATING_CONTROL_INIT
)
181 cntl
= ASIC_PIPE_INIT
;
182 else if (power_gating
== PIPE_GATING_CONTROL_ENABLE
)
183 cntl
= ASIC_PIPE_ENABLE
;
185 cntl
= ASIC_PIPE_DISABLE
;
187 if (controller_id
== underlay_idx
)
188 controller_id
= CONTROLLER_ID_UNDERLAY0
- 1;
190 if (power_gating
!= PIPE_GATING_CONTROL_INIT
|| controller_id
== 0){
192 bp_result
= dcb
->funcs
->enable_disp_power_gating(
193 dcb
, controller_id
+ 1, cntl
);
195 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
196 * by default when command table is called
198 * Bios parser accepts controller_id = 6 as indicative of
199 * underlay pipe in dce110. But we do not support more
202 if (controller_id
< CONTROLLER_ID_MAX
- 1)
204 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE
, controller_id
),
208 if (power_gating
!= PIPE_GATING_CONTROL_ENABLE
)
209 dce110_init_pte(ctx
);
211 if (bp_result
== BP_RESULT_OK
)
217 static void build_prescale_params(struct ipp_prescale_params
*prescale_params
,
218 const struct dc_plane_state
*plane_state
)
220 prescale_params
->mode
= IPP_PRESCALE_MODE_FIXED_UNSIGNED
;
222 switch (plane_state
->format
) {
223 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
:
224 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
:
225 prescale_params
->scale
= 0x2020;
227 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
:
228 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
:
229 prescale_params
->scale
= 0x2008;
231 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
:
232 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
:
233 prescale_params
->scale
= 0x2000;
241 static bool dce110_set_input_transfer_func(
242 struct pipe_ctx
*pipe_ctx
,
243 const struct dc_plane_state
*plane_state
)
245 struct input_pixel_processor
*ipp
= pipe_ctx
->plane_res
.ipp
;
246 const struct dc_transfer_func
*tf
= NULL
;
247 struct ipp_prescale_params prescale_params
= { 0 };
253 if (plane_state
->in_transfer_func
)
254 tf
= plane_state
->in_transfer_func
;
256 build_prescale_params(&prescale_params
, plane_state
);
257 ipp
->funcs
->ipp_program_prescale(ipp
, &prescale_params
);
259 if (plane_state
->gamma_correction
&& dce_use_lut(plane_state
))
260 ipp
->funcs
->ipp_program_input_lut(ipp
, plane_state
->gamma_correction
);
263 /* Default case if no input transfer function specified */
264 ipp
->funcs
->ipp_set_degamma(ipp
,
265 IPP_DEGAMMA_MODE_HW_sRGB
);
266 } else if (tf
->type
== TF_TYPE_PREDEFINED
) {
268 case TRANSFER_FUNCTION_SRGB
:
269 ipp
->funcs
->ipp_set_degamma(ipp
,
270 IPP_DEGAMMA_MODE_HW_sRGB
);
272 case TRANSFER_FUNCTION_BT709
:
273 ipp
->funcs
->ipp_set_degamma(ipp
,
274 IPP_DEGAMMA_MODE_HW_xvYCC
);
276 case TRANSFER_FUNCTION_LINEAR
:
277 ipp
->funcs
->ipp_set_degamma(ipp
,
278 IPP_DEGAMMA_MODE_BYPASS
);
280 case TRANSFER_FUNCTION_PQ
:
287 } else if (tf
->type
== TF_TYPE_BYPASS
) {
288 ipp
->funcs
->ipp_set_degamma(ipp
, IPP_DEGAMMA_MODE_BYPASS
);
290 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
297 static bool convert_to_custom_float(
298 struct pwl_result_data
*rgb_resulted
,
299 struct curve_points
*arr_points
,
300 uint32_t hw_points_num
)
302 struct custom_float_format fmt
;
304 struct pwl_result_data
*rgb
= rgb_resulted
;
308 fmt
.exponenta_bits
= 6;
309 fmt
.mantissa_bits
= 12;
312 if (!convert_to_custom_float_format(
315 &arr_points
[0].custom_float_x
)) {
320 if (!convert_to_custom_float_format(
321 arr_points
[0].offset
,
323 &arr_points
[0].custom_float_offset
)) {
328 if (!convert_to_custom_float_format(
331 &arr_points
[0].custom_float_slope
)) {
336 fmt
.mantissa_bits
= 10;
339 if (!convert_to_custom_float_format(
342 &arr_points
[1].custom_float_x
)) {
347 if (!convert_to_custom_float_format(
350 &arr_points
[1].custom_float_y
)) {
355 if (!convert_to_custom_float_format(
358 &arr_points
[2].custom_float_slope
)) {
363 fmt
.mantissa_bits
= 12;
366 while (i
!= hw_points_num
) {
367 if (!convert_to_custom_float_format(
375 if (!convert_to_custom_float_format(
383 if (!convert_to_custom_float_format(
391 if (!convert_to_custom_float_format(
394 &rgb
->delta_red_reg
)) {
399 if (!convert_to_custom_float_format(
402 &rgb
->delta_green_reg
)) {
407 if (!convert_to_custom_float_format(
410 &rgb
->delta_blue_reg
)) {
422 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
423 *output_tf
, struct pwl_params
*regamma_params
)
425 struct curve_points
*arr_points
;
426 struct pwl_result_data
*rgb_resulted
;
427 struct pwl_result_data
*rgb
;
428 struct pwl_result_data
*rgb_plus_1
;
429 struct fixed31_32 y_r
;
430 struct fixed31_32 y_g
;
431 struct fixed31_32 y_b
;
432 struct fixed31_32 y1_min
;
433 struct fixed31_32 y3_max
;
435 int32_t segment_start
, segment_end
;
436 uint32_t i
, j
, k
, seg_distr
[16], increment
, start_index
, hw_points
;
438 if (output_tf
== NULL
|| regamma_params
== NULL
||
439 output_tf
->type
== TF_TYPE_BYPASS
)
442 arr_points
= regamma_params
->arr_points
;
443 rgb_resulted
= regamma_params
->rgb_resulted
;
446 memset(regamma_params
, 0, sizeof(struct pwl_params
));
448 if (output_tf
->tf
== TRANSFER_FUNCTION_PQ
) {
450 * segments are from 2^-11 to 2^5
474 * segment is from 2^-10 to 2^0
497 for (k
= 0; k
< 16; k
++) {
498 if (seg_distr
[k
] != -1)
499 hw_points
+= (1 << seg_distr
[k
]);
503 for (k
= 0; k
< (segment_end
- segment_start
); k
++) {
504 increment
= 32 / (1 << seg_distr
[k
]);
505 start_index
= (segment_start
+ k
+ 25) * 32;
506 for (i
= start_index
; i
< start_index
+ 32; i
+= increment
) {
507 if (j
== hw_points
- 1)
509 rgb_resulted
[j
].red
= output_tf
->tf_pts
.red
[i
];
510 rgb_resulted
[j
].green
= output_tf
->tf_pts
.green
[i
];
511 rgb_resulted
[j
].blue
= output_tf
->tf_pts
.blue
[i
];
517 start_index
= (segment_end
+ 25) * 32;
518 rgb_resulted
[hw_points
- 1].red
=
519 output_tf
->tf_pts
.red
[start_index
];
520 rgb_resulted
[hw_points
- 1].green
=
521 output_tf
->tf_pts
.green
[start_index
];
522 rgb_resulted
[hw_points
- 1].blue
=
523 output_tf
->tf_pts
.blue
[start_index
];
525 arr_points
[0].x
= dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
526 dal_fixed31_32_from_int(segment_start
));
527 arr_points
[1].x
= dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
528 dal_fixed31_32_from_int(segment_end
));
529 arr_points
[2].x
= dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
530 dal_fixed31_32_from_int(segment_end
));
532 y_r
= rgb_resulted
[0].red
;
533 y_g
= rgb_resulted
[0].green
;
534 y_b
= rgb_resulted
[0].blue
;
536 y1_min
= dal_fixed31_32_min(y_r
, dal_fixed31_32_min(y_g
, y_b
));
538 arr_points
[0].y
= y1_min
;
539 arr_points
[0].slope
= dal_fixed31_32_div(
543 y_r
= rgb_resulted
[hw_points
- 1].red
;
544 y_g
= rgb_resulted
[hw_points
- 1].green
;
545 y_b
= rgb_resulted
[hw_points
- 1].blue
;
547 /* see comment above, m_arrPoints[1].y should be the Y value for the
548 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
550 y3_max
= dal_fixed31_32_max(y_r
, dal_fixed31_32_max(y_g
, y_b
));
552 arr_points
[1].y
= y3_max
;
553 arr_points
[2].y
= y3_max
;
555 arr_points
[1].slope
= dal_fixed31_32_zero
;
556 arr_points
[2].slope
= dal_fixed31_32_zero
;
558 if (output_tf
->tf
== TRANSFER_FUNCTION_PQ
) {
559 /* for PQ, we want to have a straight line from last HW X point,
560 * and the slope to be such that we hit 1.0 at 10000 nits.
562 const struct fixed31_32 end_value
=
563 dal_fixed31_32_from_int(125);
565 arr_points
[1].slope
= dal_fixed31_32_div(
566 dal_fixed31_32_sub(dal_fixed31_32_one
, arr_points
[1].y
),
567 dal_fixed31_32_sub(end_value
, arr_points
[1].x
));
568 arr_points
[2].slope
= dal_fixed31_32_div(
569 dal_fixed31_32_sub(dal_fixed31_32_one
, arr_points
[1].y
),
570 dal_fixed31_32_sub(end_value
, arr_points
[1].x
));
573 regamma_params
->hw_points_num
= hw_points
;
576 for (k
= 0; k
< 16 && i
< 16; k
++) {
577 if (seg_distr
[k
] != -1) {
578 regamma_params
->arr_curve_points
[k
].segments_num
=
580 regamma_params
->arr_curve_points
[i
].offset
=
581 regamma_params
->arr_curve_points
[k
].
582 offset
+ (1 << seg_distr
[k
]);
587 if (seg_distr
[k
] != -1)
588 regamma_params
->arr_curve_points
[k
].segments_num
=
592 rgb_plus_1
= rgb_resulted
+ 1;
596 while (i
!= hw_points
+ 1) {
597 if (dal_fixed31_32_lt(rgb_plus_1
->red
, rgb
->red
))
598 rgb_plus_1
->red
= rgb
->red
;
599 if (dal_fixed31_32_lt(rgb_plus_1
->green
, rgb
->green
))
600 rgb_plus_1
->green
= rgb
->green
;
601 if (dal_fixed31_32_lt(rgb_plus_1
->blue
, rgb
->blue
))
602 rgb_plus_1
->blue
= rgb
->blue
;
604 rgb
->delta_red
= dal_fixed31_32_sub(
607 rgb
->delta_green
= dal_fixed31_32_sub(
610 rgb
->delta_blue
= dal_fixed31_32_sub(
619 convert_to_custom_float(rgb_resulted
, arr_points
, hw_points
);
624 static bool dce110_set_output_transfer_func(
625 struct pipe_ctx
*pipe_ctx
,
626 const struct dc_stream_state
*stream
)
628 struct transform
*xfm
= pipe_ctx
->plane_res
.xfm
;
630 xfm
->funcs
->opp_power_on_regamma_lut(xfm
, true);
631 xfm
->regamma_params
.hw_points_num
= GAMMA_HW_POINTS_NUM
;
633 if (stream
->out_transfer_func
&&
634 stream
->out_transfer_func
->type
==
635 TF_TYPE_PREDEFINED
&&
636 stream
->out_transfer_func
->tf
==
637 TRANSFER_FUNCTION_SRGB
) {
638 xfm
->funcs
->opp_set_regamma_mode(xfm
, OPP_REGAMMA_SRGB
);
639 } else if (dce110_translate_regamma_to_hw_format(
640 stream
->out_transfer_func
, &xfm
->regamma_params
)) {
641 xfm
->funcs
->opp_program_regamma_pwl(xfm
, &xfm
->regamma_params
);
642 xfm
->funcs
->opp_set_regamma_mode(xfm
, OPP_REGAMMA_USER
);
644 xfm
->funcs
->opp_set_regamma_mode(xfm
, OPP_REGAMMA_BYPASS
);
647 xfm
->funcs
->opp_power_on_regamma_lut(xfm
, false);
652 static enum dc_status
bios_parser_crtc_source_select(
653 struct pipe_ctx
*pipe_ctx
)
656 /* call VBIOS table to set CRTC source for the HW
658 * note: video bios clears all FMT setting here. */
659 struct bp_crtc_source_select crtc_source_select
= {0};
660 const struct dc_sink
*sink
= pipe_ctx
->stream
->sink
;
662 crtc_source_select
.engine_id
= pipe_ctx
->stream_enc
->id
;
663 crtc_source_select
.controller_id
= pipe_ctx
->pipe_idx
+ 1;
664 /*TODO: Need to un-hardcode color depth, dp_audio and account for
665 * the case where signal and sink signal is different (translator
667 crtc_source_select
.signal
= pipe_ctx
->stream
->signal
;
668 crtc_source_select
.enable_dp_audio
= false;
669 crtc_source_select
.sink_signal
= pipe_ctx
->stream
->signal
;
670 crtc_source_select
.display_output_bit_depth
= PANEL_8BIT_COLOR
;
672 dcb
= sink
->ctx
->dc_bios
;
674 if (BP_RESULT_OK
!= dcb
->funcs
->crtc_source_select(
676 &crtc_source_select
)) {
677 return DC_ERROR_UNEXPECTED
;
683 void dce110_update_info_frame(struct pipe_ctx
*pipe_ctx
)
685 ASSERT(pipe_ctx
->stream
);
687 if (pipe_ctx
->stream_enc
== NULL
)
688 return; /* this is not root pipe */
690 if (dc_is_hdmi_signal(pipe_ctx
->stream
->signal
))
691 pipe_ctx
->stream_enc
->funcs
->update_hdmi_info_packets(
692 pipe_ctx
->stream_enc
,
693 &pipe_ctx
->encoder_info_frame
);
694 else if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
695 pipe_ctx
->stream_enc
->funcs
->update_dp_info_packets(
696 pipe_ctx
->stream_enc
,
697 &pipe_ctx
->encoder_info_frame
);
700 void dce110_enable_stream(struct pipe_ctx
*pipe_ctx
)
702 enum dc_lane_count lane_count
=
703 pipe_ctx
->stream
->sink
->link
->cur_link_settings
.lane_count
;
705 struct dc_crtc_timing
*timing
= &pipe_ctx
->stream
->timing
;
706 struct dc_link
*link
= pipe_ctx
->stream
->sink
->link
;
708 /* 1. update AVI info frame (HDMI, DP)
709 * we always need to update info frame
711 uint32_t active_total_with_borders
;
712 uint32_t early_control
= 0;
713 struct timing_generator
*tg
= pipe_ctx
->tg
;
715 /* TODOFPGA may change to hwss.update_info_frame */
716 dce110_update_info_frame(pipe_ctx
);
717 /* enable early control to avoid corruption on DP monitor*/
718 active_total_with_borders
=
719 timing
->h_addressable
720 + timing
->h_border_left
721 + timing
->h_border_right
;
724 early_control
= active_total_with_borders
% lane_count
;
726 if (early_control
== 0)
727 early_control
= lane_count
;
729 tg
->funcs
->set_early_control(tg
, early_control
);
731 /* enable audio only within mode set */
732 if (pipe_ctx
->audio
!= NULL
) {
733 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
734 pipe_ctx
->stream_enc
->funcs
->dp_audio_enable(pipe_ctx
->stream_enc
);
737 /* For MST, there are multiply stream go to only one link.
738 * connect DIG back_end to front_end while enable_stream and
739 * disconnect them during disable_stream
740 * BY this, it is logic clean to separate stream and link */
741 link
->link_enc
->funcs
->connect_dig_be_to_fe(link
->link_enc
,
742 pipe_ctx
->stream_enc
->id
, true);
746 void dce110_disable_stream(struct pipe_ctx
*pipe_ctx
)
748 struct dc_stream_state
*stream
= pipe_ctx
->stream
;
749 struct dc_link
*link
= stream
->sink
->link
;
751 if (pipe_ctx
->audio
) {
752 pipe_ctx
->audio
->funcs
->az_disable(pipe_ctx
->audio
);
754 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
755 pipe_ctx
->stream_enc
->funcs
->dp_audio_disable(
756 pipe_ctx
->stream_enc
);
758 pipe_ctx
->stream_enc
->funcs
->hdmi_audio_disable(
759 pipe_ctx
->stream_enc
);
761 pipe_ctx
->audio
= NULL
;
763 /* TODO: notify audio driver for if audio modes list changed
764 * add audio mode list change flag */
765 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
766 * stream->stream_engine_id);
770 if (dc_is_hdmi_signal(pipe_ctx
->stream
->signal
))
771 pipe_ctx
->stream_enc
->funcs
->stop_hdmi_info_packets(
772 pipe_ctx
->stream_enc
);
774 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
775 pipe_ctx
->stream_enc
->funcs
->stop_dp_info_packets(
776 pipe_ctx
->stream_enc
);
778 pipe_ctx
->stream_enc
->funcs
->audio_mute_control(
779 pipe_ctx
->stream_enc
, true);
782 /* blank at encoder level */
783 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
784 pipe_ctx
->stream_enc
->funcs
->dp_blank(pipe_ctx
->stream_enc
);
786 link
->link_enc
->funcs
->connect_dig_be_to_fe(
788 pipe_ctx
->stream_enc
->id
,
793 void dce110_unblank_stream(struct pipe_ctx
*pipe_ctx
,
794 struct dc_link_settings
*link_settings
)
796 struct encoder_unblank_param params
= { { 0 } };
798 /* only 3 items below are used by unblank */
799 params
.pixel_clk_khz
=
800 pipe_ctx
->stream
->timing
.pix_clk_khz
;
801 params
.link_settings
.link_rate
= link_settings
->link_rate
;
802 pipe_ctx
->stream_enc
->funcs
->dp_unblank(pipe_ctx
->stream_enc
, ¶ms
);
806 void dce110_set_avmute(struct pipe_ctx
*pipe_ctx
, bool enable
)
808 if (pipe_ctx
!= NULL
&& pipe_ctx
->stream_enc
!= NULL
)
809 pipe_ctx
->stream_enc
->funcs
->set_avmute(pipe_ctx
->stream_enc
, enable
);
812 static enum audio_dto_source
translate_to_dto_source(enum controller_id crtc_id
)
815 case CONTROLLER_ID_D0
:
816 return DTO_SOURCE_ID0
;
817 case CONTROLLER_ID_D1
:
818 return DTO_SOURCE_ID1
;
819 case CONTROLLER_ID_D2
:
820 return DTO_SOURCE_ID2
;
821 case CONTROLLER_ID_D3
:
822 return DTO_SOURCE_ID3
;
823 case CONTROLLER_ID_D4
:
824 return DTO_SOURCE_ID4
;
825 case CONTROLLER_ID_D5
:
826 return DTO_SOURCE_ID5
;
828 return DTO_SOURCE_UNKNOWN
;
832 static void build_audio_output(
833 const struct pipe_ctx
*pipe_ctx
,
834 struct audio_output
*audio_output
)
836 const struct dc_stream_state
*stream
= pipe_ctx
->stream
;
837 audio_output
->engine_id
= pipe_ctx
->stream_enc
->id
;
839 audio_output
->signal
= pipe_ctx
->stream
->signal
;
841 /* audio_crtc_info */
843 audio_output
->crtc_info
.h_total
=
844 stream
->timing
.h_total
;
847 * Audio packets are sent during actual CRTC blank physical signal, we
848 * need to specify actual active signal portion
850 audio_output
->crtc_info
.h_active
=
851 stream
->timing
.h_addressable
852 + stream
->timing
.h_border_left
853 + stream
->timing
.h_border_right
;
855 audio_output
->crtc_info
.v_active
=
856 stream
->timing
.v_addressable
857 + stream
->timing
.v_border_top
858 + stream
->timing
.v_border_bottom
;
860 audio_output
->crtc_info
.pixel_repetition
= 1;
862 audio_output
->crtc_info
.interlaced
=
863 stream
->timing
.flags
.INTERLACE
;
865 audio_output
->crtc_info
.refresh_rate
=
866 (stream
->timing
.pix_clk_khz
*1000)/
867 (stream
->timing
.h_total
*stream
->timing
.v_total
);
869 audio_output
->crtc_info
.color_depth
=
870 stream
->timing
.display_color_depth
;
872 audio_output
->crtc_info
.requested_pixel_clock
=
873 pipe_ctx
->pix_clk_params
.requested_pix_clk
;
875 audio_output
->crtc_info
.calculated_pixel_clock
=
876 pipe_ctx
->pix_clk_params
.requested_pix_clk
;
878 /*for HDMI, audio ACR is with deep color ratio factor*/
879 if (dc_is_hdmi_signal(pipe_ctx
->stream
->signal
) &&
880 audio_output
->crtc_info
.requested_pixel_clock
==
881 stream
->timing
.pix_clk_khz
) {
882 if (pipe_ctx
->pix_clk_params
.pixel_encoding
== PIXEL_ENCODING_YCBCR420
) {
883 audio_output
->crtc_info
.requested_pixel_clock
=
884 audio_output
->crtc_info
.requested_pixel_clock
/2;
885 audio_output
->crtc_info
.calculated_pixel_clock
=
886 pipe_ctx
->pix_clk_params
.requested_pix_clk
/2;
891 if (pipe_ctx
->stream
->signal
== SIGNAL_TYPE_DISPLAY_PORT
||
892 pipe_ctx
->stream
->signal
== SIGNAL_TYPE_DISPLAY_PORT_MST
) {
893 audio_output
->pll_info
.dp_dto_source_clock_in_khz
=
894 pipe_ctx
->dis_clk
->funcs
->get_dp_ref_clk_frequency(
898 audio_output
->pll_info
.feed_back_divider
=
899 pipe_ctx
->pll_settings
.feedback_divider
;
901 audio_output
->pll_info
.dto_source
=
902 translate_to_dto_source(
903 pipe_ctx
->pipe_idx
+ 1);
905 /* TODO hard code to enable for now. Need get from stream */
906 audio_output
->pll_info
.ss_enabled
= true;
908 audio_output
->pll_info
.ss_percentage
=
909 pipe_ctx
->pll_settings
.ss_percentage
;
912 static void get_surface_visual_confirm_color(const struct pipe_ctx
*pipe_ctx
,
913 struct tg_color
*color
)
915 uint32_t color_value
= MAX_TG_COLOR_VALUE
* (4 - pipe_ctx
->pipe_idx
) / 4;
917 switch (pipe_ctx
->plane_res
.scl_data
.format
) {
918 case PIXEL_FORMAT_ARGB8888
:
919 /* set boarder color to red */
920 color
->color_r_cr
= color_value
;
923 case PIXEL_FORMAT_ARGB2101010
:
924 /* set boarder color to blue */
925 color
->color_b_cb
= color_value
;
927 case PIXEL_FORMAT_420BPP8
:
928 /* set boarder color to green */
929 color
->color_g_y
= color_value
;
931 case PIXEL_FORMAT_420BPP10
:
932 /* set boarder color to yellow */
933 color
->color_g_y
= color_value
;
934 color
->color_r_cr
= color_value
;
936 case PIXEL_FORMAT_FP16
:
937 /* set boarder color to white */
938 color
->color_r_cr
= color_value
;
939 color
->color_b_cb
= color_value
;
940 color
->color_g_y
= color_value
;
947 static void program_scaler(const struct core_dc
*dc
,
948 const struct pipe_ctx
*pipe_ctx
)
950 struct tg_color color
= {0};
952 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
954 if (pipe_ctx
->plane_res
.xfm
->funcs
->transform_set_pixel_storage_depth
== NULL
)
958 if (dc
->public.debug
.surface_visual_confirm
)
959 get_surface_visual_confirm_color(pipe_ctx
, &color
);
961 color_space_to_black_color(dc
,
962 pipe_ctx
->stream
->output_color_space
,
965 pipe_ctx
->plane_res
.xfm
->funcs
->transform_set_pixel_storage_depth(
966 pipe_ctx
->plane_res
.xfm
,
967 pipe_ctx
->plane_res
.scl_data
.lb_params
.depth
,
968 &pipe_ctx
->stream
->bit_depth_params
);
970 if (pipe_ctx
->tg
->funcs
->set_overscan_blank_color
)
971 pipe_ctx
->tg
->funcs
->set_overscan_blank_color(
975 pipe_ctx
->plane_res
.xfm
->funcs
->transform_set_scaler(pipe_ctx
->plane_res
.xfm
,
976 &pipe_ctx
->plane_res
.scl_data
);
979 static enum dc_status
dce110_prog_pixclk_crtc_otg(
980 struct pipe_ctx
*pipe_ctx
,
981 struct validate_context
*context
,
984 struct dc_stream_state
*stream
= pipe_ctx
->stream
;
985 struct pipe_ctx
*pipe_ctx_old
= &dc
->current_context
->res_ctx
.
986 pipe_ctx
[pipe_ctx
->pipe_idx
];
987 struct tg_color black_color
= {0};
989 if (!pipe_ctx_old
->stream
) {
991 /* program blank color */
992 color_space_to_black_color(dc
,
993 stream
->output_color_space
, &black_color
);
994 pipe_ctx
->tg
->funcs
->set_blank_color(
999 * Must blank CRTC after disabling power gating and before any
1000 * programming, otherwise CRTC will be hung in bad state
1002 pipe_ctx
->tg
->funcs
->set_blank(pipe_ctx
->tg
, true);
1004 if (false == pipe_ctx
->clock_source
->funcs
->program_pix_clk(
1005 pipe_ctx
->clock_source
,
1006 &pipe_ctx
->pix_clk_params
,
1007 &pipe_ctx
->pll_settings
)) {
1008 BREAK_TO_DEBUGGER();
1009 return DC_ERROR_UNEXPECTED
;
1012 pipe_ctx
->tg
->funcs
->program_timing(
1017 pipe_ctx
->tg
->funcs
->set_static_screen_control(
1022 if (!pipe_ctx_old
->stream
) {
1023 if (false == pipe_ctx
->tg
->funcs
->enable_crtc(
1025 BREAK_TO_DEBUGGER();
1026 return DC_ERROR_UNEXPECTED
;
1035 static enum dc_status
apply_single_controller_ctx_to_hw(
1036 struct pipe_ctx
*pipe_ctx
,
1037 struct validate_context
*context
,
1040 struct dc_stream_state
*stream
= pipe_ctx
->stream
;
1041 struct pipe_ctx
*pipe_ctx_old
= &dc
->current_context
->res_ctx
.
1042 pipe_ctx
[pipe_ctx
->pipe_idx
];
1045 dc
->hwss
.prog_pixclk_crtc_otg(pipe_ctx
, context
, dc
);
1047 pipe_ctx
->stream_res
.opp
->funcs
->opp_set_dyn_expansion(
1048 pipe_ctx
->stream_res
.opp
,
1049 COLOR_SPACE_YCBCR601
,
1050 stream
->timing
.display_color_depth
,
1051 pipe_ctx
->stream
->signal
);
1053 /* FPGA does not program backend */
1054 if (IS_FPGA_MAXIMUS_DC(dc
->ctx
->dce_environment
)) {
1055 pipe_ctx
->stream_res
.opp
->funcs
->opp_program_fmt(
1056 pipe_ctx
->stream_res
.opp
,
1057 &stream
->bit_depth_params
,
1061 /* TODO: move to stream encoder */
1062 if (pipe_ctx
->stream
->signal
!= SIGNAL_TYPE_VIRTUAL
)
1063 if (DC_OK
!= bios_parser_crtc_source_select(pipe_ctx
)) {
1064 BREAK_TO_DEBUGGER();
1065 return DC_ERROR_UNEXPECTED
;
1068 if (pipe_ctx
->stream
->signal
!= SIGNAL_TYPE_VIRTUAL
)
1069 stream
->sink
->link
->link_enc
->funcs
->setup(
1070 stream
->sink
->link
->link_enc
,
1071 pipe_ctx
->stream
->signal
);
1073 if (pipe_ctx
->stream
->signal
!= SIGNAL_TYPE_VIRTUAL
)
1074 pipe_ctx
->stream_enc
->funcs
->setup_stereo_sync(
1075 pipe_ctx
->stream_enc
,
1077 stream
->timing
.timing_3d_format
!= TIMING_3D_FORMAT_NONE
);
1080 /*vbios crtc_source_selection and encoder_setup will override fmt_C*/
1081 pipe_ctx
->stream_res
.opp
->funcs
->opp_program_fmt(
1082 pipe_ctx
->stream_res
.opp
,
1083 &stream
->bit_depth_params
,
1086 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
1087 pipe_ctx
->stream_enc
->funcs
->dp_set_stream_attribute(
1088 pipe_ctx
->stream_enc
,
1090 stream
->output_color_space
);
1092 if (dc_is_hdmi_signal(pipe_ctx
->stream
->signal
))
1093 pipe_ctx
->stream_enc
->funcs
->hdmi_set_stream_attribute(
1094 pipe_ctx
->stream_enc
,
1096 stream
->phy_pix_clk
,
1097 pipe_ctx
->audio
!= NULL
);
1099 if (dc_is_dvi_signal(pipe_ctx
->stream
->signal
))
1100 pipe_ctx
->stream_enc
->funcs
->dvi_set_stream_attribute(
1101 pipe_ctx
->stream_enc
,
1103 (pipe_ctx
->stream
->signal
== SIGNAL_TYPE_DVI_DUAL_LINK
) ?
1106 resource_build_info_frame(pipe_ctx
);
1107 dce110_update_info_frame(pipe_ctx
);
1108 if (!pipe_ctx_old
->stream
) {
1109 core_link_enable_stream(pipe_ctx
);
1112 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
1113 dce110_unblank_stream(pipe_ctx
,
1114 &stream
->sink
->link
->cur_link_settings
);
1117 pipe_ctx
->plane_res
.scl_data
.lb_params
.alpha_en
= pipe_ctx
->bottom_pipe
!= 0;
1118 /* program_scaler and allocate_mem_input are not new asic */
1119 if ((!pipe_ctx_old
||
1120 memcmp(&pipe_ctx_old
->plane_res
.scl_data
, &pipe_ctx
->plane_res
.scl_data
,
1121 sizeof(struct scaler_data
)) != 0) &&
1122 pipe_ctx
->plane_state
) {
1123 program_scaler(dc
, pipe_ctx
);
1126 /* mst support - use total stream count */
1127 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1128 if (pipe_ctx
->plane_res
.mi
->funcs
->allocate_mem_input
!= NULL
)
1130 pipe_ctx
->plane_res
.mi
->funcs
->allocate_mem_input(
1131 pipe_ctx
->plane_res
.mi
,
1132 stream
->timing
.h_total
,
1133 stream
->timing
.v_total
,
1134 stream
->timing
.pix_clk_khz
,
1135 context
->stream_count
);
1137 pipe_ctx
->stream
->sink
->link
->psr_enabled
= false;
1142 /******************************************************************************/
1144 static void power_down_encoders(struct core_dc
*dc
)
1148 for (i
= 0; i
< dc
->link_count
; i
++) {
1149 dc
->links
[i
]->link_enc
->funcs
->disable_output(
1150 dc
->links
[i
]->link_enc
, SIGNAL_TYPE_NONE
);
1154 static void power_down_controllers(struct core_dc
*dc
)
1158 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
1159 dc
->res_pool
->timing_generators
[i
]->funcs
->disable_crtc(
1160 dc
->res_pool
->timing_generators
[i
]);
1164 static void power_down_clock_sources(struct core_dc
*dc
)
1168 if (dc
->res_pool
->dp_clock_source
->funcs
->cs_power_down(
1169 dc
->res_pool
->dp_clock_source
) == false)
1170 dm_error("Failed to power down pll! (dp clk src)\n");
1172 for (i
= 0; i
< dc
->res_pool
->clk_src_count
; i
++) {
1173 if (dc
->res_pool
->clock_sources
[i
]->funcs
->cs_power_down(
1174 dc
->res_pool
->clock_sources
[i
]) == false)
1175 dm_error("Failed to power down pll! (clk src index=%d)\n", i
);
1179 static void power_down_all_hw_blocks(struct core_dc
*dc
)
1181 power_down_encoders(dc
);
1183 power_down_controllers(dc
);
1185 power_down_clock_sources(dc
);
1188 if (dc
->fbc_compressor
)
1189 dc
->fbc_compressor
->funcs
->disable_fbc(dc
->fbc_compressor
);
1193 static void disable_vga_and_power_gate_all_controllers(
1197 struct timing_generator
*tg
;
1198 struct dc_context
*ctx
= dc
->ctx
;
1200 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
1201 tg
= dc
->res_pool
->timing_generators
[i
];
1203 if (tg
->funcs
->disable_vga
)
1204 tg
->funcs
->disable_vga(tg
);
1206 /* Enable CLOCK gating for each pipe BEFORE controller
1208 enable_display_pipe_clock_gating(ctx
,
1211 dc
->hwss
.power_down_front_end(dc
, i
);
1216 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1217 * 1. Power down all DC HW blocks
1218 * 2. Disable VGA engine on all controllers
1219 * 3. Enable power gating for controller
1220 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1222 void dce110_enable_accelerated_mode(struct core_dc
*dc
)
1224 power_down_all_hw_blocks(dc
);
1226 disable_vga_and_power_gate_all_controllers(dc
);
1227 bios_set_scratch_acc_mode_change(dc
->ctx
->dc_bios
);
1230 static uint32_t compute_pstate_blackout_duration(
1231 struct bw_fixed blackout_duration
,
1232 const struct dc_stream_state
*stream
)
1234 uint32_t total_dest_line_time_ns
;
1235 uint32_t pstate_blackout_duration_ns
;
1237 pstate_blackout_duration_ns
= 1000 * blackout_duration
.value
>> 24;
1239 total_dest_line_time_ns
= 1000000UL *
1240 stream
->timing
.h_total
/
1241 stream
->timing
.pix_clk_khz
+
1242 pstate_blackout_duration_ns
;
1244 return total_dest_line_time_ns
;
1247 void dce110_set_displaymarks(
1248 const struct core_dc
*dc
,
1249 struct validate_context
*context
)
1251 uint8_t i
, num_pipes
;
1252 unsigned int underlay_idx
= dc
->res_pool
->underlay_pipe_index
;
1254 for (i
= 0, num_pipes
= 0; i
< MAX_PIPES
; i
++) {
1255 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1256 uint32_t total_dest_line_time_ns
;
1258 if (pipe_ctx
->stream
== NULL
)
1261 total_dest_line_time_ns
= compute_pstate_blackout_duration(
1262 dc
->bw_vbios
.blackout_duration
, pipe_ctx
->stream
);
1263 pipe_ctx
->plane_res
.mi
->funcs
->mem_input_program_display_marks(
1264 pipe_ctx
->plane_res
.mi
,
1265 context
->bw
.dce
.nbp_state_change_wm_ns
[num_pipes
],
1266 context
->bw
.dce
.stutter_exit_wm_ns
[num_pipes
],
1267 context
->bw
.dce
.urgent_wm_ns
[num_pipes
],
1268 total_dest_line_time_ns
);
1269 if (i
== underlay_idx
) {
1271 pipe_ctx
->plane_res
.mi
->funcs
->mem_input_program_chroma_display_marks(
1272 pipe_ctx
->plane_res
.mi
,
1273 context
->bw
.dce
.nbp_state_change_wm_ns
[num_pipes
],
1274 context
->bw
.dce
.stutter_exit_wm_ns
[num_pipes
],
1275 context
->bw
.dce
.urgent_wm_ns
[num_pipes
],
1276 total_dest_line_time_ns
);
1282 static void set_safe_displaymarks(
1283 struct resource_context
*res_ctx
,
1284 const struct resource_pool
*pool
)
1287 int underlay_idx
= pool
->underlay_pipe_index
;
1288 struct dce_watermarks max_marks
= {
1289 MAX_WATERMARK
, MAX_WATERMARK
, MAX_WATERMARK
, MAX_WATERMARK
};
1290 struct dce_watermarks nbp_marks
= {
1291 SAFE_NBP_MARK
, SAFE_NBP_MARK
, SAFE_NBP_MARK
, SAFE_NBP_MARK
};
1293 for (i
= 0; i
< MAX_PIPES
; i
++) {
1294 if (res_ctx
->pipe_ctx
[i
].stream
== NULL
)
1297 res_ctx
->pipe_ctx
[i
].plane_res
.mi
->funcs
->mem_input_program_display_marks(
1298 res_ctx
->pipe_ctx
[i
].plane_res
.mi
,
1303 if (i
== underlay_idx
)
1304 res_ctx
->pipe_ctx
[i
].plane_res
.mi
->funcs
->mem_input_program_chroma_display_marks(
1305 res_ctx
->pipe_ctx
[i
].plane_res
.mi
,
1313 static void switch_dp_clock_sources(
1314 const struct core_dc
*dc
,
1315 struct resource_context
*res_ctx
)
1318 for (i
= 0; i
< MAX_PIPES
; i
++) {
1319 struct pipe_ctx
*pipe_ctx
= &res_ctx
->pipe_ctx
[i
];
1321 if (pipe_ctx
->stream
== NULL
|| pipe_ctx
->top_pipe
)
1324 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
)) {
1325 struct clock_source
*clk_src
=
1326 resource_find_used_clk_src_for_sharing(
1330 clk_src
!= pipe_ctx
->clock_source
) {
1331 resource_unreference_clock_source(
1332 res_ctx
, dc
->res_pool
,
1333 &pipe_ctx
->clock_source
);
1334 pipe_ctx
->clock_source
= clk_src
;
1335 resource_reference_clock_source(
1336 res_ctx
, dc
->res_pool
, clk_src
);
1338 dce_crtc_switch_to_clk_src(dc
->hwseq
, clk_src
, i
);
1344 /*******************************************************************************
1346 ******************************************************************************/
1348 static void set_drr(struct pipe_ctx
**pipe_ctx
,
1349 int num_pipes
, int vmin
, int vmax
)
1352 struct drr_params params
= {0};
1354 params
.vertical_total_max
= vmax
;
1355 params
.vertical_total_min
= vmin
;
1357 /* TODO: If multiple pipes are to be supported, you need
1361 for (i
= 0; i
< num_pipes
; i
++) {
1362 pipe_ctx
[i
]->tg
->funcs
->set_drr(pipe_ctx
[i
]->tg
, ¶ms
);
1366 static void get_position(struct pipe_ctx
**pipe_ctx
,
1368 struct crtc_position
*position
)
1372 /* TODO: handle pipes > 1
1374 for (i
= 0; i
< num_pipes
; i
++)
1375 pipe_ctx
[i
]->tg
->funcs
->get_position(pipe_ctx
[i
]->tg
, position
);
1378 static void set_static_screen_control(struct pipe_ctx
**pipe_ctx
,
1379 int num_pipes
, const struct dc_static_screen_events
*events
)
1382 unsigned int value
= 0;
1384 if (events
->overlay_update
)
1386 if (events
->surface_update
)
1388 if (events
->cursor_update
)
1395 for (i
= 0; i
< num_pipes
; i
++)
1396 pipe_ctx
[i
]->tg
->funcs
->
1397 set_static_screen_control(pipe_ctx
[i
]->tg
, value
);
1400 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1401 * may not be programmed yet.
1402 * TODO: after mode set, pre_mode_set = false,
1403 * may read PLL register to get pixel clock
1405 static uint32_t get_max_pixel_clock_for_all_paths(
1407 struct validate_context
*context
,
1410 uint32_t max_pix_clk
= 0;
1413 if (!pre_mode_set
) {
1414 /* TODO: read ASIC register to get pixel clock */
1418 for (i
= 0; i
< MAX_PIPES
; i
++) {
1419 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1421 if (pipe_ctx
->stream
== NULL
)
1424 /* do not check under lay */
1425 if (pipe_ctx
->top_pipe
)
1428 if (pipe_ctx
->pix_clk_params
.requested_pix_clk
> max_pix_clk
)
1430 pipe_ctx
->pix_clk_params
.requested_pix_clk
;
1433 if (max_pix_clk
== 0)
1439 /* Find clock state based on clock requested. if clock value is 0, simply
1440 * set clock state as requested without finding clock state by clock value
1441 *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock.
1443 * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value
1444 * etc support for dcn1.0
1446 static void apply_min_clocks(
1448 struct validate_context
*context
,
1449 enum dm_pp_clocks_state
*clocks_state
,
1452 struct state_dependent_clocks req_clocks
= {0};
1453 struct pipe_ctx
*pipe_ctx
;
1456 for (i
= 0; i
< MAX_PIPES
; i
++) {
1457 pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1458 if (pipe_ctx
->dis_clk
!= NULL
)
1462 if (!pre_mode_set
) {
1463 /* set clock_state without verification */
1464 if (pipe_ctx
->dis_clk
->funcs
->set_min_clocks_state
) {
1465 pipe_ctx
->dis_clk
->funcs
->set_min_clocks_state(
1466 pipe_ctx
->dis_clk
, *clocks_state
);
1470 /* TODO: This is incorrect. Figure out how to fix. */
1471 pipe_ctx
->dis_clk
->funcs
->apply_clock_voltage_request(
1473 DM_PP_CLOCK_TYPE_DISPLAY_CLK
,
1474 pipe_ctx
->dis_clk
->cur_clocks_value
.dispclk_in_khz
,
1478 pipe_ctx
->dis_clk
->funcs
->apply_clock_voltage_request(
1480 DM_PP_CLOCK_TYPE_PIXELCLK
,
1481 pipe_ctx
->dis_clk
->cur_clocks_value
.max_pixelclk_in_khz
,
1485 pipe_ctx
->dis_clk
->funcs
->apply_clock_voltage_request(
1487 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
,
1488 pipe_ctx
->dis_clk
->cur_clocks_value
.max_non_dp_phyclk_in_khz
,
1494 /* get the required state based on state dependent clocks:
1495 * display clock and pixel clock
1497 req_clocks
.display_clk_khz
= context
->bw
.dce
.dispclk_khz
;
1499 req_clocks
.pixel_clk_khz
= get_max_pixel_clock_for_all_paths(
1502 if (pipe_ctx
->dis_clk
->funcs
->get_required_clocks_state
) {
1503 *clocks_state
= pipe_ctx
->dis_clk
->funcs
->get_required_clocks_state(
1504 pipe_ctx
->dis_clk
, &req_clocks
);
1505 pipe_ctx
->dis_clk
->funcs
->set_min_clocks_state(
1506 pipe_ctx
->dis_clk
, *clocks_state
);
1508 pipe_ctx
->dis_clk
->funcs
->apply_clock_voltage_request(
1510 DM_PP_CLOCK_TYPE_DISPLAY_CLK
,
1511 req_clocks
.display_clk_khz
,
1515 pipe_ctx
->dis_clk
->funcs
->apply_clock_voltage_request(
1517 DM_PP_CLOCK_TYPE_PIXELCLK
,
1518 req_clocks
.pixel_clk_khz
,
1522 pipe_ctx
->dis_clk
->funcs
->apply_clock_voltage_request(
1524 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
,
1525 req_clocks
.pixel_clk_khz
,
1534 * Check if FBC can be enabled
1536 static enum dc_status
validate_fbc(struct core_dc
*dc
,
1537 struct validate_context
*context
)
1539 struct pipe_ctx
*pipe_ctx
=
1540 &context
->res_ctx
.pipe_ctx
[0];
1542 ASSERT(dc
->fbc_compressor
);
1544 /* FBC memory should be allocated */
1545 if (!dc
->ctx
->fbc_gpu_addr
)
1546 return DC_ERROR_UNEXPECTED
;
1548 /* Only supports single display */
1549 if (context
->stream_count
!= 1)
1550 return DC_ERROR_UNEXPECTED
;
1552 /* Only supports eDP */
1553 if (pipe_ctx
->stream
->sink
->link
->connector_signal
!= SIGNAL_TYPE_EDP
)
1554 return DC_ERROR_UNEXPECTED
;
1556 /* PSR should not be enabled */
1557 if (pipe_ctx
->stream
->sink
->link
->psr_enabled
)
1558 return DC_ERROR_UNEXPECTED
;
1566 static enum dc_status
enable_fbc(struct core_dc
*dc
,
1567 struct validate_context
*context
)
1569 enum dc_status status
= validate_fbc(dc
, context
);
1571 if (status
== DC_OK
) {
1572 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1573 struct compr_addr_and_pitch_params params
= {0, 0, 0};
1574 struct compressor
*compr
= dc
->fbc_compressor
;
1575 struct pipe_ctx
*pipe_ctx
=
1576 &context
->res_ctx
.pipe_ctx
[0];
1578 params
.source_view_width
=
1579 pipe_ctx
->stream
->timing
.h_addressable
;
1580 params
.source_view_height
=
1581 pipe_ctx
->stream
->timing
.v_addressable
;
1583 compr
->compr_surface_address
.quad_part
= dc
->ctx
->fbc_gpu_addr
;
1585 compr
->funcs
->surface_address_and_pitch(compr
, ¶ms
);
1586 compr
->funcs
->set_fbc_invalidation_triggers(compr
, 1);
1588 compr
->funcs
->enable_fbc(compr
, ¶ms
);
1594 static enum dc_status
apply_ctx_to_hw_fpga(
1596 struct validate_context
*context
)
1598 enum dc_status status
= DC_ERROR_UNEXPECTED
;
1601 for (i
= 0; i
< MAX_PIPES
; i
++) {
1602 struct pipe_ctx
*pipe_ctx_old
=
1603 &dc
->current_context
->res_ctx
.pipe_ctx
[i
];
1604 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1606 if (pipe_ctx
->stream
== NULL
)
1609 if (pipe_ctx
->stream
== pipe_ctx_old
->stream
)
1612 status
= apply_single_controller_ctx_to_hw(
1617 if (status
!= DC_OK
)
1624 static void dce110_reset_hw_ctx_wrap(
1626 struct validate_context
*context
)
1630 /* Reset old context */
1631 /* look up the targets that have been removed since last commit */
1632 for (i
= 0; i
< MAX_PIPES
; i
++) {
1633 struct pipe_ctx
*pipe_ctx_old
=
1634 &dc
->current_context
->res_ctx
.pipe_ctx
[i
];
1635 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1637 /* Note: We need to disable output if clock sources change,
1638 * since bios does optimization and doesn't apply if changing
1639 * PHY when not already disabled.
1642 /* Skip underlay pipe since it will be handled in commit surface*/
1643 if (!pipe_ctx_old
->stream
|| pipe_ctx_old
->top_pipe
)
1646 if (!pipe_ctx
->stream
||
1647 pipe_need_reprogram(pipe_ctx_old
, pipe_ctx
)) {
1648 core_link_disable_stream(pipe_ctx_old
);
1649 pipe_ctx_old
->tg
->funcs
->set_blank(pipe_ctx_old
->tg
, true);
1650 if (!hwss_wait_for_blank_complete(pipe_ctx_old
->tg
)) {
1651 dm_error("DC: failed to blank crtc!\n");
1652 BREAK_TO_DEBUGGER();
1654 pipe_ctx_old
->tg
->funcs
->disable_crtc(pipe_ctx_old
->tg
);
1655 pipe_ctx_old
->plane_res
.mi
->funcs
->free_mem_input(
1656 pipe_ctx_old
->plane_res
.mi
, dc
->current_context
->stream_count
);
1657 resource_unreference_clock_source(
1658 &dc
->current_context
->res_ctx
, dc
->res_pool
,
1659 &pipe_ctx_old
->clock_source
);
1661 dc
->hwss
.power_down_front_end(dc
, pipe_ctx_old
->pipe_idx
);
1663 pipe_ctx_old
->stream
= NULL
;
1669 enum dc_status
dce110_apply_ctx_to_hw(
1671 struct validate_context
*context
)
1673 struct dc_bios
*dcb
= dc
->ctx
->dc_bios
;
1674 enum dc_status status
;
1676 enum dm_pp_clocks_state clocks_state
= DM_PP_CLOCKS_STATE_INVALID
;
1678 /* Reset old context */
1679 /* look up the targets that have been removed since last commit */
1680 dc
->hwss
.reset_hw_ctx_wrap(dc
, context
);
1682 /* Skip applying if no targets */
1683 if (context
->stream_count
<= 0)
1686 if (IS_FPGA_MAXIMUS_DC(dc
->ctx
->dce_environment
)) {
1687 apply_ctx_to_hw_fpga(dc
, context
);
1691 /* Apply new context */
1692 dcb
->funcs
->set_scratch_critical_state(dcb
, true);
1694 /* below is for real asic only */
1695 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
1696 struct pipe_ctx
*pipe_ctx_old
=
1697 &dc
->current_context
->res_ctx
.pipe_ctx
[i
];
1698 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1700 if (pipe_ctx
->stream
== NULL
|| pipe_ctx
->top_pipe
)
1703 if (pipe_ctx
->stream
== pipe_ctx_old
->stream
) {
1704 if (pipe_ctx_old
->clock_source
!= pipe_ctx
->clock_source
)
1705 dce_crtc_switch_to_clk_src(dc
->hwseq
,
1706 pipe_ctx
->clock_source
, i
);
1710 dc
->hwss
.enable_display_power_gating(
1711 dc
, i
, dc
->ctx
->dc_bios
,
1712 PIPE_GATING_CONTROL_DISABLE
);
1715 set_safe_displaymarks(&context
->res_ctx
, dc
->res_pool
);
1718 if (dc
->fbc_compressor
)
1719 dc
->fbc_compressor
->funcs
->disable_fbc(dc
->fbc_compressor
);
1721 /*TODO: when pplib works*/
1722 apply_min_clocks(dc
, context
, &clocks_state
, true);
1724 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1725 if (dc
->ctx
->dce_version
>= DCN_VERSION_1_0
) {
1726 if (context
->bw
.dcn
.calc_clk
.fclk_khz
1727 > dc
->current_context
->bw
.dcn
.cur_clk
.fclk_khz
) {
1728 struct dm_pp_clock_for_voltage_req clock
;
1730 clock
.clk_type
= DM_PP_CLOCK_TYPE_FCLK
;
1731 clock
.clocks_in_khz
= context
->bw
.dcn
.calc_clk
.fclk_khz
;
1732 dm_pp_apply_clock_for_voltage_request(dc
->ctx
, &clock
);
1733 dc
->current_context
->bw
.dcn
.cur_clk
.fclk_khz
= clock
.clocks_in_khz
;
1734 context
->bw
.dcn
.cur_clk
.fclk_khz
= clock
.clocks_in_khz
;
1736 if (context
->bw
.dcn
.calc_clk
.dcfclk_khz
1737 > dc
->current_context
->bw
.dcn
.cur_clk
.dcfclk_khz
) {
1738 struct dm_pp_clock_for_voltage_req clock
;
1740 clock
.clk_type
= DM_PP_CLOCK_TYPE_DCFCLK
;
1741 clock
.clocks_in_khz
= context
->bw
.dcn
.calc_clk
.dcfclk_khz
;
1742 dm_pp_apply_clock_for_voltage_request(dc
->ctx
, &clock
);
1743 dc
->current_context
->bw
.dcn
.cur_clk
.dcfclk_khz
= clock
.clocks_in_khz
;
1744 context
->bw
.dcn
.cur_clk
.dcfclk_khz
= clock
.clocks_in_khz
;
1746 if (context
->bw
.dcn
.calc_clk
.dispclk_khz
1747 > dc
->current_context
->bw
.dcn
.cur_clk
.dispclk_khz
) {
1748 dc
->res_pool
->display_clock
->funcs
->set_clock(
1749 dc
->res_pool
->display_clock
,
1750 context
->bw
.dcn
.calc_clk
.dispclk_khz
);
1751 dc
->current_context
->bw
.dcn
.cur_clk
.dispclk_khz
=
1752 context
->bw
.dcn
.calc_clk
.dispclk_khz
;
1753 context
->bw
.dcn
.cur_clk
.dispclk_khz
=
1754 context
->bw
.dcn
.calc_clk
.dispclk_khz
;
1758 if (context
->bw
.dce
.dispclk_khz
1759 > dc
->current_context
->bw
.dce
.dispclk_khz
) {
1760 dc
->res_pool
->display_clock
->funcs
->set_clock(
1761 dc
->res_pool
->display_clock
,
1762 context
->bw
.dce
.dispclk_khz
* 115 / 100);
1764 /* program audio wall clock. use HDMI as clock source if HDMI
1765 * audio active. Otherwise, use DP as clock source
1766 * first, loop to find any HDMI audio, if not, loop find DP audio
1768 /* Setup audio rate clock source */
1770 * Audio lag happened on DP monitor when unplug a HDMI monitor
1773 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1774 * is set to either dto0 or dto1, audio should work fine.
1775 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1776 * set to dto0 will cause audio lag.
1779 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1780 * find first available pipe with audio, setup audio wall DTO per topology
1781 * instead of per pipe.
1783 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
1784 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1786 if (pipe_ctx
->stream
== NULL
)
1789 if (pipe_ctx
->top_pipe
)
1792 if (pipe_ctx
->stream
->signal
!= SIGNAL_TYPE_HDMI_TYPE_A
)
1795 if (pipe_ctx
->audio
!= NULL
) {
1796 struct audio_output audio_output
;
1798 build_audio_output(pipe_ctx
, &audio_output
);
1800 pipe_ctx
->audio
->funcs
->wall_dto_setup(
1802 pipe_ctx
->stream
->signal
,
1803 &audio_output
.crtc_info
,
1804 &audio_output
.pll_info
);
1809 /* no HDMI audio is found, try DP audio */
1810 if (i
== dc
->res_pool
->pipe_count
) {
1811 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
1812 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1814 if (pipe_ctx
->stream
== NULL
)
1817 if (pipe_ctx
->top_pipe
)
1820 if (!dc_is_dp_signal(pipe_ctx
->stream
->signal
))
1823 if (pipe_ctx
->audio
!= NULL
) {
1824 struct audio_output audio_output
;
1826 build_audio_output(pipe_ctx
, &audio_output
);
1828 pipe_ctx
->audio
->funcs
->wall_dto_setup(
1830 pipe_ctx
->stream
->signal
,
1831 &audio_output
.crtc_info
,
1832 &audio_output
.pll_info
);
1838 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
1839 struct pipe_ctx
*pipe_ctx_old
=
1840 &dc
->current_context
->res_ctx
.pipe_ctx
[i
];
1841 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
1843 if (pipe_ctx
->stream
== NULL
)
1846 if (pipe_ctx
->stream
== pipe_ctx_old
->stream
)
1849 if (pipe_ctx
->stream
&& pipe_ctx_old
->stream
1850 && !pipe_need_reprogram(pipe_ctx_old
, pipe_ctx
))
1853 if (pipe_ctx
->top_pipe
)
1856 if (context
->res_ctx
.pipe_ctx
[i
].audio
!= NULL
) {
1858 struct audio_output audio_output
;
1860 build_audio_output(pipe_ctx
, &audio_output
);
1862 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
))
1863 pipe_ctx
->stream_enc
->funcs
->dp_audio_setup(
1864 pipe_ctx
->stream_enc
,
1865 pipe_ctx
->audio
->inst
,
1866 &pipe_ctx
->stream
->audio_info
);
1868 pipe_ctx
->stream_enc
->funcs
->hdmi_audio_setup(
1869 pipe_ctx
->stream_enc
,
1870 pipe_ctx
->audio
->inst
,
1871 &pipe_ctx
->stream
->audio_info
,
1872 &audio_output
.crtc_info
);
1874 pipe_ctx
->audio
->funcs
->az_configure(
1876 pipe_ctx
->stream
->signal
,
1877 &audio_output
.crtc_info
,
1878 &pipe_ctx
->stream
->audio_info
);
1881 status
= apply_single_controller_ctx_to_hw(
1886 if (dc
->hwss
.power_on_front_end
)
1887 dc
->hwss
.power_on_front_end(dc
, pipe_ctx
, context
);
1889 if (DC_OK
!= status
)
1893 dc
->hwss
.set_bandwidth(dc
, context
, true);
1896 apply_min_clocks(dc
, context
, &clocks_state
, false);
1898 dcb
->funcs
->set_scratch_critical_state(dcb
, false);
1900 switch_dp_clock_sources(dc
, &context
->res_ctx
);
1903 if (dc
->fbc_compressor
)
1904 enable_fbc(dc
, context
);
1911 /*******************************************************************************
1912 * Front End programming
1913 ******************************************************************************/
1914 static void set_default_colors(struct pipe_ctx
*pipe_ctx
)
1916 struct default_adjustment default_adjust
= { 0 };
1918 default_adjust
.force_hw_default
= false;
1919 if (pipe_ctx
->plane_state
== NULL
)
1920 default_adjust
.in_color_space
= COLOR_SPACE_SRGB
;
1922 default_adjust
.in_color_space
=
1923 pipe_ctx
->plane_state
->color_space
;
1924 if (pipe_ctx
->stream
== NULL
)
1925 default_adjust
.out_color_space
= COLOR_SPACE_SRGB
;
1927 default_adjust
.out_color_space
=
1928 pipe_ctx
->stream
->output_color_space
;
1929 default_adjust
.csc_adjust_type
= GRAPHICS_CSC_ADJUST_TYPE_SW
;
1930 default_adjust
.surface_pixel_format
= pipe_ctx
->plane_res
.scl_data
.format
;
1932 /* display color depth */
1933 default_adjust
.color_depth
=
1934 pipe_ctx
->stream
->timing
.display_color_depth
;
1936 /* Lb color depth */
1937 default_adjust
.lb_color_depth
= pipe_ctx
->plane_res
.scl_data
.lb_params
.depth
;
1939 pipe_ctx
->plane_res
.xfm
->funcs
->opp_set_csc_default(
1940 pipe_ctx
->plane_res
.xfm
, &default_adjust
);
1944 /*******************************************************************************
1945 * In order to turn on/off specific surface we will program
1948 * In case that we have two surfaces and they have a different visibility
1949 * we can't turn off the CRTC since it will turn off the entire display
1951 * |----------------------------------------------- |
1952 * |bottom pipe|curr pipe | | |
1953 * |Surface |Surface | Blender | CRCT |
1954 * |visibility |visibility | Configuration| |
1955 * |------------------------------------------------|
1956 * | off | off | CURRENT_PIPE | blank |
1957 * | off | on | CURRENT_PIPE | unblank |
1958 * | on | off | OTHER_PIPE | unblank |
1959 * | on | on | BLENDING | unblank |
1960 * -------------------------------------------------|
1962 ******************************************************************************/
1963 static void program_surface_visibility(const struct core_dc
*dc
,
1964 struct pipe_ctx
*pipe_ctx
)
1966 enum blnd_mode blender_mode
= BLND_MODE_CURRENT_PIPE
;
1967 bool blank_target
= false;
1969 if (pipe_ctx
->bottom_pipe
) {
1971 /* For now we are supporting only two pipes */
1972 ASSERT(pipe_ctx
->bottom_pipe
->bottom_pipe
== NULL
);
1974 if (pipe_ctx
->bottom_pipe
->plane_state
->visible
) {
1975 if (pipe_ctx
->plane_state
->visible
)
1976 blender_mode
= BLND_MODE_BLENDING
;
1978 blender_mode
= BLND_MODE_OTHER_PIPE
;
1980 } else if (!pipe_ctx
->plane_state
->visible
)
1981 blank_target
= true;
1983 } else if (!pipe_ctx
->plane_state
->visible
)
1984 blank_target
= true;
1986 dce_set_blender_mode(dc
->hwseq
, pipe_ctx
->pipe_idx
, blender_mode
);
1987 pipe_ctx
->tg
->funcs
->set_blank(pipe_ctx
->tg
, blank_target
);
1991 static void program_gamut_remap(struct pipe_ctx
*pipe_ctx
)
1993 struct xfm_grph_csc_adjustment adjust
;
1994 memset(&adjust
, 0, sizeof(adjust
));
1995 adjust
.gamut_adjust_type
= GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS
;
1998 if (pipe_ctx
->stream
->gamut_remap_matrix
.enable_remap
== true) {
1999 adjust
.gamut_adjust_type
= GRAPHICS_GAMUT_ADJUST_TYPE_SW
;
2000 adjust
.temperature_matrix
[0] =
2002 gamut_remap_matrix
.matrix
[0];
2003 adjust
.temperature_matrix
[1] =
2005 gamut_remap_matrix
.matrix
[1];
2006 adjust
.temperature_matrix
[2] =
2008 gamut_remap_matrix
.matrix
[2];
2009 adjust
.temperature_matrix
[3] =
2011 gamut_remap_matrix
.matrix
[4];
2012 adjust
.temperature_matrix
[4] =
2014 gamut_remap_matrix
.matrix
[5];
2015 adjust
.temperature_matrix
[5] =
2017 gamut_remap_matrix
.matrix
[6];
2018 adjust
.temperature_matrix
[6] =
2020 gamut_remap_matrix
.matrix
[8];
2021 adjust
.temperature_matrix
[7] =
2023 gamut_remap_matrix
.matrix
[9];
2024 adjust
.temperature_matrix
[8] =
2026 gamut_remap_matrix
.matrix
[10];
2029 pipe_ctx
->plane_res
.xfm
->funcs
->transform_set_gamut_remap(pipe_ctx
->plane_res
.xfm
, &adjust
);
2033 * TODO REMOVE, USE UPDATE INSTEAD
2035 static void set_plane_config(
2036 const struct core_dc
*dc
,
2037 struct pipe_ctx
*pipe_ctx
,
2038 struct resource_context
*res_ctx
)
2040 struct mem_input
*mi
= pipe_ctx
->plane_res
.mi
;
2041 struct dc_plane_state
*plane_state
= pipe_ctx
->plane_state
;
2042 struct xfm_grph_csc_adjustment adjust
;
2043 struct out_csc_color_matrix tbl_entry
;
2046 memset(&adjust
, 0, sizeof(adjust
));
2047 memset(&tbl_entry
, 0, sizeof(tbl_entry
));
2048 adjust
.gamut_adjust_type
= GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS
;
2050 dce_enable_fe_clock(dc
->hwseq
, pipe_ctx
->pipe_idx
, true);
2052 set_default_colors(pipe_ctx
);
2053 if (pipe_ctx
->stream
->csc_color_matrix
.enable_adjustment
2055 tbl_entry
.color_space
=
2056 pipe_ctx
->stream
->output_color_space
;
2058 for (i
= 0; i
< 12; i
++)
2059 tbl_entry
.regval
[i
] =
2060 pipe_ctx
->stream
->csc_color_matrix
.matrix
[i
];
2062 pipe_ctx
->plane_res
.xfm
->funcs
->opp_set_csc_adjustment
2063 (pipe_ctx
->plane_res
.xfm
, &tbl_entry
);
2066 if (pipe_ctx
->stream
->gamut_remap_matrix
.enable_remap
== true) {
2067 adjust
.gamut_adjust_type
= GRAPHICS_GAMUT_ADJUST_TYPE_SW
;
2068 adjust
.temperature_matrix
[0] =
2070 gamut_remap_matrix
.matrix
[0];
2071 adjust
.temperature_matrix
[1] =
2073 gamut_remap_matrix
.matrix
[1];
2074 adjust
.temperature_matrix
[2] =
2076 gamut_remap_matrix
.matrix
[2];
2077 adjust
.temperature_matrix
[3] =
2079 gamut_remap_matrix
.matrix
[4];
2080 adjust
.temperature_matrix
[4] =
2082 gamut_remap_matrix
.matrix
[5];
2083 adjust
.temperature_matrix
[5] =
2085 gamut_remap_matrix
.matrix
[6];
2086 adjust
.temperature_matrix
[6] =
2088 gamut_remap_matrix
.matrix
[8];
2089 adjust
.temperature_matrix
[7] =
2091 gamut_remap_matrix
.matrix
[9];
2092 adjust
.temperature_matrix
[8] =
2094 gamut_remap_matrix
.matrix
[10];
2097 pipe_ctx
->plane_res
.xfm
->funcs
->transform_set_gamut_remap(pipe_ctx
->plane_res
.xfm
, &adjust
);
2099 pipe_ctx
->plane_res
.scl_data
.lb_params
.alpha_en
= pipe_ctx
->bottom_pipe
!= 0;
2100 program_scaler(dc
, pipe_ctx
);
2102 program_surface_visibility(dc
, pipe_ctx
);
2104 mi
->funcs
->mem_input_program_surface_config(
2106 plane_state
->format
,
2107 &plane_state
->tiling_info
,
2108 &plane_state
->plane_size
,
2109 plane_state
->rotation
,
2112 if (mi
->funcs
->set_blank
)
2113 mi
->funcs
->set_blank(mi
, pipe_ctx
->plane_state
->visible
);
2115 if (dc
->public.config
.gpu_vm_support
)
2116 mi
->funcs
->mem_input_program_pte_vm(
2117 pipe_ctx
->plane_res
.mi
,
2118 plane_state
->format
,
2119 &plane_state
->tiling_info
,
2120 plane_state
->rotation
);
2123 static void update_plane_addr(const struct core_dc
*dc
,
2124 struct pipe_ctx
*pipe_ctx
)
2126 struct dc_plane_state
*plane_state
= pipe_ctx
->plane_state
;
2128 if (plane_state
== NULL
)
2131 pipe_ctx
->plane_res
.mi
->funcs
->mem_input_program_surface_flip_and_addr(
2132 pipe_ctx
->plane_res
.mi
,
2133 &plane_state
->address
,
2134 plane_state
->flip_immediate
);
2136 plane_state
->status
.requested_address
= plane_state
->address
;
2139 void dce110_update_pending_status(struct pipe_ctx
*pipe_ctx
)
2141 struct dc_plane_state
*plane_state
= pipe_ctx
->plane_state
;
2143 if (plane_state
== NULL
)
2146 plane_state
->status
.is_flip_pending
=
2147 pipe_ctx
->plane_res
.mi
->funcs
->mem_input_is_flip_pending(
2148 pipe_ctx
->plane_res
.mi
);
2150 if (plane_state
->status
.is_flip_pending
&& !plane_state
->visible
)
2151 pipe_ctx
->plane_res
.mi
->current_address
= pipe_ctx
->plane_res
.mi
->request_address
;
2153 plane_state
->status
.current_address
= pipe_ctx
->plane_res
.mi
->current_address
;
2154 if (pipe_ctx
->plane_res
.mi
->current_address
.type
== PLN_ADDR_TYPE_GRPH_STEREO
&&
2155 pipe_ctx
->tg
->funcs
->is_stereo_left_eye
) {
2156 plane_state
->status
.is_right_eye
=\
2157 !pipe_ctx
->tg
->funcs
->is_stereo_left_eye(pipe_ctx
->tg
);
2161 void dce110_power_down(struct core_dc
*dc
)
2163 power_down_all_hw_blocks(dc
);
2164 disable_vga_and_power_gate_all_controllers(dc
);
2167 static bool wait_for_reset_trigger_to_occur(
2168 struct dc_context
*dc_ctx
,
2169 struct timing_generator
*tg
)
2173 /* To avoid endless loop we wait at most
2174 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2175 const uint32_t frames_to_wait_on_triggered_reset
= 10;
2178 for (i
= 0; i
< frames_to_wait_on_triggered_reset
; i
++) {
2180 if (!tg
->funcs
->is_counter_moving(tg
)) {
2181 DC_ERROR("TG counter is not moving!\n");
2185 if (tg
->funcs
->did_triggered_reset_occur(tg
)) {
2187 /* usually occurs at i=1 */
2188 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2193 /* Wait for one frame. */
2194 tg
->funcs
->wait_for_state(tg
, CRTC_STATE_VACTIVE
);
2195 tg
->funcs
->wait_for_state(tg
, CRTC_STATE_VBLANK
);
2199 DC_ERROR("GSL: Timeout on reset trigger!\n");
2204 /* Enable timing synchronization for a group of Timing Generators. */
2205 static void dce110_enable_timing_synchronization(
2209 struct pipe_ctx
*grouped_pipes
[])
2211 struct dc_context
*dc_ctx
= dc
->ctx
;
2212 struct dcp_gsl_params gsl_params
= { 0 };
2215 DC_SYNC_INFO("GSL: Setting-up...\n");
2217 /* Designate a single TG in the group as a master.
2218 * Since HW doesn't care which one, we always assign
2219 * the 1st one in the group. */
2220 gsl_params
.gsl_group
= 0;
2221 gsl_params
.gsl_master
= grouped_pipes
[0]->tg
->inst
;
2223 for (i
= 0; i
< group_size
; i
++)
2224 grouped_pipes
[i
]->tg
->funcs
->setup_global_swap_lock(
2225 grouped_pipes
[i
]->tg
, &gsl_params
);
2227 /* Reset slave controllers on master VSync */
2228 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2230 for (i
= 1 /* skip the master */; i
< group_size
; i
++)
2231 grouped_pipes
[i
]->tg
->funcs
->enable_reset_trigger(
2232 grouped_pipes
[i
]->tg
, gsl_params
.gsl_group
);
2236 for (i
= 1 /* skip the master */; i
< group_size
; i
++) {
2237 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2238 wait_for_reset_trigger_to_occur(dc_ctx
, grouped_pipes
[i
]->tg
);
2239 /* Regardless of success of the wait above, remove the reset or
2240 * the driver will start timing out on Display requests. */
2241 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2242 grouped_pipes
[i
]->tg
->funcs
->disable_reset_trigger(grouped_pipes
[i
]->tg
);
2246 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2247 * is that the sync'ed displays will not drift out of sync over time*/
2248 DC_SYNC_INFO("GSL: Restoring register states.\n");
2249 for (i
= 0; i
< group_size
; i
++)
2250 grouped_pipes
[i
]->tg
->funcs
->tear_down_global_swap_lock(grouped_pipes
[i
]->tg
);
2252 DC_SYNC_INFO("GSL: Set-up complete.\n");
2255 static void init_hw(struct core_dc
*dc
)
2259 struct transform
*xfm
;
2262 bp
= dc
->ctx
->dc_bios
;
2263 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
2264 xfm
= dc
->res_pool
->transforms
[i
];
2265 xfm
->funcs
->transform_reset(xfm
);
2267 dc
->hwss
.enable_display_power_gating(
2269 PIPE_GATING_CONTROL_INIT
);
2270 dc
->hwss
.enable_display_power_gating(
2272 PIPE_GATING_CONTROL_DISABLE
);
2273 dc
->hwss
.enable_display_pipe_clock_gating(
2278 dce_clock_gating_power_up(dc
->hwseq
, false);
2279 /***************************************/
2281 for (i
= 0; i
< dc
->link_count
; i
++) {
2282 /****************************************/
2283 /* Power up AND update implementation according to the
2284 * required signal (which may be different from the
2285 * default signal on connector). */
2286 struct dc_link
*link
= dc
->links
[i
];
2287 link
->link_enc
->funcs
->hw_init(link
->link_enc
);
2290 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
2291 struct timing_generator
*tg
= dc
->res_pool
->timing_generators
[i
];
2293 tg
->funcs
->disable_vga(tg
);
2295 /* Blank controller using driver code instead of
2297 tg
->funcs
->set_blank(tg
, true);
2298 hwss_wait_for_blank_complete(tg
);
2301 for (i
= 0; i
< dc
->res_pool
->audio_count
; i
++) {
2302 struct audio
*audio
= dc
->res_pool
->audios
[i
];
2303 audio
->funcs
->hw_init(audio
);
2306 abm
= dc
->res_pool
->abm
;
2308 abm
->funcs
->init_backlight(abm
);
2309 abm
->funcs
->abm_init(abm
);
2312 if (dc
->fbc_compressor
)
2313 dc
->fbc_compressor
->funcs
->power_up_fbc(dc
->fbc_compressor
);
2318 void dce110_fill_display_configs(
2319 const struct validate_context
*context
,
2320 struct dm_pp_display_configuration
*pp_display_cfg
)
2325 for (j
= 0; j
< context
->stream_count
; j
++) {
2328 const struct dc_stream_state
*stream
= context
->streams
[j
];
2329 struct dm_pp_single_disp_config
*cfg
=
2330 &pp_display_cfg
->disp_configs
[num_cfgs
];
2331 const struct pipe_ctx
*pipe_ctx
= NULL
;
2333 for (k
= 0; k
< MAX_PIPES
; k
++)
2334 if (stream
== context
->res_ctx
.pipe_ctx
[k
].stream
) {
2335 pipe_ctx
= &context
->res_ctx
.pipe_ctx
[k
];
2339 ASSERT(pipe_ctx
!= NULL
);
2342 cfg
->signal
= pipe_ctx
->stream
->signal
;
2343 cfg
->pipe_idx
= pipe_ctx
->pipe_idx
;
2344 cfg
->src_height
= stream
->src
.height
;
2345 cfg
->src_width
= stream
->src
.width
;
2346 cfg
->ddi_channel_mapping
=
2347 stream
->sink
->link
->ddi_channel_mapping
.raw
;
2349 stream
->sink
->link
->link_enc
->transmitter
;
2350 cfg
->link_settings
.lane_count
=
2351 stream
->sink
->link
->cur_link_settings
.lane_count
;
2352 cfg
->link_settings
.link_rate
=
2353 stream
->sink
->link
->cur_link_settings
.link_rate
;
2354 cfg
->link_settings
.link_spread
=
2355 stream
->sink
->link
->cur_link_settings
.link_spread
;
2356 cfg
->sym_clock
= stream
->phy_pix_clk
;
2357 /* Round v_refresh*/
2358 cfg
->v_refresh
= stream
->timing
.pix_clk_khz
* 1000;
2359 cfg
->v_refresh
/= stream
->timing
.h_total
;
2360 cfg
->v_refresh
= (cfg
->v_refresh
+ stream
->timing
.v_total
/ 2)
2361 / stream
->timing
.v_total
;
2364 pp_display_cfg
->display_count
= num_cfgs
;
2367 uint32_t dce110_get_min_vblank_time_us(const struct validate_context
*context
)
2370 uint32_t min_vertical_blank_time
= -1;
2372 for (j
= 0; j
< context
->stream_count
; j
++) {
2373 struct dc_stream_state
*stream
= context
->streams
[j
];
2374 uint32_t vertical_blank_in_pixels
= 0;
2375 uint32_t vertical_blank_time
= 0;
2377 vertical_blank_in_pixels
= stream
->timing
.h_total
*
2378 (stream
->timing
.v_total
2379 - stream
->timing
.v_addressable
);
2381 vertical_blank_time
= vertical_blank_in_pixels
2382 * 1000 / stream
->timing
.pix_clk_khz
;
2384 if (min_vertical_blank_time
> vertical_blank_time
)
2385 min_vertical_blank_time
= vertical_blank_time
;
2388 return min_vertical_blank_time
;
2391 static int determine_sclk_from_bounding_box(
2392 const struct core_dc
*dc
,
2398 * Some asics do not give us sclk levels, so we just report the actual
2401 if (dc
->sclk_lvls
.num_levels
== 0)
2402 return required_sclk
;
2404 for (i
= 0; i
< dc
->sclk_lvls
.num_levels
; i
++) {
2405 if (dc
->sclk_lvls
.clocks_in_khz
[i
] >= required_sclk
)
2406 return dc
->sclk_lvls
.clocks_in_khz
[i
];
2409 * even maximum level could not satisfy requirement, this
2410 * is unexpected at this stage, should have been caught at
2414 return dc
->sclk_lvls
.clocks_in_khz
[dc
->sclk_lvls
.num_levels
- 1];
2417 static void pplib_apply_display_requirements(
2419 struct validate_context
*context
)
2421 struct dm_pp_display_configuration
*pp_display_cfg
= &context
->pp_display_cfg
;
2423 pp_display_cfg
->all_displays_in_sync
=
2424 context
->bw
.dce
.all_displays_in_sync
;
2425 pp_display_cfg
->nb_pstate_switch_disable
=
2426 context
->bw
.dce
.nbp_state_change_enable
== false;
2427 pp_display_cfg
->cpu_cc6_disable
=
2428 context
->bw
.dce
.cpuc_state_change_enable
== false;
2429 pp_display_cfg
->cpu_pstate_disable
=
2430 context
->bw
.dce
.cpup_state_change_enable
== false;
2431 pp_display_cfg
->cpu_pstate_separation_time
=
2432 context
->bw
.dce
.blackout_recovery_time_us
;
2434 pp_display_cfg
->min_memory_clock_khz
= context
->bw
.dce
.yclk_khz
2435 / MEMORY_TYPE_MULTIPLIER
;
2437 pp_display_cfg
->min_engine_clock_khz
= determine_sclk_from_bounding_box(
2439 context
->bw
.dce
.sclk_khz
);
2441 pp_display_cfg
->min_engine_clock_deep_sleep_khz
2442 = context
->bw
.dce
.sclk_deep_sleep_khz
;
2444 pp_display_cfg
->avail_mclk_switch_time_us
=
2445 dce110_get_min_vblank_time_us(context
);
2447 pp_display_cfg
->avail_mclk_switch_time_in_disp_active_us
= 0;
2449 pp_display_cfg
->disp_clk_khz
= context
->bw
.dce
.dispclk_khz
;
2451 dce110_fill_display_configs(context
, pp_display_cfg
);
2453 /* TODO: is this still applicable?*/
2454 if (pp_display_cfg
->display_count
== 1) {
2455 const struct dc_crtc_timing
*timing
=
2456 &context
->streams
[0]->timing
;
2458 pp_display_cfg
->crtc_index
=
2459 pp_display_cfg
->disp_configs
[0].pipe_idx
;
2460 pp_display_cfg
->line_time_in_us
= timing
->h_total
* 1000
2461 / timing
->pix_clk_khz
;
2464 if (memcmp(&dc
->prev_display_config
, pp_display_cfg
, sizeof(
2465 struct dm_pp_display_configuration
)) != 0)
2466 dm_pp_apply_display_requirements(dc
->ctx
, pp_display_cfg
);
2468 dc
->prev_display_config
= *pp_display_cfg
;
2471 static void dce110_set_bandwidth(
2473 struct validate_context
*context
,
2474 bool decrease_allowed
)
2476 dce110_set_displaymarks(dc
, context
);
2478 if (decrease_allowed
|| context
->bw
.dce
.dispclk_khz
> dc
->current_context
->bw
.dce
.dispclk_khz
) {
2479 dc
->res_pool
->display_clock
->funcs
->set_clock(
2480 dc
->res_pool
->display_clock
,
2481 context
->bw
.dce
.dispclk_khz
* 115 / 100);
2482 dc
->current_context
->bw
.dce
.dispclk_khz
= context
->bw
.dce
.dispclk_khz
;
2485 pplib_apply_display_requirements(dc
, context
);
2488 static void dce110_program_front_end_for_pipe(
2489 struct core_dc
*dc
, struct pipe_ctx
*pipe_ctx
)
2491 struct mem_input
*mi
= pipe_ctx
->plane_res
.mi
;
2492 struct pipe_ctx
*old_pipe
= NULL
;
2493 struct dc_plane_state
*plane_state
= pipe_ctx
->plane_state
;
2494 struct xfm_grph_csc_adjustment adjust
;
2495 struct out_csc_color_matrix tbl_entry
;
2498 memset(&tbl_entry
, 0, sizeof(tbl_entry
));
2500 if (dc
->current_context
)
2501 old_pipe
= &dc
->current_context
->res_ctx
.pipe_ctx
[pipe_ctx
->pipe_idx
];
2503 memset(&adjust
, 0, sizeof(adjust
));
2504 adjust
.gamut_adjust_type
= GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS
;
2506 dce_enable_fe_clock(dc
->hwseq
, pipe_ctx
->pipe_idx
, true);
2508 set_default_colors(pipe_ctx
);
2509 if (pipe_ctx
->stream
->csc_color_matrix
.enable_adjustment
2511 tbl_entry
.color_space
=
2512 pipe_ctx
->stream
->output_color_space
;
2514 for (i
= 0; i
< 12; i
++)
2515 tbl_entry
.regval
[i
] =
2516 pipe_ctx
->stream
->csc_color_matrix
.matrix
[i
];
2518 pipe_ctx
->plane_res
.xfm
->funcs
->opp_set_csc_adjustment
2519 (pipe_ctx
->plane_res
.xfm
, &tbl_entry
);
2522 if (pipe_ctx
->stream
->gamut_remap_matrix
.enable_remap
== true) {
2523 adjust
.gamut_adjust_type
= GRAPHICS_GAMUT_ADJUST_TYPE_SW
;
2524 adjust
.temperature_matrix
[0] =
2526 gamut_remap_matrix
.matrix
[0];
2527 adjust
.temperature_matrix
[1] =
2529 gamut_remap_matrix
.matrix
[1];
2530 adjust
.temperature_matrix
[2] =
2532 gamut_remap_matrix
.matrix
[2];
2533 adjust
.temperature_matrix
[3] =
2535 gamut_remap_matrix
.matrix
[4];
2536 adjust
.temperature_matrix
[4] =
2538 gamut_remap_matrix
.matrix
[5];
2539 adjust
.temperature_matrix
[5] =
2541 gamut_remap_matrix
.matrix
[6];
2542 adjust
.temperature_matrix
[6] =
2544 gamut_remap_matrix
.matrix
[8];
2545 adjust
.temperature_matrix
[7] =
2547 gamut_remap_matrix
.matrix
[9];
2548 adjust
.temperature_matrix
[8] =
2550 gamut_remap_matrix
.matrix
[10];
2553 pipe_ctx
->plane_res
.xfm
->funcs
->transform_set_gamut_remap(pipe_ctx
->plane_res
.xfm
, &adjust
);
2555 pipe_ctx
->plane_res
.scl_data
.lb_params
.alpha_en
= pipe_ctx
->bottom_pipe
!= 0;
2557 program_scaler(dc
, pipe_ctx
);
2559 mi
->funcs
->mem_input_program_surface_config(
2561 plane_state
->format
,
2562 &plane_state
->tiling_info
,
2563 &plane_state
->plane_size
,
2564 plane_state
->rotation
,
2567 if (mi
->funcs
->set_blank
)
2568 mi
->funcs
->set_blank(mi
, pipe_ctx
->plane_state
->visible
);
2570 if (dc
->public.config
.gpu_vm_support
)
2571 mi
->funcs
->mem_input_program_pte_vm(
2572 pipe_ctx
->plane_res
.mi
,
2573 plane_state
->format
,
2574 &plane_state
->tiling_info
,
2575 plane_state
->rotation
);
2577 dm_logger_write(dc
->ctx
->logger
, LOG_SURFACE
,
2578 "Pipe:%d 0x%x: addr hi:0x%x, "
2581 " %d; dst: %d, %d, %d, %d;"
2582 "clip: %d, %d, %d, %d\n",
2584 pipe_ctx
->plane_state
,
2585 pipe_ctx
->plane_state
->address
.grph
.addr
.high_part
,
2586 pipe_ctx
->plane_state
->address
.grph
.addr
.low_part
,
2587 pipe_ctx
->plane_state
->src_rect
.x
,
2588 pipe_ctx
->plane_state
->src_rect
.y
,
2589 pipe_ctx
->plane_state
->src_rect
.width
,
2590 pipe_ctx
->plane_state
->src_rect
.height
,
2591 pipe_ctx
->plane_state
->dst_rect
.x
,
2592 pipe_ctx
->plane_state
->dst_rect
.y
,
2593 pipe_ctx
->plane_state
->dst_rect
.width
,
2594 pipe_ctx
->plane_state
->dst_rect
.height
,
2595 pipe_ctx
->plane_state
->clip_rect
.x
,
2596 pipe_ctx
->plane_state
->clip_rect
.y
,
2597 pipe_ctx
->plane_state
->clip_rect
.width
,
2598 pipe_ctx
->plane_state
->clip_rect
.height
);
2600 dm_logger_write(dc
->ctx
->logger
, LOG_SURFACE
,
2601 "Pipe %d: width, height, x, y\n"
2602 "viewport:%d, %d, %d, %d\n"
2603 "recout: %d, %d, %d, %d\n",
2605 pipe_ctx
->plane_res
.scl_data
.viewport
.width
,
2606 pipe_ctx
->plane_res
.scl_data
.viewport
.height
,
2607 pipe_ctx
->plane_res
.scl_data
.viewport
.x
,
2608 pipe_ctx
->plane_res
.scl_data
.viewport
.y
,
2609 pipe_ctx
->plane_res
.scl_data
.recout
.width
,
2610 pipe_ctx
->plane_res
.scl_data
.recout
.height
,
2611 pipe_ctx
->plane_res
.scl_data
.recout
.x
,
2612 pipe_ctx
->plane_res
.scl_data
.recout
.y
);
2615 static void dce110_apply_ctx_for_surface(
2617 const struct dc_plane_state
*plane_state
,
2618 struct validate_context
*context
)
2625 for (i
= 0; i
< dc
->res_pool
->pipe_count
; i
++) {
2626 struct pipe_ctx
*pipe_ctx
= &context
->res_ctx
.pipe_ctx
[i
];
2628 if (pipe_ctx
->plane_state
!= plane_state
)
2631 dce110_program_front_end_for_pipe(dc
, pipe_ctx
);
2632 program_surface_visibility(dc
, pipe_ctx
);
2637 static void dce110_power_down_fe(struct core_dc
*dc
, int fe_idx
)
2639 /* Do not power down fe when stream is active on dce*/
2640 if (dc
->current_context
->res_ctx
.pipe_ctx
[fe_idx
].stream
)
2643 dc
->hwss
.enable_display_power_gating(
2644 dc
, fe_idx
, dc
->ctx
->dc_bios
, PIPE_GATING_CONTROL_ENABLE
);
2646 dc
->res_pool
->transforms
[fe_idx
]->funcs
->transform_reset(
2647 dc
->res_pool
->transforms
[fe_idx
]);
2650 static void dce110_wait_for_mpcc_disconnect(
2652 struct resource_pool
*res_pool
,
2653 struct pipe_ctx
*pipe_ctx
)
2658 static void program_csc_matrix(struct pipe_ctx
*pipe_ctx
,
2659 enum dc_color_space colorspace
,
2663 struct out_csc_color_matrix tbl_entry
;
2665 if (pipe_ctx
->stream
->csc_color_matrix
.enable_adjustment
2667 enum dc_color_space color_space
=
2668 pipe_ctx
->stream
->output_color_space
;
2670 //uint16_t matrix[12];
2671 for (i
= 0; i
< 12; i
++)
2672 tbl_entry
.regval
[i
] = pipe_ctx
->stream
->csc_color_matrix
.matrix
[i
];
2674 tbl_entry
.color_space
= color_space
;
2675 //tbl_entry.regval = matrix;
2676 pipe_ctx
->plane_res
.xfm
->funcs
->opp_set_csc_adjustment(pipe_ctx
->plane_res
.xfm
, &tbl_entry
);
2680 static const struct hw_sequencer_funcs dce110_funcs
= {
2681 .program_gamut_remap
= program_gamut_remap
,
2682 .program_csc_matrix
= program_csc_matrix
,
2684 .apply_ctx_to_hw
= dce110_apply_ctx_to_hw
,
2685 .apply_ctx_for_surface
= dce110_apply_ctx_for_surface
,
2686 .set_plane_config
= set_plane_config
,
2687 .update_plane_addr
= update_plane_addr
,
2688 .update_pending_status
= dce110_update_pending_status
,
2689 .set_input_transfer_func
= dce110_set_input_transfer_func
,
2690 .set_output_transfer_func
= dce110_set_output_transfer_func
,
2691 .power_down
= dce110_power_down
,
2692 .enable_accelerated_mode
= dce110_enable_accelerated_mode
,
2693 .enable_timing_synchronization
= dce110_enable_timing_synchronization
,
2694 .update_info_frame
= dce110_update_info_frame
,
2695 .enable_stream
= dce110_enable_stream
,
2696 .disable_stream
= dce110_disable_stream
,
2697 .unblank_stream
= dce110_unblank_stream
,
2698 .enable_display_pipe_clock_gating
= enable_display_pipe_clock_gating
,
2699 .enable_display_power_gating
= dce110_enable_display_power_gating
,
2700 .power_down_front_end
= dce110_power_down_fe
,
2701 .pipe_control_lock
= dce_pipe_control_lock
,
2702 .set_bandwidth
= dce110_set_bandwidth
,
2704 .get_position
= get_position
,
2705 .set_static_screen_control
= set_static_screen_control
,
2706 .reset_hw_ctx_wrap
= dce110_reset_hw_ctx_wrap
,
2707 .prog_pixclk_crtc_otg
= dce110_prog_pixclk_crtc_otg
,
2708 .setup_stereo
= NULL
,
2709 .set_avmute
= dce110_set_avmute
,
2710 .wait_for_mpcc_disconnect
= dce110_wait_for_mpcc_disconnect
2713 bool dce110_hw_sequencer_construct(struct core_dc
*dc
)
2715 dc
->hwss
= dce110_funcs
;