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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "resource.h"
31 #include "hw_sequencer.h"
32 #include "dm_helpers.h"
33 #include "dce110_hw_sequencer.h"
34 #include "dce110_timing_generator.h"
35
36 #include "bios/bios_parser_helper.h"
37 #include "timing_generator.h"
38 #include "mem_input.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "transform.h"
42 #include "stream_encoder.h"
43 #include "link_encoder.h"
44 #include "clock_source.h"
45 #include "abm.h"
46 #include "audio.h"
47 #include "dce/dce_hwseq.h"
48
49 /* include DCE11 register header files */
50 #include "dce/dce_11_0_d.h"
51 #include "dce/dce_11_0_sh_mask.h"
52 #include "custom_float.h"
53
54 struct dce110_hw_seq_reg_offsets {
55 uint32_t crtc;
56 };
57
58 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
59 {
60 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
61 },
62 {
63 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
64 },
65 {
66 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
67 },
68 {
69 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
70 }
71 };
72
73 #define HW_REG_BLND(reg, id)\
74 (reg + reg_offsets[id].blnd)
75
76 #define HW_REG_CRTC(reg, id)\
77 (reg + reg_offsets[id].crtc)
78
79 #define MAX_WATERMARK 0xFFFF
80 #define SAFE_NBP_MARK 0x7FFF
81
82 /*******************************************************************************
83 * Private definitions
84 ******************************************************************************/
85 /***************************PIPE_CONTROL***********************************/
86 static void dce110_init_pte(struct dc_context *ctx)
87 {
88 uint32_t addr;
89 uint32_t value = 0;
90 uint32_t chunk_int = 0;
91 uint32_t chunk_mul = 0;
92
93 addr = mmUNP_DVMM_PTE_CONTROL;
94 value = dm_read_reg(ctx, addr);
95
96 set_reg_field_value(
97 value,
98 0,
99 DVMM_PTE_CONTROL,
100 DVMM_USE_SINGLE_PTE);
101
102 set_reg_field_value(
103 value,
104 1,
105 DVMM_PTE_CONTROL,
106 DVMM_PTE_BUFFER_MODE0);
107
108 set_reg_field_value(
109 value,
110 1,
111 DVMM_PTE_CONTROL,
112 DVMM_PTE_BUFFER_MODE1);
113
114 dm_write_reg(ctx, addr, value);
115
116 addr = mmDVMM_PTE_REQ;
117 value = dm_read_reg(ctx, addr);
118
119 chunk_int = get_reg_field_value(
120 value,
121 DVMM_PTE_REQ,
122 HFLIP_PTEREQ_PER_CHUNK_INT);
123
124 chunk_mul = get_reg_field_value(
125 value,
126 DVMM_PTE_REQ,
127 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
128
129 if (chunk_int != 0x4 || chunk_mul != 0x4) {
130
131 set_reg_field_value(
132 value,
133 255,
134 DVMM_PTE_REQ,
135 MAX_PTEREQ_TO_ISSUE);
136
137 set_reg_field_value(
138 value,
139 4,
140 DVMM_PTE_REQ,
141 HFLIP_PTEREQ_PER_CHUNK_INT);
142
143 set_reg_field_value(
144 value,
145 4,
146 DVMM_PTE_REQ,
147 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
148
149 dm_write_reg(ctx, addr, value);
150 }
151 }
152 /**************************************************************************/
153
154 static void enable_display_pipe_clock_gating(
155 struct dc_context *ctx,
156 bool clock_gating)
157 {
158 /*TODO*/
159 }
160
161 static bool dce110_enable_display_power_gating(
162 struct core_dc *dc,
163 uint8_t controller_id,
164 struct dc_bios *dcb,
165 enum pipe_gating_control power_gating)
166 {
167 enum bp_result bp_result = BP_RESULT_OK;
168 enum bp_pipe_control_action cntl;
169 struct dc_context *ctx = dc->ctx;
170 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
171
172 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
173 return true;
174
175 if (power_gating == PIPE_GATING_CONTROL_INIT)
176 cntl = ASIC_PIPE_INIT;
177 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
178 cntl = ASIC_PIPE_ENABLE;
179 else
180 cntl = ASIC_PIPE_DISABLE;
181
182 if (controller_id == underlay_idx)
183 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
184
185 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
186
187 bp_result = dcb->funcs->enable_disp_power_gating(
188 dcb, controller_id + 1, cntl);
189
190 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
191 * by default when command table is called
192 *
193 * Bios parser accepts controller_id = 6 as indicative of
194 * underlay pipe in dce110. But we do not support more
195 * than 3.
196 */
197 if (controller_id < CONTROLLER_ID_MAX - 1)
198 dm_write_reg(ctx,
199 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
200 0);
201 }
202
203 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
204 dce110_init_pte(ctx);
205
206 if (bp_result == BP_RESULT_OK)
207 return true;
208 else
209 return false;
210 }
211
212 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
213 const struct core_surface *surface)
214 {
215 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
216
217 switch (surface->public.format) {
218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
220 prescale_params->scale = 0x2020;
221 break;
222 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
223 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
224 prescale_params->scale = 0x2008;
225 break;
226 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
227 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
228 prescale_params->scale = 0x2000;
229 break;
230 default:
231 ASSERT(false);
232 break;
233 }
234 }
235
236
237 /* Only use LUT for 8 bit formats */
238 static bool use_lut(const struct core_surface *surface)
239 {
240 switch (surface->public.format) {
241 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
242 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
243 return true;
244 default:
245 return false;
246 }
247 }
248
249 static bool dce110_set_input_transfer_func(
250 struct pipe_ctx *pipe_ctx,
251 const struct core_surface *surface)
252 {
253 struct input_pixel_processor *ipp = pipe_ctx->ipp;
254 const struct core_transfer_func *tf = NULL;
255 struct ipp_prescale_params prescale_params = { 0 };
256 bool result = true;
257
258 if (ipp == NULL)
259 return false;
260
261 if (surface->public.in_transfer_func)
262 tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func);
263
264 build_prescale_params(&prescale_params, surface);
265 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
266
267 if (surface->public.gamma_correction && use_lut(surface))
268 ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
269
270 if (tf == NULL) {
271 /* Default case if no input transfer function specified */
272 ipp->funcs->ipp_set_degamma(ipp,
273 IPP_DEGAMMA_MODE_HW_sRGB);
274 } else if (tf->public.type == TF_TYPE_PREDEFINED) {
275 switch (tf->public.tf) {
276 case TRANSFER_FUNCTION_SRGB:
277 ipp->funcs->ipp_set_degamma(ipp,
278 IPP_DEGAMMA_MODE_HW_sRGB);
279 break;
280 case TRANSFER_FUNCTION_BT709:
281 ipp->funcs->ipp_set_degamma(ipp,
282 IPP_DEGAMMA_MODE_HW_xvYCC);
283 break;
284 case TRANSFER_FUNCTION_LINEAR:
285 ipp->funcs->ipp_set_degamma(ipp,
286 IPP_DEGAMMA_MODE_BYPASS);
287 break;
288 case TRANSFER_FUNCTION_PQ:
289 result = false;
290 break;
291 default:
292 result = false;
293 break;
294 }
295 } else if (tf->public.type == TF_TYPE_BYPASS) {
296 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
297 } else {
298 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
299 result = false;
300 }
301
302 return result;
303 }
304
305 static bool convert_to_custom_float(
306 struct pwl_result_data *rgb_resulted,
307 struct curve_points *arr_points,
308 uint32_t hw_points_num)
309 {
310 struct custom_float_format fmt;
311
312 struct pwl_result_data *rgb = rgb_resulted;
313
314 uint32_t i = 0;
315
316 fmt.exponenta_bits = 6;
317 fmt.mantissa_bits = 12;
318 fmt.sign = true;
319
320 if (!convert_to_custom_float_format(
321 arr_points[0].x,
322 &fmt,
323 &arr_points[0].custom_float_x)) {
324 BREAK_TO_DEBUGGER();
325 return false;
326 }
327
328 if (!convert_to_custom_float_format(
329 arr_points[0].offset,
330 &fmt,
331 &arr_points[0].custom_float_offset)) {
332 BREAK_TO_DEBUGGER();
333 return false;
334 }
335
336 if (!convert_to_custom_float_format(
337 arr_points[0].slope,
338 &fmt,
339 &arr_points[0].custom_float_slope)) {
340 BREAK_TO_DEBUGGER();
341 return false;
342 }
343
344 fmt.mantissa_bits = 10;
345 fmt.sign = false;
346
347 if (!convert_to_custom_float_format(
348 arr_points[1].x,
349 &fmt,
350 &arr_points[1].custom_float_x)) {
351 BREAK_TO_DEBUGGER();
352 return false;
353 }
354
355 if (!convert_to_custom_float_format(
356 arr_points[1].y,
357 &fmt,
358 &arr_points[1].custom_float_y)) {
359 BREAK_TO_DEBUGGER();
360 return false;
361 }
362
363 if (!convert_to_custom_float_format(
364 arr_points[2].slope,
365 &fmt,
366 &arr_points[2].custom_float_slope)) {
367 BREAK_TO_DEBUGGER();
368 return false;
369 }
370
371 fmt.mantissa_bits = 12;
372 fmt.sign = true;
373
374 while (i != hw_points_num) {
375 if (!convert_to_custom_float_format(
376 rgb->red,
377 &fmt,
378 &rgb->red_reg)) {
379 BREAK_TO_DEBUGGER();
380 return false;
381 }
382
383 if (!convert_to_custom_float_format(
384 rgb->green,
385 &fmt,
386 &rgb->green_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(
392 rgb->blue,
393 &fmt,
394 &rgb->blue_reg)) {
395 BREAK_TO_DEBUGGER();
396 return false;
397 }
398
399 if (!convert_to_custom_float_format(
400 rgb->delta_red,
401 &fmt,
402 &rgb->delta_red_reg)) {
403 BREAK_TO_DEBUGGER();
404 return false;
405 }
406
407 if (!convert_to_custom_float_format(
408 rgb->delta_green,
409 &fmt,
410 &rgb->delta_green_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 if (!convert_to_custom_float_format(
416 rgb->delta_blue,
417 &fmt,
418 &rgb->delta_blue_reg)) {
419 BREAK_TO_DEBUGGER();
420 return false;
421 }
422
423 ++rgb;
424 ++i;
425 }
426
427 return true;
428 }
429
430 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
431 *output_tf, struct pwl_params *regamma_params)
432 {
433 struct curve_points *arr_points;
434 struct pwl_result_data *rgb_resulted;
435 struct pwl_result_data *rgb;
436 struct pwl_result_data *rgb_plus_1;
437 struct fixed31_32 y_r;
438 struct fixed31_32 y_g;
439 struct fixed31_32 y_b;
440 struct fixed31_32 y1_min;
441 struct fixed31_32 y3_max;
442
443 int32_t segment_start, segment_end;
444 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
445
446 if (output_tf == NULL || regamma_params == NULL ||
447 output_tf->type == TF_TYPE_BYPASS)
448 return false;
449
450 arr_points = regamma_params->arr_points;
451 rgb_resulted = regamma_params->rgb_resulted;
452 hw_points = 0;
453
454 memset(regamma_params, 0, sizeof(struct pwl_params));
455
456 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
457 /* 16 segments
458 * segments are from 2^-11 to 2^5
459 */
460 segment_start = -11;
461 segment_end = 5;
462
463 seg_distr[0] = 2;
464 seg_distr[1] = 2;
465 seg_distr[2] = 2;
466 seg_distr[3] = 2;
467 seg_distr[4] = 2;
468 seg_distr[5] = 2;
469 seg_distr[6] = 3;
470 seg_distr[7] = 4;
471 seg_distr[8] = 4;
472 seg_distr[9] = 4;
473 seg_distr[10] = 4;
474 seg_distr[11] = 5;
475 seg_distr[12] = 5;
476 seg_distr[13] = 5;
477 seg_distr[14] = 5;
478 seg_distr[15] = 5;
479
480 } else {
481 /* 10 segments
482 * segment is from 2^-10 to 2^0
483 */
484 segment_start = -10;
485 segment_end = 0;
486
487 seg_distr[0] = 3;
488 seg_distr[1] = 4;
489 seg_distr[2] = 4;
490 seg_distr[3] = 4;
491 seg_distr[4] = 4;
492 seg_distr[5] = 4;
493 seg_distr[6] = 4;
494 seg_distr[7] = 4;
495 seg_distr[8] = 5;
496 seg_distr[9] = 5;
497 seg_distr[10] = -1;
498 seg_distr[11] = -1;
499 seg_distr[12] = -1;
500 seg_distr[13] = -1;
501 seg_distr[14] = -1;
502 seg_distr[15] = -1;
503 }
504
505 for (k = 0; k < 16; k++) {
506 if (seg_distr[k] != -1)
507 hw_points += (1 << seg_distr[k]);
508 }
509
510 j = 0;
511 for (k = 0; k < (segment_end - segment_start); k++) {
512 increment = 32 / (1 << seg_distr[k]);
513 start_index = (segment_start + k + 25) * 32;
514 for (i = start_index; i < start_index + 32; i += increment) {
515 if (j == hw_points - 1)
516 break;
517 rgb_resulted[j].red = output_tf->tf_pts.red[i];
518 rgb_resulted[j].green = output_tf->tf_pts.green[i];
519 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
520 j++;
521 }
522 }
523
524 /* last point */
525 start_index = (segment_end + 25) * 32;
526 rgb_resulted[hw_points - 1].red =
527 output_tf->tf_pts.red[start_index];
528 rgb_resulted[hw_points - 1].green =
529 output_tf->tf_pts.green[start_index];
530 rgb_resulted[hw_points - 1].blue =
531 output_tf->tf_pts.blue[start_index];
532
533 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
534 dal_fixed31_32_from_int(segment_start));
535 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
536 dal_fixed31_32_from_int(segment_end));
537 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
538 dal_fixed31_32_from_int(segment_end));
539
540 y_r = rgb_resulted[0].red;
541 y_g = rgb_resulted[0].green;
542 y_b = rgb_resulted[0].blue;
543
544 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
545
546 arr_points[0].y = y1_min;
547 arr_points[0].slope = dal_fixed31_32_div(
548 arr_points[0].y,
549 arr_points[0].x);
550
551 y_r = rgb_resulted[hw_points - 1].red;
552 y_g = rgb_resulted[hw_points - 1].green;
553 y_b = rgb_resulted[hw_points - 1].blue;
554
555 /* see comment above, m_arrPoints[1].y should be the Y value for the
556 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
557 */
558 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
559
560 arr_points[1].y = y3_max;
561 arr_points[2].y = y3_max;
562
563 arr_points[1].slope = dal_fixed31_32_zero;
564 arr_points[2].slope = dal_fixed31_32_zero;
565
566 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
567 /* for PQ, we want to have a straight line from last HW X point,
568 * and the slope to be such that we hit 1.0 at 10000 nits.
569 */
570 const struct fixed31_32 end_value =
571 dal_fixed31_32_from_int(125);
572
573 arr_points[1].slope = dal_fixed31_32_div(
574 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
575 dal_fixed31_32_sub(end_value, arr_points[1].x));
576 arr_points[2].slope = dal_fixed31_32_div(
577 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
578 dal_fixed31_32_sub(end_value, arr_points[1].x));
579 }
580
581 regamma_params->hw_points_num = hw_points;
582
583 i = 1;
584 for (k = 0; k < 16 && i < 16; k++) {
585 if (seg_distr[k] != -1) {
586 regamma_params->arr_curve_points[k].segments_num =
587 seg_distr[k];
588 regamma_params->arr_curve_points[i].offset =
589 regamma_params->arr_curve_points[k].
590 offset + (1 << seg_distr[k]);
591 }
592 i++;
593 }
594
595 if (seg_distr[k] != -1)
596 regamma_params->arr_curve_points[k].segments_num =
597 seg_distr[k];
598
599 rgb = rgb_resulted;
600 rgb_plus_1 = rgb_resulted + 1;
601
602 i = 1;
603
604 while (i != hw_points + 1) {
605 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
606 rgb_plus_1->red = rgb->red;
607 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
608 rgb_plus_1->green = rgb->green;
609 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
610 rgb_plus_1->blue = rgb->blue;
611
612 rgb->delta_red = dal_fixed31_32_sub(
613 rgb_plus_1->red,
614 rgb->red);
615 rgb->delta_green = dal_fixed31_32_sub(
616 rgb_plus_1->green,
617 rgb->green);
618 rgb->delta_blue = dal_fixed31_32_sub(
619 rgb_plus_1->blue,
620 rgb->blue);
621
622 ++rgb_plus_1;
623 ++rgb;
624 ++i;
625 }
626
627 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
628
629 return true;
630 }
631
632 static bool dce110_set_output_transfer_func(
633 struct pipe_ctx *pipe_ctx,
634 const struct core_surface *surface, /* Surface - To be removed */
635 const struct core_stream *stream)
636 {
637 struct output_pixel_processor *opp = pipe_ctx->opp;
638
639 opp->funcs->opp_power_on_regamma_lut(opp, true);
640 opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM;
641
642 if (stream->public.out_transfer_func &&
643 stream->public.out_transfer_func->type ==
644 TF_TYPE_PREDEFINED &&
645 stream->public.out_transfer_func->tf ==
646 TRANSFER_FUNCTION_SRGB) {
647 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
648 } else if (dce110_translate_regamma_to_hw_format(
649 stream->public.out_transfer_func, opp->regamma_params)) {
650 opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params);
651 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
652 } else {
653 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
654 }
655
656 opp->funcs->opp_power_on_regamma_lut(opp, false);
657
658 return true;
659 }
660
661 static enum dc_status bios_parser_crtc_source_select(
662 struct pipe_ctx *pipe_ctx)
663 {
664 struct dc_bios *dcb;
665 /* call VBIOS table to set CRTC source for the HW
666 * encoder block
667 * note: video bios clears all FMT setting here. */
668 struct bp_crtc_source_select crtc_source_select = {0};
669 const struct core_sink *sink = pipe_ctx->stream->sink;
670
671 crtc_source_select.engine_id = pipe_ctx->stream_enc->id;
672 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
673 /*TODO: Need to un-hardcode color depth, dp_audio and account for
674 * the case where signal and sink signal is different (translator
675 * encoder)*/
676 crtc_source_select.signal = pipe_ctx->stream->signal;
677 crtc_source_select.enable_dp_audio = false;
678 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
679 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
680
681 dcb = sink->ctx->dc_bios;
682
683 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
684 dcb,
685 &crtc_source_select)) {
686 return DC_ERROR_UNEXPECTED;
687 }
688
689 return DC_OK;
690 }
691
692 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
693 {
694 ASSERT(pipe_ctx->stream);
695
696 if (pipe_ctx->stream_enc == NULL)
697 return; /* this is not root pipe */
698
699 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
700 pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
701 pipe_ctx->stream_enc,
702 &pipe_ctx->encoder_info_frame);
703 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
704 pipe_ctx->stream_enc->funcs->update_dp_info_packets(
705 pipe_ctx->stream_enc,
706 &pipe_ctx->encoder_info_frame);
707 }
708
709 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
710 {
711 enum dc_lane_count lane_count =
712 pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count;
713
714 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
715 struct core_link *link = pipe_ctx->stream->sink->link;
716
717 /* 1. update AVI info frame (HDMI, DP)
718 * we always need to update info frame
719 */
720 uint32_t active_total_with_borders;
721 uint32_t early_control = 0;
722 struct timing_generator *tg = pipe_ctx->tg;
723
724 /* TODOFPGA may change to hwss.update_info_frame */
725 dce110_update_info_frame(pipe_ctx);
726 /* enable early control to avoid corruption on DP monitor*/
727 active_total_with_borders =
728 timing->h_addressable
729 + timing->h_border_left
730 + timing->h_border_right;
731
732 if (lane_count != 0)
733 early_control = active_total_with_borders % lane_count;
734
735 if (early_control == 0)
736 early_control = lane_count;
737
738 tg->funcs->set_early_control(tg, early_control);
739
740 /* enable audio only within mode set */
741 if (pipe_ctx->audio != NULL) {
742 if (dc_is_dp_signal(pipe_ctx->stream->signal))
743 pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc);
744 }
745
746 /* For MST, there are multiply stream go to only one link.
747 * connect DIG back_end to front_end while enable_stream and
748 * disconnect them during disable_stream
749 * BY this, it is logic clean to separate stream and link */
750 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
751 pipe_ctx->stream_enc->id, true);
752
753 }
754
755 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
756 {
757 struct core_stream *stream = pipe_ctx->stream;
758 struct core_link *link = stream->sink->link;
759
760 if (pipe_ctx->audio) {
761 pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio);
762
763 if (dc_is_dp_signal(pipe_ctx->stream->signal))
764 pipe_ctx->stream_enc->funcs->dp_audio_disable(
765 pipe_ctx->stream_enc);
766 else
767 pipe_ctx->stream_enc->funcs->hdmi_audio_disable(
768 pipe_ctx->stream_enc);
769
770 pipe_ctx->audio = NULL;
771
772 /* TODO: notify audio driver for if audio modes list changed
773 * add audio mode list change flag */
774 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
775 * stream->stream_engine_id);
776 */
777 }
778
779 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
780 pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets(
781 pipe_ctx->stream_enc);
782
783 if (dc_is_dp_signal(pipe_ctx->stream->signal))
784 pipe_ctx->stream_enc->funcs->stop_dp_info_packets(
785 pipe_ctx->stream_enc);
786
787 pipe_ctx->stream_enc->funcs->audio_mute_control(
788 pipe_ctx->stream_enc, true);
789
790
791 /* blank at encoder level */
792 if (dc_is_dp_signal(pipe_ctx->stream->signal))
793 pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc);
794
795 link->link_enc->funcs->connect_dig_be_to_fe(
796 link->link_enc,
797 pipe_ctx->stream_enc->id,
798 false);
799
800 }
801
802 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
803 struct dc_link_settings *link_settings)
804 {
805 struct encoder_unblank_param params = { { 0 } };
806
807 /* only 3 items below are used by unblank */
808 params.pixel_clk_khz =
809 pipe_ctx->stream->public.timing.pix_clk_khz;
810 params.link_settings.link_rate = link_settings->link_rate;
811 pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, &params);
812 }
813
814 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
815 {
816 switch (crtc_id) {
817 case CONTROLLER_ID_D0:
818 return DTO_SOURCE_ID0;
819 case CONTROLLER_ID_D1:
820 return DTO_SOURCE_ID1;
821 case CONTROLLER_ID_D2:
822 return DTO_SOURCE_ID2;
823 case CONTROLLER_ID_D3:
824 return DTO_SOURCE_ID3;
825 case CONTROLLER_ID_D4:
826 return DTO_SOURCE_ID4;
827 case CONTROLLER_ID_D5:
828 return DTO_SOURCE_ID5;
829 default:
830 return DTO_SOURCE_UNKNOWN;
831 }
832 }
833
834 static void build_audio_output(
835 const struct pipe_ctx *pipe_ctx,
836 struct audio_output *audio_output)
837 {
838 const struct core_stream *stream = pipe_ctx->stream;
839 audio_output->engine_id = pipe_ctx->stream_enc->id;
840
841 audio_output->signal = pipe_ctx->stream->signal;
842
843 /* audio_crtc_info */
844
845 audio_output->crtc_info.h_total =
846 stream->public.timing.h_total;
847
848 /*
849 * Audio packets are sent during actual CRTC blank physical signal, we
850 * need to specify actual active signal portion
851 */
852 audio_output->crtc_info.h_active =
853 stream->public.timing.h_addressable
854 + stream->public.timing.h_border_left
855 + stream->public.timing.h_border_right;
856
857 audio_output->crtc_info.v_active =
858 stream->public.timing.v_addressable
859 + stream->public.timing.v_border_top
860 + stream->public.timing.v_border_bottom;
861
862 audio_output->crtc_info.pixel_repetition = 1;
863
864 audio_output->crtc_info.interlaced =
865 stream->public.timing.flags.INTERLACE;
866
867 audio_output->crtc_info.refresh_rate =
868 (stream->public.timing.pix_clk_khz*1000)/
869 (stream->public.timing.h_total*stream->public.timing.v_total);
870
871 audio_output->crtc_info.color_depth =
872 stream->public.timing.display_color_depth;
873
874 audio_output->crtc_info.requested_pixel_clock =
875 pipe_ctx->pix_clk_params.requested_pix_clk;
876
877 audio_output->crtc_info.calculated_pixel_clock =
878 pipe_ctx->pix_clk_params.requested_pix_clk;
879
880 /*for HDMI, audio ACR is with deep color ratio factor*/
881 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
882 audio_output->crtc_info.requested_pixel_clock ==
883 stream->public.timing.pix_clk_khz) {
884 if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
885 audio_output->crtc_info.requested_pixel_clock =
886 audio_output->crtc_info.requested_pixel_clock/2;
887 audio_output->crtc_info.calculated_pixel_clock =
888 pipe_ctx->pix_clk_params.requested_pix_clk/2;
889
890 }
891 }
892
893 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
894 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
895 audio_output->pll_info.dp_dto_source_clock_in_khz =
896 pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
897 pipe_ctx->dis_clk);
898 }
899
900 audio_output->pll_info.feed_back_divider =
901 pipe_ctx->pll_settings.feedback_divider;
902
903 audio_output->pll_info.dto_source =
904 translate_to_dto_source(
905 pipe_ctx->pipe_idx + 1);
906
907 /* TODO hard code to enable for now. Need get from stream */
908 audio_output->pll_info.ss_enabled = true;
909
910 audio_output->pll_info.ss_percentage =
911 pipe_ctx->pll_settings.ss_percentage;
912 }
913
914 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
915 struct tg_color *color)
916 {
917 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
918
919 switch (pipe_ctx->scl_data.format) {
920 case PIXEL_FORMAT_ARGB8888:
921 /* set boarder color to red */
922 color->color_r_cr = color_value;
923 break;
924
925 case PIXEL_FORMAT_ARGB2101010:
926 /* set boarder color to blue */
927 color->color_b_cb = color_value;
928 break;
929 case PIXEL_FORMAT_420BPP12:
930 case PIXEL_FORMAT_420BPP15:
931 /* set boarder color to green */
932 color->color_g_y = color_value;
933 break;
934 case PIXEL_FORMAT_FP16:
935 /* set boarder color to white */
936 color->color_r_cr = color_value;
937 color->color_b_cb = color_value;
938 color->color_g_y = color_value;
939 break;
940 default:
941 break;
942 }
943 }
944
945 static void program_scaler(const struct core_dc *dc,
946 const struct pipe_ctx *pipe_ctx)
947 {
948 struct tg_color color = {0};
949
950 if (dc->public.debug.surface_visual_confirm)
951 get_surface_visual_confirm_color(pipe_ctx, &color);
952 else
953 color_space_to_black_color(dc,
954 pipe_ctx->stream->public.output_color_space,
955 &color);
956
957 pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth(
958 pipe_ctx->xfm,
959 pipe_ctx->scl_data.lb_params.depth,
960 &pipe_ctx->stream->bit_depth_params);
961
962 if (pipe_ctx->tg->funcs->set_overscan_blank_color)
963 pipe_ctx->tg->funcs->set_overscan_blank_color(
964 pipe_ctx->tg,
965 &color);
966
967 pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm,
968 &pipe_ctx->scl_data);
969 }
970
971 static enum dc_status dce110_prog_pixclk_crtc_otg(
972 struct pipe_ctx *pipe_ctx,
973 struct validate_context *context,
974 struct core_dc *dc)
975 {
976 struct core_stream *stream = pipe_ctx->stream;
977 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
978 pipe_ctx[pipe_ctx->pipe_idx];
979 struct tg_color black_color = {0};
980
981 if (!pipe_ctx_old->stream) {
982
983 /* program blank color */
984 color_space_to_black_color(dc,
985 stream->public.output_color_space, &black_color);
986 pipe_ctx->tg->funcs->set_blank_color(
987 pipe_ctx->tg,
988 &black_color);
989
990 /*
991 * Must blank CRTC after disabling power gating and before any
992 * programming, otherwise CRTC will be hung in bad state
993 */
994 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
995
996 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
997 pipe_ctx->clock_source,
998 &pipe_ctx->pix_clk_params,
999 &pipe_ctx->pll_settings)) {
1000 BREAK_TO_DEBUGGER();
1001 return DC_ERROR_UNEXPECTED;
1002 }
1003
1004 pipe_ctx->tg->funcs->program_timing(
1005 pipe_ctx->tg,
1006 &stream->public.timing,
1007 true);
1008 }
1009
1010 if (!pipe_ctx_old->stream) {
1011 if (false == pipe_ctx->tg->funcs->enable_crtc(
1012 pipe_ctx->tg)) {
1013 BREAK_TO_DEBUGGER();
1014 return DC_ERROR_UNEXPECTED;
1015 }
1016 }
1017
1018 return DC_OK;
1019 }
1020
1021 static enum dc_status apply_single_controller_ctx_to_hw(
1022 struct pipe_ctx *pipe_ctx,
1023 struct validate_context *context,
1024 struct core_dc *dc)
1025 {
1026 struct core_stream *stream = pipe_ctx->stream;
1027 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
1028 pipe_ctx[pipe_ctx->pipe_idx];
1029
1030 /* */
1031 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1032
1033 pipe_ctx->opp->funcs->opp_set_dyn_expansion(
1034 pipe_ctx->opp,
1035 COLOR_SPACE_YCBCR601,
1036 stream->public.timing.display_color_depth,
1037 pipe_ctx->stream->signal);
1038
1039 /* FPGA does not program backend */
1040 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1041 pipe_ctx->opp->funcs->opp_program_fmt(
1042 pipe_ctx->opp,
1043 &stream->bit_depth_params,
1044 &stream->clamping);
1045 return DC_OK;
1046 }
1047 /* TODO: move to stream encoder */
1048 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1049 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1050 BREAK_TO_DEBUGGER();
1051 return DC_ERROR_UNEXPECTED;
1052 }
1053
1054 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1055 stream->sink->link->link_enc->funcs->setup(
1056 stream->sink->link->link_enc,
1057 pipe_ctx->stream->signal);
1058
1059 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1060 pipe_ctx->stream_enc->funcs->setup_stereo_sync(
1061 pipe_ctx->stream_enc,
1062 pipe_ctx->tg->inst,
1063 stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1064
1065
1066 /*vbios crtc_source_selection and encoder_setup will override fmt_C*/
1067 pipe_ctx->opp->funcs->opp_program_fmt(
1068 pipe_ctx->opp,
1069 &stream->bit_depth_params,
1070 &stream->clamping);
1071
1072 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1073 pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
1074 pipe_ctx->stream_enc,
1075 &stream->public.timing,
1076 stream->public.output_color_space);
1077
1078 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1079 pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute(
1080 pipe_ctx->stream_enc,
1081 &stream->public.timing,
1082 stream->phy_pix_clk,
1083 pipe_ctx->audio != NULL);
1084
1085 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1086 pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute(
1087 pipe_ctx->stream_enc,
1088 &stream->public.timing,
1089 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1090 true : false);
1091
1092 if (!pipe_ctx_old->stream) {
1093 core_link_enable_stream(pipe_ctx);
1094
1095 resource_build_info_frame(pipe_ctx);
1096 dce110_update_info_frame(pipe_ctx);
1097 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1098 dce110_unblank_stream(pipe_ctx,
1099 &stream->sink->link->public.cur_link_settings);
1100 }
1101
1102 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1103 /* program_scaler and allocate_mem_input are not new asic */
1104 if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data,
1105 &pipe_ctx->scl_data,
1106 sizeof(struct scaler_data)) != 0)
1107 program_scaler(dc, pipe_ctx);
1108
1109 /* mst support - use total stream count */
1110 pipe_ctx->mi->funcs->allocate_mem_input(
1111 pipe_ctx->mi,
1112 stream->public.timing.h_total,
1113 stream->public.timing.v_total,
1114 stream->public.timing.pix_clk_khz,
1115 context->stream_count);
1116
1117 return DC_OK;
1118 }
1119
1120 /******************************************************************************/
1121
1122 static void power_down_encoders(struct core_dc *dc)
1123 {
1124 int i;
1125
1126 for (i = 0; i < dc->link_count; i++) {
1127 dc->links[i]->link_enc->funcs->disable_output(
1128 dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
1129 }
1130 }
1131
1132 static void power_down_controllers(struct core_dc *dc)
1133 {
1134 int i;
1135
1136 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1137 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1138 dc->res_pool->timing_generators[i]);
1139 }
1140 }
1141
1142 static void power_down_clock_sources(struct core_dc *dc)
1143 {
1144 int i;
1145
1146 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1147 dc->res_pool->dp_clock_source) == false)
1148 dm_error("Failed to power down pll! (dp clk src)\n");
1149
1150 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1151 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1152 dc->res_pool->clock_sources[i]) == false)
1153 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1154 }
1155 }
1156
1157 static void power_down_all_hw_blocks(struct core_dc *dc)
1158 {
1159 power_down_encoders(dc);
1160
1161 power_down_controllers(dc);
1162
1163 power_down_clock_sources(dc);
1164 }
1165
1166 static void disable_vga_and_power_gate_all_controllers(
1167 struct core_dc *dc)
1168 {
1169 int i;
1170 struct timing_generator *tg;
1171 struct dc_context *ctx = dc->ctx;
1172
1173 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1174 tg = dc->res_pool->timing_generators[i];
1175
1176 tg->funcs->disable_vga(tg);
1177
1178 /* Enable CLOCK gating for each pipe BEFORE controller
1179 * powergating. */
1180 enable_display_pipe_clock_gating(ctx,
1181 true);
1182
1183 dc->hwss.power_down_front_end(
1184 dc, &dc->current_context->res_ctx.pipe_ctx[i]);
1185 }
1186 }
1187
1188 /**
1189 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1190 * 1. Power down all DC HW blocks
1191 * 2. Disable VGA engine on all controllers
1192 * 3. Enable power gating for controller
1193 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1194 */
1195 void dce110_enable_accelerated_mode(struct core_dc *dc)
1196 {
1197 power_down_all_hw_blocks(dc);
1198
1199 disable_vga_and_power_gate_all_controllers(dc);
1200 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1201 }
1202
1203 static uint32_t compute_pstate_blackout_duration(
1204 struct bw_fixed blackout_duration,
1205 const struct core_stream *stream)
1206 {
1207 uint32_t total_dest_line_time_ns;
1208 uint32_t pstate_blackout_duration_ns;
1209
1210 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1211
1212 total_dest_line_time_ns = 1000000UL *
1213 stream->public.timing.h_total /
1214 stream->public.timing.pix_clk_khz +
1215 pstate_blackout_duration_ns;
1216
1217 return total_dest_line_time_ns;
1218 }
1219
1220 void dce110_set_displaymarks(
1221 const struct core_dc *dc,
1222 struct validate_context *context)
1223 {
1224 uint8_t i, num_pipes;
1225 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1226
1227 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1228 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1229 uint32_t total_dest_line_time_ns;
1230
1231 if (pipe_ctx->stream == NULL)
1232 continue;
1233
1234 total_dest_line_time_ns = compute_pstate_blackout_duration(
1235 dc->bw_vbios.blackout_duration, pipe_ctx->stream);
1236 pipe_ctx->mi->funcs->mem_input_program_display_marks(
1237 pipe_ctx->mi,
1238 context->bw_results.nbp_state_change_wm_ns[num_pipes],
1239 context->bw_results.stutter_exit_wm_ns[num_pipes],
1240 context->bw_results.urgent_wm_ns[num_pipes],
1241 total_dest_line_time_ns);
1242 if (i == underlay_idx) {
1243 num_pipes++;
1244 pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks(
1245 pipe_ctx->mi,
1246 context->bw_results.nbp_state_change_wm_ns[num_pipes],
1247 context->bw_results.stutter_exit_wm_ns[num_pipes],
1248 context->bw_results.urgent_wm_ns[num_pipes],
1249 total_dest_line_time_ns);
1250 }
1251 num_pipes++;
1252 }
1253 }
1254
1255 static void set_safe_displaymarks(struct resource_context *res_ctx)
1256 {
1257 int i;
1258 int underlay_idx = res_ctx->pool->underlay_pipe_index;
1259 struct bw_watermarks max_marks = {
1260 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1261 struct bw_watermarks nbp_marks = {
1262 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1263
1264 for (i = 0; i < MAX_PIPES; i++) {
1265 if (res_ctx->pipe_ctx[i].stream == NULL)
1266 continue;
1267
1268 res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks(
1269 res_ctx->pipe_ctx[i].mi,
1270 nbp_marks,
1271 max_marks,
1272 max_marks,
1273 MAX_WATERMARK);
1274 if (i == underlay_idx)
1275 res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks(
1276 res_ctx->pipe_ctx[i].mi,
1277 nbp_marks,
1278 max_marks,
1279 max_marks,
1280 MAX_WATERMARK);
1281 }
1282 }
1283
1284 static void switch_dp_clock_sources(
1285 const struct core_dc *dc,
1286 struct resource_context *res_ctx)
1287 {
1288 uint8_t i;
1289 for (i = 0; i < MAX_PIPES; i++) {
1290 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1291
1292 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1293 continue;
1294
1295 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1296 struct clock_source *clk_src =
1297 resource_find_used_clk_src_for_sharing(
1298 res_ctx, pipe_ctx);
1299
1300 if (clk_src &&
1301 clk_src != pipe_ctx->clock_source) {
1302 resource_unreference_clock_source(
1303 res_ctx, &pipe_ctx->clock_source);
1304 pipe_ctx->clock_source = clk_src;
1305 resource_reference_clock_source(res_ctx, clk_src);
1306
1307 dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
1308 }
1309 }
1310 }
1311 }
1312
1313 /*******************************************************************************
1314 * Public functions
1315 ******************************************************************************/
1316
1317 static void reset_single_pipe_hw_ctx(
1318 const struct core_dc *dc,
1319 struct pipe_ctx *pipe_ctx,
1320 struct validate_context *context)
1321 {
1322 core_link_disable_stream(pipe_ctx);
1323 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
1324 if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) {
1325 dm_error("DC: failed to blank crtc!\n");
1326 BREAK_TO_DEBUGGER();
1327 }
1328 pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
1329 pipe_ctx->mi->funcs->free_mem_input(
1330 pipe_ctx->mi, context->stream_count);
1331 resource_unreference_clock_source(
1332 &context->res_ctx, &pipe_ctx->clock_source);
1333
1334 dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx);
1335
1336 pipe_ctx->stream = NULL;
1337 }
1338
1339 static void set_drr(struct pipe_ctx **pipe_ctx,
1340 int num_pipes, int vmin, int vmax)
1341 {
1342 int i = 0;
1343 struct drr_params params = {0};
1344
1345 params.vertical_total_max = vmax;
1346 params.vertical_total_min = vmin;
1347
1348 /* TODO: If multiple pipes are to be supported, you need
1349 * some GSL stuff
1350 */
1351
1352 for (i = 0; i < num_pipes; i++) {
1353 pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
1354 }
1355 }
1356
1357 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1358 int num_pipes, int value)
1359 {
1360 unsigned int i;
1361
1362 for (i = 0; i < num_pipes; i++)
1363 pipe_ctx[i]->tg->funcs->
1364 set_static_screen_control(pipe_ctx[i]->tg, value);
1365 }
1366
1367 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1368 * may not be programmed yet.
1369 * TODO: after mode set, pre_mode_set = false,
1370 * may read PLL register to get pixel clock
1371 */
1372 static uint32_t get_max_pixel_clock_for_all_paths(
1373 struct core_dc *dc,
1374 struct validate_context *context,
1375 bool pre_mode_set)
1376 {
1377 uint32_t max_pix_clk = 0;
1378 int i;
1379
1380 if (!pre_mode_set) {
1381 /* TODO: read ASIC register to get pixel clock */
1382 ASSERT(0);
1383 }
1384
1385 for (i = 0; i < MAX_PIPES; i++) {
1386 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1387
1388 if (pipe_ctx->stream == NULL)
1389 continue;
1390
1391 /* do not check under lay */
1392 if (pipe_ctx->top_pipe)
1393 continue;
1394
1395 if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk)
1396 max_pix_clk =
1397 pipe_ctx->pix_clk_params.requested_pix_clk;
1398 }
1399
1400 if (max_pix_clk == 0)
1401 ASSERT(0);
1402
1403 return max_pix_clk;
1404 }
1405
1406 /* Find clock state based on clock requested. if clock value is 0, simply
1407 * set clock state as requested without finding clock state by clock value
1408 *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock.
1409 *
1410 * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value
1411 * etc support for dcn1.0
1412 */
1413 static void apply_min_clocks(
1414 struct core_dc *dc,
1415 struct validate_context *context,
1416 enum dm_pp_clocks_state *clocks_state,
1417 bool pre_mode_set)
1418 {
1419 struct state_dependent_clocks req_clocks = {0};
1420 struct pipe_ctx *pipe_ctx;
1421 int i;
1422
1423 for (i = 0; i < MAX_PIPES; i++) {
1424 pipe_ctx = &context->res_ctx.pipe_ctx[i];
1425 if (pipe_ctx->dis_clk != NULL)
1426 break;
1427 }
1428
1429 if (!pre_mode_set) {
1430 /* set clock_state without verification */
1431 if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
1432 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1433 pipe_ctx->dis_clk, *clocks_state);
1434 return;
1435 }
1436
1437 /* TODO: This is incorrect. Figure out how to fix. */
1438 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1439 pipe_ctx->dis_clk,
1440 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1441 pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz,
1442 pre_mode_set,
1443 false);
1444
1445 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1446 pipe_ctx->dis_clk,
1447 DM_PP_CLOCK_TYPE_PIXELCLK,
1448 pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1449 pre_mode_set,
1450 false);
1451
1452 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1453 pipe_ctx->dis_clk,
1454 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1455 pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1456 pre_mode_set,
1457 false);
1458 return;
1459 }
1460
1461 /* get the required state based on state dependent clocks:
1462 * display clock and pixel clock
1463 */
1464 req_clocks.display_clk_khz = context->dispclk_khz;
1465
1466 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1467 dc, context, true);
1468
1469 if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) {
1470 *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state(
1471 pipe_ctx->dis_clk, &req_clocks);
1472 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1473 pipe_ctx->dis_clk, *clocks_state);
1474 } else {
1475 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1476 pipe_ctx->dis_clk,
1477 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1478 req_clocks.display_clk_khz,
1479 pre_mode_set,
1480 false);
1481
1482 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1483 pipe_ctx->dis_clk,
1484 DM_PP_CLOCK_TYPE_PIXELCLK,
1485 req_clocks.pixel_clk_khz,
1486 pre_mode_set,
1487 false);
1488
1489 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1490 pipe_ctx->dis_clk,
1491 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1492 req_clocks.pixel_clk_khz,
1493 pre_mode_set,
1494 false);
1495 }
1496 }
1497
1498 static enum dc_status apply_ctx_to_hw_fpga(
1499 struct core_dc *dc,
1500 struct validate_context *context)
1501 {
1502 enum dc_status status = DC_ERROR_UNEXPECTED;
1503 int i;
1504
1505 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1506 struct pipe_ctx *pipe_ctx_old =
1507 &dc->current_context->res_ctx.pipe_ctx[i];
1508 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1509
1510 if (pipe_ctx->stream == NULL)
1511 continue;
1512
1513 if (pipe_ctx->stream == pipe_ctx_old->stream)
1514 continue;
1515
1516 status = apply_single_controller_ctx_to_hw(
1517 pipe_ctx,
1518 context,
1519 dc);
1520
1521 if (status != DC_OK)
1522 return status;
1523 }
1524
1525 return DC_OK;
1526 }
1527
1528 static void reset_hw_ctx_wrap(
1529 struct core_dc *dc,
1530 struct validate_context *context)
1531 {
1532 int i;
1533
1534 /* Reset old context */
1535 /* look up the targets that have been removed since last commit */
1536 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1537 struct pipe_ctx *pipe_ctx_old =
1538 &dc->current_context->res_ctx.pipe_ctx[i];
1539 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1540
1541 /* Note: We need to disable output if clock sources change,
1542 * since bios does optimization and doesn't apply if changing
1543 * PHY when not already disabled.
1544 */
1545
1546 /* Skip underlay pipe since it will be handled in commit surface*/
1547 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1548 continue;
1549
1550 if (!pipe_ctx->stream ||
1551 pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1552 reset_single_pipe_hw_ctx(
1553 dc, pipe_ctx_old, dc->current_context);
1554 }
1555 }
1556
1557
1558 enum dc_status dce110_apply_ctx_to_hw(
1559 struct core_dc *dc,
1560 struct validate_context *context)
1561 {
1562 struct dc_bios *dcb = dc->ctx->dc_bios;
1563 enum dc_status status;
1564 int i;
1565 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1566
1567 /* Reset old context */
1568 /* look up the targets that have been removed since last commit */
1569 dc->hwss.reset_hw_ctx_wrap(dc, context);
1570
1571 /* Skip applying if no targets */
1572 if (context->stream_count <= 0)
1573 return DC_OK;
1574
1575 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1576 apply_ctx_to_hw_fpga(dc, context);
1577 return DC_OK;
1578 }
1579
1580 /* Apply new context */
1581 dcb->funcs->set_scratch_critical_state(dcb, true);
1582
1583 /* below is for real asic only */
1584 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1585 struct pipe_ctx *pipe_ctx_old =
1586 &dc->current_context->res_ctx.pipe_ctx[i];
1587 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1588
1589 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1590 continue;
1591
1592 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1593 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1594 dce_crtc_switch_to_clk_src(dc->hwseq,
1595 pipe_ctx->clock_source, i);
1596 continue;
1597 }
1598
1599 dc->hwss.enable_display_power_gating(
1600 dc, i, dc->ctx->dc_bios,
1601 PIPE_GATING_CONTROL_DISABLE);
1602 }
1603
1604 set_safe_displaymarks(&context->res_ctx);
1605 /*TODO: when pplib works*/
1606 apply_min_clocks(dc, context, &clocks_state, true);
1607
1608 if (context->dispclk_khz
1609 > dc->current_context->dispclk_khz) {
1610 context->res_ctx.pool->display_clock->funcs->set_clock(
1611 context->res_ctx.pool->display_clock,
1612 context->dispclk_khz * 115 / 100);
1613 }
1614 /* program audio wall clock. use HDMI as clock source if HDMI
1615 * audio active. Otherwise, use DP as clock source
1616 * first, loop to find any HDMI audio, if not, loop find DP audio
1617 */
1618 /* Setup audio rate clock source */
1619 /* Issue:
1620 * Audio lag happened on DP monitor when unplug a HDMI monitor
1621 *
1622 * Cause:
1623 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1624 * is set to either dto0 or dto1, audio should work fine.
1625 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1626 * set to dto0 will cause audio lag.
1627 *
1628 * Solution:
1629 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1630 * find first available pipe with audio, setup audio wall DTO per topology
1631 * instead of per pipe.
1632 */
1633 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1634 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1635
1636 if (pipe_ctx->stream == NULL)
1637 continue;
1638
1639 if (pipe_ctx->top_pipe)
1640 continue;
1641
1642 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1643 continue;
1644
1645 if (pipe_ctx->audio != NULL) {
1646 struct audio_output audio_output;
1647
1648 build_audio_output(pipe_ctx, &audio_output);
1649
1650 pipe_ctx->audio->funcs->wall_dto_setup(
1651 pipe_ctx->audio,
1652 pipe_ctx->stream->signal,
1653 &audio_output.crtc_info,
1654 &audio_output.pll_info);
1655 break;
1656 }
1657 }
1658
1659 /* no HDMI audio is found, try DP audio */
1660 if (i == context->res_ctx.pool->pipe_count) {
1661 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1662 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1663
1664 if (pipe_ctx->stream == NULL)
1665 continue;
1666
1667 if (pipe_ctx->top_pipe)
1668 continue;
1669
1670 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1671 continue;
1672
1673 if (pipe_ctx->audio != NULL) {
1674 struct audio_output audio_output;
1675
1676 build_audio_output(pipe_ctx, &audio_output);
1677
1678 pipe_ctx->audio->funcs->wall_dto_setup(
1679 pipe_ctx->audio,
1680 pipe_ctx->stream->signal,
1681 &audio_output.crtc_info,
1682 &audio_output.pll_info);
1683 break;
1684 }
1685 }
1686 }
1687
1688 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1689 struct pipe_ctx *pipe_ctx_old =
1690 &dc->current_context->res_ctx.pipe_ctx[i];
1691 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1692
1693 if (pipe_ctx->stream == NULL)
1694 continue;
1695
1696 if (pipe_ctx->stream == pipe_ctx_old->stream)
1697 continue;
1698
1699 if (pipe_ctx->stream && pipe_ctx_old->stream
1700 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1701 continue;
1702
1703 if (pipe_ctx->top_pipe)
1704 continue;
1705
1706 if (context->res_ctx.pipe_ctx[i].audio != NULL) {
1707
1708 struct audio_output audio_output;
1709
1710 build_audio_output(pipe_ctx, &audio_output);
1711
1712 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1713 pipe_ctx->stream_enc->funcs->dp_audio_setup(
1714 pipe_ctx->stream_enc,
1715 pipe_ctx->audio->inst,
1716 &pipe_ctx->stream->public.audio_info);
1717 else
1718 pipe_ctx->stream_enc->funcs->hdmi_audio_setup(
1719 pipe_ctx->stream_enc,
1720 pipe_ctx->audio->inst,
1721 &pipe_ctx->stream->public.audio_info,
1722 &audio_output.crtc_info);
1723
1724 pipe_ctx->audio->funcs->az_configure(
1725 pipe_ctx->audio,
1726 pipe_ctx->stream->signal,
1727 &audio_output.crtc_info,
1728 &pipe_ctx->stream->public.audio_info);
1729 }
1730
1731 status = apply_single_controller_ctx_to_hw(
1732 pipe_ctx,
1733 context,
1734 dc);
1735
1736 if (dc->hwss.power_on_front_end)
1737 dc->hwss.power_on_front_end(dc, pipe_ctx, context);
1738
1739 if (DC_OK != status)
1740 return status;
1741 }
1742
1743 dc->hwss.set_bandwidth(dc, context, true);
1744
1745 /* to save power */
1746 apply_min_clocks(dc, context, &clocks_state, false);
1747
1748 dcb->funcs->set_scratch_critical_state(dcb, false);
1749
1750 switch_dp_clock_sources(dc, &context->res_ctx);
1751
1752
1753 return DC_OK;
1754 }
1755
1756 /*******************************************************************************
1757 * Front End programming
1758 ******************************************************************************/
1759 static void set_default_colors(struct pipe_ctx *pipe_ctx)
1760 {
1761 struct default_adjustment default_adjust = { 0 };
1762
1763 default_adjust.force_hw_default = false;
1764 if (pipe_ctx->surface == NULL)
1765 default_adjust.in_color_space = COLOR_SPACE_SRGB;
1766 else
1767 default_adjust.in_color_space =
1768 pipe_ctx->surface->public.color_space;
1769 if (pipe_ctx->stream == NULL)
1770 default_adjust.out_color_space = COLOR_SPACE_SRGB;
1771 else
1772 default_adjust.out_color_space =
1773 pipe_ctx->stream->public.output_color_space;
1774 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
1775 default_adjust.surface_pixel_format = pipe_ctx->scl_data.format;
1776
1777 /* display color depth */
1778 default_adjust.color_depth =
1779 pipe_ctx->stream->public.timing.display_color_depth;
1780
1781 /* Lb color depth */
1782 default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth;
1783
1784 pipe_ctx->opp->funcs->opp_set_csc_default(
1785 pipe_ctx->opp, &default_adjust);
1786 }
1787
1788
1789 /*******************************************************************************
1790 * In order to turn on/off specific surface we will program
1791 * Blender + CRTC
1792 *
1793 * In case that we have two surfaces and they have a different visibility
1794 * we can't turn off the CRTC since it will turn off the entire display
1795 *
1796 * |----------------------------------------------- |
1797 * |bottom pipe|curr pipe | | |
1798 * |Surface |Surface | Blender | CRCT |
1799 * |visibility |visibility | Configuration| |
1800 * |------------------------------------------------|
1801 * | off | off | CURRENT_PIPE | blank |
1802 * | off | on | CURRENT_PIPE | unblank |
1803 * | on | off | OTHER_PIPE | unblank |
1804 * | on | on | BLENDING | unblank |
1805 * -------------------------------------------------|
1806 *
1807 ******************************************************************************/
1808 static void program_surface_visibility(const struct core_dc *dc,
1809 struct pipe_ctx *pipe_ctx)
1810 {
1811 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
1812 bool blank_target = false;
1813
1814 if (pipe_ctx->bottom_pipe) {
1815
1816 /* For now we are supporting only two pipes */
1817 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
1818
1819 if (pipe_ctx->bottom_pipe->surface->public.visible) {
1820 if (pipe_ctx->surface->public.visible)
1821 blender_mode = BLND_MODE_BLENDING;
1822 else
1823 blender_mode = BLND_MODE_OTHER_PIPE;
1824
1825 } else if (!pipe_ctx->surface->public.visible)
1826 blank_target = true;
1827
1828 } else if (!pipe_ctx->surface->public.visible)
1829 blank_target = true;
1830
1831 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
1832 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target);
1833
1834 }
1835
1836 /**
1837 * TODO REMOVE, USE UPDATE INSTEAD
1838 */
1839 static void set_plane_config(
1840 const struct core_dc *dc,
1841 struct pipe_ctx *pipe_ctx,
1842 struct resource_context *res_ctx)
1843 {
1844 struct mem_input *mi = pipe_ctx->mi;
1845 struct core_surface *surface = pipe_ctx->surface;
1846 struct xfm_grph_csc_adjustment adjust;
1847 struct out_csc_color_matrix tbl_entry;
1848 unsigned int i;
1849
1850 memset(&adjust, 0, sizeof(adjust));
1851 memset(&tbl_entry, 0, sizeof(tbl_entry));
1852 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1853
1854 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
1855
1856 set_default_colors(pipe_ctx);
1857 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
1858 == true) {
1859 tbl_entry.color_space =
1860 pipe_ctx->stream->public.output_color_space;
1861
1862 for (i = 0; i < 12; i++)
1863 tbl_entry.regval[i] =
1864 pipe_ctx->stream->public.csc_color_matrix.matrix[i];
1865
1866 pipe_ctx->opp->funcs->opp_set_csc_adjustment
1867 (pipe_ctx->opp, &tbl_entry);
1868 }
1869
1870 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
1871 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1872 adjust.temperature_matrix[0] =
1873 pipe_ctx->stream->
1874 public.gamut_remap_matrix.matrix[0];
1875 adjust.temperature_matrix[1] =
1876 pipe_ctx->stream->
1877 public.gamut_remap_matrix.matrix[1];
1878 adjust.temperature_matrix[2] =
1879 pipe_ctx->stream->
1880 public.gamut_remap_matrix.matrix[2];
1881 adjust.temperature_matrix[3] =
1882 pipe_ctx->stream->
1883 public.gamut_remap_matrix.matrix[4];
1884 adjust.temperature_matrix[4] =
1885 pipe_ctx->stream->
1886 public.gamut_remap_matrix.matrix[5];
1887 adjust.temperature_matrix[5] =
1888 pipe_ctx->stream->
1889 public.gamut_remap_matrix.matrix[6];
1890 adjust.temperature_matrix[6] =
1891 pipe_ctx->stream->
1892 public.gamut_remap_matrix.matrix[8];
1893 adjust.temperature_matrix[7] =
1894 pipe_ctx->stream->
1895 public.gamut_remap_matrix.matrix[9];
1896 adjust.temperature_matrix[8] =
1897 pipe_ctx->stream->
1898 public.gamut_remap_matrix.matrix[10];
1899 }
1900
1901 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
1902
1903 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1904 program_scaler(dc, pipe_ctx);
1905
1906 program_surface_visibility(dc, pipe_ctx);
1907
1908 mi->funcs->mem_input_program_surface_config(
1909 mi,
1910 surface->public.format,
1911 &surface->public.tiling_info,
1912 &surface->public.plane_size,
1913 surface->public.rotation,
1914 NULL,
1915 false,
1916 pipe_ctx->surface->public.visible);
1917
1918 if (dc->public.config.gpu_vm_support)
1919 mi->funcs->mem_input_program_pte_vm(
1920 pipe_ctx->mi,
1921 surface->public.format,
1922 &surface->public.tiling_info,
1923 surface->public.rotation);
1924 }
1925
1926 static void update_plane_addr(const struct core_dc *dc,
1927 struct pipe_ctx *pipe_ctx)
1928 {
1929 struct core_surface *surface = pipe_ctx->surface;
1930
1931 if (surface == NULL)
1932 return;
1933
1934 pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
1935 pipe_ctx->mi,
1936 &surface->public.address,
1937 surface->public.flip_immediate);
1938
1939 surface->status.requested_address = surface->public.address;
1940 }
1941
1942 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
1943 {
1944 struct core_surface *surface = pipe_ctx->surface;
1945
1946 if (surface == NULL)
1947 return;
1948
1949 surface->status.is_flip_pending =
1950 pipe_ctx->mi->funcs->mem_input_is_flip_pending(
1951 pipe_ctx->mi);
1952
1953 if (surface->status.is_flip_pending && !surface->public.visible)
1954 pipe_ctx->mi->current_address = pipe_ctx->mi->request_address;
1955
1956 surface->status.current_address = pipe_ctx->mi->current_address;
1957 }
1958
1959 void dce110_power_down(struct core_dc *dc)
1960 {
1961 power_down_all_hw_blocks(dc);
1962 disable_vga_and_power_gate_all_controllers(dc);
1963 }
1964
1965 static bool wait_for_reset_trigger_to_occur(
1966 struct dc_context *dc_ctx,
1967 struct timing_generator *tg)
1968 {
1969 bool rc = false;
1970
1971 /* To avoid endless loop we wait at most
1972 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1973 const uint32_t frames_to_wait_on_triggered_reset = 10;
1974 uint32_t i;
1975
1976 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1977
1978 if (!tg->funcs->is_counter_moving(tg)) {
1979 DC_ERROR("TG counter is not moving!\n");
1980 break;
1981 }
1982
1983 if (tg->funcs->did_triggered_reset_occur(tg)) {
1984 rc = true;
1985 /* usually occurs at i=1 */
1986 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1987 i);
1988 break;
1989 }
1990
1991 /* Wait for one frame. */
1992 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1993 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1994 }
1995
1996 if (false == rc)
1997 DC_ERROR("GSL: Timeout on reset trigger!\n");
1998
1999 return rc;
2000 }
2001
2002 /* Enable timing synchronization for a group of Timing Generators. */
2003 static void dce110_enable_timing_synchronization(
2004 struct core_dc *dc,
2005 int group_index,
2006 int group_size,
2007 struct pipe_ctx *grouped_pipes[])
2008 {
2009 struct dc_context *dc_ctx = dc->ctx;
2010 struct dcp_gsl_params gsl_params = { 0 };
2011 int i;
2012
2013 DC_SYNC_INFO("GSL: Setting-up...\n");
2014
2015 /* Designate a single TG in the group as a master.
2016 * Since HW doesn't care which one, we always assign
2017 * the 1st one in the group. */
2018 gsl_params.gsl_group = 0;
2019 gsl_params.gsl_master = grouped_pipes[0]->tg->inst;
2020
2021 for (i = 0; i < group_size; i++)
2022 grouped_pipes[i]->tg->funcs->setup_global_swap_lock(
2023 grouped_pipes[i]->tg, &gsl_params);
2024
2025 /* Reset slave controllers on master VSync */
2026 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2027
2028 for (i = 1 /* skip the master */; i < group_size; i++)
2029 grouped_pipes[i]->tg->funcs->enable_reset_trigger(
2030 grouped_pipes[i]->tg, gsl_params.gsl_group);
2031
2032
2033
2034 for (i = 1 /* skip the master */; i < group_size; i++) {
2035 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2036 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg);
2037 /* Regardless of success of the wait above, remove the reset or
2038 * the driver will start timing out on Display requests. */
2039 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2040 grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg);
2041 }
2042
2043
2044 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2045 * is that the sync'ed displays will not drift out of sync over time*/
2046 DC_SYNC_INFO("GSL: Restoring register states.\n");
2047 for (i = 0; i < group_size; i++)
2048 grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg);
2049
2050 DC_SYNC_INFO("GSL: Set-up complete.\n");
2051 }
2052
2053 static void init_hw(struct core_dc *dc)
2054 {
2055 int i;
2056 struct dc_bios *bp;
2057 struct transform *xfm;
2058 struct abm *abm;
2059
2060 bp = dc->ctx->dc_bios;
2061 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2062 xfm = dc->res_pool->transforms[i];
2063 xfm->funcs->transform_reset(xfm);
2064
2065 dc->hwss.enable_display_power_gating(
2066 dc, i, bp,
2067 PIPE_GATING_CONTROL_INIT);
2068 dc->hwss.enable_display_power_gating(
2069 dc, i, bp,
2070 PIPE_GATING_CONTROL_DISABLE);
2071 dc->hwss.enable_display_pipe_clock_gating(
2072 dc->ctx,
2073 true);
2074 }
2075
2076 dce_clock_gating_power_up(dc->hwseq, false);
2077 /***************************************/
2078
2079 for (i = 0; i < dc->link_count; i++) {
2080 /****************************************/
2081 /* Power up AND update implementation according to the
2082 * required signal (which may be different from the
2083 * default signal on connector). */
2084 struct core_link *link = dc->links[i];
2085 link->link_enc->funcs->hw_init(link->link_enc);
2086 }
2087
2088 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2089 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2090
2091 tg->funcs->disable_vga(tg);
2092
2093 /* Blank controller using driver code instead of
2094 * command table. */
2095 tg->funcs->set_blank(tg, true);
2096 hwss_wait_for_blank_complete(tg);
2097 }
2098
2099 for (i = 0; i < dc->res_pool->audio_count; i++) {
2100 struct audio *audio = dc->res_pool->audios[i];
2101 audio->funcs->hw_init(audio);
2102 }
2103
2104 abm = dc->res_pool->abm;
2105 if (abm != NULL) {
2106 abm->funcs->init_backlight(abm);
2107 abm->funcs->abm_init(abm);
2108 }
2109 }
2110
2111 void dce110_fill_display_configs(
2112 const struct validate_context *context,
2113 struct dm_pp_display_configuration *pp_display_cfg)
2114 {
2115 int j;
2116 int num_cfgs = 0;
2117
2118 for (j = 0; j < context->stream_count; j++) {
2119 int k;
2120
2121 const struct core_stream *stream = context->streams[j];
2122 struct dm_pp_single_disp_config *cfg =
2123 &pp_display_cfg->disp_configs[num_cfgs];
2124 const struct pipe_ctx *pipe_ctx = NULL;
2125
2126 for (k = 0; k < MAX_PIPES; k++)
2127 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2128 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2129 break;
2130 }
2131
2132 ASSERT(pipe_ctx != NULL);
2133
2134 num_cfgs++;
2135 cfg->signal = pipe_ctx->stream->signal;
2136 cfg->pipe_idx = pipe_ctx->pipe_idx;
2137 cfg->src_height = stream->public.src.height;
2138 cfg->src_width = stream->public.src.width;
2139 cfg->ddi_channel_mapping =
2140 stream->sink->link->ddi_channel_mapping.raw;
2141 cfg->transmitter =
2142 stream->sink->link->link_enc->transmitter;
2143 cfg->link_settings.lane_count =
2144 stream->sink->link->public.cur_link_settings.lane_count;
2145 cfg->link_settings.link_rate =
2146 stream->sink->link->public.cur_link_settings.link_rate;
2147 cfg->link_settings.link_spread =
2148 stream->sink->link->public.cur_link_settings.link_spread;
2149 cfg->sym_clock = stream->phy_pix_clk;
2150 /* Round v_refresh*/
2151 cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
2152 cfg->v_refresh /= stream->public.timing.h_total;
2153 cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
2154 / stream->public.timing.v_total;
2155 }
2156
2157 pp_display_cfg->display_count = num_cfgs;
2158 }
2159
2160 uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
2161 {
2162 uint8_t j;
2163 uint32_t min_vertical_blank_time = -1;
2164
2165 for (j = 0; j < context->stream_count; j++) {
2166 const struct dc_stream *stream = &context->streams[j]->public;
2167 uint32_t vertical_blank_in_pixels = 0;
2168 uint32_t vertical_blank_time = 0;
2169
2170 vertical_blank_in_pixels = stream->timing.h_total *
2171 (stream->timing.v_total
2172 - stream->timing.v_addressable);
2173
2174 vertical_blank_time = vertical_blank_in_pixels
2175 * 1000 / stream->timing.pix_clk_khz;
2176
2177 if (min_vertical_blank_time > vertical_blank_time)
2178 min_vertical_blank_time = vertical_blank_time;
2179 }
2180
2181 return min_vertical_blank_time;
2182 }
2183
2184 static int determine_sclk_from_bounding_box(
2185 const struct core_dc *dc,
2186 int required_sclk)
2187 {
2188 int i;
2189
2190 /*
2191 * Some asics do not give us sclk levels, so we just report the actual
2192 * required sclk
2193 */
2194 if (dc->sclk_lvls.num_levels == 0)
2195 return required_sclk;
2196
2197 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2198 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2199 return dc->sclk_lvls.clocks_in_khz[i];
2200 }
2201 /*
2202 * even maximum level could not satisfy requirement, this
2203 * is unexpected at this stage, should have been caught at
2204 * validation time
2205 */
2206 ASSERT(0);
2207 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2208 }
2209
2210 static void pplib_apply_display_requirements(
2211 struct core_dc *dc,
2212 struct validate_context *context)
2213 {
2214 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2215
2216 pp_display_cfg->all_displays_in_sync =
2217 context->bw_results.all_displays_in_sync;
2218 pp_display_cfg->nb_pstate_switch_disable =
2219 context->bw_results.nbp_state_change_enable == false;
2220 pp_display_cfg->cpu_cc6_disable =
2221 context->bw_results.cpuc_state_change_enable == false;
2222 pp_display_cfg->cpu_pstate_disable =
2223 context->bw_results.cpup_state_change_enable == false;
2224 pp_display_cfg->cpu_pstate_separation_time =
2225 context->bw_results.blackout_recovery_time_us;
2226
2227 pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
2228 / MEMORY_TYPE_MULTIPLIER;
2229
2230 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2231 dc,
2232 context->bw_results.required_sclk);
2233
2234 pp_display_cfg->min_engine_clock_deep_sleep_khz
2235 = context->bw_results.required_sclk_deep_sleep;
2236
2237 pp_display_cfg->avail_mclk_switch_time_us =
2238 dce110_get_min_vblank_time_us(context);
2239 /* TODO: dce11.2*/
2240 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2241
2242 pp_display_cfg->disp_clk_khz = context->dispclk_khz;
2243
2244 dce110_fill_display_configs(context, pp_display_cfg);
2245
2246 /* TODO: is this still applicable?*/
2247 if (pp_display_cfg->display_count == 1) {
2248 const struct dc_crtc_timing *timing =
2249 &context->streams[0]->public.timing;
2250
2251 pp_display_cfg->crtc_index =
2252 pp_display_cfg->disp_configs[0].pipe_idx;
2253 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2254 / timing->pix_clk_khz;
2255 }
2256
2257 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2258 struct dm_pp_display_configuration)) != 0)
2259 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2260
2261 dc->prev_display_config = *pp_display_cfg;
2262 }
2263
2264 static void dce110_set_bandwidth(
2265 struct core_dc *dc,
2266 struct validate_context *context,
2267 bool decrease_allowed)
2268 {
2269 dc->hwss.set_displaymarks(dc, context);
2270
2271 if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
2272 context->res_ctx.pool->display_clock->funcs->set_clock(
2273 context->res_ctx.pool->display_clock,
2274 context->dispclk_khz * 115 / 100);
2275 dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
2276 dc->current_context->dispclk_khz = context->dispclk_khz;
2277 }
2278
2279 pplib_apply_display_requirements(dc, context);
2280 }
2281
2282 static void dce110_program_front_end_for_pipe(
2283 struct core_dc *dc, struct pipe_ctx *pipe_ctx)
2284 {
2285 struct mem_input *mi = pipe_ctx->mi;
2286 struct pipe_ctx *old_pipe = NULL;
2287 struct core_surface *surface = pipe_ctx->surface;
2288 struct xfm_grph_csc_adjustment adjust;
2289 struct out_csc_color_matrix tbl_entry;
2290 unsigned int i;
2291
2292 memset(&tbl_entry, 0, sizeof(tbl_entry));
2293
2294 if (dc->current_context)
2295 old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2296
2297 memset(&adjust, 0, sizeof(adjust));
2298 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2299
2300 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2301
2302 set_default_colors(pipe_ctx);
2303 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
2304 == true) {
2305 tbl_entry.color_space =
2306 pipe_ctx->stream->public.output_color_space;
2307
2308 for (i = 0; i < 12; i++)
2309 tbl_entry.regval[i] =
2310 pipe_ctx->stream->public.csc_color_matrix.matrix[i];
2311
2312 pipe_ctx->opp->funcs->opp_set_csc_adjustment
2313 (pipe_ctx->opp, &tbl_entry);
2314 }
2315
2316 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
2317 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2318 adjust.temperature_matrix[0] =
2319 pipe_ctx->stream->
2320 public.gamut_remap_matrix.matrix[0];
2321 adjust.temperature_matrix[1] =
2322 pipe_ctx->stream->
2323 public.gamut_remap_matrix.matrix[1];
2324 adjust.temperature_matrix[2] =
2325 pipe_ctx->stream->
2326 public.gamut_remap_matrix.matrix[2];
2327 adjust.temperature_matrix[3] =
2328 pipe_ctx->stream->
2329 public.gamut_remap_matrix.matrix[4];
2330 adjust.temperature_matrix[4] =
2331 pipe_ctx->stream->
2332 public.gamut_remap_matrix.matrix[5];
2333 adjust.temperature_matrix[5] =
2334 pipe_ctx->stream->
2335 public.gamut_remap_matrix.matrix[6];
2336 adjust.temperature_matrix[6] =
2337 pipe_ctx->stream->
2338 public.gamut_remap_matrix.matrix[8];
2339 adjust.temperature_matrix[7] =
2340 pipe_ctx->stream->
2341 public.gamut_remap_matrix.matrix[9];
2342 adjust.temperature_matrix[8] =
2343 pipe_ctx->stream->
2344 public.gamut_remap_matrix.matrix[10];
2345 }
2346
2347 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
2348
2349 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2350 if (old_pipe && memcmp(&old_pipe->scl_data,
2351 &pipe_ctx->scl_data,
2352 sizeof(struct scaler_data)) != 0)
2353 program_scaler(dc, pipe_ctx);
2354
2355 mi->funcs->mem_input_program_surface_config(
2356 mi,
2357 surface->public.format,
2358 &surface->public.tiling_info,
2359 &surface->public.plane_size,
2360 surface->public.rotation,
2361 NULL,
2362 false,
2363 pipe_ctx->surface->public.visible);
2364
2365 if (dc->public.config.gpu_vm_support)
2366 mi->funcs->mem_input_program_pte_vm(
2367 pipe_ctx->mi,
2368 surface->public.format,
2369 &surface->public.tiling_info,
2370 surface->public.rotation);
2371
2372 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2373 "Pipe:%d 0x%x: addr hi:0x%x, "
2374 "addr low:0x%x, "
2375 "src: %d, %d, %d,"
2376 " %d; dst: %d, %d, %d, %d;"
2377 "clip: %d, %d, %d, %d\n",
2378 pipe_ctx->pipe_idx,
2379 pipe_ctx->surface,
2380 pipe_ctx->surface->public.address.grph.addr.high_part,
2381 pipe_ctx->surface->public.address.grph.addr.low_part,
2382 pipe_ctx->surface->public.src_rect.x,
2383 pipe_ctx->surface->public.src_rect.y,
2384 pipe_ctx->surface->public.src_rect.width,
2385 pipe_ctx->surface->public.src_rect.height,
2386 pipe_ctx->surface->public.dst_rect.x,
2387 pipe_ctx->surface->public.dst_rect.y,
2388 pipe_ctx->surface->public.dst_rect.width,
2389 pipe_ctx->surface->public.dst_rect.height,
2390 pipe_ctx->surface->public.clip_rect.x,
2391 pipe_ctx->surface->public.clip_rect.y,
2392 pipe_ctx->surface->public.clip_rect.width,
2393 pipe_ctx->surface->public.clip_rect.height);
2394
2395 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2396 "Pipe %d: width, height, x, y\n"
2397 "viewport:%d, %d, %d, %d\n"
2398 "recout: %d, %d, %d, %d\n",
2399 pipe_ctx->pipe_idx,
2400 pipe_ctx->scl_data.viewport.width,
2401 pipe_ctx->scl_data.viewport.height,
2402 pipe_ctx->scl_data.viewport.x,
2403 pipe_ctx->scl_data.viewport.y,
2404 pipe_ctx->scl_data.recout.width,
2405 pipe_ctx->scl_data.recout.height,
2406 pipe_ctx->scl_data.recout.x,
2407 pipe_ctx->scl_data.recout.y);
2408 }
2409
2410 static void dce110_apply_ctx_for_surface(
2411 struct core_dc *dc,
2412 struct core_surface *surface,
2413 struct validate_context *context)
2414 {
2415 int i;
2416
2417 /* TODO remove when removing the surface reset workaroud*/
2418 if (!surface)
2419 return;
2420
2421 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
2422 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2423
2424 if (pipe_ctx->surface != surface)
2425 continue;
2426
2427 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2428 program_surface_visibility(dc, pipe_ctx);
2429
2430 }
2431 }
2432
2433 static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
2434 {
2435 int i;
2436
2437 for (i = 0; i < dc->res_pool->pipe_count; i++)
2438 if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe)
2439 break;
2440
2441 if (i == dc->res_pool->pipe_count)
2442 return;
2443
2444 dc->hwss.enable_display_power_gating(
2445 dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2446 if (pipe->xfm)
2447 pipe->xfm->funcs->transform_reset(pipe->xfm);
2448 memset(&pipe->scl_data, 0, sizeof(struct scaler_data));
2449 }
2450
2451 static const struct hw_sequencer_funcs dce110_funcs = {
2452 .init_hw = init_hw,
2453 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2454 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2455 .set_plane_config = set_plane_config,
2456 .update_plane_addr = update_plane_addr,
2457 .update_pending_status = dce110_update_pending_status,
2458 .set_input_transfer_func = dce110_set_input_transfer_func,
2459 .set_output_transfer_func = dce110_set_output_transfer_func,
2460 .power_down = dce110_power_down,
2461 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2462 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2463 .update_info_frame = dce110_update_info_frame,
2464 .enable_stream = dce110_enable_stream,
2465 .disable_stream = dce110_disable_stream,
2466 .unblank_stream = dce110_unblank_stream,
2467 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2468 .enable_display_power_gating = dce110_enable_display_power_gating,
2469 .power_down_front_end = dce110_power_down_fe,
2470 .pipe_control_lock = dce_pipe_control_lock,
2471 .set_displaymarks = dce110_set_displaymarks,
2472 .set_bandwidth = dce110_set_bandwidth,
2473 .set_drr = set_drr,
2474 .set_static_screen_control = set_static_screen_control,
2475 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2476 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
2477 };
2478
2479 bool dce110_hw_sequencer_construct(struct core_dc *dc)
2480 {
2481 dc->hwss = dce110_funcs;
2482
2483 return true;
2484 }
2485
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