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drm/amd/display: fix HDMI 12bits last two bits are zero issue
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "resource.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35
36 #ifdef ENABLE_FBC
37 #include "dce110_compressor.h"
38 #endif
39
40 #include "bios/bios_parser_helper.h"
41 #include "timing_generator.h"
42 #include "mem_input.h"
43 #include "opp.h"
44 #include "ipp.h"
45 #include "transform.h"
46 #include "stream_encoder.h"
47 #include "link_encoder.h"
48 #include "clock_source.h"
49 #include "abm.h"
50 #include "audio.h"
51 #include "dce/dce_hwseq.h"
52 #include "reg_helper.h"
53
54 /* include DCE11 register header files */
55 #include "dce/dce_11_0_d.h"
56 #include "dce/dce_11_0_sh_mask.h"
57 #include "custom_float.h"
58
59 struct dce110_hw_seq_reg_offsets {
60 uint32_t crtc;
61 };
62
63 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
64 {
65 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
66 },
67 {
68 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
69 },
70 {
71 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
72 },
73 {
74 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
75 }
76 };
77
78 #define HW_REG_BLND(reg, id)\
79 (reg + reg_offsets[id].blnd)
80
81 #define HW_REG_CRTC(reg, id)\
82 (reg + reg_offsets[id].crtc)
83
84 #define MAX_WATERMARK 0xFFFF
85 #define SAFE_NBP_MARK 0x7FFF
86
87 /*******************************************************************************
88 * Private definitions
89 ******************************************************************************/
90 /***************************PIPE_CONTROL***********************************/
91 static void dce110_init_pte(struct dc_context *ctx)
92 {
93 uint32_t addr;
94 uint32_t value = 0;
95 uint32_t chunk_int = 0;
96 uint32_t chunk_mul = 0;
97
98 addr = mmUNP_DVMM_PTE_CONTROL;
99 value = dm_read_reg(ctx, addr);
100
101 set_reg_field_value(
102 value,
103 0,
104 DVMM_PTE_CONTROL,
105 DVMM_USE_SINGLE_PTE);
106
107 set_reg_field_value(
108 value,
109 1,
110 DVMM_PTE_CONTROL,
111 DVMM_PTE_BUFFER_MODE0);
112
113 set_reg_field_value(
114 value,
115 1,
116 DVMM_PTE_CONTROL,
117 DVMM_PTE_BUFFER_MODE1);
118
119 dm_write_reg(ctx, addr, value);
120
121 addr = mmDVMM_PTE_REQ;
122 value = dm_read_reg(ctx, addr);
123
124 chunk_int = get_reg_field_value(
125 value,
126 DVMM_PTE_REQ,
127 HFLIP_PTEREQ_PER_CHUNK_INT);
128
129 chunk_mul = get_reg_field_value(
130 value,
131 DVMM_PTE_REQ,
132 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
133
134 if (chunk_int != 0x4 || chunk_mul != 0x4) {
135
136 set_reg_field_value(
137 value,
138 255,
139 DVMM_PTE_REQ,
140 MAX_PTEREQ_TO_ISSUE);
141
142 set_reg_field_value(
143 value,
144 4,
145 DVMM_PTE_REQ,
146 HFLIP_PTEREQ_PER_CHUNK_INT);
147
148 set_reg_field_value(
149 value,
150 4,
151 DVMM_PTE_REQ,
152 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
153
154 dm_write_reg(ctx, addr, value);
155 }
156 }
157 /**************************************************************************/
158
159 static void enable_display_pipe_clock_gating(
160 struct dc_context *ctx,
161 bool clock_gating)
162 {
163 /*TODO*/
164 }
165
166 static bool dce110_enable_display_power_gating(
167 struct core_dc *dc,
168 uint8_t controller_id,
169 struct dc_bios *dcb,
170 enum pipe_gating_control power_gating)
171 {
172 enum bp_result bp_result = BP_RESULT_OK;
173 enum bp_pipe_control_action cntl;
174 struct dc_context *ctx = dc->ctx;
175 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
176
177 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
178 return true;
179
180 if (power_gating == PIPE_GATING_CONTROL_INIT)
181 cntl = ASIC_PIPE_INIT;
182 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
183 cntl = ASIC_PIPE_ENABLE;
184 else
185 cntl = ASIC_PIPE_DISABLE;
186
187 if (controller_id == underlay_idx)
188 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
189
190 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
191
192 bp_result = dcb->funcs->enable_disp_power_gating(
193 dcb, controller_id + 1, cntl);
194
195 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
196 * by default when command table is called
197 *
198 * Bios parser accepts controller_id = 6 as indicative of
199 * underlay pipe in dce110. But we do not support more
200 * than 3.
201 */
202 if (controller_id < CONTROLLER_ID_MAX - 1)
203 dm_write_reg(ctx,
204 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
205 0);
206 }
207
208 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
209 dce110_init_pte(ctx);
210
211 if (bp_result == BP_RESULT_OK)
212 return true;
213 else
214 return false;
215 }
216
217 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
218 const struct dc_plane_state *plane_state)
219 {
220 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
221
222 switch (plane_state->format) {
223 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
224 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
225 prescale_params->scale = 0x2020;
226 break;
227 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
228 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
229 prescale_params->scale = 0x2008;
230 break;
231 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
232 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
233 prescale_params->scale = 0x2000;
234 break;
235 default:
236 ASSERT(false);
237 break;
238 }
239 }
240
241 static bool dce110_set_input_transfer_func(
242 struct pipe_ctx *pipe_ctx,
243 const struct dc_plane_state *plane_state)
244 {
245 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
246 const struct dc_transfer_func *tf = NULL;
247 struct ipp_prescale_params prescale_params = { 0 };
248 bool result = true;
249
250 if (ipp == NULL)
251 return false;
252
253 if (plane_state->in_transfer_func)
254 tf = plane_state->in_transfer_func;
255
256 build_prescale_params(&prescale_params, plane_state);
257 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
258
259 if (plane_state->gamma_correction && dce_use_lut(plane_state))
260 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
261
262 if (tf == NULL) {
263 /* Default case if no input transfer function specified */
264 ipp->funcs->ipp_set_degamma(ipp,
265 IPP_DEGAMMA_MODE_HW_sRGB);
266 } else if (tf->type == TF_TYPE_PREDEFINED) {
267 switch (tf->tf) {
268 case TRANSFER_FUNCTION_SRGB:
269 ipp->funcs->ipp_set_degamma(ipp,
270 IPP_DEGAMMA_MODE_HW_sRGB);
271 break;
272 case TRANSFER_FUNCTION_BT709:
273 ipp->funcs->ipp_set_degamma(ipp,
274 IPP_DEGAMMA_MODE_HW_xvYCC);
275 break;
276 case TRANSFER_FUNCTION_LINEAR:
277 ipp->funcs->ipp_set_degamma(ipp,
278 IPP_DEGAMMA_MODE_BYPASS);
279 break;
280 case TRANSFER_FUNCTION_PQ:
281 result = false;
282 break;
283 default:
284 result = false;
285 break;
286 }
287 } else if (tf->type == TF_TYPE_BYPASS) {
288 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
289 } else {
290 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
291 result = false;
292 }
293
294 return result;
295 }
296
297 static bool convert_to_custom_float(
298 struct pwl_result_data *rgb_resulted,
299 struct curve_points *arr_points,
300 uint32_t hw_points_num)
301 {
302 struct custom_float_format fmt;
303
304 struct pwl_result_data *rgb = rgb_resulted;
305
306 uint32_t i = 0;
307
308 fmt.exponenta_bits = 6;
309 fmt.mantissa_bits = 12;
310 fmt.sign = true;
311
312 if (!convert_to_custom_float_format(
313 arr_points[0].x,
314 &fmt,
315 &arr_points[0].custom_float_x)) {
316 BREAK_TO_DEBUGGER();
317 return false;
318 }
319
320 if (!convert_to_custom_float_format(
321 arr_points[0].offset,
322 &fmt,
323 &arr_points[0].custom_float_offset)) {
324 BREAK_TO_DEBUGGER();
325 return false;
326 }
327
328 if (!convert_to_custom_float_format(
329 arr_points[0].slope,
330 &fmt,
331 &arr_points[0].custom_float_slope)) {
332 BREAK_TO_DEBUGGER();
333 return false;
334 }
335
336 fmt.mantissa_bits = 10;
337 fmt.sign = false;
338
339 if (!convert_to_custom_float_format(
340 arr_points[1].x,
341 &fmt,
342 &arr_points[1].custom_float_x)) {
343 BREAK_TO_DEBUGGER();
344 return false;
345 }
346
347 if (!convert_to_custom_float_format(
348 arr_points[1].y,
349 &fmt,
350 &arr_points[1].custom_float_y)) {
351 BREAK_TO_DEBUGGER();
352 return false;
353 }
354
355 if (!convert_to_custom_float_format(
356 arr_points[2].slope,
357 &fmt,
358 &arr_points[2].custom_float_slope)) {
359 BREAK_TO_DEBUGGER();
360 return false;
361 }
362
363 fmt.mantissa_bits = 12;
364 fmt.sign = true;
365
366 while (i != hw_points_num) {
367 if (!convert_to_custom_float_format(
368 rgb->red,
369 &fmt,
370 &rgb->red_reg)) {
371 BREAK_TO_DEBUGGER();
372 return false;
373 }
374
375 if (!convert_to_custom_float_format(
376 rgb->green,
377 &fmt,
378 &rgb->green_reg)) {
379 BREAK_TO_DEBUGGER();
380 return false;
381 }
382
383 if (!convert_to_custom_float_format(
384 rgb->blue,
385 &fmt,
386 &rgb->blue_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(
392 rgb->delta_red,
393 &fmt,
394 &rgb->delta_red_reg)) {
395 BREAK_TO_DEBUGGER();
396 return false;
397 }
398
399 if (!convert_to_custom_float_format(
400 rgb->delta_green,
401 &fmt,
402 &rgb->delta_green_reg)) {
403 BREAK_TO_DEBUGGER();
404 return false;
405 }
406
407 if (!convert_to_custom_float_format(
408 rgb->delta_blue,
409 &fmt,
410 &rgb->delta_blue_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 ++rgb;
416 ++i;
417 }
418
419 return true;
420 }
421
422 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
423 *output_tf, struct pwl_params *regamma_params)
424 {
425 struct curve_points *arr_points;
426 struct pwl_result_data *rgb_resulted;
427 struct pwl_result_data *rgb;
428 struct pwl_result_data *rgb_plus_1;
429 struct fixed31_32 y_r;
430 struct fixed31_32 y_g;
431 struct fixed31_32 y_b;
432 struct fixed31_32 y1_min;
433 struct fixed31_32 y3_max;
434
435 int32_t segment_start, segment_end;
436 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
437
438 if (output_tf == NULL || regamma_params == NULL ||
439 output_tf->type == TF_TYPE_BYPASS)
440 return false;
441
442 arr_points = regamma_params->arr_points;
443 rgb_resulted = regamma_params->rgb_resulted;
444 hw_points = 0;
445
446 memset(regamma_params, 0, sizeof(struct pwl_params));
447
448 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
449 /* 16 segments
450 * segments are from 2^-11 to 2^5
451 */
452 segment_start = -11;
453 segment_end = 5;
454
455 seg_distr[0] = 2;
456 seg_distr[1] = 2;
457 seg_distr[2] = 2;
458 seg_distr[3] = 2;
459 seg_distr[4] = 2;
460 seg_distr[5] = 2;
461 seg_distr[6] = 3;
462 seg_distr[7] = 4;
463 seg_distr[8] = 4;
464 seg_distr[9] = 4;
465 seg_distr[10] = 4;
466 seg_distr[11] = 5;
467 seg_distr[12] = 5;
468 seg_distr[13] = 5;
469 seg_distr[14] = 5;
470 seg_distr[15] = 5;
471
472 } else {
473 /* 10 segments
474 * segment is from 2^-10 to 2^0
475 */
476 segment_start = -10;
477 segment_end = 0;
478
479 seg_distr[0] = 3;
480 seg_distr[1] = 4;
481 seg_distr[2] = 4;
482 seg_distr[3] = 4;
483 seg_distr[4] = 4;
484 seg_distr[5] = 4;
485 seg_distr[6] = 4;
486 seg_distr[7] = 4;
487 seg_distr[8] = 5;
488 seg_distr[9] = 5;
489 seg_distr[10] = -1;
490 seg_distr[11] = -1;
491 seg_distr[12] = -1;
492 seg_distr[13] = -1;
493 seg_distr[14] = -1;
494 seg_distr[15] = -1;
495 }
496
497 for (k = 0; k < 16; k++) {
498 if (seg_distr[k] != -1)
499 hw_points += (1 << seg_distr[k]);
500 }
501
502 j = 0;
503 for (k = 0; k < (segment_end - segment_start); k++) {
504 increment = 32 / (1 << seg_distr[k]);
505 start_index = (segment_start + k + 25) * 32;
506 for (i = start_index; i < start_index + 32; i += increment) {
507 if (j == hw_points - 1)
508 break;
509 rgb_resulted[j].red = output_tf->tf_pts.red[i];
510 rgb_resulted[j].green = output_tf->tf_pts.green[i];
511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
512 j++;
513 }
514 }
515
516 /* last point */
517 start_index = (segment_end + 25) * 32;
518 rgb_resulted[hw_points - 1].red =
519 output_tf->tf_pts.red[start_index];
520 rgb_resulted[hw_points - 1].green =
521 output_tf->tf_pts.green[start_index];
522 rgb_resulted[hw_points - 1].blue =
523 output_tf->tf_pts.blue[start_index];
524
525 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
526 dal_fixed31_32_from_int(segment_start));
527 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
528 dal_fixed31_32_from_int(segment_end));
529 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
530 dal_fixed31_32_from_int(segment_end));
531
532 y_r = rgb_resulted[0].red;
533 y_g = rgb_resulted[0].green;
534 y_b = rgb_resulted[0].blue;
535
536 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
537
538 arr_points[0].y = y1_min;
539 arr_points[0].slope = dal_fixed31_32_div(
540 arr_points[0].y,
541 arr_points[0].x);
542
543 y_r = rgb_resulted[hw_points - 1].red;
544 y_g = rgb_resulted[hw_points - 1].green;
545 y_b = rgb_resulted[hw_points - 1].blue;
546
547 /* see comment above, m_arrPoints[1].y should be the Y value for the
548 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
549 */
550 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
551
552 arr_points[1].y = y3_max;
553 arr_points[2].y = y3_max;
554
555 arr_points[1].slope = dal_fixed31_32_zero;
556 arr_points[2].slope = dal_fixed31_32_zero;
557
558 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
559 /* for PQ, we want to have a straight line from last HW X point,
560 * and the slope to be such that we hit 1.0 at 10000 nits.
561 */
562 const struct fixed31_32 end_value =
563 dal_fixed31_32_from_int(125);
564
565 arr_points[1].slope = dal_fixed31_32_div(
566 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
567 dal_fixed31_32_sub(end_value, arr_points[1].x));
568 arr_points[2].slope = dal_fixed31_32_div(
569 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
570 dal_fixed31_32_sub(end_value, arr_points[1].x));
571 }
572
573 regamma_params->hw_points_num = hw_points;
574
575 i = 1;
576 for (k = 0; k < 16 && i < 16; k++) {
577 if (seg_distr[k] != -1) {
578 regamma_params->arr_curve_points[k].segments_num =
579 seg_distr[k];
580 regamma_params->arr_curve_points[i].offset =
581 regamma_params->arr_curve_points[k].
582 offset + (1 << seg_distr[k]);
583 }
584 i++;
585 }
586
587 if (seg_distr[k] != -1)
588 regamma_params->arr_curve_points[k].segments_num =
589 seg_distr[k];
590
591 rgb = rgb_resulted;
592 rgb_plus_1 = rgb_resulted + 1;
593
594 i = 1;
595
596 while (i != hw_points + 1) {
597 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
598 rgb_plus_1->red = rgb->red;
599 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
600 rgb_plus_1->green = rgb->green;
601 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
602 rgb_plus_1->blue = rgb->blue;
603
604 rgb->delta_red = dal_fixed31_32_sub(
605 rgb_plus_1->red,
606 rgb->red);
607 rgb->delta_green = dal_fixed31_32_sub(
608 rgb_plus_1->green,
609 rgb->green);
610 rgb->delta_blue = dal_fixed31_32_sub(
611 rgb_plus_1->blue,
612 rgb->blue);
613
614 ++rgb_plus_1;
615 ++rgb;
616 ++i;
617 }
618
619 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
620
621 return true;
622 }
623
624 static bool dce110_set_output_transfer_func(
625 struct pipe_ctx *pipe_ctx,
626 const struct dc_stream_state *stream)
627 {
628 struct transform *xfm = pipe_ctx->plane_res.xfm;
629
630 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
631 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
632
633 if (stream->out_transfer_func &&
634 stream->out_transfer_func->type ==
635 TF_TYPE_PREDEFINED &&
636 stream->out_transfer_func->tf ==
637 TRANSFER_FUNCTION_SRGB) {
638 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
639 } else if (dce110_translate_regamma_to_hw_format(
640 stream->out_transfer_func, &xfm->regamma_params)) {
641 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
642 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
643 } else {
644 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
645 }
646
647 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
648
649 return true;
650 }
651
652 static enum dc_status bios_parser_crtc_source_select(
653 struct pipe_ctx *pipe_ctx)
654 {
655 struct dc_bios *dcb;
656 /* call VBIOS table to set CRTC source for the HW
657 * encoder block
658 * note: video bios clears all FMT setting here. */
659 struct bp_crtc_source_select crtc_source_select = {0};
660 const struct dc_sink *sink = pipe_ctx->stream->sink;
661
662 crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
663 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
664 /*TODO: Need to un-hardcode color depth, dp_audio and account for
665 * the case where signal and sink signal is different (translator
666 * encoder)*/
667 crtc_source_select.signal = pipe_ctx->stream->signal;
668 crtc_source_select.enable_dp_audio = false;
669 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
670 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
671
672 dcb = sink->ctx->dc_bios;
673
674 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
675 dcb,
676 &crtc_source_select)) {
677 return DC_ERROR_UNEXPECTED;
678 }
679
680 return DC_OK;
681 }
682
683 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
684 {
685 ASSERT(pipe_ctx->stream);
686
687 if (pipe_ctx->stream_res.stream_enc == NULL)
688 return; /* this is not root pipe */
689
690 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
691 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
692 pipe_ctx->stream_res.stream_enc,
693 &pipe_ctx->stream_res.encoder_info_frame);
694 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
695 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
696 pipe_ctx->stream_res.stream_enc,
697 &pipe_ctx->stream_res.encoder_info_frame);
698 }
699
700 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
701 {
702 enum dc_lane_count lane_count =
703 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
704
705 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
706 struct dc_link *link = pipe_ctx->stream->sink->link;
707
708 /* 1. update AVI info frame (HDMI, DP)
709 * we always need to update info frame
710 */
711 uint32_t active_total_with_borders;
712 uint32_t early_control = 0;
713 struct timing_generator *tg = pipe_ctx->stream_res.tg;
714
715 /* TODOFPGA may change to hwss.update_info_frame */
716 dce110_update_info_frame(pipe_ctx);
717 /* enable early control to avoid corruption on DP monitor*/
718 active_total_with_borders =
719 timing->h_addressable
720 + timing->h_border_left
721 + timing->h_border_right;
722
723 if (lane_count != 0)
724 early_control = active_total_with_borders % lane_count;
725
726 if (early_control == 0)
727 early_control = lane_count;
728
729 tg->funcs->set_early_control(tg, early_control);
730
731 /* enable audio only within mode set */
732 if (pipe_ctx->stream_res.audio != NULL) {
733 if (dc_is_dp_signal(pipe_ctx->stream->signal))
734 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
735 }
736
737 /* For MST, there are multiply stream go to only one link.
738 * connect DIG back_end to front_end while enable_stream and
739 * disconnect them during disable_stream
740 * BY this, it is logic clean to separate stream and link */
741 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
742 pipe_ctx->stream_res.stream_enc->id, true);
743
744 }
745
746 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
747 {
748 struct dc_stream_state *stream = pipe_ctx->stream;
749 struct dc_link *link = stream->sink->link;
750
751 if (pipe_ctx->stream_res.audio) {
752 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
753
754 if (dc_is_dp_signal(pipe_ctx->stream->signal))
755 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
756 pipe_ctx->stream_res.stream_enc);
757 else
758 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
759 pipe_ctx->stream_res.stream_enc);
760
761 pipe_ctx->stream_res.audio = NULL;
762
763 /* TODO: notify audio driver for if audio modes list changed
764 * add audio mode list change flag */
765 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
766 * stream->stream_engine_id);
767 */
768 }
769
770 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
771 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
772 pipe_ctx->stream_res.stream_enc);
773
774 if (dc_is_dp_signal(pipe_ctx->stream->signal))
775 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
776 pipe_ctx->stream_res.stream_enc);
777
778 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
779 pipe_ctx->stream_res.stream_enc, true);
780
781
782 /* blank at encoder level */
783 if (dc_is_dp_signal(pipe_ctx->stream->signal))
784 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
785
786 link->link_enc->funcs->connect_dig_be_to_fe(
787 link->link_enc,
788 pipe_ctx->stream_res.stream_enc->id,
789 false);
790
791 }
792
793 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
794 struct dc_link_settings *link_settings)
795 {
796 struct encoder_unblank_param params = { { 0 } };
797
798 /* only 3 items below are used by unblank */
799 params.pixel_clk_khz =
800 pipe_ctx->stream->timing.pix_clk_khz;
801 params.link_settings.link_rate = link_settings->link_rate;
802 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
803 }
804
805
806 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
807 {
808 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
809 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
810 }
811
812 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
813 {
814 switch (crtc_id) {
815 case CONTROLLER_ID_D0:
816 return DTO_SOURCE_ID0;
817 case CONTROLLER_ID_D1:
818 return DTO_SOURCE_ID1;
819 case CONTROLLER_ID_D2:
820 return DTO_SOURCE_ID2;
821 case CONTROLLER_ID_D3:
822 return DTO_SOURCE_ID3;
823 case CONTROLLER_ID_D4:
824 return DTO_SOURCE_ID4;
825 case CONTROLLER_ID_D5:
826 return DTO_SOURCE_ID5;
827 default:
828 return DTO_SOURCE_UNKNOWN;
829 }
830 }
831
832 static void build_audio_output(
833 const struct pipe_ctx *pipe_ctx,
834 struct audio_output *audio_output)
835 {
836 const struct dc_stream_state *stream = pipe_ctx->stream;
837 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
838
839 audio_output->signal = pipe_ctx->stream->signal;
840
841 /* audio_crtc_info */
842
843 audio_output->crtc_info.h_total =
844 stream->timing.h_total;
845
846 /*
847 * Audio packets are sent during actual CRTC blank physical signal, we
848 * need to specify actual active signal portion
849 */
850 audio_output->crtc_info.h_active =
851 stream->timing.h_addressable
852 + stream->timing.h_border_left
853 + stream->timing.h_border_right;
854
855 audio_output->crtc_info.v_active =
856 stream->timing.v_addressable
857 + stream->timing.v_border_top
858 + stream->timing.v_border_bottom;
859
860 audio_output->crtc_info.pixel_repetition = 1;
861
862 audio_output->crtc_info.interlaced =
863 stream->timing.flags.INTERLACE;
864
865 audio_output->crtc_info.refresh_rate =
866 (stream->timing.pix_clk_khz*1000)/
867 (stream->timing.h_total*stream->timing.v_total);
868
869 audio_output->crtc_info.color_depth =
870 stream->timing.display_color_depth;
871
872 audio_output->crtc_info.requested_pixel_clock =
873 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
874
875 audio_output->crtc_info.calculated_pixel_clock =
876 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
877
878 /*for HDMI, audio ACR is with deep color ratio factor*/
879 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
880 audio_output->crtc_info.requested_pixel_clock ==
881 stream->timing.pix_clk_khz) {
882 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
883 audio_output->crtc_info.requested_pixel_clock =
884 audio_output->crtc_info.requested_pixel_clock/2;
885 audio_output->crtc_info.calculated_pixel_clock =
886 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
887
888 }
889 }
890
891 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
892 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
893 audio_output->pll_info.dp_dto_source_clock_in_khz =
894 pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
895 pipe_ctx->dis_clk);
896 }
897
898 audio_output->pll_info.feed_back_divider =
899 pipe_ctx->pll_settings.feedback_divider;
900
901 audio_output->pll_info.dto_source =
902 translate_to_dto_source(
903 pipe_ctx->pipe_idx + 1);
904
905 /* TODO hard code to enable for now. Need get from stream */
906 audio_output->pll_info.ss_enabled = true;
907
908 audio_output->pll_info.ss_percentage =
909 pipe_ctx->pll_settings.ss_percentage;
910 }
911
912 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
913 struct tg_color *color)
914 {
915 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
916
917 switch (pipe_ctx->plane_res.scl_data.format) {
918 case PIXEL_FORMAT_ARGB8888:
919 /* set boarder color to red */
920 color->color_r_cr = color_value;
921 break;
922
923 case PIXEL_FORMAT_ARGB2101010:
924 /* set boarder color to blue */
925 color->color_b_cb = color_value;
926 break;
927 case PIXEL_FORMAT_420BPP8:
928 /* set boarder color to green */
929 color->color_g_y = color_value;
930 break;
931 case PIXEL_FORMAT_420BPP10:
932 /* set boarder color to yellow */
933 color->color_g_y = color_value;
934 color->color_r_cr = color_value;
935 break;
936 case PIXEL_FORMAT_FP16:
937 /* set boarder color to white */
938 color->color_r_cr = color_value;
939 color->color_b_cb = color_value;
940 color->color_g_y = color_value;
941 break;
942 default:
943 break;
944 }
945 }
946
947 static void program_scaler(const struct core_dc *dc,
948 const struct pipe_ctx *pipe_ctx)
949 {
950 struct tg_color color = {0};
951
952 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
953 /* TOFPGA */
954 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
955 return;
956 #endif
957
958 if (dc->public.debug.surface_visual_confirm)
959 get_surface_visual_confirm_color(pipe_ctx, &color);
960 else
961 color_space_to_black_color(dc,
962 pipe_ctx->stream->output_color_space,
963 &color);
964
965 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
966 pipe_ctx->plane_res.xfm,
967 pipe_ctx->plane_res.scl_data.lb_params.depth,
968 &pipe_ctx->stream->bit_depth_params);
969
970 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
971 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
972 pipe_ctx->stream_res.tg,
973 &color);
974
975 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
976 &pipe_ctx->plane_res.scl_data);
977 }
978
979 static enum dc_status dce110_prog_pixclk_crtc_otg(
980 struct pipe_ctx *pipe_ctx,
981 struct validate_context *context,
982 struct core_dc *dc)
983 {
984 struct dc_stream_state *stream = pipe_ctx->stream;
985 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
986 pipe_ctx[pipe_ctx->pipe_idx];
987 struct tg_color black_color = {0};
988
989 if (!pipe_ctx_old->stream) {
990
991 /* program blank color */
992 color_space_to_black_color(dc,
993 stream->output_color_space, &black_color);
994 pipe_ctx->stream_res.tg->funcs->set_blank_color(
995 pipe_ctx->stream_res.tg,
996 &black_color);
997
998 /*
999 * Must blank CRTC after disabling power gating and before any
1000 * programming, otherwise CRTC will be hung in bad state
1001 */
1002 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1003
1004 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1005 pipe_ctx->clock_source,
1006 &pipe_ctx->stream_res.pix_clk_params,
1007 &pipe_ctx->pll_settings)) {
1008 BREAK_TO_DEBUGGER();
1009 return DC_ERROR_UNEXPECTED;
1010 }
1011
1012 pipe_ctx->stream_res.tg->funcs->program_timing(
1013 pipe_ctx->stream_res.tg,
1014 &stream->timing,
1015 true);
1016
1017 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1018 pipe_ctx->stream_res.tg,
1019 0x182);
1020 }
1021
1022 if (!pipe_ctx_old->stream) {
1023 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1024 pipe_ctx->stream_res.tg)) {
1025 BREAK_TO_DEBUGGER();
1026 return DC_ERROR_UNEXPECTED;
1027 }
1028 }
1029
1030
1031
1032 return DC_OK;
1033 }
1034
1035 static enum dc_status apply_single_controller_ctx_to_hw(
1036 struct pipe_ctx *pipe_ctx,
1037 struct validate_context *context,
1038 struct core_dc *dc)
1039 {
1040 struct dc_stream_state *stream = pipe_ctx->stream;
1041 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
1042 pipe_ctx[pipe_ctx->pipe_idx];
1043
1044 /* */
1045 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1046
1047 /* FPGA does not program backend */
1048 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1049 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1050 pipe_ctx->stream_res.opp,
1051 COLOR_SPACE_YCBCR601,
1052 stream->timing.display_color_depth,
1053 pipe_ctx->stream->signal);
1054
1055 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1056 pipe_ctx->stream_res.opp,
1057 &stream->bit_depth_params,
1058 &stream->clamping);
1059 return DC_OK;
1060 }
1061 /* TODO: move to stream encoder */
1062 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1063 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1064 BREAK_TO_DEBUGGER();
1065 return DC_ERROR_UNEXPECTED;
1066 }
1067 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1068 pipe_ctx->stream_res.opp,
1069 COLOR_SPACE_YCBCR601,
1070 stream->timing.display_color_depth,
1071 pipe_ctx->stream->signal);
1072
1073 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1074 stream->sink->link->link_enc->funcs->setup(
1075 stream->sink->link->link_enc,
1076 pipe_ctx->stream->signal);
1077
1078 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1079 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1080 pipe_ctx->stream_res.stream_enc,
1081 pipe_ctx->stream_res.tg->inst,
1082 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1083
1084
1085 /*vbios crtc_source_selection and encoder_setup will override fmt_C*/
1086 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1087 pipe_ctx->stream_res.opp,
1088 &stream->bit_depth_params,
1089 &stream->clamping);
1090
1091 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1092 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1093 pipe_ctx->stream_res.stream_enc,
1094 &stream->timing,
1095 stream->output_color_space);
1096
1097 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1098 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1099 pipe_ctx->stream_res.stream_enc,
1100 &stream->timing,
1101 stream->phy_pix_clk,
1102 pipe_ctx->stream_res.audio != NULL);
1103
1104 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1105 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1106 pipe_ctx->stream_res.stream_enc,
1107 &stream->timing,
1108 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1109 true : false);
1110
1111 resource_build_info_frame(pipe_ctx);
1112 dce110_update_info_frame(pipe_ctx);
1113 if (!pipe_ctx_old->stream) {
1114 core_link_enable_stream(pipe_ctx);
1115
1116
1117 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1118 dce110_unblank_stream(pipe_ctx,
1119 &stream->sink->link->cur_link_settings);
1120 }
1121
1122 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1123 /* program_scaler and allocate_mem_input are not new asic */
1124 if ((!pipe_ctx_old ||
1125 memcmp(&pipe_ctx_old->plane_res.scl_data, &pipe_ctx->plane_res.scl_data,
1126 sizeof(struct scaler_data)) != 0) &&
1127 pipe_ctx->plane_state) {
1128 program_scaler(dc, pipe_ctx);
1129 }
1130
1131 /* mst support - use total stream count */
1132 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1133 if (pipe_ctx->plane_res.mi->funcs->allocate_mem_input != NULL)
1134 #endif
1135 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
1136 pipe_ctx->plane_res.mi,
1137 stream->timing.h_total,
1138 stream->timing.v_total,
1139 stream->timing.pix_clk_khz,
1140 context->stream_count);
1141
1142 pipe_ctx->stream->sink->link->psr_enabled = false;
1143
1144 return DC_OK;
1145 }
1146
1147 /******************************************************************************/
1148
1149 static void power_down_encoders(struct core_dc *dc)
1150 {
1151 int i;
1152
1153 for (i = 0; i < dc->link_count; i++) {
1154 dc->links[i]->link_enc->funcs->disable_output(
1155 dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
1156 }
1157 }
1158
1159 static void power_down_controllers(struct core_dc *dc)
1160 {
1161 int i;
1162
1163 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1164 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1165 dc->res_pool->timing_generators[i]);
1166 }
1167 }
1168
1169 static void power_down_clock_sources(struct core_dc *dc)
1170 {
1171 int i;
1172
1173 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1174 dc->res_pool->dp_clock_source) == false)
1175 dm_error("Failed to power down pll! (dp clk src)\n");
1176
1177 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1178 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1179 dc->res_pool->clock_sources[i]) == false)
1180 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1181 }
1182 }
1183
1184 static void power_down_all_hw_blocks(struct core_dc *dc)
1185 {
1186 power_down_encoders(dc);
1187
1188 power_down_controllers(dc);
1189
1190 power_down_clock_sources(dc);
1191
1192 #ifdef ENABLE_FBC
1193 if (dc->fbc_compressor)
1194 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1195 #endif
1196 }
1197
1198 static void disable_vga_and_power_gate_all_controllers(
1199 struct core_dc *dc)
1200 {
1201 int i;
1202 struct timing_generator *tg;
1203 struct dc_context *ctx = dc->ctx;
1204
1205 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1206 tg = dc->res_pool->timing_generators[i];
1207
1208 if (tg->funcs->disable_vga)
1209 tg->funcs->disable_vga(tg);
1210
1211 /* Enable CLOCK gating for each pipe BEFORE controller
1212 * powergating. */
1213 enable_display_pipe_clock_gating(ctx,
1214 true);
1215
1216 dc->hwss.power_down_front_end(dc, i);
1217 }
1218 }
1219
1220 /**
1221 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1222 * 1. Power down all DC HW blocks
1223 * 2. Disable VGA engine on all controllers
1224 * 3. Enable power gating for controller
1225 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1226 */
1227 void dce110_enable_accelerated_mode(struct core_dc *dc)
1228 {
1229 power_down_all_hw_blocks(dc);
1230
1231 disable_vga_and_power_gate_all_controllers(dc);
1232 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1233 }
1234
1235 static uint32_t compute_pstate_blackout_duration(
1236 struct bw_fixed blackout_duration,
1237 const struct dc_stream_state *stream)
1238 {
1239 uint32_t total_dest_line_time_ns;
1240 uint32_t pstate_blackout_duration_ns;
1241
1242 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1243
1244 total_dest_line_time_ns = 1000000UL *
1245 stream->timing.h_total /
1246 stream->timing.pix_clk_khz +
1247 pstate_blackout_duration_ns;
1248
1249 return total_dest_line_time_ns;
1250 }
1251
1252 void dce110_set_displaymarks(
1253 const struct core_dc *dc,
1254 struct validate_context *context)
1255 {
1256 uint8_t i, num_pipes;
1257 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1258
1259 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1260 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1261 uint32_t total_dest_line_time_ns;
1262
1263 if (pipe_ctx->stream == NULL)
1264 continue;
1265
1266 total_dest_line_time_ns = compute_pstate_blackout_duration(
1267 dc->bw_vbios.blackout_duration, pipe_ctx->stream);
1268 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1269 pipe_ctx->plane_res.mi,
1270 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1271 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1272 context->bw.dce.urgent_wm_ns[num_pipes],
1273 total_dest_line_time_ns);
1274 if (i == underlay_idx) {
1275 num_pipes++;
1276 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1277 pipe_ctx->plane_res.mi,
1278 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1279 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1280 context->bw.dce.urgent_wm_ns[num_pipes],
1281 total_dest_line_time_ns);
1282 }
1283 num_pipes++;
1284 }
1285 }
1286
1287 static void set_safe_displaymarks(
1288 struct resource_context *res_ctx,
1289 const struct resource_pool *pool)
1290 {
1291 int i;
1292 int underlay_idx = pool->underlay_pipe_index;
1293 struct dce_watermarks max_marks = {
1294 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1295 struct dce_watermarks nbp_marks = {
1296 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1297
1298 for (i = 0; i < MAX_PIPES; i++) {
1299 if (res_ctx->pipe_ctx[i].stream == NULL)
1300 continue;
1301
1302 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1303 res_ctx->pipe_ctx[i].plane_res.mi,
1304 nbp_marks,
1305 max_marks,
1306 max_marks,
1307 MAX_WATERMARK);
1308 if (i == underlay_idx)
1309 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1310 res_ctx->pipe_ctx[i].plane_res.mi,
1311 nbp_marks,
1312 max_marks,
1313 max_marks,
1314 MAX_WATERMARK);
1315 }
1316 }
1317
1318 static void switch_dp_clock_sources(
1319 const struct core_dc *dc,
1320 struct resource_context *res_ctx)
1321 {
1322 uint8_t i;
1323 for (i = 0; i < MAX_PIPES; i++) {
1324 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1325
1326 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1327 continue;
1328
1329 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1330 struct clock_source *clk_src =
1331 resource_find_used_clk_src_for_sharing(
1332 res_ctx, pipe_ctx);
1333
1334 if (clk_src &&
1335 clk_src != pipe_ctx->clock_source) {
1336 resource_unreference_clock_source(
1337 res_ctx, dc->res_pool,
1338 &pipe_ctx->clock_source);
1339 pipe_ctx->clock_source = clk_src;
1340 resource_reference_clock_source(
1341 res_ctx, dc->res_pool, clk_src);
1342
1343 dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
1344 }
1345 }
1346 }
1347 }
1348
1349 /*******************************************************************************
1350 * Public functions
1351 ******************************************************************************/
1352
1353 static void set_drr(struct pipe_ctx **pipe_ctx,
1354 int num_pipes, int vmin, int vmax)
1355 {
1356 int i = 0;
1357 struct drr_params params = {0};
1358
1359 params.vertical_total_max = vmax;
1360 params.vertical_total_min = vmin;
1361
1362 /* TODO: If multiple pipes are to be supported, you need
1363 * some GSL stuff
1364 */
1365
1366 for (i = 0; i < num_pipes; i++) {
1367 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1368 }
1369 }
1370
1371 static void get_position(struct pipe_ctx **pipe_ctx,
1372 int num_pipes,
1373 struct crtc_position *position)
1374 {
1375 int i = 0;
1376
1377 /* TODO: handle pipes > 1
1378 */
1379 for (i = 0; i < num_pipes; i++)
1380 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1381 }
1382
1383 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1384 int num_pipes, const struct dc_static_screen_events *events)
1385 {
1386 unsigned int i;
1387 unsigned int value = 0;
1388
1389 if (events->overlay_update)
1390 value |= 0x100;
1391 if (events->surface_update)
1392 value |= 0x80;
1393 if (events->cursor_update)
1394 value |= 0x2;
1395
1396 #ifdef ENABLE_FBC
1397 value |= 0x84;
1398 #endif
1399
1400 for (i = 0; i < num_pipes; i++)
1401 pipe_ctx[i]->stream_res.tg->funcs->
1402 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1403 }
1404
1405 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1406 * may not be programmed yet.
1407 * TODO: after mode set, pre_mode_set = false,
1408 * may read PLL register to get pixel clock
1409 */
1410 static uint32_t get_max_pixel_clock_for_all_paths(
1411 struct core_dc *dc,
1412 struct validate_context *context,
1413 bool pre_mode_set)
1414 {
1415 uint32_t max_pix_clk = 0;
1416 int i;
1417
1418 if (!pre_mode_set) {
1419 /* TODO: read ASIC register to get pixel clock */
1420 ASSERT(0);
1421 }
1422
1423 for (i = 0; i < MAX_PIPES; i++) {
1424 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1425
1426 if (pipe_ctx->stream == NULL)
1427 continue;
1428
1429 /* do not check under lay */
1430 if (pipe_ctx->top_pipe)
1431 continue;
1432
1433 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1434 max_pix_clk =
1435 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1436 }
1437
1438 if (max_pix_clk == 0)
1439 ASSERT(0);
1440
1441 return max_pix_clk;
1442 }
1443
1444 /* Find clock state based on clock requested. if clock value is 0, simply
1445 * set clock state as requested without finding clock state by clock value
1446 *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock.
1447 *
1448 * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value
1449 * etc support for dcn1.0
1450 */
1451 static void apply_min_clocks(
1452 struct core_dc *dc,
1453 struct validate_context *context,
1454 enum dm_pp_clocks_state *clocks_state,
1455 bool pre_mode_set)
1456 {
1457 struct state_dependent_clocks req_clocks = {0};
1458 struct pipe_ctx *pipe_ctx;
1459 int i;
1460
1461 for (i = 0; i < MAX_PIPES; i++) {
1462 pipe_ctx = &context->res_ctx.pipe_ctx[i];
1463 if (pipe_ctx->dis_clk != NULL)
1464 break;
1465 }
1466
1467 if (!pre_mode_set) {
1468 /* set clock_state without verification */
1469 if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
1470 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1471 pipe_ctx->dis_clk, *clocks_state);
1472 return;
1473 }
1474
1475 /* TODO: This is incorrect. Figure out how to fix. */
1476 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1477 pipe_ctx->dis_clk,
1478 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1479 pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz,
1480 pre_mode_set,
1481 false);
1482
1483 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1484 pipe_ctx->dis_clk,
1485 DM_PP_CLOCK_TYPE_PIXELCLK,
1486 pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1487 pre_mode_set,
1488 false);
1489
1490 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1491 pipe_ctx->dis_clk,
1492 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1493 pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1494 pre_mode_set,
1495 false);
1496 return;
1497 }
1498
1499 /* get the required state based on state dependent clocks:
1500 * display clock and pixel clock
1501 */
1502 req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1503
1504 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1505 dc, context, true);
1506
1507 if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) {
1508 *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state(
1509 pipe_ctx->dis_clk, &req_clocks);
1510 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1511 pipe_ctx->dis_clk, *clocks_state);
1512 } else {
1513 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1514 pipe_ctx->dis_clk,
1515 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1516 req_clocks.display_clk_khz,
1517 pre_mode_set,
1518 false);
1519
1520 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1521 pipe_ctx->dis_clk,
1522 DM_PP_CLOCK_TYPE_PIXELCLK,
1523 req_clocks.pixel_clk_khz,
1524 pre_mode_set,
1525 false);
1526
1527 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1528 pipe_ctx->dis_clk,
1529 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1530 req_clocks.pixel_clk_khz,
1531 pre_mode_set,
1532 false);
1533 }
1534 }
1535
1536 #ifdef ENABLE_FBC
1537
1538 /*
1539 * Check if FBC can be enabled
1540 */
1541 static enum dc_status validate_fbc(struct core_dc *dc,
1542 struct validate_context *context)
1543 {
1544 struct pipe_ctx *pipe_ctx =
1545 &context->res_ctx.pipe_ctx[0];
1546
1547 ASSERT(dc->fbc_compressor);
1548
1549 /* FBC memory should be allocated */
1550 if (!dc->ctx->fbc_gpu_addr)
1551 return DC_ERROR_UNEXPECTED;
1552
1553 /* Only supports single display */
1554 if (context->stream_count != 1)
1555 return DC_ERROR_UNEXPECTED;
1556
1557 /* Only supports eDP */
1558 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1559 return DC_ERROR_UNEXPECTED;
1560
1561 /* PSR should not be enabled */
1562 if (pipe_ctx->stream->sink->link->psr_enabled)
1563 return DC_ERROR_UNEXPECTED;
1564
1565 return DC_OK;
1566 }
1567
1568 /*
1569 * Enable FBC
1570 */
1571 static enum dc_status enable_fbc(struct core_dc *dc,
1572 struct validate_context *context)
1573 {
1574 enum dc_status status = validate_fbc(dc, context);
1575
1576 if (status == DC_OK) {
1577 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1578 struct compr_addr_and_pitch_params params = {0, 0, 0};
1579 struct compressor *compr = dc->fbc_compressor;
1580 struct pipe_ctx *pipe_ctx =
1581 &context->res_ctx.pipe_ctx[0];
1582
1583 params.source_view_width =
1584 pipe_ctx->stream->timing.h_addressable;
1585 params.source_view_height =
1586 pipe_ctx->stream->timing.v_addressable;
1587
1588 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1589
1590 compr->funcs->surface_address_and_pitch(compr, &params);
1591 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1592
1593 compr->funcs->enable_fbc(compr, &params);
1594 }
1595 return status;
1596 }
1597 #endif
1598
1599 static enum dc_status apply_ctx_to_hw_fpga(
1600 struct core_dc *dc,
1601 struct validate_context *context)
1602 {
1603 enum dc_status status = DC_ERROR_UNEXPECTED;
1604 int i;
1605
1606 for (i = 0; i < MAX_PIPES; i++) {
1607 struct pipe_ctx *pipe_ctx_old =
1608 &dc->current_context->res_ctx.pipe_ctx[i];
1609 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1610
1611 if (pipe_ctx->stream == NULL)
1612 continue;
1613
1614 if (pipe_ctx->stream == pipe_ctx_old->stream)
1615 continue;
1616
1617 status = apply_single_controller_ctx_to_hw(
1618 pipe_ctx,
1619 context,
1620 dc);
1621
1622 if (status != DC_OK)
1623 return status;
1624 }
1625
1626 return DC_OK;
1627 }
1628
1629 static void dce110_reset_hw_ctx_wrap(
1630 struct core_dc *dc,
1631 struct validate_context *context)
1632 {
1633 int i;
1634
1635 /* Reset old context */
1636 /* look up the targets that have been removed since last commit */
1637 for (i = 0; i < MAX_PIPES; i++) {
1638 struct pipe_ctx *pipe_ctx_old =
1639 &dc->current_context->res_ctx.pipe_ctx[i];
1640 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1641
1642 /* Note: We need to disable output if clock sources change,
1643 * since bios does optimization and doesn't apply if changing
1644 * PHY when not already disabled.
1645 */
1646
1647 /* Skip underlay pipe since it will be handled in commit surface*/
1648 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1649 continue;
1650
1651 if (!pipe_ctx->stream ||
1652 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1653 core_link_disable_stream(pipe_ctx_old);
1654 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1655 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1656 dm_error("DC: failed to blank crtc!\n");
1657 BREAK_TO_DEBUGGER();
1658 }
1659 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1660 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1661 pipe_ctx_old->plane_res.mi, dc->current_context->stream_count);
1662 resource_unreference_clock_source(
1663 &dc->current_context->res_ctx, dc->res_pool,
1664 &pipe_ctx_old->clock_source);
1665
1666 dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
1667
1668 pipe_ctx_old->stream = NULL;
1669 }
1670 }
1671 }
1672
1673
1674 enum dc_status dce110_apply_ctx_to_hw(
1675 struct core_dc *dc,
1676 struct validate_context *context)
1677 {
1678 struct dc_bios *dcb = dc->ctx->dc_bios;
1679 enum dc_status status;
1680 int i;
1681 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1682
1683 /* Reset old context */
1684 /* look up the targets that have been removed since last commit */
1685 dc->hwss.reset_hw_ctx_wrap(dc, context);
1686
1687 /* Skip applying if no targets */
1688 if (context->stream_count <= 0)
1689 return DC_OK;
1690
1691 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1692 apply_ctx_to_hw_fpga(dc, context);
1693 return DC_OK;
1694 }
1695
1696 /* Apply new context */
1697 dcb->funcs->set_scratch_critical_state(dcb, true);
1698
1699 /* below is for real asic only */
1700 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1701 struct pipe_ctx *pipe_ctx_old =
1702 &dc->current_context->res_ctx.pipe_ctx[i];
1703 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1704
1705 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1706 continue;
1707
1708 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1709 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1710 dce_crtc_switch_to_clk_src(dc->hwseq,
1711 pipe_ctx->clock_source, i);
1712 continue;
1713 }
1714
1715 dc->hwss.enable_display_power_gating(
1716 dc, i, dc->ctx->dc_bios,
1717 PIPE_GATING_CONTROL_DISABLE);
1718 }
1719
1720 set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1721
1722 #ifdef ENABLE_FBC
1723 if (dc->fbc_compressor)
1724 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1725 #endif
1726 /*TODO: when pplib works*/
1727 apply_min_clocks(dc, context, &clocks_state, true);
1728
1729 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1730 if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1731 if (context->bw.dcn.calc_clk.fclk_khz
1732 > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
1733 struct dm_pp_clock_for_voltage_req clock;
1734
1735 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1736 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1737 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1738 dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1739 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1740 }
1741 if (context->bw.dcn.calc_clk.dcfclk_khz
1742 > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
1743 struct dm_pp_clock_for_voltage_req clock;
1744
1745 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1746 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1747 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1748 dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1749 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1750 }
1751 if (context->bw.dcn.calc_clk.dispclk_khz
1752 > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
1753 dc->res_pool->display_clock->funcs->set_clock(
1754 dc->res_pool->display_clock,
1755 context->bw.dcn.calc_clk.dispclk_khz);
1756 dc->current_context->bw.dcn.cur_clk.dispclk_khz =
1757 context->bw.dcn.calc_clk.dispclk_khz;
1758 context->bw.dcn.cur_clk.dispclk_khz =
1759 context->bw.dcn.calc_clk.dispclk_khz;
1760 }
1761 } else
1762 #endif
1763 if (context->bw.dce.dispclk_khz
1764 > dc->current_context->bw.dce.dispclk_khz) {
1765 dc->res_pool->display_clock->funcs->set_clock(
1766 dc->res_pool->display_clock,
1767 context->bw.dce.dispclk_khz * 115 / 100);
1768 }
1769 /* program audio wall clock. use HDMI as clock source if HDMI
1770 * audio active. Otherwise, use DP as clock source
1771 * first, loop to find any HDMI audio, if not, loop find DP audio
1772 */
1773 /* Setup audio rate clock source */
1774 /* Issue:
1775 * Audio lag happened on DP monitor when unplug a HDMI monitor
1776 *
1777 * Cause:
1778 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1779 * is set to either dto0 or dto1, audio should work fine.
1780 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1781 * set to dto0 will cause audio lag.
1782 *
1783 * Solution:
1784 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1785 * find first available pipe with audio, setup audio wall DTO per topology
1786 * instead of per pipe.
1787 */
1788 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1789 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1790
1791 if (pipe_ctx->stream == NULL)
1792 continue;
1793
1794 if (pipe_ctx->top_pipe)
1795 continue;
1796
1797 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1798 continue;
1799
1800 if (pipe_ctx->stream_res.audio != NULL) {
1801 struct audio_output audio_output;
1802
1803 build_audio_output(pipe_ctx, &audio_output);
1804
1805 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1806 pipe_ctx->stream_res.audio,
1807 pipe_ctx->stream->signal,
1808 &audio_output.crtc_info,
1809 &audio_output.pll_info);
1810 break;
1811 }
1812 }
1813
1814 /* no HDMI audio is found, try DP audio */
1815 if (i == dc->res_pool->pipe_count) {
1816 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1817 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1818
1819 if (pipe_ctx->stream == NULL)
1820 continue;
1821
1822 if (pipe_ctx->top_pipe)
1823 continue;
1824
1825 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1826 continue;
1827
1828 if (pipe_ctx->stream_res.audio != NULL) {
1829 struct audio_output audio_output;
1830
1831 build_audio_output(pipe_ctx, &audio_output);
1832
1833 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1834 pipe_ctx->stream_res.audio,
1835 pipe_ctx->stream->signal,
1836 &audio_output.crtc_info,
1837 &audio_output.pll_info);
1838 break;
1839 }
1840 }
1841 }
1842
1843 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1844 struct pipe_ctx *pipe_ctx_old =
1845 &dc->current_context->res_ctx.pipe_ctx[i];
1846 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1847
1848 if (pipe_ctx->stream == NULL)
1849 continue;
1850
1851 if (pipe_ctx->stream == pipe_ctx_old->stream)
1852 continue;
1853
1854 if (pipe_ctx->stream && pipe_ctx_old->stream
1855 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1856 continue;
1857
1858 if (pipe_ctx->top_pipe)
1859 continue;
1860
1861 if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
1862
1863 struct audio_output audio_output;
1864
1865 build_audio_output(pipe_ctx, &audio_output);
1866
1867 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1868 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1869 pipe_ctx->stream_res.stream_enc,
1870 pipe_ctx->stream_res.audio->inst,
1871 &pipe_ctx->stream->audio_info);
1872 else
1873 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1874 pipe_ctx->stream_res.stream_enc,
1875 pipe_ctx->stream_res.audio->inst,
1876 &pipe_ctx->stream->audio_info,
1877 &audio_output.crtc_info);
1878
1879 pipe_ctx->stream_res.audio->funcs->az_configure(
1880 pipe_ctx->stream_res.audio,
1881 pipe_ctx->stream->signal,
1882 &audio_output.crtc_info,
1883 &pipe_ctx->stream->audio_info);
1884 }
1885
1886 status = apply_single_controller_ctx_to_hw(
1887 pipe_ctx,
1888 context,
1889 dc);
1890
1891 if (dc->hwss.power_on_front_end)
1892 dc->hwss.power_on_front_end(dc, pipe_ctx, context);
1893
1894 if (DC_OK != status)
1895 return status;
1896 }
1897
1898 dc->hwss.set_bandwidth(dc, context, true);
1899
1900 /* to save power */
1901 apply_min_clocks(dc, context, &clocks_state, false);
1902
1903 dcb->funcs->set_scratch_critical_state(dcb, false);
1904
1905 switch_dp_clock_sources(dc, &context->res_ctx);
1906
1907 #ifdef ENABLE_FBC
1908 if (dc->fbc_compressor)
1909 enable_fbc(dc, context);
1910
1911 #endif
1912
1913 return DC_OK;
1914 }
1915
1916 /*******************************************************************************
1917 * Front End programming
1918 ******************************************************************************/
1919 static void set_default_colors(struct pipe_ctx *pipe_ctx)
1920 {
1921 struct default_adjustment default_adjust = { 0 };
1922
1923 default_adjust.force_hw_default = false;
1924 if (pipe_ctx->plane_state == NULL)
1925 default_adjust.in_color_space = COLOR_SPACE_SRGB;
1926 else
1927 default_adjust.in_color_space =
1928 pipe_ctx->plane_state->color_space;
1929 if (pipe_ctx->stream == NULL)
1930 default_adjust.out_color_space = COLOR_SPACE_SRGB;
1931 else
1932 default_adjust.out_color_space =
1933 pipe_ctx->stream->output_color_space;
1934 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
1935 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
1936
1937 /* display color depth */
1938 default_adjust.color_depth =
1939 pipe_ctx->stream->timing.display_color_depth;
1940
1941 /* Lb color depth */
1942 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
1943
1944 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
1945 pipe_ctx->plane_res.xfm, &default_adjust);
1946 }
1947
1948
1949 /*******************************************************************************
1950 * In order to turn on/off specific surface we will program
1951 * Blender + CRTC
1952 *
1953 * In case that we have two surfaces and they have a different visibility
1954 * we can't turn off the CRTC since it will turn off the entire display
1955 *
1956 * |----------------------------------------------- |
1957 * |bottom pipe|curr pipe | | |
1958 * |Surface |Surface | Blender | CRCT |
1959 * |visibility |visibility | Configuration| |
1960 * |------------------------------------------------|
1961 * | off | off | CURRENT_PIPE | blank |
1962 * | off | on | CURRENT_PIPE | unblank |
1963 * | on | off | OTHER_PIPE | unblank |
1964 * | on | on | BLENDING | unblank |
1965 * -------------------------------------------------|
1966 *
1967 ******************************************************************************/
1968 static void program_surface_visibility(const struct core_dc *dc,
1969 struct pipe_ctx *pipe_ctx)
1970 {
1971 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
1972 bool blank_target = false;
1973
1974 if (pipe_ctx->bottom_pipe) {
1975
1976 /* For now we are supporting only two pipes */
1977 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
1978
1979 if (pipe_ctx->bottom_pipe->plane_state->visible) {
1980 if (pipe_ctx->plane_state->visible)
1981 blender_mode = BLND_MODE_BLENDING;
1982 else
1983 blender_mode = BLND_MODE_OTHER_PIPE;
1984
1985 } else if (!pipe_ctx->plane_state->visible)
1986 blank_target = true;
1987
1988 } else if (!pipe_ctx->plane_state->visible)
1989 blank_target = true;
1990
1991 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
1992 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
1993
1994 }
1995
1996 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1997 {
1998 struct xfm_grph_csc_adjustment adjust;
1999 memset(&adjust, 0, sizeof(adjust));
2000 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2001
2002
2003 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2004 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2005 adjust.temperature_matrix[0] =
2006 pipe_ctx->stream->
2007 gamut_remap_matrix.matrix[0];
2008 adjust.temperature_matrix[1] =
2009 pipe_ctx->stream->
2010 gamut_remap_matrix.matrix[1];
2011 adjust.temperature_matrix[2] =
2012 pipe_ctx->stream->
2013 gamut_remap_matrix.matrix[2];
2014 adjust.temperature_matrix[3] =
2015 pipe_ctx->stream->
2016 gamut_remap_matrix.matrix[4];
2017 adjust.temperature_matrix[4] =
2018 pipe_ctx->stream->
2019 gamut_remap_matrix.matrix[5];
2020 adjust.temperature_matrix[5] =
2021 pipe_ctx->stream->
2022 gamut_remap_matrix.matrix[6];
2023 adjust.temperature_matrix[6] =
2024 pipe_ctx->stream->
2025 gamut_remap_matrix.matrix[8];
2026 adjust.temperature_matrix[7] =
2027 pipe_ctx->stream->
2028 gamut_remap_matrix.matrix[9];
2029 adjust.temperature_matrix[8] =
2030 pipe_ctx->stream->
2031 gamut_remap_matrix.matrix[10];
2032 }
2033
2034 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2035 }
2036
2037 /**
2038 * TODO REMOVE, USE UPDATE INSTEAD
2039 */
2040 static void set_plane_config(
2041 const struct core_dc *dc,
2042 struct pipe_ctx *pipe_ctx,
2043 struct resource_context *res_ctx)
2044 {
2045 struct mem_input *mi = pipe_ctx->plane_res.mi;
2046 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2047 struct xfm_grph_csc_adjustment adjust;
2048 struct out_csc_color_matrix tbl_entry;
2049 unsigned int i;
2050
2051 memset(&adjust, 0, sizeof(adjust));
2052 memset(&tbl_entry, 0, sizeof(tbl_entry));
2053 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2054
2055 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2056
2057 set_default_colors(pipe_ctx);
2058 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2059 == true) {
2060 tbl_entry.color_space =
2061 pipe_ctx->stream->output_color_space;
2062
2063 for (i = 0; i < 12; i++)
2064 tbl_entry.regval[i] =
2065 pipe_ctx->stream->csc_color_matrix.matrix[i];
2066
2067 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2068 (pipe_ctx->plane_res.xfm, &tbl_entry);
2069 }
2070
2071 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2072 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2073 adjust.temperature_matrix[0] =
2074 pipe_ctx->stream->
2075 gamut_remap_matrix.matrix[0];
2076 adjust.temperature_matrix[1] =
2077 pipe_ctx->stream->
2078 gamut_remap_matrix.matrix[1];
2079 adjust.temperature_matrix[2] =
2080 pipe_ctx->stream->
2081 gamut_remap_matrix.matrix[2];
2082 adjust.temperature_matrix[3] =
2083 pipe_ctx->stream->
2084 gamut_remap_matrix.matrix[4];
2085 adjust.temperature_matrix[4] =
2086 pipe_ctx->stream->
2087 gamut_remap_matrix.matrix[5];
2088 adjust.temperature_matrix[5] =
2089 pipe_ctx->stream->
2090 gamut_remap_matrix.matrix[6];
2091 adjust.temperature_matrix[6] =
2092 pipe_ctx->stream->
2093 gamut_remap_matrix.matrix[8];
2094 adjust.temperature_matrix[7] =
2095 pipe_ctx->stream->
2096 gamut_remap_matrix.matrix[9];
2097 adjust.temperature_matrix[8] =
2098 pipe_ctx->stream->
2099 gamut_remap_matrix.matrix[10];
2100 }
2101
2102 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2103
2104 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2105 program_scaler(dc, pipe_ctx);
2106
2107 program_surface_visibility(dc, pipe_ctx);
2108
2109 mi->funcs->mem_input_program_surface_config(
2110 mi,
2111 plane_state->format,
2112 &plane_state->tiling_info,
2113 &plane_state->plane_size,
2114 plane_state->rotation,
2115 NULL,
2116 false);
2117 if (mi->funcs->set_blank)
2118 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2119
2120 if (dc->public.config.gpu_vm_support)
2121 mi->funcs->mem_input_program_pte_vm(
2122 pipe_ctx->plane_res.mi,
2123 plane_state->format,
2124 &plane_state->tiling_info,
2125 plane_state->rotation);
2126 }
2127
2128 static void update_plane_addr(const struct core_dc *dc,
2129 struct pipe_ctx *pipe_ctx)
2130 {
2131 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2132
2133 if (plane_state == NULL)
2134 return;
2135
2136 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2137 pipe_ctx->plane_res.mi,
2138 &plane_state->address,
2139 plane_state->flip_immediate);
2140
2141 plane_state->status.requested_address = plane_state->address;
2142 }
2143
2144 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2145 {
2146 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2147
2148 if (plane_state == NULL)
2149 return;
2150
2151 plane_state->status.is_flip_pending =
2152 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2153 pipe_ctx->plane_res.mi);
2154
2155 if (plane_state->status.is_flip_pending && !plane_state->visible)
2156 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2157
2158 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2159 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2160 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2161 plane_state->status.is_right_eye =\
2162 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2163 }
2164 }
2165
2166 void dce110_power_down(struct core_dc *dc)
2167 {
2168 power_down_all_hw_blocks(dc);
2169 disable_vga_and_power_gate_all_controllers(dc);
2170 }
2171
2172 static bool wait_for_reset_trigger_to_occur(
2173 struct dc_context *dc_ctx,
2174 struct timing_generator *tg)
2175 {
2176 bool rc = false;
2177
2178 /* To avoid endless loop we wait at most
2179 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2180 const uint32_t frames_to_wait_on_triggered_reset = 10;
2181 uint32_t i;
2182
2183 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2184
2185 if (!tg->funcs->is_counter_moving(tg)) {
2186 DC_ERROR("TG counter is not moving!\n");
2187 break;
2188 }
2189
2190 if (tg->funcs->did_triggered_reset_occur(tg)) {
2191 rc = true;
2192 /* usually occurs at i=1 */
2193 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2194 i);
2195 break;
2196 }
2197
2198 /* Wait for one frame. */
2199 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2200 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2201 }
2202
2203 if (false == rc)
2204 DC_ERROR("GSL: Timeout on reset trigger!\n");
2205
2206 return rc;
2207 }
2208
2209 /* Enable timing synchronization for a group of Timing Generators. */
2210 static void dce110_enable_timing_synchronization(
2211 struct core_dc *dc,
2212 int group_index,
2213 int group_size,
2214 struct pipe_ctx *grouped_pipes[])
2215 {
2216 struct dc_context *dc_ctx = dc->ctx;
2217 struct dcp_gsl_params gsl_params = { 0 };
2218 int i;
2219
2220 DC_SYNC_INFO("GSL: Setting-up...\n");
2221
2222 /* Designate a single TG in the group as a master.
2223 * Since HW doesn't care which one, we always assign
2224 * the 1st one in the group. */
2225 gsl_params.gsl_group = 0;
2226 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2227
2228 for (i = 0; i < group_size; i++)
2229 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2230 grouped_pipes[i]->stream_res.tg, &gsl_params);
2231
2232 /* Reset slave controllers on master VSync */
2233 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2234
2235 for (i = 1 /* skip the master */; i < group_size; i++)
2236 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2237 grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
2238
2239
2240
2241 for (i = 1 /* skip the master */; i < group_size; i++) {
2242 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2243 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2244 /* Regardless of success of the wait above, remove the reset or
2245 * the driver will start timing out on Display requests. */
2246 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2247 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
2248 }
2249
2250
2251 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2252 * is that the sync'ed displays will not drift out of sync over time*/
2253 DC_SYNC_INFO("GSL: Restoring register states.\n");
2254 for (i = 0; i < group_size; i++)
2255 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2256
2257 DC_SYNC_INFO("GSL: Set-up complete.\n");
2258 }
2259
2260 static void init_hw(struct core_dc *dc)
2261 {
2262 int i;
2263 struct dc_bios *bp;
2264 struct transform *xfm;
2265 struct abm *abm;
2266
2267 bp = dc->ctx->dc_bios;
2268 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2269 xfm = dc->res_pool->transforms[i];
2270 xfm->funcs->transform_reset(xfm);
2271
2272 dc->hwss.enable_display_power_gating(
2273 dc, i, bp,
2274 PIPE_GATING_CONTROL_INIT);
2275 dc->hwss.enable_display_power_gating(
2276 dc, i, bp,
2277 PIPE_GATING_CONTROL_DISABLE);
2278 dc->hwss.enable_display_pipe_clock_gating(
2279 dc->ctx,
2280 true);
2281 }
2282
2283 dce_clock_gating_power_up(dc->hwseq, false);
2284 /***************************************/
2285
2286 for (i = 0; i < dc->link_count; i++) {
2287 /****************************************/
2288 /* Power up AND update implementation according to the
2289 * required signal (which may be different from the
2290 * default signal on connector). */
2291 struct dc_link *link = dc->links[i];
2292 link->link_enc->funcs->hw_init(link->link_enc);
2293 }
2294
2295 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2296 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2297
2298 tg->funcs->disable_vga(tg);
2299
2300 /* Blank controller using driver code instead of
2301 * command table. */
2302 tg->funcs->set_blank(tg, true);
2303 hwss_wait_for_blank_complete(tg);
2304 }
2305
2306 for (i = 0; i < dc->res_pool->audio_count; i++) {
2307 struct audio *audio = dc->res_pool->audios[i];
2308 audio->funcs->hw_init(audio);
2309 }
2310
2311 abm = dc->res_pool->abm;
2312 if (abm != NULL) {
2313 abm->funcs->init_backlight(abm);
2314 abm->funcs->abm_init(abm);
2315 }
2316 #ifdef ENABLE_FBC
2317 if (dc->fbc_compressor)
2318 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2319 #endif
2320
2321 }
2322
2323 void dce110_fill_display_configs(
2324 const struct validate_context *context,
2325 struct dm_pp_display_configuration *pp_display_cfg)
2326 {
2327 int j;
2328 int num_cfgs = 0;
2329
2330 for (j = 0; j < context->stream_count; j++) {
2331 int k;
2332
2333 const struct dc_stream_state *stream = context->streams[j];
2334 struct dm_pp_single_disp_config *cfg =
2335 &pp_display_cfg->disp_configs[num_cfgs];
2336 const struct pipe_ctx *pipe_ctx = NULL;
2337
2338 for (k = 0; k < MAX_PIPES; k++)
2339 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2340 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2341 break;
2342 }
2343
2344 ASSERT(pipe_ctx != NULL);
2345
2346 num_cfgs++;
2347 cfg->signal = pipe_ctx->stream->signal;
2348 cfg->pipe_idx = pipe_ctx->pipe_idx;
2349 cfg->src_height = stream->src.height;
2350 cfg->src_width = stream->src.width;
2351 cfg->ddi_channel_mapping =
2352 stream->sink->link->ddi_channel_mapping.raw;
2353 cfg->transmitter =
2354 stream->sink->link->link_enc->transmitter;
2355 cfg->link_settings.lane_count =
2356 stream->sink->link->cur_link_settings.lane_count;
2357 cfg->link_settings.link_rate =
2358 stream->sink->link->cur_link_settings.link_rate;
2359 cfg->link_settings.link_spread =
2360 stream->sink->link->cur_link_settings.link_spread;
2361 cfg->sym_clock = stream->phy_pix_clk;
2362 /* Round v_refresh*/
2363 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2364 cfg->v_refresh /= stream->timing.h_total;
2365 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2366 / stream->timing.v_total;
2367 }
2368
2369 pp_display_cfg->display_count = num_cfgs;
2370 }
2371
2372 uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
2373 {
2374 uint8_t j;
2375 uint32_t min_vertical_blank_time = -1;
2376
2377 for (j = 0; j < context->stream_count; j++) {
2378 struct dc_stream_state *stream = context->streams[j];
2379 uint32_t vertical_blank_in_pixels = 0;
2380 uint32_t vertical_blank_time = 0;
2381
2382 vertical_blank_in_pixels = stream->timing.h_total *
2383 (stream->timing.v_total
2384 - stream->timing.v_addressable);
2385
2386 vertical_blank_time = vertical_blank_in_pixels
2387 * 1000 / stream->timing.pix_clk_khz;
2388
2389 if (min_vertical_blank_time > vertical_blank_time)
2390 min_vertical_blank_time = vertical_blank_time;
2391 }
2392
2393 return min_vertical_blank_time;
2394 }
2395
2396 static int determine_sclk_from_bounding_box(
2397 const struct core_dc *dc,
2398 int required_sclk)
2399 {
2400 int i;
2401
2402 /*
2403 * Some asics do not give us sclk levels, so we just report the actual
2404 * required sclk
2405 */
2406 if (dc->sclk_lvls.num_levels == 0)
2407 return required_sclk;
2408
2409 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2410 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2411 return dc->sclk_lvls.clocks_in_khz[i];
2412 }
2413 /*
2414 * even maximum level could not satisfy requirement, this
2415 * is unexpected at this stage, should have been caught at
2416 * validation time
2417 */
2418 ASSERT(0);
2419 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2420 }
2421
2422 static void pplib_apply_display_requirements(
2423 struct core_dc *dc,
2424 struct validate_context *context)
2425 {
2426 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2427
2428 pp_display_cfg->all_displays_in_sync =
2429 context->bw.dce.all_displays_in_sync;
2430 pp_display_cfg->nb_pstate_switch_disable =
2431 context->bw.dce.nbp_state_change_enable == false;
2432 pp_display_cfg->cpu_cc6_disable =
2433 context->bw.dce.cpuc_state_change_enable == false;
2434 pp_display_cfg->cpu_pstate_disable =
2435 context->bw.dce.cpup_state_change_enable == false;
2436 pp_display_cfg->cpu_pstate_separation_time =
2437 context->bw.dce.blackout_recovery_time_us;
2438
2439 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2440 / MEMORY_TYPE_MULTIPLIER;
2441
2442 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2443 dc,
2444 context->bw.dce.sclk_khz);
2445
2446 pp_display_cfg->min_engine_clock_deep_sleep_khz
2447 = context->bw.dce.sclk_deep_sleep_khz;
2448
2449 pp_display_cfg->avail_mclk_switch_time_us =
2450 dce110_get_min_vblank_time_us(context);
2451 /* TODO: dce11.2*/
2452 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2453
2454 pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2455
2456 dce110_fill_display_configs(context, pp_display_cfg);
2457
2458 /* TODO: is this still applicable?*/
2459 if (pp_display_cfg->display_count == 1) {
2460 const struct dc_crtc_timing *timing =
2461 &context->streams[0]->timing;
2462
2463 pp_display_cfg->crtc_index =
2464 pp_display_cfg->disp_configs[0].pipe_idx;
2465 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2466 / timing->pix_clk_khz;
2467 }
2468
2469 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2470 struct dm_pp_display_configuration)) != 0)
2471 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2472
2473 dc->prev_display_config = *pp_display_cfg;
2474 }
2475
2476 static void dce110_set_bandwidth(
2477 struct core_dc *dc,
2478 struct validate_context *context,
2479 bool decrease_allowed)
2480 {
2481 dce110_set_displaymarks(dc, context);
2482
2483 if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) {
2484 dc->res_pool->display_clock->funcs->set_clock(
2485 dc->res_pool->display_clock,
2486 context->bw.dce.dispclk_khz * 115 / 100);
2487 dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2488 }
2489
2490 pplib_apply_display_requirements(dc, context);
2491 }
2492
2493 static void dce110_program_front_end_for_pipe(
2494 struct core_dc *dc, struct pipe_ctx *pipe_ctx)
2495 {
2496 struct mem_input *mi = pipe_ctx->plane_res.mi;
2497 struct pipe_ctx *old_pipe = NULL;
2498 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2499 struct xfm_grph_csc_adjustment adjust;
2500 struct out_csc_color_matrix tbl_entry;
2501 unsigned int i;
2502
2503 memset(&tbl_entry, 0, sizeof(tbl_entry));
2504
2505 if (dc->current_context)
2506 old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2507
2508 memset(&adjust, 0, sizeof(adjust));
2509 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2510
2511 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2512
2513 set_default_colors(pipe_ctx);
2514 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2515 == true) {
2516 tbl_entry.color_space =
2517 pipe_ctx->stream->output_color_space;
2518
2519 for (i = 0; i < 12; i++)
2520 tbl_entry.regval[i] =
2521 pipe_ctx->stream->csc_color_matrix.matrix[i];
2522
2523 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2524 (pipe_ctx->plane_res.xfm, &tbl_entry);
2525 }
2526
2527 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2528 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2529 adjust.temperature_matrix[0] =
2530 pipe_ctx->stream->
2531 gamut_remap_matrix.matrix[0];
2532 adjust.temperature_matrix[1] =
2533 pipe_ctx->stream->
2534 gamut_remap_matrix.matrix[1];
2535 adjust.temperature_matrix[2] =
2536 pipe_ctx->stream->
2537 gamut_remap_matrix.matrix[2];
2538 adjust.temperature_matrix[3] =
2539 pipe_ctx->stream->
2540 gamut_remap_matrix.matrix[4];
2541 adjust.temperature_matrix[4] =
2542 pipe_ctx->stream->
2543 gamut_remap_matrix.matrix[5];
2544 adjust.temperature_matrix[5] =
2545 pipe_ctx->stream->
2546 gamut_remap_matrix.matrix[6];
2547 adjust.temperature_matrix[6] =
2548 pipe_ctx->stream->
2549 gamut_remap_matrix.matrix[8];
2550 adjust.temperature_matrix[7] =
2551 pipe_ctx->stream->
2552 gamut_remap_matrix.matrix[9];
2553 adjust.temperature_matrix[8] =
2554 pipe_ctx->stream->
2555 gamut_remap_matrix.matrix[10];
2556 }
2557
2558 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2559
2560 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2561
2562 program_scaler(dc, pipe_ctx);
2563
2564 mi->funcs->mem_input_program_surface_config(
2565 mi,
2566 plane_state->format,
2567 &plane_state->tiling_info,
2568 &plane_state->plane_size,
2569 plane_state->rotation,
2570 NULL,
2571 false);
2572 if (mi->funcs->set_blank)
2573 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2574
2575 if (dc->public.config.gpu_vm_support)
2576 mi->funcs->mem_input_program_pte_vm(
2577 pipe_ctx->plane_res.mi,
2578 plane_state->format,
2579 &plane_state->tiling_info,
2580 plane_state->rotation);
2581
2582 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2583 "Pipe:%d 0x%x: addr hi:0x%x, "
2584 "addr low:0x%x, "
2585 "src: %d, %d, %d,"
2586 " %d; dst: %d, %d, %d, %d;"
2587 "clip: %d, %d, %d, %d\n",
2588 pipe_ctx->pipe_idx,
2589 pipe_ctx->plane_state,
2590 pipe_ctx->plane_state->address.grph.addr.high_part,
2591 pipe_ctx->plane_state->address.grph.addr.low_part,
2592 pipe_ctx->plane_state->src_rect.x,
2593 pipe_ctx->plane_state->src_rect.y,
2594 pipe_ctx->plane_state->src_rect.width,
2595 pipe_ctx->plane_state->src_rect.height,
2596 pipe_ctx->plane_state->dst_rect.x,
2597 pipe_ctx->plane_state->dst_rect.y,
2598 pipe_ctx->plane_state->dst_rect.width,
2599 pipe_ctx->plane_state->dst_rect.height,
2600 pipe_ctx->plane_state->clip_rect.x,
2601 pipe_ctx->plane_state->clip_rect.y,
2602 pipe_ctx->plane_state->clip_rect.width,
2603 pipe_ctx->plane_state->clip_rect.height);
2604
2605 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2606 "Pipe %d: width, height, x, y\n"
2607 "viewport:%d, %d, %d, %d\n"
2608 "recout: %d, %d, %d, %d\n",
2609 pipe_ctx->pipe_idx,
2610 pipe_ctx->plane_res.scl_data.viewport.width,
2611 pipe_ctx->plane_res.scl_data.viewport.height,
2612 pipe_ctx->plane_res.scl_data.viewport.x,
2613 pipe_ctx->plane_res.scl_data.viewport.y,
2614 pipe_ctx->plane_res.scl_data.recout.width,
2615 pipe_ctx->plane_res.scl_data.recout.height,
2616 pipe_ctx->plane_res.scl_data.recout.x,
2617 pipe_ctx->plane_res.scl_data.recout.y);
2618 }
2619
2620 static void dce110_apply_ctx_for_surface(
2621 struct core_dc *dc,
2622 const struct dc_stream_state *stream,
2623 int num_planes,
2624 struct validate_context *context)
2625 {
2626 int i, be_idx;
2627
2628 if (num_planes == 0)
2629 return;
2630
2631 be_idx = -1;
2632 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2633 if (stream == context->res_ctx.pipe_ctx[i].stream) {
2634 be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
2635 break;
2636 }
2637 }
2638
2639 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2640 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2641
2642 if (pipe_ctx->stream == stream)
2643 continue;
2644
2645 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2646 program_surface_visibility(dc, pipe_ctx);
2647
2648 }
2649 }
2650
2651 static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
2652 {
2653 /* Do not power down fe when stream is active on dce*/
2654 if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream)
2655 return;
2656
2657 dc->hwss.enable_display_power_gating(
2658 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2659
2660 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2661 dc->res_pool->transforms[fe_idx]);
2662 }
2663
2664 static void dce110_wait_for_mpcc_disconnect(
2665 struct core_dc *dc,
2666 struct resource_pool *res_pool,
2667 struct pipe_ctx *pipe_ctx)
2668 {
2669 /* do nothing*/
2670 }
2671
2672 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2673 enum dc_color_space colorspace,
2674 uint16_t *matrix)
2675 {
2676 int i;
2677 struct out_csc_color_matrix tbl_entry;
2678
2679 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2680 == true) {
2681 enum dc_color_space color_space =
2682 pipe_ctx->stream->output_color_space;
2683
2684 //uint16_t matrix[12];
2685 for (i = 0; i < 12; i++)
2686 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2687
2688 tbl_entry.color_space = color_space;
2689 //tbl_entry.regval = matrix;
2690 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2691 }
2692 }
2693
2694 static const struct hw_sequencer_funcs dce110_funcs = {
2695 .program_gamut_remap = program_gamut_remap,
2696 .program_csc_matrix = program_csc_matrix,
2697 .init_hw = init_hw,
2698 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2699 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2700 .set_plane_config = set_plane_config,
2701 .update_plane_addr = update_plane_addr,
2702 .update_pending_status = dce110_update_pending_status,
2703 .set_input_transfer_func = dce110_set_input_transfer_func,
2704 .set_output_transfer_func = dce110_set_output_transfer_func,
2705 .power_down = dce110_power_down,
2706 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2707 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2708 .update_info_frame = dce110_update_info_frame,
2709 .enable_stream = dce110_enable_stream,
2710 .disable_stream = dce110_disable_stream,
2711 .unblank_stream = dce110_unblank_stream,
2712 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2713 .enable_display_power_gating = dce110_enable_display_power_gating,
2714 .power_down_front_end = dce110_power_down_fe,
2715 .pipe_control_lock = dce_pipe_control_lock,
2716 .set_bandwidth = dce110_set_bandwidth,
2717 .set_drr = set_drr,
2718 .get_position = get_position,
2719 .set_static_screen_control = set_static_screen_control,
2720 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2721 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
2722 .setup_stereo = NULL,
2723 .set_avmute = dce110_set_avmute,
2724 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect
2725 };
2726
2727 bool dce110_hw_sequencer_construct(struct core_dc *dc)
2728 {
2729 dc->hwss = dce110_funcs;
2730
2731 return true;
2732 }
2733
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