drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DAL_DISPLAY_CLOCK_DCE112_H__
  26 #define __DAL_DISPLAY_CLOCK_DCE112_H__
  27
  28 #include "display_clock_interface.h"
  29
  30 struct display_clock_dce112 {
  31         struct display_clock disp_clk_base;
  32         bool use_max_disp_clk;
  33         uint32_t dentist_vco_freq_khz;
  34         /* Cache the status of DFS-bypass feature*/
  35         bool dfs_bypass_enabled;
  36         /* GPU PLL SS percentage (if down-spread enabled) */
  37         uint32_t gpu_pll_ss_percentage;
  38         /* GPU PLL SS percentage Divider (100 or 1000) */
  39         uint32_t gpu_pll_ss_divider;
  40         /* Flag for Enabled SS on GPU PLL */
  41         bool ss_on_gpu_pll;
  42         /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
  43          * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
  44         uint32_t dfs_bypass_disp_clk;
  45         struct state_dependent_clocks *max_clks_by_state;
  46
  47 };
  48
  49 #define DCLCK112_FROM_BASE(dc_base) \
  50         container_of(dc_base, struct display_clock_dce112, disp_clk_base)
  51
  52 /* Array identifiers and count for the divider ranges.*/
  53 enum divider_range_count {
  54         DIVIDER_RANGE_01 = 0,
  55         DIVIDER_RANGE_02,
  56         DIVIDER_RANGE_03,
  57         DIVIDER_RANGE_MAX /* == 3*/
  58 };
  59
  60 /* Starting point for each divider range.*/
  61 enum divider_range_start {
  62         DIVIDER_RANGE_01_START = 200, /* 2.00*/
  63         DIVIDER_RANGE_02_START = 1600, /* 16.00*/
  64         DIVIDER_RANGE_03_START = 3200, /* 32.00*/
  65         DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
  66 };
  67
  68 bool dal_display_clock_dce112_construct(
  69         struct display_clock_dce112 *dc112,
  70         struct dc_context *ctx);
  71
  72 void dispclk_dce112_destroy(struct display_clock **base);
  73
  74 enum clocks_state dispclk_dce112_get_min_clocks_state(
  75         struct display_clock *base);
  76
  77 enum clocks_state dispclk_dce112_get_required_clocks_state(
  78         struct display_clock *dc,
  79         struct state_dependent_clocks *req_clocks);
  80
  81 void dispclk_dce112_set_clock(
  82         struct display_clock *base,
  83         uint32_t requested_clk_khz);
  84
  85 bool dispclk_dce112_set_min_clocks_state(
  86         struct display_clock *base,
  87         enum clocks_state clocks_state);
  88
  89 void dispclk_dce112_store_max_clocks_state(
  90         struct display_clock *base,
  91         enum clocks_state max_clocks_state);
  92
  93 #endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */