drivers/gpu/drm/amd/display/dc/inc/core_types.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef _CORE_TYPES_H_
  27 #define _CORE_TYPES_H_
  28
  29 #include "dc.h"
  30 #include "dce_calcs.h"
  31 #include "dcn_calcs.h"
  32 #include "ddc_service_types.h"
  33 #include "dc_bios_types.h"
  34 #include "mem_input.h"
  35 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  36 #include "mpc.h"
  37 #endif
  38
  39 #define MAX_CLOCK_SOURCES 7
  40
  41 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
  42                 uint32_t controller_id);
  43
  44 #include "grph_object_id.h"
  45 #include "link_encoder.h"
  46 #include "stream_encoder.h"
  47 #include "clock_source.h"
  48 #include "audio.h"
  49 #include "dm_pp_smu.h"
  50
  51
  52 /************ link *****************/
  53 struct link_init_data {
  54         const struct dc *dc;
  55         struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
  56         uint32_t connector_index; /* this will be mapped to the HPD pins */
  57         uint32_t link_index; /* this is mapped to DAL display_index
  58                                 TODO: remove it when DC is complete. */
  59 };
  60
  61 enum {
  62         FREE_ACQUIRED_RESOURCE = 0,
  63         KEEP_ACQUIRED_RESOURCE = 1,
  64 };
  65
  66 struct dc_link *link_create(const struct link_init_data *init_params);
  67 void link_destroy(struct dc_link **link);
  68
  69 enum dc_status dc_link_validate_mode_timing(
  70                 const struct dc_stream_state *stream,
  71                 struct dc_link *link,
  72                 const struct dc_crtc_timing *timing);
  73
  74 void core_link_resume(struct dc_link *link);
  75
  76 void core_link_enable_stream(
  77                 struct dc_state *state,
  78                 struct pipe_ctx *pipe_ctx);
  79
  80 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);
  81
  82 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
  83 /********** DAL Core*********************/
  84 #include "display_clock.h"
  85 #include "transform.h"
  86
  87 struct resource_pool;
  88 struct dc_state;
  89 struct resource_context;
  90
  91 struct resource_funcs {
  92         void (*destroy)(struct resource_pool **pool);
  93         struct link_encoder *(*link_enc_create)(
  94                         const struct encoder_init_data *init);
  95
  96         enum dc_status (*validate_guaranteed)(
  97                                         struct dc *dc,
  98                                         struct dc_stream_state *stream,
  99                                         struct dc_state *context);
 100
 101         bool (*validate_bandwidth)(
 102                                         struct dc *dc,
 103                                         struct dc_state *context);
 104
 105         enum dc_status (*validate_global)(
 106                 struct dc *dc,
 107                 struct dc_state *context);
 108
 109         struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
 110                         struct dc_state *context,
 111                         const struct resource_pool *pool,
 112                         struct dc_stream_state *stream);
 113
 114         enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
 115
 116         enum dc_status (*add_stream_to_ctx)(
 117                         struct dc *dc,
 118                         struct dc_state *new_ctx,
 119                         struct dc_stream_state *dc_stream);
 120 };
 121
 122 struct audio_support{
 123         bool dp_audio;
 124         bool hdmi_audio_on_dongle;
 125         bool hdmi_audio_native;
 126 };
 127
 128 #define NO_UNDERLAY_PIPE -1
 129
 130 struct resource_pool {
 131         struct mem_input *mis[MAX_PIPES];
 132         struct input_pixel_processor *ipps[MAX_PIPES];
 133         struct transform *transforms[MAX_PIPES];
 134         struct output_pixel_processor *opps[MAX_PIPES];
 135         struct timing_generator *timing_generators[MAX_PIPES];
 136         struct stream_encoder *stream_enc[MAX_PIPES * 2];
 137
 138         struct mpc *mpc;
 139         struct pp_smu_funcs_rv *pp_smu;
 140         struct pp_smu_display_requirement_rv pp_smu_req;
 141
 142         unsigned int pipe_count;
 143         unsigned int underlay_pipe_index;
 144         unsigned int stream_enc_count;
 145         unsigned int ref_clock_inKhz;
 146
 147         /*
 148          * reserved clock source for DP
 149          */
 150         struct clock_source *dp_clock_source;
 151
 152         struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
 153         unsigned int clk_src_count;
 154
 155         struct audio *audios[MAX_PIPES];
 156         unsigned int audio_count;
 157         struct audio_support audio_support;
 158
 159         struct display_clock *display_clock;
 160         struct irq_service *irqs;
 161
 162         struct abm *abm;
 163         struct dmcu *dmcu;
 164
 165         const struct resource_funcs *funcs;
 166         const struct resource_caps *res_cap;
 167 };
 168
 169 struct stream_resource {
 170         struct output_pixel_processor *opp;
 171         struct timing_generator *tg;
 172         struct stream_encoder *stream_enc;
 173         struct audio *audio;
 174
 175         struct pixel_clk_params pix_clk_params;
 176         struct encoder_info_frame encoder_info_frame;
 177 };
 178
 179 struct plane_resource {
 180         struct scaler_data scl_data;
 181
 182         struct mem_input *mi;
 183         struct input_pixel_processor *ipp;
 184         struct transform *xfm;
 185 };
 186
 187 struct pipe_ctx {
 188         struct dc_plane_state *plane_state;
 189         struct dc_stream_state *stream;
 190
 191         struct plane_resource plane_res;
 192         struct stream_resource stream_res;
 193
 194         struct clock_source *clock_source;
 195
 196         struct pll_settings pll_settings;
 197
 198         uint8_t pipe_idx;
 199
 200         struct pipe_ctx *top_pipe;
 201         struct pipe_ctx *bottom_pipe;
 202
 203 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 204         struct _vcs_dpi_display_dlg_regs_st dlg_regs;
 205         struct _vcs_dpi_display_ttu_regs_st ttu_regs;
 206         struct _vcs_dpi_display_rq_regs_st rq_regs;
 207         struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
 208 #endif
 209         struct dwbc *dwbc;
 210 };
 211
 212 struct resource_context {
 213         struct pipe_ctx pipe_ctx[MAX_PIPES];
 214         bool is_stream_enc_acquired[MAX_PIPES * 2];
 215         bool is_audio_acquired[MAX_PIPES];
 216         uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
 217         uint8_t dp_clock_source_ref_count;
 218 };
 219
 220 struct dce_bw_output {
 221         bool cpuc_state_change_enable;
 222         bool cpup_state_change_enable;
 223         bool stutter_mode_enable;
 224         bool nbp_state_change_enable;
 225         bool all_displays_in_sync;
 226         struct dce_watermarks urgent_wm_ns[MAX_PIPES];
 227         struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
 228         struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
 229         int sclk_khz;
 230         int sclk_deep_sleep_khz;
 231         int yclk_khz;
 232         int dispclk_khz;
 233         int blackout_recovery_time_us;
 234 };
 235
 236 struct dcn_bw_clocks {
 237         int dispclk_khz;
 238         bool dppclk_div;
 239         int dcfclk_khz;
 240         int dcfclk_deep_sleep_khz;
 241         int fclk_khz;
 242         int dram_ccm_us;
 243         int min_active_dram_ccm_us;
 244 };
 245
 246 struct dcn_bw_output {
 247         struct dcn_bw_clocks cur_clk;
 248         struct dcn_bw_clocks calc_clk;
 249         struct dcn_watermark_set watermarks;
 250 };
 251
 252 union bw_context {
 253         struct dcn_bw_output dcn;
 254         struct dce_bw_output dce;
 255 };
 256
 257 struct dc_state {
 258         struct dc_stream_state *streams[MAX_PIPES];
 259         struct dc_stream_status stream_status[MAX_PIPES];
 260         uint8_t stream_count;
 261
 262         struct resource_context res_ctx;
 263
 264         /* The output from BW and WM calculations. */
 265         union bw_context bw;
 266
 267         /* Note: these are big structures, do *not* put on stack! */
 268         struct dm_pp_display_configuration pp_display_cfg;
 269 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 270         struct dcn_bw_internal_vars dcn_bw_vars;
 271 #endif
 272
 273         struct display_clock *dis_clk;
 274
 275         struct kref refcount;
 276 };
 277
 278 #endif /* _CORE_TYPES_H_ */