drivers/gpu/drm/amd/display/dc/inc/core_types.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef _CORE_TYPES_H_
  27 #define _CORE_TYPES_H_
  28
  29 #include "dc.h"
  30 #include "dce_calcs.h"
  31 #include "dcn_calcs.h"
  32 #include "ddc_service_types.h"
  33 #include "dc_bios_types.h"
  34 #include "mem_input.h"
  35 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  36 #include "mpc.h"
  37 #endif
  38
  39 #define MAX_CLOCK_SOURCES 7
  40
  41 void enable_surface_flip_reporting(struct dc_surface *dc_surface,
  42                 uint32_t controller_id);
  43
  44 #include "grph_object_id.h"
  45 #include "link_encoder.h"
  46 #include "stream_encoder.h"
  47 #include "clock_source.h"
  48 #include "audio.h"
  49 #include "hw_sequencer_types.h"
  50
  51
  52 /************ link *****************/
  53 struct link_init_data {
  54         const struct core_dc *dc;
  55         struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
  56         uint32_t connector_index; /* this will be mapped to the HPD pins */
  57         uint32_t link_index; /* this is mapped to DAL display_index
  58                                 TODO: remove it when DC is complete. */
  59 };
  60
  61 struct dc_link *link_create(const struct link_init_data *init_params);
  62 void link_destroy(struct dc_link **link);
  63
  64 enum dc_status dc_link_validate_mode_timing(
  65                 const struct dc_stream *stream,
  66                 struct dc_link *link,
  67                 const struct dc_crtc_timing *timing);
  68
  69 void core_link_resume(struct dc_link *link);
  70
  71 void core_link_enable_stream(struct pipe_ctx *pipe_ctx);
  72
  73 void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
  74
  75 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
  76 /********** DAL Core*********************/
  77 #include "display_clock.h"
  78 #include "transform.h"
  79
  80 struct resource_pool;
  81 struct validate_context;
  82 struct resource_context;
  83
  84 struct resource_funcs {
  85         void (*destroy)(struct resource_pool **pool);
  86         struct link_encoder *(*link_enc_create)(
  87                         const struct encoder_init_data *init);
  88         enum dc_status (*validate_with_context)(
  89                                         const struct core_dc *dc,
  90                                         const struct dc_validation_set set[],
  91                                         int set_count,
  92                                         struct validate_context *context,
  93                                         struct validate_context *old_context);
  94
  95         enum dc_status (*validate_guaranteed)(
  96                                         const struct core_dc *dc,
  97                                         struct dc_stream *stream,
  98                                         struct validate_context *context);
  99
 100         bool (*validate_bandwidth)(
 101                                         const struct core_dc *dc,
 102                                         struct validate_context *context);
 103
 104         struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
 105                         struct validate_context *context,
 106                         const struct resource_pool *pool,
 107                         struct dc_stream *stream);
 108
 109         enum dc_status (*validate_surface)(const struct dc_surface *surface);
 110 };
 111
 112 struct audio_support{
 113         bool dp_audio;
 114         bool hdmi_audio_on_dongle;
 115         bool hdmi_audio_native;
 116 };
 117
 118 #define NO_UNDERLAY_PIPE -1
 119
 120 struct resource_pool {
 121         struct mem_input *mis[MAX_PIPES];
 122         struct input_pixel_processor *ipps[MAX_PIPES];
 123         struct transform *transforms[MAX_PIPES];
 124         struct output_pixel_processor *opps[MAX_PIPES];
 125         struct timing_generator *timing_generators[MAX_PIPES];
 126         struct stream_encoder *stream_enc[MAX_PIPES * 2];
 127 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 128         struct mpc *mpc;
 129 #endif
 130
 131         unsigned int pipe_count;
 132         unsigned int underlay_pipe_index;
 133         unsigned int stream_enc_count;
 134         unsigned int ref_clock_inKhz;
 135
 136         /*
 137          * reserved clock source for DP
 138          */
 139         struct clock_source *dp_clock_source;
 140
 141         struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
 142         unsigned int clk_src_count;
 143
 144         struct audio *audios[MAX_PIPES];
 145         unsigned int audio_count;
 146         struct audio_support audio_support;
 147
 148         struct display_clock *display_clock;
 149         struct irq_service *irqs;
 150
 151         struct abm *abm;
 152         struct dmcu *dmcu;
 153
 154         const struct resource_funcs *funcs;
 155         const struct resource_caps *res_cap;
 156 };
 157
 158 struct pipe_ctx {
 159         struct dc_surface *surface;
 160         struct dc_stream *stream;
 161
 162         struct mem_input *mi;
 163         struct input_pixel_processor *ipp;
 164         struct transform *xfm;
 165         struct output_pixel_processor *opp;
 166         struct timing_generator *tg;
 167
 168         struct scaler_data scl_data;
 169
 170         struct stream_encoder *stream_enc;
 171         struct display_clock *dis_clk;
 172         struct clock_source *clock_source;
 173
 174         struct audio *audio;
 175
 176         struct pixel_clk_params pix_clk_params;
 177         struct pll_settings pll_settings;
 178
 179         /*fmt*/
 180         struct encoder_info_frame encoder_info_frame;
 181
 182         uint8_t pipe_idx;
 183
 184         struct pipe_ctx *top_pipe;
 185         struct pipe_ctx *bottom_pipe;
 186
 187 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 188         struct _vcs_dpi_display_dlg_regs_st dlg_regs;
 189         struct _vcs_dpi_display_ttu_regs_st ttu_regs;
 190         struct _vcs_dpi_display_rq_regs_st rq_regs;
 191         struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
 192 #endif
 193 };
 194
 195 struct resource_context {
 196         struct pipe_ctx pipe_ctx[MAX_PIPES];
 197         bool is_stream_enc_acquired[MAX_PIPES * 2];
 198         bool is_audio_acquired[MAX_PIPES];
 199         uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
 200         uint8_t dp_clock_source_ref_count;
 201 };
 202
 203 struct dce_bw_output {
 204         bool cpuc_state_change_enable;
 205         bool cpup_state_change_enable;
 206         bool stutter_mode_enable;
 207         bool nbp_state_change_enable;
 208         bool all_displays_in_sync;
 209         struct dce_watermarks urgent_wm_ns[MAX_PIPES];
 210         struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
 211         struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
 212         int sclk_khz;
 213         int sclk_deep_sleep_khz;
 214         int yclk_khz;
 215         int dispclk_khz;
 216         int blackout_recovery_time_us;
 217 };
 218
 219 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 220 struct dcn_bw_clocks {
 221         int dispclk_khz;
 222         bool dppclk_div;
 223         int dcfclk_khz;
 224         int dcfclk_deep_sleep_khz;
 225         int fclk_khz;
 226         int dram_ccm_us;
 227         int min_active_dram_ccm_us;
 228 };
 229
 230 struct dcn_bw_output {
 231         struct dcn_bw_clocks cur_clk;
 232         struct dcn_bw_clocks calc_clk;
 233         struct dcn_watermark_set watermarks;
 234 };
 235 #endif
 236
 237 union bw_context {
 238 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 239         struct dcn_bw_output dcn;
 240 #endif
 241         struct dce_bw_output dce;
 242 };
 243
 244 struct validate_context {
 245         struct dc_stream *streams[MAX_PIPES];
 246         struct dc_stream_status stream_status[MAX_PIPES];
 247         uint8_t stream_count;
 248
 249         struct resource_context res_ctx;
 250
 251         /* The output from BW and WM calculations. */
 252         union bw_context bw;
 253
 254         /* Note: these are big structures, do *not* put on stack! */
 255         struct dm_pp_display_configuration pp_display_cfg;
 256 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 257         struct dcn_bw_internal_vars dcn_bw_vars;
 258 #endif
 259
 260         int ref_count;
 261 };
 262
 263 #endif /* _CORE_TYPES_H_ */