drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HW_SEQUENCER_H__
  27 #define __DC_HW_SEQUENCER_H__
  28 #include "core_types.h"
  29 #include "timing_generator.h"
  30
  31 struct gamma_parameters;
  32
  33 enum pipe_gating_control {
  34         PIPE_GATING_CONTROL_DISABLE = 0,
  35         PIPE_GATING_CONTROL_ENABLE,
  36         PIPE_GATING_CONTROL_INIT
  37 };
  38
  39 enum pipe_lock_control {
  40         PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
  41         PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
  42         PIPE_LOCK_CONTROL_SCL = 1 << 2,
  43         PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
  44         PIPE_LOCK_CONTROL_MODE = 1 << 4
  45 };
  46
  47 struct dce_hwseq;
  48
  49 struct hw_sequencer_funcs {
  50
  51         void (*init_hw)(struct core_dc *dc);
  52
  53         enum dc_status (*apply_ctx_to_hw)(
  54                         struct core_dc *dc, struct validate_context *context);
  55
  56         void (*reset_hw_ctx_wrap)(
  57                         struct core_dc *dc, struct validate_context *context);
  58
  59         void (*prepare_pipe_for_context)(
  60                         struct core_dc *dc,
  61                         struct pipe_ctx *pipe_ctx,
  62                         struct validate_context *context);
  63
  64         void (*apply_ctx_for_surface)(
  65                         struct core_dc *dc,
  66                         struct core_surface *surface,
  67                         struct validate_context *context);
  68
  69         void (*set_plane_config)(
  70                         const struct core_dc *dc,
  71                         struct pipe_ctx *pipe_ctx,
  72                         struct resource_context *res_ctx);
  73
  74         void (*update_plane_addr)(
  75                 const struct core_dc *dc,
  76                 struct pipe_ctx *pipe_ctx);
  77
  78         void (*update_pending_status)(
  79                         struct pipe_ctx *pipe_ctx);
  80
  81         bool (*set_gamma_correction)(
  82                                 struct input_pixel_processor *ipp,
  83                                 struct output_pixel_processor *opp,
  84                                 const struct core_gamma *ramp,
  85                                 const struct core_surface *surface);
  86
  87         void (*power_down)(struct core_dc *dc);
  88
  89         void (*enable_accelerated_mode)(struct core_dc *dc);
  90
  91         void (*enable_timing_synchronization)(
  92                         struct core_dc *dc,
  93                         int group_index,
  94                         int group_size,
  95                         struct pipe_ctx *grouped_pipes[]);
  96
  97         /* backlight control */
  98         void (*encoder_set_lcd_backlight_level)(
  99                 struct link_encoder *enc, uint32_t level);
 100
 101         void (*enable_display_pipe_clock_gating)(
 102                                         struct dc_context *ctx,
 103                                         bool clock_gating);
 104
 105         bool (*enable_display_power_gating)(
 106                                         struct core_dc *dc,
 107                                         uint8_t controller_id,
 108                                         struct dc_bios *dcb,
 109                                         enum pipe_gating_control power_gating);
 110
 111         void (*power_down_front_end)(struct core_dc *dc, struct pipe_ctx *pipe);
 112         void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
 113
 114         void (*enable_stream)(struct pipe_ctx *pipe_ctx);
 115
 116         void (*disable_stream)(struct pipe_ctx *pipe_ctx);
 117
 118         void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
 119                         struct dc_link_settings *link_settings);
 120
 121         void (*pipe_control_lock)(
 122                                 struct dce_hwseq *hwseq,
 123                                 unsigned int blnd_inst,
 124                                 enum pipe_lock_control control_mask,
 125                                 bool lock);
 126
 127         void (*set_displaymarks)(
 128                                 const struct core_dc *dc,
 129                                 struct validate_context *context);
 130
 131         void (*increase_watermarks_for_pipe)(struct core_dc *dc,
 132                         struct pipe_ctx *pipe_ctx,
 133                         struct validate_context *context);
 134
 135         void (*set_display_clock)(struct validate_context *context);
 136
 137         void (*set_bandwidth)(struct core_dc *dc);
 138
 139         void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
 140                         int vmin, int vmax);
 141
 142         void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
 143                         int num_pipes, int value);
 144
 145         enum dc_status (*prog_pixclk_crtc_otg)(
 146                         struct pipe_ctx *pipe_ctx,
 147                         struct validate_context *context,
 148                         struct core_dc *dc);
 149 };
 150
 151 void color_space_to_black_color(
 152         const struct core_dc *dc,
 153         enum dc_color_space colorspace,
 154         struct tg_color *black_color);
 155
 156 #endif /* __DC_HW_SEQUENCER_H__ */