2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/gfp.h>
26 #include <linux/slab.h>
27 #include "amd_shared.h"
28 #include "amd_powerplay.h"
29 #include "pp_instance.h"
30 #include "power_state.h"
31 #include "eventmanager.h"
34 #define PP_CHECK(handle) \
36 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
40 #define PP_CHECK_HW(hwmgr) \
42 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
46 static int pp_early_init(void *handle
)
51 static int pp_sw_init(void *handle
)
53 struct pp_instance
*pp_handle
;
54 struct pp_hwmgr
*hwmgr
;
60 pp_handle
= (struct pp_instance
*)handle
;
61 hwmgr
= pp_handle
->hwmgr
;
65 if (hwmgr
->pptable_func
== NULL
||
66 hwmgr
->pptable_func
->pptable_init
== NULL
||
67 hwmgr
->hwmgr_func
->backend_init
== NULL
)
70 ret
= hwmgr
->pptable_func
->pptable_init(hwmgr
);
74 ret
= hwmgr
->hwmgr_func
->backend_init(hwmgr
);
78 pr_info("amdgpu: powerplay initialized\n");
82 pr_err("amdgpu: powerplay initialization failed\n");
86 static int pp_sw_fini(void *handle
)
88 struct pp_instance
*pp_handle
;
89 struct pp_hwmgr
*hwmgr
;
95 pp_handle
= (struct pp_instance
*)handle
;
96 hwmgr
= pp_handle
->hwmgr
;
100 if (hwmgr
->hwmgr_func
->backend_fini
!= NULL
)
101 ret
= hwmgr
->hwmgr_func
->backend_fini(hwmgr
);
106 static int pp_hw_init(void *handle
)
108 struct pp_instance
*pp_handle
;
109 struct pp_smumgr
*smumgr
;
110 struct pp_eventmgr
*eventmgr
;
116 pp_handle
= (struct pp_instance
*)handle
;
117 smumgr
= pp_handle
->smu_mgr
;
119 if (smumgr
== NULL
|| smumgr
->smumgr_funcs
== NULL
||
120 smumgr
->smumgr_funcs
->smu_init
== NULL
||
121 smumgr
->smumgr_funcs
->start_smu
== NULL
)
124 ret
= smumgr
->smumgr_funcs
->smu_init(smumgr
);
126 printk(KERN_ERR
"[ powerplay ] smc initialization failed\n");
130 ret
= smumgr
->smumgr_funcs
->start_smu(smumgr
);
132 printk(KERN_ERR
"[ powerplay ] smc start failed\n");
133 smumgr
->smumgr_funcs
->smu_fini(smumgr
);
137 hw_init_power_state_table(pp_handle
->hwmgr
);
138 eventmgr
= pp_handle
->eventmgr
;
140 if (eventmgr
== NULL
|| eventmgr
->pp_eventmgr_init
== NULL
)
143 ret
= eventmgr
->pp_eventmgr_init(eventmgr
);
147 static int pp_hw_fini(void *handle
)
149 struct pp_instance
*pp_handle
;
150 struct pp_smumgr
*smumgr
;
151 struct pp_eventmgr
*eventmgr
;
156 pp_handle
= (struct pp_instance
*)handle
;
157 eventmgr
= pp_handle
->eventmgr
;
159 if (eventmgr
!= NULL
|| eventmgr
->pp_eventmgr_fini
!= NULL
)
160 eventmgr
->pp_eventmgr_fini(eventmgr
);
162 smumgr
= pp_handle
->smu_mgr
;
164 if (smumgr
!= NULL
|| smumgr
->smumgr_funcs
!= NULL
||
165 smumgr
->smumgr_funcs
->smu_fini
!= NULL
)
166 smumgr
->smumgr_funcs
->smu_fini(smumgr
);
171 static bool pp_is_idle(void *handle
)
176 static int pp_wait_for_idle(void *handle
)
181 static int pp_sw_reset(void *handle
)
187 static int pp_set_clockgating_state(void *handle
,
188 enum amd_clockgating_state state
)
190 struct pp_hwmgr
*hwmgr
;
191 uint32_t msg_id
, pp_state
;
196 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
200 if (hwmgr
->hwmgr_func
->update_clock_gatings
== NULL
) {
201 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
205 if (state
== AMD_CG_STATE_UNGATE
)
208 pp_state
= PP_STATE_CG
| PP_STATE_LS
;
210 /* Enable/disable GFX blocks clock gating through SMU */
211 msg_id
= PP_CG_MSG_ID(PP_GROUP_GFX
,
213 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
215 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
216 msg_id
= PP_CG_MSG_ID(PP_GROUP_GFX
,
218 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
220 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
221 msg_id
= PP_CG_MSG_ID(PP_GROUP_GFX
,
223 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
225 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
226 msg_id
= PP_CG_MSG_ID(PP_GROUP_GFX
,
228 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
230 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
231 msg_id
= PP_CG_MSG_ID(PP_GROUP_GFX
,
233 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
235 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
237 /* Enable/disable System blocks clock gating through SMU */
238 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
240 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
242 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
243 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
245 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
247 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
248 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
250 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
252 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
253 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
255 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
257 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
258 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
260 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
262 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
263 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
265 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
267 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
268 msg_id
= PP_CG_MSG_ID(PP_GROUP_SYS
,
270 PP_STATE_SUPPORT_CG
| PP_STATE_SUPPORT_LS
,
272 hwmgr
->hwmgr_func
->update_clock_gatings(hwmgr
, &msg_id
);
277 static int pp_set_powergating_state(void *handle
,
278 enum amd_powergating_state state
)
280 struct pp_hwmgr
*hwmgr
;
285 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
289 if (hwmgr
->hwmgr_func
->enable_per_cu_power_gating
== NULL
) {
290 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
294 /* Enable/disable GFX per cu powergating through SMU */
295 return hwmgr
->hwmgr_func
->enable_per_cu_power_gating(hwmgr
,
296 state
== AMD_PG_STATE_GATE
? true : false);
299 static int pp_suspend(void *handle
)
301 struct pp_instance
*pp_handle
;
302 struct pp_eventmgr
*eventmgr
;
303 struct pem_event_data event_data
= { {0} };
308 pp_handle
= (struct pp_instance
*)handle
;
309 eventmgr
= pp_handle
->eventmgr
;
310 pem_handle_event(eventmgr
, AMD_PP_EVENT_SUSPEND
, &event_data
);
314 static int pp_resume(void *handle
)
316 struct pp_instance
*pp_handle
;
317 struct pp_eventmgr
*eventmgr
;
318 struct pem_event_data event_data
= { {0} };
319 struct pp_smumgr
*smumgr
;
325 pp_handle
= (struct pp_instance
*)handle
;
326 smumgr
= pp_handle
->smu_mgr
;
328 if (smumgr
== NULL
|| smumgr
->smumgr_funcs
== NULL
||
329 smumgr
->smumgr_funcs
->start_smu
== NULL
)
332 ret
= smumgr
->smumgr_funcs
->start_smu(smumgr
);
334 printk(KERN_ERR
"[ powerplay ] smc start failed\n");
335 smumgr
->smumgr_funcs
->smu_fini(smumgr
);
339 eventmgr
= pp_handle
->eventmgr
;
340 pem_handle_event(eventmgr
, AMD_PP_EVENT_RESUME
, &event_data
);
345 const struct amd_ip_funcs pp_ip_funcs
= {
347 .early_init
= pp_early_init
,
349 .sw_init
= pp_sw_init
,
350 .sw_fini
= pp_sw_fini
,
351 .hw_init
= pp_hw_init
,
352 .hw_fini
= pp_hw_fini
,
353 .suspend
= pp_suspend
,
355 .is_idle
= pp_is_idle
,
356 .wait_for_idle
= pp_wait_for_idle
,
357 .soft_reset
= pp_sw_reset
,
358 .set_clockgating_state
= pp_set_clockgating_state
,
359 .set_powergating_state
= pp_set_powergating_state
,
362 static int pp_dpm_load_fw(void *handle
)
367 static int pp_dpm_fw_loading_complete(void *handle
)
372 static int pp_dpm_force_performance_level(void *handle
,
373 enum amd_dpm_forced_level level
)
375 struct pp_instance
*pp_handle
;
376 struct pp_hwmgr
*hwmgr
;
381 pp_handle
= (struct pp_instance
*)handle
;
383 hwmgr
= pp_handle
->hwmgr
;
387 if (hwmgr
->hwmgr_func
->force_dpm_level
== NULL
) {
388 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
392 hwmgr
->hwmgr_func
->force_dpm_level(hwmgr
, level
);
397 static enum amd_dpm_forced_level
pp_dpm_get_performance_level(
400 struct pp_hwmgr
*hwmgr
;
405 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
410 return (((struct pp_instance
*)handle
)->hwmgr
->dpm_level
);
413 static int pp_dpm_get_sclk(void *handle
, bool low
)
415 struct pp_hwmgr
*hwmgr
;
420 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
424 if (hwmgr
->hwmgr_func
->get_sclk
== NULL
) {
425 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
429 return hwmgr
->hwmgr_func
->get_sclk(hwmgr
, low
);
432 static int pp_dpm_get_mclk(void *handle
, bool low
)
434 struct pp_hwmgr
*hwmgr
;
439 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
443 if (hwmgr
->hwmgr_func
->get_mclk
== NULL
) {
444 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
448 return hwmgr
->hwmgr_func
->get_mclk(hwmgr
, low
);
451 static int pp_dpm_powergate_vce(void *handle
, bool gate
)
453 struct pp_hwmgr
*hwmgr
;
458 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
462 if (hwmgr
->hwmgr_func
->powergate_vce
== NULL
) {
463 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
467 return hwmgr
->hwmgr_func
->powergate_vce(hwmgr
, gate
);
470 static int pp_dpm_powergate_uvd(void *handle
, bool gate
)
472 struct pp_hwmgr
*hwmgr
;
477 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
481 if (hwmgr
->hwmgr_func
->powergate_uvd
== NULL
) {
482 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
486 return hwmgr
->hwmgr_func
->powergate_uvd(hwmgr
, gate
);
489 static enum PP_StateUILabel
power_state_convert(enum amd_pm_state_type state
)
492 case POWER_STATE_TYPE_BATTERY
:
493 return PP_StateUILabel_Battery
;
494 case POWER_STATE_TYPE_BALANCED
:
495 return PP_StateUILabel_Balanced
;
496 case POWER_STATE_TYPE_PERFORMANCE
:
497 return PP_StateUILabel_Performance
;
499 return PP_StateUILabel_None
;
503 int pp_dpm_dispatch_tasks(void *handle
, enum amd_pp_event event_id
, void *input
, void *output
)
506 struct pp_instance
*pp_handle
;
507 struct pem_event_data data
= { {0} };
509 pp_handle
= (struct pp_instance
*)handle
;
511 if (pp_handle
== NULL
)
515 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE
:
516 ret
= pem_handle_event(pp_handle
->eventmgr
, event_id
, &data
);
518 case AMD_PP_EVENT_ENABLE_USER_STATE
:
520 enum amd_pm_state_type ps
;
524 ps
= *(unsigned long *)input
;
526 data
.requested_ui_label
= power_state_convert(ps
);
527 ret
= pem_handle_event(pp_handle
->eventmgr
, event_id
, &data
);
530 case AMD_PP_EVENT_COMPLETE_INIT
:
531 ret
= pem_handle_event(pp_handle
->eventmgr
, event_id
, &data
);
539 enum amd_pm_state_type
pp_dpm_get_current_power_state(void *handle
)
541 struct pp_hwmgr
*hwmgr
;
542 struct pp_power_state
*state
;
547 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
549 if (hwmgr
== NULL
|| hwmgr
->current_ps
== NULL
)
552 state
= hwmgr
->current_ps
;
554 switch (state
->classification
.ui_label
) {
555 case PP_StateUILabel_Battery
:
556 return POWER_STATE_TYPE_BATTERY
;
557 case PP_StateUILabel_Balanced
:
558 return POWER_STATE_TYPE_BALANCED
;
559 case PP_StateUILabel_Performance
:
560 return POWER_STATE_TYPE_PERFORMANCE
;
562 if (state
->classification
.flags
& PP_StateClassificationFlag_Boot
)
563 return POWER_STATE_TYPE_INTERNAL_BOOT
;
565 return POWER_STATE_TYPE_DEFAULT
;
570 pp_debugfs_print_current_performance_level(void *handle
,
573 struct pp_hwmgr
*hwmgr
;
578 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
580 if (hwmgr
== NULL
|| hwmgr
->hwmgr_func
== NULL
)
583 if (hwmgr
->hwmgr_func
->print_current_perforce_level
== NULL
) {
584 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
588 hwmgr
->hwmgr_func
->print_current_perforce_level(hwmgr
, m
);
591 static int pp_dpm_set_fan_control_mode(void *handle
, uint32_t mode
)
593 struct pp_hwmgr
*hwmgr
;
598 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
602 if (hwmgr
->hwmgr_func
->set_fan_control_mode
== NULL
) {
603 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
607 return hwmgr
->hwmgr_func
->set_fan_control_mode(hwmgr
, mode
);
610 static int pp_dpm_get_fan_control_mode(void *handle
)
612 struct pp_hwmgr
*hwmgr
;
617 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
621 if (hwmgr
->hwmgr_func
->get_fan_control_mode
== NULL
) {
622 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
626 return hwmgr
->hwmgr_func
->get_fan_control_mode(hwmgr
);
629 static int pp_dpm_set_fan_speed_percent(void *handle
, uint32_t percent
)
631 struct pp_hwmgr
*hwmgr
;
636 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
640 if (hwmgr
->hwmgr_func
->set_fan_speed_percent
== NULL
) {
641 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
645 return hwmgr
->hwmgr_func
->set_fan_speed_percent(hwmgr
, percent
);
648 static int pp_dpm_get_fan_speed_percent(void *handle
, uint32_t *speed
)
650 struct pp_hwmgr
*hwmgr
;
655 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
659 if (hwmgr
->hwmgr_func
->get_fan_speed_percent
== NULL
) {
660 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
664 return hwmgr
->hwmgr_func
->get_fan_speed_percent(hwmgr
, speed
);
667 static int pp_dpm_get_temperature(void *handle
)
669 struct pp_hwmgr
*hwmgr
;
674 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
678 if (hwmgr
->hwmgr_func
->get_temperature
== NULL
) {
679 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
683 return hwmgr
->hwmgr_func
->get_temperature(hwmgr
);
686 static int pp_dpm_get_pp_num_states(void *handle
,
687 struct pp_states_info
*data
)
689 struct pp_hwmgr
*hwmgr
;
695 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
697 if (hwmgr
== NULL
|| hwmgr
->ps
== NULL
)
700 data
->nums
= hwmgr
->num_ps
;
702 for (i
= 0; i
< hwmgr
->num_ps
; i
++) {
703 struct pp_power_state
*state
= (struct pp_power_state
*)
704 ((unsigned long)hwmgr
->ps
+ i
* hwmgr
->ps_size
);
705 switch (state
->classification
.ui_label
) {
706 case PP_StateUILabel_Battery
:
707 data
->states
[i
] = POWER_STATE_TYPE_BATTERY
;
709 case PP_StateUILabel_Balanced
:
710 data
->states
[i
] = POWER_STATE_TYPE_BALANCED
;
712 case PP_StateUILabel_Performance
:
713 data
->states
[i
] = POWER_STATE_TYPE_PERFORMANCE
;
716 if (state
->classification
.flags
& PP_StateClassificationFlag_Boot
)
717 data
->states
[i
] = POWER_STATE_TYPE_INTERNAL_BOOT
;
719 data
->states
[i
] = POWER_STATE_TYPE_DEFAULT
;
726 static int pp_dpm_get_pp_table(void *handle
, char **table
)
728 struct pp_hwmgr
*hwmgr
;
733 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
737 if (hwmgr
->hwmgr_func
->get_pp_table
== NULL
) {
738 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
742 return hwmgr
->hwmgr_func
->get_pp_table(hwmgr
, table
);
745 static int pp_dpm_set_pp_table(void *handle
, const char *buf
, size_t size
)
747 struct pp_hwmgr
*hwmgr
;
752 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
756 if (hwmgr
->hwmgr_func
->set_pp_table
== NULL
) {
757 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
761 return hwmgr
->hwmgr_func
->set_pp_table(hwmgr
, buf
, size
);
764 static int pp_dpm_force_clock_level(void *handle
,
765 enum pp_clock_type type
, uint32_t mask
)
767 struct pp_hwmgr
*hwmgr
;
772 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
776 if (hwmgr
->hwmgr_func
->force_clock_level
== NULL
) {
777 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
781 return hwmgr
->hwmgr_func
->force_clock_level(hwmgr
, type
, mask
);
784 static int pp_dpm_print_clock_levels(void *handle
,
785 enum pp_clock_type type
, char *buf
)
787 struct pp_hwmgr
*hwmgr
;
792 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
796 if (hwmgr
->hwmgr_func
->print_clock_levels
== NULL
) {
797 printk(KERN_INFO
"%s was not implemented.\n", __func__
);
800 return hwmgr
->hwmgr_func
->print_clock_levels(hwmgr
, type
, buf
);
803 const struct amd_powerplay_funcs pp_dpm_funcs
= {
804 .get_temperature
= pp_dpm_get_temperature
,
805 .load_firmware
= pp_dpm_load_fw
,
806 .wait_for_fw_loading_complete
= pp_dpm_fw_loading_complete
,
807 .force_performance_level
= pp_dpm_force_performance_level
,
808 .get_performance_level
= pp_dpm_get_performance_level
,
809 .get_current_power_state
= pp_dpm_get_current_power_state
,
810 .get_sclk
= pp_dpm_get_sclk
,
811 .get_mclk
= pp_dpm_get_mclk
,
812 .powergate_vce
= pp_dpm_powergate_vce
,
813 .powergate_uvd
= pp_dpm_powergate_uvd
,
814 .dispatch_tasks
= pp_dpm_dispatch_tasks
,
815 .print_current_performance_level
= pp_debugfs_print_current_performance_level
,
816 .set_fan_control_mode
= pp_dpm_set_fan_control_mode
,
817 .get_fan_control_mode
= pp_dpm_get_fan_control_mode
,
818 .set_fan_speed_percent
= pp_dpm_set_fan_speed_percent
,
819 .get_fan_speed_percent
= pp_dpm_get_fan_speed_percent
,
820 .get_pp_num_states
= pp_dpm_get_pp_num_states
,
821 .get_pp_table
= pp_dpm_get_pp_table
,
822 .set_pp_table
= pp_dpm_set_pp_table
,
823 .force_clock_level
= pp_dpm_force_clock_level
,
824 .print_clock_levels
= pp_dpm_print_clock_levels
,
827 static int amd_pp_instance_init(struct amd_pp_init
*pp_init
,
828 struct amd_powerplay
*amd_pp
)
831 struct pp_instance
*handle
;
833 handle
= kzalloc(sizeof(struct pp_instance
), GFP_KERNEL
);
837 handle
->pp_valid
= PP_VALID
;
839 ret
= smum_init(pp_init
, handle
);
843 ret
= hwmgr_init(pp_init
, handle
);
847 ret
= eventmgr_init(handle
);
851 amd_pp
->pp_handle
= handle
;
855 hwmgr_fini(handle
->hwmgr
);
857 smum_fini(handle
->smu_mgr
);
863 static int amd_pp_instance_fini(void *handle
)
865 struct pp_instance
*instance
= (struct pp_instance
*)handle
;
867 if (instance
== NULL
)
870 eventmgr_fini(instance
->eventmgr
);
872 hwmgr_fini(instance
->hwmgr
);
874 smum_fini(instance
->smu_mgr
);
880 int amd_powerplay_init(struct amd_pp_init
*pp_init
,
881 struct amd_powerplay
*amd_pp
)
885 if (pp_init
== NULL
|| amd_pp
== NULL
)
888 ret
= amd_pp_instance_init(pp_init
, amd_pp
);
893 amd_pp
->ip_funcs
= &pp_ip_funcs
;
894 amd_pp
->pp_funcs
= &pp_dpm_funcs
;
899 int amd_powerplay_fini(void *handle
)
901 amd_pp_instance_fini(handle
);
906 /* export this function to DAL */
908 int amd_powerplay_display_configuration_change(void *handle
,
909 const struct amd_pp_display_configuration
*display_config
)
911 struct pp_hwmgr
*hwmgr
;
913 PP_CHECK((struct pp_instance
*)handle
);
915 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
917 phm_store_dal_configuration_data(hwmgr
, display_config
);
922 int amd_powerplay_get_display_power_level(void *handle
,
923 struct amd_pp_simple_clock_info
*output
)
925 struct pp_hwmgr
*hwmgr
;
927 PP_CHECK((struct pp_instance
*)handle
);
932 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
934 return phm_get_dal_power_level(hwmgr
, output
);
937 int amd_powerplay_get_current_clocks(void *handle
,
938 struct amd_pp_clock_info
*clocks
)
940 struct pp_hwmgr
*hwmgr
;
941 struct amd_pp_simple_clock_info simple_clocks
;
942 struct pp_clock_info hw_clocks
;
944 PP_CHECK((struct pp_instance
*)handle
);
949 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
951 phm_get_dal_power_level(hwmgr
, &simple_clocks
);
953 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_PowerContainment
)) {
954 if (0 != phm_get_clock_info(hwmgr
, &hwmgr
->current_ps
->hardware
, &hw_clocks
, PHM_PerformanceLevelDesignation_PowerContainment
))
955 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
957 if (0 != phm_get_clock_info(hwmgr
, &hwmgr
->current_ps
->hardware
, &hw_clocks
, PHM_PerformanceLevelDesignation_Activity
))
958 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
961 clocks
->min_engine_clock
= hw_clocks
.min_eng_clk
;
962 clocks
->max_engine_clock
= hw_clocks
.max_eng_clk
;
963 clocks
->min_memory_clock
= hw_clocks
.min_mem_clk
;
964 clocks
->max_memory_clock
= hw_clocks
.max_mem_clk
;
965 clocks
->min_bus_bandwidth
= hw_clocks
.min_bus_bandwidth
;
966 clocks
->max_bus_bandwidth
= hw_clocks
.max_bus_bandwidth
;
968 clocks
->max_engine_clock_in_sr
= hw_clocks
.max_eng_clk
;
969 clocks
->min_engine_clock_in_sr
= hw_clocks
.min_eng_clk
;
971 clocks
->max_clocks_state
= simple_clocks
.level
;
973 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr
, &hwmgr
->current_ps
->hardware
, &hw_clocks
)) {
974 clocks
->max_engine_clock_in_sr
= hw_clocks
.max_eng_clk
;
975 clocks
->min_engine_clock_in_sr
= hw_clocks
.min_eng_clk
;
982 int amd_powerplay_get_clock_by_type(void *handle
, enum amd_pp_clock_type type
, struct amd_pp_clocks
*clocks
)
986 struct pp_hwmgr
*hwmgr
;
988 PP_CHECK((struct pp_instance
*)handle
);
993 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
995 result
= phm_get_clock_by_type(hwmgr
, type
, clocks
);
1000 int amd_powerplay_get_display_mode_validation_clocks(void *handle
,
1001 struct amd_pp_simple_clock_info
*clocks
)
1004 struct pp_hwmgr
*hwmgr
;
1006 PP_CHECK((struct pp_instance
*)handle
);
1011 hwmgr
= ((struct pp_instance
*)handle
)->hwmgr
;
1013 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_DynamicPatchPowerState
))
1014 result
= phm_get_max_high_clocks(hwmgr
, clocks
);