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11 * The above copyright notice and this permission notice (including the
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21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <drm/drm_scdc_helper.h>
33 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
34 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
35 * HDMI source and HDMI sink to exchange data. The same I2C interface that
36 * is used to access EDID serves as the transport mechanism for SCDC.
39 #define SCDC_I2C_SLAVE_ADDRESS 0x54
42 * drm_scdc_read - read a block of data from SCDC
43 * @adapter: I2C controller
44 * @offset: start offset of block to read
45 * @buffer: return location for the block to read
46 * @size: size of the block to read
48 * Reads a block of data from SCDC, starting at a given offset.
51 * 0 on success, negative error code on failure.
53 ssize_t
drm_scdc_read(struct i2c_adapter
*adapter
, u8 offset
, void *buffer
,
57 struct i2c_msg msgs
[2] = {
59 .addr
= SCDC_I2C_SLAVE_ADDRESS
,
64 .addr
= SCDC_I2C_SLAVE_ADDRESS
,
71 ret
= i2c_transfer(adapter
, msgs
, ARRAY_SIZE(msgs
));
74 if (ret
!= ARRAY_SIZE(msgs
))
79 EXPORT_SYMBOL(drm_scdc_read
);
82 * drm_scdc_write - write a block of data to SCDC
83 * @adapter: I2C controller
84 * @offset: start offset of block to write
85 * @buffer: block of data to write
86 * @size: size of the block to write
88 * Writes a block of data to SCDC, starting at a given offset.
91 * 0 on success, negative error code on failure.
93 ssize_t
drm_scdc_write(struct i2c_adapter
*adapter
, u8 offset
,
94 const void *buffer
, size_t size
)
96 struct i2c_msg msg
= {
97 .addr
= SCDC_I2C_SLAVE_ADDRESS
,
105 data
= kmalloc(1 + size
, GFP_TEMPORARY
);
111 memcpy(data
, &offset
, sizeof(offset
));
112 memcpy(data
+ 1, buffer
, size
);
114 err
= i2c_transfer(adapter
, &msg
, 1);
125 EXPORT_SYMBOL(drm_scdc_write
);
128 * drm_scdc_check_scrambling_status - what is status of scrambling?
129 * @adapter: I2C adapter for DDC channel
131 * Reads the scrambler status over SCDC, and checks the
135 * True if the scrambling is enabled, false otherwise.
138 bool drm_scdc_get_scrambling_status(struct i2c_adapter
*adapter
)
143 ret
= drm_scdc_readb(adapter
, SCDC_SCRAMBLER_STATUS
, &status
);
145 DRM_ERROR("Failed to read scrambling status, error %d\n", ret
);
149 return status
& SCDC_SCRAMBLING_STATUS
;
151 EXPORT_SYMBOL(drm_scdc_get_scrambling_status
);
154 * drm_scdc_set_scrambling - enable scrambling
155 * @adapter: I2C adapter for DDC channel
156 * @enable: bool to indicate if scrambling is to be enabled/disabled
158 * Writes the TMDS config register over SCDC channel, and:
159 * enables scrambling when enable = 1
160 * disables scrambling when enable = 0
163 * True if scrambling is set/reset successfully, false otherwise.
166 bool drm_scdc_set_scrambling(struct i2c_adapter
*adapter
, bool enable
)
171 ret
= drm_scdc_readb(adapter
, SCDC_TMDS_CONFIG
, &config
);
173 DRM_ERROR("Failed to read tmds config, err=%d\n", ret
);
178 config
|= SCDC_SCRAMBLING_ENABLE
;
180 config
&= ~SCDC_SCRAMBLING_ENABLE
;
182 ret
= drm_scdc_writeb(adapter
, SCDC_TMDS_CONFIG
, config
);
184 DRM_ERROR("Failed to enable scrambling, error %d\n", ret
);
190 EXPORT_SYMBOL(drm_scdc_set_scrambling
);
193 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
194 * @adapter: I2C adapter for DDC channel
195 * @set: ret or reset the high clock ratio
197 * TMDS clock ratio calculations go like this:
198 * TMDS character = 10 bit TMDS encoded value
199 * TMDS character rate = The rate at which TMDS characters are transmitted(Mcsc)
200 * TMDS bit rate = 10x TMDS character rate
202 * TMDS clock rate for pixel clock < 340 MHz = 1x the character rate
203 * = 1/10 pixel clock rate
204 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character rate
205 * = 1/40 pixel clock rate
207 * Writes to the TMDS config register over SCDC channel, and:
208 * sets TMDS clock ratio to 1/40 when set = 1
209 * sets TMDS clock ratio to 1/10 when set = 0
212 * True if write is successful, false otherwise.
214 bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter
*adapter
, bool set
)
219 ret
= drm_scdc_readb(adapter
, SCDC_TMDS_CONFIG
, &config
);
221 DRM_ERROR("Failed to read tmds config, err=%d\n", ret
);
226 config
|= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40
;
228 config
&= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40
;
230 ret
= drm_scdc_writeb(adapter
, SCDC_TMDS_CONFIG
, config
);
232 DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret
);
237 * The spec says that a source should wait minimum 1ms and maximum
238 * 100ms after writing the TMDS config for clock ratio. Lets allow a
239 * wait of upto 2ms here.
241 usleep_range(1000, 2000);
244 EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio
);