drivers/gpu/drm/etnaviv/etnaviv_gpu.h

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __ETNAVIV_GPU_H__
  18 #define __ETNAVIV_GPU_H__
  19
  20 #include <linux/clk.h>
  21 #include <linux/regulator/consumer.h>
  22
  23 #include "etnaviv_drv.h"
  24
  25 struct etnaviv_gem_submit;
  26 struct etnaviv_vram_mapping;
  27
  28 struct etnaviv_chip_identity {
  29         /* Chip model. */
  30         u32 model;
  31
  32         /* Revision value.*/
  33         u32 revision;
  34
  35         /* Supported feature fields. */
  36         u32 features;
  37
  38         /* Supported minor feature fields. */
  39         u32 minor_features0;
  40
  41         /* Supported minor feature 1 fields. */
  42         u32 minor_features1;
  43
  44         /* Supported minor feature 2 fields. */
  45         u32 minor_features2;
  46
  47         /* Supported minor feature 3 fields. */
  48         u32 minor_features3;
  49
  50         /* Supported minor feature 4 fields. */
  51         u32 minor_features4;
  52
  53         /* Supported minor feature 5 fields. */
  54         u32 minor_features5;
  55
  56         /* Number of streams supported. */
  57         u32 stream_count;
  58
  59         /* Total number of temporary registers per thread. */
  60         u32 register_max;
  61
  62         /* Maximum number of threads. */
  63         u32 thread_count;
  64
  65         /* Number of shader cores. */
  66         u32 shader_core_count;
  67
  68         /* Size of the vertex cache. */
  69         u32 vertex_cache_size;
  70
  71         /* Number of entries in the vertex output buffer. */
  72         u32 vertex_output_buffer_size;
  73
  74         /* Number of pixel pipes. */
  75         u32 pixel_pipes;
  76
  77         /* Number of instructions. */
  78         u32 instruction_count;
  79
  80         /* Number of constants. */
  81         u32 num_constants;
  82
  83         /* Buffer size */
  84         u32 buffer_size;
  85
  86         /* Number of varyings */
  87         u8 varyings_count;
  88 };
  89
  90 struct etnaviv_event {
  91         bool used;
  92         struct dma_fence *fence;
  93 };
  94
  95 struct etnaviv_cmdbuf;
  96
  97 struct etnaviv_gpu {
  98         struct drm_device *drm;
  99         struct device *dev;
 100         struct mutex lock;
 101         struct etnaviv_chip_identity identity;
 102         struct etnaviv_file_private *lastctx;
 103         bool switch_context;
 104
 105         /* 'ring'-buffer: */
 106         struct etnaviv_cmdbuf *buffer;
 107         int exec_state;
 108
 109         /* bus base address of memory  */
 110         u32 memory_base;
 111
 112         /* event management: */
 113         struct etnaviv_event event[30];
 114         struct completion event_free;
 115         spinlock_t event_spinlock;
 116
 117         /* list of currently in-flight command buffers */
 118         struct list_head active_cmd_list;
 119
 120         u32 idle_mask;
 121
 122         /* Fencing support */
 123         u32 next_fence;
 124         u32 active_fence;
 125         u32 completed_fence;
 126         u32 retired_fence;
 127         wait_queue_head_t fence_event;
 128         u64 fence_context;
 129         spinlock_t fence_spinlock;
 130
 131         /* worker for handling active-list retiring: */
 132         struct work_struct retire_work;
 133
 134         void __iomem *mmio;
 135         int irq;
 136
 137         struct etnaviv_iommu *mmu;
 138
 139         /* Power Control: */
 140         struct clk *clk_bus;
 141         struct clk *clk_core;
 142         struct clk *clk_shader;
 143
 144         /* Hang Detction: */
 145 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
 146 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
 147         struct timer_list hangcheck_timer;
 148         u32 hangcheck_fence;
 149         u32 hangcheck_dma_addr;
 150         struct work_struct recover_work;
 151 };
 152
 153 struct etnaviv_cmdbuf {
 154         /* device this cmdbuf is allocated for */
 155         struct etnaviv_gpu *gpu;
 156         /* user context key, must be unique between all active users */
 157         struct etnaviv_file_private *ctx;
 158         /* cmdbuf properties */
 159         void *vaddr;
 160         dma_addr_t paddr;
 161         u32 size;
 162         u32 user_size;
 163         /* vram node used if the cmdbuf is mapped through the MMUv2 */
 164         struct drm_mm_node vram_node;
 165         /* fence after which this buffer is to be disposed */
 166         struct dma_fence *fence;
 167         /* target exec state */
 168         u32 exec_state;
 169         /* per GPU in-flight list */
 170         struct list_head node;
 171         /* BOs attached to this command buffer */
 172         unsigned int nr_bos;
 173         struct etnaviv_vram_mapping *bo_map[0];
 174 };
 175
 176 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
 177 {
 178         etnaviv_writel(data, gpu->mmio + reg);
 179 }
 180
 181 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
 182 {
 183         return etnaviv_readl(gpu->mmio + reg);
 184 }
 185
 186 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
 187 {
 188         return fence_after_eq(gpu->completed_fence, fence);
 189 }
 190
 191 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
 192 {
 193         return fence_after_eq(gpu->retired_fence, fence);
 194 }
 195
 196 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
 197
 198 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
 199
 200 #ifdef CONFIG_DEBUG_FS
 201 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
 202 #endif
 203
 204 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
 205         unsigned int context, bool exclusive);
 206
 207 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
 208 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
 209         u32 fence, struct timespec *timeout);
 210 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
 211         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
 212 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
 213         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf);
 214 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu,
 215                                               u32 size, size_t nr_bos);
 216 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf);
 217 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
 218 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
 219 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
 220 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
 221
 222 extern struct platform_driver etnaviv_gpu_driver;
 223
 224 #endif /* __ETNAVIV_GPU_H__ */