2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (obj
->user_pin_count
> 0)
101 else if (i915_gem_obj_is_pinned(obj
))
107 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
109 switch (obj
->tiling_mode
) {
111 case I915_TILING_NONE
: return " ";
112 case I915_TILING_X
: return "X";
113 case I915_TILING_Y
: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->has_global_gtt_mapping
? "g" : " ";
123 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
128 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj
),
132 get_global_flag(obj
),
133 obj
->base
.size
/ 1024,
134 obj
->base
.read_domains
,
135 obj
->base
.write_domain
,
136 obj
->last_read_seqno
,
137 obj
->last_write_seqno
,
138 obj
->last_fenced_seqno
,
139 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
140 obj
->dirty
? " dirty" : "",
141 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
143 seq_printf(m
, " (name: %d)", obj
->base
.name
);
144 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
145 if (vma
->pin_count
> 0)
147 seq_printf(m
, " (pinned x %d)", pin_count
);
148 if (obj
->pin_display
)
149 seq_printf(m
, " (display)");
150 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
151 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
152 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
153 if (!i915_is_ggtt(vma
->vm
))
157 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
158 vma
->node
.start
, vma
->node
.size
);
161 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->ring
!= NULL
)
172 seq_printf(m
, " (%s)", obj
->ring
->name
);
173 if (obj
->frontbuffer_bits
)
174 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
177 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
179 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
180 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
184 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
186 struct drm_info_node
*node
= m
->private;
187 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
188 struct list_head
*head
;
189 struct drm_device
*dev
= node
->minor
->dev
;
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
192 struct i915_vma
*vma
;
193 size_t total_obj_size
, total_gtt_size
;
196 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
200 /* FIXME: the user of this interface might want more than just GGTT */
203 seq_puts(m
, "Active:\n");
204 head
= &vm
->active_list
;
207 seq_puts(m
, "Inactive:\n");
208 head
= &vm
->inactive_list
;
211 mutex_unlock(&dev
->struct_mutex
);
215 total_obj_size
= total_gtt_size
= count
= 0;
216 list_for_each_entry(vma
, head
, mm_list
) {
218 describe_obj(m
, vma
->obj
);
220 total_obj_size
+= vma
->obj
->base
.size
;
221 total_gtt_size
+= vma
->node
.size
;
224 mutex_unlock(&dev
->struct_mutex
);
226 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count
, total_obj_size
, total_gtt_size
);
231 static int obj_rank_by_stolen(void *priv
,
232 struct list_head
*A
, struct list_head
*B
)
234 struct drm_i915_gem_object
*a
=
235 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
236 struct drm_i915_gem_object
*b
=
237 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
239 return a
->stolen
->start
- b
->stolen
->start
;
242 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
244 struct drm_info_node
*node
= m
->private;
245 struct drm_device
*dev
= node
->minor
->dev
;
246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 struct drm_i915_gem_object
*obj
;
248 size_t total_obj_size
, total_gtt_size
;
252 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
256 total_obj_size
= total_gtt_size
= count
= 0;
257 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
258 if (obj
->stolen
== NULL
)
261 list_add(&obj
->obj_exec_link
, &stolen
);
263 total_obj_size
+= obj
->base
.size
;
264 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
267 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
268 if (obj
->stolen
== NULL
)
271 list_add(&obj
->obj_exec_link
, &stolen
);
273 total_obj_size
+= obj
->base
.size
;
276 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
277 seq_puts(m
, "Stolen:\n");
278 while (!list_empty(&stolen
)) {
279 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
281 describe_obj(m
, obj
);
283 list_del_init(&obj
->obj_exec_link
);
285 mutex_unlock(&dev
->struct_mutex
);
287 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count
, total_obj_size
, total_gtt_size
);
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
304 struct drm_i915_file_private
*file_priv
;
306 size_t total
, unbound
;
307 size_t global
, shared
;
308 size_t active
, inactive
;
311 static int per_file_stats(int id
, void *ptr
, void *data
)
313 struct drm_i915_gem_object
*obj
= ptr
;
314 struct file_stats
*stats
= data
;
315 struct i915_vma
*vma
;
318 stats
->total
+= obj
->base
.size
;
320 if (obj
->base
.name
|| obj
->base
.dma_buf
)
321 stats
->shared
+= obj
->base
.size
;
323 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
324 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
325 struct i915_hw_ppgtt
*ppgtt
;
327 if (!drm_mm_node_allocated(&vma
->node
))
330 if (i915_is_ggtt(vma
->vm
)) {
331 stats
->global
+= obj
->base
.size
;
335 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
336 if (ppgtt
->file_priv
!= stats
->file_priv
)
339 if (obj
->ring
) /* XXX per-vma statistic */
340 stats
->active
+= obj
->base
.size
;
342 stats
->inactive
+= obj
->base
.size
;
347 if (i915_gem_obj_ggtt_bound(obj
)) {
348 stats
->global
+= obj
->base
.size
;
350 stats
->active
+= obj
->base
.size
;
352 stats
->inactive
+= obj
->base
.size
;
357 if (!list_empty(&obj
->global_list
))
358 stats
->unbound
+= obj
->base
.size
;
363 #define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
374 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
376 struct drm_info_node
*node
= m
->private;
377 struct drm_device
*dev
= node
->minor
->dev
;
378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
379 u32 count
, mappable_count
, purgeable_count
;
380 size_t size
, mappable_size
, purgeable_size
;
381 struct drm_i915_gem_object
*obj
;
382 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
383 struct drm_file
*file
;
384 struct i915_vma
*vma
;
387 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
391 seq_printf(m
, "%u objects, %zu bytes\n",
392 dev_priv
->mm
.object_count
,
393 dev_priv
->mm
.object_memory
);
395 size
= count
= mappable_size
= mappable_count
= 0;
396 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
397 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count
, mappable_count
, size
, mappable_size
);
400 size
= count
= mappable_size
= mappable_count
= 0;
401 count_vmas(&vm
->active_list
, mm_list
);
402 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count
, mappable_count
, size
, mappable_size
);
405 size
= count
= mappable_size
= mappable_count
= 0;
406 count_vmas(&vm
->inactive_list
, mm_list
);
407 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count
, mappable_count
, size
, mappable_size
);
410 size
= count
= purgeable_size
= purgeable_count
= 0;
411 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
412 size
+= obj
->base
.size
, ++count
;
413 if (obj
->madv
== I915_MADV_DONTNEED
)
414 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
416 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
418 size
= count
= mappable_size
= mappable_count
= 0;
419 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
420 if (obj
->fault_mappable
) {
421 size
+= i915_gem_obj_ggtt_size(obj
);
424 if (obj
->pin_mappable
) {
425 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
428 if (obj
->madv
== I915_MADV_DONTNEED
) {
429 purgeable_size
+= obj
->base
.size
;
433 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
434 purgeable_count
, purgeable_size
);
435 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count
, mappable_size
);
437 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
440 seq_printf(m
, "%zu [%lu] gtt total\n",
441 dev_priv
->gtt
.base
.total
,
442 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
445 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
446 struct file_stats stats
;
447 struct task_struct
*task
;
449 memset(&stats
, 0, sizeof(stats
));
450 stats
.file_priv
= file
->driver_priv
;
451 spin_lock(&file
->table_lock
);
452 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
453 spin_unlock(&file
->table_lock
);
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
461 task
= pid_task(file
->pid
, PIDTYPE_PID
);
462 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
463 task
? task
->comm
: "<unknown>",
474 mutex_unlock(&dev
->struct_mutex
);
479 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
481 struct drm_info_node
*node
= m
->private;
482 struct drm_device
*dev
= node
->minor
->dev
;
483 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
485 struct drm_i915_gem_object
*obj
;
486 size_t total_obj_size
, total_gtt_size
;
489 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
493 total_obj_size
= total_gtt_size
= count
= 0;
494 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
495 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
499 describe_obj(m
, obj
);
501 total_obj_size
+= obj
->base
.size
;
502 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
506 mutex_unlock(&dev
->struct_mutex
);
508 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count
, total_obj_size
, total_gtt_size
);
514 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
516 struct drm_info_node
*node
= m
->private;
517 struct drm_device
*dev
= node
->minor
->dev
;
519 struct intel_crtc
*crtc
;
522 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
526 for_each_intel_crtc(dev
, crtc
) {
527 const char pipe
= pipe_name(crtc
->pipe
);
528 const char plane
= plane_name(crtc
->plane
);
529 struct intel_unpin_work
*work
;
531 spin_lock_irqsave(&dev
->event_lock
, flags
);
532 work
= crtc
->unpin_work
;
534 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
537 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
538 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
541 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
544 if (work
->enable_stall_check
)
545 seq_puts(m
, "Stall check enabled, ");
547 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
548 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
550 if (work
->old_fb_obj
) {
551 struct drm_i915_gem_object
*obj
= work
->old_fb_obj
;
553 seq_printf(m
, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj
));
556 if (work
->pending_flip_obj
) {
557 struct drm_i915_gem_object
*obj
= work
->pending_flip_obj
;
559 seq_printf(m
, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj
));
563 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
566 mutex_unlock(&dev
->struct_mutex
);
571 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
573 struct drm_info_node
*node
= m
->private;
574 struct drm_device
*dev
= node
->minor
->dev
;
575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
576 struct intel_engine_cs
*ring
;
577 struct drm_i915_gem_request
*gem_request
;
580 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
585 for_each_ring(ring
, dev_priv
, i
) {
586 if (list_empty(&ring
->request_list
))
589 seq_printf(m
, "%s requests:\n", ring
->name
);
590 list_for_each_entry(gem_request
,
593 seq_printf(m
, " %d @ %d\n",
595 (int) (jiffies
- gem_request
->emitted_jiffies
));
599 mutex_unlock(&dev
->struct_mutex
);
602 seq_puts(m
, "No requests\n");
607 static void i915_ring_seqno_info(struct seq_file
*m
,
608 struct intel_engine_cs
*ring
)
610 if (ring
->get_seqno
) {
611 seq_printf(m
, "Current sequence (%s): %u\n",
612 ring
->name
, ring
->get_seqno(ring
, false));
616 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
618 struct drm_info_node
*node
= m
->private;
619 struct drm_device
*dev
= node
->minor
->dev
;
620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
621 struct intel_engine_cs
*ring
;
624 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
627 intel_runtime_pm_get(dev_priv
);
629 for_each_ring(ring
, dev_priv
, i
)
630 i915_ring_seqno_info(m
, ring
);
632 intel_runtime_pm_put(dev_priv
);
633 mutex_unlock(&dev
->struct_mutex
);
639 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
641 struct drm_info_node
*node
= m
->private;
642 struct drm_device
*dev
= node
->minor
->dev
;
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
644 struct intel_engine_cs
*ring
;
647 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
650 intel_runtime_pm_get(dev_priv
);
652 if (IS_CHERRYVIEW(dev
)) {
654 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ
));
657 seq_printf(m
, "Display IER:\t%08x\n",
659 seq_printf(m
, "Display IIR:\t%08x\n",
661 seq_printf(m
, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW
));
663 seq_printf(m
, "Display IMR:\t%08x\n",
665 for_each_pipe(dev_priv
, pipe
)
666 seq_printf(m
, "Pipe %c stat:\t%08x\n",
668 I915_READ(PIPESTAT(pipe
)));
670 seq_printf(m
, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN
));
672 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT
));
674 seq_printf(m
, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT
));
677 for (i
= 0; i
< 4; i
++) {
678 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
679 i
, I915_READ(GEN8_GT_IMR(i
)));
680 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
681 i
, I915_READ(GEN8_GT_IIR(i
)));
682 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
683 i
, I915_READ(GEN8_GT_IER(i
)));
686 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR
));
688 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR
));
690 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER
));
692 } else if (INTEL_INFO(dev
)->gen
>= 8) {
693 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ
));
696 for (i
= 0; i
< 4; i
++) {
697 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
698 i
, I915_READ(GEN8_GT_IMR(i
)));
699 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
700 i
, I915_READ(GEN8_GT_IIR(i
)));
701 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
702 i
, I915_READ(GEN8_GT_IER(i
)));
705 for_each_pipe(dev_priv
, pipe
) {
706 if (!intel_display_power_enabled(dev_priv
,
707 POWER_DOMAIN_PIPE(pipe
))) {
708 seq_printf(m
, "Pipe %c power disabled\n",
712 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
714 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
715 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
717 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
718 seq_printf(m
, "Pipe %c IER:\t%08x\n",
720 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
723 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
724 I915_READ(GEN8_DE_PORT_IMR
));
725 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
726 I915_READ(GEN8_DE_PORT_IIR
));
727 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
728 I915_READ(GEN8_DE_PORT_IER
));
730 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
731 I915_READ(GEN8_DE_MISC_IMR
));
732 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
733 I915_READ(GEN8_DE_MISC_IIR
));
734 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
735 I915_READ(GEN8_DE_MISC_IER
));
737 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
738 I915_READ(GEN8_PCU_IMR
));
739 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
740 I915_READ(GEN8_PCU_IIR
));
741 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
742 I915_READ(GEN8_PCU_IER
));
743 } else if (IS_VALLEYVIEW(dev
)) {
744 seq_printf(m
, "Display IER:\t%08x\n",
746 seq_printf(m
, "Display IIR:\t%08x\n",
748 seq_printf(m
, "Display IIR_RW:\t%08x\n",
749 I915_READ(VLV_IIR_RW
));
750 seq_printf(m
, "Display IMR:\t%08x\n",
752 for_each_pipe(dev_priv
, pipe
)
753 seq_printf(m
, "Pipe %c stat:\t%08x\n",
755 I915_READ(PIPESTAT(pipe
)));
757 seq_printf(m
, "Master IER:\t%08x\n",
758 I915_READ(VLV_MASTER_IER
));
760 seq_printf(m
, "Render IER:\t%08x\n",
762 seq_printf(m
, "Render IIR:\t%08x\n",
764 seq_printf(m
, "Render IMR:\t%08x\n",
767 seq_printf(m
, "PM IER:\t\t%08x\n",
768 I915_READ(GEN6_PMIER
));
769 seq_printf(m
, "PM IIR:\t\t%08x\n",
770 I915_READ(GEN6_PMIIR
));
771 seq_printf(m
, "PM IMR:\t\t%08x\n",
772 I915_READ(GEN6_PMIMR
));
774 seq_printf(m
, "Port hotplug:\t%08x\n",
775 I915_READ(PORT_HOTPLUG_EN
));
776 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
777 I915_READ(VLV_DPFLIPSTAT
));
778 seq_printf(m
, "DPINVGTT:\t%08x\n",
779 I915_READ(DPINVGTT
));
781 } else if (!HAS_PCH_SPLIT(dev
)) {
782 seq_printf(m
, "Interrupt enable: %08x\n",
784 seq_printf(m
, "Interrupt identity: %08x\n",
786 seq_printf(m
, "Interrupt mask: %08x\n",
788 for_each_pipe(dev_priv
, pipe
)
789 seq_printf(m
, "Pipe %c stat: %08x\n",
791 I915_READ(PIPESTAT(pipe
)));
793 seq_printf(m
, "North Display Interrupt enable: %08x\n",
795 seq_printf(m
, "North Display Interrupt identity: %08x\n",
797 seq_printf(m
, "North Display Interrupt mask: %08x\n",
799 seq_printf(m
, "South Display Interrupt enable: %08x\n",
801 seq_printf(m
, "South Display Interrupt identity: %08x\n",
803 seq_printf(m
, "South Display Interrupt mask: %08x\n",
805 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
807 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
809 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
812 for_each_ring(ring
, dev_priv
, i
) {
813 if (INTEL_INFO(dev
)->gen
>= 6) {
815 "Graphics Interrupt mask (%s): %08x\n",
816 ring
->name
, I915_READ_IMR(ring
));
818 i915_ring_seqno_info(m
, ring
);
820 intel_runtime_pm_put(dev_priv
);
821 mutex_unlock(&dev
->struct_mutex
);
826 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
828 struct drm_info_node
*node
= m
->private;
829 struct drm_device
*dev
= node
->minor
->dev
;
830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
833 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
837 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
838 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
839 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
840 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
842 seq_printf(m
, "Fence %d, pin count = %d, object = ",
843 i
, dev_priv
->fence_regs
[i
].pin_count
);
845 seq_puts(m
, "unused");
847 describe_obj(m
, obj
);
851 mutex_unlock(&dev
->struct_mutex
);
855 static int i915_hws_info(struct seq_file
*m
, void *data
)
857 struct drm_info_node
*node
= m
->private;
858 struct drm_device
*dev
= node
->minor
->dev
;
859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
860 struct intel_engine_cs
*ring
;
864 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
865 hws
= ring
->status_page
.page_addr
;
869 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
870 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
872 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
878 i915_error_state_write(struct file
*filp
,
879 const char __user
*ubuf
,
883 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
884 struct drm_device
*dev
= error_priv
->dev
;
887 DRM_DEBUG_DRIVER("Resetting error state\n");
889 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
893 i915_destroy_error_state(dev
);
894 mutex_unlock(&dev
->struct_mutex
);
899 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
901 struct drm_device
*dev
= inode
->i_private
;
902 struct i915_error_state_file_priv
*error_priv
;
904 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
908 error_priv
->dev
= dev
;
910 i915_error_state_get(dev
, error_priv
);
912 file
->private_data
= error_priv
;
917 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
919 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
921 i915_error_state_put(error_priv
);
927 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
928 size_t count
, loff_t
*pos
)
930 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
931 struct drm_i915_error_state_buf error_str
;
933 ssize_t ret_count
= 0;
936 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
940 ret
= i915_error_state_to_str(&error_str
, error_priv
);
944 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
951 *pos
= error_str
.start
+ ret_count
;
953 i915_error_state_buf_release(&error_str
);
954 return ret
?: ret_count
;
957 static const struct file_operations i915_error_state_fops
= {
958 .owner
= THIS_MODULE
,
959 .open
= i915_error_state_open
,
960 .read
= i915_error_state_read
,
961 .write
= i915_error_state_write
,
962 .llseek
= default_llseek
,
963 .release
= i915_error_state_release
,
967 i915_next_seqno_get(void *data
, u64
*val
)
969 struct drm_device
*dev
= data
;
970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
973 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
977 *val
= dev_priv
->next_seqno
;
978 mutex_unlock(&dev
->struct_mutex
);
984 i915_next_seqno_set(void *data
, u64 val
)
986 struct drm_device
*dev
= data
;
989 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
993 ret
= i915_gem_set_seqno(dev
, val
);
994 mutex_unlock(&dev
->struct_mutex
);
999 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1000 i915_next_seqno_get
, i915_next_seqno_set
,
1003 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1005 struct drm_info_node
*node
= m
->private;
1006 struct drm_device
*dev
= node
->minor
->dev
;
1007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1010 intel_runtime_pm_get(dev_priv
);
1012 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1015 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1016 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1018 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1019 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1020 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1022 seq_printf(m
, "Current P-state: %d\n",
1023 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1024 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1025 IS_BROADWELL(dev
)) {
1026 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1027 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1028 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1029 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1030 u32 rpstat
, cagf
, reqf
;
1031 u32 rpupei
, rpcurup
, rpprevup
;
1032 u32 rpdownei
, rpcurdown
, rpprevdown
;
1033 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1036 /* RPSTAT1 is in the GT power well */
1037 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1041 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
1043 reqf
= I915_READ(GEN6_RPNSWREQ
);
1044 reqf
&= ~GEN6_TURBO_DISABLE
;
1045 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1049 reqf
*= GT_FREQUENCY_MULTIPLIER
;
1051 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1052 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1053 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1055 rpstat
= I915_READ(GEN6_RPSTAT1
);
1056 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1057 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1058 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1059 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1060 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1061 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1062 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1063 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1065 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1066 cagf
*= GT_FREQUENCY_MULTIPLIER
;
1068 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
1069 mutex_unlock(&dev
->struct_mutex
);
1071 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1072 pm_ier
= I915_READ(GEN6_PMIER
);
1073 pm_imr
= I915_READ(GEN6_PMIMR
);
1074 pm_isr
= I915_READ(GEN6_PMISR
);
1075 pm_iir
= I915_READ(GEN6_PMIIR
);
1076 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1078 pm_ier
= I915_READ(GEN8_GT_IER(2));
1079 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1080 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1081 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1082 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1084 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1085 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1086 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1087 seq_printf(m
, "Render p-state ratio: %d\n",
1088 (gt_perf_status
& 0xff00) >> 8);
1089 seq_printf(m
, "Render p-state VID: %d\n",
1090 gt_perf_status
& 0xff);
1091 seq_printf(m
, "Render p-state limit: %d\n",
1092 rp_state_limits
& 0xff);
1093 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1094 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1095 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1096 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1097 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1098 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1099 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1100 GEN6_CURICONT_MASK
);
1101 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1102 GEN6_CURBSYTAVG_MASK
);
1103 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1104 GEN6_CURBSYTAVG_MASK
);
1105 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1107 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1108 GEN6_CURBSYTAVG_MASK
);
1109 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1110 GEN6_CURBSYTAVG_MASK
);
1112 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1113 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1114 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1116 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1117 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1118 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1120 max_freq
= rp_state_cap
& 0xff;
1121 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1122 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1124 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1125 dev_priv
->rps
.max_freq
* GT_FREQUENCY_MULTIPLIER
);
1126 } else if (IS_VALLEYVIEW(dev
)) {
1129 mutex_lock(&dev_priv
->rps
.hw_lock
);
1130 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1131 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1132 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1134 seq_printf(m
, "max GPU freq: %d MHz\n",
1135 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1137 seq_printf(m
, "min GPU freq: %d MHz\n",
1138 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1140 seq_printf(m
, "efficient (RPe) frequency: %d MHz\n",
1141 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1143 seq_printf(m
, "current GPU freq: %d MHz\n",
1144 vlv_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1145 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1147 seq_puts(m
, "no P-state info available\n");
1151 intel_runtime_pm_put(dev_priv
);
1155 static int ironlake_drpc_info(struct seq_file
*m
)
1157 struct drm_info_node
*node
= m
->private;
1158 struct drm_device
*dev
= node
->minor
->dev
;
1159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1160 u32 rgvmodectl
, rstdbyctl
;
1164 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1167 intel_runtime_pm_get(dev_priv
);
1169 rgvmodectl
= I915_READ(MEMMODECTL
);
1170 rstdbyctl
= I915_READ(RSTDBYCTL
);
1171 crstandvid
= I915_READ16(CRSTANDVID
);
1173 intel_runtime_pm_put(dev_priv
);
1174 mutex_unlock(&dev
->struct_mutex
);
1176 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1178 seq_printf(m
, "Boost freq: %d\n",
1179 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1180 MEMMODE_BOOST_FREQ_SHIFT
);
1181 seq_printf(m
, "HW control enabled: %s\n",
1182 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1183 seq_printf(m
, "SW control enabled: %s\n",
1184 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1185 seq_printf(m
, "Gated voltage change: %s\n",
1186 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1187 seq_printf(m
, "Starting frequency: P%d\n",
1188 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1189 seq_printf(m
, "Max P-state: P%d\n",
1190 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1191 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1192 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1193 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1194 seq_printf(m
, "Render standby enabled: %s\n",
1195 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1196 seq_puts(m
, "Current RS state: ");
1197 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1199 seq_puts(m
, "on\n");
1201 case RSX_STATUS_RC1
:
1202 seq_puts(m
, "RC1\n");
1204 case RSX_STATUS_RC1E
:
1205 seq_puts(m
, "RC1E\n");
1207 case RSX_STATUS_RS1
:
1208 seq_puts(m
, "RS1\n");
1210 case RSX_STATUS_RS2
:
1211 seq_puts(m
, "RS2 (RC6)\n");
1213 case RSX_STATUS_RS3
:
1214 seq_puts(m
, "RC3 (RC6+)\n");
1217 seq_puts(m
, "unknown\n");
1224 static int vlv_drpc_info(struct seq_file
*m
)
1227 struct drm_info_node
*node
= m
->private;
1228 struct drm_device
*dev
= node
->minor
->dev
;
1229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1230 u32 rpmodectl1
, rcctl1
;
1231 unsigned fw_rendercount
= 0, fw_mediacount
= 0;
1233 intel_runtime_pm_get(dev_priv
);
1235 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1236 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1238 intel_runtime_pm_put(dev_priv
);
1240 seq_printf(m
, "Video Turbo Mode: %s\n",
1241 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1242 seq_printf(m
, "Turbo enabled: %s\n",
1243 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1244 seq_printf(m
, "HW control enabled: %s\n",
1245 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1246 seq_printf(m
, "SW control enabled: %s\n",
1247 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1248 GEN6_RP_MEDIA_SW_MODE
));
1249 seq_printf(m
, "RC6 Enabled: %s\n",
1250 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1251 GEN6_RC_CTL_EI_MODE(1))));
1252 seq_printf(m
, "Render Power Well: %s\n",
1253 (I915_READ(VLV_GTLC_PW_STATUS
) &
1254 VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1255 seq_printf(m
, "Media Power Well: %s\n",
1256 (I915_READ(VLV_GTLC_PW_STATUS
) &
1257 VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1259 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1260 I915_READ(VLV_GT_RENDER_RC6
));
1261 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1262 I915_READ(VLV_GT_MEDIA_RC6
));
1264 spin_lock_irq(&dev_priv
->uncore
.lock
);
1265 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1266 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1267 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1269 seq_printf(m
, "Forcewake Render Count = %u\n", fw_rendercount
);
1270 seq_printf(m
, "Forcewake Media Count = %u\n", fw_mediacount
);
1277 static int gen6_drpc_info(struct seq_file
*m
)
1280 struct drm_info_node
*node
= m
->private;
1281 struct drm_device
*dev
= node
->minor
->dev
;
1282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1283 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1284 unsigned forcewake_count
;
1287 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1290 intel_runtime_pm_get(dev_priv
);
1292 spin_lock_irq(&dev_priv
->uncore
.lock
);
1293 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1294 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1296 if (forcewake_count
) {
1297 seq_puts(m
, "RC information inaccurate because somebody "
1298 "holds a forcewake reference \n");
1300 /* NB: we cannot use forcewake, else we read the wrong values */
1301 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1303 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1306 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1307 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1309 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1310 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1311 mutex_unlock(&dev
->struct_mutex
);
1312 mutex_lock(&dev_priv
->rps
.hw_lock
);
1313 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1314 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1316 intel_runtime_pm_put(dev_priv
);
1318 seq_printf(m
, "Video Turbo Mode: %s\n",
1319 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1320 seq_printf(m
, "HW control enabled: %s\n",
1321 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1322 seq_printf(m
, "SW control enabled: %s\n",
1323 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1324 GEN6_RP_MEDIA_SW_MODE
));
1325 seq_printf(m
, "RC1e Enabled: %s\n",
1326 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1327 seq_printf(m
, "RC6 Enabled: %s\n",
1328 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1329 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1330 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1331 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1332 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1333 seq_puts(m
, "Current RC state: ");
1334 switch (gt_core_status
& GEN6_RCn_MASK
) {
1336 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1337 seq_puts(m
, "Core Power Down\n");
1339 seq_puts(m
, "on\n");
1342 seq_puts(m
, "RC3\n");
1345 seq_puts(m
, "RC6\n");
1348 seq_puts(m
, "RC7\n");
1351 seq_puts(m
, "Unknown\n");
1355 seq_printf(m
, "Core Power Down: %s\n",
1356 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1358 /* Not exactly sure what this is */
1359 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1360 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1361 seq_printf(m
, "RC6 residency since boot: %u\n",
1362 I915_READ(GEN6_GT_GFX_RC6
));
1363 seq_printf(m
, "RC6+ residency since boot: %u\n",
1364 I915_READ(GEN6_GT_GFX_RC6p
));
1365 seq_printf(m
, "RC6++ residency since boot: %u\n",
1366 I915_READ(GEN6_GT_GFX_RC6pp
));
1368 seq_printf(m
, "RC6 voltage: %dmV\n",
1369 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1370 seq_printf(m
, "RC6+ voltage: %dmV\n",
1371 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1372 seq_printf(m
, "RC6++ voltage: %dmV\n",
1373 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1377 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1379 struct drm_info_node
*node
= m
->private;
1380 struct drm_device
*dev
= node
->minor
->dev
;
1382 if (IS_VALLEYVIEW(dev
))
1383 return vlv_drpc_info(m
);
1384 else if (INTEL_INFO(dev
)->gen
>= 6)
1385 return gen6_drpc_info(m
);
1387 return ironlake_drpc_info(m
);
1390 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1392 struct drm_info_node
*node
= m
->private;
1393 struct drm_device
*dev
= node
->minor
->dev
;
1394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1396 if (!HAS_FBC(dev
)) {
1397 seq_puts(m
, "FBC unsupported on this chipset\n");
1401 intel_runtime_pm_get(dev_priv
);
1403 if (intel_fbc_enabled(dev
)) {
1404 seq_puts(m
, "FBC enabled\n");
1406 seq_puts(m
, "FBC disabled: ");
1407 switch (dev_priv
->fbc
.no_fbc_reason
) {
1409 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1411 case FBC_UNSUPPORTED
:
1412 seq_puts(m
, "unsupported by this chipset");
1415 seq_puts(m
, "no outputs");
1417 case FBC_STOLEN_TOO_SMALL
:
1418 seq_puts(m
, "not enough stolen memory");
1420 case FBC_UNSUPPORTED_MODE
:
1421 seq_puts(m
, "mode not supported");
1423 case FBC_MODE_TOO_LARGE
:
1424 seq_puts(m
, "mode too large");
1427 seq_puts(m
, "FBC unsupported on plane");
1430 seq_puts(m
, "scanout buffer not tiled");
1432 case FBC_MULTIPLE_PIPES
:
1433 seq_puts(m
, "multiple pipes are enabled");
1435 case FBC_MODULE_PARAM
:
1436 seq_puts(m
, "disabled per module param (default off)");
1438 case FBC_CHIP_DEFAULT
:
1439 seq_puts(m
, "disabled per chip default");
1442 seq_puts(m
, "unknown reason");
1447 intel_runtime_pm_put(dev_priv
);
1452 static int i915_fbc_fc_get(void *data
, u64
*val
)
1454 struct drm_device
*dev
= data
;
1455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1457 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1460 drm_modeset_lock_all(dev
);
1461 *val
= dev_priv
->fbc
.false_color
;
1462 drm_modeset_unlock_all(dev
);
1467 static int i915_fbc_fc_set(void *data
, u64 val
)
1469 struct drm_device
*dev
= data
;
1470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1473 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1476 drm_modeset_lock_all(dev
);
1478 reg
= I915_READ(ILK_DPFC_CONTROL
);
1479 dev_priv
->fbc
.false_color
= val
;
1481 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1482 (reg
| FBC_CTL_FALSE_COLOR
) :
1483 (reg
& ~FBC_CTL_FALSE_COLOR
));
1485 drm_modeset_unlock_all(dev
);
1489 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1490 i915_fbc_fc_get
, i915_fbc_fc_set
,
1493 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1495 struct drm_info_node
*node
= m
->private;
1496 struct drm_device
*dev
= node
->minor
->dev
;
1497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1499 if (!HAS_IPS(dev
)) {
1500 seq_puts(m
, "not supported\n");
1504 intel_runtime_pm_get(dev_priv
);
1506 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1507 yesno(i915
.enable_ips
));
1509 if (INTEL_INFO(dev
)->gen
>= 8) {
1510 seq_puts(m
, "Currently: unknown\n");
1512 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1513 seq_puts(m
, "Currently: enabled\n");
1515 seq_puts(m
, "Currently: disabled\n");
1518 intel_runtime_pm_put(dev_priv
);
1523 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1525 struct drm_info_node
*node
= m
->private;
1526 struct drm_device
*dev
= node
->minor
->dev
;
1527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1528 bool sr_enabled
= false;
1530 intel_runtime_pm_get(dev_priv
);
1532 if (HAS_PCH_SPLIT(dev
))
1533 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1534 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1535 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1536 else if (IS_I915GM(dev
))
1537 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1538 else if (IS_PINEVIEW(dev
))
1539 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1541 intel_runtime_pm_put(dev_priv
);
1543 seq_printf(m
, "self-refresh: %s\n",
1544 sr_enabled
? "enabled" : "disabled");
1549 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1551 struct drm_info_node
*node
= m
->private;
1552 struct drm_device
*dev
= node
->minor
->dev
;
1553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1554 unsigned long temp
, chipset
, gfx
;
1560 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1564 temp
= i915_mch_val(dev_priv
);
1565 chipset
= i915_chipset_val(dev_priv
);
1566 gfx
= i915_gfx_val(dev_priv
);
1567 mutex_unlock(&dev
->struct_mutex
);
1569 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1570 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1571 seq_printf(m
, "GFX power: %ld\n", gfx
);
1572 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1577 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1579 struct drm_info_node
*node
= m
->private;
1580 struct drm_device
*dev
= node
->minor
->dev
;
1581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1583 int gpu_freq
, ia_freq
;
1585 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1586 seq_puts(m
, "unsupported on this chipset\n");
1590 intel_runtime_pm_get(dev_priv
);
1592 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1594 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1598 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1600 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1601 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1604 sandybridge_pcode_read(dev_priv
,
1605 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1607 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1608 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1609 ((ia_freq
>> 0) & 0xff) * 100,
1610 ((ia_freq
>> 8) & 0xff) * 100);
1613 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1616 intel_runtime_pm_put(dev_priv
);
1620 static int i915_opregion(struct seq_file
*m
, void *unused
)
1622 struct drm_info_node
*node
= m
->private;
1623 struct drm_device
*dev
= node
->minor
->dev
;
1624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1625 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1626 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1632 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1636 if (opregion
->header
) {
1637 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1638 seq_write(m
, data
, OPREGION_SIZE
);
1641 mutex_unlock(&dev
->struct_mutex
);
1648 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1650 struct drm_info_node
*node
= m
->private;
1651 struct drm_device
*dev
= node
->minor
->dev
;
1652 struct intel_fbdev
*ifbdev
= NULL
;
1653 struct intel_framebuffer
*fb
;
1655 #ifdef CONFIG_DRM_I915_FBDEV
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1658 ifbdev
= dev_priv
->fbdev
;
1659 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1661 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1665 fb
->base
.bits_per_pixel
,
1666 atomic_read(&fb
->base
.refcount
.refcount
));
1667 describe_obj(m
, fb
->obj
);
1671 mutex_lock(&dev
->mode_config
.fb_lock
);
1672 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1673 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1676 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1680 fb
->base
.bits_per_pixel
,
1681 atomic_read(&fb
->base
.refcount
.refcount
));
1682 describe_obj(m
, fb
->obj
);
1685 mutex_unlock(&dev
->mode_config
.fb_lock
);
1690 static void describe_ctx_ringbuf(struct seq_file
*m
,
1691 struct intel_ringbuffer
*ringbuf
)
1693 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1694 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1695 ringbuf
->last_retired_head
);
1698 static int i915_context_status(struct seq_file
*m
, void *unused
)
1700 struct drm_info_node
*node
= m
->private;
1701 struct drm_device
*dev
= node
->minor
->dev
;
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 struct intel_engine_cs
*ring
;
1704 struct intel_context
*ctx
;
1707 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1711 if (dev_priv
->ips
.pwrctx
) {
1712 seq_puts(m
, "power context ");
1713 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1717 if (dev_priv
->ips
.renderctx
) {
1718 seq_puts(m
, "render context ");
1719 describe_obj(m
, dev_priv
->ips
.renderctx
);
1723 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1724 if (!i915
.enable_execlists
&&
1725 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1728 seq_puts(m
, "HW context ");
1729 describe_ctx(m
, ctx
);
1730 for_each_ring(ring
, dev_priv
, i
) {
1731 if (ring
->default_context
== ctx
)
1732 seq_printf(m
, "(default context %s) ",
1736 if (i915
.enable_execlists
) {
1738 for_each_ring(ring
, dev_priv
, i
) {
1739 struct drm_i915_gem_object
*ctx_obj
=
1740 ctx
->engine
[i
].state
;
1741 struct intel_ringbuffer
*ringbuf
=
1742 ctx
->engine
[i
].ringbuf
;
1744 seq_printf(m
, "%s: ", ring
->name
);
1746 describe_obj(m
, ctx_obj
);
1748 describe_ctx_ringbuf(m
, ringbuf
);
1752 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1758 mutex_unlock(&dev
->struct_mutex
);
1763 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1765 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1766 struct drm_device
*dev
= node
->minor
->dev
;
1767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1768 struct intel_engine_cs
*ring
;
1769 struct intel_context
*ctx
;
1772 if (!i915
.enable_execlists
) {
1773 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1777 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1781 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1782 for_each_ring(ring
, dev_priv
, i
) {
1783 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1785 if (ring
->default_context
== ctx
)
1789 struct page
*page
= i915_gem_object_get_page(ctx_obj
, 1);
1790 uint32_t *reg_state
= kmap_atomic(page
);
1793 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1794 intel_execlists_ctx_id(ctx_obj
));
1796 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1797 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1798 i915_gem_obj_ggtt_offset(ctx_obj
) + 4096 + (j
* 4),
1799 reg_state
[j
], reg_state
[j
+ 1],
1800 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1802 kunmap_atomic(reg_state
);
1809 mutex_unlock(&dev
->struct_mutex
);
1814 static int i915_execlists(struct seq_file
*m
, void *data
)
1816 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1817 struct drm_device
*dev
= node
->minor
->dev
;
1818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1819 struct intel_engine_cs
*ring
;
1825 struct list_head
*cursor
;
1829 if (!i915
.enable_execlists
) {
1830 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1834 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1838 for_each_ring(ring
, dev_priv
, ring_id
) {
1839 struct intel_ctx_submit_request
*head_req
= NULL
;
1841 unsigned long flags
;
1843 seq_printf(m
, "%s\n", ring
->name
);
1845 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1846 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1847 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1850 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1851 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1853 read_pointer
= ring
->next_context_status_buffer
;
1854 write_pointer
= status_pointer
& 0x07;
1855 if (read_pointer
> write_pointer
)
1857 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1858 read_pointer
, write_pointer
);
1860 for (i
= 0; i
< 6; i
++) {
1861 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
1862 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
1864 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
1868 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
1869 list_for_each(cursor
, &ring
->execlist_queue
)
1871 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
1872 struct intel_ctx_submit_request
, execlist_link
);
1873 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
1875 seq_printf(m
, "\t%d requests in queue\n", count
);
1877 struct drm_i915_gem_object
*ctx_obj
;
1879 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
1880 seq_printf(m
, "\tHead request id: %u\n",
1881 intel_execlists_ctx_id(ctx_obj
));
1882 seq_printf(m
, "\tHead request tail: %u\n",
1889 mutex_unlock(&dev
->struct_mutex
);
1894 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1896 struct drm_info_node
*node
= m
->private;
1897 struct drm_device
*dev
= node
->minor
->dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 unsigned forcewake_count
= 0, fw_rendercount
= 0, fw_mediacount
= 0;
1901 spin_lock_irq(&dev_priv
->uncore
.lock
);
1902 if (IS_VALLEYVIEW(dev
)) {
1903 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1904 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1906 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1907 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1909 if (IS_VALLEYVIEW(dev
)) {
1910 seq_printf(m
, "fw_rendercount = %u\n", fw_rendercount
);
1911 seq_printf(m
, "fw_mediacount = %u\n", fw_mediacount
);
1913 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1918 static const char *swizzle_string(unsigned swizzle
)
1921 case I915_BIT_6_SWIZZLE_NONE
:
1923 case I915_BIT_6_SWIZZLE_9
:
1925 case I915_BIT_6_SWIZZLE_9_10
:
1926 return "bit9/bit10";
1927 case I915_BIT_6_SWIZZLE_9_11
:
1928 return "bit9/bit11";
1929 case I915_BIT_6_SWIZZLE_9_10_11
:
1930 return "bit9/bit10/bit11";
1931 case I915_BIT_6_SWIZZLE_9_17
:
1932 return "bit9/bit17";
1933 case I915_BIT_6_SWIZZLE_9_10_17
:
1934 return "bit9/bit10/bit17";
1935 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1942 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1944 struct drm_info_node
*node
= m
->private;
1945 struct drm_device
*dev
= node
->minor
->dev
;
1946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1949 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1952 intel_runtime_pm_get(dev_priv
);
1954 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1955 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1956 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1957 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1959 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
1960 seq_printf(m
, "DDC = 0x%08x\n",
1962 seq_printf(m
, "C0DRB3 = 0x%04x\n",
1963 I915_READ16(C0DRB3
));
1964 seq_printf(m
, "C1DRB3 = 0x%04x\n",
1965 I915_READ16(C1DRB3
));
1966 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1967 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
1968 I915_READ(MAD_DIMM_C0
));
1969 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
1970 I915_READ(MAD_DIMM_C1
));
1971 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
1972 I915_READ(MAD_DIMM_C2
));
1973 seq_printf(m
, "TILECTL = 0x%08x\n",
1974 I915_READ(TILECTL
));
1976 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
1977 I915_READ(GAMTARBMODE
));
1979 seq_printf(m
, "ARB_MODE = 0x%08x\n",
1980 I915_READ(ARB_MODE
));
1981 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
1982 I915_READ(DISP_ARB_CTL
));
1984 intel_runtime_pm_put(dev_priv
);
1985 mutex_unlock(&dev
->struct_mutex
);
1990 static int per_file_ctx(int id
, void *ptr
, void *data
)
1992 struct intel_context
*ctx
= ptr
;
1993 struct seq_file
*m
= data
;
1994 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1997 seq_printf(m
, " no ppgtt for context %d\n",
2002 if (i915_gem_context_is_default(ctx
))
2003 seq_puts(m
, " default context:\n");
2005 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2006 ppgtt
->debug_dump(ppgtt
, m
);
2011 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2014 struct intel_engine_cs
*ring
;
2015 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2021 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2022 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2023 for_each_ring(ring
, dev_priv
, unused
) {
2024 seq_printf(m
, "%s\n", ring
->name
);
2025 for (i
= 0; i
< 4; i
++) {
2026 u32 offset
= 0x270 + i
* 8;
2027 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2029 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2030 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2035 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2038 struct intel_engine_cs
*ring
;
2039 struct drm_file
*file
;
2042 if (INTEL_INFO(dev
)->gen
== 6)
2043 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2045 for_each_ring(ring
, dev_priv
, i
) {
2046 seq_printf(m
, "%s\n", ring
->name
);
2047 if (INTEL_INFO(dev
)->gen
== 7)
2048 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2049 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2050 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2051 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2053 if (dev_priv
->mm
.aliasing_ppgtt
) {
2054 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2056 seq_puts(m
, "aliasing PPGTT:\n");
2057 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
2059 ppgtt
->debug_dump(ppgtt
, m
);
2062 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2063 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2065 seq_printf(m
, "proc: %s\n",
2066 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2067 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2069 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2072 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2074 struct drm_info_node
*node
= m
->private;
2075 struct drm_device
*dev
= node
->minor
->dev
;
2076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2078 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2081 intel_runtime_pm_get(dev_priv
);
2083 if (INTEL_INFO(dev
)->gen
>= 8)
2084 gen8_ppgtt_info(m
, dev
);
2085 else if (INTEL_INFO(dev
)->gen
>= 6)
2086 gen6_ppgtt_info(m
, dev
);
2088 intel_runtime_pm_put(dev_priv
);
2089 mutex_unlock(&dev
->struct_mutex
);
2094 static int i915_llc(struct seq_file
*m
, void *data
)
2096 struct drm_info_node
*node
= m
->private;
2097 struct drm_device
*dev
= node
->minor
->dev
;
2098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2100 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2101 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2102 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2107 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2109 struct drm_info_node
*node
= m
->private;
2110 struct drm_device
*dev
= node
->minor
->dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2113 bool enabled
= false;
2115 intel_runtime_pm_get(dev_priv
);
2117 mutex_lock(&dev_priv
->psr
.lock
);
2118 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2119 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2120 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2121 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2122 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2123 dev_priv
->psr
.busy_frontbuffer_bits
);
2124 seq_printf(m
, "Re-enable work scheduled: %s\n",
2125 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2127 enabled
= HAS_PSR(dev
) &&
2128 I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2129 seq_printf(m
, "HW Enabled & Active bit: %s\n", yesno(enabled
));
2132 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2133 EDP_PSR_PERF_CNT_MASK
;
2134 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2135 mutex_unlock(&dev_priv
->psr
.lock
);
2137 intel_runtime_pm_put(dev_priv
);
2141 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2143 struct drm_info_node
*node
= m
->private;
2144 struct drm_device
*dev
= node
->minor
->dev
;
2145 struct intel_encoder
*encoder
;
2146 struct intel_connector
*connector
;
2147 struct intel_dp
*intel_dp
= NULL
;
2151 drm_modeset_lock_all(dev
);
2152 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2155 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2158 if (!connector
->base
.encoder
)
2161 encoder
= to_intel_encoder(connector
->base
.encoder
);
2162 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2165 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2167 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2171 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2172 crc
[0], crc
[1], crc
[2],
2173 crc
[3], crc
[4], crc
[5]);
2178 drm_modeset_unlock_all(dev
);
2182 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2184 struct drm_info_node
*node
= m
->private;
2185 struct drm_device
*dev
= node
->minor
->dev
;
2186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2190 if (INTEL_INFO(dev
)->gen
< 6)
2193 intel_runtime_pm_get(dev_priv
);
2195 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2196 power
= (power
& 0x1f00) >> 8;
2197 units
= 1000000 / (1 << power
); /* convert to uJ */
2198 power
= I915_READ(MCH_SECP_NRG_STTS
);
2201 intel_runtime_pm_put(dev_priv
);
2203 seq_printf(m
, "%llu", (long long unsigned)power
);
2208 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2210 struct drm_info_node
*node
= m
->private;
2211 struct drm_device
*dev
= node
->minor
->dev
;
2212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2214 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2215 seq_puts(m
, "not supported\n");
2219 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2220 seq_printf(m
, "IRQs disabled: %s\n",
2221 yesno(!intel_irqs_enabled(dev_priv
)));
2226 static const char *power_domain_str(enum intel_display_power_domain domain
)
2229 case POWER_DOMAIN_PIPE_A
:
2231 case POWER_DOMAIN_PIPE_B
:
2233 case POWER_DOMAIN_PIPE_C
:
2235 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2236 return "PIPE_A_PANEL_FITTER";
2237 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2238 return "PIPE_B_PANEL_FITTER";
2239 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2240 return "PIPE_C_PANEL_FITTER";
2241 case POWER_DOMAIN_TRANSCODER_A
:
2242 return "TRANSCODER_A";
2243 case POWER_DOMAIN_TRANSCODER_B
:
2244 return "TRANSCODER_B";
2245 case POWER_DOMAIN_TRANSCODER_C
:
2246 return "TRANSCODER_C";
2247 case POWER_DOMAIN_TRANSCODER_EDP
:
2248 return "TRANSCODER_EDP";
2249 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2250 return "PORT_DDI_A_2_LANES";
2251 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2252 return "PORT_DDI_A_4_LANES";
2253 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2254 return "PORT_DDI_B_2_LANES";
2255 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2256 return "PORT_DDI_B_4_LANES";
2257 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2258 return "PORT_DDI_C_2_LANES";
2259 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2260 return "PORT_DDI_C_4_LANES";
2261 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2262 return "PORT_DDI_D_2_LANES";
2263 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2264 return "PORT_DDI_D_4_LANES";
2265 case POWER_DOMAIN_PORT_DSI
:
2267 case POWER_DOMAIN_PORT_CRT
:
2269 case POWER_DOMAIN_PORT_OTHER
:
2270 return "PORT_OTHER";
2271 case POWER_DOMAIN_VGA
:
2273 case POWER_DOMAIN_AUDIO
:
2275 case POWER_DOMAIN_PLLS
:
2277 case POWER_DOMAIN_INIT
:
2285 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2287 struct drm_info_node
*node
= m
->private;
2288 struct drm_device
*dev
= node
->minor
->dev
;
2289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2290 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2293 mutex_lock(&power_domains
->lock
);
2295 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2296 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2297 struct i915_power_well
*power_well
;
2298 enum intel_display_power_domain power_domain
;
2300 power_well
= &power_domains
->power_wells
[i
];
2301 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2304 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2306 if (!(BIT(power_domain
) & power_well
->domains
))
2309 seq_printf(m
, " %-23s %d\n",
2310 power_domain_str(power_domain
),
2311 power_domains
->domain_use_count
[power_domain
]);
2315 mutex_unlock(&power_domains
->lock
);
2320 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2321 struct drm_display_mode
*mode
)
2325 for (i
= 0; i
< tabs
; i
++)
2328 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2329 mode
->base
.id
, mode
->name
,
2330 mode
->vrefresh
, mode
->clock
,
2331 mode
->hdisplay
, mode
->hsync_start
,
2332 mode
->hsync_end
, mode
->htotal
,
2333 mode
->vdisplay
, mode
->vsync_start
,
2334 mode
->vsync_end
, mode
->vtotal
,
2335 mode
->type
, mode
->flags
);
2338 static void intel_encoder_info(struct seq_file
*m
,
2339 struct intel_crtc
*intel_crtc
,
2340 struct intel_encoder
*intel_encoder
)
2342 struct drm_info_node
*node
= m
->private;
2343 struct drm_device
*dev
= node
->minor
->dev
;
2344 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2345 struct intel_connector
*intel_connector
;
2346 struct drm_encoder
*encoder
;
2348 encoder
= &intel_encoder
->base
;
2349 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2350 encoder
->base
.id
, encoder
->name
);
2351 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2352 struct drm_connector
*connector
= &intel_connector
->base
;
2353 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2356 drm_get_connector_status_name(connector
->status
));
2357 if (connector
->status
== connector_status_connected
) {
2358 struct drm_display_mode
*mode
= &crtc
->mode
;
2359 seq_printf(m
, ", mode:\n");
2360 intel_seq_print_mode(m
, 2, mode
);
2367 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2369 struct drm_info_node
*node
= m
->private;
2370 struct drm_device
*dev
= node
->minor
->dev
;
2371 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2372 struct intel_encoder
*intel_encoder
;
2374 if (crtc
->primary
->fb
)
2375 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2376 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2377 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2379 seq_puts(m
, "\tprimary plane disabled\n");
2380 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2381 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2384 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2386 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2388 seq_printf(m
, "\tfixed mode:\n");
2389 intel_seq_print_mode(m
, 2, mode
);
2392 static void intel_dp_info(struct seq_file
*m
,
2393 struct intel_connector
*intel_connector
)
2395 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2396 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2398 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2399 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2401 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2402 intel_panel_info(m
, &intel_connector
->panel
);
2405 static void intel_hdmi_info(struct seq_file
*m
,
2406 struct intel_connector
*intel_connector
)
2408 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2409 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2411 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2415 static void intel_lvds_info(struct seq_file
*m
,
2416 struct intel_connector
*intel_connector
)
2418 intel_panel_info(m
, &intel_connector
->panel
);
2421 static void intel_connector_info(struct seq_file
*m
,
2422 struct drm_connector
*connector
)
2424 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2425 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2426 struct drm_display_mode
*mode
;
2428 seq_printf(m
, "connector %d: type %s, status: %s\n",
2429 connector
->base
.id
, connector
->name
,
2430 drm_get_connector_status_name(connector
->status
));
2431 if (connector
->status
== connector_status_connected
) {
2432 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2433 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2434 connector
->display_info
.width_mm
,
2435 connector
->display_info
.height_mm
);
2436 seq_printf(m
, "\tsubpixel order: %s\n",
2437 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2438 seq_printf(m
, "\tCEA rev: %d\n",
2439 connector
->display_info
.cea_rev
);
2441 if (intel_encoder
) {
2442 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2443 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2444 intel_dp_info(m
, intel_connector
);
2445 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2446 intel_hdmi_info(m
, intel_connector
);
2447 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2448 intel_lvds_info(m
, intel_connector
);
2451 seq_printf(m
, "\tmodes:\n");
2452 list_for_each_entry(mode
, &connector
->modes
, head
)
2453 intel_seq_print_mode(m
, 2, mode
);
2456 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2461 if (IS_845G(dev
) || IS_I865G(dev
))
2462 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2464 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2469 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2474 pos
= I915_READ(CURPOS(pipe
));
2476 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2477 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2480 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2481 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2484 return cursor_active(dev
, pipe
);
2487 static int i915_display_info(struct seq_file
*m
, void *unused
)
2489 struct drm_info_node
*node
= m
->private;
2490 struct drm_device
*dev
= node
->minor
->dev
;
2491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2492 struct intel_crtc
*crtc
;
2493 struct drm_connector
*connector
;
2495 intel_runtime_pm_get(dev_priv
);
2496 drm_modeset_lock_all(dev
);
2497 seq_printf(m
, "CRTC info\n");
2498 seq_printf(m
, "---------\n");
2499 for_each_intel_crtc(dev
, crtc
) {
2503 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2504 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2505 yesno(crtc
->active
), crtc
->config
.pipe_src_w
, crtc
->config
.pipe_src_h
);
2507 intel_crtc_info(m
, crtc
);
2509 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2510 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2511 yesno(crtc
->cursor_base
),
2512 x
, y
, crtc
->cursor_width
, crtc
->cursor_height
,
2513 crtc
->cursor_addr
, yesno(active
));
2516 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2517 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2518 yesno(!crtc
->pch_fifo_underrun_disabled
));
2521 seq_printf(m
, "\n");
2522 seq_printf(m
, "Connector info\n");
2523 seq_printf(m
, "--------------\n");
2524 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2525 intel_connector_info(m
, connector
);
2527 drm_modeset_unlock_all(dev
);
2528 intel_runtime_pm_put(dev_priv
);
2533 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2535 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2536 struct drm_device
*dev
= node
->minor
->dev
;
2537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2538 struct intel_engine_cs
*ring
;
2539 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2542 if (!i915_semaphore_is_enabled(dev
)) {
2543 seq_puts(m
, "Semaphores are disabled\n");
2547 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2550 intel_runtime_pm_get(dev_priv
);
2552 if (IS_BROADWELL(dev
)) {
2556 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2558 seqno
= (uint64_t *)kmap_atomic(page
);
2559 for_each_ring(ring
, dev_priv
, i
) {
2562 seq_printf(m
, "%s\n", ring
->name
);
2564 seq_puts(m
, " Last signal:");
2565 for (j
= 0; j
< num_rings
; j
++) {
2566 offset
= i
* I915_NUM_RINGS
+ j
;
2567 seq_printf(m
, "0x%08llx (0x%02llx) ",
2568 seqno
[offset
], offset
* 8);
2572 seq_puts(m
, " Last wait: ");
2573 for (j
= 0; j
< num_rings
; j
++) {
2574 offset
= i
+ (j
* I915_NUM_RINGS
);
2575 seq_printf(m
, "0x%08llx (0x%02llx) ",
2576 seqno
[offset
], offset
* 8);
2581 kunmap_atomic(seqno
);
2583 seq_puts(m
, " Last signal:");
2584 for_each_ring(ring
, dev_priv
, i
)
2585 for (j
= 0; j
< num_rings
; j
++)
2586 seq_printf(m
, "0x%08x\n",
2587 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2591 seq_puts(m
, "\nSync seqno:\n");
2592 for_each_ring(ring
, dev_priv
, i
) {
2593 for (j
= 0; j
< num_rings
; j
++) {
2594 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2600 intel_runtime_pm_put(dev_priv
);
2601 mutex_unlock(&dev
->struct_mutex
);
2605 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2607 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2608 struct drm_device
*dev
= node
->minor
->dev
;
2609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2612 drm_modeset_lock_all(dev
);
2613 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2614 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2616 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2617 seq_printf(m
, " refcount: %i, active: %i, on: %s\n", pll
->refcount
,
2618 pll
->active
, yesno(pll
->on
));
2619 seq_printf(m
, " tracked hardware state:\n");
2620 seq_printf(m
, " dpll: 0x%08x\n", pll
->hw_state
.dpll
);
2621 seq_printf(m
, " dpll_md: 0x%08x\n", pll
->hw_state
.dpll_md
);
2622 seq_printf(m
, " fp0: 0x%08x\n", pll
->hw_state
.fp0
);
2623 seq_printf(m
, " fp1: 0x%08x\n", pll
->hw_state
.fp1
);
2624 seq_printf(m
, " wrpll: 0x%08x\n", pll
->hw_state
.wrpll
);
2626 drm_modeset_unlock_all(dev
);
2631 static int intel_wa_registers(struct seq_file
*m
, void *unused
)
2635 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2636 struct drm_device
*dev
= node
->minor
->dev
;
2637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2639 if (!IS_BROADWELL(dev
)) {
2640 DRM_DEBUG_DRIVER("Workaround table not available !!\n");
2644 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2648 intel_runtime_pm_get(dev_priv
);
2650 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->num_wa_regs
);
2651 for (i
= 0; i
< dev_priv
->num_wa_regs
; ++i
) {
2654 addr
= dev_priv
->intel_wa_regs
[i
].addr
;
2655 mask
= dev_priv
->intel_wa_regs
[i
].mask
;
2656 dev_priv
->intel_wa_regs
[i
].value
= I915_READ(addr
) | mask
;
2657 if (dev_priv
->intel_wa_regs
[i
].addr
)
2658 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X\n",
2659 dev_priv
->intel_wa_regs
[i
].addr
,
2660 dev_priv
->intel_wa_regs
[i
].value
,
2661 dev_priv
->intel_wa_regs
[i
].mask
);
2664 intel_runtime_pm_put(dev_priv
);
2665 mutex_unlock(&dev
->struct_mutex
);
2670 struct pipe_crc_info
{
2672 struct drm_device
*dev
;
2676 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2678 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2679 struct drm_device
*dev
= node
->minor
->dev
;
2680 struct drm_encoder
*encoder
;
2681 struct intel_encoder
*intel_encoder
;
2682 struct intel_digital_port
*intel_dig_port
;
2683 drm_modeset_lock_all(dev
);
2684 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2685 intel_encoder
= to_intel_encoder(encoder
);
2686 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2688 intel_dig_port
= enc_to_dig_port(encoder
);
2689 if (!intel_dig_port
->dp
.can_mst
)
2692 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2694 drm_modeset_unlock_all(dev
);
2698 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2700 struct pipe_crc_info
*info
= inode
->i_private
;
2701 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2702 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2704 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2707 spin_lock_irq(&pipe_crc
->lock
);
2709 if (pipe_crc
->opened
) {
2710 spin_unlock_irq(&pipe_crc
->lock
);
2711 return -EBUSY
; /* already open */
2714 pipe_crc
->opened
= true;
2715 filep
->private_data
= inode
->i_private
;
2717 spin_unlock_irq(&pipe_crc
->lock
);
2722 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2724 struct pipe_crc_info
*info
= inode
->i_private
;
2725 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2726 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2728 spin_lock_irq(&pipe_crc
->lock
);
2729 pipe_crc
->opened
= false;
2730 spin_unlock_irq(&pipe_crc
->lock
);
2735 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2736 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2737 /* account for \'0' */
2738 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2740 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2742 assert_spin_locked(&pipe_crc
->lock
);
2743 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2744 INTEL_PIPE_CRC_ENTRIES_NR
);
2748 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2751 struct pipe_crc_info
*info
= filep
->private_data
;
2752 struct drm_device
*dev
= info
->dev
;
2753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2754 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2755 char buf
[PIPE_CRC_BUFFER_LEN
];
2756 int head
, tail
, n_entries
, n
;
2760 * Don't allow user space to provide buffers not big enough to hold
2763 if (count
< PIPE_CRC_LINE_LEN
)
2766 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2769 /* nothing to read */
2770 spin_lock_irq(&pipe_crc
->lock
);
2771 while (pipe_crc_data_count(pipe_crc
) == 0) {
2774 if (filep
->f_flags
& O_NONBLOCK
) {
2775 spin_unlock_irq(&pipe_crc
->lock
);
2779 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2780 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2782 spin_unlock_irq(&pipe_crc
->lock
);
2787 /* We now have one or more entries to read */
2788 head
= pipe_crc
->head
;
2789 tail
= pipe_crc
->tail
;
2790 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
2791 count
/ PIPE_CRC_LINE_LEN
);
2792 spin_unlock_irq(&pipe_crc
->lock
);
2797 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
2800 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2801 "%8u %8x %8x %8x %8x %8x\n",
2802 entry
->frame
, entry
->crc
[0],
2803 entry
->crc
[1], entry
->crc
[2],
2804 entry
->crc
[3], entry
->crc
[4]);
2806 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
2807 buf
, PIPE_CRC_LINE_LEN
);
2808 if (ret
== PIPE_CRC_LINE_LEN
)
2811 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2812 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2814 } while (--n_entries
);
2816 spin_lock_irq(&pipe_crc
->lock
);
2817 pipe_crc
->tail
= tail
;
2818 spin_unlock_irq(&pipe_crc
->lock
);
2823 static const struct file_operations i915_pipe_crc_fops
= {
2824 .owner
= THIS_MODULE
,
2825 .open
= i915_pipe_crc_open
,
2826 .read
= i915_pipe_crc_read
,
2827 .release
= i915_pipe_crc_release
,
2830 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
2832 .name
= "i915_pipe_A_crc",
2836 .name
= "i915_pipe_B_crc",
2840 .name
= "i915_pipe_C_crc",
2845 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
2848 struct drm_device
*dev
= minor
->dev
;
2850 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
2853 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
2854 &i915_pipe_crc_fops
);
2858 return drm_add_fake_info_node(minor
, ent
, info
);
2861 static const char * const pipe_crc_sources
[] = {
2874 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
2876 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
2877 return pipe_crc_sources
[source
];
2880 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
2882 struct drm_device
*dev
= m
->private;
2883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
2887 seq_printf(m
, "%c %s\n", pipe_name(i
),
2888 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
2893 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
2895 struct drm_device
*dev
= inode
->i_private
;
2897 return single_open(file
, display_crc_ctl_show
, dev
);
2900 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2903 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2904 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2907 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2908 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
2910 case INTEL_PIPE_CRC_SOURCE_NONE
:
2920 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
2921 enum intel_pipe_crc_source
*source
)
2923 struct intel_encoder
*encoder
;
2924 struct intel_crtc
*crtc
;
2925 struct intel_digital_port
*dig_port
;
2928 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2930 drm_modeset_lock_all(dev
);
2931 for_each_intel_encoder(dev
, encoder
) {
2932 if (!encoder
->base
.crtc
)
2935 crtc
= to_intel_crtc(encoder
->base
.crtc
);
2937 if (crtc
->pipe
!= pipe
)
2940 switch (encoder
->type
) {
2941 case INTEL_OUTPUT_TVOUT
:
2942 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
2944 case INTEL_OUTPUT_DISPLAYPORT
:
2945 case INTEL_OUTPUT_EDP
:
2946 dig_port
= enc_to_dig_port(&encoder
->base
);
2947 switch (dig_port
->port
) {
2949 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
2952 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
2955 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
2958 WARN(1, "nonexisting DP port %c\n",
2959 port_name(dig_port
->port
));
2965 drm_modeset_unlock_all(dev
);
2970 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
2972 enum intel_pipe_crc_source
*source
,
2975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2976 bool need_stable_symbols
= false;
2978 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2979 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2985 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2986 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
2988 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2989 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
2990 need_stable_symbols
= true;
2992 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2993 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
2994 need_stable_symbols
= true;
2996 case INTEL_PIPE_CRC_SOURCE_NONE
:
3004 * When the pipe CRC tap point is after the transcoders we need
3005 * to tweak symbol-level features to produce a deterministic series of
3006 * symbols for a given frame. We need to reset those features only once
3007 * a frame (instead of every nth symbol):
3008 * - DC-balance: used to ensure a better clock recovery from the data
3010 * - DisplayPort scrambling: used for EMI reduction
3012 if (need_stable_symbols
) {
3013 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3015 tmp
|= DC_BALANCE_RESET_VLV
;
3017 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3019 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3021 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3027 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3029 enum intel_pipe_crc_source
*source
,
3032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3033 bool need_stable_symbols
= false;
3035 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3036 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3042 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3043 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3045 case INTEL_PIPE_CRC_SOURCE_TV
:
3046 if (!SUPPORTS_TV(dev
))
3048 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3050 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3053 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3054 need_stable_symbols
= true;
3056 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3059 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3060 need_stable_symbols
= true;
3062 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3065 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3066 need_stable_symbols
= true;
3068 case INTEL_PIPE_CRC_SOURCE_NONE
:
3076 * When the pipe CRC tap point is after the transcoders we need
3077 * to tweak symbol-level features to produce a deterministic series of
3078 * symbols for a given frame. We need to reset those features only once
3079 * a frame (instead of every nth symbol):
3080 * - DC-balance: used to ensure a better clock recovery from the data
3082 * - DisplayPort scrambling: used for EMI reduction
3084 if (need_stable_symbols
) {
3085 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3087 WARN_ON(!IS_G4X(dev
));
3089 I915_WRITE(PORT_DFT_I9XX
,
3090 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3093 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3095 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3097 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3103 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3107 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3110 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3112 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3113 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3114 tmp
&= ~DC_BALANCE_RESET_VLV
;
3115 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3119 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3123 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3126 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3128 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3129 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3131 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3132 I915_WRITE(PORT_DFT_I9XX
,
3133 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3137 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3140 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3141 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3144 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3145 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3147 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3148 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3150 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3151 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3153 case INTEL_PIPE_CRC_SOURCE_NONE
:
3163 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3166 struct intel_crtc
*crtc
=
3167 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3169 drm_modeset_lock_all(dev
);
3171 * If we use the eDP transcoder we need to make sure that we don't
3172 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3173 * relevant on hsw with pipe A when using the always-on power well
3176 if (crtc
->config
.cpu_transcoder
== TRANSCODER_EDP
&&
3177 !crtc
->config
.pch_pfit
.enabled
) {
3178 crtc
->config
.pch_pfit
.force_thru
= true;
3180 intel_display_power_get(dev_priv
,
3181 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3183 dev_priv
->display
.crtc_disable(&crtc
->base
);
3184 dev_priv
->display
.crtc_enable(&crtc
->base
);
3186 drm_modeset_unlock_all(dev
);
3189 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3192 struct intel_crtc
*crtc
=
3193 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3195 drm_modeset_lock_all(dev
);
3197 * If we use the eDP transcoder we need to make sure that we don't
3198 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3199 * relevant on hsw with pipe A when using the always-on power well
3202 if (crtc
->config
.pch_pfit
.force_thru
) {
3203 crtc
->config
.pch_pfit
.force_thru
= false;
3205 dev_priv
->display
.crtc_disable(&crtc
->base
);
3206 dev_priv
->display
.crtc_enable(&crtc
->base
);
3208 intel_display_power_put(dev_priv
,
3209 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3211 drm_modeset_unlock_all(dev
);
3214 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3216 enum intel_pipe_crc_source
*source
,
3219 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3220 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3223 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3224 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3226 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3227 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3229 case INTEL_PIPE_CRC_SOURCE_PF
:
3230 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3231 hsw_trans_edp_pipe_A_crc_wa(dev
);
3233 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3235 case INTEL_PIPE_CRC_SOURCE_NONE
:
3245 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3246 enum intel_pipe_crc_source source
)
3248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3249 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3250 u32 val
= 0; /* shut up gcc */
3253 if (pipe_crc
->source
== source
)
3256 /* forbid changing the source without going back to 'none' */
3257 if (pipe_crc
->source
&& source
)
3261 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3262 else if (INTEL_INFO(dev
)->gen
< 5)
3263 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3264 else if (IS_VALLEYVIEW(dev
))
3265 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3266 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3267 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3269 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3274 /* none -> real source transition */
3276 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3277 pipe_name(pipe
), pipe_crc_source_name(source
));
3279 pipe_crc
->entries
= kzalloc(sizeof(*pipe_crc
->entries
) *
3280 INTEL_PIPE_CRC_ENTRIES_NR
,
3282 if (!pipe_crc
->entries
)
3285 spin_lock_irq(&pipe_crc
->lock
);
3288 spin_unlock_irq(&pipe_crc
->lock
);
3291 pipe_crc
->source
= source
;
3293 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3294 POSTING_READ(PIPE_CRC_CTL(pipe
));
3296 /* real source -> none transition */
3297 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3298 struct intel_pipe_crc_entry
*entries
;
3299 struct intel_crtc
*crtc
=
3300 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3302 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3305 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3307 intel_wait_for_vblank(dev
, pipe
);
3308 drm_modeset_unlock(&crtc
->base
.mutex
);
3310 spin_lock_irq(&pipe_crc
->lock
);
3311 entries
= pipe_crc
->entries
;
3312 pipe_crc
->entries
= NULL
;
3313 spin_unlock_irq(&pipe_crc
->lock
);
3318 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3319 else if (IS_VALLEYVIEW(dev
))
3320 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3321 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3322 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3329 * Parse pipe CRC command strings:
3330 * command: wsp* object wsp+ name wsp+ source wsp*
3333 * source: (none | plane1 | plane2 | pf)
3334 * wsp: (#0x20 | #0x9 | #0xA)+
3337 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3338 * "pipe A none" -> Stop CRC
3340 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3347 /* skip leading white space */
3348 buf
= skip_spaces(buf
);
3350 break; /* end of buffer */
3352 /* find end of word */
3353 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3356 if (n_words
== max_words
) {
3357 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3359 return -EINVAL
; /* ran out of words[] before bytes */
3364 words
[n_words
++] = buf
;
3371 enum intel_pipe_crc_object
{
3372 PIPE_CRC_OBJECT_PIPE
,
3375 static const char * const pipe_crc_objects
[] = {
3380 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3384 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3385 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3393 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3395 const char name
= buf
[0];
3397 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3406 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3410 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3411 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3419 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3423 char *words
[N_WORDS
];
3425 enum intel_pipe_crc_object object
;
3426 enum intel_pipe_crc_source source
;
3428 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3429 if (n_words
!= N_WORDS
) {
3430 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3435 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3436 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3440 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3441 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3445 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3446 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3450 return pipe_crc_set_source(dev
, pipe
, source
);
3453 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3454 size_t len
, loff_t
*offp
)
3456 struct seq_file
*m
= file
->private_data
;
3457 struct drm_device
*dev
= m
->private;
3464 if (len
> PAGE_SIZE
- 1) {
3465 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3470 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3474 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3480 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3491 static const struct file_operations i915_display_crc_ctl_fops
= {
3492 .owner
= THIS_MODULE
,
3493 .open
= display_crc_ctl_open
,
3495 .llseek
= seq_lseek
,
3496 .release
= single_release
,
3497 .write
= display_crc_ctl_write
3500 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[5])
3502 struct drm_device
*dev
= m
->private;
3503 int num_levels
= ilk_wm_max_level(dev
) + 1;
3506 drm_modeset_lock_all(dev
);
3508 for (level
= 0; level
< num_levels
; level
++) {
3509 unsigned int latency
= wm
[level
];
3511 /* WM1+ latency values in 0.5us units */
3515 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3517 latency
/ 10, latency
% 10);
3520 drm_modeset_unlock_all(dev
);
3523 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3525 struct drm_device
*dev
= m
->private;
3527 wm_latency_show(m
, to_i915(dev
)->wm
.pri_latency
);
3532 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3534 struct drm_device
*dev
= m
->private;
3536 wm_latency_show(m
, to_i915(dev
)->wm
.spr_latency
);
3541 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3543 struct drm_device
*dev
= m
->private;
3545 wm_latency_show(m
, to_i915(dev
)->wm
.cur_latency
);
3550 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3552 struct drm_device
*dev
= inode
->i_private
;
3554 if (HAS_GMCH_DISPLAY(dev
))
3557 return single_open(file
, pri_wm_latency_show
, dev
);
3560 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3562 struct drm_device
*dev
= inode
->i_private
;
3564 if (HAS_GMCH_DISPLAY(dev
))
3567 return single_open(file
, spr_wm_latency_show
, dev
);
3570 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3572 struct drm_device
*dev
= inode
->i_private
;
3574 if (HAS_GMCH_DISPLAY(dev
))
3577 return single_open(file
, cur_wm_latency_show
, dev
);
3580 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3581 size_t len
, loff_t
*offp
, uint16_t wm
[5])
3583 struct seq_file
*m
= file
->private_data
;
3584 struct drm_device
*dev
= m
->private;
3585 uint16_t new[5] = { 0 };
3586 int num_levels
= ilk_wm_max_level(dev
) + 1;
3591 if (len
>= sizeof(tmp
))
3594 if (copy_from_user(tmp
, ubuf
, len
))
3599 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3600 if (ret
!= num_levels
)
3603 drm_modeset_lock_all(dev
);
3605 for (level
= 0; level
< num_levels
; level
++)
3606 wm
[level
] = new[level
];
3608 drm_modeset_unlock_all(dev
);
3614 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3615 size_t len
, loff_t
*offp
)
3617 struct seq_file
*m
= file
->private_data
;
3618 struct drm_device
*dev
= m
->private;
3620 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.pri_latency
);
3623 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3624 size_t len
, loff_t
*offp
)
3626 struct seq_file
*m
= file
->private_data
;
3627 struct drm_device
*dev
= m
->private;
3629 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.spr_latency
);
3632 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3633 size_t len
, loff_t
*offp
)
3635 struct seq_file
*m
= file
->private_data
;
3636 struct drm_device
*dev
= m
->private;
3638 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.cur_latency
);
3641 static const struct file_operations i915_pri_wm_latency_fops
= {
3642 .owner
= THIS_MODULE
,
3643 .open
= pri_wm_latency_open
,
3645 .llseek
= seq_lseek
,
3646 .release
= single_release
,
3647 .write
= pri_wm_latency_write
3650 static const struct file_operations i915_spr_wm_latency_fops
= {
3651 .owner
= THIS_MODULE
,
3652 .open
= spr_wm_latency_open
,
3654 .llseek
= seq_lseek
,
3655 .release
= single_release
,
3656 .write
= spr_wm_latency_write
3659 static const struct file_operations i915_cur_wm_latency_fops
= {
3660 .owner
= THIS_MODULE
,
3661 .open
= cur_wm_latency_open
,
3663 .llseek
= seq_lseek
,
3664 .release
= single_release
,
3665 .write
= cur_wm_latency_write
3669 i915_wedged_get(void *data
, u64
*val
)
3671 struct drm_device
*dev
= data
;
3672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3674 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3680 i915_wedged_set(void *data
, u64 val
)
3682 struct drm_device
*dev
= data
;
3683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3685 intel_runtime_pm_get(dev_priv
);
3687 i915_handle_error(dev
, val
,
3688 "Manually setting wedged to %llu", val
);
3690 intel_runtime_pm_put(dev_priv
);
3695 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3696 i915_wedged_get
, i915_wedged_set
,
3700 i915_ring_stop_get(void *data
, u64
*val
)
3702 struct drm_device
*dev
= data
;
3703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3705 *val
= dev_priv
->gpu_error
.stop_rings
;
3711 i915_ring_stop_set(void *data
, u64 val
)
3713 struct drm_device
*dev
= data
;
3714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3717 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
3719 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3723 dev_priv
->gpu_error
.stop_rings
= val
;
3724 mutex_unlock(&dev
->struct_mutex
);
3729 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
3730 i915_ring_stop_get
, i915_ring_stop_set
,
3734 i915_ring_missed_irq_get(void *data
, u64
*val
)
3736 struct drm_device
*dev
= data
;
3737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3739 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
3744 i915_ring_missed_irq_set(void *data
, u64 val
)
3746 struct drm_device
*dev
= data
;
3747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3750 /* Lock against concurrent debugfs callers */
3751 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3754 dev_priv
->gpu_error
.missed_irq_rings
= val
;
3755 mutex_unlock(&dev
->struct_mutex
);
3760 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
3761 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
3765 i915_ring_test_irq_get(void *data
, u64
*val
)
3767 struct drm_device
*dev
= data
;
3768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3770 *val
= dev_priv
->gpu_error
.test_irq_rings
;
3776 i915_ring_test_irq_set(void *data
, u64 val
)
3778 struct drm_device
*dev
= data
;
3779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
3784 /* Lock against concurrent debugfs callers */
3785 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3789 dev_priv
->gpu_error
.test_irq_rings
= val
;
3790 mutex_unlock(&dev
->struct_mutex
);
3795 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
3796 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
3799 #define DROP_UNBOUND 0x1
3800 #define DROP_BOUND 0x2
3801 #define DROP_RETIRE 0x4
3802 #define DROP_ACTIVE 0x8
3803 #define DROP_ALL (DROP_UNBOUND | \
3808 i915_drop_caches_get(void *data
, u64
*val
)
3816 i915_drop_caches_set(void *data
, u64 val
)
3818 struct drm_device
*dev
= data
;
3819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3820 struct drm_i915_gem_object
*obj
, *next
;
3821 struct i915_address_space
*vm
;
3822 struct i915_vma
*vma
, *x
;
3825 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
3827 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3828 * on ioctls on -EAGAIN. */
3829 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3833 if (val
& DROP_ACTIVE
) {
3834 ret
= i915_gpu_idle(dev
);
3839 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
3840 i915_gem_retire_requests(dev
);
3842 if (val
& DROP_BOUND
) {
3843 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3844 list_for_each_entry_safe(vma
, x
, &vm
->inactive_list
,
3849 ret
= i915_vma_unbind(vma
);
3856 if (val
& DROP_UNBOUND
) {
3857 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
3859 if (obj
->pages_pin_count
== 0) {
3860 ret
= i915_gem_object_put_pages(obj
);
3867 mutex_unlock(&dev
->struct_mutex
);
3872 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
3873 i915_drop_caches_get
, i915_drop_caches_set
,
3877 i915_max_freq_get(void *data
, u64
*val
)
3879 struct drm_device
*dev
= data
;
3880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3883 if (INTEL_INFO(dev
)->gen
< 6)
3886 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3888 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3892 if (IS_VALLEYVIEW(dev
))
3893 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
3895 *val
= dev_priv
->rps
.max_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3896 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3902 i915_max_freq_set(void *data
, u64 val
)
3904 struct drm_device
*dev
= data
;
3905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3906 u32 rp_state_cap
, hw_max
, hw_min
;
3909 if (INTEL_INFO(dev
)->gen
< 6)
3912 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3914 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
3916 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3921 * Turbo will still be enabled, but won't go above the set value.
3923 if (IS_VALLEYVIEW(dev
)) {
3924 val
= vlv_freq_opcode(dev_priv
, val
);
3926 hw_max
= dev_priv
->rps
.max_freq
;
3927 hw_min
= dev_priv
->rps
.min_freq
;
3929 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3931 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3932 hw_max
= dev_priv
->rps
.max_freq
;
3933 hw_min
= (rp_state_cap
>> 16) & 0xff;
3936 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
3937 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3941 dev_priv
->rps
.max_freq_softlimit
= val
;
3943 if (IS_VALLEYVIEW(dev
))
3944 valleyview_set_rps(dev
, val
);
3946 gen6_set_rps(dev
, val
);
3948 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3953 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
3954 i915_max_freq_get
, i915_max_freq_set
,
3958 i915_min_freq_get(void *data
, u64
*val
)
3960 struct drm_device
*dev
= data
;
3961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3964 if (INTEL_INFO(dev
)->gen
< 6)
3967 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3969 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3973 if (IS_VALLEYVIEW(dev
))
3974 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
3976 *val
= dev_priv
->rps
.min_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3977 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3983 i915_min_freq_set(void *data
, u64 val
)
3985 struct drm_device
*dev
= data
;
3986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3987 u32 rp_state_cap
, hw_max
, hw_min
;
3990 if (INTEL_INFO(dev
)->gen
< 6)
3993 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3995 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
3997 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4002 * Turbo will still be enabled, but won't go below the set value.
4004 if (IS_VALLEYVIEW(dev
)) {
4005 val
= vlv_freq_opcode(dev_priv
, val
);
4007 hw_max
= dev_priv
->rps
.max_freq
;
4008 hw_min
= dev_priv
->rps
.min_freq
;
4010 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
4012 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4013 hw_max
= dev_priv
->rps
.max_freq
;
4014 hw_min
= (rp_state_cap
>> 16) & 0xff;
4017 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4018 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4022 dev_priv
->rps
.min_freq_softlimit
= val
;
4024 if (IS_VALLEYVIEW(dev
))
4025 valleyview_set_rps(dev
, val
);
4027 gen6_set_rps(dev
, val
);
4029 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4034 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4035 i915_min_freq_get
, i915_min_freq_set
,
4039 i915_cache_sharing_get(void *data
, u64
*val
)
4041 struct drm_device
*dev
= data
;
4042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4046 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4049 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4052 intel_runtime_pm_get(dev_priv
);
4054 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4056 intel_runtime_pm_put(dev_priv
);
4057 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4059 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4065 i915_cache_sharing_set(void *data
, u64 val
)
4067 struct drm_device
*dev
= data
;
4068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4071 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4077 intel_runtime_pm_get(dev_priv
);
4078 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4080 /* Update the cache sharing policy here as well */
4081 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4082 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4083 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4084 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4086 intel_runtime_pm_put(dev_priv
);
4090 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4091 i915_cache_sharing_get
, i915_cache_sharing_set
,
4094 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4096 struct drm_device
*dev
= inode
->i_private
;
4097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4099 if (INTEL_INFO(dev
)->gen
< 6)
4102 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4107 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4109 struct drm_device
*dev
= inode
->i_private
;
4110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4112 if (INTEL_INFO(dev
)->gen
< 6)
4115 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4120 static const struct file_operations i915_forcewake_fops
= {
4121 .owner
= THIS_MODULE
,
4122 .open
= i915_forcewake_open
,
4123 .release
= i915_forcewake_release
,
4126 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4128 struct drm_device
*dev
= minor
->dev
;
4131 ent
= debugfs_create_file("i915_forcewake_user",
4134 &i915_forcewake_fops
);
4138 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4141 static int i915_debugfs_create(struct dentry
*root
,
4142 struct drm_minor
*minor
,
4144 const struct file_operations
*fops
)
4146 struct drm_device
*dev
= minor
->dev
;
4149 ent
= debugfs_create_file(name
,
4156 return drm_add_fake_info_node(minor
, ent
, fops
);
4159 static const struct drm_info_list i915_debugfs_list
[] = {
4160 {"i915_capabilities", i915_capabilities
, 0},
4161 {"i915_gem_objects", i915_gem_object_info
, 0},
4162 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4163 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4164 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4165 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4166 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4167 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4168 {"i915_gem_request", i915_gem_request_info
, 0},
4169 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4170 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4171 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4172 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4173 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4174 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4175 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4176 {"i915_frequency_info", i915_frequency_info
, 0},
4177 {"i915_drpc_info", i915_drpc_info
, 0},
4178 {"i915_emon_status", i915_emon_status
, 0},
4179 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4180 {"i915_fbc_status", i915_fbc_status
, 0},
4181 {"i915_ips_status", i915_ips_status
, 0},
4182 {"i915_sr_status", i915_sr_status
, 0},
4183 {"i915_opregion", i915_opregion
, 0},
4184 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4185 {"i915_context_status", i915_context_status
, 0},
4186 {"i915_dump_lrc", i915_dump_lrc
, 0},
4187 {"i915_execlists", i915_execlists
, 0},
4188 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
4189 {"i915_swizzle_info", i915_swizzle_info
, 0},
4190 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4191 {"i915_llc", i915_llc
, 0},
4192 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4193 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4194 {"i915_energy_uJ", i915_energy_uJ
, 0},
4195 {"i915_pc8_status", i915_pc8_status
, 0},
4196 {"i915_power_domain_info", i915_power_domain_info
, 0},
4197 {"i915_display_info", i915_display_info
, 0},
4198 {"i915_semaphore_status", i915_semaphore_status
, 0},
4199 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4200 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4201 {"intel_wa_registers", intel_wa_registers
, 0}
4203 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4205 static const struct i915_debugfs_files
{
4207 const struct file_operations
*fops
;
4208 } i915_debugfs_files
[] = {
4209 {"i915_wedged", &i915_wedged_fops
},
4210 {"i915_max_freq", &i915_max_freq_fops
},
4211 {"i915_min_freq", &i915_min_freq_fops
},
4212 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4213 {"i915_ring_stop", &i915_ring_stop_fops
},
4214 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4215 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4216 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4217 {"i915_error_state", &i915_error_state_fops
},
4218 {"i915_next_seqno", &i915_next_seqno_fops
},
4219 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4220 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4221 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4222 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4223 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4226 void intel_display_crc_init(struct drm_device
*dev
)
4228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4231 for_each_pipe(dev_priv
, pipe
) {
4232 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4234 pipe_crc
->opened
= false;
4235 spin_lock_init(&pipe_crc
->lock
);
4236 init_waitqueue_head(&pipe_crc
->wq
);
4240 int i915_debugfs_init(struct drm_minor
*minor
)
4244 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4248 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4249 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4254 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4255 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4256 i915_debugfs_files
[i
].name
,
4257 i915_debugfs_files
[i
].fops
);
4262 return drm_debugfs_create_files(i915_debugfs_list
,
4263 I915_DEBUGFS_ENTRIES
,
4264 minor
->debugfs_root
, minor
);
4267 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4271 drm_debugfs_remove_files(i915_debugfs_list
,
4272 I915_DEBUGFS_ENTRIES
, minor
);
4274 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4277 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4278 struct drm_info_list
*info_list
=
4279 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4281 drm_debugfs_remove_files(info_list
, 1, minor
);
4284 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4285 struct drm_info_list
*info_list
=
4286 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4288 drm_debugfs_remove_files(info_list
, 1, minor
);