1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver
;
57 static unsigned int i915_load_fail_count
;
59 bool __i915_inject_load_failure(const char *func
, int line
)
61 if (i915_load_fail_count
>= i915
.inject_load_failure
)
64 if (++i915_load_fail_count
== i915
.inject_load_failure
) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915
.inject_load_failure
, func
, line
);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
81 static bool shown_bug_once
;
82 struct device
*kdev
= dev_priv
->drm
.dev
;
83 bool is_error
= level
[1] <= KERN_ERR
[1];
84 bool is_debug
= level
[1] == KERN_DEBUG
[1];
88 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
96 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
97 __builtin_return_address(0), &vaf
);
99 if (is_error
&& !shown_bug_once
) {
100 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
101 shown_bug_once
= true;
107 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
109 return i915
.inject_load_failure
&&
110 i915_load_fail_count
== i915
.inject_load_failure
;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch
intel_virt_detect_pch(struct drm_i915_private
*dev_priv
)
121 enum intel_pch ret
= PCH_NOP
;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv
)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
)) {
135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
138 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
139 dev_priv
->pch_id
= INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
141 dev_priv
->pch_id
= INTEL_PCH_LPT_DEVICE_ID_TYPE
;
142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
143 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146 } else if (IS_COFFEELAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
154 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
156 struct pci_dev
*pch
= NULL
;
158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
161 if (INTEL_INFO(dev_priv
)->num_pipes
== 0) {
162 dev_priv
->pch_type
= PCH_NOP
;
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
177 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
178 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
179 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
181 dev_priv
->pch_id
= id
;
183 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
184 dev_priv
->pch_type
= PCH_IBX
;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
186 WARN_ON(!IS_GEN5(dev_priv
));
187 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
188 dev_priv
->pch_type
= PCH_CPT
;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
190 WARN_ON(!IS_GEN6(dev_priv
) &&
191 !IS_IVYBRIDGE(dev_priv
));
192 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
193 /* PantherPoint is CPT compatible */
194 dev_priv
->pch_type
= PCH_CPT
;
195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
196 WARN_ON(!IS_GEN6(dev_priv
) &&
197 !IS_IVYBRIDGE(dev_priv
));
198 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
199 dev_priv
->pch_type
= PCH_LPT
;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201 WARN_ON(!IS_HASWELL(dev_priv
) &&
202 !IS_BROADWELL(dev_priv
));
203 WARN_ON(IS_HSW_ULT(dev_priv
) ||
204 IS_BDW_ULT(dev_priv
));
205 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
206 dev_priv
->pch_type
= PCH_LPT
;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
208 WARN_ON(!IS_HASWELL(dev_priv
) &&
209 !IS_BROADWELL(dev_priv
));
210 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
211 !IS_BDW_ULT(dev_priv
));
212 } else if (id
== INTEL_PCH_WPT_DEVICE_ID_TYPE
) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv
->pch_type
= PCH_LPT
;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv
) &&
217 !IS_BROADWELL(dev_priv
));
218 WARN_ON(IS_HSW_ULT(dev_priv
) ||
219 IS_BDW_ULT(dev_priv
));
220 } else if (id
== INTEL_PCH_WPT_LP_DEVICE_ID_TYPE
) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv
->pch_type
= PCH_LPT
;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv
) &&
225 !IS_BROADWELL(dev_priv
));
226 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
227 !IS_BDW_ULT(dev_priv
));
228 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
229 dev_priv
->pch_type
= PCH_SPT
;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
231 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
232 !IS_KABYLAKE(dev_priv
));
233 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
234 dev_priv
->pch_type
= PCH_SPT
;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
236 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
237 !IS_KABYLAKE(dev_priv
));
238 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
239 dev_priv
->pch_type
= PCH_KBP
;
240 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
241 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
242 !IS_KABYLAKE(dev_priv
));
243 } else if (id
== INTEL_PCH_CNP_DEVICE_ID_TYPE
) {
244 dev_priv
->pch_type
= PCH_CNP
;
245 DRM_DEBUG_KMS("Found CannonPoint PCH\n");
246 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
247 !IS_COFFEELAKE(dev_priv
));
248 } else if (id
== INTEL_PCH_CNP_LP_DEVICE_ID_TYPE
) {
249 dev_priv
->pch_type
= PCH_CNP
;
250 DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
251 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
252 !IS_COFFEELAKE(dev_priv
));
253 } else if (id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
||
254 id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
||
255 (id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
&&
256 pch
->subsystem_vendor
==
257 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
258 pch
->subsystem_device
==
259 PCI_SUBDEVICE_ID_QEMU
)) {
261 intel_virt_detect_pch(dev_priv
);
269 DRM_DEBUG_KMS("No PCH found.\n");
274 static int i915_getparam(struct drm_device
*dev
, void *data
,
275 struct drm_file
*file_priv
)
277 struct drm_i915_private
*dev_priv
= to_i915(dev
);
278 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
279 drm_i915_getparam_t
*param
= data
;
282 switch (param
->param
) {
283 case I915_PARAM_IRQ_ACTIVE
:
284 case I915_PARAM_ALLOW_BATCHBUFFER
:
285 case I915_PARAM_LAST_DISPATCH
:
286 case I915_PARAM_HAS_EXEC_CONSTANTS
:
287 /* Reject all old ums/dri params. */
289 case I915_PARAM_CHIPSET_ID
:
290 value
= pdev
->device
;
292 case I915_PARAM_REVISION
:
293 value
= pdev
->revision
;
295 case I915_PARAM_NUM_FENCES_AVAIL
:
296 value
= dev_priv
->num_fence_regs
;
298 case I915_PARAM_HAS_OVERLAY
:
299 value
= dev_priv
->overlay
? 1 : 0;
301 case I915_PARAM_HAS_BSD
:
302 value
= !!dev_priv
->engine
[VCS
];
304 case I915_PARAM_HAS_BLT
:
305 value
= !!dev_priv
->engine
[BCS
];
307 case I915_PARAM_HAS_VEBOX
:
308 value
= !!dev_priv
->engine
[VECS
];
310 case I915_PARAM_HAS_BSD2
:
311 value
= !!dev_priv
->engine
[VCS2
];
313 case I915_PARAM_HAS_LLC
:
314 value
= HAS_LLC(dev_priv
);
316 case I915_PARAM_HAS_WT
:
317 value
= HAS_WT(dev_priv
);
319 case I915_PARAM_HAS_ALIASING_PPGTT
:
320 value
= USES_PPGTT(dev_priv
);
322 case I915_PARAM_HAS_SEMAPHORES
:
323 value
= i915
.semaphores
;
325 case I915_PARAM_HAS_SECURE_BATCHES
:
326 value
= capable(CAP_SYS_ADMIN
);
328 case I915_PARAM_CMD_PARSER_VERSION
:
329 value
= i915_cmd_parser_get_version(dev_priv
);
331 case I915_PARAM_SUBSLICE_TOTAL
:
332 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
336 case I915_PARAM_EU_TOTAL
:
337 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
341 case I915_PARAM_HAS_GPU_RESET
:
342 value
= i915
.enable_hangcheck
&& intel_has_gpu_reset(dev_priv
);
343 if (value
&& intel_has_reset_engine(dev_priv
))
346 case I915_PARAM_HAS_RESOURCE_STREAMER
:
347 value
= HAS_RESOURCE_STREAMER(dev_priv
);
349 case I915_PARAM_HAS_POOLED_EU
:
350 value
= HAS_POOLED_EU(dev_priv
);
352 case I915_PARAM_MIN_EU_IN_POOL
:
353 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
355 case I915_PARAM_HUC_STATUS
:
356 intel_runtime_pm_get(dev_priv
);
357 value
= I915_READ(HUC_STATUS2
) & HUC_FW_VERIFIED
;
358 intel_runtime_pm_put(dev_priv
);
360 case I915_PARAM_MMAP_GTT_VERSION
:
361 /* Though we've started our numbering from 1, and so class all
362 * earlier versions as 0, in effect their value is undefined as
363 * the ioctl will report EINVAL for the unknown param!
365 value
= i915_gem_mmap_gtt_version();
367 case I915_PARAM_HAS_SCHEDULER
:
368 value
= dev_priv
->engine
[RCS
] &&
369 dev_priv
->engine
[RCS
]->schedule
;
371 case I915_PARAM_MMAP_VERSION
:
372 /* Remember to bump this if the version changes! */
373 case I915_PARAM_HAS_GEM
:
374 case I915_PARAM_HAS_PAGEFLIPPING
:
375 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
376 case I915_PARAM_HAS_RELAXED_FENCING
:
377 case I915_PARAM_HAS_COHERENT_RINGS
:
378 case I915_PARAM_HAS_RELAXED_DELTA
:
379 case I915_PARAM_HAS_GEN7_SOL_RESET
:
380 case I915_PARAM_HAS_WAIT_TIMEOUT
:
381 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
382 case I915_PARAM_HAS_PINNED_BATCHES
:
383 case I915_PARAM_HAS_EXEC_NO_RELOC
:
384 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
385 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
386 case I915_PARAM_HAS_EXEC_SOFTPIN
:
387 case I915_PARAM_HAS_EXEC_ASYNC
:
388 case I915_PARAM_HAS_EXEC_FENCE
:
389 case I915_PARAM_HAS_EXEC_CAPTURE
:
390 case I915_PARAM_HAS_EXEC_BATCH_FIRST
:
391 /* For the time being all of these are always true;
392 * if some supported hardware does not have one of these
393 * features this value needs to be provided from
394 * INTEL_INFO(), a feature macro, or similar.
398 case I915_PARAM_SLICE_MASK
:
399 value
= INTEL_INFO(dev_priv
)->sseu
.slice_mask
;
403 case I915_PARAM_SUBSLICE_MASK
:
404 value
= INTEL_INFO(dev_priv
)->sseu
.subslice_mask
;
409 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
413 if (put_user(value
, param
->value
))
419 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
421 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
422 if (!dev_priv
->bridge_dev
) {
423 DRM_ERROR("bridge device not found\n");
429 /* Allocate space for the MCH regs if needed, return nonzero on error */
431 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
433 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
434 u32 temp_lo
, temp_hi
= 0;
438 if (INTEL_GEN(dev_priv
) >= 4)
439 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
440 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
441 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
443 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
446 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
450 /* Get some space for it */
451 dev_priv
->mch_res
.name
= "i915 MCHBAR";
452 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
453 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
455 MCHBAR_SIZE
, MCHBAR_SIZE
,
457 0, pcibios_align_resource
,
458 dev_priv
->bridge_dev
);
460 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
461 dev_priv
->mch_res
.start
= 0;
465 if (INTEL_GEN(dev_priv
) >= 4)
466 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
467 upper_32_bits(dev_priv
->mch_res
.start
));
469 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
470 lower_32_bits(dev_priv
->mch_res
.start
));
474 /* Setup MCHBAR if possible, return true if we should disable it again */
476 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
478 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
482 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
485 dev_priv
->mchbar_need_disable
= false;
487 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
488 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
489 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
491 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
495 /* If it's already enabled, don't have to do anything */
499 if (intel_alloc_mchbar_resource(dev_priv
))
502 dev_priv
->mchbar_need_disable
= true;
504 /* Space is allocated or reserved, so enable it. */
505 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
506 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
507 temp
| DEVEN_MCHBAR_EN
);
509 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
510 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
515 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
517 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
519 if (dev_priv
->mchbar_need_disable
) {
520 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
523 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
525 deven_val
&= ~DEVEN_MCHBAR_EN
;
526 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
531 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
534 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
539 if (dev_priv
->mch_res
.start
)
540 release_resource(&dev_priv
->mch_res
);
543 /* true = enable decode, false = disable decoder */
544 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
546 struct drm_i915_private
*dev_priv
= cookie
;
548 intel_modeset_vga_set_state(dev_priv
, state
);
550 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
551 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
553 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
556 static int i915_resume_switcheroo(struct drm_device
*dev
);
557 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
559 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
561 struct drm_device
*dev
= pci_get_drvdata(pdev
);
562 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
564 if (state
== VGA_SWITCHEROO_ON
) {
565 pr_info("switched on\n");
566 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
567 /* i915 resume handler doesn't set to D0 */
568 pci_set_power_state(pdev
, PCI_D0
);
569 i915_resume_switcheroo(dev
);
570 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
572 pr_info("switched off\n");
573 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
574 i915_suspend_switcheroo(dev
, pmm
);
575 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
579 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
581 struct drm_device
*dev
= pci_get_drvdata(pdev
);
584 * FIXME: open_count is protected by drm_global_mutex but that would lead to
585 * locking inversion with the driver load path. And the access here is
586 * completely racy anyway. So don't bother with locking for now.
588 return dev
->open_count
== 0;
591 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
592 .set_gpu_state
= i915_switcheroo_set_state
,
594 .can_switch
= i915_switcheroo_can_switch
,
597 static void i915_gem_fini(struct drm_i915_private
*dev_priv
)
599 flush_workqueue(dev_priv
->wq
);
601 mutex_lock(&dev_priv
->drm
.struct_mutex
);
602 intel_uc_fini_hw(dev_priv
);
603 i915_gem_cleanup_engines(dev_priv
);
604 i915_gem_contexts_fini(dev_priv
);
605 i915_gem_cleanup_userptr(dev_priv
);
606 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
608 i915_gem_drain_freed_objects(dev_priv
);
610 WARN_ON(!list_empty(&dev_priv
->contexts
.list
));
613 static int i915_load_modeset_init(struct drm_device
*dev
)
615 struct drm_i915_private
*dev_priv
= to_i915(dev
);
616 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
619 if (i915_inject_load_failure())
622 intel_bios_init(dev_priv
);
624 /* If we have > 1 VGA cards, then we need to arbitrate access
625 * to the common VGA resources.
627 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
628 * then we do not take part in VGA arbitration and the
629 * vga_client_register() fails with -ENODEV.
631 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
632 if (ret
&& ret
!= -ENODEV
)
635 intel_register_dsm_handler();
637 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
639 goto cleanup_vga_client
;
641 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
642 intel_update_rawclk(dev_priv
);
644 intel_power_domains_init_hw(dev_priv
, false);
646 intel_csr_ucode_init(dev_priv
);
648 ret
= intel_irq_install(dev_priv
);
652 intel_setup_gmbus(dev_priv
);
654 /* Important: The output setup functions called by modeset_init need
655 * working irqs for e.g. gmbus and dp aux transfers. */
656 ret
= intel_modeset_init(dev
);
660 intel_uc_init_fw(dev_priv
);
662 ret
= i915_gem_init(dev_priv
);
666 intel_modeset_gem_init(dev
);
668 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
671 ret
= intel_fbdev_init(dev
);
675 /* Only enable hotplug handling once the fbdev is fully set up. */
676 intel_hpd_init(dev_priv
);
678 drm_kms_helper_poll_init(dev
);
683 if (i915_gem_suspend(dev_priv
))
684 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
685 i915_gem_fini(dev_priv
);
687 intel_uc_fini_fw(dev_priv
);
689 drm_irq_uninstall(dev
);
690 intel_teardown_gmbus(dev_priv
);
692 intel_csr_ucode_fini(dev_priv
);
693 intel_power_domains_fini(dev_priv
);
694 vga_switcheroo_unregister_client(pdev
);
696 vga_client_register(pdev
, NULL
, NULL
, NULL
);
701 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
703 struct apertures_struct
*ap
;
704 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
705 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
709 ap
= alloc_apertures(1);
713 ap
->ranges
[0].base
= ggtt
->mappable_base
;
714 ap
->ranges
[0].size
= ggtt
->mappable_end
;
717 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
719 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
726 #if !defined(CONFIG_VGA_CONSOLE)
727 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
731 #elif !defined(CONFIG_DUMMY_CONSOLE)
732 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
737 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
741 DRM_INFO("Replacing VGA console driver\n");
744 if (con_is_bound(&vga_con
))
745 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
747 ret
= do_unregister_con_driver(&vga_con
);
749 /* Ignore "already unregistered". */
759 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
762 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
763 * CHV x1 PHY (DP/HDMI D)
764 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
766 if (IS_CHERRYVIEW(dev_priv
)) {
767 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
768 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
769 } else if (IS_VALLEYVIEW(dev_priv
)) {
770 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
774 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
777 * The i915 workqueue is primarily used for batched retirement of
778 * requests (and thus managing bo) once the task has been completed
779 * by the GPU. i915_gem_retire_requests() is called directly when we
780 * need high-priority retirement, such as waiting for an explicit
783 * It is also used for periodic low-priority events, such as
784 * idle-timers and recording error state.
786 * All tasks on the workqueue are expected to acquire the dev mutex
787 * so there is no point in running more than one instance of the
788 * workqueue at any time. Use an ordered one.
790 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
791 if (dev_priv
->wq
== NULL
)
794 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
795 if (dev_priv
->hotplug
.dp_wq
== NULL
)
801 destroy_workqueue(dev_priv
->wq
);
803 DRM_ERROR("Failed to allocate workqueues.\n");
808 static void i915_engines_cleanup(struct drm_i915_private
*i915
)
810 struct intel_engine_cs
*engine
;
811 enum intel_engine_id id
;
813 for_each_engine(engine
, i915
, id
)
817 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
819 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
820 destroy_workqueue(dev_priv
->wq
);
824 * We don't keep the workarounds for pre-production hardware, so we expect our
825 * driver to fail on these machines in one way or another. A little warning on
826 * dmesg may help both the user and the bug triagers.
828 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
832 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
833 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
834 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
837 DRM_ERROR("This is a pre-production stepping. "
838 "It may not be fully functional.\n");
839 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
844 * i915_driver_init_early - setup state not requiring device access
845 * @dev_priv: device private
847 * Initialize everything that is a "SW-only" state, that is state not
848 * requiring accessing the device or exposing the driver via kernel internal
849 * or userspace interfaces. Example steps belonging here: lock initialization,
850 * system memory allocation, setting up device specific attributes and
851 * function hooks not requiring accessing the device.
853 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
854 const struct pci_device_id
*ent
)
856 const struct intel_device_info
*match_info
=
857 (struct intel_device_info
*)ent
->driver_data
;
858 struct intel_device_info
*device_info
;
861 if (i915_inject_load_failure())
864 /* Setup the write-once "constant" device info */
865 device_info
= mkwrite_device_info(dev_priv
);
866 memcpy(device_info
, match_info
, sizeof(*device_info
));
867 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
869 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
870 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
872 spin_lock_init(&dev_priv
->irq_lock
);
873 spin_lock_init(&dev_priv
->gpu_error
.lock
);
874 mutex_init(&dev_priv
->backlight_lock
);
875 spin_lock_init(&dev_priv
->uncore
.lock
);
877 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
878 spin_lock_init(&dev_priv
->mmio_flip_lock
);
879 mutex_init(&dev_priv
->sb_lock
);
880 mutex_init(&dev_priv
->modeset_restore_lock
);
881 mutex_init(&dev_priv
->av_mutex
);
882 mutex_init(&dev_priv
->wm
.wm_mutex
);
883 mutex_init(&dev_priv
->pps_mutex
);
885 intel_uc_init_early(dev_priv
);
886 i915_memcpy_init_early(dev_priv
);
888 ret
= i915_workqueues_init(dev_priv
);
892 /* This must be called before any calls to HAS_PCH_* */
893 intel_detect_pch(dev_priv
);
895 intel_pm_setup(dev_priv
);
896 intel_init_dpio(dev_priv
);
897 intel_power_domains_init(dev_priv
);
898 intel_irq_init(dev_priv
);
899 intel_hangcheck_init(dev_priv
);
900 intel_init_display_hooks(dev_priv
);
901 intel_init_clock_gating_hooks(dev_priv
);
902 intel_init_audio_hooks(dev_priv
);
903 ret
= i915_gem_load_init(dev_priv
);
907 intel_display_crc_init(dev_priv
);
909 intel_device_info_dump(dev_priv
);
911 intel_detect_preproduction_hw(dev_priv
);
913 i915_perf_init(dev_priv
);
918 intel_irq_fini(dev_priv
);
919 i915_workqueues_cleanup(dev_priv
);
921 i915_engines_cleanup(dev_priv
);
926 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
927 * @dev_priv: device private
929 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
931 i915_perf_fini(dev_priv
);
932 i915_gem_load_cleanup(dev_priv
);
933 intel_irq_fini(dev_priv
);
934 i915_workqueues_cleanup(dev_priv
);
935 i915_engines_cleanup(dev_priv
);
938 static int i915_mmio_setup(struct drm_i915_private
*dev_priv
)
940 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
944 mmio_bar
= IS_GEN2(dev_priv
) ? 1 : 0;
946 * Before gen4, the registers and the GTT are behind different BARs.
947 * However, from gen4 onwards, the registers and the GTT are shared
948 * in the same BAR, so we want to restrict this ioremap from
949 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
950 * the register BAR remains the same size for all the earlier
951 * generations up to Ironlake.
953 if (INTEL_GEN(dev_priv
) < 5)
954 mmio_size
= 512 * 1024;
956 mmio_size
= 2 * 1024 * 1024;
957 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
958 if (dev_priv
->regs
== NULL
) {
959 DRM_ERROR("failed to map registers\n");
964 /* Try to make sure MCHBAR is enabled before poking at it */
965 intel_setup_mchbar(dev_priv
);
970 static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv
)
972 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
974 intel_teardown_mchbar(dev_priv
);
975 pci_iounmap(pdev
, dev_priv
->regs
);
979 * i915_driver_init_mmio - setup device MMIO
980 * @dev_priv: device private
982 * Setup minimal device state necessary for MMIO accesses later in the
983 * initialization sequence. The setup here should avoid any other device-wide
984 * side effects or exposing the driver via kernel internal or user space
987 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
991 if (i915_inject_load_failure())
994 if (i915_get_bridge_dev(dev_priv
))
997 ret
= i915_mmio_setup(dev_priv
);
1001 intel_uncore_init(dev_priv
);
1003 ret
= intel_engines_init_mmio(dev_priv
);
1007 i915_gem_init_mmio(dev_priv
);
1012 intel_uncore_fini(dev_priv
);
1014 pci_dev_put(dev_priv
->bridge_dev
);
1020 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1021 * @dev_priv: device private
1023 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
1025 intel_uncore_fini(dev_priv
);
1026 i915_mmio_cleanup(dev_priv
);
1027 pci_dev_put(dev_priv
->bridge_dev
);
1030 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
1032 i915
.enable_execlists
=
1033 intel_sanitize_enable_execlists(dev_priv
,
1034 i915
.enable_execlists
);
1037 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1038 * user's requested state against the hardware/driver capabilities. We
1039 * do this now so that we can print out any log messages once rather
1040 * than every time we check intel_enable_ppgtt().
1043 intel_sanitize_enable_ppgtt(dev_priv
, i915
.enable_ppgtt
);
1044 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
1046 i915
.semaphores
= intel_sanitize_semaphores(dev_priv
, i915
.semaphores
);
1047 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915
.semaphores
));
1049 intel_uc_sanitize_options(dev_priv
);
1051 intel_gvt_sanitize_options(dev_priv
);
1055 * i915_driver_init_hw - setup state requiring device access
1056 * @dev_priv: device private
1058 * Setup state that requires accessing the device, but doesn't require
1059 * exposing the driver via kernel internal or userspace interfaces.
1061 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1063 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1066 if (i915_inject_load_failure())
1069 intel_device_info_runtime_init(dev_priv
);
1071 intel_sanitize_options(dev_priv
);
1073 ret
= i915_ggtt_probe_hw(dev_priv
);
1077 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1078 * otherwise the vga fbdev driver falls over. */
1079 ret
= i915_kick_out_firmware_fb(dev_priv
);
1081 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1085 ret
= i915_kick_out_vgacon(dev_priv
);
1087 DRM_ERROR("failed to remove conflicting VGA console\n");
1091 ret
= i915_ggtt_init_hw(dev_priv
);
1095 ret
= i915_ggtt_enable_hw(dev_priv
);
1097 DRM_ERROR("failed to enable GGTT\n");
1101 pci_set_master(pdev
);
1103 /* overlay on gen2 is broken and can't address above 1G */
1104 if (IS_GEN2(dev_priv
)) {
1105 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1107 DRM_ERROR("failed to set DMA mask\n");
1113 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1114 * using 32bit addressing, overwriting memory if HWS is located
1117 * The documentation also mentions an issue with undefined
1118 * behaviour if any general state is accessed within a page above 4GB,
1119 * which also needs to be handled carefully.
1121 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1122 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1125 DRM_ERROR("failed to set DMA mask\n");
1131 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1132 PM_QOS_DEFAULT_VALUE
);
1134 intel_uncore_sanitize(dev_priv
);
1136 intel_opregion_setup(dev_priv
);
1138 i915_gem_load_init_fences(dev_priv
);
1140 /* On the 945G/GM, the chipset reports the MSI capability on the
1141 * integrated graphics even though the support isn't actually there
1142 * according to the published specs. It doesn't appear to function
1143 * correctly in testing on 945G.
1144 * This may be a side effect of MSI having been made available for PEG
1145 * and the registers being closely associated.
1147 * According to chipset errata, on the 965GM, MSI interrupts may
1148 * be lost or delayed, and was defeatured. MSI interrupts seem to
1149 * get lost on g4x as well, and interrupt delivery seems to stay
1150 * properly dead afterwards. So we'll just disable them for all
1151 * pre-gen5 chipsets.
1153 if (INTEL_GEN(dev_priv
) >= 5) {
1154 if (pci_enable_msi(pdev
) < 0)
1155 DRM_DEBUG_DRIVER("can't enable MSI");
1158 ret
= intel_gvt_init(dev_priv
);
1165 i915_ggtt_cleanup_hw(dev_priv
);
1171 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1172 * @dev_priv: device private
1174 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1176 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1178 if (pdev
->msi_enabled
)
1179 pci_disable_msi(pdev
);
1181 pm_qos_remove_request(&dev_priv
->pm_qos
);
1182 i915_ggtt_cleanup_hw(dev_priv
);
1186 * i915_driver_register - register the driver with the rest of the system
1187 * @dev_priv: device private
1189 * Perform any steps necessary to make the driver available via kernel
1190 * internal or userspace interfaces.
1192 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1194 struct drm_device
*dev
= &dev_priv
->drm
;
1196 i915_gem_shrinker_init(dev_priv
);
1199 * Notify a valid surface after modesetting,
1200 * when running inside a VM.
1202 if (intel_vgpu_active(dev_priv
))
1203 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1205 /* Reveal our presence to userspace */
1206 if (drm_dev_register(dev
, 0) == 0) {
1207 i915_debugfs_register(dev_priv
);
1208 i915_guc_log_register(dev_priv
);
1209 i915_setup_sysfs(dev_priv
);
1211 /* Depends on sysfs having been initialized */
1212 i915_perf_register(dev_priv
);
1214 DRM_ERROR("Failed to register driver for userspace access!\n");
1216 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1217 /* Must be done after probing outputs */
1218 intel_opregion_register(dev_priv
);
1219 acpi_video_register();
1222 if (IS_GEN5(dev_priv
))
1223 intel_gpu_ips_init(dev_priv
);
1225 intel_audio_init(dev_priv
);
1228 * Some ports require correctly set-up hpd registers for detection to
1229 * work properly (leading to ghost connected connector status), e.g. VGA
1230 * on gm45. Hence we can only set up the initial fbdev config after hpd
1231 * irqs are fully enabled. We do it last so that the async config
1232 * cannot run before the connectors are registered.
1234 intel_fbdev_initial_config_async(dev
);
1238 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1239 * @dev_priv: device private
1241 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1243 intel_audio_deinit(dev_priv
);
1245 intel_gpu_ips_teardown();
1246 acpi_video_unregister();
1247 intel_opregion_unregister(dev_priv
);
1249 i915_perf_unregister(dev_priv
);
1251 i915_teardown_sysfs(dev_priv
);
1252 i915_guc_log_unregister(dev_priv
);
1253 drm_dev_unregister(&dev_priv
->drm
);
1255 i915_gem_shrinker_cleanup(dev_priv
);
1259 * i915_driver_load - setup chip and create an initial config
1261 * @ent: matching PCI ID entry
1263 * The driver load routine has to do several things:
1264 * - drive output discovery via intel_modeset_init()
1265 * - initialize the memory manager
1266 * - allocate initial config memory
1267 * - setup the DRM framebuffer with the allocated memory
1269 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1271 const struct intel_device_info
*match_info
=
1272 (struct intel_device_info
*)ent
->driver_data
;
1273 struct drm_i915_private
*dev_priv
;
1276 /* Enable nuclear pageflip on ILK+ */
1277 if (!i915
.nuclear_pageflip
&& match_info
->gen
< 5)
1278 driver
.driver_features
&= ~DRIVER_ATOMIC
;
1281 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1283 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1285 DRM_DEV_ERROR(&pdev
->dev
, "allocation failed\n");
1289 dev_priv
->drm
.pdev
= pdev
;
1290 dev_priv
->drm
.dev_private
= dev_priv
;
1292 ret
= pci_enable_device(pdev
);
1296 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1298 * Disable the system suspend direct complete optimization, which can
1299 * leave the device suspended skipping the driver's suspend handlers
1300 * if the device was already runtime suspended. This is needed due to
1301 * the difference in our runtime and system suspend sequence and
1302 * becaue the HDA driver may require us to enable the audio power
1303 * domain during system suspend.
1305 pdev
->dev_flags
|= PCI_DEV_FLAGS_NEEDS_RESUME
;
1307 ret
= i915_driver_init_early(dev_priv
, ent
);
1309 goto out_pci_disable
;
1311 intel_runtime_pm_get(dev_priv
);
1313 ret
= i915_driver_init_mmio(dev_priv
);
1315 goto out_runtime_pm_put
;
1317 ret
= i915_driver_init_hw(dev_priv
);
1319 goto out_cleanup_mmio
;
1322 * TODO: move the vblank init and parts of modeset init steps into one
1323 * of the i915_driver_init_/i915_driver_register functions according
1324 * to the role/effect of the given init step.
1326 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1327 ret
= drm_vblank_init(&dev_priv
->drm
,
1328 INTEL_INFO(dev_priv
)->num_pipes
);
1330 goto out_cleanup_hw
;
1333 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1335 goto out_cleanup_vblank
;
1337 i915_driver_register(dev_priv
);
1339 intel_runtime_pm_enable(dev_priv
);
1341 dev_priv
->ipc_enabled
= false;
1343 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1344 DRM_INFO("DRM_I915_DEBUG enabled\n");
1345 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1346 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1348 intel_runtime_pm_put(dev_priv
);
1353 drm_vblank_cleanup(&dev_priv
->drm
);
1355 i915_driver_cleanup_hw(dev_priv
);
1357 i915_driver_cleanup_mmio(dev_priv
);
1359 intel_runtime_pm_put(dev_priv
);
1360 i915_driver_cleanup_early(dev_priv
);
1362 pci_disable_device(pdev
);
1364 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1365 drm_dev_fini(&dev_priv
->drm
);
1371 void i915_driver_unload(struct drm_device
*dev
)
1373 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1374 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1376 intel_fbdev_fini(dev
);
1378 if (i915_gem_suspend(dev_priv
))
1379 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1381 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1383 drm_atomic_helper_shutdown(dev
);
1385 intel_gvt_cleanup(dev_priv
);
1387 i915_driver_unregister(dev_priv
);
1389 drm_vblank_cleanup(dev
);
1391 intel_modeset_cleanup(dev
);
1394 * free the memory space allocated for the child device
1395 * config parsed from VBT
1397 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1398 kfree(dev_priv
->vbt
.child_dev
);
1399 dev_priv
->vbt
.child_dev
= NULL
;
1400 dev_priv
->vbt
.child_dev_num
= 0;
1402 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1403 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1404 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1405 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1407 vga_switcheroo_unregister_client(pdev
);
1408 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1410 intel_csr_ucode_fini(dev_priv
);
1412 /* Free error state after interrupts are fully disabled. */
1413 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1414 i915_reset_error_state(dev_priv
);
1416 /* Flush any outstanding unpin_work. */
1417 drain_workqueue(dev_priv
->wq
);
1419 i915_gem_fini(dev_priv
);
1420 intel_uc_fini_fw(dev_priv
);
1421 intel_fbc_cleanup_cfb(dev_priv
);
1423 intel_power_domains_fini(dev_priv
);
1425 i915_driver_cleanup_hw(dev_priv
);
1426 i915_driver_cleanup_mmio(dev_priv
);
1428 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1431 static void i915_driver_release(struct drm_device
*dev
)
1433 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1435 i915_driver_cleanup_early(dev_priv
);
1436 drm_dev_fini(&dev_priv
->drm
);
1441 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1443 struct drm_i915_private
*i915
= to_i915(dev
);
1446 ret
= i915_gem_open(i915
, file
);
1454 * i915_driver_lastclose - clean up after all DRM clients have exited
1457 * Take care of cleaning up after all DRM clients have exited. In the
1458 * mode setting case, we want to restore the kernel's initial mode (just
1459 * in case the last client left us in a bad state).
1461 * Additionally, in the non-mode setting case, we'll tear down the GTT
1462 * and DMA structures, since the kernel won't be using them, and clea
1465 static void i915_driver_lastclose(struct drm_device
*dev
)
1467 intel_fbdev_restore_mode(dev
);
1468 vga_switcheroo_process_delayed_switch();
1471 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1473 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1475 mutex_lock(&dev
->struct_mutex
);
1476 i915_gem_context_close(file
);
1477 i915_gem_release(dev
, file
);
1478 mutex_unlock(&dev
->struct_mutex
);
1483 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1485 struct drm_device
*dev
= &dev_priv
->drm
;
1486 struct intel_encoder
*encoder
;
1488 drm_modeset_lock_all(dev
);
1489 for_each_intel_encoder(dev
, encoder
)
1490 if (encoder
->suspend
)
1491 encoder
->suspend(encoder
);
1492 drm_modeset_unlock_all(dev
);
1495 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1497 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1499 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1501 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1502 if (acpi_target_system_state() < ACPI_STATE_S3
)
1508 static int i915_drm_suspend(struct drm_device
*dev
)
1510 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1511 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1512 pci_power_t opregion_target_state
;
1515 /* ignore lid events during suspend */
1516 mutex_lock(&dev_priv
->modeset_restore_lock
);
1517 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
1518 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1520 disable_rpm_wakeref_asserts(dev_priv
);
1522 /* We do a lot of poking in a lot of registers, make sure they work
1524 intel_display_set_init_power(dev_priv
, true);
1526 drm_kms_helper_poll_disable(dev
);
1528 pci_save_state(pdev
);
1530 error
= i915_gem_suspend(dev_priv
);
1533 "GEM idle failed, resume might fail\n");
1537 intel_display_suspend(dev
);
1539 intel_dp_mst_suspend(dev
);
1541 intel_runtime_pm_disable_interrupts(dev_priv
);
1542 intel_hpd_cancel_work(dev_priv
);
1544 intel_suspend_encoders(dev_priv
);
1546 intel_suspend_hw(dev_priv
);
1548 i915_gem_suspend_gtt_mappings(dev_priv
);
1550 i915_save_state(dev_priv
);
1552 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1553 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1555 intel_uncore_suspend(dev_priv
);
1556 intel_opregion_unregister(dev_priv
);
1558 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1560 dev_priv
->suspend_count
++;
1562 intel_csr_ucode_suspend(dev_priv
);
1565 enable_rpm_wakeref_asserts(dev_priv
);
1570 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1572 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1573 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1577 disable_rpm_wakeref_asserts(dev_priv
);
1579 intel_display_set_init_power(dev_priv
, false);
1581 fw_csr
= !IS_GEN9_LP(dev_priv
) &&
1582 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1584 * In case of firmware assisted context save/restore don't manually
1585 * deinit the power domains. This also means the CSR/DMC firmware will
1586 * stay active, it will power down any HW resources as required and
1587 * also enable deeper system power states that would be blocked if the
1588 * firmware was inactive.
1591 intel_power_domains_suspend(dev_priv
);
1594 if (IS_GEN9_LP(dev_priv
))
1595 bxt_enable_dc9(dev_priv
);
1596 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1597 hsw_enable_pc8(dev_priv
);
1598 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1599 ret
= vlv_suspend_complete(dev_priv
);
1602 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1604 intel_power_domains_init_hw(dev_priv
, true);
1609 pci_disable_device(pdev
);
1611 * During hibernation on some platforms the BIOS may try to access
1612 * the device even though it's already in D3 and hang the machine. So
1613 * leave the device in D0 on those platforms and hope the BIOS will
1614 * power down the device properly. The issue was seen on multiple old
1615 * GENs with different BIOS vendors, so having an explicit blacklist
1616 * is inpractical; apply the workaround on everything pre GEN6. The
1617 * platforms where the issue was seen:
1618 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1622 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1623 pci_set_power_state(pdev
, PCI_D3hot
);
1625 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1628 enable_rpm_wakeref_asserts(dev_priv
);
1633 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1638 DRM_ERROR("dev: %p\n", dev
);
1639 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1643 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1644 state
.event
!= PM_EVENT_FREEZE
))
1647 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1650 error
= i915_drm_suspend(dev
);
1654 return i915_drm_suspend_late(dev
, false);
1657 static int i915_drm_resume(struct drm_device
*dev
)
1659 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1662 disable_rpm_wakeref_asserts(dev_priv
);
1663 intel_sanitize_gt_powersave(dev_priv
);
1665 ret
= i915_ggtt_enable_hw(dev_priv
);
1667 DRM_ERROR("failed to re-enable GGTT\n");
1669 intel_csr_ucode_resume(dev_priv
);
1671 i915_gem_resume(dev_priv
);
1673 i915_restore_state(dev_priv
);
1674 intel_pps_unlock_regs_wa(dev_priv
);
1675 intel_opregion_setup(dev_priv
);
1677 intel_init_pch_refclk(dev_priv
);
1680 * Interrupts have to be enabled before any batches are run. If not the
1681 * GPU will hang. i915_gem_init_hw() will initiate batches to
1682 * update/restore the context.
1684 * drm_mode_config_reset() needs AUX interrupts.
1686 * Modeset enabling in intel_modeset_init_hw() also needs working
1689 intel_runtime_pm_enable_interrupts(dev_priv
);
1691 drm_mode_config_reset(dev
);
1693 mutex_lock(&dev
->struct_mutex
);
1694 if (i915_gem_init_hw(dev_priv
)) {
1695 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1696 i915_gem_set_wedged(dev_priv
);
1698 mutex_unlock(&dev
->struct_mutex
);
1700 intel_guc_resume(dev_priv
);
1702 intel_modeset_init_hw(dev
);
1704 spin_lock_irq(&dev_priv
->irq_lock
);
1705 if (dev_priv
->display
.hpd_irq_setup
)
1706 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1707 spin_unlock_irq(&dev_priv
->irq_lock
);
1709 intel_dp_mst_resume(dev
);
1711 intel_display_resume(dev
);
1713 drm_kms_helper_poll_enable(dev
);
1716 * ... but also need to make sure that hotplug processing
1717 * doesn't cause havoc. Like in the driver load code we don't
1718 * bother with the tiny race here where we might loose hotplug
1721 intel_hpd_init(dev_priv
);
1723 intel_opregion_register(dev_priv
);
1725 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1727 mutex_lock(&dev_priv
->modeset_restore_lock
);
1728 dev_priv
->modeset_restore
= MODESET_DONE
;
1729 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1731 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1733 intel_autoenable_gt_powersave(dev_priv
);
1735 enable_rpm_wakeref_asserts(dev_priv
);
1740 static int i915_drm_resume_early(struct drm_device
*dev
)
1742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1743 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1747 * We have a resume ordering issue with the snd-hda driver also
1748 * requiring our device to be power up. Due to the lack of a
1749 * parent/child relationship we currently solve this with an early
1752 * FIXME: This should be solved with a special hdmi sink device or
1753 * similar so that power domains can be employed.
1757 * Note that we need to set the power state explicitly, since we
1758 * powered off the device during freeze and the PCI core won't power
1759 * it back up for us during thaw. Powering off the device during
1760 * freeze is not a hard requirement though, and during the
1761 * suspend/resume phases the PCI core makes sure we get here with the
1762 * device powered on. So in case we change our freeze logic and keep
1763 * the device powered we can also remove the following set power state
1766 ret
= pci_set_power_state(pdev
, PCI_D0
);
1768 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1773 * Note that pci_enable_device() first enables any parent bridge
1774 * device and only then sets the power state for this device. The
1775 * bridge enabling is a nop though, since bridge devices are resumed
1776 * first. The order of enabling power and enabling the device is
1777 * imposed by the PCI core as described above, so here we preserve the
1778 * same order for the freeze/thaw phases.
1780 * TODO: eventually we should remove pci_disable_device() /
1781 * pci_enable_enable_device() from suspend/resume. Due to how they
1782 * depend on the device enable refcount we can't anyway depend on them
1783 * disabling/enabling the device.
1785 if (pci_enable_device(pdev
)) {
1790 pci_set_master(pdev
);
1792 disable_rpm_wakeref_asserts(dev_priv
);
1794 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1795 ret
= vlv_resume_prepare(dev_priv
, false);
1797 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1800 intel_uncore_resume_early(dev_priv
);
1802 if (IS_GEN9_LP(dev_priv
)) {
1803 if (!dev_priv
->suspended_to_idle
)
1804 gen9_sanitize_dc_state(dev_priv
);
1805 bxt_disable_dc9(dev_priv
);
1806 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1807 hsw_disable_pc8(dev_priv
);
1810 intel_uncore_sanitize(dev_priv
);
1812 if (IS_GEN9_LP(dev_priv
) ||
1813 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1814 intel_power_domains_init_hw(dev_priv
, true);
1816 i915_gem_sanitize(dev_priv
);
1818 enable_rpm_wakeref_asserts(dev_priv
);
1821 dev_priv
->suspended_to_idle
= false;
1826 static int i915_resume_switcheroo(struct drm_device
*dev
)
1830 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1833 ret
= i915_drm_resume_early(dev
);
1837 return i915_drm_resume(dev
);
1841 * i915_reset - reset chip after a hang
1842 * @dev_priv: device private to reset
1844 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1847 * Caller must hold the struct_mutex.
1849 * Procedure is fairly simple:
1850 * - reset the chip using the reset reg
1851 * - re-init context state
1852 * - re-init hardware status page
1853 * - re-init ring buffer
1854 * - re-init interrupt state
1857 void i915_reset(struct drm_i915_private
*dev_priv
)
1859 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
1862 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
1863 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF
, &error
->flags
));
1865 if (!test_bit(I915_RESET_HANDOFF
, &error
->flags
))
1868 /* Clear any previous failed attempts at recovery. Time to try again. */
1869 if (!i915_gem_unset_wedged(dev_priv
))
1872 error
->reset_count
++;
1874 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1875 disable_irq(dev_priv
->drm
.irq
);
1876 ret
= i915_gem_reset_prepare(dev_priv
);
1878 DRM_ERROR("GPU recovery failed\n");
1879 intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1883 ret
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1886 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1888 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1892 i915_gem_reset(dev_priv
);
1893 intel_overlay_reset(dev_priv
);
1895 /* Ok, now get things going again... */
1898 * Everything depends on having the GTT running, so we need to start
1899 * there. Fortunately we don't need to do this unless we reset the
1900 * chip at a PCI level.
1902 * Next we need to restore the context, but we don't use those
1905 * Ring buffer needs to be re-initialized in the KMS case, or if X
1906 * was running at the time of the reset (i.e. we weren't VT
1909 ret
= i915_gem_init_hw(dev_priv
);
1911 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1915 i915_queue_hangcheck(dev_priv
);
1918 i915_gem_reset_finish(dev_priv
);
1919 enable_irq(dev_priv
->drm
.irq
);
1922 clear_bit(I915_RESET_HANDOFF
, &error
->flags
);
1923 wake_up_bit(&error
->flags
, I915_RESET_HANDOFF
);
1927 i915_gem_set_wedged(dev_priv
);
1928 i915_gem_retire_requests(dev_priv
);
1933 * i915_reset_engine - reset GPU engine to recover from a hang
1934 * @engine: engine to reset
1936 * Reset a specific GPU engine. Useful if a hang is detected.
1937 * Returns zero on successful reset or otherwise an error code.
1940 * - identifies the request that caused the hang and it is dropped
1941 * - reset engine (which will force the engine to idle)
1942 * - re-init/configure engine
1944 int i915_reset_engine(struct intel_engine_cs
*engine
)
1946 struct i915_gpu_error
*error
= &engine
->i915
->gpu_error
;
1947 struct drm_i915_gem_request
*active_request
;
1950 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE
+ engine
->id
, &error
->flags
));
1952 DRM_DEBUG_DRIVER("resetting %s\n", engine
->name
);
1954 active_request
= i915_gem_reset_prepare_engine(engine
);
1955 if (IS_ERR(active_request
)) {
1956 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1957 ret
= PTR_ERR(active_request
);
1962 * The request that caused the hang is stuck on elsp, we know the
1963 * active request and can drop it, adjust head to skip the offending
1964 * request to resume executing remaining requests in the queue.
1966 i915_gem_reset_engine(engine
, active_request
);
1968 /* Finally, reset just this engine. */
1969 ret
= intel_gpu_reset(engine
->i915
, intel_engine_flag(engine
));
1971 i915_gem_reset_finish_engine(engine
);
1974 /* If we fail here, we expect to fallback to a global reset */
1975 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1981 * The engine and its registers (and workarounds in case of render)
1982 * have been reset to their default values. Follow the init_ring
1983 * process to program RING_MODE, HWSP and re-enable submission.
1985 ret
= engine
->init_hw(engine
);
1989 error
->reset_engine_count
[engine
->id
]++;
1994 static int i915_pm_suspend(struct device
*kdev
)
1996 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1997 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2000 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
2004 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2007 return i915_drm_suspend(dev
);
2010 static int i915_pm_suspend_late(struct device
*kdev
)
2012 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2015 * We have a suspend ordering issue with the snd-hda driver also
2016 * requiring our device to be power up. Due to the lack of a
2017 * parent/child relationship we currently solve this with an late
2020 * FIXME: This should be solved with a special hdmi sink device or
2021 * similar so that power domains can be employed.
2023 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2026 return i915_drm_suspend_late(dev
, false);
2029 static int i915_pm_poweroff_late(struct device
*kdev
)
2031 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2033 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2036 return i915_drm_suspend_late(dev
, true);
2039 static int i915_pm_resume_early(struct device
*kdev
)
2041 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2043 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2046 return i915_drm_resume_early(dev
);
2049 static int i915_pm_resume(struct device
*kdev
)
2051 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2053 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2056 return i915_drm_resume(dev
);
2059 /* freeze: before creating the hibernation_image */
2060 static int i915_pm_freeze(struct device
*kdev
)
2064 ret
= i915_pm_suspend(kdev
);
2068 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
2075 static int i915_pm_freeze_late(struct device
*kdev
)
2079 ret
= i915_pm_suspend_late(kdev
);
2083 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
2090 /* thaw: called after creating the hibernation image, but before turning off. */
2091 static int i915_pm_thaw_early(struct device
*kdev
)
2093 return i915_pm_resume_early(kdev
);
2096 static int i915_pm_thaw(struct device
*kdev
)
2098 return i915_pm_resume(kdev
);
2101 /* restore: called after loading the hibernation image. */
2102 static int i915_pm_restore_early(struct device
*kdev
)
2104 return i915_pm_resume_early(kdev
);
2107 static int i915_pm_restore(struct device
*kdev
)
2109 return i915_pm_resume(kdev
);
2113 * Save all Gunit registers that may be lost after a D3 and a subsequent
2114 * S0i[R123] transition. The list of registers needing a save/restore is
2115 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2116 * registers in the following way:
2117 * - Driver: saved/restored by the driver
2118 * - Punit : saved/restored by the Punit firmware
2119 * - No, w/o marking: no need to save/restore, since the register is R/O or
2120 * used internally by the HW in a way that doesn't depend
2121 * keeping the content across a suspend/resume.
2122 * - Debug : used for debugging
2124 * We save/restore all registers marked with 'Driver', with the following
2126 * - Registers out of use, including also registers marked with 'Debug'.
2127 * These have no effect on the driver's operation, so we don't save/restore
2128 * them to reduce the overhead.
2129 * - Registers that are fully setup by an initialization function called from
2130 * the resume path. For example many clock gating and RPS/RC6 registers.
2131 * - Registers that provide the right functionality with their reset defaults.
2133 * TODO: Except for registers that based on the above 3 criteria can be safely
2134 * ignored, we save/restore all others, practically treating the HW context as
2135 * a black-box for the driver. Further investigation is needed to reduce the
2136 * saved/restored registers even further, by following the same 3 criteria.
2138 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2140 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2143 /* GAM 0x4000-0x4770 */
2144 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2145 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2146 s
->arb_mode
= I915_READ(ARB_MODE
);
2147 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2148 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2150 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2151 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2153 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2154 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2156 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2157 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2158 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2159 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2161 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2163 /* MBC 0x9024-0x91D0, 0x8500 */
2164 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2165 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2166 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2168 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2169 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2170 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2171 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2172 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2173 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2174 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2176 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2177 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2178 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2179 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2180 s
->ecobus
= I915_READ(ECOBUS
);
2181 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2182 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2183 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2184 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2185 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2186 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2188 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2189 s
->gt_imr
= I915_READ(GTIMR
);
2190 s
->gt_ier
= I915_READ(GTIER
);
2191 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2192 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2194 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2195 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2197 /* GT SA CZ domain, 0x100000-0x138124 */
2198 s
->tilectl
= I915_READ(TILECTL
);
2199 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2200 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2201 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2202 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2204 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2205 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2206 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2207 s
->pcbr
= I915_READ(VLV_PCBR
);
2208 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2211 * Not saving any of:
2212 * DFT, 0x9800-0x9EC0
2213 * SARB, 0xB000-0xB1FC
2214 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2219 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2221 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2225 /* GAM 0x4000-0x4770 */
2226 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2227 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2228 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2229 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2230 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2232 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2233 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2235 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2236 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2238 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2239 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2240 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2241 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2243 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2245 /* MBC 0x9024-0x91D0, 0x8500 */
2246 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2247 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2248 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2250 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2251 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2252 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2253 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2254 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2255 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2256 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2258 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2259 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2260 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2261 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2262 I915_WRITE(ECOBUS
, s
->ecobus
);
2263 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2264 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2265 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2266 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2267 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2268 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2270 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2271 I915_WRITE(GTIMR
, s
->gt_imr
);
2272 I915_WRITE(GTIER
, s
->gt_ier
);
2273 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2274 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2276 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2277 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2279 /* GT SA CZ domain, 0x100000-0x138124 */
2280 I915_WRITE(TILECTL
, s
->tilectl
);
2281 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2283 * Preserve the GT allow wake and GFX force clock bit, they are not
2284 * be restored, as they are used to control the s0ix suspend/resume
2285 * sequence by the caller.
2287 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2288 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2289 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2290 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2292 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2293 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2294 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2295 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2297 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2299 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2300 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2301 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2302 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2303 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2306 static int vlv_wait_for_pw_status(struct drm_i915_private
*dev_priv
,
2309 /* The HW does not like us polling for PW_STATUS frequently, so
2310 * use the sleeping loop rather than risk the busy spin within
2311 * intel_wait_for_register().
2313 * Transitioning between RC6 states should be at most 2ms (see
2314 * valleyview_enable_rps) so use a 3ms timeout.
2316 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS
) & mask
) == val
,
2320 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2325 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2326 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2328 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2329 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2334 err
= intel_wait_for_register(dev_priv
,
2335 VLV_GTLC_SURVIVABILITY_REG
,
2336 VLV_GFX_CLK_STATUS_BIT
,
2337 VLV_GFX_CLK_STATUS_BIT
,
2340 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2341 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2346 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2352 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2353 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2355 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2356 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2357 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2359 mask
= VLV_GTLC_ALLOWWAKEACK
;
2360 val
= allow
? mask
: 0;
2362 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2364 DRM_ERROR("timeout disabling GT waking\n");
2369 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2375 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2376 val
= wait_for_on
? mask
: 0;
2379 * RC6 transitioning can be delayed up to 2 msec (see
2380 * valleyview_enable_rps), use 3 msec for safety.
2382 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2383 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2384 onoff(wait_for_on
));
2387 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2389 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2392 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2393 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2396 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2402 * Bspec defines the following GT well on flags as debug only, so
2403 * don't treat them as hard failures.
2405 vlv_wait_for_gt_wells(dev_priv
, false);
2407 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2408 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2410 vlv_check_no_gt_access(dev_priv
);
2412 err
= vlv_force_gfx_clock(dev_priv
, true);
2416 err
= vlv_allow_gt_wake(dev_priv
, false);
2420 if (!IS_CHERRYVIEW(dev_priv
))
2421 vlv_save_gunit_s0ix_state(dev_priv
);
2423 err
= vlv_force_gfx_clock(dev_priv
, false);
2430 /* For safety always re-enable waking and disable gfx clock forcing */
2431 vlv_allow_gt_wake(dev_priv
, true);
2433 vlv_force_gfx_clock(dev_priv
, false);
2438 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2445 * If any of the steps fail just try to continue, that's the best we
2446 * can do at this point. Return the first error code (which will also
2447 * leave RPM permanently disabled).
2449 ret
= vlv_force_gfx_clock(dev_priv
, true);
2451 if (!IS_CHERRYVIEW(dev_priv
))
2452 vlv_restore_gunit_s0ix_state(dev_priv
);
2454 err
= vlv_allow_gt_wake(dev_priv
, true);
2458 err
= vlv_force_gfx_clock(dev_priv
, false);
2462 vlv_check_no_gt_access(dev_priv
);
2465 intel_init_clock_gating(dev_priv
);
2470 static int intel_runtime_suspend(struct device
*kdev
)
2472 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2473 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2474 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2477 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6())))
2480 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2483 DRM_DEBUG_KMS("Suspending device\n");
2485 disable_rpm_wakeref_asserts(dev_priv
);
2488 * We are safe here against re-faults, since the fault handler takes
2491 i915_gem_runtime_suspend(dev_priv
);
2493 intel_guc_suspend(dev_priv
);
2495 intel_runtime_pm_disable_interrupts(dev_priv
);
2498 if (IS_GEN9_LP(dev_priv
)) {
2499 bxt_display_core_uninit(dev_priv
);
2500 bxt_enable_dc9(dev_priv
);
2501 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2502 hsw_enable_pc8(dev_priv
);
2503 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2504 ret
= vlv_suspend_complete(dev_priv
);
2508 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2509 intel_runtime_pm_enable_interrupts(dev_priv
);
2511 enable_rpm_wakeref_asserts(dev_priv
);
2516 intel_uncore_suspend(dev_priv
);
2518 enable_rpm_wakeref_asserts(dev_priv
);
2519 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2521 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2522 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2524 dev_priv
->pm
.suspended
= true;
2527 * FIXME: We really should find a document that references the arguments
2530 if (IS_BROADWELL(dev_priv
)) {
2532 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2533 * being detected, and the call we do at intel_runtime_resume()
2534 * won't be able to restore them. Since PCI_D3hot matches the
2535 * actual specification and appears to be working, use it.
2537 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2540 * current versions of firmware which depend on this opregion
2541 * notification have repurposed the D1 definition to mean
2542 * "runtime suspended" vs. what you would normally expect (D3)
2543 * to distinguish it from notifications that might be sent via
2546 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2549 assert_forcewakes_inactive(dev_priv
);
2551 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2552 intel_hpd_poll_init(dev_priv
);
2554 DRM_DEBUG_KMS("Device suspended\n");
2558 static int intel_runtime_resume(struct device
*kdev
)
2560 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2561 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2562 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2565 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2568 DRM_DEBUG_KMS("Resuming device\n");
2570 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2571 disable_rpm_wakeref_asserts(dev_priv
);
2573 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2574 dev_priv
->pm
.suspended
= false;
2575 if (intel_uncore_unclaimed_mmio(dev_priv
))
2576 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2578 intel_guc_resume(dev_priv
);
2580 if (IS_GEN9_LP(dev_priv
)) {
2581 bxt_disable_dc9(dev_priv
);
2582 bxt_display_core_init(dev_priv
, true);
2583 if (dev_priv
->csr
.dmc_payload
&&
2584 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2585 gen9_enable_dc5(dev_priv
);
2586 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2587 hsw_disable_pc8(dev_priv
);
2588 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2589 ret
= vlv_resume_prepare(dev_priv
, true);
2593 * No point of rolling back things in case of an error, as the best
2594 * we can do is to hope that things will still work (and disable RPM).
2596 i915_gem_init_swizzling(dev_priv
);
2597 i915_gem_restore_fences(dev_priv
);
2599 intel_runtime_pm_enable_interrupts(dev_priv
);
2602 * On VLV/CHV display interrupts are part of the display
2603 * power well, so hpd is reinitialized from there. For
2604 * everyone else do it here.
2606 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2607 intel_hpd_init(dev_priv
);
2609 enable_rpm_wakeref_asserts(dev_priv
);
2612 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2614 DRM_DEBUG_KMS("Device resumed\n");
2619 const struct dev_pm_ops i915_pm_ops
= {
2621 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2624 .suspend
= i915_pm_suspend
,
2625 .suspend_late
= i915_pm_suspend_late
,
2626 .resume_early
= i915_pm_resume_early
,
2627 .resume
= i915_pm_resume
,
2631 * @freeze, @freeze_late : called (1) before creating the
2632 * hibernation image [PMSG_FREEZE] and
2633 * (2) after rebooting, before restoring
2634 * the image [PMSG_QUIESCE]
2635 * @thaw, @thaw_early : called (1) after creating the hibernation
2636 * image, before writing it [PMSG_THAW]
2637 * and (2) after failing to create or
2638 * restore the image [PMSG_RECOVER]
2639 * @poweroff, @poweroff_late: called after writing the hibernation
2640 * image, before rebooting [PMSG_HIBERNATE]
2641 * @restore, @restore_early : called after rebooting and restoring the
2642 * hibernation image [PMSG_RESTORE]
2644 .freeze
= i915_pm_freeze
,
2645 .freeze_late
= i915_pm_freeze_late
,
2646 .thaw_early
= i915_pm_thaw_early
,
2647 .thaw
= i915_pm_thaw
,
2648 .poweroff
= i915_pm_suspend
,
2649 .poweroff_late
= i915_pm_poweroff_late
,
2650 .restore_early
= i915_pm_restore_early
,
2651 .restore
= i915_pm_restore
,
2653 /* S0ix (via runtime suspend) event handlers */
2654 .runtime_suspend
= intel_runtime_suspend
,
2655 .runtime_resume
= intel_runtime_resume
,
2658 static const struct vm_operations_struct i915_gem_vm_ops
= {
2659 .fault
= i915_gem_fault
,
2660 .open
= drm_gem_vm_open
,
2661 .close
= drm_gem_vm_close
,
2664 static const struct file_operations i915_driver_fops
= {
2665 .owner
= THIS_MODULE
,
2667 .release
= drm_release
,
2668 .unlocked_ioctl
= drm_ioctl
,
2669 .mmap
= drm_gem_mmap
,
2672 .compat_ioctl
= i915_compat_ioctl
,
2673 .llseek
= noop_llseek
,
2677 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2678 struct drm_file
*file
)
2683 static const struct drm_ioctl_desc i915_ioctls
[] = {
2684 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2685 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2686 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2687 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2688 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2689 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2690 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2691 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2692 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2693 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2694 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2695 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2696 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2697 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2698 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2699 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2700 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2701 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2702 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2703 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2704 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2705 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2706 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2707 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2708 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2709 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2710 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2711 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2712 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2713 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2714 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2715 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2716 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2717 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2718 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2719 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2720 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2721 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2722 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2723 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2724 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2725 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2726 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2727 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2728 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2729 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2730 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2731 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2732 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2733 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2734 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2735 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2736 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2739 static struct drm_driver driver
= {
2740 /* Don't use MTRRs here; the Xserver or userspace app should
2741 * deal with them for Intel hardware.
2744 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2745 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
,
2746 .release
= i915_driver_release
,
2747 .open
= i915_driver_open
,
2748 .lastclose
= i915_driver_lastclose
,
2749 .postclose
= i915_driver_postclose
,
2750 .set_busid
= drm_pci_set_busid
,
2752 .gem_close_object
= i915_gem_close_object
,
2753 .gem_free_object_unlocked
= i915_gem_free_object
,
2754 .gem_vm_ops
= &i915_gem_vm_ops
,
2756 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2757 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2758 .gem_prime_export
= i915_gem_prime_export
,
2759 .gem_prime_import
= i915_gem_prime_import
,
2761 .dumb_create
= i915_gem_dumb_create
,
2762 .dumb_map_offset
= i915_gem_mmap_gtt
,
2763 .dumb_destroy
= drm_gem_dumb_destroy
,
2764 .ioctls
= i915_ioctls
,
2765 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2766 .fops
= &i915_driver_fops
,
2767 .name
= DRIVER_NAME
,
2768 .desc
= DRIVER_DESC
,
2769 .date
= DRIVER_DATE
,
2770 .major
= DRIVER_MAJOR
,
2771 .minor
= DRIVER_MINOR
,
2772 .patchlevel
= DRIVER_PATCHLEVEL
,
2775 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2776 #include "selftests/mock_drm.c"