1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver
;
57 static unsigned int i915_load_fail_count
;
59 bool __i915_inject_load_failure(const char *func
, int line
)
61 if (i915_load_fail_count
>= i915_modparams
.inject_load_failure
)
64 if (++i915_load_fail_count
== i915_modparams
.inject_load_failure
) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915_modparams
.inject_load_failure
, func
, line
);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
81 static bool shown_bug_once
;
82 struct device
*kdev
= dev_priv
->drm
.dev
;
83 bool is_error
= level
[1] <= KERN_ERR
[1];
84 bool is_debug
= level
[1] == KERN_DEBUG
[1];
88 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
96 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
97 __builtin_return_address(0), &vaf
);
99 if (is_error
&& !shown_bug_once
) {
100 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
101 shown_bug_once
= true;
107 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
109 return i915_modparams
.inject_load_failure
&&
110 i915_load_fail_count
== i915_modparams
.inject_load_failure
;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch
intel_virt_detect_pch(struct drm_i915_private
*dev_priv
)
121 enum intel_pch ret
= PCH_NOP
;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv
)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
)) {
135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
138 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
139 dev_priv
->pch_id
= INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
141 dev_priv
->pch_id
= INTEL_PCH_LPT_DEVICE_ID_TYPE
;
142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
143 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146 } else if (IS_COFFEELAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
154 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
156 struct pci_dev
*pch
= NULL
;
158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
161 if (INTEL_INFO(dev_priv
)->num_pipes
== 0) {
162 dev_priv
->pch_type
= PCH_NOP
;
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
177 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
178 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
179 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
181 dev_priv
->pch_id
= id
;
183 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
184 dev_priv
->pch_type
= PCH_IBX
;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
186 WARN_ON(!IS_GEN5(dev_priv
));
187 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
188 dev_priv
->pch_type
= PCH_CPT
;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
190 WARN_ON(!IS_GEN6(dev_priv
) &&
191 !IS_IVYBRIDGE(dev_priv
));
192 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
193 /* PantherPoint is CPT compatible */
194 dev_priv
->pch_type
= PCH_CPT
;
195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
196 WARN_ON(!IS_GEN6(dev_priv
) &&
197 !IS_IVYBRIDGE(dev_priv
));
198 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
199 dev_priv
->pch_type
= PCH_LPT
;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201 WARN_ON(!IS_HASWELL(dev_priv
) &&
202 !IS_BROADWELL(dev_priv
));
203 WARN_ON(IS_HSW_ULT(dev_priv
) ||
204 IS_BDW_ULT(dev_priv
));
205 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
206 dev_priv
->pch_type
= PCH_LPT
;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
208 WARN_ON(!IS_HASWELL(dev_priv
) &&
209 !IS_BROADWELL(dev_priv
));
210 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
211 !IS_BDW_ULT(dev_priv
));
212 } else if (id
== INTEL_PCH_WPT_DEVICE_ID_TYPE
) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv
->pch_type
= PCH_LPT
;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv
) &&
217 !IS_BROADWELL(dev_priv
));
218 WARN_ON(IS_HSW_ULT(dev_priv
) ||
219 IS_BDW_ULT(dev_priv
));
220 } else if (id
== INTEL_PCH_WPT_LP_DEVICE_ID_TYPE
) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv
->pch_type
= PCH_LPT
;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv
) &&
225 !IS_BROADWELL(dev_priv
));
226 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
227 !IS_BDW_ULT(dev_priv
));
228 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
229 dev_priv
->pch_type
= PCH_SPT
;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
231 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
232 !IS_KABYLAKE(dev_priv
));
233 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
234 dev_priv
->pch_type
= PCH_SPT
;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
236 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
237 !IS_KABYLAKE(dev_priv
));
238 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
239 dev_priv
->pch_type
= PCH_KBP
;
240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
241 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
242 !IS_KABYLAKE(dev_priv
) &&
243 !IS_COFFEELAKE(dev_priv
));
244 } else if (id
== INTEL_PCH_CNP_DEVICE_ID_TYPE
) {
245 dev_priv
->pch_type
= PCH_CNP
;
246 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
247 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
248 !IS_COFFEELAKE(dev_priv
));
249 } else if (id
== INTEL_PCH_CNP_LP_DEVICE_ID_TYPE
) {
250 dev_priv
->pch_type
= PCH_CNP
;
251 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
252 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
253 !IS_COFFEELAKE(dev_priv
));
254 } else if (id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
||
255 id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
||
256 (id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
&&
257 pch
->subsystem_vendor
==
258 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
259 pch
->subsystem_device
==
260 PCI_SUBDEVICE_ID_QEMU
)) {
262 intel_virt_detect_pch(dev_priv
);
270 DRM_DEBUG_KMS("No PCH found.\n");
275 static int i915_getparam(struct drm_device
*dev
, void *data
,
276 struct drm_file
*file_priv
)
278 struct drm_i915_private
*dev_priv
= to_i915(dev
);
279 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
280 drm_i915_getparam_t
*param
= data
;
283 switch (param
->param
) {
284 case I915_PARAM_IRQ_ACTIVE
:
285 case I915_PARAM_ALLOW_BATCHBUFFER
:
286 case I915_PARAM_LAST_DISPATCH
:
287 case I915_PARAM_HAS_EXEC_CONSTANTS
:
288 /* Reject all old ums/dri params. */
290 case I915_PARAM_CHIPSET_ID
:
291 value
= pdev
->device
;
293 case I915_PARAM_REVISION
:
294 value
= pdev
->revision
;
296 case I915_PARAM_NUM_FENCES_AVAIL
:
297 value
= dev_priv
->num_fence_regs
;
299 case I915_PARAM_HAS_OVERLAY
:
300 value
= dev_priv
->overlay
? 1 : 0;
302 case I915_PARAM_HAS_BSD
:
303 value
= !!dev_priv
->engine
[VCS
];
305 case I915_PARAM_HAS_BLT
:
306 value
= !!dev_priv
->engine
[BCS
];
308 case I915_PARAM_HAS_VEBOX
:
309 value
= !!dev_priv
->engine
[VECS
];
311 case I915_PARAM_HAS_BSD2
:
312 value
= !!dev_priv
->engine
[VCS2
];
314 case I915_PARAM_HAS_LLC
:
315 value
= HAS_LLC(dev_priv
);
317 case I915_PARAM_HAS_WT
:
318 value
= HAS_WT(dev_priv
);
320 case I915_PARAM_HAS_ALIASING_PPGTT
:
321 value
= USES_PPGTT(dev_priv
);
323 case I915_PARAM_HAS_SEMAPHORES
:
324 value
= i915_modparams
.semaphores
;
326 case I915_PARAM_HAS_SECURE_BATCHES
:
327 value
= capable(CAP_SYS_ADMIN
);
329 case I915_PARAM_CMD_PARSER_VERSION
:
330 value
= i915_cmd_parser_get_version(dev_priv
);
332 case I915_PARAM_SUBSLICE_TOTAL
:
333 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
337 case I915_PARAM_EU_TOTAL
:
338 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
342 case I915_PARAM_HAS_GPU_RESET
:
343 value
= i915_modparams
.enable_hangcheck
&&
344 intel_has_gpu_reset(dev_priv
);
345 if (value
&& intel_has_reset_engine(dev_priv
))
348 case I915_PARAM_HAS_RESOURCE_STREAMER
:
349 value
= HAS_RESOURCE_STREAMER(dev_priv
);
351 case I915_PARAM_HAS_POOLED_EU
:
352 value
= HAS_POOLED_EU(dev_priv
);
354 case I915_PARAM_MIN_EU_IN_POOL
:
355 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
357 case I915_PARAM_HUC_STATUS
:
358 intel_runtime_pm_get(dev_priv
);
359 value
= I915_READ(HUC_STATUS2
) & HUC_FW_VERIFIED
;
360 intel_runtime_pm_put(dev_priv
);
362 case I915_PARAM_MMAP_GTT_VERSION
:
363 /* Though we've started our numbering from 1, and so class all
364 * earlier versions as 0, in effect their value is undefined as
365 * the ioctl will report EINVAL for the unknown param!
367 value
= i915_gem_mmap_gtt_version();
369 case I915_PARAM_HAS_SCHEDULER
:
371 if (dev_priv
->engine
[RCS
] && dev_priv
->engine
[RCS
]->schedule
) {
372 value
|= I915_SCHEDULER_CAP_ENABLED
;
373 value
|= I915_SCHEDULER_CAP_PRIORITY
;
375 if (INTEL_INFO(dev_priv
)->has_logical_ring_preemption
&&
376 i915_modparams
.enable_execlists
&&
377 !i915_modparams
.enable_guc_submission
)
378 value
|= I915_SCHEDULER_CAP_PREEMPTION
;
382 case I915_PARAM_MMAP_VERSION
:
383 /* Remember to bump this if the version changes! */
384 case I915_PARAM_HAS_GEM
:
385 case I915_PARAM_HAS_PAGEFLIPPING
:
386 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
387 case I915_PARAM_HAS_RELAXED_FENCING
:
388 case I915_PARAM_HAS_COHERENT_RINGS
:
389 case I915_PARAM_HAS_RELAXED_DELTA
:
390 case I915_PARAM_HAS_GEN7_SOL_RESET
:
391 case I915_PARAM_HAS_WAIT_TIMEOUT
:
392 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
393 case I915_PARAM_HAS_PINNED_BATCHES
:
394 case I915_PARAM_HAS_EXEC_NO_RELOC
:
395 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
396 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
397 case I915_PARAM_HAS_EXEC_SOFTPIN
:
398 case I915_PARAM_HAS_EXEC_ASYNC
:
399 case I915_PARAM_HAS_EXEC_FENCE
:
400 case I915_PARAM_HAS_EXEC_CAPTURE
:
401 case I915_PARAM_HAS_EXEC_BATCH_FIRST
:
402 case I915_PARAM_HAS_EXEC_FENCE_ARRAY
:
403 /* For the time being all of these are always true;
404 * if some supported hardware does not have one of these
405 * features this value needs to be provided from
406 * INTEL_INFO(), a feature macro, or similar.
410 case I915_PARAM_SLICE_MASK
:
411 value
= INTEL_INFO(dev_priv
)->sseu
.slice_mask
;
415 case I915_PARAM_SUBSLICE_MASK
:
416 value
= INTEL_INFO(dev_priv
)->sseu
.subslice_mask
;
421 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
425 if (put_user(value
, param
->value
))
431 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
433 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
434 if (!dev_priv
->bridge_dev
) {
435 DRM_ERROR("bridge device not found\n");
441 /* Allocate space for the MCH regs if needed, return nonzero on error */
443 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
445 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
446 u32 temp_lo
, temp_hi
= 0;
450 if (INTEL_GEN(dev_priv
) >= 4)
451 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
452 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
453 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
455 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
458 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
462 /* Get some space for it */
463 dev_priv
->mch_res
.name
= "i915 MCHBAR";
464 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
465 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
467 MCHBAR_SIZE
, MCHBAR_SIZE
,
469 0, pcibios_align_resource
,
470 dev_priv
->bridge_dev
);
472 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
473 dev_priv
->mch_res
.start
= 0;
477 if (INTEL_GEN(dev_priv
) >= 4)
478 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
479 upper_32_bits(dev_priv
->mch_res
.start
));
481 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
482 lower_32_bits(dev_priv
->mch_res
.start
));
486 /* Setup MCHBAR if possible, return true if we should disable it again */
488 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
490 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
494 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
497 dev_priv
->mchbar_need_disable
= false;
499 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
500 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
501 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
503 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
507 /* If it's already enabled, don't have to do anything */
511 if (intel_alloc_mchbar_resource(dev_priv
))
514 dev_priv
->mchbar_need_disable
= true;
516 /* Space is allocated or reserved, so enable it. */
517 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
518 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
519 temp
| DEVEN_MCHBAR_EN
);
521 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
522 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
527 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
529 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
531 if (dev_priv
->mchbar_need_disable
) {
532 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
535 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
537 deven_val
&= ~DEVEN_MCHBAR_EN
;
538 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
543 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
546 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
551 if (dev_priv
->mch_res
.start
)
552 release_resource(&dev_priv
->mch_res
);
555 /* true = enable decode, false = disable decoder */
556 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
558 struct drm_i915_private
*dev_priv
= cookie
;
560 intel_modeset_vga_set_state(dev_priv
, state
);
562 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
563 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
565 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
568 static int i915_resume_switcheroo(struct drm_device
*dev
);
569 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
571 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
573 struct drm_device
*dev
= pci_get_drvdata(pdev
);
574 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
576 if (state
== VGA_SWITCHEROO_ON
) {
577 pr_info("switched on\n");
578 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
579 /* i915 resume handler doesn't set to D0 */
580 pci_set_power_state(pdev
, PCI_D0
);
581 i915_resume_switcheroo(dev
);
582 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
584 pr_info("switched off\n");
585 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
586 i915_suspend_switcheroo(dev
, pmm
);
587 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
591 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
593 struct drm_device
*dev
= pci_get_drvdata(pdev
);
596 * FIXME: open_count is protected by drm_global_mutex but that would lead to
597 * locking inversion with the driver load path. And the access here is
598 * completely racy anyway. So don't bother with locking for now.
600 return dev
->open_count
== 0;
603 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
604 .set_gpu_state
= i915_switcheroo_set_state
,
606 .can_switch
= i915_switcheroo_can_switch
,
609 static void i915_gem_fini(struct drm_i915_private
*dev_priv
)
611 /* Flush any outstanding unpin_work. */
612 i915_gem_drain_workqueue(dev_priv
);
614 mutex_lock(&dev_priv
->drm
.struct_mutex
);
615 intel_uc_fini_hw(dev_priv
);
616 i915_gem_cleanup_engines(dev_priv
);
617 i915_gem_contexts_fini(dev_priv
);
618 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
620 i915_gem_cleanup_userptr(dev_priv
);
622 i915_gem_drain_freed_objects(dev_priv
);
624 WARN_ON(!list_empty(&dev_priv
->contexts
.list
));
627 static int i915_load_modeset_init(struct drm_device
*dev
)
629 struct drm_i915_private
*dev_priv
= to_i915(dev
);
630 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
633 if (i915_inject_load_failure())
636 intel_bios_init(dev_priv
);
638 /* If we have > 1 VGA cards, then we need to arbitrate access
639 * to the common VGA resources.
641 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
642 * then we do not take part in VGA arbitration and the
643 * vga_client_register() fails with -ENODEV.
645 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
646 if (ret
&& ret
!= -ENODEV
)
649 intel_register_dsm_handler();
651 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
653 goto cleanup_vga_client
;
655 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
656 intel_update_rawclk(dev_priv
);
658 intel_power_domains_init_hw(dev_priv
, false);
660 intel_csr_ucode_init(dev_priv
);
662 ret
= intel_irq_install(dev_priv
);
666 intel_setup_gmbus(dev_priv
);
668 /* Important: The output setup functions called by modeset_init need
669 * working irqs for e.g. gmbus and dp aux transfers. */
670 ret
= intel_modeset_init(dev
);
674 intel_uc_init_fw(dev_priv
);
676 ret
= i915_gem_init(dev_priv
);
680 intel_modeset_gem_init(dev
);
682 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
685 ret
= intel_fbdev_init(dev
);
689 /* Only enable hotplug handling once the fbdev is fully set up. */
690 intel_hpd_init(dev_priv
);
692 drm_kms_helper_poll_init(dev
);
697 if (i915_gem_suspend(dev_priv
))
698 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
699 i915_gem_fini(dev_priv
);
701 intel_uc_fini_fw(dev_priv
);
703 drm_irq_uninstall(dev
);
704 intel_teardown_gmbus(dev_priv
);
706 intel_csr_ucode_fini(dev_priv
);
707 intel_power_domains_fini(dev_priv
);
708 vga_switcheroo_unregister_client(pdev
);
710 vga_client_register(pdev
, NULL
, NULL
, NULL
);
715 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
717 struct apertures_struct
*ap
;
718 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
719 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
723 ap
= alloc_apertures(1);
727 ap
->ranges
[0].base
= ggtt
->mappable_base
;
728 ap
->ranges
[0].size
= ggtt
->mappable_end
;
731 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
733 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
740 #if !defined(CONFIG_VGA_CONSOLE)
741 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
745 #elif !defined(CONFIG_DUMMY_CONSOLE)
746 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
751 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
755 DRM_INFO("Replacing VGA console driver\n");
758 if (con_is_bound(&vga_con
))
759 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
761 ret
= do_unregister_con_driver(&vga_con
);
763 /* Ignore "already unregistered". */
773 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
776 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
777 * CHV x1 PHY (DP/HDMI D)
778 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
780 if (IS_CHERRYVIEW(dev_priv
)) {
781 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
782 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
783 } else if (IS_VALLEYVIEW(dev_priv
)) {
784 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
788 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
791 * The i915 workqueue is primarily used for batched retirement of
792 * requests (and thus managing bo) once the task has been completed
793 * by the GPU. i915_gem_retire_requests() is called directly when we
794 * need high-priority retirement, such as waiting for an explicit
797 * It is also used for periodic low-priority events, such as
798 * idle-timers and recording error state.
800 * All tasks on the workqueue are expected to acquire the dev mutex
801 * so there is no point in running more than one instance of the
802 * workqueue at any time. Use an ordered one.
804 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
805 if (dev_priv
->wq
== NULL
)
808 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
809 if (dev_priv
->hotplug
.dp_wq
== NULL
)
815 destroy_workqueue(dev_priv
->wq
);
817 DRM_ERROR("Failed to allocate workqueues.\n");
822 static void i915_engines_cleanup(struct drm_i915_private
*i915
)
824 struct intel_engine_cs
*engine
;
825 enum intel_engine_id id
;
827 for_each_engine(engine
, i915
, id
)
831 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
833 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
834 destroy_workqueue(dev_priv
->wq
);
838 * We don't keep the workarounds for pre-production hardware, so we expect our
839 * driver to fail on these machines in one way or another. A little warning on
840 * dmesg may help both the user and the bug triagers.
842 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
846 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
847 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
848 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
851 DRM_ERROR("This is a pre-production stepping. "
852 "It may not be fully functional.\n");
853 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
858 * i915_driver_init_early - setup state not requiring device access
859 * @dev_priv: device private
861 * Initialize everything that is a "SW-only" state, that is state not
862 * requiring accessing the device or exposing the driver via kernel internal
863 * or userspace interfaces. Example steps belonging here: lock initialization,
864 * system memory allocation, setting up device specific attributes and
865 * function hooks not requiring accessing the device.
867 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
868 const struct pci_device_id
*ent
)
870 const struct intel_device_info
*match_info
=
871 (struct intel_device_info
*)ent
->driver_data
;
872 struct intel_device_info
*device_info
;
875 if (i915_inject_load_failure())
878 /* Setup the write-once "constant" device info */
879 device_info
= mkwrite_device_info(dev_priv
);
880 memcpy(device_info
, match_info
, sizeof(*device_info
));
881 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
883 BUILD_BUG_ON(INTEL_MAX_PLATFORMS
>
884 sizeof(device_info
->platform_mask
) * BITS_PER_BYTE
);
885 device_info
->platform_mask
= BIT(device_info
->platform
);
887 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
888 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
890 spin_lock_init(&dev_priv
->irq_lock
);
891 spin_lock_init(&dev_priv
->gpu_error
.lock
);
892 mutex_init(&dev_priv
->backlight_lock
);
893 spin_lock_init(&dev_priv
->uncore
.lock
);
895 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
896 mutex_init(&dev_priv
->sb_lock
);
897 mutex_init(&dev_priv
->modeset_restore_lock
);
898 mutex_init(&dev_priv
->av_mutex
);
899 mutex_init(&dev_priv
->wm
.wm_mutex
);
900 mutex_init(&dev_priv
->pps_mutex
);
902 intel_uc_init_early(dev_priv
);
903 i915_memcpy_init_early(dev_priv
);
905 ret
= i915_workqueues_init(dev_priv
);
909 /* This must be called before any calls to HAS_PCH_* */
910 intel_detect_pch(dev_priv
);
912 intel_pm_setup(dev_priv
);
913 intel_init_dpio(dev_priv
);
914 intel_power_domains_init(dev_priv
);
915 intel_irq_init(dev_priv
);
916 intel_hangcheck_init(dev_priv
);
917 intel_init_display_hooks(dev_priv
);
918 intel_init_clock_gating_hooks(dev_priv
);
919 intel_init_audio_hooks(dev_priv
);
920 ret
= i915_gem_load_init(dev_priv
);
924 intel_display_crc_init(dev_priv
);
926 intel_device_info_dump(dev_priv
);
928 intel_detect_preproduction_hw(dev_priv
);
930 i915_perf_init(dev_priv
);
935 intel_irq_fini(dev_priv
);
936 i915_workqueues_cleanup(dev_priv
);
938 i915_engines_cleanup(dev_priv
);
943 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
944 * @dev_priv: device private
946 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
948 i915_perf_fini(dev_priv
);
949 i915_gem_load_cleanup(dev_priv
);
950 intel_irq_fini(dev_priv
);
951 i915_workqueues_cleanup(dev_priv
);
952 i915_engines_cleanup(dev_priv
);
955 static int i915_mmio_setup(struct drm_i915_private
*dev_priv
)
957 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
961 mmio_bar
= IS_GEN2(dev_priv
) ? 1 : 0;
963 * Before gen4, the registers and the GTT are behind different BARs.
964 * However, from gen4 onwards, the registers and the GTT are shared
965 * in the same BAR, so we want to restrict this ioremap from
966 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
967 * the register BAR remains the same size for all the earlier
968 * generations up to Ironlake.
970 if (INTEL_GEN(dev_priv
) < 5)
971 mmio_size
= 512 * 1024;
973 mmio_size
= 2 * 1024 * 1024;
974 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
975 if (dev_priv
->regs
== NULL
) {
976 DRM_ERROR("failed to map registers\n");
981 /* Try to make sure MCHBAR is enabled before poking at it */
982 intel_setup_mchbar(dev_priv
);
987 static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv
)
989 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
991 intel_teardown_mchbar(dev_priv
);
992 pci_iounmap(pdev
, dev_priv
->regs
);
996 * i915_driver_init_mmio - setup device MMIO
997 * @dev_priv: device private
999 * Setup minimal device state necessary for MMIO accesses later in the
1000 * initialization sequence. The setup here should avoid any other device-wide
1001 * side effects or exposing the driver via kernel internal or user space
1004 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
1008 if (i915_inject_load_failure())
1011 if (i915_get_bridge_dev(dev_priv
))
1014 ret
= i915_mmio_setup(dev_priv
);
1018 intel_uncore_init(dev_priv
);
1020 intel_uc_init_mmio(dev_priv
);
1022 ret
= intel_engines_init_mmio(dev_priv
);
1026 i915_gem_init_mmio(dev_priv
);
1031 intel_uncore_fini(dev_priv
);
1033 pci_dev_put(dev_priv
->bridge_dev
);
1039 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1040 * @dev_priv: device private
1042 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
1044 intel_uncore_fini(dev_priv
);
1045 i915_mmio_cleanup(dev_priv
);
1046 pci_dev_put(dev_priv
->bridge_dev
);
1049 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
1051 i915_modparams
.enable_execlists
=
1052 intel_sanitize_enable_execlists(dev_priv
,
1053 i915_modparams
.enable_execlists
);
1056 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1057 * user's requested state against the hardware/driver capabilities. We
1058 * do this now so that we can print out any log messages once rather
1059 * than every time we check intel_enable_ppgtt().
1061 i915_modparams
.enable_ppgtt
=
1062 intel_sanitize_enable_ppgtt(dev_priv
,
1063 i915_modparams
.enable_ppgtt
);
1064 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams
.enable_ppgtt
);
1066 i915_modparams
.semaphores
=
1067 intel_sanitize_semaphores(dev_priv
, i915_modparams
.semaphores
);
1068 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1069 yesno(i915_modparams
.semaphores
));
1071 intel_uc_sanitize_options(dev_priv
);
1073 intel_gvt_sanitize_options(dev_priv
);
1077 * i915_driver_init_hw - setup state requiring device access
1078 * @dev_priv: device private
1080 * Setup state that requires accessing the device, but doesn't require
1081 * exposing the driver via kernel internal or userspace interfaces.
1083 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1085 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1088 if (i915_inject_load_failure())
1091 intel_device_info_runtime_init(dev_priv
);
1093 intel_sanitize_options(dev_priv
);
1095 ret
= i915_ggtt_probe_hw(dev_priv
);
1099 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1100 * otherwise the vga fbdev driver falls over. */
1101 ret
= i915_kick_out_firmware_fb(dev_priv
);
1103 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1107 ret
= i915_kick_out_vgacon(dev_priv
);
1109 DRM_ERROR("failed to remove conflicting VGA console\n");
1113 ret
= i915_ggtt_init_hw(dev_priv
);
1117 ret
= i915_ggtt_enable_hw(dev_priv
);
1119 DRM_ERROR("failed to enable GGTT\n");
1123 pci_set_master(pdev
);
1125 /* overlay on gen2 is broken and can't address above 1G */
1126 if (IS_GEN2(dev_priv
)) {
1127 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1129 DRM_ERROR("failed to set DMA mask\n");
1135 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1136 * using 32bit addressing, overwriting memory if HWS is located
1139 * The documentation also mentions an issue with undefined
1140 * behaviour if any general state is accessed within a page above 4GB,
1141 * which also needs to be handled carefully.
1143 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1144 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1147 DRM_ERROR("failed to set DMA mask\n");
1153 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1154 PM_QOS_DEFAULT_VALUE
);
1156 intel_uncore_sanitize(dev_priv
);
1158 intel_opregion_setup(dev_priv
);
1160 i915_gem_load_init_fences(dev_priv
);
1162 /* On the 945G/GM, the chipset reports the MSI capability on the
1163 * integrated graphics even though the support isn't actually there
1164 * according to the published specs. It doesn't appear to function
1165 * correctly in testing on 945G.
1166 * This may be a side effect of MSI having been made available for PEG
1167 * and the registers being closely associated.
1169 * According to chipset errata, on the 965GM, MSI interrupts may
1170 * be lost or delayed, and was defeatured. MSI interrupts seem to
1171 * get lost on g4x as well, and interrupt delivery seems to stay
1172 * properly dead afterwards. So we'll just disable them for all
1173 * pre-gen5 chipsets.
1175 if (INTEL_GEN(dev_priv
) >= 5) {
1176 if (pci_enable_msi(pdev
) < 0)
1177 DRM_DEBUG_DRIVER("can't enable MSI");
1180 ret
= intel_gvt_init(dev_priv
);
1187 i915_ggtt_cleanup_hw(dev_priv
);
1193 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1194 * @dev_priv: device private
1196 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1198 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1200 if (pdev
->msi_enabled
)
1201 pci_disable_msi(pdev
);
1203 pm_qos_remove_request(&dev_priv
->pm_qos
);
1204 i915_ggtt_cleanup_hw(dev_priv
);
1208 * i915_driver_register - register the driver with the rest of the system
1209 * @dev_priv: device private
1211 * Perform any steps necessary to make the driver available via kernel
1212 * internal or userspace interfaces.
1214 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1216 struct drm_device
*dev
= &dev_priv
->drm
;
1218 i915_gem_shrinker_init(dev_priv
);
1221 * Notify a valid surface after modesetting,
1222 * when running inside a VM.
1224 if (intel_vgpu_active(dev_priv
))
1225 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1227 /* Reveal our presence to userspace */
1228 if (drm_dev_register(dev
, 0) == 0) {
1229 i915_debugfs_register(dev_priv
);
1230 i915_guc_log_register(dev_priv
);
1231 i915_setup_sysfs(dev_priv
);
1233 /* Depends on sysfs having been initialized */
1234 i915_perf_register(dev_priv
);
1236 DRM_ERROR("Failed to register driver for userspace access!\n");
1238 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1239 /* Must be done after probing outputs */
1240 intel_opregion_register(dev_priv
);
1241 acpi_video_register();
1244 if (IS_GEN5(dev_priv
))
1245 intel_gpu_ips_init(dev_priv
);
1247 intel_audio_init(dev_priv
);
1250 * Some ports require correctly set-up hpd registers for detection to
1251 * work properly (leading to ghost connected connector status), e.g. VGA
1252 * on gm45. Hence we can only set up the initial fbdev config after hpd
1253 * irqs are fully enabled. We do it last so that the async config
1254 * cannot run before the connectors are registered.
1256 intel_fbdev_initial_config_async(dev
);
1260 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1261 * @dev_priv: device private
1263 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1265 intel_fbdev_unregister(dev_priv
);
1266 intel_audio_deinit(dev_priv
);
1268 intel_gpu_ips_teardown();
1269 acpi_video_unregister();
1270 intel_opregion_unregister(dev_priv
);
1272 i915_perf_unregister(dev_priv
);
1274 i915_teardown_sysfs(dev_priv
);
1275 i915_guc_log_unregister(dev_priv
);
1276 drm_dev_unregister(&dev_priv
->drm
);
1278 i915_gem_shrinker_cleanup(dev_priv
);
1282 * i915_driver_load - setup chip and create an initial config
1284 * @ent: matching PCI ID entry
1286 * The driver load routine has to do several things:
1287 * - drive output discovery via intel_modeset_init()
1288 * - initialize the memory manager
1289 * - allocate initial config memory
1290 * - setup the DRM framebuffer with the allocated memory
1292 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1294 const struct intel_device_info
*match_info
=
1295 (struct intel_device_info
*)ent
->driver_data
;
1296 struct drm_i915_private
*dev_priv
;
1299 /* Enable nuclear pageflip on ILK+ */
1300 if (!i915_modparams
.nuclear_pageflip
&& match_info
->gen
< 5)
1301 driver
.driver_features
&= ~DRIVER_ATOMIC
;
1304 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1306 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1308 DRM_DEV_ERROR(&pdev
->dev
, "allocation failed\n");
1312 dev_priv
->drm
.pdev
= pdev
;
1313 dev_priv
->drm
.dev_private
= dev_priv
;
1315 ret
= pci_enable_device(pdev
);
1319 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1321 * Disable the system suspend direct complete optimization, which can
1322 * leave the device suspended skipping the driver's suspend handlers
1323 * if the device was already runtime suspended. This is needed due to
1324 * the difference in our runtime and system suspend sequence and
1325 * becaue the HDA driver may require us to enable the audio power
1326 * domain during system suspend.
1328 dev_pm_set_driver_flags(&pdev
->dev
, DPM_FLAG_NEVER_SKIP
);
1330 ret
= i915_driver_init_early(dev_priv
, ent
);
1332 goto out_pci_disable
;
1334 intel_runtime_pm_get(dev_priv
);
1336 ret
= i915_driver_init_mmio(dev_priv
);
1338 goto out_runtime_pm_put
;
1340 ret
= i915_driver_init_hw(dev_priv
);
1342 goto out_cleanup_mmio
;
1345 * TODO: move the vblank init and parts of modeset init steps into one
1346 * of the i915_driver_init_/i915_driver_register functions according
1347 * to the role/effect of the given init step.
1349 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1350 ret
= drm_vblank_init(&dev_priv
->drm
,
1351 INTEL_INFO(dev_priv
)->num_pipes
);
1353 goto out_cleanup_hw
;
1356 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1358 goto out_cleanup_hw
;
1360 i915_driver_register(dev_priv
);
1362 intel_runtime_pm_enable(dev_priv
);
1364 intel_init_ipc(dev_priv
);
1366 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1367 DRM_INFO("DRM_I915_DEBUG enabled\n");
1368 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1369 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1371 intel_runtime_pm_put(dev_priv
);
1376 i915_driver_cleanup_hw(dev_priv
);
1378 i915_driver_cleanup_mmio(dev_priv
);
1380 intel_runtime_pm_put(dev_priv
);
1381 i915_driver_cleanup_early(dev_priv
);
1383 pci_disable_device(pdev
);
1385 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1386 drm_dev_fini(&dev_priv
->drm
);
1392 void i915_driver_unload(struct drm_device
*dev
)
1394 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1395 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1397 i915_driver_unregister(dev_priv
);
1399 if (i915_gem_suspend(dev_priv
))
1400 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1402 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1404 drm_atomic_helper_shutdown(dev
);
1406 intel_gvt_cleanup(dev_priv
);
1408 intel_modeset_cleanup(dev
);
1411 * free the memory space allocated for the child device
1412 * config parsed from VBT
1414 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1415 kfree(dev_priv
->vbt
.child_dev
);
1416 dev_priv
->vbt
.child_dev
= NULL
;
1417 dev_priv
->vbt
.child_dev_num
= 0;
1419 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1420 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1421 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1422 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1424 vga_switcheroo_unregister_client(pdev
);
1425 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1427 intel_csr_ucode_fini(dev_priv
);
1429 /* Free error state after interrupts are fully disabled. */
1430 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1431 i915_reset_error_state(dev_priv
);
1433 i915_gem_fini(dev_priv
);
1434 intel_uc_fini_fw(dev_priv
);
1435 intel_fbc_cleanup_cfb(dev_priv
);
1437 intel_power_domains_fini(dev_priv
);
1439 i915_driver_cleanup_hw(dev_priv
);
1440 i915_driver_cleanup_mmio(dev_priv
);
1442 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1445 static void i915_driver_release(struct drm_device
*dev
)
1447 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1449 i915_driver_cleanup_early(dev_priv
);
1450 drm_dev_fini(&dev_priv
->drm
);
1455 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1457 struct drm_i915_private
*i915
= to_i915(dev
);
1460 ret
= i915_gem_open(i915
, file
);
1468 * i915_driver_lastclose - clean up after all DRM clients have exited
1471 * Take care of cleaning up after all DRM clients have exited. In the
1472 * mode setting case, we want to restore the kernel's initial mode (just
1473 * in case the last client left us in a bad state).
1475 * Additionally, in the non-mode setting case, we'll tear down the GTT
1476 * and DMA structures, since the kernel won't be using them, and clea
1479 static void i915_driver_lastclose(struct drm_device
*dev
)
1481 intel_fbdev_restore_mode(dev
);
1482 vga_switcheroo_process_delayed_switch();
1485 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1487 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1489 mutex_lock(&dev
->struct_mutex
);
1490 i915_gem_context_close(file
);
1491 i915_gem_release(dev
, file
);
1492 mutex_unlock(&dev
->struct_mutex
);
1497 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1499 struct drm_device
*dev
= &dev_priv
->drm
;
1500 struct intel_encoder
*encoder
;
1502 drm_modeset_lock_all(dev
);
1503 for_each_intel_encoder(dev
, encoder
)
1504 if (encoder
->suspend
)
1505 encoder
->suspend(encoder
);
1506 drm_modeset_unlock_all(dev
);
1509 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1511 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1513 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1515 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1516 if (acpi_target_system_state() < ACPI_STATE_S3
)
1522 static int i915_drm_suspend(struct drm_device
*dev
)
1524 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1525 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1526 pci_power_t opregion_target_state
;
1529 /* ignore lid events during suspend */
1530 mutex_lock(&dev_priv
->modeset_restore_lock
);
1531 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
1532 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1534 disable_rpm_wakeref_asserts(dev_priv
);
1536 /* We do a lot of poking in a lot of registers, make sure they work
1538 intel_display_set_init_power(dev_priv
, true);
1540 drm_kms_helper_poll_disable(dev
);
1542 pci_save_state(pdev
);
1544 error
= i915_gem_suspend(dev_priv
);
1547 "GEM idle failed, resume might fail\n");
1551 intel_display_suspend(dev
);
1553 intel_dp_mst_suspend(dev
);
1555 intel_runtime_pm_disable_interrupts(dev_priv
);
1556 intel_hpd_cancel_work(dev_priv
);
1558 intel_suspend_encoders(dev_priv
);
1560 intel_suspend_hw(dev_priv
);
1562 i915_gem_suspend_gtt_mappings(dev_priv
);
1564 i915_save_state(dev_priv
);
1566 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1567 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1569 intel_uncore_suspend(dev_priv
);
1570 intel_opregion_unregister(dev_priv
);
1572 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1574 dev_priv
->suspend_count
++;
1576 intel_csr_ucode_suspend(dev_priv
);
1579 enable_rpm_wakeref_asserts(dev_priv
);
1584 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1586 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1587 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1591 disable_rpm_wakeref_asserts(dev_priv
);
1593 intel_display_set_init_power(dev_priv
, false);
1595 fw_csr
= !IS_GEN9_LP(dev_priv
) && !hibernation
&&
1596 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1598 * In case of firmware assisted context save/restore don't manually
1599 * deinit the power domains. This also means the CSR/DMC firmware will
1600 * stay active, it will power down any HW resources as required and
1601 * also enable deeper system power states that would be blocked if the
1602 * firmware was inactive.
1605 intel_power_domains_suspend(dev_priv
);
1608 if (IS_GEN9_LP(dev_priv
))
1609 bxt_enable_dc9(dev_priv
);
1610 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1611 hsw_enable_pc8(dev_priv
);
1612 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1613 ret
= vlv_suspend_complete(dev_priv
);
1616 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1618 intel_power_domains_init_hw(dev_priv
, true);
1623 pci_disable_device(pdev
);
1625 * During hibernation on some platforms the BIOS may try to access
1626 * the device even though it's already in D3 and hang the machine. So
1627 * leave the device in D0 on those platforms and hope the BIOS will
1628 * power down the device properly. The issue was seen on multiple old
1629 * GENs with different BIOS vendors, so having an explicit blacklist
1630 * is inpractical; apply the workaround on everything pre GEN6. The
1631 * platforms where the issue was seen:
1632 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1636 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1637 pci_set_power_state(pdev
, PCI_D3hot
);
1639 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1642 enable_rpm_wakeref_asserts(dev_priv
);
1647 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1652 DRM_ERROR("dev: %p\n", dev
);
1653 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1657 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1658 state
.event
!= PM_EVENT_FREEZE
))
1661 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1664 error
= i915_drm_suspend(dev
);
1668 return i915_drm_suspend_late(dev
, false);
1671 static int i915_drm_resume(struct drm_device
*dev
)
1673 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1676 disable_rpm_wakeref_asserts(dev_priv
);
1677 intel_sanitize_gt_powersave(dev_priv
);
1679 ret
= i915_ggtt_enable_hw(dev_priv
);
1681 DRM_ERROR("failed to re-enable GGTT\n");
1683 intel_csr_ucode_resume(dev_priv
);
1685 i915_gem_resume(dev_priv
);
1687 i915_restore_state(dev_priv
);
1688 intel_pps_unlock_regs_wa(dev_priv
);
1689 intel_opregion_setup(dev_priv
);
1691 intel_init_pch_refclk(dev_priv
);
1694 * Interrupts have to be enabled before any batches are run. If not the
1695 * GPU will hang. i915_gem_init_hw() will initiate batches to
1696 * update/restore the context.
1698 * drm_mode_config_reset() needs AUX interrupts.
1700 * Modeset enabling in intel_modeset_init_hw() also needs working
1703 intel_runtime_pm_enable_interrupts(dev_priv
);
1705 drm_mode_config_reset(dev
);
1707 mutex_lock(&dev
->struct_mutex
);
1708 if (i915_gem_init_hw(dev_priv
)) {
1709 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1710 i915_gem_set_wedged(dev_priv
);
1712 mutex_unlock(&dev
->struct_mutex
);
1714 intel_guc_resume(dev_priv
);
1716 intel_modeset_init_hw(dev
);
1718 spin_lock_irq(&dev_priv
->irq_lock
);
1719 if (dev_priv
->display
.hpd_irq_setup
)
1720 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1721 spin_unlock_irq(&dev_priv
->irq_lock
);
1723 intel_dp_mst_resume(dev
);
1725 intel_display_resume(dev
);
1727 drm_kms_helper_poll_enable(dev
);
1730 * ... but also need to make sure that hotplug processing
1731 * doesn't cause havoc. Like in the driver load code we don't
1732 * bother with the tiny race here where we might loose hotplug
1735 intel_hpd_init(dev_priv
);
1737 intel_opregion_register(dev_priv
);
1739 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1741 mutex_lock(&dev_priv
->modeset_restore_lock
);
1742 dev_priv
->modeset_restore
= MODESET_DONE
;
1743 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1745 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1747 intel_autoenable_gt_powersave(dev_priv
);
1749 enable_rpm_wakeref_asserts(dev_priv
);
1754 static int i915_drm_resume_early(struct drm_device
*dev
)
1756 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1757 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1761 * We have a resume ordering issue with the snd-hda driver also
1762 * requiring our device to be power up. Due to the lack of a
1763 * parent/child relationship we currently solve this with an early
1766 * FIXME: This should be solved with a special hdmi sink device or
1767 * similar so that power domains can be employed.
1771 * Note that we need to set the power state explicitly, since we
1772 * powered off the device during freeze and the PCI core won't power
1773 * it back up for us during thaw. Powering off the device during
1774 * freeze is not a hard requirement though, and during the
1775 * suspend/resume phases the PCI core makes sure we get here with the
1776 * device powered on. So in case we change our freeze logic and keep
1777 * the device powered we can also remove the following set power state
1780 ret
= pci_set_power_state(pdev
, PCI_D0
);
1782 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1787 * Note that pci_enable_device() first enables any parent bridge
1788 * device and only then sets the power state for this device. The
1789 * bridge enabling is a nop though, since bridge devices are resumed
1790 * first. The order of enabling power and enabling the device is
1791 * imposed by the PCI core as described above, so here we preserve the
1792 * same order for the freeze/thaw phases.
1794 * TODO: eventually we should remove pci_disable_device() /
1795 * pci_enable_enable_device() from suspend/resume. Due to how they
1796 * depend on the device enable refcount we can't anyway depend on them
1797 * disabling/enabling the device.
1799 if (pci_enable_device(pdev
)) {
1804 pci_set_master(pdev
);
1806 disable_rpm_wakeref_asserts(dev_priv
);
1808 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1809 ret
= vlv_resume_prepare(dev_priv
, false);
1811 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1814 intel_uncore_resume_early(dev_priv
);
1816 if (IS_GEN9_LP(dev_priv
)) {
1817 if (!dev_priv
->suspended_to_idle
)
1818 gen9_sanitize_dc_state(dev_priv
);
1819 bxt_disable_dc9(dev_priv
);
1820 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1821 hsw_disable_pc8(dev_priv
);
1824 intel_uncore_sanitize(dev_priv
);
1826 if (IS_GEN9_LP(dev_priv
) ||
1827 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1828 intel_power_domains_init_hw(dev_priv
, true);
1830 i915_gem_sanitize(dev_priv
);
1832 enable_rpm_wakeref_asserts(dev_priv
);
1835 dev_priv
->suspended_to_idle
= false;
1840 static int i915_resume_switcheroo(struct drm_device
*dev
)
1844 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1847 ret
= i915_drm_resume_early(dev
);
1851 return i915_drm_resume(dev
);
1855 * i915_reset - reset chip after a hang
1856 * @i915: #drm_i915_private to reset
1857 * @flags: Instructions
1859 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1862 * Caller must hold the struct_mutex.
1864 * Procedure is fairly simple:
1865 * - reset the chip using the reset reg
1866 * - re-init context state
1867 * - re-init hardware status page
1868 * - re-init ring buffer
1869 * - re-init interrupt state
1872 void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
)
1874 struct i915_gpu_error
*error
= &i915
->gpu_error
;
1877 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1878 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF
, &error
->flags
));
1880 if (!test_bit(I915_RESET_HANDOFF
, &error
->flags
))
1883 /* Clear any previous failed attempts at recovery. Time to try again. */
1884 if (!i915_gem_unset_wedged(i915
))
1887 if (!(flags
& I915_RESET_QUIET
))
1888 dev_notice(i915
->drm
.dev
, "Resetting chip after gpu hang\n");
1889 error
->reset_count
++;
1891 disable_irq(i915
->drm
.irq
);
1892 ret
= i915_gem_reset_prepare(i915
);
1894 DRM_ERROR("GPU recovery failed\n");
1895 intel_gpu_reset(i915
, ALL_ENGINES
);
1899 ret
= intel_gpu_reset(i915
, ALL_ENGINES
);
1902 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1904 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1908 i915_gem_reset(i915
);
1909 intel_overlay_reset(i915
);
1911 /* Ok, now get things going again... */
1914 * Everything depends on having the GTT running, so we need to start
1917 ret
= i915_ggtt_enable_hw(i915
);
1919 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret
);
1924 * Next we need to restore the context, but we don't use those
1927 * Ring buffer needs to be re-initialized in the KMS case, or if X
1928 * was running at the time of the reset (i.e. we weren't VT
1931 ret
= i915_gem_init_hw(i915
);
1933 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1937 i915_queue_hangcheck(i915
);
1940 i915_gem_reset_finish(i915
);
1941 enable_irq(i915
->drm
.irq
);
1944 clear_bit(I915_RESET_HANDOFF
, &error
->flags
);
1945 wake_up_bit(&error
->flags
, I915_RESET_HANDOFF
);
1949 i915_gem_set_wedged(i915
);
1950 i915_gem_retire_requests(i915
);
1955 * i915_reset_engine - reset GPU engine to recover from a hang
1956 * @engine: engine to reset
1959 * Reset a specific GPU engine. Useful if a hang is detected.
1960 * Returns zero on successful reset or otherwise an error code.
1963 * - identifies the request that caused the hang and it is dropped
1964 * - reset engine (which will force the engine to idle)
1965 * - re-init/configure engine
1967 int i915_reset_engine(struct intel_engine_cs
*engine
, unsigned int flags
)
1969 struct i915_gpu_error
*error
= &engine
->i915
->gpu_error
;
1970 struct drm_i915_gem_request
*active_request
;
1973 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE
+ engine
->id
, &error
->flags
));
1975 if (!(flags
& I915_RESET_QUIET
)) {
1976 dev_notice(engine
->i915
->drm
.dev
,
1977 "Resetting %s after gpu hang\n", engine
->name
);
1979 error
->reset_engine_count
[engine
->id
]++;
1981 active_request
= i915_gem_reset_prepare_engine(engine
);
1982 if (IS_ERR(active_request
)) {
1983 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1984 ret
= PTR_ERR(active_request
);
1988 ret
= intel_gpu_reset(engine
->i915
, intel_engine_flag(engine
));
1990 /* If we fail here, we expect to fallback to a global reset */
1991 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1997 * The request that caused the hang is stuck on elsp, we know the
1998 * active request and can drop it, adjust head to skip the offending
1999 * request to resume executing remaining requests in the queue.
2001 i915_gem_reset_engine(engine
, active_request
);
2004 * The engine and its registers (and workarounds in case of render)
2005 * have been reset to their default values. Follow the init_ring
2006 * process to program RING_MODE, HWSP and re-enable submission.
2008 ret
= engine
->init_hw(engine
);
2013 i915_gem_reset_finish_engine(engine
);
2017 static int i915_pm_suspend(struct device
*kdev
)
2019 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2020 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2023 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
2027 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2030 return i915_drm_suspend(dev
);
2033 static int i915_pm_suspend_late(struct device
*kdev
)
2035 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2038 * We have a suspend ordering issue with the snd-hda driver also
2039 * requiring our device to be power up. Due to the lack of a
2040 * parent/child relationship we currently solve this with an late
2043 * FIXME: This should be solved with a special hdmi sink device or
2044 * similar so that power domains can be employed.
2046 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2049 return i915_drm_suspend_late(dev
, false);
2052 static int i915_pm_poweroff_late(struct device
*kdev
)
2054 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2056 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2059 return i915_drm_suspend_late(dev
, true);
2062 static int i915_pm_resume_early(struct device
*kdev
)
2064 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2066 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2069 return i915_drm_resume_early(dev
);
2072 static int i915_pm_resume(struct device
*kdev
)
2074 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2076 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2079 return i915_drm_resume(dev
);
2082 /* freeze: before creating the hibernation_image */
2083 static int i915_pm_freeze(struct device
*kdev
)
2085 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2088 if (dev
->switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2089 ret
= i915_drm_suspend(dev
);
2094 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
2101 static int i915_pm_freeze_late(struct device
*kdev
)
2103 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2106 if (dev
->switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2107 ret
= i915_drm_suspend_late(dev
, true);
2112 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
2119 /* thaw: called after creating the hibernation image, but before turning off. */
2120 static int i915_pm_thaw_early(struct device
*kdev
)
2122 return i915_pm_resume_early(kdev
);
2125 static int i915_pm_thaw(struct device
*kdev
)
2127 return i915_pm_resume(kdev
);
2130 /* restore: called after loading the hibernation image. */
2131 static int i915_pm_restore_early(struct device
*kdev
)
2133 return i915_pm_resume_early(kdev
);
2136 static int i915_pm_restore(struct device
*kdev
)
2138 return i915_pm_resume(kdev
);
2142 * Save all Gunit registers that may be lost after a D3 and a subsequent
2143 * S0i[R123] transition. The list of registers needing a save/restore is
2144 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2145 * registers in the following way:
2146 * - Driver: saved/restored by the driver
2147 * - Punit : saved/restored by the Punit firmware
2148 * - No, w/o marking: no need to save/restore, since the register is R/O or
2149 * used internally by the HW in a way that doesn't depend
2150 * keeping the content across a suspend/resume.
2151 * - Debug : used for debugging
2153 * We save/restore all registers marked with 'Driver', with the following
2155 * - Registers out of use, including also registers marked with 'Debug'.
2156 * These have no effect on the driver's operation, so we don't save/restore
2157 * them to reduce the overhead.
2158 * - Registers that are fully setup by an initialization function called from
2159 * the resume path. For example many clock gating and RPS/RC6 registers.
2160 * - Registers that provide the right functionality with their reset defaults.
2162 * TODO: Except for registers that based on the above 3 criteria can be safely
2163 * ignored, we save/restore all others, practically treating the HW context as
2164 * a black-box for the driver. Further investigation is needed to reduce the
2165 * saved/restored registers even further, by following the same 3 criteria.
2167 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2169 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2172 /* GAM 0x4000-0x4770 */
2173 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2174 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2175 s
->arb_mode
= I915_READ(ARB_MODE
);
2176 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2177 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2179 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2180 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2182 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2183 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2185 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2186 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2187 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2188 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2190 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2192 /* MBC 0x9024-0x91D0, 0x8500 */
2193 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2194 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2195 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2197 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2198 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2199 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2200 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2201 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2202 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2203 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2205 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2206 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2207 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2208 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2209 s
->ecobus
= I915_READ(ECOBUS
);
2210 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2211 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2212 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2213 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2214 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2215 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2217 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2218 s
->gt_imr
= I915_READ(GTIMR
);
2219 s
->gt_ier
= I915_READ(GTIER
);
2220 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2221 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2223 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2224 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2226 /* GT SA CZ domain, 0x100000-0x138124 */
2227 s
->tilectl
= I915_READ(TILECTL
);
2228 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2229 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2230 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2231 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2233 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2234 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2235 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2236 s
->pcbr
= I915_READ(VLV_PCBR
);
2237 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2240 * Not saving any of:
2241 * DFT, 0x9800-0x9EC0
2242 * SARB, 0xB000-0xB1FC
2243 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2248 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2250 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2254 /* GAM 0x4000-0x4770 */
2255 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2256 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2257 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2258 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2259 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2261 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2262 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2264 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2265 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2267 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2268 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2269 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2270 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2272 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2274 /* MBC 0x9024-0x91D0, 0x8500 */
2275 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2276 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2277 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2279 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2280 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2281 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2282 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2283 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2284 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2285 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2287 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2288 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2289 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2290 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2291 I915_WRITE(ECOBUS
, s
->ecobus
);
2292 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2293 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2294 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2295 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2296 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2297 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2299 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2300 I915_WRITE(GTIMR
, s
->gt_imr
);
2301 I915_WRITE(GTIER
, s
->gt_ier
);
2302 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2303 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2305 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2306 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2308 /* GT SA CZ domain, 0x100000-0x138124 */
2309 I915_WRITE(TILECTL
, s
->tilectl
);
2310 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2312 * Preserve the GT allow wake and GFX force clock bit, they are not
2313 * be restored, as they are used to control the s0ix suspend/resume
2314 * sequence by the caller.
2316 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2317 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2318 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2319 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2321 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2322 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2323 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2324 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2326 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2328 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2329 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2330 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2331 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2332 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2335 static int vlv_wait_for_pw_status(struct drm_i915_private
*dev_priv
,
2338 /* The HW does not like us polling for PW_STATUS frequently, so
2339 * use the sleeping loop rather than risk the busy spin within
2340 * intel_wait_for_register().
2342 * Transitioning between RC6 states should be at most 2ms (see
2343 * valleyview_enable_rps) so use a 3ms timeout.
2345 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS
) & mask
) == val
,
2349 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2354 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2355 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2357 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2358 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2363 err
= intel_wait_for_register(dev_priv
,
2364 VLV_GTLC_SURVIVABILITY_REG
,
2365 VLV_GFX_CLK_STATUS_BIT
,
2366 VLV_GFX_CLK_STATUS_BIT
,
2369 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2370 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2375 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2381 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2382 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2384 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2385 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2386 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2388 mask
= VLV_GTLC_ALLOWWAKEACK
;
2389 val
= allow
? mask
: 0;
2391 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2393 DRM_ERROR("timeout disabling GT waking\n");
2398 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2404 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2405 val
= wait_for_on
? mask
: 0;
2408 * RC6 transitioning can be delayed up to 2 msec (see
2409 * valleyview_enable_rps), use 3 msec for safety.
2411 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2412 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2413 onoff(wait_for_on
));
2416 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2418 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2421 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2422 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2425 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2431 * Bspec defines the following GT well on flags as debug only, so
2432 * don't treat them as hard failures.
2434 vlv_wait_for_gt_wells(dev_priv
, false);
2436 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2437 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2439 vlv_check_no_gt_access(dev_priv
);
2441 err
= vlv_force_gfx_clock(dev_priv
, true);
2445 err
= vlv_allow_gt_wake(dev_priv
, false);
2449 if (!IS_CHERRYVIEW(dev_priv
))
2450 vlv_save_gunit_s0ix_state(dev_priv
);
2452 err
= vlv_force_gfx_clock(dev_priv
, false);
2459 /* For safety always re-enable waking and disable gfx clock forcing */
2460 vlv_allow_gt_wake(dev_priv
, true);
2462 vlv_force_gfx_clock(dev_priv
, false);
2467 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2474 * If any of the steps fail just try to continue, that's the best we
2475 * can do at this point. Return the first error code (which will also
2476 * leave RPM permanently disabled).
2478 ret
= vlv_force_gfx_clock(dev_priv
, true);
2480 if (!IS_CHERRYVIEW(dev_priv
))
2481 vlv_restore_gunit_s0ix_state(dev_priv
);
2483 err
= vlv_allow_gt_wake(dev_priv
, true);
2487 err
= vlv_force_gfx_clock(dev_priv
, false);
2491 vlv_check_no_gt_access(dev_priv
);
2494 intel_init_clock_gating(dev_priv
);
2499 static int intel_runtime_suspend(struct device
*kdev
)
2501 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2502 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2503 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2506 if (WARN_ON_ONCE(!(dev_priv
->gt_pm
.rc6
.enabled
&& intel_rc6_enabled())))
2509 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2512 DRM_DEBUG_KMS("Suspending device\n");
2514 disable_rpm_wakeref_asserts(dev_priv
);
2517 * We are safe here against re-faults, since the fault handler takes
2520 i915_gem_runtime_suspend(dev_priv
);
2522 intel_guc_suspend(dev_priv
);
2524 intel_runtime_pm_disable_interrupts(dev_priv
);
2527 if (IS_GEN9_LP(dev_priv
)) {
2528 bxt_display_core_uninit(dev_priv
);
2529 bxt_enable_dc9(dev_priv
);
2530 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2531 hsw_enable_pc8(dev_priv
);
2532 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2533 ret
= vlv_suspend_complete(dev_priv
);
2537 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2538 intel_runtime_pm_enable_interrupts(dev_priv
);
2540 enable_rpm_wakeref_asserts(dev_priv
);
2545 intel_uncore_suspend(dev_priv
);
2547 enable_rpm_wakeref_asserts(dev_priv
);
2548 WARN_ON_ONCE(atomic_read(&dev_priv
->runtime_pm
.wakeref_count
));
2550 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2551 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2553 dev_priv
->runtime_pm
.suspended
= true;
2556 * FIXME: We really should find a document that references the arguments
2559 if (IS_BROADWELL(dev_priv
)) {
2561 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2562 * being detected, and the call we do at intel_runtime_resume()
2563 * won't be able to restore them. Since PCI_D3hot matches the
2564 * actual specification and appears to be working, use it.
2566 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2569 * current versions of firmware which depend on this opregion
2570 * notification have repurposed the D1 definition to mean
2571 * "runtime suspended" vs. what you would normally expect (D3)
2572 * to distinguish it from notifications that might be sent via
2575 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2578 assert_forcewakes_inactive(dev_priv
);
2580 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2581 intel_hpd_poll_init(dev_priv
);
2583 DRM_DEBUG_KMS("Device suspended\n");
2587 static int intel_runtime_resume(struct device
*kdev
)
2589 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2590 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2591 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2594 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2597 DRM_DEBUG_KMS("Resuming device\n");
2599 WARN_ON_ONCE(atomic_read(&dev_priv
->runtime_pm
.wakeref_count
));
2600 disable_rpm_wakeref_asserts(dev_priv
);
2602 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2603 dev_priv
->runtime_pm
.suspended
= false;
2604 if (intel_uncore_unclaimed_mmio(dev_priv
))
2605 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2607 intel_guc_resume(dev_priv
);
2609 if (IS_GEN9_LP(dev_priv
)) {
2610 bxt_disable_dc9(dev_priv
);
2611 bxt_display_core_init(dev_priv
, true);
2612 if (dev_priv
->csr
.dmc_payload
&&
2613 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2614 gen9_enable_dc5(dev_priv
);
2615 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2616 hsw_disable_pc8(dev_priv
);
2617 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2618 ret
= vlv_resume_prepare(dev_priv
, true);
2622 * No point of rolling back things in case of an error, as the best
2623 * we can do is to hope that things will still work (and disable RPM).
2625 i915_gem_init_swizzling(dev_priv
);
2626 i915_gem_restore_fences(dev_priv
);
2628 intel_runtime_pm_enable_interrupts(dev_priv
);
2631 * On VLV/CHV display interrupts are part of the display
2632 * power well, so hpd is reinitialized from there. For
2633 * everyone else do it here.
2635 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2636 intel_hpd_init(dev_priv
);
2638 intel_enable_ipc(dev_priv
);
2640 enable_rpm_wakeref_asserts(dev_priv
);
2643 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2645 DRM_DEBUG_KMS("Device resumed\n");
2650 const struct dev_pm_ops i915_pm_ops
= {
2652 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2655 .suspend
= i915_pm_suspend
,
2656 .suspend_late
= i915_pm_suspend_late
,
2657 .resume_early
= i915_pm_resume_early
,
2658 .resume
= i915_pm_resume
,
2662 * @freeze, @freeze_late : called (1) before creating the
2663 * hibernation image [PMSG_FREEZE] and
2664 * (2) after rebooting, before restoring
2665 * the image [PMSG_QUIESCE]
2666 * @thaw, @thaw_early : called (1) after creating the hibernation
2667 * image, before writing it [PMSG_THAW]
2668 * and (2) after failing to create or
2669 * restore the image [PMSG_RECOVER]
2670 * @poweroff, @poweroff_late: called after writing the hibernation
2671 * image, before rebooting [PMSG_HIBERNATE]
2672 * @restore, @restore_early : called after rebooting and restoring the
2673 * hibernation image [PMSG_RESTORE]
2675 .freeze
= i915_pm_freeze
,
2676 .freeze_late
= i915_pm_freeze_late
,
2677 .thaw_early
= i915_pm_thaw_early
,
2678 .thaw
= i915_pm_thaw
,
2679 .poweroff
= i915_pm_suspend
,
2680 .poweroff_late
= i915_pm_poweroff_late
,
2681 .restore_early
= i915_pm_restore_early
,
2682 .restore
= i915_pm_restore
,
2684 /* S0ix (via runtime suspend) event handlers */
2685 .runtime_suspend
= intel_runtime_suspend
,
2686 .runtime_resume
= intel_runtime_resume
,
2689 static const struct vm_operations_struct i915_gem_vm_ops
= {
2690 .fault
= i915_gem_fault
,
2691 .open
= drm_gem_vm_open
,
2692 .close
= drm_gem_vm_close
,
2695 static const struct file_operations i915_driver_fops
= {
2696 .owner
= THIS_MODULE
,
2698 .release
= drm_release
,
2699 .unlocked_ioctl
= drm_ioctl
,
2700 .mmap
= drm_gem_mmap
,
2703 .compat_ioctl
= i915_compat_ioctl
,
2704 .llseek
= noop_llseek
,
2708 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2709 struct drm_file
*file
)
2714 static const struct drm_ioctl_desc i915_ioctls
[] = {
2715 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2716 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2717 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2718 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2719 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2720 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2721 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2722 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2723 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2724 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2725 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2726 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2727 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2728 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2729 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2730 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2731 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2732 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2733 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2734 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2735 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2736 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2737 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2738 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2739 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2740 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2741 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2742 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2743 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2744 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2745 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2746 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2747 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2748 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2749 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2750 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2751 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2752 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2753 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2754 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2755 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2756 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2757 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2758 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2759 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2760 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2761 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2762 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2763 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2764 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2765 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2766 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2767 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2768 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG
, i915_perf_add_config_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
2769 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG
, i915_perf_remove_config_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
2772 static struct drm_driver driver
= {
2773 /* Don't use MTRRs here; the Xserver or userspace app should
2774 * deal with them for Intel hardware.
2777 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2778 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
| DRIVER_SYNCOBJ
,
2779 .release
= i915_driver_release
,
2780 .open
= i915_driver_open
,
2781 .lastclose
= i915_driver_lastclose
,
2782 .postclose
= i915_driver_postclose
,
2784 .gem_close_object
= i915_gem_close_object
,
2785 .gem_free_object_unlocked
= i915_gem_free_object
,
2786 .gem_vm_ops
= &i915_gem_vm_ops
,
2788 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2789 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2790 .gem_prime_export
= i915_gem_prime_export
,
2791 .gem_prime_import
= i915_gem_prime_import
,
2793 .dumb_create
= i915_gem_dumb_create
,
2794 .dumb_map_offset
= i915_gem_mmap_gtt
,
2795 .ioctls
= i915_ioctls
,
2796 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2797 .fops
= &i915_driver_fops
,
2798 .name
= DRIVER_NAME
,
2799 .desc
= DRIVER_DESC
,
2800 .date
= DRIVER_DATE
,
2801 .major
= DRIVER_MAJOR
,
2802 .minor
= DRIVER_MINOR
,
2803 .patchlevel
= DRIVER_PATCHLEVEL
,
2806 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2807 #include "selftests/mock_drm.c"