1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170703"
84 #define DRIVER_TIMESTAMP 1499064041
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func
, int line
);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t
;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val
)
125 static inline uint_fixed_16_16_t
u32_to_fixed16(uint32_t val
)
127 uint_fixed_16_16_t fp
;
135 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp
)
137 return DIV_ROUND_UP(fp
.val
, 1 << 16);
140 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp
)
145 static inline uint_fixed_16_16_t
min_fixed16(uint_fixed_16_16_t min1
,
146 uint_fixed_16_16_t min2
)
148 uint_fixed_16_16_t min
;
150 min
.val
= min(min1
.val
, min2
.val
);
154 static inline uint_fixed_16_16_t
max_fixed16(uint_fixed_16_16_t max1
,
155 uint_fixed_16_16_t max2
)
157 uint_fixed_16_16_t max
;
159 max
.val
= max(max1
.val
, max2
.val
);
163 static inline uint_fixed_16_16_t
clamp_u64_to_fixed16(uint64_t val
)
165 uint_fixed_16_16_t fp
;
167 fp
.val
= clamp_t(uint32_t, val
, 0, ~0);
171 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val
,
172 uint_fixed_16_16_t d
)
174 return DIV_ROUND_UP(val
.val
, d
.val
);
177 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val
,
178 uint_fixed_16_16_t mul
)
180 uint64_t intermediate_val
;
182 intermediate_val
= (uint64_t) val
* mul
.val
;
183 intermediate_val
= DIV_ROUND_UP_ULL(intermediate_val
, 1 << 16);
184 WARN_ON(intermediate_val
>> 32);
185 return clamp_t(uint32_t, intermediate_val
, 0, ~0);
188 static inline uint_fixed_16_16_t
mul_fixed16(uint_fixed_16_16_t val
,
189 uint_fixed_16_16_t mul
)
191 uint64_t intermediate_val
;
193 intermediate_val
= (uint64_t) val
.val
* mul
.val
;
194 intermediate_val
= intermediate_val
>> 16;
195 return clamp_u64_to_fixed16(intermediate_val
);
198 static inline uint_fixed_16_16_t
div_fixed16(uint32_t val
, uint32_t d
)
202 interm_val
= (uint64_t)val
<< 16;
203 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
204 return clamp_u64_to_fixed16(interm_val
);
207 static inline uint32_t div_round_up_u32_fixed16(uint32_t val
,
208 uint_fixed_16_16_t d
)
212 interm_val
= (uint64_t)val
<< 16;
213 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
.val
);
214 WARN_ON(interm_val
>> 32);
215 return clamp_t(uint32_t, interm_val
, 0, ~0);
218 static inline uint_fixed_16_16_t
mul_u32_fixed16(uint32_t val
,
219 uint_fixed_16_16_t mul
)
221 uint64_t intermediate_val
;
223 intermediate_val
= (uint64_t) val
* mul
.val
;
224 return clamp_u64_to_fixed16(intermediate_val
);
227 static inline const char *yesno(bool v
)
229 return v
? "yes" : "no";
232 static inline const char *onoff(bool v
)
234 return v
? "on" : "off";
237 static inline const char *enableddisabled(bool v
)
239 return v
? "enabled" : "disabled";
248 I915_MAX_PIPES
= _PIPE_EDP
250 #define pipe_name(p) ((p) + 'A')
262 static inline const char *transcoder_name(enum transcoder transcoder
)
264 switch (transcoder
) {
273 case TRANSCODER_DSI_A
:
275 case TRANSCODER_DSI_C
:
282 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
284 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
288 * Global legacy plane identifier. Valid only for primary/sprite
289 * planes on pre-g4x, and only for primary planes on g4x+.
296 #define plane_name(p) ((p) + 'A')
298 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
301 * Per-pipe plane identifier.
302 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
303 * number of planes per CRTC. Not all platforms really have this many planes,
304 * which means some arrays of size I915_MAX_PLANES may have unused entries
305 * between the topmost sprite plane and the cursor plane.
307 * This is expected to be passed to various register macros
308 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
319 #define for_each_plane_id_on_crtc(__crtc, __p) \
320 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
321 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
332 #define port_name(p) ((p) + 'A')
334 #define I915_NUM_PHYS_VLV 2
347 enum intel_display_power_domain
{
351 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
352 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
353 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
354 POWER_DOMAIN_TRANSCODER_A
,
355 POWER_DOMAIN_TRANSCODER_B
,
356 POWER_DOMAIN_TRANSCODER_C
,
357 POWER_DOMAIN_TRANSCODER_EDP
,
358 POWER_DOMAIN_TRANSCODER_DSI_A
,
359 POWER_DOMAIN_TRANSCODER_DSI_C
,
360 POWER_DOMAIN_PORT_DDI_A_LANES
,
361 POWER_DOMAIN_PORT_DDI_B_LANES
,
362 POWER_DOMAIN_PORT_DDI_C_LANES
,
363 POWER_DOMAIN_PORT_DDI_D_LANES
,
364 POWER_DOMAIN_PORT_DDI_E_LANES
,
365 POWER_DOMAIN_PORT_DDI_A_IO
,
366 POWER_DOMAIN_PORT_DDI_B_IO
,
367 POWER_DOMAIN_PORT_DDI_C_IO
,
368 POWER_DOMAIN_PORT_DDI_D_IO
,
369 POWER_DOMAIN_PORT_DDI_E_IO
,
370 POWER_DOMAIN_PORT_DSI
,
371 POWER_DOMAIN_PORT_CRT
,
372 POWER_DOMAIN_PORT_OTHER
,
381 POWER_DOMAIN_MODESET
,
387 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
388 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
389 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
390 #define POWER_DOMAIN_TRANSCODER(tran) \
391 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
392 (tran) + POWER_DOMAIN_TRANSCODER_A)
396 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
408 #define for_each_hpd_pin(__pin) \
409 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
411 #define HPD_STORM_DEFAULT_THRESHOLD 5
413 struct i915_hotplug
{
414 struct work_struct hotplug_work
;
417 unsigned long last_jiffies
;
422 HPD_MARK_DISABLED
= 2
424 } stats
[HPD_NUM_PINS
];
426 struct delayed_work reenable_work
;
428 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
431 struct work_struct dig_port_work
;
433 struct work_struct poll_init_work
;
436 unsigned int hpd_storm_threshold
;
439 * if we get a HPD irq from DP and a HPD irq from non-DP
440 * the non-DP HPD could block the workqueue on a mode config
441 * mutex getting, that userspace may have taken. However
442 * userspace is waiting on the DP workqueue to run which is
443 * blocked behind the non-DP one.
445 struct workqueue_struct
*dp_wq
;
448 #define I915_GEM_GPU_DOMAINS \
449 (I915_GEM_DOMAIN_RENDER | \
450 I915_GEM_DOMAIN_SAMPLER | \
451 I915_GEM_DOMAIN_COMMAND | \
452 I915_GEM_DOMAIN_INSTRUCTION | \
453 I915_GEM_DOMAIN_VERTEX)
455 #define for_each_pipe(__dev_priv, __p) \
456 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
457 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
458 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
459 for_each_if ((__mask) & (1 << (__p)))
460 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
462 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
464 #define for_each_sprite(__dev_priv, __p, __s) \
466 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
469 #define for_each_port_masked(__port, __ports_mask) \
470 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
471 for_each_if ((__ports_mask) & (1 << (__port)))
473 #define for_each_crtc(dev, crtc) \
474 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
476 #define for_each_intel_plane(dev, intel_plane) \
477 list_for_each_entry(intel_plane, \
478 &(dev)->mode_config.plane_list, \
481 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
482 list_for_each_entry(intel_plane, \
483 &(dev)->mode_config.plane_list, \
485 for_each_if ((plane_mask) & \
486 (1 << drm_plane_index(&intel_plane->base)))
488 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
489 list_for_each_entry(intel_plane, \
490 &(dev)->mode_config.plane_list, \
492 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
494 #define for_each_intel_crtc(dev, intel_crtc) \
495 list_for_each_entry(intel_crtc, \
496 &(dev)->mode_config.crtc_list, \
499 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
500 list_for_each_entry(intel_crtc, \
501 &(dev)->mode_config.crtc_list, \
503 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
505 #define for_each_intel_encoder(dev, intel_encoder) \
506 list_for_each_entry(intel_encoder, \
507 &(dev)->mode_config.encoder_list, \
510 #define for_each_intel_connector_iter(intel_connector, iter) \
511 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
513 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
514 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
515 for_each_if ((intel_encoder)->base.crtc == (__crtc))
517 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
518 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
519 for_each_if ((intel_connector)->base.encoder == (__encoder))
521 #define for_each_power_domain(domain, mask) \
522 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
523 for_each_if (BIT_ULL(domain) & (mask))
525 #define for_each_power_well(__dev_priv, __power_well) \
526 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
527 (__power_well) - (__dev_priv)->power_domains.power_wells < \
528 (__dev_priv)->power_domains.power_well_count; \
531 #define for_each_power_well_rev(__dev_priv, __power_well) \
532 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
533 (__dev_priv)->power_domains.power_well_count - 1; \
534 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
537 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
538 for_each_power_well(__dev_priv, __power_well) \
539 for_each_if ((__power_well)->domains & (__domain_mask))
541 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
542 for_each_power_well_rev(__dev_priv, __power_well) \
543 for_each_if ((__power_well)->domains & (__domain_mask))
545 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
547 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
548 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
549 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
551 for_each_if (plane_state)
553 struct drm_i915_private
;
554 struct i915_mm_struct
;
555 struct i915_mmu_object
;
557 struct drm_i915_file_private
{
558 struct drm_i915_private
*dev_priv
;
559 struct drm_file
*file
;
563 struct list_head request_list
;
564 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
565 * chosen to prevent the CPU getting more than a frame ahead of the GPU
566 * (when using lax throttling for the frontbuffer). We also use it to
567 * offer free GPU waitboosts for severely congested workloads.
569 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
571 struct idr context_idr
;
573 struct intel_rps_client
{
577 unsigned int bsd_engine
;
579 /* Client can have a maximum of 3 contexts banned before
580 * it is denied of creating new contexts. As one context
581 * ban needs 4 consecutive hangs, and more if there is
582 * progress in between, this is a last resort stop gap measure
583 * to limit the badly behaving clients access to gpu.
585 #define I915_MAX_CLIENT_CONTEXT_BANS 3
589 /* Used by dp and fdi links */
590 struct intel_link_m_n
{
598 void intel_link_compute_m_n(int bpp
, int nlanes
,
599 int pixel_clock
, int link_clock
,
600 struct intel_link_m_n
*m_n
,
603 /* Interface history:
606 * 1.2: Add Power Management
607 * 1.3: Add vblank support
608 * 1.4: Fix cmdbuffer path, add heap destroy
609 * 1.5: Add vblank pipe configuration
610 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
611 * - Support vertical blank on secondary display pipe
613 #define DRIVER_MAJOR 1
614 #define DRIVER_MINOR 6
615 #define DRIVER_PATCHLEVEL 0
617 struct opregion_header
;
618 struct opregion_acpi
;
619 struct opregion_swsci
;
620 struct opregion_asle
;
622 struct intel_opregion
{
623 struct opregion_header
*header
;
624 struct opregion_acpi
*acpi
;
625 struct opregion_swsci
*swsci
;
626 u32 swsci_gbda_sub_functions
;
627 u32 swsci_sbcb_sub_functions
;
628 struct opregion_asle
*asle
;
633 struct work_struct asle_work
;
635 #define OPREGION_SIZE (8*1024)
637 struct intel_overlay
;
638 struct intel_overlay_error_state
;
640 struct sdvo_device_mapping
{
649 struct intel_connector
;
650 struct intel_encoder
;
651 struct intel_atomic_state
;
652 struct intel_crtc_state
;
653 struct intel_initial_plane_config
;
657 struct intel_cdclk_state
;
659 struct drm_i915_display_funcs
{
660 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
661 struct intel_cdclk_state
*cdclk_state
);
662 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
663 const struct intel_cdclk_state
*cdclk_state
);
664 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
665 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
666 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
667 struct intel_crtc
*intel_crtc
,
668 struct intel_crtc_state
*newstate
);
669 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
670 struct intel_crtc_state
*cstate
);
671 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
672 struct intel_crtc_state
*cstate
);
673 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
674 struct intel_crtc_state
*cstate
);
675 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
676 void (*update_wm
)(struct intel_crtc
*crtc
);
677 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
678 /* Returns the active state of the crtc, and if the crtc is active,
679 * fills out the pipe-config with the hw state. */
680 bool (*get_pipe_config
)(struct intel_crtc
*,
681 struct intel_crtc_state
*);
682 void (*get_initial_plane_config
)(struct intel_crtc
*,
683 struct intel_initial_plane_config
*);
684 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
685 struct intel_crtc_state
*crtc_state
);
686 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
687 struct drm_atomic_state
*old_state
);
688 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
689 struct drm_atomic_state
*old_state
);
690 void (*update_crtcs
)(struct drm_atomic_state
*state
,
691 unsigned int *crtc_vblank_mask
);
692 void (*audio_codec_enable
)(struct drm_connector
*connector
,
693 struct intel_encoder
*encoder
,
694 const struct drm_display_mode
*adjusted_mode
);
695 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
696 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
697 const struct intel_crtc_state
*crtc_state
);
698 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
699 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
700 struct drm_framebuffer
*fb
,
701 struct drm_i915_gem_object
*obj
,
702 struct drm_i915_gem_request
*req
,
704 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
705 /* clock updates for mode set */
707 /* render clock increase/decrease */
708 /* display clock increase/decrease */
709 /* pll clock increase/decrease */
711 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
712 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
715 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
716 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
717 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
720 struct work_struct work
;
722 uint32_t *dmc_payload
;
723 uint32_t dmc_fw_size
;
726 i915_reg_t mmioaddr
[8];
727 uint32_t mmiodata
[8];
729 uint32_t allowed_dc_mask
;
732 #define DEV_INFO_FOR_EACH_FLAG(func) \
735 func(is_alpha_support); \
736 /* Keep has_* in alphabetical order */ \
737 func(has_64bit_reloc); \
738 func(has_aliasing_ppgtt); \
742 func(has_reset_engine); \
744 func(has_fpga_dbg); \
745 func(has_full_ppgtt); \
746 func(has_full_48bit_ppgtt); \
747 func(has_gmbus_irq); \
748 func(has_gmch_display); \
754 func(has_logical_ring_contexts); \
756 func(has_pipe_cxsr); \
757 func(has_pooled_eu); \
761 func(has_resource_streamer); \
762 func(has_runtime_pm); \
764 func(unfenced_needs_alignment); \
765 func(cursor_needs_physical); \
766 func(hws_needs_physical); \
767 func(overlay_needs_physical); \
770 struct sseu_dev_info
{
776 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
779 u8 has_subslice_pg
:1;
783 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
785 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
788 /* Keep in gen based order, and chronological order within a gen */
789 enum intel_platform
{
790 INTEL_PLATFORM_UNINITIALIZED
= 0,
821 struct intel_device_info
{
822 u32 display_mmio_offset
;
825 u8 num_sprites
[I915_MAX_PIPES
];
826 u8 num_scalers
[I915_MAX_PIPES
];
829 enum intel_platform platform
;
830 u8 ring_mask
; /* Rings supported by the HW */
832 #define DEFINE_FLAG(name) u8 name:1
833 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
835 u16 ddb_size
; /* in blocks */
836 /* Register offsets for the various display pipes and transcoders */
837 int pipe_offsets
[I915_MAX_TRANSCODERS
];
838 int trans_offsets
[I915_MAX_TRANSCODERS
];
839 int palette_offsets
[I915_MAX_PIPES
];
840 int cursor_offsets
[I915_MAX_PIPES
];
842 /* Slice/subslice/EU info */
843 struct sseu_dev_info sseu
;
846 u16 degamma_lut_size
;
851 struct intel_display_error_state
;
853 struct i915_gpu_state
{
856 struct timeval boottime
;
857 struct timeval uptime
;
859 struct drm_i915_private
*i915
;
869 struct intel_device_info device_info
;
870 struct i915_params params
;
872 /* Generic register state */
876 u32 gtier
[4], ngtier
;
880 u32 error
; /* gen6+ */
881 u32 err_int
; /* gen7 */
882 u32 fault_data0
; /* gen8, gen9 */
883 u32 fault_data1
; /* gen8, gen9 */
891 u64 fence
[I915_MAX_NUM_FENCES
];
892 struct intel_overlay_error_state
*overlay
;
893 struct intel_display_error_state
*display
;
894 struct drm_i915_error_object
*semaphore
;
895 struct drm_i915_error_object
*guc_log
;
897 struct drm_i915_error_engine
{
899 /* Software tracked state */
902 unsigned long hangcheck_timestamp
;
903 bool hangcheck_stalled
;
904 enum intel_engine_hangcheck_action hangcheck_action
;
905 struct i915_address_space
*vm
;
909 /* position of active request inside the ring */
910 u32 rq_head
, rq_post
, rq_tail
;
912 /* our own tracking of ring head and tail */
935 u32 rc_psmi
; /* sleep state */
936 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
937 struct intel_instdone instdone
;
939 struct drm_i915_error_context
{
940 char comm
[TASK_COMM_LEN
];
949 struct drm_i915_error_object
{
955 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
957 struct drm_i915_error_object
**user_bo
;
960 struct drm_i915_error_object
*wa_ctx
;
962 struct drm_i915_error_request
{
970 } *requests
, execlist
[2];
972 struct drm_i915_error_waiter
{
973 char comm
[TASK_COMM_LEN
];
985 } engine
[I915_NUM_ENGINES
];
987 struct drm_i915_error_buffer
{
990 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
994 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1001 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1002 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1003 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1006 enum i915_cache_level
{
1007 I915_CACHE_NONE
= 0,
1008 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1009 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1010 caches, eg sampler/render caches, and the
1011 large Last-Level-Cache. LLC is coherent with
1012 the CPU, but L3 is only visible to the GPU. */
1013 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1016 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1027 /* This is always the inner lock when overlapping with struct_mutex and
1028 * it's the outer lock when overlapping with stolen_lock. */
1031 unsigned int possible_framebuffer_bits
;
1032 unsigned int busy_bits
;
1033 unsigned int visible_pipes_mask
;
1034 struct intel_crtc
*crtc
;
1036 struct drm_mm_node compressed_fb
;
1037 struct drm_mm_node
*compressed_llb
;
1044 bool underrun_detected
;
1045 struct work_struct underrun_work
;
1047 struct intel_fbc_state_cache
{
1048 struct i915_vma
*vma
;
1051 unsigned int mode_flags
;
1052 uint32_t hsw_bdw_pixel_rate
;
1056 unsigned int rotation
;
1063 const struct drm_format_info
*format
;
1064 unsigned int stride
;
1068 struct intel_fbc_reg_params
{
1069 struct i915_vma
*vma
;
1074 unsigned int fence_y_offset
;
1078 const struct drm_format_info
*format
;
1079 unsigned int stride
;
1085 struct intel_fbc_work
{
1087 u32 scheduled_vblank
;
1088 struct work_struct work
;
1091 const char *no_fbc_reason
;
1095 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1096 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1097 * parsing for same resolution.
1099 enum drrs_refresh_rate_type
{
1102 DRRS_MAX_RR
, /* RR count */
1105 enum drrs_support_type
{
1106 DRRS_NOT_SUPPORTED
= 0,
1107 STATIC_DRRS_SUPPORT
= 1,
1108 SEAMLESS_DRRS_SUPPORT
= 2
1114 struct delayed_work work
;
1115 struct intel_dp
*dp
;
1116 unsigned busy_frontbuffer_bits
;
1117 enum drrs_refresh_rate_type refresh_rate_type
;
1118 enum drrs_support_type type
;
1125 struct intel_dp
*enabled
;
1127 struct delayed_work work
;
1128 unsigned busy_frontbuffer_bits
;
1130 bool aux_frame_sync
;
1132 bool y_cord_support
;
1133 bool colorimetry_support
;
1138 PCH_NONE
= 0, /* No PCH present */
1139 PCH_IBX
, /* Ibexpeak PCH */
1140 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
1141 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
1142 PCH_SPT
, /* Sunrisepoint PCH */
1143 PCH_KBP
, /* Kabypoint PCH */
1144 PCH_CNP
, /* Cannonpoint PCH */
1148 enum intel_sbi_destination
{
1153 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1154 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1155 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1156 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1157 #define QUIRK_INCREASE_T12_DELAY (1<<6)
1160 struct intel_fbc_work
;
1162 struct intel_gmbus
{
1163 struct i2c_adapter adapter
;
1164 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1167 i915_reg_t gpio_reg
;
1168 struct i2c_algo_bit_data bit_algo
;
1169 struct drm_i915_private
*dev_priv
;
1172 struct i915_suspend_saved_registers
{
1174 u32 saveFBC_CONTROL
;
1175 u32 saveCACHE_MODE_0
;
1176 u32 saveMI_ARB_STATE
;
1180 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1181 u32 savePCH_PORT_HOTPLUG
;
1185 struct vlv_s0ix_state
{
1192 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1193 u32 media_max_req_count
;
1194 u32 gfx_max_req_count
;
1220 u32 rp_down_timeout
;
1226 /* Display 1 CZ domain */
1231 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1233 /* GT SA CZ domain */
1240 /* Display 2 CZ domain */
1244 u32 clock_gate_dis2
;
1247 struct intel_rps_ei
{
1253 struct intel_gen6_power_mgmt
{
1255 * work, interrupts_enabled and pm_iir are protected by
1256 * dev_priv->irq_lock
1258 struct work_struct work
;
1259 bool interrupts_enabled
;
1262 /* PM interrupt bits that should never be masked */
1265 /* Frequencies are stored in potentially platform dependent multiples.
1266 * In other words, *_freq needs to be multiplied by X to be interesting.
1267 * Soft limits are those which are used for the dynamic reclocking done
1268 * by the driver (raise frequencies under heavy loads, and lower for
1269 * lighter loads). Hard limits are those imposed by the hardware.
1271 * A distinction is made for overclocking, which is never enabled by
1272 * default, and is considered to be above the hard limit if it's
1275 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1276 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1277 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1278 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1279 u8 min_freq
; /* AKA RPn. Minimum frequency */
1280 u8 boost_freq
; /* Frequency to request when wait boosting */
1281 u8 idle_freq
; /* Frequency to request when we are idle */
1282 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1283 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1284 u8 rp0_freq
; /* Non-overclocked max frequency. */
1285 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1287 u8 up_threshold
; /* Current %busy required to uplock */
1288 u8 down_threshold
; /* Current %busy required to downclock */
1291 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1294 struct delayed_work autoenable_work
;
1295 atomic_t num_waiters
;
1298 /* manual wa residency calculations */
1299 struct intel_rps_ei ei
;
1302 * Protects RPS/RC6 register access and PCU communication.
1303 * Must be taken after struct_mutex if nested. Note that
1304 * this lock may be held for long periods of time when
1305 * talking to hw - so only take it when talking to hw!
1307 struct mutex hw_lock
;
1310 /* defined intel_pm.c */
1311 extern spinlock_t mchdev_lock
;
1313 struct intel_ilk_power_mgmt
{
1321 unsigned long last_time1
;
1322 unsigned long chipset_power
;
1325 unsigned long gfx_power
;
1332 struct drm_i915_private
;
1333 struct i915_power_well
;
1335 struct i915_power_well_ops
{
1337 * Synchronize the well's hw state to match the current sw state, for
1338 * example enable/disable it based on the current refcount. Called
1339 * during driver init and resume time, possibly after first calling
1340 * the enable/disable handlers.
1342 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1343 struct i915_power_well
*power_well
);
1345 * Enable the well and resources that depend on it (for example
1346 * interrupts located on the well). Called after the 0->1 refcount
1349 void (*enable
)(struct drm_i915_private
*dev_priv
,
1350 struct i915_power_well
*power_well
);
1352 * Disable the well and resources that depend on it. Called after
1353 * the 1->0 refcount transition.
1355 void (*disable
)(struct drm_i915_private
*dev_priv
,
1356 struct i915_power_well
*power_well
);
1357 /* Returns the hw enabled state. */
1358 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1359 struct i915_power_well
*power_well
);
1362 /* Power well structure for haswell */
1363 struct i915_power_well
{
1366 /* power well enable/disable usage count */
1368 /* cached hw enabled state */
1371 /* unique identifier for this power well */
1374 * Arbitraty data associated with this power well. Platform and power
1378 const struct i915_power_well_ops
*ops
;
1381 struct i915_power_domains
{
1383 * Power wells needed for initialization at driver init and suspend
1384 * time are on. They are kept on until after the first modeset.
1388 int power_well_count
;
1391 int domain_use_count
[POWER_DOMAIN_NUM
];
1392 struct i915_power_well
*power_wells
;
1395 #define MAX_L3_SLICES 2
1396 struct intel_l3_parity
{
1397 u32
*remap_info
[MAX_L3_SLICES
];
1398 struct work_struct error_work
;
1402 struct i915_gem_mm
{
1403 /** Memory allocator for GTT stolen memory */
1404 struct drm_mm stolen
;
1405 /** Protects the usage of the GTT stolen memory allocator. This is
1406 * always the inner lock when overlapping with struct_mutex. */
1407 struct mutex stolen_lock
;
1409 /** List of all objects in gtt_space. Used to restore gtt
1410 * mappings on resume */
1411 struct list_head bound_list
;
1413 * List of objects which are not bound to the GTT (thus
1414 * are idle and not used by the GPU). These objects may or may
1415 * not actually have any pages attached.
1417 struct list_head unbound_list
;
1419 /** List of all objects in gtt_space, currently mmaped by userspace.
1420 * All objects within this list must also be on bound_list.
1422 struct list_head userfault_list
;
1425 * List of objects which are pending destruction.
1427 struct llist_head free_list
;
1428 struct work_struct free_work
;
1430 /** Usable portion of the GTT for GEM */
1431 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1433 /** PPGTT used for aliasing the PPGTT with the GTT */
1434 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1436 struct notifier_block oom_notifier
;
1437 struct notifier_block vmap_notifier
;
1438 struct shrinker shrinker
;
1440 /** LRU list of objects with fence regs on them. */
1441 struct list_head fence_list
;
1444 * Workqueue to fault in userptr pages, flushed by the execbuf
1445 * when required but otherwise left to userspace to try again
1448 struct workqueue_struct
*userptr_wq
;
1450 u64 unordered_timeline
;
1452 /* the indicator for dispatch video commands on two BSD rings */
1453 atomic_t bsd_engine_dispatch_index
;
1455 /** Bit 6 swizzling required for X tiling */
1456 uint32_t bit_6_swizzle_x
;
1457 /** Bit 6 swizzling required for Y tiling */
1458 uint32_t bit_6_swizzle_y
;
1460 /* accounting, useful for userland debugging */
1461 spinlock_t object_stat_lock
;
1466 struct drm_i915_error_state_buf
{
1467 struct drm_i915_private
*i915
;
1476 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1477 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1479 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1480 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1482 struct i915_gpu_error
{
1483 /* For hangcheck timer */
1484 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1485 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1487 struct delayed_work hangcheck_work
;
1489 /* For reset and error_state handling. */
1491 /* Protected by the above dev->gpu_error.lock. */
1492 struct i915_gpu_state
*first_error
;
1494 unsigned long missed_irq_rings
;
1497 * State variable controlling the reset flow and count
1499 * This is a counter which gets incremented when reset is triggered,
1501 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1502 * meaning that any waiters holding onto the struct_mutex should
1503 * relinquish the lock immediately in order for the reset to start.
1505 * If reset is not completed succesfully, the I915_WEDGE bit is
1506 * set meaning that hardware is terminally sour and there is no
1507 * recovery. All waiters on the reset_queue will be woken when
1510 * This counter is used by the wait_seqno code to notice that reset
1511 * event happened and it needs to restart the entire ioctl (since most
1512 * likely the seqno it waited for won't ever signal anytime soon).
1514 * This is important for lock-free wait paths, where no contended lock
1515 * naturally enforces the correct ordering between the bail-out of the
1516 * waiter and the gpu reset work code.
1518 unsigned long reset_count
;
1521 * flags: Control various stages of the GPU reset
1523 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1524 * other users acquiring the struct_mutex. To do this we set the
1525 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1526 * and then check for that bit before acquiring the struct_mutex (in
1527 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1528 * secondary role in preventing two concurrent global reset attempts.
1530 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1531 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1532 * but it may be held by some long running waiter (that we cannot
1533 * interrupt without causing trouble). Once we are ready to do the GPU
1534 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1535 * they already hold the struct_mutex and want to participate they can
1536 * inspect the bit and do the reset directly, otherwise the worker
1537 * waits for the struct_mutex.
1539 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1540 * acquire the struct_mutex to reset an engine, we need an explicit
1541 * flag to prevent two concurrent reset attempts in the same engine.
1542 * As the number of engines continues to grow, allocate the flags from
1543 * the most significant bits.
1545 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1546 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1547 * i915_gem_request_alloc(), this bit is checked and the sequence
1548 * aborted (with -EIO reported to userspace) if set.
1550 unsigned long flags
;
1551 #define I915_RESET_BACKOFF 0
1552 #define I915_RESET_HANDOFF 1
1553 #define I915_WEDGED (BITS_PER_LONG - 1)
1554 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1556 /** Number of times an engine has been reset */
1557 u32 reset_engine_count
[I915_NUM_ENGINES
];
1560 * Waitqueue to signal when a hang is detected. Used to for waiters
1561 * to release the struct_mutex for the reset to procede.
1563 wait_queue_head_t wait_queue
;
1566 * Waitqueue to signal when the reset has completed. Used by clients
1567 * that wait for dev_priv->mm.wedged to settle.
1569 wait_queue_head_t reset_queue
;
1571 /* For missed irq/seqno simulation. */
1572 unsigned long test_irq_rings
;
1575 enum modeset_restore
{
1576 MODESET_ON_LID_OPEN
,
1581 #define DP_AUX_A 0x40
1582 #define DP_AUX_B 0x10
1583 #define DP_AUX_C 0x20
1584 #define DP_AUX_D 0x30
1586 #define DDC_PIN_B 0x05
1587 #define DDC_PIN_C 0x04
1588 #define DDC_PIN_D 0x06
1590 struct ddi_vbt_port_info
{
1592 * This is an index in the HDMI/DVI DDI buffer translation table.
1593 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1594 * populate this field.
1596 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1597 uint8_t hdmi_level_shift
;
1599 uint8_t supports_dvi
:1;
1600 uint8_t supports_hdmi
:1;
1601 uint8_t supports_dp
:1;
1602 uint8_t supports_edp
:1;
1604 uint8_t alternate_aux_channel
;
1605 uint8_t alternate_ddc_pin
;
1607 uint8_t dp_boost_level
;
1608 uint8_t hdmi_boost_level
;
1611 enum psr_lines_to_wait
{
1612 PSR_0_LINES_TO_WAIT
= 0,
1614 PSR_4_LINES_TO_WAIT
,
1618 struct intel_vbt_data
{
1619 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1620 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1623 unsigned int int_tv_support
:1;
1624 unsigned int lvds_dither
:1;
1625 unsigned int lvds_vbt
:1;
1626 unsigned int int_crt_support
:1;
1627 unsigned int lvds_use_ssc
:1;
1628 unsigned int display_clock_mode
:1;
1629 unsigned int fdi_rx_polarity_inverted
:1;
1630 unsigned int panel_type
:4;
1632 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1634 enum drrs_support_type drrs_type
;
1645 struct edp_power_seq pps
;
1650 bool require_aux_wakeup
;
1652 enum psr_lines_to_wait lines_to_wait
;
1653 int tp1_wakeup_time
;
1654 int tp2_tp3_wakeup_time
;
1660 bool active_low_pwm
;
1661 u8 min_brightness
; /* min_brightness/255 of max */
1662 u8 controller
; /* brightness controller number */
1663 enum intel_backlight_type type
;
1669 struct mipi_config
*config
;
1670 struct mipi_pps_data
*pps
;
1674 const u8
*sequence
[MIPI_SEQ_MAX
];
1680 union child_device_config
*child_dev
;
1682 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1683 struct sdvo_device_mapping sdvo_mappings
[2];
1686 enum intel_ddb_partitioning
{
1688 INTEL_DDB_PART_5_6
, /* IVB+ */
1691 struct intel_wm_level
{
1699 struct ilk_wm_values
{
1700 uint32_t wm_pipe
[3];
1702 uint32_t wm_lp_spr
[3];
1703 uint32_t wm_linetime
[3];
1705 enum intel_ddb_partitioning partitioning
;
1708 struct g4x_pipe_wm
{
1709 uint16_t plane
[I915_MAX_PLANES
];
1719 struct vlv_wm_ddl_values
{
1720 uint8_t plane
[I915_MAX_PLANES
];
1723 struct vlv_wm_values
{
1724 struct g4x_pipe_wm pipe
[3];
1725 struct g4x_sr_wm sr
;
1726 struct vlv_wm_ddl_values ddl
[3];
1731 struct g4x_wm_values
{
1732 struct g4x_pipe_wm pipe
[2];
1733 struct g4x_sr_wm sr
;
1734 struct g4x_sr_wm hpll
;
1740 struct skl_ddb_entry
{
1741 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1744 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1746 return entry
->end
- entry
->start
;
1749 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1750 const struct skl_ddb_entry
*e2
)
1752 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1758 struct skl_ddb_allocation
{
1759 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1760 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1763 struct skl_wm_values
{
1764 unsigned dirty_pipes
;
1765 struct skl_ddb_allocation ddb
;
1768 struct skl_wm_level
{
1770 uint16_t plane_res_b
;
1771 uint8_t plane_res_l
;
1775 * This struct helps tracking the state needed for runtime PM, which puts the
1776 * device in PCI D3 state. Notice that when this happens, nothing on the
1777 * graphics device works, even register access, so we don't get interrupts nor
1780 * Every piece of our code that needs to actually touch the hardware needs to
1781 * either call intel_runtime_pm_get or call intel_display_power_get with the
1782 * appropriate power domain.
1784 * Our driver uses the autosuspend delay feature, which means we'll only really
1785 * suspend if we stay with zero refcount for a certain amount of time. The
1786 * default value is currently very conservative (see intel_runtime_pm_enable), but
1787 * it can be changed with the standard runtime PM files from sysfs.
1789 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1790 * goes back to false exactly before we reenable the IRQs. We use this variable
1791 * to check if someone is trying to enable/disable IRQs while they're supposed
1792 * to be disabled. This shouldn't happen and we'll print some error messages in
1795 * For more, read the Documentation/power/runtime_pm.txt.
1797 struct i915_runtime_pm
{
1798 atomic_t wakeref_count
;
1803 enum intel_pipe_crc_source
{
1804 INTEL_PIPE_CRC_SOURCE_NONE
,
1805 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1806 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1807 INTEL_PIPE_CRC_SOURCE_PF
,
1808 INTEL_PIPE_CRC_SOURCE_PIPE
,
1809 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1810 INTEL_PIPE_CRC_SOURCE_TV
,
1811 INTEL_PIPE_CRC_SOURCE_DP_B
,
1812 INTEL_PIPE_CRC_SOURCE_DP_C
,
1813 INTEL_PIPE_CRC_SOURCE_DP_D
,
1814 INTEL_PIPE_CRC_SOURCE_AUTO
,
1815 INTEL_PIPE_CRC_SOURCE_MAX
,
1818 struct intel_pipe_crc_entry
{
1823 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1824 struct intel_pipe_crc
{
1826 bool opened
; /* exclusive access to the result file */
1827 struct intel_pipe_crc_entry
*entries
;
1828 enum intel_pipe_crc_source source
;
1830 wait_queue_head_t wq
;
1834 struct i915_frontbuffer_tracking
{
1838 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1845 struct i915_wa_reg
{
1848 /* bitmask representing WA bits */
1853 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1854 * allowing it for RCS as we don't foresee any requirement of having
1855 * a whitelist for other engines. When it is really required for
1856 * other engines then the limit need to be increased.
1858 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1860 struct i915_workarounds
{
1861 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1863 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1866 struct i915_virtual_gpu
{
1870 /* used in computing the new watermarks state */
1871 struct intel_wm_config
{
1872 unsigned int num_pipes_active
;
1873 bool sprites_enabled
;
1874 bool sprites_scaled
;
1877 struct i915_oa_format
{
1882 struct i915_oa_reg
{
1887 struct i915_perf_stream
;
1890 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1892 struct i915_perf_stream_ops
{
1894 * @enable: Enables the collection of HW samples, either in response to
1895 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1896 * without `I915_PERF_FLAG_DISABLED`.
1898 void (*enable
)(struct i915_perf_stream
*stream
);
1901 * @disable: Disables the collection of HW samples, either in response
1902 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1905 void (*disable
)(struct i915_perf_stream
*stream
);
1908 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1909 * once there is something ready to read() for the stream
1911 void (*poll_wait
)(struct i915_perf_stream
*stream
,
1916 * @wait_unlocked: For handling a blocking read, wait until there is
1917 * something to ready to read() for the stream. E.g. wait on the same
1918 * wait queue that would be passed to poll_wait().
1920 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
1923 * @read: Copy buffered metrics as records to userspace
1924 * **buf**: the userspace, destination buffer
1925 * **count**: the number of bytes to copy, requested by userspace
1926 * **offset**: zero at the start of the read, updated as the read
1927 * proceeds, it represents how many bytes have been copied so far and
1928 * the buffer offset for copying the next record.
1930 * Copy as many buffered i915 perf samples and records for this stream
1931 * to userspace as will fit in the given buffer.
1933 * Only write complete records; returning -%ENOSPC if there isn't room
1934 * for a complete record.
1936 * Return any error condition that results in a short read such as
1937 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1938 * returning to userspace.
1940 int (*read
)(struct i915_perf_stream
*stream
,
1946 * @destroy: Cleanup any stream specific resources.
1948 * The stream will always be disabled before this is called.
1950 void (*destroy
)(struct i915_perf_stream
*stream
);
1954 * struct i915_perf_stream - state for a single open stream FD
1956 struct i915_perf_stream
{
1958 * @dev_priv: i915 drm device
1960 struct drm_i915_private
*dev_priv
;
1963 * @link: Links the stream into ``&drm_i915_private->streams``
1965 struct list_head link
;
1968 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1969 * properties given when opening a stream, representing the contents
1970 * of a single sample as read() by userspace.
1975 * @sample_size: Considering the configured contents of a sample
1976 * combined with the required header size, this is the total size
1977 * of a single sample record.
1982 * @ctx: %NULL if measuring system-wide across all contexts or a
1983 * specific context that is being monitored.
1985 struct i915_gem_context
*ctx
;
1988 * @enabled: Whether the stream is currently enabled, considering
1989 * whether the stream was opened in a disabled state and based
1990 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1995 * @ops: The callbacks providing the implementation of this specific
1996 * type of configured stream.
1998 const struct i915_perf_stream_ops
*ops
;
2002 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2004 struct i915_oa_ops
{
2006 * @init_oa_buffer: Resets the head and tail pointers of the
2007 * circular buffer for periodic OA reports.
2009 * Called when first opening a stream for OA metrics, but also may be
2010 * called in response to an OA buffer overflow or other error
2013 * Note it may be necessary to clear the full OA buffer here as part of
2014 * maintaining the invariable that new reports must be written to
2015 * zeroed memory for us to be able to reliable detect if an expected
2016 * report has not yet landed in memory. (At least on Haswell the OA
2017 * buffer tail pointer is not synchronized with reports being visible
2020 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2023 * @select_metric_set: The auto generated code that checks whether a
2024 * requested OA config is applicable to the system and if so sets up
2025 * the mux, oa and flex eu register config pointers according to the
2026 * current dev_priv->perf.oa.metrics_set.
2028 int (*select_metric_set
)(struct drm_i915_private
*dev_priv
);
2031 * @enable_metric_set: Selects and applies any MUX configuration to set
2032 * up the Boolean and Custom (B/C) counters that are part of the
2033 * counter reports being sampled. May apply system constraints such as
2034 * disabling EU clock gating as required.
2036 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
);
2039 * @disable_metric_set: Remove system constraints associated with using
2042 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2045 * @oa_enable: Enable periodic sampling
2047 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2050 * @oa_disable: Disable periodic sampling
2052 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2055 * @read: Copy data from the circular OA buffer into a given userspace
2058 int (*read
)(struct i915_perf_stream
*stream
,
2064 * @oa_hw_tail_read: read the OA tail pointer register
2066 * In particular this enables us to share all the fiddly code for
2067 * handling the OA unit tail pointer race that affects multiple
2070 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
2073 struct intel_cdclk_state
{
2074 unsigned int cdclk
, vco
, ref
;
2077 struct drm_i915_private
{
2078 struct drm_device drm
;
2080 struct kmem_cache
*objects
;
2081 struct kmem_cache
*vmas
;
2082 struct kmem_cache
*requests
;
2083 struct kmem_cache
*dependencies
;
2084 struct kmem_cache
*priorities
;
2086 const struct intel_device_info info
;
2090 struct intel_uncore uncore
;
2092 struct i915_virtual_gpu vgpu
;
2094 struct intel_gvt
*gvt
;
2096 struct intel_huc huc
;
2097 struct intel_guc guc
;
2099 struct intel_csr csr
;
2101 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2103 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2104 * controller on different i2c buses. */
2105 struct mutex gmbus_mutex
;
2108 * Base address of the gmbus and gpio block.
2110 uint32_t gpio_mmio_base
;
2112 /* MMIO base address for MIPI regs */
2113 uint32_t mipi_mmio_base
;
2115 uint32_t psr_mmio_base
;
2117 uint32_t pps_mmio_base
;
2119 wait_queue_head_t gmbus_wait_queue
;
2121 struct pci_dev
*bridge_dev
;
2122 struct i915_gem_context
*kernel_context
;
2123 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2124 struct i915_vma
*semaphore
;
2126 struct drm_dma_handle
*status_page_dmah
;
2127 struct resource mch_res
;
2129 /* protects the irq masks */
2130 spinlock_t irq_lock
;
2132 /* protects the mmio flip data */
2133 spinlock_t mmio_flip_lock
;
2135 bool display_irqs_enabled
;
2137 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2138 struct pm_qos_request pm_qos
;
2140 /* Sideband mailbox protection */
2141 struct mutex sb_lock
;
2143 /** Cached value of IMR to avoid reads in updating the bitfield */
2146 u32 de_irq_mask
[I915_MAX_PIPES
];
2153 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2155 struct i915_hotplug hotplug
;
2156 struct intel_fbc fbc
;
2157 struct i915_drrs drrs
;
2158 struct intel_opregion opregion
;
2159 struct intel_vbt_data vbt
;
2161 bool preserve_bios_swizzle
;
2164 struct intel_overlay
*overlay
;
2166 /* backlight registers and fields in struct intel_panel */
2167 struct mutex backlight_lock
;
2170 bool no_aux_handshake
;
2172 /* protects panel power sequencer state */
2173 struct mutex pps_mutex
;
2175 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2176 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2178 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2179 unsigned int skl_preferred_vco_freq
;
2180 unsigned int max_cdclk_freq
;
2182 unsigned int max_dotclk_freq
;
2183 unsigned int rawclk_freq
;
2184 unsigned int hpll_freq
;
2185 unsigned int czclk_freq
;
2189 * The current logical cdclk state.
2190 * See intel_atomic_state.cdclk.logical
2192 * For reading holding any crtc lock is sufficient,
2193 * for writing must hold all of them.
2195 struct intel_cdclk_state logical
;
2197 * The current actual cdclk state.
2198 * See intel_atomic_state.cdclk.actual
2200 struct intel_cdclk_state actual
;
2201 /* The current hardware cdclk state */
2202 struct intel_cdclk_state hw
;
2206 * wq - Driver workqueue for GEM.
2208 * NOTE: Work items scheduled here are not allowed to grab any modeset
2209 * locks, for otherwise the flushing done in the pageflip code will
2210 * result in deadlocks.
2212 struct workqueue_struct
*wq
;
2214 /* Display functions */
2215 struct drm_i915_display_funcs display
;
2217 /* PCH chipset type */
2218 enum intel_pch pch_type
;
2219 unsigned short pch_id
;
2221 unsigned long quirks
;
2223 enum modeset_restore modeset_restore
;
2224 struct mutex modeset_restore_lock
;
2225 struct drm_atomic_state
*modeset_restore_state
;
2226 struct drm_modeset_acquire_ctx reset_ctx
;
2228 struct list_head vm_list
; /* Global list of all address spaces */
2229 struct i915_ggtt ggtt
; /* VM representing the global address space */
2231 struct i915_gem_mm mm
;
2232 DECLARE_HASHTABLE(mm_structs
, 7);
2233 struct mutex mm_lock
;
2235 /* Kernel Modesetting */
2237 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2238 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2239 wait_queue_head_t pending_flip_queue
;
2241 #ifdef CONFIG_DEBUG_FS
2242 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2245 /* dpll and cdclk state is protected by connection_mutex */
2246 int num_shared_dpll
;
2247 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2248 const struct intel_dpll_mgr
*dpll_mgr
;
2251 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2252 * Must be global rather than per dpll, because on some platforms
2253 * plls share registers.
2255 struct mutex dpll_lock
;
2257 unsigned int active_crtcs
;
2258 unsigned int min_pixclk
[I915_MAX_PIPES
];
2260 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2262 struct i915_workarounds workarounds
;
2264 struct i915_frontbuffer_tracking fb_tracking
;
2266 struct intel_atomic_helper
{
2267 struct llist_head free_list
;
2268 struct work_struct free_work
;
2273 bool mchbar_need_disable
;
2275 struct intel_l3_parity l3_parity
;
2277 /* Cannot be determined by PCIID. You must always read a register. */
2280 /* gen6+ rps state */
2281 struct intel_gen6_power_mgmt rps
;
2283 /* ilk-only ips/rps state. Everything in here is protected by the global
2284 * mchdev_lock in intel_pm.c */
2285 struct intel_ilk_power_mgmt ips
;
2287 struct i915_power_domains power_domains
;
2289 struct i915_psr psr
;
2291 struct i915_gpu_error gpu_error
;
2293 struct drm_i915_gem_object
*vlv_pctx
;
2295 #ifdef CONFIG_DRM_FBDEV_EMULATION
2296 /* list of fbdev register on this device */
2297 struct intel_fbdev
*fbdev
;
2298 struct work_struct fbdev_suspend_work
;
2301 struct drm_property
*broadcast_rgb_property
;
2302 struct drm_property
*force_audio_property
;
2304 /* hda/i915 audio component */
2305 struct i915_audio_component
*audio_component
;
2306 bool audio_component_registered
;
2308 * av_mutex - mutex for audio/video sync
2311 struct mutex av_mutex
;
2314 struct list_head list
;
2315 struct llist_head free_list
;
2316 struct work_struct free_work
;
2318 /* The hw wants to have a stable context identifier for the
2319 * lifetime of the context (for OA, PASID, faults, etc).
2320 * This is limited in execlists to 21 bits.
2323 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2328 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2329 u32 chv_phy_control
;
2331 * Shadows for CHV DPLL_MD regs to keep the state
2332 * checker somewhat working in the presence hardware
2333 * crappiness (can't read out DPLL_MD for pipes B & C).
2335 u32 chv_dpll_md
[I915_MAX_PIPES
];
2339 bool suspended_to_idle
;
2340 struct i915_suspend_saved_registers regfile
;
2341 struct vlv_s0ix_state vlv_s0ix_state
;
2344 I915_SAGV_UNKNOWN
= 0,
2347 I915_SAGV_NOT_CONTROLLED
2352 * Raw watermark latency values:
2353 * in 0.1us units for WM0,
2354 * in 0.5us units for WM1+.
2357 uint16_t pri_latency
[5];
2359 uint16_t spr_latency
[5];
2361 uint16_t cur_latency
[5];
2363 * Raw watermark memory latency values
2364 * for SKL for all 8 levels
2367 uint16_t skl_latency
[8];
2369 /* current hardware state */
2371 struct ilk_wm_values hw
;
2372 struct skl_wm_values skl_hw
;
2373 struct vlv_wm_values vlv
;
2374 struct g4x_wm_values g4x
;
2380 * Should be held around atomic WM register writing; also
2381 * protects * intel_crtc->wm.active and
2382 * cstate->wm.need_postvbl_update.
2384 struct mutex wm_mutex
;
2387 * Set during HW readout of watermarks/DDB. Some platforms
2388 * need to know when we're still using BIOS-provided values
2389 * (which we don't fully trust).
2391 bool distrust_bios_wm
;
2394 struct i915_runtime_pm pm
;
2399 struct kobject
*metrics_kobj
;
2400 struct ctl_table_header
*sysctl_header
;
2403 struct list_head streams
;
2406 struct i915_perf_stream
*exclusive_stream
;
2408 u32 specific_ctx_id
;
2410 struct hrtimer poll_check_timer
;
2411 wait_queue_head_t poll_wq
;
2415 * For rate limiting any notifications of spurious
2416 * invalid OA reports
2418 struct ratelimit_state spurious_report_rs
;
2421 int period_exponent
;
2422 int timestamp_frequency
;
2426 const struct i915_oa_reg
*mux_regs
[6];
2427 int mux_regs_lens
[6];
2430 const struct i915_oa_reg
*b_counter_regs
;
2431 int b_counter_regs_len
;
2432 const struct i915_oa_reg
*flex_regs
;
2436 struct i915_vma
*vma
;
2443 * Locks reads and writes to all head/tail state
2445 * Consider: the head and tail pointer state
2446 * needs to be read consistently from a hrtimer
2447 * callback (atomic context) and read() fop
2448 * (user context) with tail pointer updates
2449 * happening in atomic context and head updates
2450 * in user context and the (unlikely)
2451 * possibility of read() errors needing to
2452 * reset all head/tail state.
2454 * Note: Contention or performance aren't
2455 * currently a significant concern here
2456 * considering the relatively low frequency of
2457 * hrtimer callbacks (5ms period) and that
2458 * reads typically only happen in response to a
2459 * hrtimer event and likely complete before the
2462 * Note: This lock is not held *while* reading
2463 * and copying data to userspace so the value
2464 * of head observed in htrimer callbacks won't
2465 * represent any partial consumption of data.
2467 spinlock_t ptr_lock
;
2470 * One 'aging' tail pointer and one 'aged'
2471 * tail pointer ready to used for reading.
2473 * Initial values of 0xffffffff are invalid
2474 * and imply that an update is required
2475 * (and should be ignored by an attempted
2483 * Index for the aged tail ready to read()
2486 unsigned int aged_tail_idx
;
2489 * A monotonic timestamp for when the current
2490 * aging tail pointer was read; used to
2491 * determine when it is old enough to trust.
2493 u64 aging_timestamp
;
2496 * Although we can always read back the head
2497 * pointer register, we prefer to avoid
2498 * trusting the HW state, just to avoid any
2499 * risk that some hardware condition could
2500 * somehow bump the head pointer unpredictably
2501 * and cause us to forward the wrong OA buffer
2502 * data to userspace.
2507 u32 gen7_latched_oastatus1
;
2508 u32 ctx_oactxctrl_offset
;
2509 u32 ctx_flexeu0_offset
;
2512 * The RPT_ID/reason field for Gen8+ includes a bit
2513 * to determine if the CTX ID in the report is valid
2514 * but the specific bit differs between Gen 8 and 9
2516 u32 gen8_valid_ctx_bit
;
2518 struct i915_oa_ops ops
;
2519 const struct i915_oa_format
*oa_formats
;
2524 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2526 void (*resume
)(struct drm_i915_private
*);
2527 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2529 struct list_head timelines
;
2530 struct i915_gem_timeline global_timeline
;
2531 u32 active_requests
;
2534 * Is the GPU currently considered idle, or busy executing
2535 * userspace requests? Whilst idle, we allow runtime power
2536 * management to power down the hardware and display clocks.
2537 * In order to reduce the effect on performance, there
2538 * is a slight delay before we do so.
2543 * We leave the user IRQ off as much as possible,
2544 * but this means that requests will finish and never
2545 * be retired once the system goes idle. Set a timer to
2546 * fire periodically while the ring is running. When it
2547 * fires, go retire requests.
2549 struct delayed_work retire_work
;
2552 * When we detect an idle GPU, we want to turn on
2553 * powersaving features. So once we see that there
2554 * are no more requests outstanding and no more
2555 * arrive within a small period of time, we fire
2556 * off the idle_work.
2558 struct delayed_work idle_work
;
2560 ktime_t last_init_time
;
2563 /* perform PHY state sanity checks? */
2564 bool chv_phy_assert
[2];
2568 /* Used to save the pipe-to-encoder mapping for audio */
2569 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2571 /* necessary resource sharing with HDMI LPE audio driver. */
2573 struct platform_device
*platdev
;
2578 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2579 * will be rejected. Instead look for a better place.
2583 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2585 return container_of(dev
, struct drm_i915_private
, drm
);
2588 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2590 return to_i915(dev_get_drvdata(kdev
));
2593 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2595 return container_of(guc
, struct drm_i915_private
, guc
);
2598 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2600 return container_of(huc
, struct drm_i915_private
, huc
);
2603 /* Simple iterator over all initialised engines */
2604 #define for_each_engine(engine__, dev_priv__, id__) \
2606 (id__) < I915_NUM_ENGINES; \
2608 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2610 /* Iterator over subset of engines selected by mask */
2611 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2612 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2613 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2615 enum hdmi_force_audio
{
2616 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2617 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2618 HDMI_AUDIO_AUTO
, /* trust EDID */
2619 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2622 #define I915_GTT_OFFSET_NONE ((u32)-1)
2625 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2626 * considered to be the frontbuffer for the given plane interface-wise. This
2627 * doesn't mean that the hw necessarily already scans it out, but that any
2628 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2630 * We have one bit per pipe and per scanout plane type.
2632 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2633 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2634 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2635 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2636 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2637 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2638 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2639 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2640 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2641 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2642 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2643 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2646 * Optimised SGL iterator for GEM objects
2648 static __always_inline
struct sgt_iter
{
2649 struct scatterlist
*sgp
;
2656 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2657 struct sgt_iter s
= { .sgp
= sgl
};
2660 s
.max
= s
.curr
= s
.sgp
->offset
;
2661 s
.max
+= s
.sgp
->length
;
2663 s
.dma
= sg_dma_address(s
.sgp
);
2665 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2671 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2674 if (unlikely(sg_is_chain(sg
)))
2675 sg
= sg_chain_ptr(sg
);
2680 * __sg_next - return the next scatterlist entry in a list
2681 * @sg: The current sg entry
2684 * If the entry is the last, return NULL; otherwise, step to the next
2685 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2686 * otherwise just return the pointer to the current element.
2688 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2690 #ifdef CONFIG_DEBUG_SG
2691 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2693 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2697 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2698 * @__dmap: DMA address (output)
2699 * @__iter: 'struct sgt_iter' (iterator state, internal)
2700 * @__sgt: sg_table to iterate over (input)
2702 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2703 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2704 ((__dmap) = (__iter).dma + (__iter).curr); \
2705 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2706 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2709 * for_each_sgt_page - iterate over the pages of the given sg_table
2710 * @__pp: page pointer (output)
2711 * @__iter: 'struct sgt_iter' (iterator state, internal)
2712 * @__sgt: sg_table to iterate over (input)
2714 #define for_each_sgt_page(__pp, __iter, __sgt) \
2715 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2716 ((__pp) = (__iter).pfn == 0 ? NULL : \
2717 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2718 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2719 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2721 static inline const struct intel_device_info
*
2722 intel_info(const struct drm_i915_private
*dev_priv
)
2724 return &dev_priv
->info
;
2727 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2729 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2730 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2732 #define REVID_FOREVER 0xff
2733 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2735 #define GEN_FOREVER (0)
2737 * Returns true if Gen is in inclusive range [Start, End].
2739 * Use GEN_FOREVER for unbound start and or end.
2741 #define IS_GEN(dev_priv, s, e) ({ \
2742 unsigned int __s = (s), __e = (e); \
2743 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2744 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2745 if ((__s) != GEN_FOREVER) \
2747 if ((__e) == GEN_FOREVER) \
2748 __e = BITS_PER_LONG - 1; \
2751 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2755 * Return true if revision is in range [since,until] inclusive.
2757 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2759 #define IS_REVID(p, since, until) \
2760 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2762 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2763 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2764 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2765 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2766 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2767 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2768 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2769 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2770 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2771 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2772 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2773 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2774 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2775 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2776 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2777 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2778 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2779 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2780 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2781 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2782 INTEL_DEVID(dev_priv) == 0x0152 || \
2783 INTEL_DEVID(dev_priv) == 0x015a)
2784 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2785 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2786 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2787 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2788 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2789 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2790 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2791 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2792 #define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE)
2793 #define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE)
2794 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2795 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2796 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2797 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2798 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2799 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2800 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2801 /* ULX machines are also considered ULT. */
2802 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2803 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2804 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2805 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2806 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2807 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2808 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2809 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2810 /* ULX machines are also considered ULT. */
2811 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2812 INTEL_DEVID(dev_priv) == 0x0A1E)
2813 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2814 INTEL_DEVID(dev_priv) == 0x1913 || \
2815 INTEL_DEVID(dev_priv) == 0x1916 || \
2816 INTEL_DEVID(dev_priv) == 0x1921 || \
2817 INTEL_DEVID(dev_priv) == 0x1926)
2818 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2819 INTEL_DEVID(dev_priv) == 0x1915 || \
2820 INTEL_DEVID(dev_priv) == 0x191E)
2821 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2822 INTEL_DEVID(dev_priv) == 0x5913 || \
2823 INTEL_DEVID(dev_priv) == 0x5916 || \
2824 INTEL_DEVID(dev_priv) == 0x5921 || \
2825 INTEL_DEVID(dev_priv) == 0x5926)
2826 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2827 INTEL_DEVID(dev_priv) == 0x5915 || \
2828 INTEL_DEVID(dev_priv) == 0x591E)
2829 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2830 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2831 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2832 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2833 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2834 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2835 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2836 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2837 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2838 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2839 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2840 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2842 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2844 #define SKL_REVID_A0 0x0
2845 #define SKL_REVID_B0 0x1
2846 #define SKL_REVID_C0 0x2
2847 #define SKL_REVID_D0 0x3
2848 #define SKL_REVID_E0 0x4
2849 #define SKL_REVID_F0 0x5
2850 #define SKL_REVID_G0 0x6
2851 #define SKL_REVID_H0 0x7
2853 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2855 #define BXT_REVID_A0 0x0
2856 #define BXT_REVID_A1 0x1
2857 #define BXT_REVID_B0 0x3
2858 #define BXT_REVID_B_LAST 0x8
2859 #define BXT_REVID_C0 0x9
2861 #define IS_BXT_REVID(dev_priv, since, until) \
2862 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2864 #define KBL_REVID_A0 0x0
2865 #define KBL_REVID_B0 0x1
2866 #define KBL_REVID_C0 0x2
2867 #define KBL_REVID_D0 0x3
2868 #define KBL_REVID_E0 0x4
2870 #define IS_KBL_REVID(dev_priv, since, until) \
2871 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2873 #define GLK_REVID_A0 0x0
2874 #define GLK_REVID_A1 0x1
2876 #define IS_GLK_REVID(dev_priv, since, until) \
2877 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2879 #define CNL_REVID_A0 0x0
2880 #define CNL_REVID_B0 0x1
2882 #define IS_CNL_REVID(p, since, until) \
2883 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2886 * The genX designation typically refers to the render engine, so render
2887 * capability related checks should use IS_GEN, while display and other checks
2888 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2891 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2892 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2893 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2894 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2895 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2896 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2897 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2898 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2899 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2901 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2902 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2903 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2905 #define ENGINE_MASK(id) BIT(id)
2906 #define RENDER_RING ENGINE_MASK(RCS)
2907 #define BSD_RING ENGINE_MASK(VCS)
2908 #define BLT_RING ENGINE_MASK(BCS)
2909 #define VEBOX_RING ENGINE_MASK(VECS)
2910 #define BSD2_RING ENGINE_MASK(VCS2)
2911 #define ALL_ENGINES (~0)
2913 #define HAS_ENGINE(dev_priv, id) \
2914 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2916 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2917 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2918 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2919 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2921 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2922 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2923 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2924 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2925 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2927 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2929 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2930 ((dev_priv)->info.has_logical_ring_contexts)
2931 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2932 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2933 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2935 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2936 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2937 ((dev_priv)->info.overlay_needs_physical)
2939 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2940 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2942 /* WaRsDisableCoarsePowerGating:skl,bxt */
2943 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2944 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2947 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2948 * even when in MSI mode. This results in spurious interrupt warnings if the
2949 * legacy irq no. is shared with another device. The kernel then disables that
2950 * interrupt source and so prevents the other device from working properly.
2952 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2953 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2955 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2956 * rows, which changed the alignment requirements and fence programming.
2958 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2959 !(IS_I915G(dev_priv) || \
2960 IS_I915GM(dev_priv)))
2961 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2962 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2964 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2965 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2966 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2967 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2969 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2971 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2973 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2974 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2975 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2976 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2977 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2979 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2981 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2982 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2985 * For now, anything with a GuC requires uCode loading, and then supports
2986 * command submission once loaded. But these are logically independent
2987 * properties, so we have separate macros to test them.
2989 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2990 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2991 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2992 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2993 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2995 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2997 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2999 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3000 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3001 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3002 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3003 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3004 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3005 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3006 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3007 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3008 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3009 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3010 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3011 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3012 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3013 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3014 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3016 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3017 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3018 #define HAS_PCH_CNP_LP(dev_priv) \
3019 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3020 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3021 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3022 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3023 #define HAS_PCH_LPT_LP(dev_priv) \
3024 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3025 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3026 #define HAS_PCH_LPT_H(dev_priv) \
3027 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3028 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3029 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3030 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3031 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3032 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3034 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3036 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3038 /* DPF == dynamic parity feature */
3039 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3040 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3041 2 : HAS_L3_DPF(dev_priv))
3043 #define GT_FREQUENCY_MULTIPLIER 50
3044 #define GEN9_FREQ_SCALER 3
3046 #include "i915_trace.h"
3048 static inline bool intel_vtd_active(void)
3050 #ifdef CONFIG_INTEL_IOMMU
3051 if (intel_iommu_gfx_mapped
)
3057 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3059 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
3063 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3065 return IS_BROXTON(dev_priv
) && intel_vtd_active();
3068 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
3071 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
3075 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
3076 const char *fmt
, ...);
3078 #define i915_report_error(dev_priv, fmt, ...) \
3079 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3081 #ifdef CONFIG_COMPAT
3082 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3085 #define i915_compat_ioctl NULL
3087 extern const struct dev_pm_ops i915_pm_ops
;
3089 extern int i915_driver_load(struct pci_dev
*pdev
,
3090 const struct pci_device_id
*ent
);
3091 extern void i915_driver_unload(struct drm_device
*dev
);
3092 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3093 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3094 extern void i915_reset(struct drm_i915_private
*dev_priv
);
3095 extern int i915_reset_engine(struct intel_engine_cs
*engine
);
3096 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
3097 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3098 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3099 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3100 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3101 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3102 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3103 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3104 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3106 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
3107 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3109 /* intel_hotplug.c */
3110 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3111 u32 pin_mask
, u32 long_mask
);
3112 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3113 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3114 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3115 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
3116 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3117 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3120 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3122 unsigned long delay
;
3124 if (unlikely(!i915
.enable_hangcheck
))
3127 /* Don't continually defer the hangcheck so that it is always run at
3128 * least once after work has been scheduled on any ring. Otherwise,
3129 * we will ignore a hung ring if a second ring is kept busy.
3132 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3133 queue_delayed_work(system_long_wq
,
3134 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3138 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3140 const char *fmt
, ...);
3142 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3143 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
3144 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3145 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3147 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3149 return dev_priv
->gvt
;
3152 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3154 return dev_priv
->vgpu
.active
;
3158 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3162 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3165 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3166 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3167 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3170 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3171 uint32_t interrupt_mask
,
3172 uint32_t enabled_irq_mask
);
3174 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3176 ilk_update_display_irq(dev_priv
, bits
, bits
);
3179 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3181 ilk_update_display_irq(dev_priv
, bits
, 0);
3183 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3185 uint32_t interrupt_mask
,
3186 uint32_t enabled_irq_mask
);
3187 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3188 enum pipe pipe
, uint32_t bits
)
3190 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3192 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3193 enum pipe pipe
, uint32_t bits
)
3195 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3197 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3198 uint32_t interrupt_mask
,
3199 uint32_t enabled_irq_mask
);
3201 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3203 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3206 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3208 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3212 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3213 struct drm_file
*file_priv
);
3214 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3215 struct drm_file
*file_priv
);
3216 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3217 struct drm_file
*file_priv
);
3218 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3219 struct drm_file
*file_priv
);
3220 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3221 struct drm_file
*file_priv
);
3222 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3223 struct drm_file
*file_priv
);
3224 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3225 struct drm_file
*file_priv
);
3226 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3227 struct drm_file
*file_priv
);
3228 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3229 struct drm_file
*file_priv
);
3230 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3231 struct drm_file
*file_priv
);
3232 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3233 struct drm_file
*file
);
3234 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3235 struct drm_file
*file
);
3236 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3237 struct drm_file
*file_priv
);
3238 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3239 struct drm_file
*file_priv
);
3240 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3241 struct drm_file
*file_priv
);
3242 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3243 struct drm_file
*file_priv
);
3244 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3245 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
3246 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3247 struct drm_file
*file
);
3248 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3249 struct drm_file
*file_priv
);
3250 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3251 struct drm_file
*file_priv
);
3252 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3253 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3254 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3255 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3256 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3257 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3259 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3260 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3261 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3262 const struct drm_i915_gem_object_ops
*ops
);
3263 struct drm_i915_gem_object
*
3264 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3265 struct drm_i915_gem_object
*
3266 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3267 const void *data
, size_t size
);
3268 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3269 void i915_gem_free_object(struct drm_gem_object
*obj
);
3271 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3273 /* A single pass should suffice to release all the freed objects (along
3274 * most call paths) , but be a little more paranoid in that freeing
3275 * the objects does take a little amount of time, during which the rcu
3276 * callbacks could have added new objects into the freed list, and
3277 * armed the work again.
3281 } while (flush_work(&i915
->mm
.free_work
));
3284 struct i915_vma
* __must_check
3285 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3286 const struct i915_ggtt_view
*view
,
3291 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3292 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3294 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3296 static inline int __sg_page_count(const struct scatterlist
*sg
)
3298 return sg
->length
>> PAGE_SHIFT
;
3301 struct scatterlist
*
3302 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3303 unsigned int n
, unsigned int *offset
);
3306 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3310 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3314 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3317 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3318 struct sg_table
*pages
);
3319 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3321 static inline int __must_check
3322 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3324 might_lock(&obj
->mm
.lock
);
3326 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3329 return __i915_gem_object_get_pages(obj
);
3333 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3335 GEM_BUG_ON(!obj
->mm
.pages
);
3337 atomic_inc(&obj
->mm
.pages_pin_count
);
3341 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3343 return atomic_read(&obj
->mm
.pages_pin_count
);
3347 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3349 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3350 GEM_BUG_ON(!obj
->mm
.pages
);
3352 atomic_dec(&obj
->mm
.pages_pin_count
);
3356 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3358 __i915_gem_object_unpin_pages(obj
);
3361 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3366 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3367 enum i915_mm_subclass subclass
);
3368 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3370 enum i915_map_type
{
3376 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3377 * @obj: the object to map into kernel address space
3378 * @type: the type of mapping, used to select pgprot_t
3380 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3381 * pages and then returns a contiguous mapping of the backing storage into
3382 * the kernel address space. Based on the @type of mapping, the PTE will be
3383 * set to either WriteBack or WriteCombine (via pgprot_t).
3385 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3386 * mapping is no longer required.
3388 * Returns the pointer through which to access the mapped object, or an
3389 * ERR_PTR() on error.
3391 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3392 enum i915_map_type type
);
3395 * i915_gem_object_unpin_map - releases an earlier mapping
3396 * @obj: the object to unmap
3398 * After pinning the object and mapping its pages, once you are finished
3399 * with your access, call i915_gem_object_unpin_map() to release the pin
3400 * upon the mapping. Once the pin count reaches zero, that mapping may be
3403 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3405 i915_gem_object_unpin_pages(obj
);
3408 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3409 unsigned int *needs_clflush
);
3410 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3411 unsigned int *needs_clflush
);
3412 #define CLFLUSH_BEFORE BIT(0)
3413 #define CLFLUSH_AFTER BIT(1)
3414 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3417 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3419 i915_gem_object_unpin_pages(obj
);
3422 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3423 void i915_vma_move_to_active(struct i915_vma
*vma
,
3424 struct drm_i915_gem_request
*req
,
3425 unsigned int flags
);
3426 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3427 struct drm_device
*dev
,
3428 struct drm_mode_create_dumb
*args
);
3429 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3430 uint32_t handle
, uint64_t *offset
);
3431 int i915_gem_mmap_gtt_version(void);
3433 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3434 struct drm_i915_gem_object
*new,
3435 unsigned frontbuffer_bits
);
3437 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3439 struct drm_i915_gem_request
*
3440 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3442 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3444 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3446 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3449 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3451 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3454 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3456 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3459 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3461 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3464 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3466 return READ_ONCE(error
->reset_count
);
3469 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3470 struct intel_engine_cs
*engine
)
3472 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3475 struct drm_i915_gem_request
*
3476 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3477 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3478 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3479 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3480 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3481 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3482 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3483 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3484 struct drm_i915_gem_request
*request
);
3486 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3487 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3488 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3489 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3490 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3491 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3492 unsigned int flags
);
3493 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3494 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3495 int i915_gem_fault(struct vm_fault
*vmf
);
3496 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3499 struct intel_rps_client
*rps
);
3500 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3503 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3506 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3508 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3510 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3511 struct i915_vma
* __must_check
3512 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3514 const struct i915_ggtt_view
*view
);
3515 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3516 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3518 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3519 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3521 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3522 enum i915_cache_level cache_level
);
3524 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3525 struct dma_buf
*dma_buf
);
3527 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3528 struct drm_gem_object
*gem_obj
, int flags
);
3530 static inline struct i915_hw_ppgtt
*
3531 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3533 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3536 /* i915_gem_fence_reg.c */
3537 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3538 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3540 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3541 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3543 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3544 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3545 struct sg_table
*pages
);
3546 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3547 struct sg_table
*pages
);
3549 static inline struct i915_gem_context
*
3550 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3552 return idr_find(&file_priv
->context_idr
, id
);
3555 static inline struct i915_gem_context
*
3556 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3558 struct i915_gem_context
*ctx
;
3561 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3562 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3569 static inline struct intel_timeline
*
3570 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3571 struct intel_engine_cs
*engine
)
3573 struct i915_address_space
*vm
;
3575 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3576 return &vm
->timeline
.engine
[engine
->id
];
3579 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3580 struct drm_file
*file
);
3581 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3582 struct i915_gem_context
*ctx
,
3583 uint32_t *reg_state
);
3585 /* i915_gem_evict.c */
3586 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3587 u64 min_size
, u64 alignment
,
3588 unsigned cache_level
,
3591 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3592 struct drm_mm_node
*node
,
3593 unsigned int flags
);
3594 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3596 /* belongs in i915_gem_gtt.h */
3597 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3600 if (INTEL_GEN(dev_priv
) < 6)
3601 intel_gtt_chipset_flush();
3604 /* i915_gem_stolen.c */
3605 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3606 struct drm_mm_node
*node
, u64 size
,
3607 unsigned alignment
);
3608 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3609 struct drm_mm_node
*node
, u64 size
,
3610 unsigned alignment
, u64 start
,
3612 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3613 struct drm_mm_node
*node
);
3614 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3615 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3616 struct drm_i915_gem_object
*
3617 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3618 struct drm_i915_gem_object
*
3619 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3624 /* i915_gem_internal.c */
3625 struct drm_i915_gem_object
*
3626 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3629 /* i915_gem_shrinker.c */
3630 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3631 unsigned long target
,
3633 #define I915_SHRINK_PURGEABLE 0x1
3634 #define I915_SHRINK_UNBOUND 0x2
3635 #define I915_SHRINK_BOUND 0x4
3636 #define I915_SHRINK_ACTIVE 0x8
3637 #define I915_SHRINK_VMAPS 0x10
3638 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3639 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3640 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3643 /* i915_gem_tiling.c */
3644 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3646 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3648 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3649 i915_gem_object_is_tiled(obj
);
3652 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3653 unsigned int tiling
, unsigned int stride
);
3654 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3655 unsigned int tiling
, unsigned int stride
);
3657 /* i915_debugfs.c */
3658 #ifdef CONFIG_DEBUG_FS
3659 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3660 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3661 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3663 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3664 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3666 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3669 /* i915_gpu_error.c */
3670 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3673 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3674 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3675 const struct i915_gpu_state
*gpu
);
3676 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3677 struct drm_i915_private
*i915
,
3678 size_t count
, loff_t pos
);
3679 static inline void i915_error_state_buf_release(
3680 struct drm_i915_error_state_buf
*eb
)
3685 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3686 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3688 const char *error_msg
);
3690 static inline struct i915_gpu_state
*
3691 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3693 kref_get(&gpu
->ref
);
3697 void __i915_gpu_state_free(struct kref
*kref
);
3698 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3701 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3704 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3705 void i915_reset_error_state(struct drm_i915_private
*i915
);
3709 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3711 const char *error_msg
)
3715 static inline struct i915_gpu_state
*
3716 i915_first_error_state(struct drm_i915_private
*i915
)
3721 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3727 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3729 /* i915_cmd_parser.c */
3730 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3731 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3732 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3733 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3734 struct drm_i915_gem_object
*batch_obj
,
3735 struct drm_i915_gem_object
*shadow_batch_obj
,
3736 u32 batch_start_offset
,
3741 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3742 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3743 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3744 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3746 /* i915_suspend.c */
3747 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3748 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3751 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3752 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3754 /* intel_lpe_audio.c */
3755 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
3756 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
3757 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
3758 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
3759 enum pipe pipe
, enum port port
,
3760 const void *eld
, int ls_clock
, bool dp_output
);
3763 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3764 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3765 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3768 extern struct i2c_adapter
*
3769 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3770 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3771 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3772 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3774 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3776 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3779 void intel_bios_init(struct drm_i915_private
*dev_priv
);
3780 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3781 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3782 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3783 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3784 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3785 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3786 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3787 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3789 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3793 /* intel_opregion.c */
3795 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3796 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3797 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3798 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3799 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3801 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3803 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3805 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3806 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3807 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3808 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3812 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3817 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3821 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3829 extern void intel_register_dsm_handler(void);
3830 extern void intel_unregister_dsm_handler(void);
3832 static inline void intel_register_dsm_handler(void) { return; }
3833 static inline void intel_unregister_dsm_handler(void) { return; }
3834 #endif /* CONFIG_ACPI */
3836 /* intel_device_info.c */
3837 static inline struct intel_device_info
*
3838 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3840 return (struct intel_device_info
*)&dev_priv
->info
;
3843 const char *intel_platform_name(enum intel_platform platform
);
3844 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3845 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3848 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3849 extern int intel_modeset_init(struct drm_device
*dev
);
3850 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3851 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3852 extern int intel_connector_register(struct drm_connector
*);
3853 extern void intel_connector_unregister(struct drm_connector
*);
3854 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3856 extern void intel_display_resume(struct drm_device
*dev
);
3857 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3858 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3859 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3860 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
3861 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3862 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3865 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3866 struct drm_file
*file
);
3869 extern struct intel_overlay_error_state
*
3870 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3871 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3872 struct intel_overlay_error_state
*error
);
3874 extern struct intel_display_error_state
*
3875 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3876 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3877 struct intel_display_error_state
*error
);
3879 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3880 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3881 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
3882 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
3884 /* intel_sideband.c */
3885 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3886 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3887 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3888 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3889 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3890 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3891 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3892 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3893 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3894 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3895 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3896 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3897 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3898 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3899 enum intel_sbi_destination destination
);
3900 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3901 enum intel_sbi_destination destination
);
3902 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3903 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3905 /* intel_dpio_phy.c */
3906 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
3907 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3908 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3909 enum port port
, u32 margin
, u32 scale
,
3910 u32 enable
, u32 deemphasis
);
3911 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3912 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3913 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3915 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3917 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3918 uint8_t lane_count
);
3919 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3920 uint8_t lane_lat_optim_mask
);
3921 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3923 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3924 u32 deemph_reg_value
, u32 margin_reg_value
,
3925 bool uniq_trans_scale
);
3926 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3928 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3929 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3930 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3931 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3933 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3934 u32 demph_reg_value
, u32 preemph_reg_value
,
3935 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3936 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3937 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3938 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3940 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3941 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3942 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
3943 const i915_reg_t reg
);
3945 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3946 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3948 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3949 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3950 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3951 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3953 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3954 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3955 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3956 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3958 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3959 * will be implemented using 2 32-bit writes in an arbitrary order with
3960 * an arbitrary delay between them. This can cause the hardware to
3961 * act upon the intermediate value, possibly leading to corruption and
3962 * machine death. For this reason we do not support I915_WRITE64, or
3963 * dev_priv->uncore.funcs.mmio_writeq.
3965 * When reading a 64-bit value as two 32-bit values, the delay may cause
3966 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3967 * occasionally a 64-bit register does not actualy support a full readq
3968 * and must be read using two 32-bit reads.
3970 * You have been warned.
3972 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3974 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3975 u32 upper, lower, old_upper, loop = 0; \
3976 upper = I915_READ(upper_reg); \
3978 old_upper = upper; \
3979 lower = I915_READ(lower_reg); \
3980 upper = I915_READ(upper_reg); \
3981 } while (upper != old_upper && loop++ < 2); \
3982 (u64)upper << 32 | lower; })
3984 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3985 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3987 #define __raw_read(x, s) \
3988 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3991 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3994 #define __raw_write(x, s) \
3995 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3996 i915_reg_t reg, uint##x##_t val) \
3998 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4013 /* These are untraced mmio-accessors that are only valid to be used inside
4014 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4017 * Think twice, and think again, before using these.
4019 * As an example, these accessors can possibly be used between:
4021 * spin_lock_irq(&dev_priv->uncore.lock);
4022 * intel_uncore_forcewake_get__locked();
4026 * intel_uncore_forcewake_put__locked();
4027 * spin_unlock_irq(&dev_priv->uncore.lock);
4030 * Note: some registers may not need forcewake held, so
4031 * intel_uncore_forcewake_{get,put} can be omitted, see
4032 * intel_uncore_forcewake_for_reg().
4034 * Certain architectures will die if the same cacheline is concurrently accessed
4035 * by different clients (e.g. on Ivybridge). Access to registers should
4036 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4037 * a more localised lock guarding all access to that bank of registers.
4039 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4040 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4041 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4042 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4044 /* "Broadcast RGB" property */
4045 #define INTEL_BROADCAST_RGB_AUTO 0
4046 #define INTEL_BROADCAST_RGB_FULL 1
4047 #define INTEL_BROADCAST_RGB_LIMITED 2
4049 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4051 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4052 return VLV_VGACNTRL
;
4053 else if (INTEL_GEN(dev_priv
) >= 5)
4054 return CPU_VGACNTRL
;
4059 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4061 unsigned long j
= msecs_to_jiffies(m
);
4063 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4066 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4068 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4071 static inline unsigned long
4072 timespec_to_jiffies_timeout(const struct timespec
*value
)
4074 unsigned long j
= timespec_to_jiffies(value
);
4076 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4080 * If you need to wait X milliseconds between events A and B, but event B
4081 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4082 * when event A happened, then just before event B you call this function and
4083 * pass the timestamp as the first argument, and X as the second argument.
4086 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4088 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4091 * Don't re-read the value of "jiffies" every time since it may change
4092 * behind our back and break the math.
4094 tmp_jiffies
= jiffies
;
4095 target_jiffies
= timestamp_jiffies
+
4096 msecs_to_jiffies_timeout(to_wait_ms
);
4098 if (time_after(target_jiffies
, tmp_jiffies
)) {
4099 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4100 while (remaining_jiffies
)
4102 schedule_timeout_uninterruptible(remaining_jiffies
);
4107 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4109 struct intel_engine_cs
*engine
= req
->engine
;
4112 /* Note that the engine may have wrapped around the seqno, and
4113 * so our request->global_seqno will be ahead of the hardware,
4114 * even though it completed the request before wrapping. We catch
4115 * this by kicking all the waiters before resetting the seqno
4116 * in hardware, and also signal the fence.
4118 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4121 /* The request was dequeued before we were awoken. We check after
4122 * inspecting the hw to confirm that this was the same request
4123 * that generated the HWS update. The memory barriers within
4124 * the request execution are sufficient to ensure that a check
4125 * after reading the value from hw matches this request.
4127 seqno
= i915_gem_request_global_seqno(req
);
4131 /* Before we do the heavier coherent read of the seqno,
4132 * check the value (hopefully) in the CPU cacheline.
4134 if (__i915_gem_request_completed(req
, seqno
))
4137 /* Ensure our read of the seqno is coherent so that we
4138 * do not "miss an interrupt" (i.e. if this is the last
4139 * request and the seqno write from the GPU is not visible
4140 * by the time the interrupt fires, we will see that the
4141 * request is incomplete and go back to sleep awaiting
4142 * another interrupt that will never come.)
4144 * Strictly, we only need to do this once after an interrupt,
4145 * but it is easier and safer to do it every time the waiter
4148 if (engine
->irq_seqno_barrier
&&
4149 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4150 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4152 /* The ordering of irq_posted versus applying the barrier
4153 * is crucial. The clearing of the current irq_posted must
4154 * be visible before we perform the barrier operation,
4155 * such that if a subsequent interrupt arrives, irq_posted
4156 * is reasserted and our task rewoken (which causes us to
4157 * do another __i915_request_irq_complete() immediately
4158 * and reapply the barrier). Conversely, if the clear
4159 * occurs after the barrier, then an interrupt that arrived
4160 * whilst we waited on the barrier would not trigger a
4161 * barrier on the next pass, and the read may not see the
4164 engine
->irq_seqno_barrier(engine
);
4166 /* If we consume the irq, but we are no longer the bottom-half,
4167 * the real bottom-half may not have serialised their own
4168 * seqno check with the irq-barrier (i.e. may have inspected
4169 * the seqno before we believe it coherent since they see
4170 * irq_posted == false but we are still running).
4172 spin_lock_irq(&b
->irq_lock
);
4173 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4174 /* Note that if the bottom-half is changed as we
4175 * are sending the wake-up, the new bottom-half will
4176 * be woken by whomever made the change. We only have
4177 * to worry about when we steal the irq-posted for
4180 wake_up_process(b
->irq_wait
->tsk
);
4181 spin_unlock_irq(&b
->irq_lock
);
4183 if (__i915_gem_request_completed(req
, seqno
))
4190 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4191 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4193 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4194 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4195 * perform the operation. To check beforehand, pass in the parameters to
4196 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4197 * you only need to pass in the minor offsets, page-aligned pointers are
4200 * For just checking for SSE4.1, in the foreknowledge that the future use
4201 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4203 #define i915_can_memcpy_from_wc(dst, src, len) \
4204 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4206 #define i915_has_memcpy_from_wc() \
4207 i915_memcpy_from_wc(NULL, NULL, 0)
4210 int remap_io_mapping(struct vm_area_struct
*vma
,
4211 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4212 struct io_mapping
*iomap
);
4214 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object
*obj
)
4216 return (obj
->cache_level
!= I915_CACHE_NONE
||
4217 HAS_LLC(to_i915(obj
->base
.dev
)));