1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_fence_reg.h"
64 #include "i915_gem_object.h"
65 #include "i915_gem_gtt.h"
66 #include "i915_gem_render_state.h"
67 #include "i915_gem_request.h"
68 #include "i915_gem_timeline.h"
72 #include "intel_gvt.h"
74 /* General customization:
77 #define DRIVER_NAME "i915"
78 #define DRIVER_DESC "Intel Graphics"
79 #define DRIVER_DATE "20161121"
80 #define DRIVER_TIMESTAMP 1479717903
83 /* Many gcc seem to no see through this and fall over :( */
85 #define WARN_ON(x) ({ \
86 bool __i915_warn_cond = (x); \
87 if (__builtin_constant_p(__i915_warn_cond)) \
88 BUILD_BUG_ON(__i915_warn_cond); \
89 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
98 (long) (x), __func__);
100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
101 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
102 * which may not necessarily be a user visible problem. This will either
103 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
104 * enable distros and users to tailor their preferred amount of i915 abrt
107 #define I915_STATE_WARN(condition, format...) ({ \
108 int __ret_warn_on = !!(condition); \
109 if (unlikely(__ret_warn_on)) \
110 if (!WARN(i915.verbose_state_checks, format)) \
112 unlikely(__ret_warn_on); \
115 #define I915_STATE_WARN_ON(x) \
116 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
118 bool __i915_inject_load_failure(const char *func
, int line
);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
122 static inline const char *yesno(bool v
)
124 return v
? "yes" : "no";
127 static inline const char *onoff(bool v
)
129 return v
? "on" : "off";
132 static inline const char *enableddisabled(bool v
)
134 return v
? "enabled" : "disabled";
143 I915_MAX_PIPES
= _PIPE_EDP
145 #define pipe_name(p) ((p) + 'A')
157 static inline const char *transcoder_name(enum transcoder transcoder
)
159 switch (transcoder
) {
168 case TRANSCODER_DSI_A
:
170 case TRANSCODER_DSI_C
:
177 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
179 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
183 * Global legacy plane identifier. Valid only for primary/sprite
184 * planes on pre-g4x, and only for primary planes on g4x+.
191 #define plane_name(p) ((p) + 'A')
193 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
196 * Per-pipe plane identifier.
197 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
198 * number of planes per CRTC. Not all platforms really have this many planes,
199 * which means some arrays of size I915_MAX_PLANES may have unused entries
200 * between the topmost sprite plane and the cursor plane.
202 * This is expected to be passed to various register macros
203 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
213 #define for_each_plane_id_on_crtc(__crtc, __p) \
214 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
215 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
226 #define port_name(p) ((p) + 'A')
228 #define I915_NUM_PHYS_VLV 2
240 enum intel_display_power_domain
{
244 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
245 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
246 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
247 POWER_DOMAIN_TRANSCODER_A
,
248 POWER_DOMAIN_TRANSCODER_B
,
249 POWER_DOMAIN_TRANSCODER_C
,
250 POWER_DOMAIN_TRANSCODER_EDP
,
251 POWER_DOMAIN_TRANSCODER_DSI_A
,
252 POWER_DOMAIN_TRANSCODER_DSI_C
,
253 POWER_DOMAIN_PORT_DDI_A_LANES
,
254 POWER_DOMAIN_PORT_DDI_B_LANES
,
255 POWER_DOMAIN_PORT_DDI_C_LANES
,
256 POWER_DOMAIN_PORT_DDI_D_LANES
,
257 POWER_DOMAIN_PORT_DDI_E_LANES
,
258 POWER_DOMAIN_PORT_DSI
,
259 POWER_DOMAIN_PORT_CRT
,
260 POWER_DOMAIN_PORT_OTHER
,
269 POWER_DOMAIN_MODESET
,
275 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
276 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
277 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
278 #define POWER_DOMAIN_TRANSCODER(tran) \
279 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
280 (tran) + POWER_DOMAIN_TRANSCODER_A)
284 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
296 #define for_each_hpd_pin(__pin) \
297 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
299 struct i915_hotplug
{
300 struct work_struct hotplug_work
;
303 unsigned long last_jiffies
;
308 HPD_MARK_DISABLED
= 2
310 } stats
[HPD_NUM_PINS
];
312 struct delayed_work reenable_work
;
314 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
317 struct work_struct dig_port_work
;
319 struct work_struct poll_init_work
;
323 * if we get a HPD irq from DP and a HPD irq from non-DP
324 * the non-DP HPD could block the workqueue on a mode config
325 * mutex getting, that userspace may have taken. However
326 * userspace is waiting on the DP workqueue to run which is
327 * blocked behind the non-DP one.
329 struct workqueue_struct
*dp_wq
;
332 #define I915_GEM_GPU_DOMAINS \
333 (I915_GEM_DOMAIN_RENDER | \
334 I915_GEM_DOMAIN_SAMPLER | \
335 I915_GEM_DOMAIN_COMMAND | \
336 I915_GEM_DOMAIN_INSTRUCTION | \
337 I915_GEM_DOMAIN_VERTEX)
339 #define for_each_pipe(__dev_priv, __p) \
340 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
341 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
342 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
343 for_each_if ((__mask) & (1 << (__p)))
344 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
346 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
348 #define for_each_sprite(__dev_priv, __p, __s) \
350 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
353 #define for_each_port_masked(__port, __ports_mask) \
354 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
355 for_each_if ((__ports_mask) & (1 << (__port)))
357 #define for_each_crtc(dev, crtc) \
358 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
360 #define for_each_intel_plane(dev, intel_plane) \
361 list_for_each_entry(intel_plane, \
362 &(dev)->mode_config.plane_list, \
365 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
366 list_for_each_entry(intel_plane, \
367 &(dev)->mode_config.plane_list, \
369 for_each_if ((plane_mask) & \
370 (1 << drm_plane_index(&intel_plane->base)))
372 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
373 list_for_each_entry(intel_plane, \
374 &(dev)->mode_config.plane_list, \
376 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
378 #define for_each_intel_crtc(dev, intel_crtc) \
379 list_for_each_entry(intel_crtc, \
380 &(dev)->mode_config.crtc_list, \
383 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
384 list_for_each_entry(intel_crtc, \
385 &(dev)->mode_config.crtc_list, \
387 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
389 #define for_each_intel_encoder(dev, intel_encoder) \
390 list_for_each_entry(intel_encoder, \
391 &(dev)->mode_config.encoder_list, \
394 #define for_each_intel_connector(dev, intel_connector) \
395 list_for_each_entry(intel_connector, \
396 &(dev)->mode_config.connector_list, \
399 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
400 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
401 for_each_if ((intel_encoder)->base.crtc == (__crtc))
403 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
404 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
405 for_each_if ((intel_connector)->base.encoder == (__encoder))
407 #define for_each_power_domain(domain, mask) \
408 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
409 for_each_if ((1 << (domain)) & (mask))
411 struct drm_i915_private
;
412 struct i915_mm_struct
;
413 struct i915_mmu_object
;
415 struct drm_i915_file_private
{
416 struct drm_i915_private
*dev_priv
;
417 struct drm_file
*file
;
421 struct list_head request_list
;
422 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
423 * chosen to prevent the CPU getting more than a frame ahead of the GPU
424 * (when using lax throttling for the frontbuffer). We also use it to
425 * offer free GPU waitboosts for severely congested workloads.
427 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
429 struct idr context_idr
;
431 struct intel_rps_client
{
432 struct list_head link
;
436 unsigned int bsd_engine
;
438 /* Client can have a maximum of 3 contexts banned before
439 * it is denied of creating new contexts. As one context
440 * ban needs 4 consecutive hangs, and more if there is
441 * progress in between, this is a last resort stop gap measure
442 * to limit the badly behaving clients access to gpu.
444 #define I915_MAX_CLIENT_CONTEXT_BANS 3
448 /* Used by dp and fdi links */
449 struct intel_link_m_n
{
457 void intel_link_compute_m_n(int bpp
, int nlanes
,
458 int pixel_clock
, int link_clock
,
459 struct intel_link_m_n
*m_n
);
461 /* Interface history:
464 * 1.2: Add Power Management
465 * 1.3: Add vblank support
466 * 1.4: Fix cmdbuffer path, add heap destroy
467 * 1.5: Add vblank pipe configuration
468 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
469 * - Support vertical blank on secondary display pipe
471 #define DRIVER_MAJOR 1
472 #define DRIVER_MINOR 6
473 #define DRIVER_PATCHLEVEL 0
475 struct opregion_header
;
476 struct opregion_acpi
;
477 struct opregion_swsci
;
478 struct opregion_asle
;
480 struct intel_opregion
{
481 struct opregion_header
*header
;
482 struct opregion_acpi
*acpi
;
483 struct opregion_swsci
*swsci
;
484 u32 swsci_gbda_sub_functions
;
485 u32 swsci_sbcb_sub_functions
;
486 struct opregion_asle
*asle
;
491 struct work_struct asle_work
;
493 #define OPREGION_SIZE (8*1024)
495 struct intel_overlay
;
496 struct intel_overlay_error_state
;
498 struct sdvo_device_mapping
{
507 struct intel_connector
;
508 struct intel_encoder
;
509 struct intel_atomic_state
;
510 struct intel_crtc_state
;
511 struct intel_initial_plane_config
;
516 struct drm_i915_display_funcs
{
517 int (*get_display_clock_speed
)(struct drm_i915_private
*dev_priv
);
518 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
519 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
520 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
521 struct intel_crtc
*intel_crtc
,
522 struct intel_crtc_state
*newstate
);
523 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
524 struct intel_crtc_state
*cstate
);
525 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
526 struct intel_crtc_state
*cstate
);
527 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
528 struct intel_crtc_state
*cstate
);
529 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
530 void (*update_wm
)(struct intel_crtc
*crtc
);
531 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
532 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
533 /* Returns the active state of the crtc, and if the crtc is active,
534 * fills out the pipe-config with the hw state. */
535 bool (*get_pipe_config
)(struct intel_crtc
*,
536 struct intel_crtc_state
*);
537 void (*get_initial_plane_config
)(struct intel_crtc
*,
538 struct intel_initial_plane_config
*);
539 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
540 struct intel_crtc_state
*crtc_state
);
541 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
542 struct drm_atomic_state
*old_state
);
543 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
544 struct drm_atomic_state
*old_state
);
545 void (*update_crtcs
)(struct drm_atomic_state
*state
,
546 unsigned int *crtc_vblank_mask
);
547 void (*audio_codec_enable
)(struct drm_connector
*connector
,
548 struct intel_encoder
*encoder
,
549 const struct drm_display_mode
*adjusted_mode
);
550 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
551 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
552 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
553 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
554 struct drm_framebuffer
*fb
,
555 struct drm_i915_gem_object
*obj
,
556 struct drm_i915_gem_request
*req
,
558 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
559 /* clock updates for mode set */
561 /* render clock increase/decrease */
562 /* display clock increase/decrease */
563 /* pll clock increase/decrease */
565 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
566 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
569 enum forcewake_domain_id
{
570 FW_DOMAIN_ID_RENDER
= 0,
571 FW_DOMAIN_ID_BLITTER
,
577 enum forcewake_domains
{
578 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
579 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
580 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
581 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
586 #define FW_REG_READ (1)
587 #define FW_REG_WRITE (2)
589 enum decoupled_power_domain
{
590 GEN9_DECOUPLED_PD_BLITTER
= 0,
591 GEN9_DECOUPLED_PD_RENDER
,
592 GEN9_DECOUPLED_PD_MEDIA
,
593 GEN9_DECOUPLED_PD_ALL
597 GEN9_DECOUPLED_OP_WRITE
= 0,
598 GEN9_DECOUPLED_OP_READ
601 enum forcewake_domains
602 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
603 i915_reg_t reg
, unsigned int op
);
605 struct intel_uncore_funcs
{
606 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
607 enum forcewake_domains domains
);
608 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
609 enum forcewake_domains domains
);
611 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
612 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
613 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
614 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
616 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
617 uint8_t val
, bool trace
);
618 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
619 uint16_t val
, bool trace
);
620 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
621 uint32_t val
, bool trace
);
624 struct intel_forcewake_range
{
628 enum forcewake_domains domains
;
631 struct intel_uncore
{
632 spinlock_t lock
; /** lock is also taken in irq contexts. */
634 const struct intel_forcewake_range
*fw_domains_table
;
635 unsigned int fw_domains_table_entries
;
637 struct intel_uncore_funcs funcs
;
641 enum forcewake_domains fw_domains
;
642 enum forcewake_domains fw_domains_active
;
644 struct intel_uncore_forcewake_domain
{
645 struct drm_i915_private
*i915
;
646 enum forcewake_domain_id id
;
647 enum forcewake_domains mask
;
649 struct hrtimer timer
;
656 } fw_domain
[FW_DOMAIN_ID_COUNT
];
658 int unclaimed_mmio_check
;
661 /* Iterate over initialised fw domains */
662 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
663 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
664 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
666 for_each_if ((mask__) & (domain__)->mask)
668 #define for_each_fw_domain(domain__, dev_priv__) \
669 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
671 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
672 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
673 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
676 struct work_struct work
;
678 uint32_t *dmc_payload
;
679 uint32_t dmc_fw_size
;
682 i915_reg_t mmioaddr
[8];
683 uint32_t mmiodata
[8];
685 uint32_t allowed_dc_mask
;
688 #define DEV_INFO_FOR_EACH_FLAG(func) \
689 /* Keep is_* in chronological order */ \
697 func(is_broadwater); \
698 func(is_crestline); \
699 func(is_ivybridge); \
700 func(is_valleyview); \
701 func(is_cherryview); \
703 func(is_broadwell); \
706 func(is_geminilake); \
709 func(is_alpha_support); \
710 /* Keep has_* in alphabetical order */ \
711 func(has_64bit_reloc); \
716 func(has_fpga_dbg); \
717 func(has_gmbus_irq); \
718 func(has_gmch_display); \
721 func(has_hw_contexts); \
724 func(has_logical_ring_contexts); \
726 func(has_pipe_cxsr); \
727 func(has_pooled_eu); \
731 func(has_resource_streamer); \
732 func(has_runtime_pm); \
734 func(cursor_needs_physical); \
735 func(hws_needs_physical); \
736 func(overlay_needs_physical); \
738 func(has_decoupled_mmio)
740 struct sseu_dev_info
{
746 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
749 u8 has_subslice_pg
:1;
753 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
755 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
758 struct intel_device_info
{
759 u32 display_mmio_offset
;
762 u8 num_sprites
[I915_MAX_PIPES
];
765 u8 ring_mask
; /* Rings supported by the HW */
767 #define DEFINE_FLAG(name) u8 name:1
768 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
770 u16 ddb_size
; /* in blocks */
771 /* Register offsets for the various display pipes and transcoders */
772 int pipe_offsets
[I915_MAX_TRANSCODERS
];
773 int trans_offsets
[I915_MAX_TRANSCODERS
];
774 int palette_offsets
[I915_MAX_PIPES
];
775 int cursor_offsets
[I915_MAX_PIPES
];
777 /* Slice/subslice/EU info */
778 struct sseu_dev_info sseu
;
781 u16 degamma_lut_size
;
786 struct intel_display_error_state
;
788 struct drm_i915_error_state
{
791 struct timeval boottime
;
792 struct timeval uptime
;
794 struct drm_i915_private
*i915
;
801 struct intel_device_info device_info
;
803 /* Generic register state */
811 u32 error
; /* gen6+ */
812 u32 err_int
; /* gen7 */
813 u32 fault_data0
; /* gen8, gen9 */
814 u32 fault_data1
; /* gen8, gen9 */
821 u64 fence
[I915_MAX_NUM_FENCES
];
822 struct intel_overlay_error_state
*overlay
;
823 struct intel_display_error_state
*display
;
824 struct drm_i915_error_object
*semaphore
;
825 struct drm_i915_error_object
*guc_log
;
827 struct drm_i915_error_engine
{
829 /* Software tracked state */
832 unsigned long hangcheck_timestamp
;
833 bool hangcheck_stalled
;
834 enum intel_engine_hangcheck_action hangcheck_action
;
835 struct i915_address_space
*vm
;
838 /* position of active request inside the ring */
839 u32 rq_head
, rq_post
, rq_tail
;
841 /* our own tracking of ring head and tail */
864 u32 rc_psmi
; /* sleep state */
865 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
866 struct intel_instdone instdone
;
868 struct drm_i915_error_object
{
874 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
876 struct drm_i915_error_object
*wa_ctx
;
878 struct drm_i915_error_request
{
886 } *requests
, execlist
[2];
888 struct drm_i915_error_waiter
{
889 char comm
[TASK_COMM_LEN
];
903 char comm
[TASK_COMM_LEN
];
905 } engine
[I915_NUM_ENGINES
];
907 struct drm_i915_error_buffer
{
910 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
914 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
921 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
922 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
923 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
926 enum i915_cache_level
{
928 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
929 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
930 caches, eg sampler/render caches, and the
931 large Last-Level-Cache. LLC is coherent with
932 the CPU, but L3 is only visible to the GPU. */
933 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
936 #define DEFAULT_CONTEXT_HANDLE 0
939 * struct i915_gem_context - as the name implies, represents a context.
940 * @ref: reference count.
941 * @user_handle: userspace tracking identity for this context.
942 * @remap_slice: l3 row remapping information.
943 * @flags: context specific flags:
944 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
945 * @file_priv: filp associated with this context (NULL for global default
947 * @hang_stats: information about the role of this context in possible GPU
949 * @ppgtt: virtual memory space used by this context.
950 * @legacy_hw_ctx: render context backing object and whether it is correctly
951 * initialized (legacy ring submission mechanism only).
952 * @link: link in the global list of contexts.
954 * Contexts are memory images used by the hardware to store copies of their
957 struct i915_gem_context
{
959 struct drm_i915_private
*i915
;
960 struct drm_i915_file_private
*file_priv
;
961 struct i915_hw_ppgtt
*ppgtt
;
966 #define CONTEXT_NO_ZEROMAP BIT(0)
967 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
969 /* Unique identifier for this context, used by the hw for tracking */
972 int priority
; /* greater priorities are serviced first */
976 struct intel_context
{
977 struct i915_vma
*state
;
978 struct intel_ring
*ring
;
979 uint32_t *lrc_reg_state
;
983 } engine
[I915_NUM_ENGINES
];
986 struct atomic_notifier_head status_notifier
;
987 bool execlists_force_single_submission
;
989 struct list_head link
;
996 unsigned int guilty_count
; /* guilty of a hang */
997 unsigned int active_count
; /* active during hang */
999 #define CONTEXT_SCORE_GUILTY 10
1000 #define CONTEXT_SCORE_BAN_THRESHOLD 40
1001 /* Accumulated score of hangs caused by this context */
1014 /* This is always the inner lock when overlapping with struct_mutex and
1015 * it's the outer lock when overlapping with stolen_lock. */
1018 unsigned int possible_framebuffer_bits
;
1019 unsigned int busy_bits
;
1020 unsigned int visible_pipes_mask
;
1021 struct intel_crtc
*crtc
;
1023 struct drm_mm_node compressed_fb
;
1024 struct drm_mm_node
*compressed_llb
;
1031 bool underrun_detected
;
1032 struct work_struct underrun_work
;
1034 struct intel_fbc_state_cache
{
1036 unsigned int mode_flags
;
1037 uint32_t hsw_bdw_pixel_rate
;
1041 unsigned int rotation
;
1048 u64 ilk_ggtt_offset
;
1049 uint32_t pixel_format
;
1050 unsigned int stride
;
1052 unsigned int tiling_mode
;
1056 struct intel_fbc_reg_params
{
1060 unsigned int fence_y_offset
;
1065 uint32_t pixel_format
;
1066 unsigned int stride
;
1073 struct intel_fbc_work
{
1075 u32 scheduled_vblank
;
1076 struct work_struct work
;
1079 const char *no_fbc_reason
;
1083 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1084 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1085 * parsing for same resolution.
1087 enum drrs_refresh_rate_type
{
1090 DRRS_MAX_RR
, /* RR count */
1093 enum drrs_support_type
{
1094 DRRS_NOT_SUPPORTED
= 0,
1095 STATIC_DRRS_SUPPORT
= 1,
1096 SEAMLESS_DRRS_SUPPORT
= 2
1102 struct delayed_work work
;
1103 struct intel_dp
*dp
;
1104 unsigned busy_frontbuffer_bits
;
1105 enum drrs_refresh_rate_type refresh_rate_type
;
1106 enum drrs_support_type type
;
1113 struct intel_dp
*enabled
;
1115 struct delayed_work work
;
1116 unsigned busy_frontbuffer_bits
;
1118 bool aux_frame_sync
;
1123 PCH_NONE
= 0, /* No PCH present */
1124 PCH_IBX
, /* Ibexpeak PCH */
1125 PCH_CPT
, /* Cougarpoint PCH */
1126 PCH_LPT
, /* Lynxpoint PCH */
1127 PCH_SPT
, /* Sunrisepoint PCH */
1128 PCH_KBP
, /* Kabypoint PCH */
1132 enum intel_sbi_destination
{
1137 #define QUIRK_PIPEA_FORCE (1<<0)
1138 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1139 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1140 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1141 #define QUIRK_PIPEB_FORCE (1<<4)
1142 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1145 struct intel_fbc_work
;
1147 struct intel_gmbus
{
1148 struct i2c_adapter adapter
;
1149 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1152 i915_reg_t gpio_reg
;
1153 struct i2c_algo_bit_data bit_algo
;
1154 struct drm_i915_private
*dev_priv
;
1157 struct i915_suspend_saved_registers
{
1159 u32 saveFBC_CONTROL
;
1160 u32 saveCACHE_MODE_0
;
1161 u32 saveMI_ARB_STATE
;
1165 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1166 u32 savePCH_PORT_HOTPLUG
;
1170 struct vlv_s0ix_state
{
1177 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1178 u32 media_max_req_count
;
1179 u32 gfx_max_req_count
;
1205 u32 rp_down_timeout
;
1211 /* Display 1 CZ domain */
1216 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1218 /* GT SA CZ domain */
1225 /* Display 2 CZ domain */
1229 u32 clock_gate_dis2
;
1232 struct intel_rps_ei
{
1238 struct intel_gen6_power_mgmt
{
1240 * work, interrupts_enabled and pm_iir are protected by
1241 * dev_priv->irq_lock
1243 struct work_struct work
;
1244 bool interrupts_enabled
;
1247 /* PM interrupt bits that should never be masked */
1250 /* Frequencies are stored in potentially platform dependent multiples.
1251 * In other words, *_freq needs to be multiplied by X to be interesting.
1252 * Soft limits are those which are used for the dynamic reclocking done
1253 * by the driver (raise frequencies under heavy loads, and lower for
1254 * lighter loads). Hard limits are those imposed by the hardware.
1256 * A distinction is made for overclocking, which is never enabled by
1257 * default, and is considered to be above the hard limit if it's
1260 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1261 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1262 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1263 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1264 u8 min_freq
; /* AKA RPn. Minimum frequency */
1265 u8 boost_freq
; /* Frequency to request when wait boosting */
1266 u8 idle_freq
; /* Frequency to request when we are idle */
1267 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1268 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1269 u8 rp0_freq
; /* Non-overclocked max frequency. */
1270 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1272 u8 up_threshold
; /* Current %busy required to uplock */
1273 u8 down_threshold
; /* Current %busy required to downclock */
1276 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1278 spinlock_t client_lock
;
1279 struct list_head clients
;
1283 struct delayed_work autoenable_work
;
1286 /* manual wa residency calculations */
1287 struct intel_rps_ei up_ei
, down_ei
;
1290 * Protects RPS/RC6 register access and PCU communication.
1291 * Must be taken after struct_mutex if nested. Note that
1292 * this lock may be held for long periods of time when
1293 * talking to hw - so only take it when talking to hw!
1295 struct mutex hw_lock
;
1298 /* defined intel_pm.c */
1299 extern spinlock_t mchdev_lock
;
1301 struct intel_ilk_power_mgmt
{
1309 unsigned long last_time1
;
1310 unsigned long chipset_power
;
1313 unsigned long gfx_power
;
1320 struct drm_i915_private
;
1321 struct i915_power_well
;
1323 struct i915_power_well_ops
{
1325 * Synchronize the well's hw state to match the current sw state, for
1326 * example enable/disable it based on the current refcount. Called
1327 * during driver init and resume time, possibly after first calling
1328 * the enable/disable handlers.
1330 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1331 struct i915_power_well
*power_well
);
1333 * Enable the well and resources that depend on it (for example
1334 * interrupts located on the well). Called after the 0->1 refcount
1337 void (*enable
)(struct drm_i915_private
*dev_priv
,
1338 struct i915_power_well
*power_well
);
1340 * Disable the well and resources that depend on it. Called after
1341 * the 1->0 refcount transition.
1343 void (*disable
)(struct drm_i915_private
*dev_priv
,
1344 struct i915_power_well
*power_well
);
1345 /* Returns the hw enabled state. */
1346 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1347 struct i915_power_well
*power_well
);
1350 /* Power well structure for haswell */
1351 struct i915_power_well
{
1354 /* power well enable/disable usage count */
1356 /* cached hw enabled state */
1358 unsigned long domains
;
1359 /* unique identifier for this power well */
1362 * Arbitraty data associated with this power well. Platform and power
1366 const struct i915_power_well_ops
*ops
;
1369 struct i915_power_domains
{
1371 * Power wells needed for initialization at driver init and suspend
1372 * time are on. They are kept on until after the first modeset.
1376 int power_well_count
;
1379 int domain_use_count
[POWER_DOMAIN_NUM
];
1380 struct i915_power_well
*power_wells
;
1383 #define MAX_L3_SLICES 2
1384 struct intel_l3_parity
{
1385 u32
*remap_info
[MAX_L3_SLICES
];
1386 struct work_struct error_work
;
1390 struct i915_gem_mm
{
1391 /** Memory allocator for GTT stolen memory */
1392 struct drm_mm stolen
;
1393 /** Protects the usage of the GTT stolen memory allocator. This is
1394 * always the inner lock when overlapping with struct_mutex. */
1395 struct mutex stolen_lock
;
1397 /** List of all objects in gtt_space. Used to restore gtt
1398 * mappings on resume */
1399 struct list_head bound_list
;
1401 * List of objects which are not bound to the GTT (thus
1402 * are idle and not used by the GPU). These objects may or may
1403 * not actually have any pages attached.
1405 struct list_head unbound_list
;
1407 /** List of all objects in gtt_space, currently mmaped by userspace.
1408 * All objects within this list must also be on bound_list.
1410 struct list_head userfault_list
;
1413 * List of objects which are pending destruction.
1415 struct llist_head free_list
;
1416 struct work_struct free_work
;
1418 /** Usable portion of the GTT for GEM */
1419 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1421 /** PPGTT used for aliasing the PPGTT with the GTT */
1422 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1424 struct notifier_block oom_notifier
;
1425 struct notifier_block vmap_notifier
;
1426 struct shrinker shrinker
;
1428 /** LRU list of objects with fence regs on them. */
1429 struct list_head fence_list
;
1432 * Are we in a non-interruptible section of code like
1437 /* the indicator for dispatch video commands on two BSD rings */
1438 atomic_t bsd_engine_dispatch_index
;
1440 /** Bit 6 swizzling required for X tiling */
1441 uint32_t bit_6_swizzle_x
;
1442 /** Bit 6 swizzling required for Y tiling */
1443 uint32_t bit_6_swizzle_y
;
1445 /* accounting, useful for userland debugging */
1446 spinlock_t object_stat_lock
;
1451 struct drm_i915_error_state_buf
{
1452 struct drm_i915_private
*i915
;
1461 struct i915_error_state_file_priv
{
1462 struct drm_i915_private
*i915
;
1463 struct drm_i915_error_state
*error
;
1466 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1467 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1469 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1470 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1472 struct i915_gpu_error
{
1473 /* For hangcheck timer */
1474 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1475 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1477 struct delayed_work hangcheck_work
;
1479 /* For reset and error_state handling. */
1481 /* Protected by the above dev->gpu_error.lock. */
1482 struct drm_i915_error_state
*first_error
;
1484 unsigned long missed_irq_rings
;
1487 * State variable controlling the reset flow and count
1489 * This is a counter which gets incremented when reset is triggered,
1491 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1492 * meaning that any waiters holding onto the struct_mutex should
1493 * relinquish the lock immediately in order for the reset to start.
1495 * If reset is not completed succesfully, the I915_WEDGE bit is
1496 * set meaning that hardware is terminally sour and there is no
1497 * recovery. All waiters on the reset_queue will be woken when
1500 * This counter is used by the wait_seqno code to notice that reset
1501 * event happened and it needs to restart the entire ioctl (since most
1502 * likely the seqno it waited for won't ever signal anytime soon).
1504 * This is important for lock-free wait paths, where no contended lock
1505 * naturally enforces the correct ordering between the bail-out of the
1506 * waiter and the gpu reset work code.
1508 unsigned long reset_count
;
1510 unsigned long flags
;
1511 #define I915_RESET_IN_PROGRESS 0
1512 #define I915_WEDGED (BITS_PER_LONG - 1)
1515 * Waitqueue to signal when a hang is detected. Used to for waiters
1516 * to release the struct_mutex for the reset to procede.
1518 wait_queue_head_t wait_queue
;
1521 * Waitqueue to signal when the reset has completed. Used by clients
1522 * that wait for dev_priv->mm.wedged to settle.
1524 wait_queue_head_t reset_queue
;
1526 /* For missed irq/seqno simulation. */
1527 unsigned long test_irq_rings
;
1530 enum modeset_restore
{
1531 MODESET_ON_LID_OPEN
,
1536 #define DP_AUX_A 0x40
1537 #define DP_AUX_B 0x10
1538 #define DP_AUX_C 0x20
1539 #define DP_AUX_D 0x30
1541 #define DDC_PIN_B 0x05
1542 #define DDC_PIN_C 0x04
1543 #define DDC_PIN_D 0x06
1545 struct ddi_vbt_port_info
{
1547 * This is an index in the HDMI/DVI DDI buffer translation table.
1548 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1549 * populate this field.
1551 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1552 uint8_t hdmi_level_shift
;
1554 uint8_t supports_dvi
:1;
1555 uint8_t supports_hdmi
:1;
1556 uint8_t supports_dp
:1;
1558 uint8_t alternate_aux_channel
;
1559 uint8_t alternate_ddc_pin
;
1561 uint8_t dp_boost_level
;
1562 uint8_t hdmi_boost_level
;
1565 enum psr_lines_to_wait
{
1566 PSR_0_LINES_TO_WAIT
= 0,
1568 PSR_4_LINES_TO_WAIT
,
1572 struct intel_vbt_data
{
1573 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1574 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1577 unsigned int int_tv_support
:1;
1578 unsigned int lvds_dither
:1;
1579 unsigned int lvds_vbt
:1;
1580 unsigned int int_crt_support
:1;
1581 unsigned int lvds_use_ssc
:1;
1582 unsigned int display_clock_mode
:1;
1583 unsigned int fdi_rx_polarity_inverted
:1;
1584 unsigned int panel_type
:4;
1586 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1588 enum drrs_support_type drrs_type
;
1599 struct edp_power_seq pps
;
1604 bool require_aux_wakeup
;
1606 enum psr_lines_to_wait lines_to_wait
;
1607 int tp1_wakeup_time
;
1608 int tp2_tp3_wakeup_time
;
1614 bool active_low_pwm
;
1615 u8 min_brightness
; /* min_brightness/255 of max */
1616 enum intel_backlight_type type
;
1622 struct mipi_config
*config
;
1623 struct mipi_pps_data
*pps
;
1627 const u8
*sequence
[MIPI_SEQ_MAX
];
1633 union child_device_config
*child_dev
;
1635 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1636 struct sdvo_device_mapping sdvo_mappings
[2];
1639 enum intel_ddb_partitioning
{
1641 INTEL_DDB_PART_5_6
, /* IVB+ */
1644 struct intel_wm_level
{
1652 struct ilk_wm_values
{
1653 uint32_t wm_pipe
[3];
1655 uint32_t wm_lp_spr
[3];
1656 uint32_t wm_linetime
[3];
1658 enum intel_ddb_partitioning partitioning
;
1661 struct vlv_pipe_wm
{
1672 struct vlv_wm_values
{
1673 struct vlv_pipe_wm pipe
[3];
1674 struct vlv_sr_wm sr
;
1684 struct skl_ddb_entry
{
1685 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1688 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1690 return entry
->end
- entry
->start
;
1693 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1694 const struct skl_ddb_entry
*e2
)
1696 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1702 struct skl_ddb_allocation
{
1703 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1704 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1707 struct skl_wm_values
{
1708 unsigned dirty_pipes
;
1709 struct skl_ddb_allocation ddb
;
1712 struct skl_wm_level
{
1714 uint16_t plane_res_b
;
1715 uint8_t plane_res_l
;
1719 * This struct helps tracking the state needed for runtime PM, which puts the
1720 * device in PCI D3 state. Notice that when this happens, nothing on the
1721 * graphics device works, even register access, so we don't get interrupts nor
1724 * Every piece of our code that needs to actually touch the hardware needs to
1725 * either call intel_runtime_pm_get or call intel_display_power_get with the
1726 * appropriate power domain.
1728 * Our driver uses the autosuspend delay feature, which means we'll only really
1729 * suspend if we stay with zero refcount for a certain amount of time. The
1730 * default value is currently very conservative (see intel_runtime_pm_enable), but
1731 * it can be changed with the standard runtime PM files from sysfs.
1733 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1734 * goes back to false exactly before we reenable the IRQs. We use this variable
1735 * to check if someone is trying to enable/disable IRQs while they're supposed
1736 * to be disabled. This shouldn't happen and we'll print some error messages in
1739 * For more, read the Documentation/power/runtime_pm.txt.
1741 struct i915_runtime_pm
{
1742 atomic_t wakeref_count
;
1747 enum intel_pipe_crc_source
{
1748 INTEL_PIPE_CRC_SOURCE_NONE
,
1749 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1750 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1751 INTEL_PIPE_CRC_SOURCE_PF
,
1752 INTEL_PIPE_CRC_SOURCE_PIPE
,
1753 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1754 INTEL_PIPE_CRC_SOURCE_TV
,
1755 INTEL_PIPE_CRC_SOURCE_DP_B
,
1756 INTEL_PIPE_CRC_SOURCE_DP_C
,
1757 INTEL_PIPE_CRC_SOURCE_DP_D
,
1758 INTEL_PIPE_CRC_SOURCE_AUTO
,
1759 INTEL_PIPE_CRC_SOURCE_MAX
,
1762 struct intel_pipe_crc_entry
{
1767 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1768 struct intel_pipe_crc
{
1770 bool opened
; /* exclusive access to the result file */
1771 struct intel_pipe_crc_entry
*entries
;
1772 enum intel_pipe_crc_source source
;
1774 wait_queue_head_t wq
;
1777 struct i915_frontbuffer_tracking
{
1781 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1788 struct i915_wa_reg
{
1791 /* bitmask representing WA bits */
1796 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1797 * allowing it for RCS as we don't foresee any requirement of having
1798 * a whitelist for other engines. When it is really required for
1799 * other engines then the limit need to be increased.
1801 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1803 struct i915_workarounds
{
1804 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1806 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1809 struct i915_virtual_gpu
{
1813 /* used in computing the new watermarks state */
1814 struct intel_wm_config
{
1815 unsigned int num_pipes_active
;
1816 bool sprites_enabled
;
1817 bool sprites_scaled
;
1820 struct i915_oa_format
{
1825 struct i915_oa_reg
{
1830 struct i915_perf_stream
;
1832 struct i915_perf_stream_ops
{
1833 /* Enables the collection of HW samples, either in response to
1834 * I915_PERF_IOCTL_ENABLE or implicitly called when stream is
1835 * opened without I915_PERF_FLAG_DISABLED.
1837 void (*enable
)(struct i915_perf_stream
*stream
);
1839 /* Disables the collection of HW samples, either in response to
1840 * I915_PERF_IOCTL_DISABLE or implicitly called before
1841 * destroying the stream.
1843 void (*disable
)(struct i915_perf_stream
*stream
);
1845 /* Call poll_wait, passing a wait queue that will be woken
1846 * once there is something ready to read() for the stream
1848 void (*poll_wait
)(struct i915_perf_stream
*stream
,
1852 /* For handling a blocking read, wait until there is something
1853 * to ready to read() for the stream. E.g. wait on the same
1854 * wait queue that would be passed to poll_wait().
1856 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
1858 /* read - Copy buffered metrics as records to userspace
1859 * @buf: the userspace, destination buffer
1860 * @count: the number of bytes to copy, requested by userspace
1861 * @offset: zero at the start of the read, updated as the read
1862 * proceeds, it represents how many bytes have been
1863 * copied so far and the buffer offset for copying the
1866 * Copy as many buffered i915 perf samples and records for
1867 * this stream to userspace as will fit in the given buffer.
1869 * Only write complete records; returning -ENOSPC if there
1870 * isn't room for a complete record.
1872 * Return any error condition that results in a short read
1873 * such as -ENOSPC or -EFAULT, even though these may be
1874 * squashed before returning to userspace.
1876 int (*read
)(struct i915_perf_stream
*stream
,
1881 /* Cleanup any stream specific resources.
1883 * The stream will always be disabled before this is called.
1885 void (*destroy
)(struct i915_perf_stream
*stream
);
1888 struct i915_perf_stream
{
1889 struct drm_i915_private
*dev_priv
;
1891 struct list_head link
;
1896 struct i915_gem_context
*ctx
;
1899 const struct i915_perf_stream_ops
*ops
;
1902 struct i915_oa_ops
{
1903 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
1904 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
);
1905 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
1906 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
1907 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
1908 void (*update_oacontrol
)(struct drm_i915_private
*dev_priv
);
1909 void (*update_hw_ctx_id_locked
)(struct drm_i915_private
*dev_priv
,
1911 int (*read
)(struct i915_perf_stream
*stream
,
1915 bool (*oa_buffer_is_empty
)(struct drm_i915_private
*dev_priv
);
1918 struct drm_i915_private
{
1919 struct drm_device drm
;
1921 struct kmem_cache
*objects
;
1922 struct kmem_cache
*vmas
;
1923 struct kmem_cache
*requests
;
1924 struct kmem_cache
*dependencies
;
1926 const struct intel_device_info info
;
1928 int relative_constants_mode
;
1932 struct intel_uncore uncore
;
1934 struct i915_virtual_gpu vgpu
;
1936 struct intel_gvt
*gvt
;
1938 struct intel_guc guc
;
1940 struct intel_csr csr
;
1942 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1944 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1945 * controller on different i2c buses. */
1946 struct mutex gmbus_mutex
;
1949 * Base address of the gmbus and gpio block.
1951 uint32_t gpio_mmio_base
;
1953 /* MMIO base address for MIPI regs */
1954 uint32_t mipi_mmio_base
;
1956 uint32_t psr_mmio_base
;
1958 uint32_t pps_mmio_base
;
1960 wait_queue_head_t gmbus_wait_queue
;
1962 struct pci_dev
*bridge_dev
;
1963 struct i915_gem_context
*kernel_context
;
1964 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
1965 struct i915_vma
*semaphore
;
1967 struct drm_dma_handle
*status_page_dmah
;
1968 struct resource mch_res
;
1970 /* protects the irq masks */
1971 spinlock_t irq_lock
;
1973 /* protects the mmio flip data */
1974 spinlock_t mmio_flip_lock
;
1976 bool display_irqs_enabled
;
1978 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1979 struct pm_qos_request pm_qos
;
1981 /* Sideband mailbox protection */
1982 struct mutex sb_lock
;
1984 /** Cached value of IMR to avoid reads in updating the bitfield */
1987 u32 de_irq_mask
[I915_MAX_PIPES
];
1994 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1996 struct i915_hotplug hotplug
;
1997 struct intel_fbc fbc
;
1998 struct i915_drrs drrs
;
1999 struct intel_opregion opregion
;
2000 struct intel_vbt_data vbt
;
2002 bool preserve_bios_swizzle
;
2005 struct intel_overlay
*overlay
;
2007 /* backlight registers and fields in struct intel_panel */
2008 struct mutex backlight_lock
;
2011 bool no_aux_handshake
;
2013 /* protects panel power sequencer state */
2014 struct mutex pps_mutex
;
2016 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2017 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2019 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2020 unsigned int skl_preferred_vco_freq
;
2021 unsigned int cdclk_freq
, max_cdclk_freq
;
2024 * For reading holding any crtc lock is sufficient,
2025 * for writing must hold all of them.
2027 unsigned int atomic_cdclk_freq
;
2029 unsigned int max_dotclk_freq
;
2030 unsigned int rawclk_freq
;
2031 unsigned int hpll_freq
;
2032 unsigned int czclk_freq
;
2035 unsigned int vco
, ref
;
2039 * wq - Driver workqueue for GEM.
2041 * NOTE: Work items scheduled here are not allowed to grab any modeset
2042 * locks, for otherwise the flushing done in the pageflip code will
2043 * result in deadlocks.
2045 struct workqueue_struct
*wq
;
2047 /* Display functions */
2048 struct drm_i915_display_funcs display
;
2050 /* PCH chipset type */
2051 enum intel_pch pch_type
;
2052 unsigned short pch_id
;
2054 unsigned long quirks
;
2056 enum modeset_restore modeset_restore
;
2057 struct mutex modeset_restore_lock
;
2058 struct drm_atomic_state
*modeset_restore_state
;
2059 struct drm_modeset_acquire_ctx reset_ctx
;
2061 struct list_head vm_list
; /* Global list of all address spaces */
2062 struct i915_ggtt ggtt
; /* VM representing the global address space */
2064 struct i915_gem_mm mm
;
2065 DECLARE_HASHTABLE(mm_structs
, 7);
2066 struct mutex mm_lock
;
2068 /* The hw wants to have a stable context identifier for the lifetime
2069 * of the context (for OA, PASID, faults, etc). This is limited
2070 * in execlists to 21 bits.
2072 struct ida context_hw_ida
;
2073 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2075 /* Kernel Modesetting */
2077 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2078 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2079 wait_queue_head_t pending_flip_queue
;
2081 #ifdef CONFIG_DEBUG_FS
2082 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2085 /* dpll and cdclk state is protected by connection_mutex */
2086 int num_shared_dpll
;
2087 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2088 const struct intel_dpll_mgr
*dpll_mgr
;
2091 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2092 * Must be global rather than per dpll, because on some platforms
2093 * plls share registers.
2095 struct mutex dpll_lock
;
2097 unsigned int active_crtcs
;
2098 unsigned int min_pixclk
[I915_MAX_PIPES
];
2100 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2102 struct i915_workarounds workarounds
;
2104 struct i915_frontbuffer_tracking fb_tracking
;
2108 bool mchbar_need_disable
;
2110 struct intel_l3_parity l3_parity
;
2112 /* Cannot be determined by PCIID. You must always read a register. */
2115 /* gen6+ rps state */
2116 struct intel_gen6_power_mgmt rps
;
2118 /* ilk-only ips/rps state. Everything in here is protected by the global
2119 * mchdev_lock in intel_pm.c */
2120 struct intel_ilk_power_mgmt ips
;
2122 struct i915_power_domains power_domains
;
2124 struct i915_psr psr
;
2126 struct i915_gpu_error gpu_error
;
2128 struct drm_i915_gem_object
*vlv_pctx
;
2130 #ifdef CONFIG_DRM_FBDEV_EMULATION
2131 /* list of fbdev register on this device */
2132 struct intel_fbdev
*fbdev
;
2133 struct work_struct fbdev_suspend_work
;
2136 struct drm_property
*broadcast_rgb_property
;
2137 struct drm_property
*force_audio_property
;
2139 /* hda/i915 audio component */
2140 struct i915_audio_component
*audio_component
;
2141 bool audio_component_registered
;
2143 * av_mutex - mutex for audio/video sync
2146 struct mutex av_mutex
;
2148 uint32_t hw_context_size
;
2149 struct list_head context_list
;
2153 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2154 u32 chv_phy_control
;
2156 * Shadows for CHV DPLL_MD regs to keep the state
2157 * checker somewhat working in the presence hardware
2158 * crappiness (can't read out DPLL_MD for pipes B & C).
2160 u32 chv_dpll_md
[I915_MAX_PIPES
];
2164 bool suspended_to_idle
;
2165 struct i915_suspend_saved_registers regfile
;
2166 struct vlv_s0ix_state vlv_s0ix_state
;
2169 I915_SAGV_UNKNOWN
= 0,
2172 I915_SAGV_NOT_CONTROLLED
2177 * Raw watermark latency values:
2178 * in 0.1us units for WM0,
2179 * in 0.5us units for WM1+.
2182 uint16_t pri_latency
[5];
2184 uint16_t spr_latency
[5];
2186 uint16_t cur_latency
[5];
2188 * Raw watermark memory latency values
2189 * for SKL for all 8 levels
2192 uint16_t skl_latency
[8];
2194 /* current hardware state */
2196 struct ilk_wm_values hw
;
2197 struct skl_wm_values skl_hw
;
2198 struct vlv_wm_values vlv
;
2204 * Should be held around atomic WM register writing; also
2205 * protects * intel_crtc->wm.active and
2206 * cstate->wm.need_postvbl_update.
2208 struct mutex wm_mutex
;
2211 * Set during HW readout of watermarks/DDB. Some platforms
2212 * need to know when we're still using BIOS-provided values
2213 * (which we don't fully trust).
2215 bool distrust_bios_wm
;
2218 struct i915_runtime_pm pm
;
2223 struct kobject
*metrics_kobj
;
2224 struct ctl_table_header
*sysctl_header
;
2227 struct list_head streams
;
2229 spinlock_t hook_lock
;
2232 struct i915_perf_stream
*exclusive_stream
;
2234 u32 specific_ctx_id
;
2235 struct i915_vma
*pinned_rcs_vma
;
2237 struct hrtimer poll_check_timer
;
2238 wait_queue_head_t poll_wq
;
2242 int period_exponent
;
2243 int timestamp_frequency
;
2249 const struct i915_oa_reg
*mux_regs
;
2251 const struct i915_oa_reg
*b_counter_regs
;
2252 int b_counter_regs_len
;
2255 struct i915_vma
*vma
;
2261 u32 gen7_latched_oastatus1
;
2263 struct i915_oa_ops ops
;
2264 const struct i915_oa_format
*oa_formats
;
2269 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2271 void (*resume
)(struct drm_i915_private
*);
2272 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2274 struct list_head timelines
;
2275 struct i915_gem_timeline global_timeline
;
2276 u32 active_requests
;
2279 * Is the GPU currently considered idle, or busy executing
2280 * userspace requests? Whilst idle, we allow runtime power
2281 * management to power down the hardware and display clocks.
2282 * In order to reduce the effect on performance, there
2283 * is a slight delay before we do so.
2288 * We leave the user IRQ off as much as possible,
2289 * but this means that requests will finish and never
2290 * be retired once the system goes idle. Set a timer to
2291 * fire periodically while the ring is running. When it
2292 * fires, go retire requests.
2294 struct delayed_work retire_work
;
2297 * When we detect an idle GPU, we want to turn on
2298 * powersaving features. So once we see that there
2299 * are no more requests outstanding and no more
2300 * arrive within a small period of time, we fire
2301 * off the idle_work.
2303 struct delayed_work idle_work
;
2305 ktime_t last_init_time
;
2308 /* perform PHY state sanity checks? */
2309 bool chv_phy_assert
[2];
2311 /* Used to save the pipe-to-encoder mapping for audio */
2312 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2315 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2316 * will be rejected. Instead look for a better place.
2320 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2322 return container_of(dev
, struct drm_i915_private
, drm
);
2325 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2327 return to_i915(dev_get_drvdata(kdev
));
2330 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2332 return container_of(guc
, struct drm_i915_private
, guc
);
2335 /* Simple iterator over all initialised engines */
2336 #define for_each_engine(engine__, dev_priv__, id__) \
2338 (id__) < I915_NUM_ENGINES; \
2340 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2342 #define __mask_next_bit(mask) ({ \
2343 int __idx = ffs(mask) - 1; \
2344 mask &= ~BIT(__idx); \
2348 /* Iterator over subset of engines selected by mask */
2349 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2350 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2351 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2353 enum hdmi_force_audio
{
2354 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2355 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2356 HDMI_AUDIO_AUTO
, /* trust EDID */
2357 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2360 #define I915_GTT_OFFSET_NONE ((u32)-1)
2363 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2364 * considered to be the frontbuffer for the given plane interface-wise. This
2365 * doesn't mean that the hw necessarily already scans it out, but that any
2366 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2368 * We have one bit per pipe and per scanout plane type.
2370 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2371 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2372 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2373 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2374 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2375 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2376 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2377 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2378 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2379 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2380 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2381 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2384 * Optimised SGL iterator for GEM objects
2386 static __always_inline
struct sgt_iter
{
2387 struct scatterlist
*sgp
;
2394 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2395 struct sgt_iter s
= { .sgp
= sgl
};
2398 s
.max
= s
.curr
= s
.sgp
->offset
;
2399 s
.max
+= s
.sgp
->length
;
2401 s
.dma
= sg_dma_address(s
.sgp
);
2403 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2409 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2412 if (unlikely(sg_is_chain(sg
)))
2413 sg
= sg_chain_ptr(sg
);
2418 * __sg_next - return the next scatterlist entry in a list
2419 * @sg: The current sg entry
2422 * If the entry is the last, return NULL; otherwise, step to the next
2423 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2424 * otherwise just return the pointer to the current element.
2426 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2428 #ifdef CONFIG_DEBUG_SG
2429 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2431 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2435 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2436 * @__dmap: DMA address (output)
2437 * @__iter: 'struct sgt_iter' (iterator state, internal)
2438 * @__sgt: sg_table to iterate over (input)
2440 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2441 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2442 ((__dmap) = (__iter).dma + (__iter).curr); \
2443 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2444 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2447 * for_each_sgt_page - iterate over the pages of the given sg_table
2448 * @__pp: page pointer (output)
2449 * @__iter: 'struct sgt_iter' (iterator state, internal)
2450 * @__sgt: sg_table to iterate over (input)
2452 #define for_each_sgt_page(__pp, __iter, __sgt) \
2453 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2454 ((__pp) = (__iter).pfn == 0 ? NULL : \
2455 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2456 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2457 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2459 static inline const struct intel_device_info
*
2460 intel_info(const struct drm_i915_private
*dev_priv
)
2462 return &dev_priv
->info
;
2465 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2467 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2468 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2470 #define REVID_FOREVER 0xff
2471 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2473 #define GEN_FOREVER (0)
2475 * Returns true if Gen is in inclusive range [Start, End].
2477 * Use GEN_FOREVER for unbound start and or end.
2479 #define IS_GEN(dev_priv, s, e) ({ \
2480 unsigned int __s = (s), __e = (e); \
2481 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2482 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2483 if ((__s) != GEN_FOREVER) \
2485 if ((__e) == GEN_FOREVER) \
2486 __e = BITS_PER_LONG - 1; \
2489 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2493 * Return true if revision is in range [since,until] inclusive.
2495 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2497 #define IS_REVID(p, since, until) \
2498 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2500 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2501 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2502 #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
2503 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2504 #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
2505 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2506 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2507 #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
2508 #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
2509 #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
2510 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2511 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2512 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2513 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2514 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
2515 #define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
2516 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2517 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2518 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2519 INTEL_DEVID(dev_priv) == 0x0152 || \
2520 INTEL_DEVID(dev_priv) == 0x015a)
2521 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2522 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2523 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2524 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2525 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2526 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2527 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
2528 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2529 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2530 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2531 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2532 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2533 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2534 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2535 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2536 /* ULX machines are also considered ULT. */
2537 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2538 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2539 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2540 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2541 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2542 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2543 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2544 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2545 /* ULX machines are also considered ULT. */
2546 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2547 INTEL_DEVID(dev_priv) == 0x0A1E)
2548 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2549 INTEL_DEVID(dev_priv) == 0x1913 || \
2550 INTEL_DEVID(dev_priv) == 0x1916 || \
2551 INTEL_DEVID(dev_priv) == 0x1921 || \
2552 INTEL_DEVID(dev_priv) == 0x1926)
2553 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2554 INTEL_DEVID(dev_priv) == 0x1915 || \
2555 INTEL_DEVID(dev_priv) == 0x191E)
2556 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2557 INTEL_DEVID(dev_priv) == 0x5913 || \
2558 INTEL_DEVID(dev_priv) == 0x5916 || \
2559 INTEL_DEVID(dev_priv) == 0x5921 || \
2560 INTEL_DEVID(dev_priv) == 0x5926)
2561 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2562 INTEL_DEVID(dev_priv) == 0x5915 || \
2563 INTEL_DEVID(dev_priv) == 0x591E)
2564 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2565 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2566 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2567 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2569 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2571 #define SKL_REVID_A0 0x0
2572 #define SKL_REVID_B0 0x1
2573 #define SKL_REVID_C0 0x2
2574 #define SKL_REVID_D0 0x3
2575 #define SKL_REVID_E0 0x4
2576 #define SKL_REVID_F0 0x5
2577 #define SKL_REVID_G0 0x6
2578 #define SKL_REVID_H0 0x7
2580 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2582 #define BXT_REVID_A0 0x0
2583 #define BXT_REVID_A1 0x1
2584 #define BXT_REVID_B0 0x3
2585 #define BXT_REVID_B_LAST 0x8
2586 #define BXT_REVID_C0 0x9
2588 #define IS_BXT_REVID(dev_priv, since, until) \
2589 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2591 #define KBL_REVID_A0 0x0
2592 #define KBL_REVID_B0 0x1
2593 #define KBL_REVID_C0 0x2
2594 #define KBL_REVID_D0 0x3
2595 #define KBL_REVID_E0 0x4
2597 #define IS_KBL_REVID(dev_priv, since, until) \
2598 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2601 * The genX designation typically refers to the render engine, so render
2602 * capability related checks should use IS_GEN, while display and other checks
2603 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2606 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2607 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2608 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2609 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2610 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2611 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2612 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2613 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2615 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2617 #define ENGINE_MASK(id) BIT(id)
2618 #define RENDER_RING ENGINE_MASK(RCS)
2619 #define BSD_RING ENGINE_MASK(VCS)
2620 #define BLT_RING ENGINE_MASK(BCS)
2621 #define VEBOX_RING ENGINE_MASK(VECS)
2622 #define BSD2_RING ENGINE_MASK(VCS2)
2623 #define ALL_ENGINES (~0)
2625 #define HAS_ENGINE(dev_priv, id) \
2626 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2628 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2629 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2630 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2631 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2633 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2634 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2635 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2636 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2637 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2639 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2641 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2642 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2643 ((dev_priv)->info.has_logical_ring_contexts)
2644 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2645 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2646 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2648 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2649 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2650 ((dev_priv)->info.overlay_needs_physical)
2652 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2653 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2655 /* WaRsDisableCoarsePowerGating:skl,bxt */
2656 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2657 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2658 IS_SKL_GT3(dev_priv) || \
2659 IS_SKL_GT4(dev_priv))
2662 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2663 * even when in MSI mode. This results in spurious interrupt warnings if the
2664 * legacy irq no. is shared with another device. The kernel then disables that
2665 * interrupt source and so prevents the other device from working properly.
2667 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2668 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2670 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2671 * rows, which changed the alignment requirements and fence programming.
2673 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2674 !(IS_I915G(dev_priv) || \
2675 IS_I915GM(dev_priv)))
2676 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2677 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2679 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2680 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2681 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2683 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2685 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2687 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2688 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2689 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2690 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2691 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2693 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2695 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2696 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2699 * For now, anything with a GuC requires uCode loading, and then supports
2700 * command submission once loaded. But these are logically independent
2701 * properties, so we have separate macros to test them.
2703 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2704 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2705 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2707 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2709 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2711 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2712 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2713 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2714 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2715 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2716 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2717 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2718 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2719 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2720 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2721 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2722 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2724 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2725 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2726 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2727 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2728 #define HAS_PCH_LPT_LP(dev_priv) \
2729 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2730 #define HAS_PCH_LPT_H(dev_priv) \
2731 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2732 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2733 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2734 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2735 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2737 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2739 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2741 /* DPF == dynamic parity feature */
2742 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2743 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2744 2 : HAS_L3_DPF(dev_priv))
2746 #define GT_FREQUENCY_MULTIPLIER 50
2747 #define GEN9_FREQ_SCALER 3
2749 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2751 #include "i915_trace.h"
2753 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2755 #ifdef CONFIG_INTEL_IOMMU
2756 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2762 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2765 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2769 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2770 const char *fmt
, ...);
2772 #define i915_report_error(dev_priv, fmt, ...) \
2773 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2775 #ifdef CONFIG_COMPAT
2776 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2779 #define i915_compat_ioctl NULL
2781 extern const struct dev_pm_ops i915_pm_ops
;
2783 extern int i915_driver_load(struct pci_dev
*pdev
,
2784 const struct pci_device_id
*ent
);
2785 extern void i915_driver_unload(struct drm_device
*dev
);
2786 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2787 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2788 extern void i915_reset(struct drm_i915_private
*dev_priv
);
2789 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2790 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2791 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
2792 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2793 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2794 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2795 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2796 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2798 /* intel_hotplug.c */
2799 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2800 u32 pin_mask
, u32 long_mask
);
2801 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2802 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2803 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2804 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2805 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2806 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2809 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2811 unsigned long delay
;
2813 if (unlikely(!i915
.enable_hangcheck
))
2816 /* Don't continually defer the hangcheck so that it is always run at
2817 * least once after work has been scheduled on any ring. Otherwise,
2818 * we will ignore a hung ring if a second ring is kept busy.
2821 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2822 queue_delayed_work(system_long_wq
,
2823 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2827 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2829 const char *fmt
, ...);
2831 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2832 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2833 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2835 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2836 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2837 bool restore_forcewake
);
2838 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2839 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2840 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2841 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2842 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2844 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2845 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2846 enum forcewake_domains domains
);
2847 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2848 enum forcewake_domains domains
);
2849 /* Like above but the caller must manage the uncore.lock itself.
2850 * Must be used with I915_READ_FW and friends.
2852 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2853 enum forcewake_domains domains
);
2854 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2855 enum forcewake_domains domains
);
2856 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2858 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2860 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
2864 const unsigned long timeout_ms
);
2865 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
2869 const unsigned long timeout_ms
);
2871 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2873 return dev_priv
->gvt
;
2876 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2878 return dev_priv
->vgpu
.active
;
2882 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2886 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2889 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2890 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2891 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2894 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2895 uint32_t interrupt_mask
,
2896 uint32_t enabled_irq_mask
);
2898 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2900 ilk_update_display_irq(dev_priv
, bits
, bits
);
2903 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2905 ilk_update_display_irq(dev_priv
, bits
, 0);
2907 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2909 uint32_t interrupt_mask
,
2910 uint32_t enabled_irq_mask
);
2911 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2912 enum pipe pipe
, uint32_t bits
)
2914 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2916 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2917 enum pipe pipe
, uint32_t bits
)
2919 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2921 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2922 uint32_t interrupt_mask
,
2923 uint32_t enabled_irq_mask
);
2925 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2927 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2930 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2932 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2936 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2937 struct drm_file
*file_priv
);
2938 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2939 struct drm_file
*file_priv
);
2940 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2941 struct drm_file
*file_priv
);
2942 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2943 struct drm_file
*file_priv
);
2944 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2945 struct drm_file
*file_priv
);
2946 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2947 struct drm_file
*file_priv
);
2948 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2949 struct drm_file
*file_priv
);
2950 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2951 struct drm_file
*file_priv
);
2952 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2953 struct drm_file
*file_priv
);
2954 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2955 struct drm_file
*file_priv
);
2956 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2957 struct drm_file
*file
);
2958 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2959 struct drm_file
*file
);
2960 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2961 struct drm_file
*file_priv
);
2962 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2963 struct drm_file
*file_priv
);
2964 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2965 struct drm_file
*file_priv
);
2966 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2967 struct drm_file
*file_priv
);
2968 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
2969 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2970 struct drm_file
*file
);
2971 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2972 struct drm_file
*file_priv
);
2973 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2974 struct drm_file
*file_priv
);
2975 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
2976 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
2977 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
2978 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
2979 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
2981 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
2982 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2983 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2984 const struct drm_i915_gem_object_ops
*ops
);
2985 struct drm_i915_gem_object
*
2986 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
2987 struct drm_i915_gem_object
*
2988 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
2989 const void *data
, size_t size
);
2990 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
2991 void i915_gem_free_object(struct drm_gem_object
*obj
);
2993 struct i915_vma
* __must_check
2994 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2995 const struct i915_ggtt_view
*view
,
3000 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3001 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3003 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3005 static inline int __sg_page_count(const struct scatterlist
*sg
)
3007 return sg
->length
>> PAGE_SHIFT
;
3010 struct scatterlist
*
3011 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3012 unsigned int n
, unsigned int *offset
);
3015 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3019 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3023 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3026 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3027 struct sg_table
*pages
);
3028 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3030 static inline int __must_check
3031 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3033 might_lock(&obj
->mm
.lock
);
3035 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3038 return __i915_gem_object_get_pages(obj
);
3042 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3044 GEM_BUG_ON(!obj
->mm
.pages
);
3046 atomic_inc(&obj
->mm
.pages_pin_count
);
3050 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3052 return atomic_read(&obj
->mm
.pages_pin_count
);
3056 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3058 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3059 GEM_BUG_ON(!obj
->mm
.pages
);
3061 atomic_dec(&obj
->mm
.pages_pin_count
);
3062 GEM_BUG_ON(atomic_read(&obj
->mm
.pages_pin_count
) < obj
->bind_count
);
3066 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3068 __i915_gem_object_unpin_pages(obj
);
3071 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3076 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3077 enum i915_mm_subclass subclass
);
3078 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3080 enum i915_map_type
{
3086 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3087 * @obj - the object to map into kernel address space
3088 * @type - the type of mapping, used to select pgprot_t
3090 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3091 * pages and then returns a contiguous mapping of the backing storage into
3092 * the kernel address space. Based on the @type of mapping, the PTE will be
3093 * set to either WriteBack or WriteCombine (via pgprot_t).
3095 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3096 * mapping is no longer required.
3098 * Returns the pointer through which to access the mapped object, or an
3099 * ERR_PTR() on error.
3101 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3102 enum i915_map_type type
);
3105 * i915_gem_object_unpin_map - releases an earlier mapping
3106 * @obj - the object to unmap
3108 * After pinning the object and mapping its pages, once you are finished
3109 * with your access, call i915_gem_object_unpin_map() to release the pin
3110 * upon the mapping. Once the pin count reaches zero, that mapping may be
3113 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3115 i915_gem_object_unpin_pages(obj
);
3118 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3119 unsigned int *needs_clflush
);
3120 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3121 unsigned int *needs_clflush
);
3122 #define CLFLUSH_BEFORE 0x1
3123 #define CLFLUSH_AFTER 0x2
3124 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3127 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3129 i915_gem_object_unpin_pages(obj
);
3132 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3133 void i915_vma_move_to_active(struct i915_vma
*vma
,
3134 struct drm_i915_gem_request
*req
,
3135 unsigned int flags
);
3136 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3137 struct drm_device
*dev
,
3138 struct drm_mode_create_dumb
*args
);
3139 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3140 uint32_t handle
, uint64_t *offset
);
3141 int i915_gem_mmap_gtt_version(void);
3143 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3144 struct drm_i915_gem_object
*new,
3145 unsigned frontbuffer_bits
);
3147 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3149 struct drm_i915_gem_request
*
3150 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3152 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3154 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3156 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3159 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3161 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3164 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3166 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3169 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3171 return READ_ONCE(error
->reset_count
);
3174 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3175 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3176 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3177 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3178 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3179 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3180 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3181 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3182 unsigned int flags
);
3183 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3184 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3185 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3186 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3189 struct intel_rps_client
*rps
);
3190 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3193 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3196 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3199 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3200 struct i915_vma
* __must_check
3201 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3203 const struct i915_ggtt_view
*view
);
3204 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3205 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3207 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3208 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3210 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3212 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3213 int tiling_mode
, bool fenced
);
3215 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3216 enum i915_cache_level cache_level
);
3218 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3219 struct dma_buf
*dma_buf
);
3221 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3222 struct drm_gem_object
*gem_obj
, int flags
);
3225 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3226 struct i915_address_space
*vm
,
3227 const struct i915_ggtt_view
*view
);
3230 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3231 struct i915_address_space
*vm
,
3232 const struct i915_ggtt_view
*view
);
3234 static inline struct i915_hw_ppgtt
*
3235 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3237 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3240 static inline struct i915_vma
*
3241 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3242 const struct i915_ggtt_view
*view
)
3244 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3247 static inline unsigned long
3248 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3249 const struct i915_ggtt_view
*view
)
3251 return i915_ggtt_offset(i915_gem_object_to_ggtt(o
, view
));
3254 /* i915_gem_fence_reg.c */
3255 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3256 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3258 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3260 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3261 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3262 struct sg_table
*pages
);
3263 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3264 struct sg_table
*pages
);
3266 /* i915_gem_context.c */
3267 int __must_check
i915_gem_context_init(struct drm_i915_private
*dev_priv
);
3268 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3269 void i915_gem_context_fini(struct drm_i915_private
*dev_priv
);
3270 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3271 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3272 int i915_switch_context(struct drm_i915_gem_request
*req
);
3273 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3275 i915_gem_context_pin_legacy(struct i915_gem_context
*ctx
,
3276 unsigned int flags
);
3277 void i915_gem_context_free(struct kref
*ctx_ref
);
3278 struct i915_gem_context
*
3279 i915_gem_context_create_gvt(struct drm_device
*dev
);
3281 static inline struct i915_gem_context
*
3282 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3284 struct i915_gem_context
*ctx
;
3286 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3288 ctx
= idr_find(&file_priv
->context_idr
, id
);
3290 return ERR_PTR(-ENOENT
);
3295 static inline struct i915_gem_context
*
3296 i915_gem_context_get(struct i915_gem_context
*ctx
)
3298 kref_get(&ctx
->ref
);
3302 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3304 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3305 kref_put(&ctx
->ref
, i915_gem_context_free
);
3308 static inline struct intel_timeline
*
3309 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3310 struct intel_engine_cs
*engine
)
3312 struct i915_address_space
*vm
;
3314 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3315 return &vm
->timeline
.engine
[engine
->id
];
3318 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3320 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3323 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3324 struct drm_file
*file
);
3325 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3326 struct drm_file
*file
);
3327 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3328 struct drm_file
*file_priv
);
3329 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3330 struct drm_file
*file_priv
);
3331 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3332 struct drm_file
*file
);
3334 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3335 struct drm_file
*file
);
3337 /* i915_gem_evict.c */
3338 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3339 u64 min_size
, u64 alignment
,
3340 unsigned cache_level
,
3343 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3344 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3346 /* belongs in i915_gem_gtt.h */
3347 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3350 if (INTEL_GEN(dev_priv
) < 6)
3351 intel_gtt_chipset_flush();
3354 /* i915_gem_stolen.c */
3355 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3356 struct drm_mm_node
*node
, u64 size
,
3357 unsigned alignment
);
3358 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3359 struct drm_mm_node
*node
, u64 size
,
3360 unsigned alignment
, u64 start
,
3362 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3363 struct drm_mm_node
*node
);
3364 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3365 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3366 struct drm_i915_gem_object
*
3367 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3368 struct drm_i915_gem_object
*
3369 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3374 /* i915_gem_internal.c */
3375 struct drm_i915_gem_object
*
3376 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3379 /* i915_gem_shrinker.c */
3380 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3381 unsigned long target
,
3383 #define I915_SHRINK_PURGEABLE 0x1
3384 #define I915_SHRINK_UNBOUND 0x2
3385 #define I915_SHRINK_BOUND 0x4
3386 #define I915_SHRINK_ACTIVE 0x8
3387 #define I915_SHRINK_VMAPS 0x10
3388 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3389 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3390 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3393 /* i915_gem_tiling.c */
3394 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3396 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3398 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3399 i915_gem_object_is_tiled(obj
);
3402 /* i915_debugfs.c */
3403 #ifdef CONFIG_DEBUG_FS
3404 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3405 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3406 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3407 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3409 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3410 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3411 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3413 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3416 /* i915_gpu_error.c */
3417 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3420 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3421 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3422 const struct i915_error_state_file_priv
*error
);
3423 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3424 struct drm_i915_private
*i915
,
3425 size_t count
, loff_t pos
);
3426 static inline void i915_error_state_buf_release(
3427 struct drm_i915_error_state_buf
*eb
)
3431 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3433 const char *error_msg
);
3434 void i915_error_state_get(struct drm_device
*dev
,
3435 struct i915_error_state_file_priv
*error_priv
);
3436 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3437 void i915_destroy_error_state(struct drm_i915_private
*dev_priv
);
3441 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3443 const char *error_msg
)
3447 static inline void i915_destroy_error_state(struct drm_i915_private
*dev_priv
)
3453 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3455 /* i915_cmd_parser.c */
3456 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3457 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3458 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3459 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3460 struct drm_i915_gem_object
*batch_obj
,
3461 struct drm_i915_gem_object
*shadow_batch_obj
,
3462 u32 batch_start_offset
,
3467 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3468 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3469 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3470 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3472 /* i915_suspend.c */
3473 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3474 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3477 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3478 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3481 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3482 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3483 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3486 extern struct i2c_adapter
*
3487 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3488 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3489 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3490 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3492 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3494 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3497 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3498 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3499 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3500 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3501 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3502 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3503 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3504 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3505 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3507 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3511 /* intel_opregion.c */
3513 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3514 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3515 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3516 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3517 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3519 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3521 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3523 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3524 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3525 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3526 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3530 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3535 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3539 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3547 extern void intel_register_dsm_handler(void);
3548 extern void intel_unregister_dsm_handler(void);
3550 static inline void intel_register_dsm_handler(void) { return; }
3551 static inline void intel_unregister_dsm_handler(void) { return; }
3552 #endif /* CONFIG_ACPI */
3554 /* intel_device_info.c */
3555 static inline struct intel_device_info
*
3556 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3558 return (struct intel_device_info
*)&dev_priv
->info
;
3561 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3562 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3565 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3566 extern int intel_modeset_init(struct drm_device
*dev
);
3567 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3568 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3569 extern int intel_connector_register(struct drm_connector
*);
3570 extern void intel_connector_unregister(struct drm_connector
*);
3571 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3573 extern void intel_display_resume(struct drm_device
*dev
);
3574 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3575 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3576 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3577 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
3578 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3579 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3582 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3583 struct drm_file
*file
);
3586 extern struct intel_overlay_error_state
*
3587 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3588 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3589 struct intel_overlay_error_state
*error
);
3591 extern struct intel_display_error_state
*
3592 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3593 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3594 struct drm_i915_private
*dev_priv
,
3595 struct intel_display_error_state
*error
);
3597 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3598 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3600 /* intel_sideband.c */
3601 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3602 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3603 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3604 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3605 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3606 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3607 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3608 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3609 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3610 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3611 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3612 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3613 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3614 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3615 enum intel_sbi_destination destination
);
3616 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3617 enum intel_sbi_destination destination
);
3618 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3619 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3621 /* intel_dpio_phy.c */
3622 void bxt_port_to_phy_channel(enum port port
,
3623 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3624 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3625 enum port port
, u32 margin
, u32 scale
,
3626 u32 enable
, u32 deemphasis
);
3627 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3628 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3629 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3631 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3633 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3634 uint8_t lane_count
);
3635 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3636 uint8_t lane_lat_optim_mask
);
3637 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3639 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3640 u32 deemph_reg_value
, u32 margin_reg_value
,
3641 bool uniq_trans_scale
);
3642 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3644 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3645 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3646 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3647 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3649 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3650 u32 demph_reg_value
, u32 preemph_reg_value
,
3651 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3652 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3653 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3654 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3656 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3657 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3659 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3660 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3662 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3663 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3664 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3665 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3667 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3668 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3669 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3670 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3672 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3673 * will be implemented using 2 32-bit writes in an arbitrary order with
3674 * an arbitrary delay between them. This can cause the hardware to
3675 * act upon the intermediate value, possibly leading to corruption and
3676 * machine death. For this reason we do not support I915_WRITE64, or
3677 * dev_priv->uncore.funcs.mmio_writeq.
3679 * When reading a 64-bit value as two 32-bit values, the delay may cause
3680 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3681 * occasionally a 64-bit register does not actualy support a full readq
3682 * and must be read using two 32-bit reads.
3684 * You have been warned.
3686 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3688 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3689 u32 upper, lower, old_upper, loop = 0; \
3690 upper = I915_READ(upper_reg); \
3692 old_upper = upper; \
3693 lower = I915_READ(lower_reg); \
3694 upper = I915_READ(upper_reg); \
3695 } while (upper != old_upper && loop++ < 2); \
3696 (u64)upper << 32 | lower; })
3698 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3699 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3701 #define __raw_read(x, s) \
3702 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3705 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3708 #define __raw_write(x, s) \
3709 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3710 i915_reg_t reg, uint##x##_t val) \
3712 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3727 /* These are untraced mmio-accessors that are only valid to be used inside
3728 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3731 * Think twice, and think again, before using these.
3733 * As an example, these accessors can possibly be used between:
3735 * spin_lock_irq(&dev_priv->uncore.lock);
3736 * intel_uncore_forcewake_get__locked();
3740 * intel_uncore_forcewake_put__locked();
3741 * spin_unlock_irq(&dev_priv->uncore.lock);
3744 * Note: some registers may not need forcewake held, so
3745 * intel_uncore_forcewake_{get,put} can be omitted, see
3746 * intel_uncore_forcewake_for_reg().
3748 * Certain architectures will die if the same cacheline is concurrently accessed
3749 * by different clients (e.g. on Ivybridge). Access to registers should
3750 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3751 * a more localised lock guarding all access to that bank of registers.
3753 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3754 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3755 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3756 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3758 /* "Broadcast RGB" property */
3759 #define INTEL_BROADCAST_RGB_AUTO 0
3760 #define INTEL_BROADCAST_RGB_FULL 1
3761 #define INTEL_BROADCAST_RGB_LIMITED 2
3763 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
3765 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3766 return VLV_VGACNTRL
;
3767 else if (INTEL_GEN(dev_priv
) >= 5)
3768 return CPU_VGACNTRL
;
3773 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3775 unsigned long j
= msecs_to_jiffies(m
);
3777 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3780 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3782 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3785 static inline unsigned long
3786 timespec_to_jiffies_timeout(const struct timespec
*value
)
3788 unsigned long j
= timespec_to_jiffies(value
);
3790 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3794 * If you need to wait X milliseconds between events A and B, but event B
3795 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3796 * when event A happened, then just before event B you call this function and
3797 * pass the timestamp as the first argument, and X as the second argument.
3800 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3802 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3805 * Don't re-read the value of "jiffies" every time since it may change
3806 * behind our back and break the math.
3808 tmp_jiffies
= jiffies
;
3809 target_jiffies
= timestamp_jiffies
+
3810 msecs_to_jiffies_timeout(to_wait_ms
);
3812 if (time_after(target_jiffies
, tmp_jiffies
)) {
3813 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3814 while (remaining_jiffies
)
3816 schedule_timeout_uninterruptible(remaining_jiffies
);
3821 __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3823 struct intel_engine_cs
*engine
= req
->engine
;
3825 /* Before we do the heavier coherent read of the seqno,
3826 * check the value (hopefully) in the CPU cacheline.
3828 if (__i915_gem_request_completed(req
))
3831 /* Ensure our read of the seqno is coherent so that we
3832 * do not "miss an interrupt" (i.e. if this is the last
3833 * request and the seqno write from the GPU is not visible
3834 * by the time the interrupt fires, we will see that the
3835 * request is incomplete and go back to sleep awaiting
3836 * another interrupt that will never come.)
3838 * Strictly, we only need to do this once after an interrupt,
3839 * but it is easier and safer to do it every time the waiter
3842 if (engine
->irq_seqno_barrier
&&
3843 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3844 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
3845 struct task_struct
*tsk
;
3847 /* The ordering of irq_posted versus applying the barrier
3848 * is crucial. The clearing of the current irq_posted must
3849 * be visible before we perform the barrier operation,
3850 * such that if a subsequent interrupt arrives, irq_posted
3851 * is reasserted and our task rewoken (which causes us to
3852 * do another __i915_request_irq_complete() immediately
3853 * and reapply the barrier). Conversely, if the clear
3854 * occurs after the barrier, then an interrupt that arrived
3855 * whilst we waited on the barrier would not trigger a
3856 * barrier on the next pass, and the read may not see the
3859 engine
->irq_seqno_barrier(engine
);
3861 /* If we consume the irq, but we are no longer the bottom-half,
3862 * the real bottom-half may not have serialised their own
3863 * seqno check with the irq-barrier (i.e. may have inspected
3864 * the seqno before we believe it coherent since they see
3865 * irq_posted == false but we are still running).
3868 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
3869 if (tsk
&& tsk
!= current
)
3870 /* Note that if the bottom-half is changed as we
3871 * are sending the wake-up, the new bottom-half will
3872 * be woken by whomever made the change. We only have
3873 * to worry about when we steal the irq-posted for
3876 wake_up_process(tsk
);
3879 if (__i915_gem_request_completed(req
))
3886 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
3887 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
3890 int remap_io_mapping(struct vm_area_struct
*vma
,
3891 unsigned long addr
, unsigned long pfn
, unsigned long size
,
3892 struct io_mapping
*iomap
);
3894 #define ptr_mask_bits(ptr) ({ \
3895 unsigned long __v = (unsigned long)(ptr); \
3896 (typeof(ptr))(__v & PAGE_MASK); \
3899 #define ptr_unpack_bits(ptr, bits) ({ \
3900 unsigned long __v = (unsigned long)(ptr); \
3901 (bits) = __v & ~PAGE_MASK; \
3902 (typeof(ptr))(__v & PAGE_MASK); \
3905 #define ptr_pack_bits(ptr, bits) \
3906 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3908 #define fetch_and_zero(ptr) ({ \
3909 typeof(*ptr) __T = *(ptr); \
3910 *(ptr) = (typeof(*ptr))0; \