1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
58 #include "intel_guc.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_fence_reg.h"
64 #include "i915_gem_object.h"
65 #include "i915_gem_gtt.h"
66 #include "i915_gem_render_state.h"
67 #include "i915_gem_request.h"
68 #include "i915_gem_timeline.h"
72 #include "intel_gvt.h"
74 /* General customization:
77 #define DRIVER_NAME "i915"
78 #define DRIVER_DESC "Intel Graphics"
79 #define DRIVER_DATE "20161121"
80 #define DRIVER_TIMESTAMP 1479717903
83 /* Many gcc seem to no see through this and fall over :( */
85 #define WARN_ON(x) ({ \
86 bool __i915_warn_cond = (x); \
87 if (__builtin_constant_p(__i915_warn_cond)) \
88 BUILD_BUG_ON(__i915_warn_cond); \
89 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
98 (long) (x), __func__);
100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
101 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
102 * which may not necessarily be a user visible problem. This will either
103 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
104 * enable distros and users to tailor their preferred amount of i915 abrt
107 #define I915_STATE_WARN(condition, format...) ({ \
108 int __ret_warn_on = !!(condition); \
109 if (unlikely(__ret_warn_on)) \
110 if (!WARN(i915.verbose_state_checks, format)) \
112 unlikely(__ret_warn_on); \
115 #define I915_STATE_WARN_ON(x) \
116 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
118 bool __i915_inject_load_failure(const char *func
, int line
);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
122 static inline const char *yesno(bool v
)
124 return v
? "yes" : "no";
127 static inline const char *onoff(bool v
)
129 return v
? "on" : "off";
132 static inline const char *enableddisabled(bool v
)
134 return v
? "enabled" : "disabled";
143 I915_MAX_PIPES
= _PIPE_EDP
145 #define pipe_name(p) ((p) + 'A')
157 static inline const char *transcoder_name(enum transcoder transcoder
)
159 switch (transcoder
) {
168 case TRANSCODER_DSI_A
:
170 case TRANSCODER_DSI_C
:
177 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
179 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
183 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
184 * number of planes per CRTC. Not all platforms really have this many planes,
185 * which means some arrays of size I915_MAX_PLANES may have unused entries
186 * between the topmost sprite plane and the cursor plane.
195 #define plane_name(p) ((p) + 'A')
197 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
208 #define port_name(p) ((p) + 'A')
210 #define I915_NUM_PHYS_VLV 2
222 enum intel_display_power_domain
{
226 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
227 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
228 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
229 POWER_DOMAIN_TRANSCODER_A
,
230 POWER_DOMAIN_TRANSCODER_B
,
231 POWER_DOMAIN_TRANSCODER_C
,
232 POWER_DOMAIN_TRANSCODER_EDP
,
233 POWER_DOMAIN_TRANSCODER_DSI_A
,
234 POWER_DOMAIN_TRANSCODER_DSI_C
,
235 POWER_DOMAIN_PORT_DDI_A_LANES
,
236 POWER_DOMAIN_PORT_DDI_B_LANES
,
237 POWER_DOMAIN_PORT_DDI_C_LANES
,
238 POWER_DOMAIN_PORT_DDI_D_LANES
,
239 POWER_DOMAIN_PORT_DDI_E_LANES
,
240 POWER_DOMAIN_PORT_DSI
,
241 POWER_DOMAIN_PORT_CRT
,
242 POWER_DOMAIN_PORT_OTHER
,
251 POWER_DOMAIN_MODESET
,
257 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
258 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
259 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
260 #define POWER_DOMAIN_TRANSCODER(tran) \
261 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
262 (tran) + POWER_DOMAIN_TRANSCODER_A)
266 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
278 #define for_each_hpd_pin(__pin) \
279 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
281 struct i915_hotplug
{
282 struct work_struct hotplug_work
;
285 unsigned long last_jiffies
;
290 HPD_MARK_DISABLED
= 2
292 } stats
[HPD_NUM_PINS
];
294 struct delayed_work reenable_work
;
296 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
299 struct work_struct dig_port_work
;
301 struct work_struct poll_init_work
;
305 * if we get a HPD irq from DP and a HPD irq from non-DP
306 * the non-DP HPD could block the workqueue on a mode config
307 * mutex getting, that userspace may have taken. However
308 * userspace is waiting on the DP workqueue to run which is
309 * blocked behind the non-DP one.
311 struct workqueue_struct
*dp_wq
;
314 #define I915_GEM_GPU_DOMAINS \
315 (I915_GEM_DOMAIN_RENDER | \
316 I915_GEM_DOMAIN_SAMPLER | \
317 I915_GEM_DOMAIN_COMMAND | \
318 I915_GEM_DOMAIN_INSTRUCTION | \
319 I915_GEM_DOMAIN_VERTEX)
321 #define for_each_pipe(__dev_priv, __p) \
322 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
323 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
324 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
325 for_each_if ((__mask) & (1 << (__p)))
326 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
328 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
330 #define for_each_sprite(__dev_priv, __p, __s) \
332 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
335 #define for_each_port_masked(__port, __ports_mask) \
336 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
337 for_each_if ((__ports_mask) & (1 << (__port)))
339 #define for_each_crtc(dev, crtc) \
340 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
342 #define for_each_intel_plane(dev, intel_plane) \
343 list_for_each_entry(intel_plane, \
344 &(dev)->mode_config.plane_list, \
347 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
348 list_for_each_entry(intel_plane, \
349 &(dev)->mode_config.plane_list, \
351 for_each_if ((plane_mask) & \
352 (1 << drm_plane_index(&intel_plane->base)))
354 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
355 list_for_each_entry(intel_plane, \
356 &(dev)->mode_config.plane_list, \
358 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
360 #define for_each_intel_crtc(dev, intel_crtc) \
361 list_for_each_entry(intel_crtc, \
362 &(dev)->mode_config.crtc_list, \
365 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
366 list_for_each_entry(intel_crtc, \
367 &(dev)->mode_config.crtc_list, \
369 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
371 #define for_each_intel_encoder(dev, intel_encoder) \
372 list_for_each_entry(intel_encoder, \
373 &(dev)->mode_config.encoder_list, \
376 #define for_each_intel_connector(dev, intel_connector) \
377 list_for_each_entry(intel_connector, \
378 &(dev)->mode_config.connector_list, \
381 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
382 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
383 for_each_if ((intel_encoder)->base.crtc == (__crtc))
385 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
386 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
387 for_each_if ((intel_connector)->base.encoder == (__encoder))
389 #define for_each_power_domain(domain, mask) \
390 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
391 for_each_if ((1 << (domain)) & (mask))
393 struct drm_i915_private
;
394 struct i915_mm_struct
;
395 struct i915_mmu_object
;
397 struct drm_i915_file_private
{
398 struct drm_i915_private
*dev_priv
;
399 struct drm_file
*file
;
403 struct list_head request_list
;
404 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
405 * chosen to prevent the CPU getting more than a frame ahead of the GPU
406 * (when using lax throttling for the frontbuffer). We also use it to
407 * offer free GPU waitboosts for severely congested workloads.
409 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
411 struct idr context_idr
;
413 struct intel_rps_client
{
414 struct list_head link
;
418 unsigned int bsd_engine
;
421 /* Used by dp and fdi links */
422 struct intel_link_m_n
{
430 void intel_link_compute_m_n(int bpp
, int nlanes
,
431 int pixel_clock
, int link_clock
,
432 struct intel_link_m_n
*m_n
);
434 /* Interface history:
437 * 1.2: Add Power Management
438 * 1.3: Add vblank support
439 * 1.4: Fix cmdbuffer path, add heap destroy
440 * 1.5: Add vblank pipe configuration
441 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
442 * - Support vertical blank on secondary display pipe
444 #define DRIVER_MAJOR 1
445 #define DRIVER_MINOR 6
446 #define DRIVER_PATCHLEVEL 0
448 struct opregion_header
;
449 struct opregion_acpi
;
450 struct opregion_swsci
;
451 struct opregion_asle
;
453 struct intel_opregion
{
454 struct opregion_header
*header
;
455 struct opregion_acpi
*acpi
;
456 struct opregion_swsci
*swsci
;
457 u32 swsci_gbda_sub_functions
;
458 u32 swsci_sbcb_sub_functions
;
459 struct opregion_asle
*asle
;
464 struct work_struct asle_work
;
466 #define OPREGION_SIZE (8*1024)
468 struct intel_overlay
;
469 struct intel_overlay_error_state
;
471 struct sdvo_device_mapping
{
480 struct intel_connector
;
481 struct intel_encoder
;
482 struct intel_atomic_state
;
483 struct intel_crtc_state
;
484 struct intel_initial_plane_config
;
489 struct drm_i915_display_funcs
{
490 int (*get_display_clock_speed
)(struct drm_i915_private
*dev_priv
);
491 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
492 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
493 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
494 struct intel_crtc
*intel_crtc
,
495 struct intel_crtc_state
*newstate
);
496 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
497 struct intel_crtc_state
*cstate
);
498 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
499 struct intel_crtc_state
*cstate
);
500 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
501 struct intel_crtc_state
*cstate
);
502 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
503 void (*update_wm
)(struct intel_crtc
*crtc
);
504 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
505 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
506 /* Returns the active state of the crtc, and if the crtc is active,
507 * fills out the pipe-config with the hw state. */
508 bool (*get_pipe_config
)(struct intel_crtc
*,
509 struct intel_crtc_state
*);
510 void (*get_initial_plane_config
)(struct intel_crtc
*,
511 struct intel_initial_plane_config
*);
512 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
513 struct intel_crtc_state
*crtc_state
);
514 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
515 struct drm_atomic_state
*old_state
);
516 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
517 struct drm_atomic_state
*old_state
);
518 void (*update_crtcs
)(struct drm_atomic_state
*state
,
519 unsigned int *crtc_vblank_mask
);
520 void (*audio_codec_enable
)(struct drm_connector
*connector
,
521 struct intel_encoder
*encoder
,
522 const struct drm_display_mode
*adjusted_mode
);
523 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
524 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
525 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
526 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
527 struct drm_framebuffer
*fb
,
528 struct drm_i915_gem_object
*obj
,
529 struct drm_i915_gem_request
*req
,
531 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
532 /* clock updates for mode set */
534 /* render clock increase/decrease */
535 /* display clock increase/decrease */
536 /* pll clock increase/decrease */
538 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
539 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
542 enum forcewake_domain_id
{
543 FW_DOMAIN_ID_RENDER
= 0,
544 FW_DOMAIN_ID_BLITTER
,
550 enum forcewake_domains
{
551 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
552 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
553 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
554 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
559 #define FW_REG_READ (1)
560 #define FW_REG_WRITE (2)
562 enum decoupled_power_domain
{
563 GEN9_DECOUPLED_PD_BLITTER
= 0,
564 GEN9_DECOUPLED_PD_RENDER
,
565 GEN9_DECOUPLED_PD_MEDIA
,
566 GEN9_DECOUPLED_PD_ALL
570 GEN9_DECOUPLED_OP_WRITE
= 0,
571 GEN9_DECOUPLED_OP_READ
574 enum forcewake_domains
575 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
576 i915_reg_t reg
, unsigned int op
);
578 struct intel_uncore_funcs
{
579 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
580 enum forcewake_domains domains
);
581 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
582 enum forcewake_domains domains
);
584 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
585 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
586 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
587 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
589 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
590 uint8_t val
, bool trace
);
591 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
592 uint16_t val
, bool trace
);
593 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
594 uint32_t val
, bool trace
);
597 struct intel_forcewake_range
{
601 enum forcewake_domains domains
;
604 struct intel_uncore
{
605 spinlock_t lock
; /** lock is also taken in irq contexts. */
607 const struct intel_forcewake_range
*fw_domains_table
;
608 unsigned int fw_domains_table_entries
;
610 struct intel_uncore_funcs funcs
;
614 enum forcewake_domains fw_domains
;
615 enum forcewake_domains fw_domains_active
;
617 struct intel_uncore_forcewake_domain
{
618 struct drm_i915_private
*i915
;
619 enum forcewake_domain_id id
;
620 enum forcewake_domains mask
;
622 struct hrtimer timer
;
629 } fw_domain
[FW_DOMAIN_ID_COUNT
];
631 int unclaimed_mmio_check
;
634 /* Iterate over initialised fw domains */
635 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
636 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
637 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
639 for_each_if ((mask__) & (domain__)->mask)
641 #define for_each_fw_domain(domain__, dev_priv__) \
642 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
644 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
645 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
646 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
649 struct work_struct work
;
651 uint32_t *dmc_payload
;
652 uint32_t dmc_fw_size
;
655 i915_reg_t mmioaddr
[8];
656 uint32_t mmiodata
[8];
658 uint32_t allowed_dc_mask
;
661 #define DEV_INFO_FOR_EACH_FLAG(func) \
662 /* Keep is_* in chronological order */ \
670 func(is_broadwater); \
671 func(is_crestline); \
672 func(is_ivybridge); \
673 func(is_valleyview); \
674 func(is_cherryview); \
676 func(is_broadwell); \
680 func(is_alpha_support); \
681 /* Keep has_* in alphabetical order */ \
682 func(has_64bit_reloc); \
687 func(has_fpga_dbg); \
688 func(has_gmbus_irq); \
689 func(has_gmch_display); \
692 func(has_hw_contexts); \
695 func(has_logical_ring_contexts); \
697 func(has_pipe_cxsr); \
698 func(has_pooled_eu); \
702 func(has_resource_streamer); \
703 func(has_runtime_pm); \
705 func(cursor_needs_physical); \
706 func(hws_needs_physical); \
707 func(overlay_needs_physical); \
709 func(has_decoupled_mmio)
711 struct sseu_dev_info
{
717 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
720 u8 has_subslice_pg
:1;
724 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
726 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
729 struct intel_device_info
{
730 u32 display_mmio_offset
;
733 u8 num_sprites
[I915_MAX_PIPES
];
736 u8 ring_mask
; /* Rings supported by the HW */
738 #define DEFINE_FLAG(name) u8 name:1
739 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
741 u16 ddb_size
; /* in blocks */
742 /* Register offsets for the various display pipes and transcoders */
743 int pipe_offsets
[I915_MAX_TRANSCODERS
];
744 int trans_offsets
[I915_MAX_TRANSCODERS
];
745 int palette_offsets
[I915_MAX_PIPES
];
746 int cursor_offsets
[I915_MAX_PIPES
];
748 /* Slice/subslice/EU info */
749 struct sseu_dev_info sseu
;
752 u16 degamma_lut_size
;
757 struct intel_display_error_state
;
759 struct drm_i915_error_state
{
762 struct timeval boottime
;
763 struct timeval uptime
;
765 struct drm_i915_private
*i915
;
772 struct intel_device_info device_info
;
774 /* Generic register state */
782 u32 error
; /* gen6+ */
783 u32 err_int
; /* gen7 */
784 u32 fault_data0
; /* gen8, gen9 */
785 u32 fault_data1
; /* gen8, gen9 */
792 u64 fence
[I915_MAX_NUM_FENCES
];
793 struct intel_overlay_error_state
*overlay
;
794 struct intel_display_error_state
*display
;
795 struct drm_i915_error_object
*semaphore
;
796 struct drm_i915_error_object
*guc_log
;
798 struct drm_i915_error_engine
{
800 /* Software tracked state */
804 enum intel_engine_hangcheck_action hangcheck_action
;
805 struct i915_address_space
*vm
;
808 /* position of active request inside the ring */
809 u32 rq_head
, rq_post
, rq_tail
;
811 /* our own tracking of ring head and tail */
834 u32 rc_psmi
; /* sleep state */
835 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
836 struct intel_instdone instdone
;
838 struct drm_i915_error_object
{
844 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
846 struct drm_i915_error_object
*wa_ctx
;
848 struct drm_i915_error_request
{
855 } *requests
, execlist
[2];
857 struct drm_i915_error_waiter
{
858 char comm
[TASK_COMM_LEN
];
872 char comm
[TASK_COMM_LEN
];
873 } engine
[I915_NUM_ENGINES
];
875 struct drm_i915_error_buffer
{
878 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
882 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
889 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
890 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
891 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
894 enum i915_cache_level
{
896 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
897 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
898 caches, eg sampler/render caches, and the
899 large Last-Level-Cache. LLC is coherent with
900 the CPU, but L3 is only visible to the GPU. */
901 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
904 struct i915_ctx_hang_stats
{
905 /* This context had batch pending when hang was declared */
906 unsigned batch_pending
;
908 /* This context had batch active when hang was declared */
909 unsigned batch_active
;
911 /* Time when this context was last blamed for a GPU reset */
912 unsigned long guilty_ts
;
914 /* If the contexts causes a second GPU hang within this time,
915 * it is permanently banned from submitting any more work.
917 unsigned long ban_period_seconds
;
919 /* This context is banned to submit more work */
923 /* This must match up with the value previously used for execbuf2.rsvd1. */
924 #define DEFAULT_CONTEXT_HANDLE 0
927 * struct i915_gem_context - as the name implies, represents a context.
928 * @ref: reference count.
929 * @user_handle: userspace tracking identity for this context.
930 * @remap_slice: l3 row remapping information.
931 * @flags: context specific flags:
932 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
933 * @file_priv: filp associated with this context (NULL for global default
935 * @hang_stats: information about the role of this context in possible GPU
937 * @ppgtt: virtual memory space used by this context.
938 * @legacy_hw_ctx: render context backing object and whether it is correctly
939 * initialized (legacy ring submission mechanism only).
940 * @link: link in the global list of contexts.
942 * Contexts are memory images used by the hardware to store copies of their
945 struct i915_gem_context
{
947 struct drm_i915_private
*i915
;
948 struct drm_i915_file_private
*file_priv
;
949 struct i915_hw_ppgtt
*ppgtt
;
953 struct i915_ctx_hang_stats hang_stats
;
956 #define CONTEXT_NO_ZEROMAP BIT(0)
957 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
959 /* Unique identifier for this context, used by the hw for tracking */
962 int priority
; /* greater priorities are serviced first */
966 struct intel_context
{
967 struct i915_vma
*state
;
968 struct intel_ring
*ring
;
969 uint32_t *lrc_reg_state
;
973 } engine
[I915_NUM_ENGINES
];
976 struct atomic_notifier_head status_notifier
;
977 bool execlists_force_single_submission
;
979 struct list_head link
;
994 /* This is always the inner lock when overlapping with struct_mutex and
995 * it's the outer lock when overlapping with stolen_lock. */
998 unsigned int possible_framebuffer_bits
;
999 unsigned int busy_bits
;
1000 unsigned int visible_pipes_mask
;
1001 struct intel_crtc
*crtc
;
1003 struct drm_mm_node compressed_fb
;
1004 struct drm_mm_node
*compressed_llb
;
1011 bool underrun_detected
;
1012 struct work_struct underrun_work
;
1014 struct intel_fbc_state_cache
{
1016 unsigned int mode_flags
;
1017 uint32_t hsw_bdw_pixel_rate
;
1021 unsigned int rotation
;
1028 u64 ilk_ggtt_offset
;
1029 uint32_t pixel_format
;
1030 unsigned int stride
;
1032 unsigned int tiling_mode
;
1036 struct intel_fbc_reg_params
{
1040 unsigned int fence_y_offset
;
1045 uint32_t pixel_format
;
1046 unsigned int stride
;
1053 struct intel_fbc_work
{
1055 u32 scheduled_vblank
;
1056 struct work_struct work
;
1059 const char *no_fbc_reason
;
1063 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1064 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1065 * parsing for same resolution.
1067 enum drrs_refresh_rate_type
{
1070 DRRS_MAX_RR
, /* RR count */
1073 enum drrs_support_type
{
1074 DRRS_NOT_SUPPORTED
= 0,
1075 STATIC_DRRS_SUPPORT
= 1,
1076 SEAMLESS_DRRS_SUPPORT
= 2
1082 struct delayed_work work
;
1083 struct intel_dp
*dp
;
1084 unsigned busy_frontbuffer_bits
;
1085 enum drrs_refresh_rate_type refresh_rate_type
;
1086 enum drrs_support_type type
;
1093 struct intel_dp
*enabled
;
1095 struct delayed_work work
;
1096 unsigned busy_frontbuffer_bits
;
1098 bool aux_frame_sync
;
1103 PCH_NONE
= 0, /* No PCH present */
1104 PCH_IBX
, /* Ibexpeak PCH */
1105 PCH_CPT
, /* Cougarpoint PCH */
1106 PCH_LPT
, /* Lynxpoint PCH */
1107 PCH_SPT
, /* Sunrisepoint PCH */
1108 PCH_KBP
, /* Kabypoint PCH */
1112 enum intel_sbi_destination
{
1117 #define QUIRK_PIPEA_FORCE (1<<0)
1118 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1119 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1120 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1121 #define QUIRK_PIPEB_FORCE (1<<4)
1122 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1125 struct intel_fbc_work
;
1127 struct intel_gmbus
{
1128 struct i2c_adapter adapter
;
1129 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1132 i915_reg_t gpio_reg
;
1133 struct i2c_algo_bit_data bit_algo
;
1134 struct drm_i915_private
*dev_priv
;
1137 struct i915_suspend_saved_registers
{
1139 u32 saveFBC_CONTROL
;
1140 u32 saveCACHE_MODE_0
;
1141 u32 saveMI_ARB_STATE
;
1145 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1146 u32 savePCH_PORT_HOTPLUG
;
1150 struct vlv_s0ix_state
{
1157 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1158 u32 media_max_req_count
;
1159 u32 gfx_max_req_count
;
1185 u32 rp_down_timeout
;
1191 /* Display 1 CZ domain */
1196 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1198 /* GT SA CZ domain */
1205 /* Display 2 CZ domain */
1209 u32 clock_gate_dis2
;
1212 struct intel_rps_ei
{
1218 struct intel_gen6_power_mgmt
{
1220 * work, interrupts_enabled and pm_iir are protected by
1221 * dev_priv->irq_lock
1223 struct work_struct work
;
1224 bool interrupts_enabled
;
1227 /* PM interrupt bits that should never be masked */
1230 /* Frequencies are stored in potentially platform dependent multiples.
1231 * In other words, *_freq needs to be multiplied by X to be interesting.
1232 * Soft limits are those which are used for the dynamic reclocking done
1233 * by the driver (raise frequencies under heavy loads, and lower for
1234 * lighter loads). Hard limits are those imposed by the hardware.
1236 * A distinction is made for overclocking, which is never enabled by
1237 * default, and is considered to be above the hard limit if it's
1240 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1241 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1242 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1243 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1244 u8 min_freq
; /* AKA RPn. Minimum frequency */
1245 u8 boost_freq
; /* Frequency to request when wait boosting */
1246 u8 idle_freq
; /* Frequency to request when we are idle */
1247 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1248 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1249 u8 rp0_freq
; /* Non-overclocked max frequency. */
1250 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1252 u8 up_threshold
; /* Current %busy required to uplock */
1253 u8 down_threshold
; /* Current %busy required to downclock */
1256 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1258 spinlock_t client_lock
;
1259 struct list_head clients
;
1263 struct delayed_work autoenable_work
;
1266 /* manual wa residency calculations */
1267 struct intel_rps_ei up_ei
, down_ei
;
1270 * Protects RPS/RC6 register access and PCU communication.
1271 * Must be taken after struct_mutex if nested. Note that
1272 * this lock may be held for long periods of time when
1273 * talking to hw - so only take it when talking to hw!
1275 struct mutex hw_lock
;
1278 /* defined intel_pm.c */
1279 extern spinlock_t mchdev_lock
;
1281 struct intel_ilk_power_mgmt
{
1289 unsigned long last_time1
;
1290 unsigned long chipset_power
;
1293 unsigned long gfx_power
;
1300 struct drm_i915_private
;
1301 struct i915_power_well
;
1303 struct i915_power_well_ops
{
1305 * Synchronize the well's hw state to match the current sw state, for
1306 * example enable/disable it based on the current refcount. Called
1307 * during driver init and resume time, possibly after first calling
1308 * the enable/disable handlers.
1310 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1311 struct i915_power_well
*power_well
);
1313 * Enable the well and resources that depend on it (for example
1314 * interrupts located on the well). Called after the 0->1 refcount
1317 void (*enable
)(struct drm_i915_private
*dev_priv
,
1318 struct i915_power_well
*power_well
);
1320 * Disable the well and resources that depend on it. Called after
1321 * the 1->0 refcount transition.
1323 void (*disable
)(struct drm_i915_private
*dev_priv
,
1324 struct i915_power_well
*power_well
);
1325 /* Returns the hw enabled state. */
1326 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1327 struct i915_power_well
*power_well
);
1330 /* Power well structure for haswell */
1331 struct i915_power_well
{
1334 /* power well enable/disable usage count */
1336 /* cached hw enabled state */
1338 unsigned long domains
;
1339 /* unique identifier for this power well */
1342 * Arbitraty data associated with this power well. Platform and power
1346 const struct i915_power_well_ops
*ops
;
1349 struct i915_power_domains
{
1351 * Power wells needed for initialization at driver init and suspend
1352 * time are on. They are kept on until after the first modeset.
1356 int power_well_count
;
1359 int domain_use_count
[POWER_DOMAIN_NUM
];
1360 struct i915_power_well
*power_wells
;
1363 #define MAX_L3_SLICES 2
1364 struct intel_l3_parity
{
1365 u32
*remap_info
[MAX_L3_SLICES
];
1366 struct work_struct error_work
;
1370 struct i915_gem_mm
{
1371 /** Memory allocator for GTT stolen memory */
1372 struct drm_mm stolen
;
1373 /** Protects the usage of the GTT stolen memory allocator. This is
1374 * always the inner lock when overlapping with struct_mutex. */
1375 struct mutex stolen_lock
;
1377 /** List of all objects in gtt_space. Used to restore gtt
1378 * mappings on resume */
1379 struct list_head bound_list
;
1381 * List of objects which are not bound to the GTT (thus
1382 * are idle and not used by the GPU). These objects may or may
1383 * not actually have any pages attached.
1385 struct list_head unbound_list
;
1387 /** List of all objects in gtt_space, currently mmaped by userspace.
1388 * All objects within this list must also be on bound_list.
1390 struct list_head userfault_list
;
1393 * List of objects which are pending destruction.
1395 struct llist_head free_list
;
1396 struct work_struct free_work
;
1398 /** Usable portion of the GTT for GEM */
1399 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1401 /** PPGTT used for aliasing the PPGTT with the GTT */
1402 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1404 struct notifier_block oom_notifier
;
1405 struct notifier_block vmap_notifier
;
1406 struct shrinker shrinker
;
1408 /** LRU list of objects with fence regs on them. */
1409 struct list_head fence_list
;
1412 * Are we in a non-interruptible section of code like
1417 /* the indicator for dispatch video commands on two BSD rings */
1418 atomic_t bsd_engine_dispatch_index
;
1420 /** Bit 6 swizzling required for X tiling */
1421 uint32_t bit_6_swizzle_x
;
1422 /** Bit 6 swizzling required for Y tiling */
1423 uint32_t bit_6_swizzle_y
;
1425 /* accounting, useful for userland debugging */
1426 spinlock_t object_stat_lock
;
1431 struct drm_i915_error_state_buf
{
1432 struct drm_i915_private
*i915
;
1441 struct i915_error_state_file_priv
{
1442 struct drm_device
*dev
;
1443 struct drm_i915_error_state
*error
;
1446 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1447 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1449 struct i915_gpu_error
{
1450 /* For hangcheck timer */
1451 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1452 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1453 /* Hang gpu twice in this window and your context gets banned */
1454 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1456 struct delayed_work hangcheck_work
;
1458 /* For reset and error_state handling. */
1460 /* Protected by the above dev->gpu_error.lock. */
1461 struct drm_i915_error_state
*first_error
;
1463 unsigned long missed_irq_rings
;
1466 * State variable controlling the reset flow and count
1468 * This is a counter which gets incremented when reset is triggered,
1470 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1471 * meaning that any waiters holding onto the struct_mutex should
1472 * relinquish the lock immediately in order for the reset to start.
1474 * If reset is not completed succesfully, the I915_WEDGE bit is
1475 * set meaning that hardware is terminally sour and there is no
1476 * recovery. All waiters on the reset_queue will be woken when
1479 * This counter is used by the wait_seqno code to notice that reset
1480 * event happened and it needs to restart the entire ioctl (since most
1481 * likely the seqno it waited for won't ever signal anytime soon).
1483 * This is important for lock-free wait paths, where no contended lock
1484 * naturally enforces the correct ordering between the bail-out of the
1485 * waiter and the gpu reset work code.
1487 unsigned long reset_count
;
1489 unsigned long flags
;
1490 #define I915_RESET_IN_PROGRESS 0
1491 #define I915_WEDGED (BITS_PER_LONG - 1)
1494 * Waitqueue to signal when a hang is detected. Used to for waiters
1495 * to release the struct_mutex for the reset to procede.
1497 wait_queue_head_t wait_queue
;
1500 * Waitqueue to signal when the reset has completed. Used by clients
1501 * that wait for dev_priv->mm.wedged to settle.
1503 wait_queue_head_t reset_queue
;
1505 /* For missed irq/seqno simulation. */
1506 unsigned long test_irq_rings
;
1509 enum modeset_restore
{
1510 MODESET_ON_LID_OPEN
,
1515 #define DP_AUX_A 0x40
1516 #define DP_AUX_B 0x10
1517 #define DP_AUX_C 0x20
1518 #define DP_AUX_D 0x30
1520 #define DDC_PIN_B 0x05
1521 #define DDC_PIN_C 0x04
1522 #define DDC_PIN_D 0x06
1524 struct ddi_vbt_port_info
{
1526 * This is an index in the HDMI/DVI DDI buffer translation table.
1527 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1528 * populate this field.
1530 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1531 uint8_t hdmi_level_shift
;
1533 uint8_t supports_dvi
:1;
1534 uint8_t supports_hdmi
:1;
1535 uint8_t supports_dp
:1;
1537 uint8_t alternate_aux_channel
;
1538 uint8_t alternate_ddc_pin
;
1540 uint8_t dp_boost_level
;
1541 uint8_t hdmi_boost_level
;
1544 enum psr_lines_to_wait
{
1545 PSR_0_LINES_TO_WAIT
= 0,
1547 PSR_4_LINES_TO_WAIT
,
1551 struct intel_vbt_data
{
1552 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1553 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1556 unsigned int int_tv_support
:1;
1557 unsigned int lvds_dither
:1;
1558 unsigned int lvds_vbt
:1;
1559 unsigned int int_crt_support
:1;
1560 unsigned int lvds_use_ssc
:1;
1561 unsigned int display_clock_mode
:1;
1562 unsigned int fdi_rx_polarity_inverted
:1;
1563 unsigned int panel_type
:4;
1565 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1567 enum drrs_support_type drrs_type
;
1578 struct edp_power_seq pps
;
1583 bool require_aux_wakeup
;
1585 enum psr_lines_to_wait lines_to_wait
;
1586 int tp1_wakeup_time
;
1587 int tp2_tp3_wakeup_time
;
1593 bool active_low_pwm
;
1594 u8 min_brightness
; /* min_brightness/255 of max */
1595 enum intel_backlight_type type
;
1601 struct mipi_config
*config
;
1602 struct mipi_pps_data
*pps
;
1606 const u8
*sequence
[MIPI_SEQ_MAX
];
1612 union child_device_config
*child_dev
;
1614 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1615 struct sdvo_device_mapping sdvo_mappings
[2];
1618 enum intel_ddb_partitioning
{
1620 INTEL_DDB_PART_5_6
, /* IVB+ */
1623 struct intel_wm_level
{
1631 struct ilk_wm_values
{
1632 uint32_t wm_pipe
[3];
1634 uint32_t wm_lp_spr
[3];
1635 uint32_t wm_linetime
[3];
1637 enum intel_ddb_partitioning partitioning
;
1640 struct vlv_pipe_wm
{
1651 struct vlv_wm_values
{
1652 struct vlv_pipe_wm pipe
[3];
1653 struct vlv_sr_wm sr
;
1663 struct skl_ddb_entry
{
1664 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1667 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1669 return entry
->end
- entry
->start
;
1672 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1673 const struct skl_ddb_entry
*e2
)
1675 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1681 struct skl_ddb_allocation
{
1682 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1683 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1686 struct skl_wm_values
{
1687 unsigned dirty_pipes
;
1688 struct skl_ddb_allocation ddb
;
1691 struct skl_wm_level
{
1693 uint16_t plane_res_b
;
1694 uint8_t plane_res_l
;
1698 * This struct helps tracking the state needed for runtime PM, which puts the
1699 * device in PCI D3 state. Notice that when this happens, nothing on the
1700 * graphics device works, even register access, so we don't get interrupts nor
1703 * Every piece of our code that needs to actually touch the hardware needs to
1704 * either call intel_runtime_pm_get or call intel_display_power_get with the
1705 * appropriate power domain.
1707 * Our driver uses the autosuspend delay feature, which means we'll only really
1708 * suspend if we stay with zero refcount for a certain amount of time. The
1709 * default value is currently very conservative (see intel_runtime_pm_enable), but
1710 * it can be changed with the standard runtime PM files from sysfs.
1712 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1713 * goes back to false exactly before we reenable the IRQs. We use this variable
1714 * to check if someone is trying to enable/disable IRQs while they're supposed
1715 * to be disabled. This shouldn't happen and we'll print some error messages in
1718 * For more, read the Documentation/power/runtime_pm.txt.
1720 struct i915_runtime_pm
{
1721 atomic_t wakeref_count
;
1726 enum intel_pipe_crc_source
{
1727 INTEL_PIPE_CRC_SOURCE_NONE
,
1728 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1729 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1730 INTEL_PIPE_CRC_SOURCE_PF
,
1731 INTEL_PIPE_CRC_SOURCE_PIPE
,
1732 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1733 INTEL_PIPE_CRC_SOURCE_TV
,
1734 INTEL_PIPE_CRC_SOURCE_DP_B
,
1735 INTEL_PIPE_CRC_SOURCE_DP_C
,
1736 INTEL_PIPE_CRC_SOURCE_DP_D
,
1737 INTEL_PIPE_CRC_SOURCE_AUTO
,
1738 INTEL_PIPE_CRC_SOURCE_MAX
,
1741 struct intel_pipe_crc_entry
{
1746 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1747 struct intel_pipe_crc
{
1749 bool opened
; /* exclusive access to the result file */
1750 struct intel_pipe_crc_entry
*entries
;
1751 enum intel_pipe_crc_source source
;
1753 wait_queue_head_t wq
;
1756 struct i915_frontbuffer_tracking
{
1760 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1767 struct i915_wa_reg
{
1770 /* bitmask representing WA bits */
1775 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1776 * allowing it for RCS as we don't foresee any requirement of having
1777 * a whitelist for other engines. When it is really required for
1778 * other engines then the limit need to be increased.
1780 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1782 struct i915_workarounds
{
1783 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1785 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1788 struct i915_virtual_gpu
{
1792 /* used in computing the new watermarks state */
1793 struct intel_wm_config
{
1794 unsigned int num_pipes_active
;
1795 bool sprites_enabled
;
1796 bool sprites_scaled
;
1799 struct drm_i915_private
{
1800 struct drm_device drm
;
1802 struct kmem_cache
*objects
;
1803 struct kmem_cache
*vmas
;
1804 struct kmem_cache
*requests
;
1805 struct kmem_cache
*dependencies
;
1807 const struct intel_device_info info
;
1809 int relative_constants_mode
;
1813 struct intel_uncore uncore
;
1815 struct i915_virtual_gpu vgpu
;
1817 struct intel_gvt
*gvt
;
1819 struct intel_guc guc
;
1821 struct intel_csr csr
;
1823 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1825 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1826 * controller on different i2c buses. */
1827 struct mutex gmbus_mutex
;
1830 * Base address of the gmbus and gpio block.
1832 uint32_t gpio_mmio_base
;
1834 /* MMIO base address for MIPI regs */
1835 uint32_t mipi_mmio_base
;
1837 uint32_t psr_mmio_base
;
1839 uint32_t pps_mmio_base
;
1841 wait_queue_head_t gmbus_wait_queue
;
1843 struct pci_dev
*bridge_dev
;
1844 struct i915_gem_context
*kernel_context
;
1845 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
1846 struct i915_vma
*semaphore
;
1848 struct drm_dma_handle
*status_page_dmah
;
1849 struct resource mch_res
;
1851 /* protects the irq masks */
1852 spinlock_t irq_lock
;
1854 /* protects the mmio flip data */
1855 spinlock_t mmio_flip_lock
;
1857 bool display_irqs_enabled
;
1859 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1860 struct pm_qos_request pm_qos
;
1862 /* Sideband mailbox protection */
1863 struct mutex sb_lock
;
1865 /** Cached value of IMR to avoid reads in updating the bitfield */
1868 u32 de_irq_mask
[I915_MAX_PIPES
];
1875 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1877 struct i915_hotplug hotplug
;
1878 struct intel_fbc fbc
;
1879 struct i915_drrs drrs
;
1880 struct intel_opregion opregion
;
1881 struct intel_vbt_data vbt
;
1883 bool preserve_bios_swizzle
;
1886 struct intel_overlay
*overlay
;
1888 /* backlight registers and fields in struct intel_panel */
1889 struct mutex backlight_lock
;
1892 bool no_aux_handshake
;
1894 /* protects panel power sequencer state */
1895 struct mutex pps_mutex
;
1897 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1898 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1900 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1901 unsigned int skl_preferred_vco_freq
;
1902 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1903 unsigned int max_dotclk_freq
;
1904 unsigned int rawclk_freq
;
1905 unsigned int hpll_freq
;
1906 unsigned int czclk_freq
;
1909 unsigned int vco
, ref
;
1913 * wq - Driver workqueue for GEM.
1915 * NOTE: Work items scheduled here are not allowed to grab any modeset
1916 * locks, for otherwise the flushing done in the pageflip code will
1917 * result in deadlocks.
1919 struct workqueue_struct
*wq
;
1921 /* Display functions */
1922 struct drm_i915_display_funcs display
;
1924 /* PCH chipset type */
1925 enum intel_pch pch_type
;
1926 unsigned short pch_id
;
1928 unsigned long quirks
;
1930 enum modeset_restore modeset_restore
;
1931 struct mutex modeset_restore_lock
;
1932 struct drm_atomic_state
*modeset_restore_state
;
1933 struct drm_modeset_acquire_ctx reset_ctx
;
1935 struct list_head vm_list
; /* Global list of all address spaces */
1936 struct i915_ggtt ggtt
; /* VM representing the global address space */
1938 struct i915_gem_mm mm
;
1939 DECLARE_HASHTABLE(mm_structs
, 7);
1940 struct mutex mm_lock
;
1942 /* The hw wants to have a stable context identifier for the lifetime
1943 * of the context (for OA, PASID, faults, etc). This is limited
1944 * in execlists to 21 bits.
1946 struct ida context_hw_ida
;
1947 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1949 /* Kernel Modesetting */
1951 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1952 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1953 wait_queue_head_t pending_flip_queue
;
1955 #ifdef CONFIG_DEBUG_FS
1956 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1959 /* dpll and cdclk state is protected by connection_mutex */
1960 int num_shared_dpll
;
1961 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1962 const struct intel_dpll_mgr
*dpll_mgr
;
1965 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1966 * Must be global rather than per dpll, because on some platforms
1967 * plls share registers.
1969 struct mutex dpll_lock
;
1971 unsigned int active_crtcs
;
1972 unsigned int min_pixclk
[I915_MAX_PIPES
];
1974 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1976 struct i915_workarounds workarounds
;
1978 struct i915_frontbuffer_tracking fb_tracking
;
1982 bool mchbar_need_disable
;
1984 struct intel_l3_parity l3_parity
;
1986 /* Cannot be determined by PCIID. You must always read a register. */
1989 /* gen6+ rps state */
1990 struct intel_gen6_power_mgmt rps
;
1992 /* ilk-only ips/rps state. Everything in here is protected by the global
1993 * mchdev_lock in intel_pm.c */
1994 struct intel_ilk_power_mgmt ips
;
1996 struct i915_power_domains power_domains
;
1998 struct i915_psr psr
;
2000 struct i915_gpu_error gpu_error
;
2002 struct drm_i915_gem_object
*vlv_pctx
;
2004 #ifdef CONFIG_DRM_FBDEV_EMULATION
2005 /* list of fbdev register on this device */
2006 struct intel_fbdev
*fbdev
;
2007 struct work_struct fbdev_suspend_work
;
2010 struct drm_property
*broadcast_rgb_property
;
2011 struct drm_property
*force_audio_property
;
2013 /* hda/i915 audio component */
2014 struct i915_audio_component
*audio_component
;
2015 bool audio_component_registered
;
2017 * av_mutex - mutex for audio/video sync
2020 struct mutex av_mutex
;
2022 uint32_t hw_context_size
;
2023 struct list_head context_list
;
2027 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2028 u32 chv_phy_control
;
2030 * Shadows for CHV DPLL_MD regs to keep the state
2031 * checker somewhat working in the presence hardware
2032 * crappiness (can't read out DPLL_MD for pipes B & C).
2034 u32 chv_dpll_md
[I915_MAX_PIPES
];
2038 bool suspended_to_idle
;
2039 struct i915_suspend_saved_registers regfile
;
2040 struct vlv_s0ix_state vlv_s0ix_state
;
2043 I915_SAGV_UNKNOWN
= 0,
2046 I915_SAGV_NOT_CONTROLLED
2051 * Raw watermark latency values:
2052 * in 0.1us units for WM0,
2053 * in 0.5us units for WM1+.
2056 uint16_t pri_latency
[5];
2058 uint16_t spr_latency
[5];
2060 uint16_t cur_latency
[5];
2062 * Raw watermark memory latency values
2063 * for SKL for all 8 levels
2066 uint16_t skl_latency
[8];
2068 /* current hardware state */
2070 struct ilk_wm_values hw
;
2071 struct skl_wm_values skl_hw
;
2072 struct vlv_wm_values vlv
;
2078 * Should be held around atomic WM register writing; also
2079 * protects * intel_crtc->wm.active and
2080 * cstate->wm.need_postvbl_update.
2082 struct mutex wm_mutex
;
2085 * Set during HW readout of watermarks/DDB. Some platforms
2086 * need to know when we're still using BIOS-provided values
2087 * (which we don't fully trust).
2089 bool distrust_bios_wm
;
2092 struct i915_runtime_pm pm
;
2094 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2096 void (*resume
)(struct drm_i915_private
*);
2097 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2099 struct list_head timelines
;
2100 struct i915_gem_timeline global_timeline
;
2101 u32 active_requests
;
2104 * Is the GPU currently considered idle, or busy executing
2105 * userspace requests? Whilst idle, we allow runtime power
2106 * management to power down the hardware and display clocks.
2107 * In order to reduce the effect on performance, there
2108 * is a slight delay before we do so.
2113 * We leave the user IRQ off as much as possible,
2114 * but this means that requests will finish and never
2115 * be retired once the system goes idle. Set a timer to
2116 * fire periodically while the ring is running. When it
2117 * fires, go retire requests.
2119 struct delayed_work retire_work
;
2122 * When we detect an idle GPU, we want to turn on
2123 * powersaving features. So once we see that there
2124 * are no more requests outstanding and no more
2125 * arrive within a small period of time, we fire
2126 * off the idle_work.
2128 struct delayed_work idle_work
;
2130 ktime_t last_init_time
;
2133 /* perform PHY state sanity checks? */
2134 bool chv_phy_assert
[2];
2136 /* Used to save the pipe-to-encoder mapping for audio */
2137 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2140 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2141 * will be rejected. Instead look for a better place.
2145 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2147 return container_of(dev
, struct drm_i915_private
, drm
);
2150 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2152 return to_i915(dev_get_drvdata(kdev
));
2155 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2157 return container_of(guc
, struct drm_i915_private
, guc
);
2160 /* Simple iterator over all initialised engines */
2161 #define for_each_engine(engine__, dev_priv__, id__) \
2163 (id__) < I915_NUM_ENGINES; \
2165 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2167 #define __mask_next_bit(mask) ({ \
2168 int __idx = ffs(mask) - 1; \
2169 mask &= ~BIT(__idx); \
2173 /* Iterator over subset of engines selected by mask */
2174 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2175 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2176 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2178 enum hdmi_force_audio
{
2179 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2180 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2181 HDMI_AUDIO_AUTO
, /* trust EDID */
2182 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2185 #define I915_GTT_OFFSET_NONE ((u32)-1)
2188 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2189 * considered to be the frontbuffer for the given plane interface-wise. This
2190 * doesn't mean that the hw necessarily already scans it out, but that any
2191 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2193 * We have one bit per pipe and per scanout plane type.
2195 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2196 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2197 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2198 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2199 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2200 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2201 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2202 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2203 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2204 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2205 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2206 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2209 * Optimised SGL iterator for GEM objects
2211 static __always_inline
struct sgt_iter
{
2212 struct scatterlist
*sgp
;
2219 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2220 struct sgt_iter s
= { .sgp
= sgl
};
2223 s
.max
= s
.curr
= s
.sgp
->offset
;
2224 s
.max
+= s
.sgp
->length
;
2226 s
.dma
= sg_dma_address(s
.sgp
);
2228 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2234 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2237 if (unlikely(sg_is_chain(sg
)))
2238 sg
= sg_chain_ptr(sg
);
2243 * __sg_next - return the next scatterlist entry in a list
2244 * @sg: The current sg entry
2247 * If the entry is the last, return NULL; otherwise, step to the next
2248 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2249 * otherwise just return the pointer to the current element.
2251 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2253 #ifdef CONFIG_DEBUG_SG
2254 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2256 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2260 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2261 * @__dmap: DMA address (output)
2262 * @__iter: 'struct sgt_iter' (iterator state, internal)
2263 * @__sgt: sg_table to iterate over (input)
2265 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2266 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2267 ((__dmap) = (__iter).dma + (__iter).curr); \
2268 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2269 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2272 * for_each_sgt_page - iterate over the pages of the given sg_table
2273 * @__pp: page pointer (output)
2274 * @__iter: 'struct sgt_iter' (iterator state, internal)
2275 * @__sgt: sg_table to iterate over (input)
2277 #define for_each_sgt_page(__pp, __iter, __sgt) \
2278 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2279 ((__pp) = (__iter).pfn == 0 ? NULL : \
2280 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2281 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2282 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2285 * A command that requires special handling by the command parser.
2287 struct drm_i915_cmd_descriptor
{
2289 * Flags describing how the command parser processes the command.
2291 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2292 * a length mask if not set
2293 * CMD_DESC_SKIP: The command is allowed but does not follow the
2294 * standard length encoding for the opcode range in
2296 * CMD_DESC_REJECT: The command is never allowed
2297 * CMD_DESC_REGISTER: The command should be checked against the
2298 * register whitelist for the appropriate ring
2299 * CMD_DESC_MASTER: The command is allowed if the submitting process
2303 #define CMD_DESC_FIXED (1<<0)
2304 #define CMD_DESC_SKIP (1<<1)
2305 #define CMD_DESC_REJECT (1<<2)
2306 #define CMD_DESC_REGISTER (1<<3)
2307 #define CMD_DESC_BITMASK (1<<4)
2308 #define CMD_DESC_MASTER (1<<5)
2311 * The command's unique identification bits and the bitmask to get them.
2312 * This isn't strictly the opcode field as defined in the spec and may
2313 * also include type, subtype, and/or subop fields.
2321 * The command's length. The command is either fixed length (i.e. does
2322 * not include a length field) or has a length field mask. The flag
2323 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2324 * a length mask. All command entries in a command table must include
2325 * length information.
2333 * Describes where to find a register address in the command to check
2334 * against the ring's register whitelist. Only valid if flags has the
2335 * CMD_DESC_REGISTER bit set.
2337 * A non-zero step value implies that the command may access multiple
2338 * registers in sequence (e.g. LRI), in that case step gives the
2339 * distance in dwords between individual offset fields.
2347 #define MAX_CMD_DESC_BITMASKS 3
2349 * Describes command checks where a particular dword is masked and
2350 * compared against an expected value. If the command does not match
2351 * the expected value, the parser rejects it. Only valid if flags has
2352 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2355 * If the check specifies a non-zero condition_mask then the parser
2356 * only performs the check when the bits specified by condition_mask
2363 u32 condition_offset
;
2365 } bits
[MAX_CMD_DESC_BITMASKS
];
2369 * A table of commands requiring special handling by the command parser.
2371 * Each engine has an array of tables. Each table consists of an array of
2372 * command descriptors, which must be sorted with command opcodes in
2375 struct drm_i915_cmd_table
{
2376 const struct drm_i915_cmd_descriptor
*table
;
2380 static inline const struct intel_device_info
*
2381 intel_info(const struct drm_i915_private
*dev_priv
)
2383 return &dev_priv
->info
;
2386 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2388 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2389 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2391 #define REVID_FOREVER 0xff
2392 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2394 #define GEN_FOREVER (0)
2396 * Returns true if Gen is in inclusive range [Start, End].
2398 * Use GEN_FOREVER for unbound start and or end.
2400 #define IS_GEN(dev_priv, s, e) ({ \
2401 unsigned int __s = (s), __e = (e); \
2402 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2403 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2404 if ((__s) != GEN_FOREVER) \
2406 if ((__e) == GEN_FOREVER) \
2407 __e = BITS_PER_LONG - 1; \
2410 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2414 * Return true if revision is in range [since,until] inclusive.
2416 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2418 #define IS_REVID(p, since, until) \
2419 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2421 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2422 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2423 #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
2424 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2425 #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
2426 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2427 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2428 #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
2429 #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
2430 #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
2431 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2432 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2433 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2434 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2435 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
2436 #define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
2437 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2438 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2439 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2440 INTEL_DEVID(dev_priv) == 0x0152 || \
2441 INTEL_DEVID(dev_priv) == 0x015a)
2442 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2443 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2444 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2445 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2446 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2447 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2448 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2449 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2450 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2451 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2452 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2453 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2454 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2455 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2456 /* ULX machines are also considered ULT. */
2457 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2458 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2459 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2460 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2461 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2462 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2463 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2464 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2465 /* ULX machines are also considered ULT. */
2466 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2467 INTEL_DEVID(dev_priv) == 0x0A1E)
2468 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2469 INTEL_DEVID(dev_priv) == 0x1913 || \
2470 INTEL_DEVID(dev_priv) == 0x1916 || \
2471 INTEL_DEVID(dev_priv) == 0x1921 || \
2472 INTEL_DEVID(dev_priv) == 0x1926)
2473 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2474 INTEL_DEVID(dev_priv) == 0x1915 || \
2475 INTEL_DEVID(dev_priv) == 0x191E)
2476 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2477 INTEL_DEVID(dev_priv) == 0x5913 || \
2478 INTEL_DEVID(dev_priv) == 0x5916 || \
2479 INTEL_DEVID(dev_priv) == 0x5921 || \
2480 INTEL_DEVID(dev_priv) == 0x5926)
2481 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2482 INTEL_DEVID(dev_priv) == 0x5915 || \
2483 INTEL_DEVID(dev_priv) == 0x591E)
2484 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2485 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2486 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2487 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2489 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2491 #define SKL_REVID_A0 0x0
2492 #define SKL_REVID_B0 0x1
2493 #define SKL_REVID_C0 0x2
2494 #define SKL_REVID_D0 0x3
2495 #define SKL_REVID_E0 0x4
2496 #define SKL_REVID_F0 0x5
2497 #define SKL_REVID_G0 0x6
2498 #define SKL_REVID_H0 0x7
2500 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2502 #define BXT_REVID_A0 0x0
2503 #define BXT_REVID_A1 0x1
2504 #define BXT_REVID_B0 0x3
2505 #define BXT_REVID_C0 0x9
2507 #define IS_BXT_REVID(dev_priv, since, until) \
2508 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2510 #define KBL_REVID_A0 0x0
2511 #define KBL_REVID_B0 0x1
2512 #define KBL_REVID_C0 0x2
2513 #define KBL_REVID_D0 0x3
2514 #define KBL_REVID_E0 0x4
2516 #define IS_KBL_REVID(dev_priv, since, until) \
2517 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2520 * The genX designation typically refers to the render engine, so render
2521 * capability related checks should use IS_GEN, while display and other checks
2522 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2525 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2526 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2527 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2528 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2529 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2530 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2531 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2532 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2534 #define ENGINE_MASK(id) BIT(id)
2535 #define RENDER_RING ENGINE_MASK(RCS)
2536 #define BSD_RING ENGINE_MASK(VCS)
2537 #define BLT_RING ENGINE_MASK(BCS)
2538 #define VEBOX_RING ENGINE_MASK(VECS)
2539 #define BSD2_RING ENGINE_MASK(VCS2)
2540 #define ALL_ENGINES (~0)
2542 #define HAS_ENGINE(dev_priv, id) \
2543 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2545 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2546 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2547 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2548 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2550 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2551 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2552 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2553 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2554 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2556 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2558 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2559 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2560 ((dev_priv)->info.has_logical_ring_contexts)
2561 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2562 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2563 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2565 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2566 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2567 ((dev_priv)->info.overlay_needs_physical)
2569 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2570 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2572 /* WaRsDisableCoarsePowerGating:skl,bxt */
2573 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2574 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2575 IS_SKL_GT3(dev_priv) || \
2576 IS_SKL_GT4(dev_priv))
2579 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2580 * even when in MSI mode. This results in spurious interrupt warnings if the
2581 * legacy irq no. is shared with another device. The kernel then disables that
2582 * interrupt source and so prevents the other device from working properly.
2584 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2585 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2587 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2588 * rows, which changed the alignment requirements and fence programming.
2590 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2591 !(IS_I915G(dev_priv) || \
2592 IS_I915GM(dev_priv)))
2593 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2594 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2596 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2597 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2598 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2600 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2602 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2604 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2605 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2606 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2607 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2608 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2610 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2612 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2613 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2616 * For now, anything with a GuC requires uCode loading, and then supports
2617 * command submission once loaded. But these are logically independent
2618 * properties, so we have separate macros to test them.
2620 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2621 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2622 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2624 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2626 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2628 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2629 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2630 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2631 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2632 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2633 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2634 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2635 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2636 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2637 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2638 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2639 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2641 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2642 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2643 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2644 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2645 #define HAS_PCH_LPT_LP(dev_priv) \
2646 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2647 #define HAS_PCH_LPT_H(dev_priv) \
2648 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2649 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2650 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2651 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2652 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2654 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2656 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2658 /* DPF == dynamic parity feature */
2659 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2660 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2661 2 : HAS_L3_DPF(dev_priv))
2663 #define GT_FREQUENCY_MULTIPLIER 50
2664 #define GEN9_FREQ_SCALER 3
2666 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2668 #include "i915_trace.h"
2670 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2672 #ifdef CONFIG_INTEL_IOMMU
2673 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2679 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2680 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2682 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2685 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2689 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2690 const char *fmt
, ...);
2692 #define i915_report_error(dev_priv, fmt, ...) \
2693 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2695 #ifdef CONFIG_COMPAT
2696 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2699 #define i915_compat_ioctl NULL
2701 extern const struct dev_pm_ops i915_pm_ops
;
2703 extern int i915_driver_load(struct pci_dev
*pdev
,
2704 const struct pci_device_id
*ent
);
2705 extern void i915_driver_unload(struct drm_device
*dev
);
2706 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2707 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2708 extern void i915_reset(struct drm_i915_private
*dev_priv
);
2709 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2710 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2711 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
2712 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2713 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2714 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2715 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2716 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2718 /* intel_hotplug.c */
2719 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2720 u32 pin_mask
, u32 long_mask
);
2721 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2722 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2723 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2724 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2725 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2726 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2729 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2731 unsigned long delay
;
2733 if (unlikely(!i915
.enable_hangcheck
))
2736 /* Don't continually defer the hangcheck so that it is always run at
2737 * least once after work has been scheduled on any ring. Otherwise,
2738 * we will ignore a hung ring if a second ring is kept busy.
2741 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2742 queue_delayed_work(system_long_wq
,
2743 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2747 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2749 const char *fmt
, ...);
2751 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2752 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2753 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2755 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2756 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2757 bool restore_forcewake
);
2758 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2759 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2760 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2761 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2762 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2764 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2765 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2766 enum forcewake_domains domains
);
2767 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2768 enum forcewake_domains domains
);
2769 /* Like above but the caller must manage the uncore.lock itself.
2770 * Must be used with I915_READ_FW and friends.
2772 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2773 enum forcewake_domains domains
);
2774 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2775 enum forcewake_domains domains
);
2776 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2778 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2780 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
2784 const unsigned long timeout_ms
);
2785 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
2789 const unsigned long timeout_ms
);
2791 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2793 return dev_priv
->gvt
;
2796 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2798 return dev_priv
->vgpu
.active
;
2802 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2806 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2809 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2810 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2811 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2814 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2815 uint32_t interrupt_mask
,
2816 uint32_t enabled_irq_mask
);
2818 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2820 ilk_update_display_irq(dev_priv
, bits
, bits
);
2823 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2825 ilk_update_display_irq(dev_priv
, bits
, 0);
2827 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2829 uint32_t interrupt_mask
,
2830 uint32_t enabled_irq_mask
);
2831 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2832 enum pipe pipe
, uint32_t bits
)
2834 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2836 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2837 enum pipe pipe
, uint32_t bits
)
2839 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2841 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2842 uint32_t interrupt_mask
,
2843 uint32_t enabled_irq_mask
);
2845 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2847 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2850 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2852 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2856 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2857 struct drm_file
*file_priv
);
2858 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2859 struct drm_file
*file_priv
);
2860 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2861 struct drm_file
*file_priv
);
2862 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2863 struct drm_file
*file_priv
);
2864 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2865 struct drm_file
*file_priv
);
2866 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2867 struct drm_file
*file_priv
);
2868 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2869 struct drm_file
*file_priv
);
2870 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2871 struct drm_file
*file_priv
);
2872 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2873 struct drm_file
*file_priv
);
2874 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2875 struct drm_file
*file_priv
);
2876 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2877 struct drm_file
*file
);
2878 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2879 struct drm_file
*file
);
2880 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2881 struct drm_file
*file_priv
);
2882 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2883 struct drm_file
*file_priv
);
2884 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2885 struct drm_file
*file_priv
);
2886 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2887 struct drm_file
*file_priv
);
2888 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
2889 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2890 struct drm_file
*file
);
2891 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2892 struct drm_file
*file_priv
);
2893 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2894 struct drm_file
*file_priv
);
2895 int i915_gem_load_init(struct drm_device
*dev
);
2896 void i915_gem_load_cleanup(struct drm_device
*dev
);
2897 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
2898 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
2899 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
2901 void *i915_gem_object_alloc(struct drm_device
*dev
);
2902 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2903 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2904 const struct drm_i915_gem_object_ops
*ops
);
2905 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
2907 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2908 struct drm_device
*dev
, const void *data
, size_t size
);
2909 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
2910 void i915_gem_free_object(struct drm_gem_object
*obj
);
2912 struct i915_vma
* __must_check
2913 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2914 const struct i915_ggtt_view
*view
,
2919 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
2920 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2922 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
2924 static inline int __sg_page_count(const struct scatterlist
*sg
)
2926 return sg
->length
>> PAGE_SHIFT
;
2929 struct scatterlist
*
2930 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
2931 unsigned int n
, unsigned int *offset
);
2934 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
2938 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
2942 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
2945 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2946 struct sg_table
*pages
);
2947 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2949 static inline int __must_check
2950 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2952 might_lock(&obj
->mm
.lock
);
2954 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
2957 return __i915_gem_object_get_pages(obj
);
2961 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2963 GEM_BUG_ON(!obj
->mm
.pages
);
2965 atomic_inc(&obj
->mm
.pages_pin_count
);
2969 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
2971 return atomic_read(&obj
->mm
.pages_pin_count
);
2975 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2977 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
2978 GEM_BUG_ON(!obj
->mm
.pages
);
2980 atomic_dec(&obj
->mm
.pages_pin_count
);
2981 GEM_BUG_ON(atomic_read(&obj
->mm
.pages_pin_count
) < obj
->bind_count
);
2985 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2987 __i915_gem_object_unpin_pages(obj
);
2990 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
2995 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2996 enum i915_mm_subclass subclass
);
2997 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
2999 enum i915_map_type
{
3005 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3006 * @obj - the object to map into kernel address space
3007 * @type - the type of mapping, used to select pgprot_t
3009 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3010 * pages and then returns a contiguous mapping of the backing storage into
3011 * the kernel address space. Based on the @type of mapping, the PTE will be
3012 * set to either WriteBack or WriteCombine (via pgprot_t).
3014 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3015 * mapping is no longer required.
3017 * Returns the pointer through which to access the mapped object, or an
3018 * ERR_PTR() on error.
3020 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3021 enum i915_map_type type
);
3024 * i915_gem_object_unpin_map - releases an earlier mapping
3025 * @obj - the object to unmap
3027 * After pinning the object and mapping its pages, once you are finished
3028 * with your access, call i915_gem_object_unpin_map() to release the pin
3029 * upon the mapping. Once the pin count reaches zero, that mapping may be
3032 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3034 i915_gem_object_unpin_pages(obj
);
3037 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3038 unsigned int *needs_clflush
);
3039 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3040 unsigned int *needs_clflush
);
3041 #define CLFLUSH_BEFORE 0x1
3042 #define CLFLUSH_AFTER 0x2
3043 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3046 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3048 i915_gem_object_unpin_pages(obj
);
3051 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3052 void i915_vma_move_to_active(struct i915_vma
*vma
,
3053 struct drm_i915_gem_request
*req
,
3054 unsigned int flags
);
3055 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3056 struct drm_device
*dev
,
3057 struct drm_mode_create_dumb
*args
);
3058 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3059 uint32_t handle
, uint64_t *offset
);
3060 int i915_gem_mmap_gtt_version(void);
3062 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3063 struct drm_i915_gem_object
*new,
3064 unsigned frontbuffer_bits
);
3066 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3068 struct drm_i915_gem_request
*
3069 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3071 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3073 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3075 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3078 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3080 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3083 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3085 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3088 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3090 return READ_ONCE(error
->reset_count
);
3093 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3094 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3095 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3096 int __must_check
i915_gem_init(struct drm_device
*dev
);
3097 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3098 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3099 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3100 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3101 unsigned int flags
);
3102 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3103 void i915_gem_resume(struct drm_device
*dev
);
3104 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3105 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3108 struct intel_rps_client
*rps
);
3109 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3112 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3115 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3118 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3119 struct i915_vma
* __must_check
3120 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3122 const struct i915_ggtt_view
*view
);
3123 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3124 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3126 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3127 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3129 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3131 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3132 int tiling_mode
, bool fenced
);
3134 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3135 enum i915_cache_level cache_level
);
3137 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3138 struct dma_buf
*dma_buf
);
3140 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3141 struct drm_gem_object
*gem_obj
, int flags
);
3144 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3145 struct i915_address_space
*vm
,
3146 const struct i915_ggtt_view
*view
);
3149 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3150 struct i915_address_space
*vm
,
3151 const struct i915_ggtt_view
*view
);
3153 static inline struct i915_hw_ppgtt
*
3154 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3156 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3159 static inline struct i915_vma
*
3160 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3161 const struct i915_ggtt_view
*view
)
3163 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3166 static inline unsigned long
3167 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3168 const struct i915_ggtt_view
*view
)
3170 return i915_ggtt_offset(i915_gem_object_to_ggtt(o
, view
));
3173 /* i915_gem_fence_reg.c */
3174 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3175 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3177 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3179 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3180 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3181 struct sg_table
*pages
);
3182 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3183 struct sg_table
*pages
);
3185 /* i915_gem_context.c */
3186 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3187 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3188 void i915_gem_context_fini(struct drm_device
*dev
);
3189 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3190 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3191 int i915_switch_context(struct drm_i915_gem_request
*req
);
3192 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3194 i915_gem_context_pin_legacy(struct i915_gem_context
*ctx
,
3195 unsigned int flags
);
3196 void i915_gem_context_free(struct kref
*ctx_ref
);
3197 struct drm_i915_gem_object
*
3198 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3199 struct i915_gem_context
*
3200 i915_gem_context_create_gvt(struct drm_device
*dev
);
3202 static inline struct i915_gem_context
*
3203 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3205 struct i915_gem_context
*ctx
;
3207 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3209 ctx
= idr_find(&file_priv
->context_idr
, id
);
3211 return ERR_PTR(-ENOENT
);
3216 static inline struct i915_gem_context
*
3217 i915_gem_context_get(struct i915_gem_context
*ctx
)
3219 kref_get(&ctx
->ref
);
3223 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3225 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3226 kref_put(&ctx
->ref
, i915_gem_context_free
);
3229 static inline struct intel_timeline
*
3230 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3231 struct intel_engine_cs
*engine
)
3233 struct i915_address_space
*vm
;
3235 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3236 return &vm
->timeline
.engine
[engine
->id
];
3239 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3241 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3244 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3245 struct drm_file
*file
);
3246 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3247 struct drm_file
*file
);
3248 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3249 struct drm_file
*file_priv
);
3250 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3251 struct drm_file
*file_priv
);
3252 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3253 struct drm_file
*file
);
3255 /* i915_gem_evict.c */
3256 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3257 u64 min_size
, u64 alignment
,
3258 unsigned cache_level
,
3261 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3262 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3264 /* belongs in i915_gem_gtt.h */
3265 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3268 if (INTEL_GEN(dev_priv
) < 6)
3269 intel_gtt_chipset_flush();
3272 /* i915_gem_stolen.c */
3273 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3274 struct drm_mm_node
*node
, u64 size
,
3275 unsigned alignment
);
3276 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3277 struct drm_mm_node
*node
, u64 size
,
3278 unsigned alignment
, u64 start
,
3280 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3281 struct drm_mm_node
*node
);
3282 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3283 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3284 struct drm_i915_gem_object
*
3285 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3286 struct drm_i915_gem_object
*
3287 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3292 /* i915_gem_internal.c */
3293 struct drm_i915_gem_object
*
3294 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3297 /* i915_gem_shrinker.c */
3298 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3299 unsigned long target
,
3301 #define I915_SHRINK_PURGEABLE 0x1
3302 #define I915_SHRINK_UNBOUND 0x2
3303 #define I915_SHRINK_BOUND 0x4
3304 #define I915_SHRINK_ACTIVE 0x8
3305 #define I915_SHRINK_VMAPS 0x10
3306 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3307 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3308 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3311 /* i915_gem_tiling.c */
3312 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3314 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3316 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3317 i915_gem_object_is_tiled(obj
);
3320 /* i915_debugfs.c */
3321 #ifdef CONFIG_DEBUG_FS
3322 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3323 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3324 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3325 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3327 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3328 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3329 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3331 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3334 /* i915_gpu_error.c */
3335 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3338 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3339 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3340 const struct i915_error_state_file_priv
*error
);
3341 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3342 struct drm_i915_private
*i915
,
3343 size_t count
, loff_t pos
);
3344 static inline void i915_error_state_buf_release(
3345 struct drm_i915_error_state_buf
*eb
)
3349 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3351 const char *error_msg
);
3352 void i915_error_state_get(struct drm_device
*dev
,
3353 struct i915_error_state_file_priv
*error_priv
);
3354 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3355 void i915_destroy_error_state(struct drm_device
*dev
);
3359 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3361 const char *error_msg
)
3365 static inline void i915_destroy_error_state(struct drm_device
*dev
)
3371 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3373 /* i915_cmd_parser.c */
3374 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3375 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3376 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3377 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3378 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3379 struct drm_i915_gem_object
*batch_obj
,
3380 struct drm_i915_gem_object
*shadow_batch_obj
,
3381 u32 batch_start_offset
,
3385 /* i915_suspend.c */
3386 extern int i915_save_state(struct drm_device
*dev
);
3387 extern int i915_restore_state(struct drm_device
*dev
);
3390 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3391 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3394 extern int intel_setup_gmbus(struct drm_device
*dev
);
3395 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3396 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3399 extern struct i2c_adapter
*
3400 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3401 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3402 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3403 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3405 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3407 extern void intel_i2c_reset(struct drm_device
*dev
);
3410 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3411 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3412 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3413 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3414 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3415 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3416 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3417 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3418 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3420 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3424 /* intel_opregion.c */
3426 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3427 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3428 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3429 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3430 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3432 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3434 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3436 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3437 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3438 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3439 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3443 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3448 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3452 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3460 extern void intel_register_dsm_handler(void);
3461 extern void intel_unregister_dsm_handler(void);
3463 static inline void intel_register_dsm_handler(void) { return; }
3464 static inline void intel_unregister_dsm_handler(void) { return; }
3465 #endif /* CONFIG_ACPI */
3467 /* intel_device_info.c */
3468 static inline struct intel_device_info
*
3469 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3471 return (struct intel_device_info
*)&dev_priv
->info
;
3474 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3475 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3478 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3479 extern int intel_modeset_init(struct drm_device
*dev
);
3480 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3481 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3482 extern int intel_connector_register(struct drm_connector
*);
3483 extern void intel_connector_unregister(struct drm_connector
*);
3484 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3486 extern void intel_display_resume(struct drm_device
*dev
);
3487 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3488 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3489 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3490 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3491 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3492 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3495 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3496 struct drm_file
*file
);
3499 extern struct intel_overlay_error_state
*
3500 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3501 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3502 struct intel_overlay_error_state
*error
);
3504 extern struct intel_display_error_state
*
3505 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3506 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3507 struct drm_i915_private
*dev_priv
,
3508 struct intel_display_error_state
*error
);
3510 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3511 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3513 /* intel_sideband.c */
3514 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3515 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3516 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3517 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3518 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3519 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3520 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3521 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3522 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3523 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3524 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3525 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3526 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3527 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3528 enum intel_sbi_destination destination
);
3529 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3530 enum intel_sbi_destination destination
);
3531 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3532 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3534 /* intel_dpio_phy.c */
3535 void bxt_port_to_phy_channel(enum port port
,
3536 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3537 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3538 enum port port
, u32 margin
, u32 scale
,
3539 u32 enable
, u32 deemphasis
);
3540 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3541 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3542 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3544 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3546 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3547 uint8_t lane_count
);
3548 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3549 uint8_t lane_lat_optim_mask
);
3550 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3552 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3553 u32 deemph_reg_value
, u32 margin_reg_value
,
3554 bool uniq_trans_scale
);
3555 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3557 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3558 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3559 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3560 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3562 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3563 u32 demph_reg_value
, u32 preemph_reg_value
,
3564 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3565 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3566 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3567 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3569 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3570 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3572 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3573 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3575 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3576 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3577 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3578 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3580 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3581 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3582 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3583 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3585 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3586 * will be implemented using 2 32-bit writes in an arbitrary order with
3587 * an arbitrary delay between them. This can cause the hardware to
3588 * act upon the intermediate value, possibly leading to corruption and
3589 * machine death. For this reason we do not support I915_WRITE64, or
3590 * dev_priv->uncore.funcs.mmio_writeq.
3592 * When reading a 64-bit value as two 32-bit values, the delay may cause
3593 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3594 * occasionally a 64-bit register does not actualy support a full readq
3595 * and must be read using two 32-bit reads.
3597 * You have been warned.
3599 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3601 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3602 u32 upper, lower, old_upper, loop = 0; \
3603 upper = I915_READ(upper_reg); \
3605 old_upper = upper; \
3606 lower = I915_READ(lower_reg); \
3607 upper = I915_READ(upper_reg); \
3608 } while (upper != old_upper && loop++ < 2); \
3609 (u64)upper << 32 | lower; })
3611 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3612 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3614 #define __raw_read(x, s) \
3615 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3618 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3621 #define __raw_write(x, s) \
3622 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3623 i915_reg_t reg, uint##x##_t val) \
3625 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3640 /* These are untraced mmio-accessors that are only valid to be used inside
3641 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3644 * Think twice, and think again, before using these.
3646 * As an example, these accessors can possibly be used between:
3648 * spin_lock_irq(&dev_priv->uncore.lock);
3649 * intel_uncore_forcewake_get__locked();
3653 * intel_uncore_forcewake_put__locked();
3654 * spin_unlock_irq(&dev_priv->uncore.lock);
3657 * Note: some registers may not need forcewake held, so
3658 * intel_uncore_forcewake_{get,put} can be omitted, see
3659 * intel_uncore_forcewake_for_reg().
3661 * Certain architectures will die if the same cacheline is concurrently accessed
3662 * by different clients (e.g. on Ivybridge). Access to registers should
3663 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3664 * a more localised lock guarding all access to that bank of registers.
3666 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3667 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3668 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3669 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3671 /* "Broadcast RGB" property */
3672 #define INTEL_BROADCAST_RGB_AUTO 0
3673 #define INTEL_BROADCAST_RGB_FULL 1
3674 #define INTEL_BROADCAST_RGB_LIMITED 2
3676 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
3678 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3679 return VLV_VGACNTRL
;
3680 else if (INTEL_GEN(dev_priv
) >= 5)
3681 return CPU_VGACNTRL
;
3686 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3688 unsigned long j
= msecs_to_jiffies(m
);
3690 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3693 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3695 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3698 static inline unsigned long
3699 timespec_to_jiffies_timeout(const struct timespec
*value
)
3701 unsigned long j
= timespec_to_jiffies(value
);
3703 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3707 * If you need to wait X milliseconds between events A and B, but event B
3708 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3709 * when event A happened, then just before event B you call this function and
3710 * pass the timestamp as the first argument, and X as the second argument.
3713 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3715 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3718 * Don't re-read the value of "jiffies" every time since it may change
3719 * behind our back and break the math.
3721 tmp_jiffies
= jiffies
;
3722 target_jiffies
= timestamp_jiffies
+
3723 msecs_to_jiffies_timeout(to_wait_ms
);
3725 if (time_after(target_jiffies
, tmp_jiffies
)) {
3726 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3727 while (remaining_jiffies
)
3729 schedule_timeout_uninterruptible(remaining_jiffies
);
3734 __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3736 struct intel_engine_cs
*engine
= req
->engine
;
3738 /* Before we do the heavier coherent read of the seqno,
3739 * check the value (hopefully) in the CPU cacheline.
3741 if (__i915_gem_request_completed(req
))
3744 /* Ensure our read of the seqno is coherent so that we
3745 * do not "miss an interrupt" (i.e. if this is the last
3746 * request and the seqno write from the GPU is not visible
3747 * by the time the interrupt fires, we will see that the
3748 * request is incomplete and go back to sleep awaiting
3749 * another interrupt that will never come.)
3751 * Strictly, we only need to do this once after an interrupt,
3752 * but it is easier and safer to do it every time the waiter
3755 if (engine
->irq_seqno_barrier
&&
3756 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3757 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
3758 struct task_struct
*tsk
;
3760 /* The ordering of irq_posted versus applying the barrier
3761 * is crucial. The clearing of the current irq_posted must
3762 * be visible before we perform the barrier operation,
3763 * such that if a subsequent interrupt arrives, irq_posted
3764 * is reasserted and our task rewoken (which causes us to
3765 * do another __i915_request_irq_complete() immediately
3766 * and reapply the barrier). Conversely, if the clear
3767 * occurs after the barrier, then an interrupt that arrived
3768 * whilst we waited on the barrier would not trigger a
3769 * barrier on the next pass, and the read may not see the
3772 engine
->irq_seqno_barrier(engine
);
3774 /* If we consume the irq, but we are no longer the bottom-half,
3775 * the real bottom-half may not have serialised their own
3776 * seqno check with the irq-barrier (i.e. may have inspected
3777 * the seqno before we believe it coherent since they see
3778 * irq_posted == false but we are still running).
3781 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
3782 if (tsk
&& tsk
!= current
)
3783 /* Note that if the bottom-half is changed as we
3784 * are sending the wake-up, the new bottom-half will
3785 * be woken by whomever made the change. We only have
3786 * to worry about when we steal the irq-posted for
3789 wake_up_process(tsk
);
3792 if (__i915_gem_request_completed(req
))
3799 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
3800 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
3803 int remap_io_mapping(struct vm_area_struct
*vma
,
3804 unsigned long addr
, unsigned long pfn
, unsigned long size
,
3805 struct io_mapping
*iomap
);
3807 #define ptr_mask_bits(ptr) ({ \
3808 unsigned long __v = (unsigned long)(ptr); \
3809 (typeof(ptr))(__v & PAGE_MASK); \
3812 #define ptr_unpack_bits(ptr, bits) ({ \
3813 unsigned long __v = (unsigned long)(ptr); \
3814 (bits) = __v & ~PAGE_MASK; \
3815 (typeof(ptr))(__v & PAGE_MASK); \
3818 #define ptr_pack_bits(ptr, bits) \
3819 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3821 #define fetch_and_zero(ptr) ({ \
3822 typeof(*ptr) __T = *(ptr); \
3823 *(ptr) = (typeof(*ptr))0; \