1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170907"
84 #define DRIVER_TIMESTAMP 1504772900
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915_modparams.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func
, int line
);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t
;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val
)
125 static inline uint_fixed_16_16_t
u32_to_fixed16(uint32_t val
)
127 uint_fixed_16_16_t fp
;
129 WARN_ON(val
> U16_MAX
);
135 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp
)
137 return DIV_ROUND_UP(fp
.val
, 1 << 16);
140 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp
)
145 static inline uint_fixed_16_16_t
min_fixed16(uint_fixed_16_16_t min1
,
146 uint_fixed_16_16_t min2
)
148 uint_fixed_16_16_t min
;
150 min
.val
= min(min1
.val
, min2
.val
);
154 static inline uint_fixed_16_16_t
max_fixed16(uint_fixed_16_16_t max1
,
155 uint_fixed_16_16_t max2
)
157 uint_fixed_16_16_t max
;
159 max
.val
= max(max1
.val
, max2
.val
);
163 static inline uint_fixed_16_16_t
clamp_u64_to_fixed16(uint64_t val
)
165 uint_fixed_16_16_t fp
;
166 WARN_ON(val
> U32_MAX
);
167 fp
.val
= (uint32_t) val
;
171 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val
,
172 uint_fixed_16_16_t d
)
174 return DIV_ROUND_UP(val
.val
, d
.val
);
177 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val
,
178 uint_fixed_16_16_t mul
)
180 uint64_t intermediate_val
;
182 intermediate_val
= (uint64_t) val
* mul
.val
;
183 intermediate_val
= DIV_ROUND_UP_ULL(intermediate_val
, 1 << 16);
184 WARN_ON(intermediate_val
> U32_MAX
);
185 return (uint32_t) intermediate_val
;
188 static inline uint_fixed_16_16_t
mul_fixed16(uint_fixed_16_16_t val
,
189 uint_fixed_16_16_t mul
)
191 uint64_t intermediate_val
;
193 intermediate_val
= (uint64_t) val
.val
* mul
.val
;
194 intermediate_val
= intermediate_val
>> 16;
195 return clamp_u64_to_fixed16(intermediate_val
);
198 static inline uint_fixed_16_16_t
div_fixed16(uint32_t val
, uint32_t d
)
202 interm_val
= (uint64_t)val
<< 16;
203 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
204 return clamp_u64_to_fixed16(interm_val
);
207 static inline uint32_t div_round_up_u32_fixed16(uint32_t val
,
208 uint_fixed_16_16_t d
)
212 interm_val
= (uint64_t)val
<< 16;
213 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
.val
);
214 WARN_ON(interm_val
> U32_MAX
);
215 return (uint32_t) interm_val
;
218 static inline uint_fixed_16_16_t
mul_u32_fixed16(uint32_t val
,
219 uint_fixed_16_16_t mul
)
221 uint64_t intermediate_val
;
223 intermediate_val
= (uint64_t) val
* mul
.val
;
224 return clamp_u64_to_fixed16(intermediate_val
);
227 static inline uint_fixed_16_16_t
add_fixed16(uint_fixed_16_16_t add1
,
228 uint_fixed_16_16_t add2
)
232 interm_sum
= (uint64_t) add1
.val
+ add2
.val
;
233 return clamp_u64_to_fixed16(interm_sum
);
236 static inline uint_fixed_16_16_t
add_fixed16_u32(uint_fixed_16_16_t add1
,
240 uint_fixed_16_16_t interm_add2
= u32_to_fixed16(add2
);
242 interm_sum
= (uint64_t) add1
.val
+ interm_add2
.val
;
243 return clamp_u64_to_fixed16(interm_sum
);
246 static inline const char *yesno(bool v
)
248 return v
? "yes" : "no";
251 static inline const char *onoff(bool v
)
253 return v
? "on" : "off";
256 static inline const char *enableddisabled(bool v
)
258 return v
? "enabled" : "disabled";
267 I915_MAX_PIPES
= _PIPE_EDP
269 #define pipe_name(p) ((p) + 'A')
281 static inline const char *transcoder_name(enum transcoder transcoder
)
283 switch (transcoder
) {
292 case TRANSCODER_DSI_A
:
294 case TRANSCODER_DSI_C
:
301 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
303 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
307 * Global legacy plane identifier. Valid only for primary/sprite
308 * planes on pre-g4x, and only for primary planes on g4x+.
315 #define plane_name(p) ((p) + 'A')
317 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
320 * Per-pipe plane identifier.
321 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
322 * number of planes per CRTC. Not all platforms really have this many planes,
323 * which means some arrays of size I915_MAX_PLANES may have unused entries
324 * between the topmost sprite plane and the cursor plane.
326 * This is expected to be passed to various register macros
327 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
338 #define for_each_plane_id_on_crtc(__crtc, __p) \
339 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
340 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
351 #define port_name(p) ((p) + 'A')
353 #define I915_NUM_PHYS_VLV 2
366 enum intel_display_power_domain
{
370 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
371 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
372 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
373 POWER_DOMAIN_TRANSCODER_A
,
374 POWER_DOMAIN_TRANSCODER_B
,
375 POWER_DOMAIN_TRANSCODER_C
,
376 POWER_DOMAIN_TRANSCODER_EDP
,
377 POWER_DOMAIN_TRANSCODER_DSI_A
,
378 POWER_DOMAIN_TRANSCODER_DSI_C
,
379 POWER_DOMAIN_PORT_DDI_A_LANES
,
380 POWER_DOMAIN_PORT_DDI_B_LANES
,
381 POWER_DOMAIN_PORT_DDI_C_LANES
,
382 POWER_DOMAIN_PORT_DDI_D_LANES
,
383 POWER_DOMAIN_PORT_DDI_E_LANES
,
384 POWER_DOMAIN_PORT_DDI_A_IO
,
385 POWER_DOMAIN_PORT_DDI_B_IO
,
386 POWER_DOMAIN_PORT_DDI_C_IO
,
387 POWER_DOMAIN_PORT_DDI_D_IO
,
388 POWER_DOMAIN_PORT_DDI_E_IO
,
389 POWER_DOMAIN_PORT_DSI
,
390 POWER_DOMAIN_PORT_CRT
,
391 POWER_DOMAIN_PORT_OTHER
,
400 POWER_DOMAIN_MODESET
,
406 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
407 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
408 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
409 #define POWER_DOMAIN_TRANSCODER(tran) \
410 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
411 (tran) + POWER_DOMAIN_TRANSCODER_A)
415 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
427 #define for_each_hpd_pin(__pin) \
428 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
430 #define HPD_STORM_DEFAULT_THRESHOLD 5
432 struct i915_hotplug
{
433 struct work_struct hotplug_work
;
436 unsigned long last_jiffies
;
441 HPD_MARK_DISABLED
= 2
443 } stats
[HPD_NUM_PINS
];
445 struct delayed_work reenable_work
;
447 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
450 struct work_struct dig_port_work
;
452 struct work_struct poll_init_work
;
455 unsigned int hpd_storm_threshold
;
458 * if we get a HPD irq from DP and a HPD irq from non-DP
459 * the non-DP HPD could block the workqueue on a mode config
460 * mutex getting, that userspace may have taken. However
461 * userspace is waiting on the DP workqueue to run which is
462 * blocked behind the non-DP one.
464 struct workqueue_struct
*dp_wq
;
467 #define I915_GEM_GPU_DOMAINS \
468 (I915_GEM_DOMAIN_RENDER | \
469 I915_GEM_DOMAIN_SAMPLER | \
470 I915_GEM_DOMAIN_COMMAND | \
471 I915_GEM_DOMAIN_INSTRUCTION | \
472 I915_GEM_DOMAIN_VERTEX)
474 #define for_each_pipe(__dev_priv, __p) \
475 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
476 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
477 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
478 for_each_if ((__mask) & (1 << (__p)))
479 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
481 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
483 #define for_each_sprite(__dev_priv, __p, __s) \
485 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
488 #define for_each_port_masked(__port, __ports_mask) \
489 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
490 for_each_if ((__ports_mask) & (1 << (__port)))
492 #define for_each_crtc(dev, crtc) \
493 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
495 #define for_each_intel_plane(dev, intel_plane) \
496 list_for_each_entry(intel_plane, \
497 &(dev)->mode_config.plane_list, \
500 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
501 list_for_each_entry(intel_plane, \
502 &(dev)->mode_config.plane_list, \
504 for_each_if ((plane_mask) & \
505 (1 << drm_plane_index(&intel_plane->base)))
507 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
508 list_for_each_entry(intel_plane, \
509 &(dev)->mode_config.plane_list, \
511 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
513 #define for_each_intel_crtc(dev, intel_crtc) \
514 list_for_each_entry(intel_crtc, \
515 &(dev)->mode_config.crtc_list, \
518 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
519 list_for_each_entry(intel_crtc, \
520 &(dev)->mode_config.crtc_list, \
522 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
524 #define for_each_intel_encoder(dev, intel_encoder) \
525 list_for_each_entry(intel_encoder, \
526 &(dev)->mode_config.encoder_list, \
529 #define for_each_intel_connector_iter(intel_connector, iter) \
530 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
532 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
533 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
534 for_each_if ((intel_encoder)->base.crtc == (__crtc))
536 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
537 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
538 for_each_if ((intel_connector)->base.encoder == (__encoder))
540 #define for_each_power_domain(domain, mask) \
541 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
542 for_each_if (BIT_ULL(domain) & (mask))
544 #define for_each_power_well(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
546 (__power_well) - (__dev_priv)->power_domains.power_wells < \
547 (__dev_priv)->power_domains.power_well_count; \
550 #define for_each_power_well_rev(__dev_priv, __power_well) \
551 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
552 (__dev_priv)->power_domains.power_well_count - 1; \
553 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
556 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
557 for_each_power_well(__dev_priv, __power_well) \
558 for_each_if ((__power_well)->domains & (__domain_mask))
560 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
561 for_each_power_well_rev(__dev_priv, __power_well) \
562 for_each_if ((__power_well)->domains & (__domain_mask))
564 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
566 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
567 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
568 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
570 for_each_if (plane_state)
572 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
574 (__i) < (__state)->base.dev->mode_config.num_crtc && \
575 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
576 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
581 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
583 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
584 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
585 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
586 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
590 struct drm_i915_private
;
591 struct i915_mm_struct
;
592 struct i915_mmu_object
;
594 struct drm_i915_file_private
{
595 struct drm_i915_private
*dev_priv
;
596 struct drm_file
*file
;
600 struct list_head request_list
;
601 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
602 * chosen to prevent the CPU getting more than a frame ahead of the GPU
603 * (when using lax throttling for the frontbuffer). We also use it to
604 * offer free GPU waitboosts for severely congested workloads.
606 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
608 struct idr context_idr
;
610 struct intel_rps_client
{
614 unsigned int bsd_engine
;
616 /* Client can have a maximum of 3 contexts banned before
617 * it is denied of creating new contexts. As one context
618 * ban needs 4 consecutive hangs, and more if there is
619 * progress in between, this is a last resort stop gap measure
620 * to limit the badly behaving clients access to gpu.
622 #define I915_MAX_CLIENT_CONTEXT_BANS 3
623 atomic_t context_bans
;
626 /* Used by dp and fdi links */
627 struct intel_link_m_n
{
635 void intel_link_compute_m_n(int bpp
, int nlanes
,
636 int pixel_clock
, int link_clock
,
637 struct intel_link_m_n
*m_n
,
640 /* Interface history:
643 * 1.2: Add Power Management
644 * 1.3: Add vblank support
645 * 1.4: Fix cmdbuffer path, add heap destroy
646 * 1.5: Add vblank pipe configuration
647 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
648 * - Support vertical blank on secondary display pipe
650 #define DRIVER_MAJOR 1
651 #define DRIVER_MINOR 6
652 #define DRIVER_PATCHLEVEL 0
654 struct opregion_header
;
655 struct opregion_acpi
;
656 struct opregion_swsci
;
657 struct opregion_asle
;
659 struct intel_opregion
{
660 struct opregion_header
*header
;
661 struct opregion_acpi
*acpi
;
662 struct opregion_swsci
*swsci
;
663 u32 swsci_gbda_sub_functions
;
664 u32 swsci_sbcb_sub_functions
;
665 struct opregion_asle
*asle
;
671 struct work_struct asle_work
;
673 #define OPREGION_SIZE (8*1024)
675 struct intel_overlay
;
676 struct intel_overlay_error_state
;
678 struct sdvo_device_mapping
{
687 struct intel_connector
;
688 struct intel_encoder
;
689 struct intel_atomic_state
;
690 struct intel_crtc_state
;
691 struct intel_initial_plane_config
;
695 struct intel_cdclk_state
;
697 struct drm_i915_display_funcs
{
698 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
699 struct intel_cdclk_state
*cdclk_state
);
700 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
701 const struct intel_cdclk_state
*cdclk_state
);
702 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
703 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
704 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
705 struct intel_crtc
*intel_crtc
,
706 struct intel_crtc_state
*newstate
);
707 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
708 struct intel_crtc_state
*cstate
);
709 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
710 struct intel_crtc_state
*cstate
);
711 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
712 struct intel_crtc_state
*cstate
);
713 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
714 void (*update_wm
)(struct intel_crtc
*crtc
);
715 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
716 /* Returns the active state of the crtc, and if the crtc is active,
717 * fills out the pipe-config with the hw state. */
718 bool (*get_pipe_config
)(struct intel_crtc
*,
719 struct intel_crtc_state
*);
720 void (*get_initial_plane_config
)(struct intel_crtc
*,
721 struct intel_initial_plane_config
*);
722 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
723 struct intel_crtc_state
*crtc_state
);
724 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
725 struct drm_atomic_state
*old_state
);
726 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
727 struct drm_atomic_state
*old_state
);
728 void (*update_crtcs
)(struct drm_atomic_state
*state
,
729 unsigned int *crtc_vblank_mask
);
730 void (*audio_codec_enable
)(struct drm_connector
*connector
,
731 struct intel_encoder
*encoder
,
732 const struct drm_display_mode
*adjusted_mode
);
733 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
734 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
735 const struct intel_crtc_state
*crtc_state
);
736 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
737 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
738 /* clock updates for mode set */
740 /* render clock increase/decrease */
741 /* display clock increase/decrease */
742 /* pll clock increase/decrease */
744 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
745 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
748 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
749 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
750 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
753 struct work_struct work
;
755 uint32_t *dmc_payload
;
756 uint32_t dmc_fw_size
;
759 i915_reg_t mmioaddr
[8];
760 uint32_t mmiodata
[8];
762 uint32_t allowed_dc_mask
;
765 #define DEV_INFO_FOR_EACH_FLAG(func) \
768 func(is_alpha_support); \
769 /* Keep has_* in alphabetical order */ \
770 func(has_64bit_reloc); \
771 func(has_aliasing_ppgtt); \
775 func(has_reset_engine); \
777 func(has_fpga_dbg); \
778 func(has_full_ppgtt); \
779 func(has_full_48bit_ppgtt); \
780 func(has_gmch_display); \
786 func(has_logical_ring_contexts); \
788 func(has_pipe_cxsr); \
789 func(has_pooled_eu); \
793 func(has_resource_streamer); \
794 func(has_runtime_pm); \
796 func(unfenced_needs_alignment); \
797 func(cursor_needs_physical); \
798 func(hws_needs_physical); \
799 func(overlay_needs_physical); \
803 struct sseu_dev_info
{
809 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
812 u8 has_subslice_pg
:1;
816 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
818 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
821 /* Keep in gen based order, and chronological order within a gen */
822 enum intel_platform
{
823 INTEL_PLATFORM_UNINITIALIZED
= 0,
854 struct intel_device_info
{
859 u8 gt
; /* GT number, 0 if undefined */
861 u8 ring_mask
; /* Rings supported by the HW */
863 enum intel_platform platform
;
866 u32 display_mmio_offset
;
869 u8 num_sprites
[I915_MAX_PIPES
];
870 u8 num_scalers
[I915_MAX_PIPES
];
872 #define DEFINE_FLAG(name) u8 name:1
873 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
875 u16 ddb_size
; /* in blocks */
877 /* Register offsets for the various display pipes and transcoders */
878 int pipe_offsets
[I915_MAX_TRANSCODERS
];
879 int trans_offsets
[I915_MAX_TRANSCODERS
];
880 int palette_offsets
[I915_MAX_PIPES
];
881 int cursor_offsets
[I915_MAX_PIPES
];
883 /* Slice/subslice/EU info */
884 struct sseu_dev_info sseu
;
887 u16 degamma_lut_size
;
892 struct intel_display_error_state
;
894 struct i915_gpu_state
{
897 struct timeval boottime
;
898 struct timeval uptime
;
900 struct drm_i915_private
*i915
;
910 struct intel_device_info device_info
;
911 struct i915_params params
;
913 /* Generic register state */
917 u32 gtier
[4], ngtier
;
921 u32 error
; /* gen6+ */
922 u32 err_int
; /* gen7 */
923 u32 fault_data0
; /* gen8, gen9 */
924 u32 fault_data1
; /* gen8, gen9 */
932 u64 fence
[I915_MAX_NUM_FENCES
];
933 struct intel_overlay_error_state
*overlay
;
934 struct intel_display_error_state
*display
;
935 struct drm_i915_error_object
*semaphore
;
936 struct drm_i915_error_object
*guc_log
;
938 struct drm_i915_error_engine
{
940 /* Software tracked state */
943 unsigned long hangcheck_timestamp
;
944 bool hangcheck_stalled
;
945 enum intel_engine_hangcheck_action hangcheck_action
;
946 struct i915_address_space
*vm
;
950 /* position of active request inside the ring */
951 u32 rq_head
, rq_post
, rq_tail
;
953 /* our own tracking of ring head and tail */
976 u32 rc_psmi
; /* sleep state */
977 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
978 struct intel_instdone instdone
;
980 struct drm_i915_error_context
{
981 char comm
[TASK_COMM_LEN
];
990 struct drm_i915_error_object
{
996 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
998 struct drm_i915_error_object
**user_bo
;
1001 struct drm_i915_error_object
*wa_ctx
;
1003 struct drm_i915_error_request
{
1011 } *requests
, execlist
[EXECLIST_MAX_PORTS
];
1012 unsigned int num_ports
;
1014 struct drm_i915_error_waiter
{
1015 char comm
[TASK_COMM_LEN
];
1027 } engine
[I915_NUM_ENGINES
];
1029 struct drm_i915_error_buffer
{
1032 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1036 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1043 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1044 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1045 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1048 enum i915_cache_level
{
1049 I915_CACHE_NONE
= 0,
1050 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1051 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1052 caches, eg sampler/render caches, and the
1053 large Last-Level-Cache. LLC is coherent with
1054 the CPU, but L3 is only visible to the GPU. */
1055 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1058 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1069 /* This is always the inner lock when overlapping with struct_mutex and
1070 * it's the outer lock when overlapping with stolen_lock. */
1073 unsigned int possible_framebuffer_bits
;
1074 unsigned int busy_bits
;
1075 unsigned int visible_pipes_mask
;
1076 struct intel_crtc
*crtc
;
1078 struct drm_mm_node compressed_fb
;
1079 struct drm_mm_node
*compressed_llb
;
1086 bool underrun_detected
;
1087 struct work_struct underrun_work
;
1090 * Due to the atomic rules we can't access some structures without the
1091 * appropriate locking, so we cache information here in order to avoid
1094 struct intel_fbc_state_cache
{
1095 struct i915_vma
*vma
;
1098 unsigned int mode_flags
;
1099 uint32_t hsw_bdw_pixel_rate
;
1103 unsigned int rotation
;
1110 const struct drm_format_info
*format
;
1111 unsigned int stride
;
1116 * This structure contains everything that's relevant to program the
1117 * hardware registers. When we want to figure out if we need to disable
1118 * and re-enable FBC for a new configuration we just check if there's
1119 * something different in the struct. The genx_fbc_activate functions
1120 * are supposed to read from it in order to program the registers.
1122 struct intel_fbc_reg_params
{
1123 struct i915_vma
*vma
;
1128 unsigned int fence_y_offset
;
1132 const struct drm_format_info
*format
;
1133 unsigned int stride
;
1137 unsigned int gen9_wa_cfb_stride
;
1140 struct intel_fbc_work
{
1142 u32 scheduled_vblank
;
1143 struct work_struct work
;
1146 const char *no_fbc_reason
;
1150 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1151 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1152 * parsing for same resolution.
1154 enum drrs_refresh_rate_type
{
1157 DRRS_MAX_RR
, /* RR count */
1160 enum drrs_support_type
{
1161 DRRS_NOT_SUPPORTED
= 0,
1162 STATIC_DRRS_SUPPORT
= 1,
1163 SEAMLESS_DRRS_SUPPORT
= 2
1169 struct delayed_work work
;
1170 struct intel_dp
*dp
;
1171 unsigned busy_frontbuffer_bits
;
1172 enum drrs_refresh_rate_type refresh_rate_type
;
1173 enum drrs_support_type type
;
1180 struct intel_dp
*enabled
;
1182 struct delayed_work work
;
1183 unsigned busy_frontbuffer_bits
;
1185 bool aux_frame_sync
;
1187 bool y_cord_support
;
1188 bool colorimetry_support
;
1191 void (*enable_source
)(struct intel_dp
*,
1192 const struct intel_crtc_state
*);
1193 void (*disable_source
)(struct intel_dp
*,
1194 const struct intel_crtc_state
*);
1195 void (*enable_sink
)(struct intel_dp
*);
1196 void (*activate
)(struct intel_dp
*);
1197 void (*setup_vsc
)(struct intel_dp
*, const struct intel_crtc_state
*);
1201 PCH_NONE
= 0, /* No PCH present */
1202 PCH_IBX
, /* Ibexpeak PCH */
1203 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
1204 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
1205 PCH_SPT
, /* Sunrisepoint PCH */
1206 PCH_KBP
, /* Kaby Lake PCH */
1207 PCH_CNP
, /* Cannon Lake PCH */
1211 enum intel_sbi_destination
{
1216 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1217 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1218 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1219 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1220 #define QUIRK_INCREASE_T12_DELAY (1<<6)
1223 struct intel_fbc_work
;
1225 struct intel_gmbus
{
1226 struct i2c_adapter adapter
;
1227 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1230 i915_reg_t gpio_reg
;
1231 struct i2c_algo_bit_data bit_algo
;
1232 struct drm_i915_private
*dev_priv
;
1235 struct i915_suspend_saved_registers
{
1237 u32 saveFBC_CONTROL
;
1238 u32 saveCACHE_MODE_0
;
1239 u32 saveMI_ARB_STATE
;
1243 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1244 u32 savePCH_PORT_HOTPLUG
;
1248 struct vlv_s0ix_state
{
1255 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1256 u32 media_max_req_count
;
1257 u32 gfx_max_req_count
;
1283 u32 rp_down_timeout
;
1289 /* Display 1 CZ domain */
1294 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1296 /* GT SA CZ domain */
1303 /* Display 2 CZ domain */
1307 u32 clock_gate_dis2
;
1310 struct intel_rps_ei
{
1316 struct intel_gen6_power_mgmt
{
1318 * work, interrupts_enabled and pm_iir are protected by
1319 * dev_priv->irq_lock
1321 struct work_struct work
;
1322 bool interrupts_enabled
;
1325 /* PM interrupt bits that should never be masked */
1328 /* Frequencies are stored in potentially platform dependent multiples.
1329 * In other words, *_freq needs to be multiplied by X to be interesting.
1330 * Soft limits are those which are used for the dynamic reclocking done
1331 * by the driver (raise frequencies under heavy loads, and lower for
1332 * lighter loads). Hard limits are those imposed by the hardware.
1334 * A distinction is made for overclocking, which is never enabled by
1335 * default, and is considered to be above the hard limit if it's
1338 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1339 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1340 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1341 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1342 u8 min_freq
; /* AKA RPn. Minimum frequency */
1343 u8 boost_freq
; /* Frequency to request when wait boosting */
1344 u8 idle_freq
; /* Frequency to request when we are idle */
1345 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1346 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1347 u8 rp0_freq
; /* Non-overclocked max frequency. */
1348 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1350 u8 up_threshold
; /* Current %busy required to uplock */
1351 u8 down_threshold
; /* Current %busy required to downclock */
1354 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1357 struct delayed_work autoenable_work
;
1358 atomic_t num_waiters
;
1361 /* manual wa residency calculations */
1362 struct intel_rps_ei ei
;
1365 * Protects RPS/RC6 register access and PCU communication.
1366 * Must be taken after struct_mutex if nested. Note that
1367 * this lock may be held for long periods of time when
1368 * talking to hw - so only take it when talking to hw!
1370 struct mutex hw_lock
;
1373 /* defined intel_pm.c */
1374 extern spinlock_t mchdev_lock
;
1376 struct intel_ilk_power_mgmt
{
1384 unsigned long last_time1
;
1385 unsigned long chipset_power
;
1388 unsigned long gfx_power
;
1395 struct drm_i915_private
;
1396 struct i915_power_well
;
1398 struct i915_power_well_ops
{
1400 * Synchronize the well's hw state to match the current sw state, for
1401 * example enable/disable it based on the current refcount. Called
1402 * during driver init and resume time, possibly after first calling
1403 * the enable/disable handlers.
1405 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1406 struct i915_power_well
*power_well
);
1408 * Enable the well and resources that depend on it (for example
1409 * interrupts located on the well). Called after the 0->1 refcount
1412 void (*enable
)(struct drm_i915_private
*dev_priv
,
1413 struct i915_power_well
*power_well
);
1415 * Disable the well and resources that depend on it. Called after
1416 * the 1->0 refcount transition.
1418 void (*disable
)(struct drm_i915_private
*dev_priv
,
1419 struct i915_power_well
*power_well
);
1420 /* Returns the hw enabled state. */
1421 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1422 struct i915_power_well
*power_well
);
1425 /* Power well structure for haswell */
1426 struct i915_power_well
{
1429 /* power well enable/disable usage count */
1431 /* cached hw enabled state */
1434 /* unique identifier for this power well */
1435 enum i915_power_well_id id
;
1437 * Arbitraty data associated with this power well. Platform and power
1445 /* Mask of pipes whose IRQ logic is backed by the pw */
1447 /* The pw is backing the VGA functionality */
1452 const struct i915_power_well_ops
*ops
;
1455 struct i915_power_domains
{
1457 * Power wells needed for initialization at driver init and suspend
1458 * time are on. They are kept on until after the first modeset.
1462 int power_well_count
;
1465 int domain_use_count
[POWER_DOMAIN_NUM
];
1466 struct i915_power_well
*power_wells
;
1469 #define MAX_L3_SLICES 2
1470 struct intel_l3_parity
{
1471 u32
*remap_info
[MAX_L3_SLICES
];
1472 struct work_struct error_work
;
1476 struct i915_gem_mm
{
1477 /** Memory allocator for GTT stolen memory */
1478 struct drm_mm stolen
;
1479 /** Protects the usage of the GTT stolen memory allocator. This is
1480 * always the inner lock when overlapping with struct_mutex. */
1481 struct mutex stolen_lock
;
1483 /** List of all objects in gtt_space. Used to restore gtt
1484 * mappings on resume */
1485 struct list_head bound_list
;
1487 * List of objects which are not bound to the GTT (thus
1488 * are idle and not used by the GPU). These objects may or may
1489 * not actually have any pages attached.
1491 struct list_head unbound_list
;
1493 /** List of all objects in gtt_space, currently mmaped by userspace.
1494 * All objects within this list must also be on bound_list.
1496 struct list_head userfault_list
;
1499 * List of objects which are pending destruction.
1501 struct llist_head free_list
;
1502 struct work_struct free_work
;
1505 * Small stash of WC pages
1507 struct pagevec wc_stash
;
1509 /** Usable portion of the GTT for GEM */
1510 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1512 /** PPGTT used for aliasing the PPGTT with the GTT */
1513 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1515 struct notifier_block oom_notifier
;
1516 struct notifier_block vmap_notifier
;
1517 struct shrinker shrinker
;
1519 /** LRU list of objects with fence regs on them. */
1520 struct list_head fence_list
;
1523 * Workqueue to fault in userptr pages, flushed by the execbuf
1524 * when required but otherwise left to userspace to try again
1527 struct workqueue_struct
*userptr_wq
;
1529 u64 unordered_timeline
;
1531 /* the indicator for dispatch video commands on two BSD rings */
1532 atomic_t bsd_engine_dispatch_index
;
1534 /** Bit 6 swizzling required for X tiling */
1535 uint32_t bit_6_swizzle_x
;
1536 /** Bit 6 swizzling required for Y tiling */
1537 uint32_t bit_6_swizzle_y
;
1539 /* accounting, useful for userland debugging */
1540 spinlock_t object_stat_lock
;
1545 struct drm_i915_error_state_buf
{
1546 struct drm_i915_private
*i915
;
1555 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1556 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1558 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1559 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1561 struct i915_gpu_error
{
1562 /* For hangcheck timer */
1563 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1564 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1566 struct delayed_work hangcheck_work
;
1568 /* For reset and error_state handling. */
1570 /* Protected by the above dev->gpu_error.lock. */
1571 struct i915_gpu_state
*first_error
;
1573 atomic_t pending_fb_pin
;
1575 unsigned long missed_irq_rings
;
1578 * State variable controlling the reset flow and count
1580 * This is a counter which gets incremented when reset is triggered,
1582 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1583 * meaning that any waiters holding onto the struct_mutex should
1584 * relinquish the lock immediately in order for the reset to start.
1586 * If reset is not completed succesfully, the I915_WEDGE bit is
1587 * set meaning that hardware is terminally sour and there is no
1588 * recovery. All waiters on the reset_queue will be woken when
1591 * This counter is used by the wait_seqno code to notice that reset
1592 * event happened and it needs to restart the entire ioctl (since most
1593 * likely the seqno it waited for won't ever signal anytime soon).
1595 * This is important for lock-free wait paths, where no contended lock
1596 * naturally enforces the correct ordering between the bail-out of the
1597 * waiter and the gpu reset work code.
1599 unsigned long reset_count
;
1602 * flags: Control various stages of the GPU reset
1604 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1605 * other users acquiring the struct_mutex. To do this we set the
1606 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1607 * and then check for that bit before acquiring the struct_mutex (in
1608 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1609 * secondary role in preventing two concurrent global reset attempts.
1611 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1612 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1613 * but it may be held by some long running waiter (that we cannot
1614 * interrupt without causing trouble). Once we are ready to do the GPU
1615 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1616 * they already hold the struct_mutex and want to participate they can
1617 * inspect the bit and do the reset directly, otherwise the worker
1618 * waits for the struct_mutex.
1620 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1621 * acquire the struct_mutex to reset an engine, we need an explicit
1622 * flag to prevent two concurrent reset attempts in the same engine.
1623 * As the number of engines continues to grow, allocate the flags from
1624 * the most significant bits.
1626 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1627 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1628 * i915_gem_request_alloc(), this bit is checked and the sequence
1629 * aborted (with -EIO reported to userspace) if set.
1631 unsigned long flags
;
1632 #define I915_RESET_BACKOFF 0
1633 #define I915_RESET_HANDOFF 1
1634 #define I915_RESET_MODESET 2
1635 #define I915_WEDGED (BITS_PER_LONG - 1)
1636 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1638 /** Number of times an engine has been reset */
1639 u32 reset_engine_count
[I915_NUM_ENGINES
];
1642 * Waitqueue to signal when a hang is detected. Used to for waiters
1643 * to release the struct_mutex for the reset to procede.
1645 wait_queue_head_t wait_queue
;
1648 * Waitqueue to signal when the reset has completed. Used by clients
1649 * that wait for dev_priv->mm.wedged to settle.
1651 wait_queue_head_t reset_queue
;
1653 /* For missed irq/seqno simulation. */
1654 unsigned long test_irq_rings
;
1657 enum modeset_restore
{
1658 MODESET_ON_LID_OPEN
,
1663 #define DP_AUX_A 0x40
1664 #define DP_AUX_B 0x10
1665 #define DP_AUX_C 0x20
1666 #define DP_AUX_D 0x30
1668 #define DDC_PIN_B 0x05
1669 #define DDC_PIN_C 0x04
1670 #define DDC_PIN_D 0x06
1672 struct ddi_vbt_port_info
{
1674 * This is an index in the HDMI/DVI DDI buffer translation table.
1675 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1676 * populate this field.
1678 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1679 uint8_t hdmi_level_shift
;
1681 uint8_t supports_dvi
:1;
1682 uint8_t supports_hdmi
:1;
1683 uint8_t supports_dp
:1;
1684 uint8_t supports_edp
:1;
1686 uint8_t alternate_aux_channel
;
1687 uint8_t alternate_ddc_pin
;
1689 uint8_t dp_boost_level
;
1690 uint8_t hdmi_boost_level
;
1693 enum psr_lines_to_wait
{
1694 PSR_0_LINES_TO_WAIT
= 0,
1696 PSR_4_LINES_TO_WAIT
,
1700 struct intel_vbt_data
{
1701 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1702 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1705 unsigned int int_tv_support
:1;
1706 unsigned int lvds_dither
:1;
1707 unsigned int lvds_vbt
:1;
1708 unsigned int int_crt_support
:1;
1709 unsigned int lvds_use_ssc
:1;
1710 unsigned int display_clock_mode
:1;
1711 unsigned int fdi_rx_polarity_inverted
:1;
1712 unsigned int panel_type
:4;
1714 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1716 enum drrs_support_type drrs_type
;
1727 struct edp_power_seq pps
;
1732 bool require_aux_wakeup
;
1734 enum psr_lines_to_wait lines_to_wait
;
1735 int tp1_wakeup_time
;
1736 int tp2_tp3_wakeup_time
;
1742 bool active_low_pwm
;
1743 u8 min_brightness
; /* min_brightness/255 of max */
1744 u8 controller
; /* brightness controller number */
1745 enum intel_backlight_type type
;
1751 struct mipi_config
*config
;
1752 struct mipi_pps_data
*pps
;
1756 const u8
*sequence
[MIPI_SEQ_MAX
];
1762 struct child_device_config
*child_dev
;
1764 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1765 struct sdvo_device_mapping sdvo_mappings
[2];
1768 enum intel_ddb_partitioning
{
1770 INTEL_DDB_PART_5_6
, /* IVB+ */
1773 struct intel_wm_level
{
1781 struct ilk_wm_values
{
1782 uint32_t wm_pipe
[3];
1784 uint32_t wm_lp_spr
[3];
1785 uint32_t wm_linetime
[3];
1787 enum intel_ddb_partitioning partitioning
;
1790 struct g4x_pipe_wm
{
1791 uint16_t plane
[I915_MAX_PLANES
];
1801 struct vlv_wm_ddl_values
{
1802 uint8_t plane
[I915_MAX_PLANES
];
1805 struct vlv_wm_values
{
1806 struct g4x_pipe_wm pipe
[3];
1807 struct g4x_sr_wm sr
;
1808 struct vlv_wm_ddl_values ddl
[3];
1813 struct g4x_wm_values
{
1814 struct g4x_pipe_wm pipe
[2];
1815 struct g4x_sr_wm sr
;
1816 struct g4x_sr_wm hpll
;
1822 struct skl_ddb_entry
{
1823 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1826 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1828 return entry
->end
- entry
->start
;
1831 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1832 const struct skl_ddb_entry
*e2
)
1834 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1840 struct skl_ddb_allocation
{
1841 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1842 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1845 struct skl_wm_values
{
1846 unsigned dirty_pipes
;
1847 struct skl_ddb_allocation ddb
;
1850 struct skl_wm_level
{
1852 uint16_t plane_res_b
;
1853 uint8_t plane_res_l
;
1856 /* Stores plane specific WM parameters */
1857 struct skl_wm_params
{
1858 bool x_tiled
, y_tiled
;
1862 uint32_t plane_pixel_rate
;
1863 uint32_t y_min_scanlines
;
1864 uint32_t plane_bytes_per_line
;
1865 uint_fixed_16_16_t plane_blocks_per_line
;
1866 uint_fixed_16_16_t y_tile_minimum
;
1867 uint32_t linetime_us
;
1871 * This struct helps tracking the state needed for runtime PM, which puts the
1872 * device in PCI D3 state. Notice that when this happens, nothing on the
1873 * graphics device works, even register access, so we don't get interrupts nor
1876 * Every piece of our code that needs to actually touch the hardware needs to
1877 * either call intel_runtime_pm_get or call intel_display_power_get with the
1878 * appropriate power domain.
1880 * Our driver uses the autosuspend delay feature, which means we'll only really
1881 * suspend if we stay with zero refcount for a certain amount of time. The
1882 * default value is currently very conservative (see intel_runtime_pm_enable), but
1883 * it can be changed with the standard runtime PM files from sysfs.
1885 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1886 * goes back to false exactly before we reenable the IRQs. We use this variable
1887 * to check if someone is trying to enable/disable IRQs while they're supposed
1888 * to be disabled. This shouldn't happen and we'll print some error messages in
1891 * For more, read the Documentation/power/runtime_pm.txt.
1893 struct i915_runtime_pm
{
1894 atomic_t wakeref_count
;
1899 enum intel_pipe_crc_source
{
1900 INTEL_PIPE_CRC_SOURCE_NONE
,
1901 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1902 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1903 INTEL_PIPE_CRC_SOURCE_PF
,
1904 INTEL_PIPE_CRC_SOURCE_PIPE
,
1905 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1906 INTEL_PIPE_CRC_SOURCE_TV
,
1907 INTEL_PIPE_CRC_SOURCE_DP_B
,
1908 INTEL_PIPE_CRC_SOURCE_DP_C
,
1909 INTEL_PIPE_CRC_SOURCE_DP_D
,
1910 INTEL_PIPE_CRC_SOURCE_AUTO
,
1911 INTEL_PIPE_CRC_SOURCE_MAX
,
1914 struct intel_pipe_crc_entry
{
1919 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1920 struct intel_pipe_crc
{
1922 bool opened
; /* exclusive access to the result file */
1923 struct intel_pipe_crc_entry
*entries
;
1924 enum intel_pipe_crc_source source
;
1926 wait_queue_head_t wq
;
1930 struct i915_frontbuffer_tracking
{
1934 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1941 struct i915_wa_reg
{
1944 /* bitmask representing WA bits */
1949 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1950 * allowing it for RCS as we don't foresee any requirement of having
1951 * a whitelist for other engines. When it is really required for
1952 * other engines then the limit need to be increased.
1954 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1956 struct i915_workarounds
{
1957 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1959 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1962 struct i915_virtual_gpu
{
1967 /* used in computing the new watermarks state */
1968 struct intel_wm_config
{
1969 unsigned int num_pipes_active
;
1970 bool sprites_enabled
;
1971 bool sprites_scaled
;
1974 struct i915_oa_format
{
1979 struct i915_oa_reg
{
1984 struct i915_oa_config
{
1985 char uuid
[UUID_STRING_LEN
+ 1];
1988 const struct i915_oa_reg
*mux_regs
;
1990 const struct i915_oa_reg
*b_counter_regs
;
1991 u32 b_counter_regs_len
;
1992 const struct i915_oa_reg
*flex_regs
;
1995 struct attribute_group sysfs_metric
;
1996 struct attribute
*attrs
[2];
1997 struct device_attribute sysfs_metric_id
;
2002 struct i915_perf_stream
;
2005 * struct i915_perf_stream_ops - the OPs to support a specific stream type
2007 struct i915_perf_stream_ops
{
2009 * @enable: Enables the collection of HW samples, either in response to
2010 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
2011 * without `I915_PERF_FLAG_DISABLED`.
2013 void (*enable
)(struct i915_perf_stream
*stream
);
2016 * @disable: Disables the collection of HW samples, either in response
2017 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
2020 void (*disable
)(struct i915_perf_stream
*stream
);
2023 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
2024 * once there is something ready to read() for the stream
2026 void (*poll_wait
)(struct i915_perf_stream
*stream
,
2031 * @wait_unlocked: For handling a blocking read, wait until there is
2032 * something to ready to read() for the stream. E.g. wait on the same
2033 * wait queue that would be passed to poll_wait().
2035 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
2038 * @read: Copy buffered metrics as records to userspace
2039 * **buf**: the userspace, destination buffer
2040 * **count**: the number of bytes to copy, requested by userspace
2041 * **offset**: zero at the start of the read, updated as the read
2042 * proceeds, it represents how many bytes have been copied so far and
2043 * the buffer offset for copying the next record.
2045 * Copy as many buffered i915 perf samples and records for this stream
2046 * to userspace as will fit in the given buffer.
2048 * Only write complete records; returning -%ENOSPC if there isn't room
2049 * for a complete record.
2051 * Return any error condition that results in a short read such as
2052 * -%ENOSPC or -%EFAULT, even though these may be squashed before
2053 * returning to userspace.
2055 int (*read
)(struct i915_perf_stream
*stream
,
2061 * @destroy: Cleanup any stream specific resources.
2063 * The stream will always be disabled before this is called.
2065 void (*destroy
)(struct i915_perf_stream
*stream
);
2069 * struct i915_perf_stream - state for a single open stream FD
2071 struct i915_perf_stream
{
2073 * @dev_priv: i915 drm device
2075 struct drm_i915_private
*dev_priv
;
2078 * @link: Links the stream into ``&drm_i915_private->streams``
2080 struct list_head link
;
2083 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2084 * properties given when opening a stream, representing the contents
2085 * of a single sample as read() by userspace.
2090 * @sample_size: Considering the configured contents of a sample
2091 * combined with the required header size, this is the total size
2092 * of a single sample record.
2097 * @ctx: %NULL if measuring system-wide across all contexts or a
2098 * specific context that is being monitored.
2100 struct i915_gem_context
*ctx
;
2103 * @enabled: Whether the stream is currently enabled, considering
2104 * whether the stream was opened in a disabled state and based
2105 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2110 * @ops: The callbacks providing the implementation of this specific
2111 * type of configured stream.
2113 const struct i915_perf_stream_ops
*ops
;
2116 * @oa_config: The OA configuration used by the stream.
2118 struct i915_oa_config
*oa_config
;
2122 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2124 struct i915_oa_ops
{
2126 * @is_valid_b_counter_reg: Validates register's address for
2127 * programming boolean counters for a particular platform.
2129 bool (*is_valid_b_counter_reg
)(struct drm_i915_private
*dev_priv
,
2133 * @is_valid_mux_reg: Validates register's address for programming mux
2134 * for a particular platform.
2136 bool (*is_valid_mux_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2139 * @is_valid_flex_reg: Validates register's address for programming
2140 * flex EU filtering for a particular platform.
2142 bool (*is_valid_flex_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2145 * @init_oa_buffer: Resets the head and tail pointers of the
2146 * circular buffer for periodic OA reports.
2148 * Called when first opening a stream for OA metrics, but also may be
2149 * called in response to an OA buffer overflow or other error
2152 * Note it may be necessary to clear the full OA buffer here as part of
2153 * maintaining the invariable that new reports must be written to
2154 * zeroed memory for us to be able to reliable detect if an expected
2155 * report has not yet landed in memory. (At least on Haswell the OA
2156 * buffer tail pointer is not synchronized with reports being visible
2159 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2162 * @enable_metric_set: Selects and applies any MUX configuration to set
2163 * up the Boolean and Custom (B/C) counters that are part of the
2164 * counter reports being sampled. May apply system constraints such as
2165 * disabling EU clock gating as required.
2167 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
,
2168 const struct i915_oa_config
*oa_config
);
2171 * @disable_metric_set: Remove system constraints associated with using
2174 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2177 * @oa_enable: Enable periodic sampling
2179 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2182 * @oa_disable: Disable periodic sampling
2184 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2187 * @read: Copy data from the circular OA buffer into a given userspace
2190 int (*read
)(struct i915_perf_stream
*stream
,
2196 * @oa_hw_tail_read: read the OA tail pointer register
2198 * In particular this enables us to share all the fiddly code for
2199 * handling the OA unit tail pointer race that affects multiple
2202 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
2205 struct intel_cdclk_state
{
2206 unsigned int cdclk
, vco
, ref
;
2209 struct drm_i915_private
{
2210 struct drm_device drm
;
2212 struct kmem_cache
*objects
;
2213 struct kmem_cache
*vmas
;
2214 struct kmem_cache
*luts
;
2215 struct kmem_cache
*requests
;
2216 struct kmem_cache
*dependencies
;
2217 struct kmem_cache
*priorities
;
2219 const struct intel_device_info info
;
2223 struct intel_uncore uncore
;
2225 struct i915_virtual_gpu vgpu
;
2227 struct intel_gvt
*gvt
;
2229 struct intel_huc huc
;
2230 struct intel_guc guc
;
2232 struct intel_csr csr
;
2234 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2236 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2237 * controller on different i2c buses. */
2238 struct mutex gmbus_mutex
;
2241 * Base address of the gmbus and gpio block.
2243 uint32_t gpio_mmio_base
;
2245 /* MMIO base address for MIPI regs */
2246 uint32_t mipi_mmio_base
;
2248 uint32_t psr_mmio_base
;
2250 uint32_t pps_mmio_base
;
2252 wait_queue_head_t gmbus_wait_queue
;
2254 struct pci_dev
*bridge_dev
;
2255 struct i915_gem_context
*kernel_context
;
2256 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2257 struct i915_vma
*semaphore
;
2259 struct drm_dma_handle
*status_page_dmah
;
2260 struct resource mch_res
;
2262 /* protects the irq masks */
2263 spinlock_t irq_lock
;
2265 bool display_irqs_enabled
;
2267 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2268 struct pm_qos_request pm_qos
;
2270 /* Sideband mailbox protection */
2271 struct mutex sb_lock
;
2273 /** Cached value of IMR to avoid reads in updating the bitfield */
2276 u32 de_irq_mask
[I915_MAX_PIPES
];
2283 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2285 struct i915_hotplug hotplug
;
2286 struct intel_fbc fbc
;
2287 struct i915_drrs drrs
;
2288 struct intel_opregion opregion
;
2289 struct intel_vbt_data vbt
;
2291 bool preserve_bios_swizzle
;
2294 struct intel_overlay
*overlay
;
2296 /* backlight registers and fields in struct intel_panel */
2297 struct mutex backlight_lock
;
2300 bool no_aux_handshake
;
2302 /* protects panel power sequencer state */
2303 struct mutex pps_mutex
;
2305 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2306 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2308 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2309 unsigned int skl_preferred_vco_freq
;
2310 unsigned int max_cdclk_freq
;
2312 unsigned int max_dotclk_freq
;
2313 unsigned int rawclk_freq
;
2314 unsigned int hpll_freq
;
2315 unsigned int czclk_freq
;
2319 * The current logical cdclk state.
2320 * See intel_atomic_state.cdclk.logical
2322 * For reading holding any crtc lock is sufficient,
2323 * for writing must hold all of them.
2325 struct intel_cdclk_state logical
;
2327 * The current actual cdclk state.
2328 * See intel_atomic_state.cdclk.actual
2330 struct intel_cdclk_state actual
;
2331 /* The current hardware cdclk state */
2332 struct intel_cdclk_state hw
;
2336 * wq - Driver workqueue for GEM.
2338 * NOTE: Work items scheduled here are not allowed to grab any modeset
2339 * locks, for otherwise the flushing done in the pageflip code will
2340 * result in deadlocks.
2342 struct workqueue_struct
*wq
;
2344 /* Display functions */
2345 struct drm_i915_display_funcs display
;
2347 /* PCH chipset type */
2348 enum intel_pch pch_type
;
2349 unsigned short pch_id
;
2351 unsigned long quirks
;
2353 enum modeset_restore modeset_restore
;
2354 struct mutex modeset_restore_lock
;
2355 struct drm_atomic_state
*modeset_restore_state
;
2356 struct drm_modeset_acquire_ctx reset_ctx
;
2358 struct list_head vm_list
; /* Global list of all address spaces */
2359 struct i915_ggtt ggtt
; /* VM representing the global address space */
2361 struct i915_gem_mm mm
;
2362 DECLARE_HASHTABLE(mm_structs
, 7);
2363 struct mutex mm_lock
;
2365 struct intel_ppat ppat
;
2367 /* Kernel Modesetting */
2369 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2370 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2372 #ifdef CONFIG_DEBUG_FS
2373 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2376 /* dpll and cdclk state is protected by connection_mutex */
2377 int num_shared_dpll
;
2378 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2379 const struct intel_dpll_mgr
*dpll_mgr
;
2382 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2383 * Must be global rather than per dpll, because on some platforms
2384 * plls share registers.
2386 struct mutex dpll_lock
;
2388 unsigned int active_crtcs
;
2389 /* minimum acceptable cdclk for each pipe */
2390 int min_cdclk
[I915_MAX_PIPES
];
2392 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2394 struct i915_workarounds workarounds
;
2396 struct i915_frontbuffer_tracking fb_tracking
;
2398 struct intel_atomic_helper
{
2399 struct llist_head free_list
;
2400 struct work_struct free_work
;
2405 bool mchbar_need_disable
;
2407 struct intel_l3_parity l3_parity
;
2409 /* Cannot be determined by PCIID. You must always read a register. */
2412 /* gen6+ rps state */
2413 struct intel_gen6_power_mgmt rps
;
2415 /* ilk-only ips/rps state. Everything in here is protected by the global
2416 * mchdev_lock in intel_pm.c */
2417 struct intel_ilk_power_mgmt ips
;
2419 struct i915_power_domains power_domains
;
2421 struct i915_psr psr
;
2423 struct i915_gpu_error gpu_error
;
2425 struct drm_i915_gem_object
*vlv_pctx
;
2427 /* list of fbdev register on this device */
2428 struct intel_fbdev
*fbdev
;
2429 struct work_struct fbdev_suspend_work
;
2431 struct drm_property
*broadcast_rgb_property
;
2432 struct drm_property
*force_audio_property
;
2434 /* hda/i915 audio component */
2435 struct i915_audio_component
*audio_component
;
2436 bool audio_component_registered
;
2438 * av_mutex - mutex for audio/video sync
2441 struct mutex av_mutex
;
2444 struct list_head list
;
2445 struct llist_head free_list
;
2446 struct work_struct free_work
;
2448 /* The hw wants to have a stable context identifier for the
2449 * lifetime of the context (for OA, PASID, faults, etc).
2450 * This is limited in execlists to 21 bits.
2453 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2458 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2459 u32 chv_phy_control
;
2461 * Shadows for CHV DPLL_MD regs to keep the state
2462 * checker somewhat working in the presence hardware
2463 * crappiness (can't read out DPLL_MD for pipes B & C).
2465 u32 chv_dpll_md
[I915_MAX_PIPES
];
2469 bool suspended_to_idle
;
2470 struct i915_suspend_saved_registers regfile
;
2471 struct vlv_s0ix_state vlv_s0ix_state
;
2474 I915_SAGV_UNKNOWN
= 0,
2477 I915_SAGV_NOT_CONTROLLED
2482 * Raw watermark latency values:
2483 * in 0.1us units for WM0,
2484 * in 0.5us units for WM1+.
2487 uint16_t pri_latency
[5];
2489 uint16_t spr_latency
[5];
2491 uint16_t cur_latency
[5];
2493 * Raw watermark memory latency values
2494 * for SKL for all 8 levels
2497 uint16_t skl_latency
[8];
2499 /* current hardware state */
2501 struct ilk_wm_values hw
;
2502 struct skl_wm_values skl_hw
;
2503 struct vlv_wm_values vlv
;
2504 struct g4x_wm_values g4x
;
2510 * Should be held around atomic WM register writing; also
2511 * protects * intel_crtc->wm.active and
2512 * cstate->wm.need_postvbl_update.
2514 struct mutex wm_mutex
;
2517 * Set during HW readout of watermarks/DDB. Some platforms
2518 * need to know when we're still using BIOS-provided values
2519 * (which we don't fully trust).
2521 bool distrust_bios_wm
;
2524 struct i915_runtime_pm pm
;
2529 struct kobject
*metrics_kobj
;
2530 struct ctl_table_header
*sysctl_header
;
2533 * Lock associated with adding/modifying/removing OA configs
2534 * in dev_priv->perf.metrics_idr.
2536 struct mutex metrics_lock
;
2539 * List of dynamic configurations, you need to hold
2540 * dev_priv->perf.metrics_lock to access it.
2542 struct idr metrics_idr
;
2545 * Lock associated with anything below within this structure
2546 * except exclusive_stream.
2549 struct list_head streams
;
2553 * The stream currently using the OA unit. If accessed
2554 * outside a syscall associated to its file
2555 * descriptor, you need to hold
2556 * dev_priv->drm.struct_mutex.
2558 struct i915_perf_stream
*exclusive_stream
;
2560 u32 specific_ctx_id
;
2562 struct hrtimer poll_check_timer
;
2563 wait_queue_head_t poll_wq
;
2567 * For rate limiting any notifications of spurious
2568 * invalid OA reports
2570 struct ratelimit_state spurious_report_rs
;
2573 int period_exponent
;
2574 int timestamp_frequency
;
2576 struct i915_oa_config test_config
;
2579 struct i915_vma
*vma
;
2586 * Locks reads and writes to all head/tail state
2588 * Consider: the head and tail pointer state
2589 * needs to be read consistently from a hrtimer
2590 * callback (atomic context) and read() fop
2591 * (user context) with tail pointer updates
2592 * happening in atomic context and head updates
2593 * in user context and the (unlikely)
2594 * possibility of read() errors needing to
2595 * reset all head/tail state.
2597 * Note: Contention or performance aren't
2598 * currently a significant concern here
2599 * considering the relatively low frequency of
2600 * hrtimer callbacks (5ms period) and that
2601 * reads typically only happen in response to a
2602 * hrtimer event and likely complete before the
2605 * Note: This lock is not held *while* reading
2606 * and copying data to userspace so the value
2607 * of head observed in htrimer callbacks won't
2608 * represent any partial consumption of data.
2610 spinlock_t ptr_lock
;
2613 * One 'aging' tail pointer and one 'aged'
2614 * tail pointer ready to used for reading.
2616 * Initial values of 0xffffffff are invalid
2617 * and imply that an update is required
2618 * (and should be ignored by an attempted
2626 * Index for the aged tail ready to read()
2629 unsigned int aged_tail_idx
;
2632 * A monotonic timestamp for when the current
2633 * aging tail pointer was read; used to
2634 * determine when it is old enough to trust.
2636 u64 aging_timestamp
;
2639 * Although we can always read back the head
2640 * pointer register, we prefer to avoid
2641 * trusting the HW state, just to avoid any
2642 * risk that some hardware condition could
2643 * somehow bump the head pointer unpredictably
2644 * and cause us to forward the wrong OA buffer
2645 * data to userspace.
2650 u32 gen7_latched_oastatus1
;
2651 u32 ctx_oactxctrl_offset
;
2652 u32 ctx_flexeu0_offset
;
2655 * The RPT_ID/reason field for Gen8+ includes a bit
2656 * to determine if the CTX ID in the report is valid
2657 * but the specific bit differs between Gen 8 and 9
2659 u32 gen8_valid_ctx_bit
;
2661 struct i915_oa_ops ops
;
2662 const struct i915_oa_format
*oa_formats
;
2666 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2668 void (*resume
)(struct drm_i915_private
*);
2669 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2671 struct list_head timelines
;
2672 struct i915_gem_timeline global_timeline
;
2673 u32 active_requests
;
2676 * Is the GPU currently considered idle, or busy executing
2677 * userspace requests? Whilst idle, we allow runtime power
2678 * management to power down the hardware and display clocks.
2679 * In order to reduce the effect on performance, there
2680 * is a slight delay before we do so.
2685 * We leave the user IRQ off as much as possible,
2686 * but this means that requests will finish and never
2687 * be retired once the system goes idle. Set a timer to
2688 * fire periodically while the ring is running. When it
2689 * fires, go retire requests.
2691 struct delayed_work retire_work
;
2694 * When we detect an idle GPU, we want to turn on
2695 * powersaving features. So once we see that there
2696 * are no more requests outstanding and no more
2697 * arrive within a small period of time, we fire
2698 * off the idle_work.
2700 struct delayed_work idle_work
;
2702 ktime_t last_init_time
;
2705 /* perform PHY state sanity checks? */
2706 bool chv_phy_assert
[2];
2710 /* Used to save the pipe-to-encoder mapping for audio */
2711 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2713 /* necessary resource sharing with HDMI LPE audio driver. */
2715 struct platform_device
*platdev
;
2720 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2721 * will be rejected. Instead look for a better place.
2725 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2727 return container_of(dev
, struct drm_i915_private
, drm
);
2730 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2732 return to_i915(dev_get_drvdata(kdev
));
2735 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2737 return container_of(guc
, struct drm_i915_private
, guc
);
2740 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2742 return container_of(huc
, struct drm_i915_private
, huc
);
2745 /* Simple iterator over all initialised engines */
2746 #define for_each_engine(engine__, dev_priv__, id__) \
2748 (id__) < I915_NUM_ENGINES; \
2750 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2752 /* Iterator over subset of engines selected by mask */
2753 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2754 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2755 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2757 enum hdmi_force_audio
{
2758 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2759 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2760 HDMI_AUDIO_AUTO
, /* trust EDID */
2761 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2764 #define I915_GTT_OFFSET_NONE ((u32)-1)
2767 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2768 * considered to be the frontbuffer for the given plane interface-wise. This
2769 * doesn't mean that the hw necessarily already scans it out, but that any
2770 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2772 * We have one bit per pipe and per scanout plane type.
2774 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2775 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2776 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2777 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2778 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2779 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2780 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2781 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2782 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2783 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2784 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2785 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2788 * Optimised SGL iterator for GEM objects
2790 static __always_inline
struct sgt_iter
{
2791 struct scatterlist
*sgp
;
2798 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2799 struct sgt_iter s
= { .sgp
= sgl
};
2802 s
.max
= s
.curr
= s
.sgp
->offset
;
2803 s
.max
+= s
.sgp
->length
;
2805 s
.dma
= sg_dma_address(s
.sgp
);
2807 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2813 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2816 if (unlikely(sg_is_chain(sg
)))
2817 sg
= sg_chain_ptr(sg
);
2822 * __sg_next - return the next scatterlist entry in a list
2823 * @sg: The current sg entry
2826 * If the entry is the last, return NULL; otherwise, step to the next
2827 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2828 * otherwise just return the pointer to the current element.
2830 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2832 #ifdef CONFIG_DEBUG_SG
2833 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2835 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2839 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2840 * @__dmap: DMA address (output)
2841 * @__iter: 'struct sgt_iter' (iterator state, internal)
2842 * @__sgt: sg_table to iterate over (input)
2844 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2845 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2846 ((__dmap) = (__iter).dma + (__iter).curr); \
2847 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2848 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2851 * for_each_sgt_page - iterate over the pages of the given sg_table
2852 * @__pp: page pointer (output)
2853 * @__iter: 'struct sgt_iter' (iterator state, internal)
2854 * @__sgt: sg_table to iterate over (input)
2856 #define for_each_sgt_page(__pp, __iter, __sgt) \
2857 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2858 ((__pp) = (__iter).pfn == 0 ? NULL : \
2859 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2860 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2861 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2863 static inline unsigned int i915_sg_segment_size(void)
2865 unsigned int size
= swiotlb_max_segment();
2868 return SCATTERLIST_MAX_SEGMENT
;
2870 size
= rounddown(size
, PAGE_SIZE
);
2871 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2872 if (size
< PAGE_SIZE
)
2878 static inline const struct intel_device_info
*
2879 intel_info(const struct drm_i915_private
*dev_priv
)
2881 return &dev_priv
->info
;
2884 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2886 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2887 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2889 #define REVID_FOREVER 0xff
2890 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2892 #define GEN_FOREVER (0)
2894 #define INTEL_GEN_MASK(s, e) ( \
2895 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2896 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2897 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2898 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2902 * Returns true if Gen is in inclusive range [Start, End].
2904 * Use GEN_FOREVER for unbound start and or end.
2906 #define IS_GEN(dev_priv, s, e) \
2907 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2910 * Return true if revision is in range [since,until] inclusive.
2912 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2914 #define IS_REVID(p, since, until) \
2915 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2917 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2919 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2920 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2921 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2922 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2923 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2924 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2925 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2926 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2927 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2928 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2929 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2930 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2931 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2932 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2933 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2934 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2935 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2936 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2937 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2938 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2939 (dev_priv)->info.gt == 1)
2940 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2941 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2942 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2943 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2944 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2945 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2946 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2947 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2948 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2949 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2950 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2951 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2952 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2953 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2954 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2955 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2956 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2957 /* ULX machines are also considered ULT. */
2958 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2959 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2960 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2961 (dev_priv)->info.gt == 3)
2962 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2963 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2964 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2965 (dev_priv)->info.gt == 3)
2966 /* ULX machines are also considered ULT. */
2967 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2968 INTEL_DEVID(dev_priv) == 0x0A1E)
2969 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2970 INTEL_DEVID(dev_priv) == 0x1913 || \
2971 INTEL_DEVID(dev_priv) == 0x1916 || \
2972 INTEL_DEVID(dev_priv) == 0x1921 || \
2973 INTEL_DEVID(dev_priv) == 0x1926)
2974 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2975 INTEL_DEVID(dev_priv) == 0x1915 || \
2976 INTEL_DEVID(dev_priv) == 0x191E)
2977 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2978 INTEL_DEVID(dev_priv) == 0x5913 || \
2979 INTEL_DEVID(dev_priv) == 0x5916 || \
2980 INTEL_DEVID(dev_priv) == 0x5921 || \
2981 INTEL_DEVID(dev_priv) == 0x5926)
2982 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2983 INTEL_DEVID(dev_priv) == 0x5915 || \
2984 INTEL_DEVID(dev_priv) == 0x591E)
2985 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2986 (dev_priv)->info.gt == 2)
2987 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2988 (dev_priv)->info.gt == 3)
2989 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2990 (dev_priv)->info.gt == 4)
2991 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2992 (dev_priv)->info.gt == 2)
2993 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2994 (dev_priv)->info.gt == 3)
2995 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2996 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2997 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2998 (dev_priv)->info.gt == 2)
3000 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
3002 #define SKL_REVID_A0 0x0
3003 #define SKL_REVID_B0 0x1
3004 #define SKL_REVID_C0 0x2
3005 #define SKL_REVID_D0 0x3
3006 #define SKL_REVID_E0 0x4
3007 #define SKL_REVID_F0 0x5
3008 #define SKL_REVID_G0 0x6
3009 #define SKL_REVID_H0 0x7
3011 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
3013 #define BXT_REVID_A0 0x0
3014 #define BXT_REVID_A1 0x1
3015 #define BXT_REVID_B0 0x3
3016 #define BXT_REVID_B_LAST 0x8
3017 #define BXT_REVID_C0 0x9
3019 #define IS_BXT_REVID(dev_priv, since, until) \
3020 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
3022 #define KBL_REVID_A0 0x0
3023 #define KBL_REVID_B0 0x1
3024 #define KBL_REVID_C0 0x2
3025 #define KBL_REVID_D0 0x3
3026 #define KBL_REVID_E0 0x4
3028 #define IS_KBL_REVID(dev_priv, since, until) \
3029 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
3031 #define GLK_REVID_A0 0x0
3032 #define GLK_REVID_A1 0x1
3034 #define IS_GLK_REVID(dev_priv, since, until) \
3035 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
3037 #define CNL_REVID_A0 0x0
3038 #define CNL_REVID_B0 0x1
3040 #define IS_CNL_REVID(p, since, until) \
3041 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
3044 * The genX designation typically refers to the render engine, so render
3045 * capability related checks should use IS_GEN, while display and other checks
3046 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
3049 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
3050 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
3051 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
3052 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
3053 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
3054 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
3055 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
3056 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
3057 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
3059 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
3060 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
3061 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
3063 #define ENGINE_MASK(id) BIT(id)
3064 #define RENDER_RING ENGINE_MASK(RCS)
3065 #define BSD_RING ENGINE_MASK(VCS)
3066 #define BLT_RING ENGINE_MASK(BCS)
3067 #define VEBOX_RING ENGINE_MASK(VECS)
3068 #define BSD2_RING ENGINE_MASK(VCS2)
3069 #define ALL_ENGINES (~0)
3071 #define HAS_ENGINE(dev_priv, id) \
3072 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
3074 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
3075 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
3076 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
3077 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
3079 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
3080 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
3081 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
3082 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
3083 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
3085 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
3087 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
3088 ((dev_priv)->info.has_logical_ring_contexts)
3089 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
3090 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
3091 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
3093 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
3094 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
3095 ((dev_priv)->info.overlay_needs_physical)
3097 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
3098 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
3100 /* WaRsDisableCoarsePowerGating:skl,bxt */
3101 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
3102 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
3105 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
3106 * even when in MSI mode. This results in spurious interrupt warnings if the
3107 * legacy irq no. is shared with another device. The kernel then disables that
3108 * interrupt source and so prevents the other device from working properly.
3110 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
3113 #define HAS_AUX_IRQ(dev_priv) true
3114 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
3116 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
3117 * rows, which changed the alignment requirements and fence programming.
3119 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
3120 !(IS_I915G(dev_priv) || \
3121 IS_I915GM(dev_priv)))
3122 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
3123 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
3125 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
3126 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
3127 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
3128 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
3130 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
3132 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
3134 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
3135 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
3136 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
3137 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
3138 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
3140 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
3142 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
3143 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
3145 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
3148 * For now, anything with a GuC requires uCode loading, and then supports
3149 * command submission once loaded. But these are logically independent
3150 * properties, so we have separate macros to test them.
3152 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
3153 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
3154 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3155 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
3156 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3158 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3160 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
3162 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3163 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3164 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3165 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3166 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3167 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3168 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3169 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3170 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3171 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3172 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3173 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3174 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3175 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3176 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3177 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3179 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3180 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3181 #define HAS_PCH_CNP_LP(dev_priv) \
3182 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3183 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3184 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3185 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3186 #define HAS_PCH_LPT_LP(dev_priv) \
3187 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3188 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3189 #define HAS_PCH_LPT_H(dev_priv) \
3190 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3191 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3192 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3193 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3194 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3195 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3197 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3199 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3201 /* DPF == dynamic parity feature */
3202 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3203 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3204 2 : HAS_L3_DPF(dev_priv))
3206 #define GT_FREQUENCY_MULTIPLIER 50
3207 #define GEN9_FREQ_SCALER 3
3209 #include "i915_trace.h"
3211 static inline bool intel_vtd_active(void)
3213 #ifdef CONFIG_INTEL_IOMMU
3214 if (intel_iommu_gfx_mapped
)
3220 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3222 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
3226 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3228 return IS_BROXTON(dev_priv
) && intel_vtd_active();
3231 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
3234 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
3238 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
3239 const char *fmt
, ...);
3241 #define i915_report_error(dev_priv, fmt, ...) \
3242 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3244 #ifdef CONFIG_COMPAT
3245 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3248 #define i915_compat_ioctl NULL
3250 extern const struct dev_pm_ops i915_pm_ops
;
3252 extern int i915_driver_load(struct pci_dev
*pdev
,
3253 const struct pci_device_id
*ent
);
3254 extern void i915_driver_unload(struct drm_device
*dev
);
3255 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3256 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3258 #define I915_RESET_QUIET BIT(0)
3259 extern void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
);
3260 extern int i915_reset_engine(struct intel_engine_cs
*engine
,
3261 unsigned int flags
);
3263 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
3264 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3265 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3266 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3267 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3268 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3269 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3270 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3271 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3273 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
3274 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3276 /* intel_hotplug.c */
3277 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3278 u32 pin_mask
, u32 long_mask
);
3279 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3280 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3281 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3282 enum port
intel_hpd_pin_to_port(enum hpd_pin pin
);
3283 enum hpd_pin
intel_hpd_pin(enum port port
);
3284 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3285 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3288 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3290 unsigned long delay
;
3292 if (unlikely(!i915_modparams
.enable_hangcheck
))
3295 /* Don't continually defer the hangcheck so that it is always run at
3296 * least once after work has been scheduled on any ring. Otherwise,
3297 * we will ignore a hung ring if a second ring is kept busy.
3300 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3301 queue_delayed_work(system_long_wq
,
3302 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3306 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3308 const char *fmt
, ...);
3310 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3311 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
3312 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3313 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3315 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3317 return dev_priv
->gvt
;
3320 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3322 return dev_priv
->vgpu
.active
;
3325 u32
i915_pipestat_enable_mask(struct drm_i915_private
*dev_priv
,
3328 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3332 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3335 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3336 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3337 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3340 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3341 uint32_t interrupt_mask
,
3342 uint32_t enabled_irq_mask
);
3344 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3346 ilk_update_display_irq(dev_priv
, bits
, bits
);
3349 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3351 ilk_update_display_irq(dev_priv
, bits
, 0);
3353 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3355 uint32_t interrupt_mask
,
3356 uint32_t enabled_irq_mask
);
3357 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3358 enum pipe pipe
, uint32_t bits
)
3360 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3362 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3363 enum pipe pipe
, uint32_t bits
)
3365 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3367 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3368 uint32_t interrupt_mask
,
3369 uint32_t enabled_irq_mask
);
3371 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3373 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3376 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3378 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3382 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3383 struct drm_file
*file_priv
);
3384 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3385 struct drm_file
*file_priv
);
3386 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3387 struct drm_file
*file_priv
);
3388 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3389 struct drm_file
*file_priv
);
3390 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3391 struct drm_file
*file_priv
);
3392 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3393 struct drm_file
*file_priv
);
3394 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3395 struct drm_file
*file_priv
);
3396 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3397 struct drm_file
*file_priv
);
3398 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3399 struct drm_file
*file_priv
);
3400 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3401 struct drm_file
*file_priv
);
3402 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3403 struct drm_file
*file
);
3404 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3405 struct drm_file
*file
);
3406 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3407 struct drm_file
*file_priv
);
3408 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3409 struct drm_file
*file_priv
);
3410 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3411 struct drm_file
*file_priv
);
3412 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3413 struct drm_file
*file_priv
);
3414 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3415 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
3416 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3417 struct drm_file
*file
);
3418 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3419 struct drm_file
*file_priv
);
3420 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3421 struct drm_file
*file_priv
);
3422 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3423 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3424 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3425 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3426 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3427 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3429 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3430 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3431 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3432 const struct drm_i915_gem_object_ops
*ops
);
3433 struct drm_i915_gem_object
*
3434 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3435 struct drm_i915_gem_object
*
3436 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3437 const void *data
, size_t size
);
3438 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3439 void i915_gem_free_object(struct drm_gem_object
*obj
);
3441 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3443 /* A single pass should suffice to release all the freed objects (along
3444 * most call paths) , but be a little more paranoid in that freeing
3445 * the objects does take a little amount of time, during which the rcu
3446 * callbacks could have added new objects into the freed list, and
3447 * armed the work again.
3451 } while (flush_work(&i915
->mm
.free_work
));
3454 static inline void i915_gem_drain_workqueue(struct drm_i915_private
*i915
)
3457 * Similar to objects above (see i915_gem_drain_freed-objects), in
3458 * general we have workers that are armed by RCU and then rearm
3459 * themselves in their callbacks. To be paranoid, we need to
3460 * drain the workqueue a second time after waiting for the RCU
3461 * grace period so that we catch work queued via RCU from the first
3462 * pass. As neither drain_workqueue() nor flush_workqueue() report
3463 * a result, we make an assumption that we only don't require more
3464 * than 2 passes to catch all recursive RCU delayed work.
3470 drain_workqueue(i915
->wq
);
3474 struct i915_vma
* __must_check
3475 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3476 const struct i915_ggtt_view
*view
,
3481 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3482 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3484 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3486 static inline int __sg_page_count(const struct scatterlist
*sg
)
3488 return sg
->length
>> PAGE_SHIFT
;
3491 struct scatterlist
*
3492 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3493 unsigned int n
, unsigned int *offset
);
3496 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3500 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3504 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3507 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3508 struct sg_table
*pages
);
3509 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3511 static inline int __must_check
3512 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3514 might_lock(&obj
->mm
.lock
);
3516 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3519 return __i915_gem_object_get_pages(obj
);
3523 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3525 GEM_BUG_ON(!obj
->mm
.pages
);
3527 atomic_inc(&obj
->mm
.pages_pin_count
);
3531 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3533 return atomic_read(&obj
->mm
.pages_pin_count
);
3537 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3539 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3540 GEM_BUG_ON(!obj
->mm
.pages
);
3542 atomic_dec(&obj
->mm
.pages_pin_count
);
3546 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3548 __i915_gem_object_unpin_pages(obj
);
3551 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3556 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3557 enum i915_mm_subclass subclass
);
3558 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3560 enum i915_map_type
{
3563 #define I915_MAP_OVERRIDE BIT(31)
3564 I915_MAP_FORCE_WB
= I915_MAP_WB
| I915_MAP_OVERRIDE
,
3565 I915_MAP_FORCE_WC
= I915_MAP_WC
| I915_MAP_OVERRIDE
,
3569 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3570 * @obj: the object to map into kernel address space
3571 * @type: the type of mapping, used to select pgprot_t
3573 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3574 * pages and then returns a contiguous mapping of the backing storage into
3575 * the kernel address space. Based on the @type of mapping, the PTE will be
3576 * set to either WriteBack or WriteCombine (via pgprot_t).
3578 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3579 * mapping is no longer required.
3581 * Returns the pointer through which to access the mapped object, or an
3582 * ERR_PTR() on error.
3584 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3585 enum i915_map_type type
);
3588 * i915_gem_object_unpin_map - releases an earlier mapping
3589 * @obj: the object to unmap
3591 * After pinning the object and mapping its pages, once you are finished
3592 * with your access, call i915_gem_object_unpin_map() to release the pin
3593 * upon the mapping. Once the pin count reaches zero, that mapping may be
3596 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3598 i915_gem_object_unpin_pages(obj
);
3601 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3602 unsigned int *needs_clflush
);
3603 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3604 unsigned int *needs_clflush
);
3605 #define CLFLUSH_BEFORE BIT(0)
3606 #define CLFLUSH_AFTER BIT(1)
3607 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3610 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3612 i915_gem_object_unpin_pages(obj
);
3615 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3616 void i915_vma_move_to_active(struct i915_vma
*vma
,
3617 struct drm_i915_gem_request
*req
,
3618 unsigned int flags
);
3619 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3620 struct drm_device
*dev
,
3621 struct drm_mode_create_dumb
*args
);
3622 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3623 uint32_t handle
, uint64_t *offset
);
3624 int i915_gem_mmap_gtt_version(void);
3626 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3627 struct drm_i915_gem_object
*new,
3628 unsigned frontbuffer_bits
);
3630 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3632 struct drm_i915_gem_request
*
3633 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3635 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3637 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3639 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3642 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3644 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3647 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3649 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3652 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3654 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3657 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3659 return READ_ONCE(error
->reset_count
);
3662 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3663 struct intel_engine_cs
*engine
)
3665 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3668 struct drm_i915_gem_request
*
3669 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3670 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3671 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3672 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3673 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3674 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3675 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3676 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3677 struct drm_i915_gem_request
*request
);
3679 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3680 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3681 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3682 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3683 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3684 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3685 unsigned int flags
);
3686 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3687 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3688 int i915_gem_fault(struct vm_fault
*vmf
);
3689 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3692 struct intel_rps_client
*rps
);
3693 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3696 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3699 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3701 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3703 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3704 struct i915_vma
* __must_check
3705 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3707 const struct i915_ggtt_view
*view
);
3708 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3709 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3711 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3712 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3714 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3715 enum i915_cache_level cache_level
);
3717 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3718 struct dma_buf
*dma_buf
);
3720 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3721 struct drm_gem_object
*gem_obj
, int flags
);
3723 static inline struct i915_hw_ppgtt
*
3724 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3726 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3729 /* i915_gem_fence_reg.c */
3730 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3731 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3732 struct drm_i915_fence_reg
*
3733 i915_reserve_fence(struct drm_i915_private
*dev_priv
);
3734 void i915_unreserve_fence(struct drm_i915_fence_reg
*fence
);
3736 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3737 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3739 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3740 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3741 struct sg_table
*pages
);
3742 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3743 struct sg_table
*pages
);
3745 static inline struct i915_gem_context
*
3746 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3748 return idr_find(&file_priv
->context_idr
, id
);
3751 static inline struct i915_gem_context
*
3752 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3754 struct i915_gem_context
*ctx
;
3757 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3758 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3765 static inline struct intel_timeline
*
3766 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3767 struct intel_engine_cs
*engine
)
3769 struct i915_address_space
*vm
;
3771 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3772 return &vm
->timeline
.engine
[engine
->id
];
3775 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3776 struct drm_file
*file
);
3777 int i915_perf_add_config_ioctl(struct drm_device
*dev
, void *data
,
3778 struct drm_file
*file
);
3779 int i915_perf_remove_config_ioctl(struct drm_device
*dev
, void *data
,
3780 struct drm_file
*file
);
3781 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3782 struct i915_gem_context
*ctx
,
3783 uint32_t *reg_state
);
3785 /* i915_gem_evict.c */
3786 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3787 u64 min_size
, u64 alignment
,
3788 unsigned cache_level
,
3791 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3792 struct drm_mm_node
*node
,
3793 unsigned int flags
);
3794 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3796 /* belongs in i915_gem_gtt.h */
3797 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3800 if (INTEL_GEN(dev_priv
) < 6)
3801 intel_gtt_chipset_flush();
3804 /* i915_gem_stolen.c */
3805 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3806 struct drm_mm_node
*node
, u64 size
,
3807 unsigned alignment
);
3808 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3809 struct drm_mm_node
*node
, u64 size
,
3810 unsigned alignment
, u64 start
,
3812 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3813 struct drm_mm_node
*node
);
3814 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3815 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3816 struct drm_i915_gem_object
*
3817 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3818 struct drm_i915_gem_object
*
3819 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3824 /* i915_gem_internal.c */
3825 struct drm_i915_gem_object
*
3826 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3829 /* i915_gem_shrinker.c */
3830 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3831 unsigned long target
,
3833 #define I915_SHRINK_PURGEABLE 0x1
3834 #define I915_SHRINK_UNBOUND 0x2
3835 #define I915_SHRINK_BOUND 0x4
3836 #define I915_SHRINK_ACTIVE 0x8
3837 #define I915_SHRINK_VMAPS 0x10
3838 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3839 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3840 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3843 /* i915_gem_tiling.c */
3844 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3846 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3848 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3849 i915_gem_object_is_tiled(obj
);
3852 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3853 unsigned int tiling
, unsigned int stride
);
3854 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3855 unsigned int tiling
, unsigned int stride
);
3857 /* i915_debugfs.c */
3858 #ifdef CONFIG_DEBUG_FS
3859 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3860 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3861 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3863 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3864 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3866 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3869 /* i915_gpu_error.c */
3870 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3873 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3874 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3875 const struct i915_gpu_state
*gpu
);
3876 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3877 struct drm_i915_private
*i915
,
3878 size_t count
, loff_t pos
);
3879 static inline void i915_error_state_buf_release(
3880 struct drm_i915_error_state_buf
*eb
)
3885 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3886 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3888 const char *error_msg
);
3890 static inline struct i915_gpu_state
*
3891 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3893 kref_get(&gpu
->ref
);
3897 void __i915_gpu_state_free(struct kref
*kref
);
3898 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3901 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3904 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3905 void i915_reset_error_state(struct drm_i915_private
*i915
);
3909 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3911 const char *error_msg
)
3915 static inline struct i915_gpu_state
*
3916 i915_first_error_state(struct drm_i915_private
*i915
)
3921 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3927 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3929 /* i915_cmd_parser.c */
3930 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3931 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3932 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3933 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3934 struct drm_i915_gem_object
*batch_obj
,
3935 struct drm_i915_gem_object
*shadow_batch_obj
,
3936 u32 batch_start_offset
,
3941 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3942 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3943 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3944 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3946 /* i915_suspend.c */
3947 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3948 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3951 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3952 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3954 /* intel_lpe_audio.c */
3955 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
3956 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
3957 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
3958 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
3959 enum pipe pipe
, enum port port
,
3960 const void *eld
, int ls_clock
, bool dp_output
);
3963 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3964 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3965 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3968 extern struct i2c_adapter
*
3969 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3970 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3971 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3972 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3974 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3976 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3979 void intel_bios_init(struct drm_i915_private
*dev_priv
);
3980 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3981 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3982 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3983 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3984 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3985 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3986 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3987 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3989 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3993 /* intel_opregion.c */
3995 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3996 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3997 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3998 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3999 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
4001 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
4003 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
4005 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
4006 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
4007 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
4008 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
4012 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
4017 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
4021 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
4029 extern void intel_register_dsm_handler(void);
4030 extern void intel_unregister_dsm_handler(void);
4032 static inline void intel_register_dsm_handler(void) { return; }
4033 static inline void intel_unregister_dsm_handler(void) { return; }
4034 #endif /* CONFIG_ACPI */
4036 /* intel_device_info.c */
4037 static inline struct intel_device_info
*
4038 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
4040 return (struct intel_device_info
*)&dev_priv
->info
;
4043 const char *intel_platform_name(enum intel_platform platform
);
4044 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
4045 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
4048 extern void intel_modeset_init_hw(struct drm_device
*dev
);
4049 extern int intel_modeset_init(struct drm_device
*dev
);
4050 extern void intel_modeset_gem_init(struct drm_device
*dev
);
4051 extern void intel_modeset_cleanup(struct drm_device
*dev
);
4052 extern int intel_connector_register(struct drm_connector
*);
4053 extern void intel_connector_unregister(struct drm_connector
*);
4054 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
4056 extern void intel_display_resume(struct drm_device
*dev
);
4057 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
4058 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
4059 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
4060 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
4061 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
4062 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
4065 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
4066 struct drm_file
*file
);
4069 extern struct intel_overlay_error_state
*
4070 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
4071 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
4072 struct intel_overlay_error_state
*error
);
4074 extern struct intel_display_error_state
*
4075 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
4076 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
4077 struct intel_display_error_state
*error
);
4079 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
4080 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
4081 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
4082 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
4084 /* intel_sideband.c */
4085 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
4086 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
4087 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
4088 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
4089 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
4090 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4091 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4092 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4093 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4094 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4095 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4096 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
4097 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
4098 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
4099 enum intel_sbi_destination destination
);
4100 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
4101 enum intel_sbi_destination destination
);
4102 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4103 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4105 /* intel_dpio_phy.c */
4106 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
4107 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
4108 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
4109 enum port port
, u32 margin
, u32 scale
,
4110 u32 enable
, u32 deemphasis
);
4111 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4112 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4113 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
4115 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
4117 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
4118 uint8_t lane_count
);
4119 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
4120 uint8_t lane_lat_optim_mask
);
4121 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
4123 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
4124 u32 deemph_reg_value
, u32 margin_reg_value
,
4125 bool uniq_trans_scale
);
4126 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
4128 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4129 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4130 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
4131 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
4133 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
4134 u32 demph_reg_value
, u32 preemph_reg_value
,
4135 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
4136 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4137 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4138 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
4140 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
4141 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
4142 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
4143 const i915_reg_t reg
);
4145 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
4146 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
4148 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
4149 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
4150 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
4151 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
4153 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
4154 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
4155 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
4156 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
4158 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
4159 * will be implemented using 2 32-bit writes in an arbitrary order with
4160 * an arbitrary delay between them. This can cause the hardware to
4161 * act upon the intermediate value, possibly leading to corruption and
4162 * machine death. For this reason we do not support I915_WRITE64, or
4163 * dev_priv->uncore.funcs.mmio_writeq.
4165 * When reading a 64-bit value as two 32-bit values, the delay may cause
4166 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
4167 * occasionally a 64-bit register does not actualy support a full readq
4168 * and must be read using two 32-bit reads.
4170 * You have been warned.
4172 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
4174 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
4175 u32 upper, lower, old_upper, loop = 0; \
4176 upper = I915_READ(upper_reg); \
4178 old_upper = upper; \
4179 lower = I915_READ(lower_reg); \
4180 upper = I915_READ(upper_reg); \
4181 } while (upper != old_upper && loop++ < 2); \
4182 (u64)upper << 32 | lower; })
4184 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
4185 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
4187 #define __raw_read(x, s) \
4188 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4191 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4194 #define __raw_write(x, s) \
4195 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4196 i915_reg_t reg, uint##x##_t val) \
4198 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4213 /* These are untraced mmio-accessors that are only valid to be used inside
4214 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4217 * Think twice, and think again, before using these.
4219 * As an example, these accessors can possibly be used between:
4221 * spin_lock_irq(&dev_priv->uncore.lock);
4222 * intel_uncore_forcewake_get__locked();
4226 * intel_uncore_forcewake_put__locked();
4227 * spin_unlock_irq(&dev_priv->uncore.lock);
4230 * Note: some registers may not need forcewake held, so
4231 * intel_uncore_forcewake_{get,put} can be omitted, see
4232 * intel_uncore_forcewake_for_reg().
4234 * Certain architectures will die if the same cacheline is concurrently accessed
4235 * by different clients (e.g. on Ivybridge). Access to registers should
4236 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4237 * a more localised lock guarding all access to that bank of registers.
4239 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4240 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4241 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4242 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4244 /* "Broadcast RGB" property */
4245 #define INTEL_BROADCAST_RGB_AUTO 0
4246 #define INTEL_BROADCAST_RGB_FULL 1
4247 #define INTEL_BROADCAST_RGB_LIMITED 2
4249 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4251 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4252 return VLV_VGACNTRL
;
4253 else if (INTEL_GEN(dev_priv
) >= 5)
4254 return CPU_VGACNTRL
;
4259 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4261 unsigned long j
= msecs_to_jiffies(m
);
4263 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4266 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4268 /* nsecs_to_jiffies64() does not guard against overflow */
4269 if (NSEC_PER_SEC
% HZ
&&
4270 div_u64(n
, NSEC_PER_SEC
) >= MAX_JIFFY_OFFSET
/ HZ
)
4271 return MAX_JIFFY_OFFSET
;
4273 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4276 static inline unsigned long
4277 timespec_to_jiffies_timeout(const struct timespec
*value
)
4279 unsigned long j
= timespec_to_jiffies(value
);
4281 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4285 * If you need to wait X milliseconds between events A and B, but event B
4286 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4287 * when event A happened, then just before event B you call this function and
4288 * pass the timestamp as the first argument, and X as the second argument.
4291 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4293 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4296 * Don't re-read the value of "jiffies" every time since it may change
4297 * behind our back and break the math.
4299 tmp_jiffies
= jiffies
;
4300 target_jiffies
= timestamp_jiffies
+
4301 msecs_to_jiffies_timeout(to_wait_ms
);
4303 if (time_after(target_jiffies
, tmp_jiffies
)) {
4304 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4305 while (remaining_jiffies
)
4307 schedule_timeout_uninterruptible(remaining_jiffies
);
4312 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4314 struct intel_engine_cs
*engine
= req
->engine
;
4317 /* Note that the engine may have wrapped around the seqno, and
4318 * so our request->global_seqno will be ahead of the hardware,
4319 * even though it completed the request before wrapping. We catch
4320 * this by kicking all the waiters before resetting the seqno
4321 * in hardware, and also signal the fence.
4323 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4326 /* The request was dequeued before we were awoken. We check after
4327 * inspecting the hw to confirm that this was the same request
4328 * that generated the HWS update. The memory barriers within
4329 * the request execution are sufficient to ensure that a check
4330 * after reading the value from hw matches this request.
4332 seqno
= i915_gem_request_global_seqno(req
);
4336 /* Before we do the heavier coherent read of the seqno,
4337 * check the value (hopefully) in the CPU cacheline.
4339 if (__i915_gem_request_completed(req
, seqno
))
4342 /* Ensure our read of the seqno is coherent so that we
4343 * do not "miss an interrupt" (i.e. if this is the last
4344 * request and the seqno write from the GPU is not visible
4345 * by the time the interrupt fires, we will see that the
4346 * request is incomplete and go back to sleep awaiting
4347 * another interrupt that will never come.)
4349 * Strictly, we only need to do this once after an interrupt,
4350 * but it is easier and safer to do it every time the waiter
4353 if (engine
->irq_seqno_barrier
&&
4354 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4355 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4357 /* The ordering of irq_posted versus applying the barrier
4358 * is crucial. The clearing of the current irq_posted must
4359 * be visible before we perform the barrier operation,
4360 * such that if a subsequent interrupt arrives, irq_posted
4361 * is reasserted and our task rewoken (which causes us to
4362 * do another __i915_request_irq_complete() immediately
4363 * and reapply the barrier). Conversely, if the clear
4364 * occurs after the barrier, then an interrupt that arrived
4365 * whilst we waited on the barrier would not trigger a
4366 * barrier on the next pass, and the read may not see the
4369 engine
->irq_seqno_barrier(engine
);
4371 /* If we consume the irq, but we are no longer the bottom-half,
4372 * the real bottom-half may not have serialised their own
4373 * seqno check with the irq-barrier (i.e. may have inspected
4374 * the seqno before we believe it coherent since they see
4375 * irq_posted == false but we are still running).
4377 spin_lock_irq(&b
->irq_lock
);
4378 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4379 /* Note that if the bottom-half is changed as we
4380 * are sending the wake-up, the new bottom-half will
4381 * be woken by whomever made the change. We only have
4382 * to worry about when we steal the irq-posted for
4385 wake_up_process(b
->irq_wait
->tsk
);
4386 spin_unlock_irq(&b
->irq_lock
);
4388 if (__i915_gem_request_completed(req
, seqno
))
4395 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4396 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4398 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4399 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4400 * perform the operation. To check beforehand, pass in the parameters to
4401 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4402 * you only need to pass in the minor offsets, page-aligned pointers are
4405 * For just checking for SSE4.1, in the foreknowledge that the future use
4406 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4408 #define i915_can_memcpy_from_wc(dst, src, len) \
4409 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4411 #define i915_has_memcpy_from_wc() \
4412 i915_memcpy_from_wc(NULL, NULL, 0)
4415 int remap_io_mapping(struct vm_area_struct
*vma
,
4416 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4417 struct io_mapping
*iomap
);
4419 static inline int intel_hws_csb_write_index(struct drm_i915_private
*i915
)
4421 if (INTEL_GEN(i915
) >= 10)
4422 return CNL_HWS_CSB_WRITE_INDEX
;
4424 return I915_HWS_CSB_WRITE_INDEX
;