2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
88 #include <linux/log2.h>
90 #include <drm/i915_drm.h>
92 #include "i915_trace.h"
94 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
96 /* Initial size (as log2) to preallocate the handle->object hashtable */
97 #define VMA_HT_BITS 2u /* 4 x 2 pointers, 64 bytes minimum */
99 static void resize_vma_ht(struct work_struct
*work
)
101 struct i915_gem_context_vma_lut
*lut
=
102 container_of(work
, typeof(*lut
), resize
);
103 unsigned int bits
, new_bits
, size
, i
;
104 struct hlist_head
*new_ht
;
106 GEM_BUG_ON(!(lut
->ht_size
& I915_CTX_RESIZE_IN_PROGRESS
));
108 bits
= 1 + ilog2(4*lut
->ht_count
/3 + 1);
109 new_bits
= min_t(unsigned int,
110 max(bits
, VMA_HT_BITS
),
111 sizeof(unsigned int) * BITS_PER_BYTE
- 1);
112 if (new_bits
== lut
->ht_bits
)
115 new_ht
= kzalloc(sizeof(*new_ht
)<<new_bits
, GFP_KERNEL
| __GFP_NOWARN
);
117 new_ht
= vzalloc(sizeof(*new_ht
)<<new_bits
);
119 /* Pretend resize succeeded and stop calling us for a bit! */
122 size
= BIT(lut
->ht_bits
);
123 for (i
= 0; i
< size
; i
++) {
124 struct i915_vma
*vma
;
125 struct hlist_node
*tmp
;
127 hlist_for_each_entry_safe(vma
, tmp
, &lut
->ht
[i
], ctx_node
)
128 hlist_add_head(&vma
->ctx_node
,
129 &new_ht
[hash_32(vma
->ctx_handle
,
134 lut
->ht_bits
= new_bits
;
136 smp_store_release(&lut
->ht_size
, BIT(bits
));
137 GEM_BUG_ON(lut
->ht_size
& I915_CTX_RESIZE_IN_PROGRESS
);
140 static void vma_lut_free(struct i915_gem_context
*ctx
)
142 struct i915_gem_context_vma_lut
*lut
= &ctx
->vma_lut
;
143 unsigned int i
, size
;
145 if (lut
->ht_size
& I915_CTX_RESIZE_IN_PROGRESS
)
146 cancel_work_sync(&lut
->resize
);
148 size
= BIT(lut
->ht_bits
);
149 for (i
= 0; i
< size
; i
++) {
150 struct i915_vma
*vma
;
152 hlist_for_each_entry(vma
, &lut
->ht
[i
], ctx_node
) {
153 vma
->obj
->vma_hashed
= NULL
;
161 void i915_gem_context_free(struct kref
*ctx_ref
)
163 struct i915_gem_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
166 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
167 trace_i915_context_free(ctx
);
168 GEM_BUG_ON(!i915_gem_context_is_closed(ctx
));
171 i915_ppgtt_put(ctx
->ppgtt
);
173 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
174 struct intel_context
*ce
= &ctx
->engine
[i
];
179 WARN_ON(ce
->pin_count
);
181 intel_ring_free(ce
->ring
);
183 __i915_gem_object_release_unless_active(ce
->state
->obj
);
189 list_del(&ctx
->link
);
191 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
195 static void context_close(struct i915_gem_context
*ctx
)
197 i915_gem_context_set_closed(ctx
);
199 i915_ppgtt_close(&ctx
->ppgtt
->base
);
200 ctx
->file_priv
= ERR_PTR(-EBADF
);
201 i915_gem_context_put(ctx
);
204 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
208 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
209 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
211 /* Contexts are only released when no longer active.
212 * Flush any pending retires to hopefully release some
213 * stale contexts and try again.
215 i915_gem_retire_requests(dev_priv
);
216 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
217 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
226 static u32
default_desc_template(const struct drm_i915_private
*i915
,
227 const struct i915_hw_ppgtt
*ppgtt
)
232 desc
= GEN8_CTX_VALID
| GEN8_CTX_PRIVILEGE
;
234 address_mode
= INTEL_LEGACY_32B_CONTEXT
;
235 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
))
236 address_mode
= INTEL_LEGACY_64B_CONTEXT
;
237 desc
|= address_mode
<< GEN8_CTX_ADDRESSING_MODE_SHIFT
;
240 desc
|= GEN8_CTX_L3LLC_COHERENT
;
242 /* TODO: WaDisableLiteRestore when we start using semaphore
243 * signalling between Command Streamers
244 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
250 static struct i915_gem_context
*
251 __create_hw_context(struct drm_i915_private
*dev_priv
,
252 struct drm_i915_file_private
*file_priv
)
254 struct i915_gem_context
*ctx
;
257 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
259 return ERR_PTR(-ENOMEM
);
261 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
267 kref_init(&ctx
->ref
);
268 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
269 ctx
->i915
= dev_priv
;
270 ctx
->priority
= I915_PRIORITY_NORMAL
;
272 ctx
->vma_lut
.ht_bits
= VMA_HT_BITS
;
273 ctx
->vma_lut
.ht_size
= BIT(VMA_HT_BITS
);
274 BUILD_BUG_ON(BIT(VMA_HT_BITS
) == I915_CTX_RESIZE_IN_PROGRESS
);
275 ctx
->vma_lut
.ht
= kcalloc(ctx
->vma_lut
.ht_size
,
276 sizeof(*ctx
->vma_lut
.ht
),
278 if (!ctx
->vma_lut
.ht
)
281 INIT_WORK(&ctx
->vma_lut
.resize
, resize_vma_ht
);
283 /* Default context will never have a file_priv */
284 ret
= DEFAULT_CONTEXT_HANDLE
;
286 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
287 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
291 ctx
->user_handle
= ret
;
293 ctx
->file_priv
= file_priv
;
295 ctx
->pid
= get_task_pid(current
, PIDTYPE_PID
);
296 ctx
->name
= kasprintf(GFP_KERNEL
, "%s[%d]/%x",
306 /* NB: Mark all slices as needing a remap so that when the context first
307 * loads it will restore whatever remap state already exists. If there
308 * is no remap info, it will be a NOP. */
309 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
311 i915_gem_context_set_bannable(ctx
);
312 ctx
->ring_size
= 4 * PAGE_SIZE
;
314 default_desc_template(dev_priv
, dev_priv
->mm
.aliasing_ppgtt
);
316 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
317 * present or not in use we still need a small bias as ring wraparound
318 * at offset 0 sometimes hangs. No idea why.
320 if (HAS_GUC(dev_priv
) && i915
.enable_guc_loading
)
321 ctx
->ggtt_offset_bias
= GUC_WOPCM_TOP
;
323 ctx
->ggtt_offset_bias
= I915_GTT_PAGE_SIZE
;
329 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
331 kvfree(ctx
->vma_lut
.ht
);
337 static void __destroy_hw_context(struct i915_gem_context
*ctx
,
338 struct drm_i915_file_private
*file_priv
)
340 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
345 * The default context needs to exist per ring that uses contexts. It stores the
346 * context state of the GPU for applications that don't utilize HW contexts, as
347 * well as an idle case.
349 static struct i915_gem_context
*
350 i915_gem_create_context(struct drm_i915_private
*dev_priv
,
351 struct drm_i915_file_private
*file_priv
)
353 struct i915_gem_context
*ctx
;
355 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
357 ctx
= __create_hw_context(dev_priv
, file_priv
);
361 if (USES_FULL_PPGTT(dev_priv
)) {
362 struct i915_hw_ppgtt
*ppgtt
;
364 ppgtt
= i915_ppgtt_create(dev_priv
, file_priv
, ctx
->name
);
366 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
368 __destroy_hw_context(ctx
, file_priv
);
369 return ERR_CAST(ppgtt
);
373 ctx
->desc_template
= default_desc_template(dev_priv
, ppgtt
);
376 trace_i915_context_create(ctx
);
382 * i915_gem_context_create_gvt - create a GVT GEM context
385 * This function is used to create a GVT specific GEM context.
388 * pointer to i915_gem_context on success, error pointer if failed
391 struct i915_gem_context
*
392 i915_gem_context_create_gvt(struct drm_device
*dev
)
394 struct i915_gem_context
*ctx
;
397 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
398 return ERR_PTR(-ENODEV
);
400 ret
= i915_mutex_lock_interruptible(dev
);
404 ctx
= __create_hw_context(to_i915(dev
), NULL
);
408 ctx
->file_priv
= ERR_PTR(-EBADF
);
409 i915_gem_context_set_closed(ctx
); /* not user accessible */
410 i915_gem_context_clear_bannable(ctx
);
411 i915_gem_context_set_force_single_submission(ctx
);
412 if (!i915
.enable_guc_submission
)
413 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
415 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
417 mutex_unlock(&dev
->struct_mutex
);
421 int i915_gem_context_init(struct drm_i915_private
*dev_priv
)
423 struct i915_gem_context
*ctx
;
425 /* Init should only be called once per module load. Eventually the
426 * restriction on the context_disabled check can be loosened. */
427 if (WARN_ON(dev_priv
->kernel_context
))
430 if (intel_vgpu_active(dev_priv
) &&
431 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
432 if (!i915
.enable_execlists
) {
433 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
438 /* Using the simple ida interface, the max is limited by sizeof(int) */
439 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
440 ida_init(&dev_priv
->context_hw_ida
);
442 ctx
= i915_gem_create_context(dev_priv
, NULL
);
444 DRM_ERROR("Failed to create default global context (error %ld)\n",
449 /* For easy recognisablity, we want the kernel context to be 0 and then
450 * all user contexts will have non-zero hw_id.
452 GEM_BUG_ON(ctx
->hw_id
);
454 i915_gem_context_clear_bannable(ctx
);
455 ctx
->priority
= I915_PRIORITY_MIN
; /* lowest priority; idle task */
456 dev_priv
->kernel_context
= ctx
;
458 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
460 DRM_DEBUG_DRIVER("%s context support initialized\n",
461 dev_priv
->engine
[RCS
]->context_size
? "logical" :
466 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
468 struct intel_engine_cs
*engine
;
469 enum intel_engine_id id
;
471 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
473 for_each_engine(engine
, dev_priv
, id
) {
474 engine
->legacy_active_context
= NULL
;
476 if (!engine
->last_retired_context
)
479 engine
->context_unpin(engine
, engine
->last_retired_context
);
480 engine
->last_retired_context
= NULL
;
483 /* Force the GPU state to be restored on enabling */
484 if (!i915
.enable_execlists
) {
485 struct i915_gem_context
*ctx
;
487 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
488 if (!i915_gem_context_is_default(ctx
))
491 for_each_engine(engine
, dev_priv
, id
)
492 ctx
->engine
[engine
->id
].initialised
= false;
494 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
497 for_each_engine(engine
, dev_priv
, id
) {
498 struct intel_context
*kce
=
499 &dev_priv
->kernel_context
->engine
[engine
->id
];
501 kce
->initialised
= true;
506 void i915_gem_context_fini(struct drm_i915_private
*dev_priv
)
508 struct i915_gem_context
*dctx
= dev_priv
->kernel_context
;
510 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
512 GEM_BUG_ON(!i915_gem_context_is_kernel(dctx
));
515 dev_priv
->kernel_context
= NULL
;
517 ida_destroy(&dev_priv
->context_hw_ida
);
520 static int context_idr_cleanup(int id
, void *p
, void *data
)
522 struct i915_gem_context
*ctx
= p
;
528 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
530 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
531 struct i915_gem_context
*ctx
;
533 idr_init(&file_priv
->context_idr
);
535 mutex_lock(&dev
->struct_mutex
);
536 ctx
= i915_gem_create_context(to_i915(dev
), file_priv
);
537 mutex_unlock(&dev
->struct_mutex
);
539 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
542 idr_destroy(&file_priv
->context_idr
);
549 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
551 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
553 lockdep_assert_held(&dev
->struct_mutex
);
555 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
556 idr_destroy(&file_priv
->context_idr
);
560 mi_set_context(struct drm_i915_gem_request
*req
, u32 flags
)
562 struct drm_i915_private
*dev_priv
= req
->i915
;
563 struct intel_engine_cs
*engine
= req
->engine
;
564 enum intel_engine_id id
;
565 const int num_rings
=
566 /* Use an extended w/a on gen7 if signalling from other rings */
567 (i915
.semaphores
&& INTEL_GEN(dev_priv
) == 7) ?
568 INTEL_INFO(dev_priv
)->num_rings
- 1 :
573 flags
|= MI_MM_SPACE_GTT
;
574 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
575 /* These flags are for resource streamer on HSW+ */
576 flags
|= HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
;
578 flags
|= MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
;
581 if (INTEL_GEN(dev_priv
) >= 7)
582 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
584 cs
= intel_ring_begin(req
, len
);
588 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
589 if (INTEL_GEN(dev_priv
) >= 7) {
590 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
592 struct intel_engine_cs
*signaller
;
594 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
595 for_each_engine(signaller
, dev_priv
, id
) {
596 if (signaller
== engine
)
599 *cs
++ = i915_mmio_reg_offset(
600 RING_PSMI_CTL(signaller
->mmio_base
));
601 *cs
++ = _MASKED_BIT_ENABLE(
602 GEN6_PSMI_SLEEP_MSG_DISABLE
);
608 *cs
++ = MI_SET_CONTEXT
;
609 *cs
++ = i915_ggtt_offset(req
->ctx
->engine
[RCS
].state
) | flags
;
611 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
612 * WaMiSetContext_Hang:snb,ivb,vlv
616 if (INTEL_GEN(dev_priv
) >= 7) {
618 struct intel_engine_cs
*signaller
;
619 i915_reg_t last_reg
= {}; /* keep gcc quiet */
621 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
622 for_each_engine(signaller
, dev_priv
, id
) {
623 if (signaller
== engine
)
626 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
627 *cs
++ = i915_mmio_reg_offset(last_reg
);
628 *cs
++ = _MASKED_BIT_DISABLE(
629 GEN6_PSMI_SLEEP_MSG_DISABLE
);
632 /* Insert a delay before the next switch! */
633 *cs
++ = MI_STORE_REGISTER_MEM
| MI_SRM_LRM_GLOBAL_GTT
;
634 *cs
++ = i915_mmio_reg_offset(last_reg
);
635 *cs
++ = i915_ggtt_offset(engine
->scratch
);
638 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
641 intel_ring_advance(req
, cs
);
646 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
648 u32
*cs
, *remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
654 cs
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
659 * Note: We do not worry about the concurrent register cacheline hang
660 * here because no other code should access these registers other than
661 * at initialization time.
663 *cs
++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4);
664 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
665 *cs
++ = i915_mmio_reg_offset(GEN7_L3LOG(slice
, i
));
666 *cs
++ = remap_info
[i
];
669 intel_ring_advance(req
, cs
);
674 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
675 struct intel_engine_cs
*engine
,
676 struct i915_gem_context
*to
)
681 if (!to
->engine
[RCS
].initialised
)
684 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
687 return to
== engine
->legacy_active_context
;
691 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
, struct intel_engine_cs
*engine
)
693 struct i915_gem_context
*from
= engine
->legacy_active_context
;
698 /* Always load the ppgtt on first use */
702 /* Same context without new entries, skip */
703 if ((!from
->ppgtt
|| from
->ppgtt
== ppgtt
) &&
704 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
707 if (engine
->id
!= RCS
)
710 if (INTEL_GEN(engine
->i915
) < 8)
717 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
718 struct i915_gem_context
*to
,
724 if (!IS_GEN8(to
->i915
))
727 if (hw_flags
& MI_RESTORE_INHIBIT
)
733 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
735 struct i915_gem_context
*to
= req
->ctx
;
736 struct intel_engine_cs
*engine
= req
->engine
;
737 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
738 struct i915_gem_context
*from
= engine
->legacy_active_context
;
742 GEM_BUG_ON(engine
->id
!= RCS
);
744 if (skip_rcs_switch(ppgtt
, engine
, to
))
747 if (needs_pd_load_pre(ppgtt
, engine
)) {
748 /* Older GENs and non render rings still want the load first,
749 * "PP_DCLV followed by PP_DIR_BASE register through Load
750 * Register Immediate commands in Ring Buffer before submitting
752 trace_switch_mm(engine
, to
);
753 ret
= ppgtt
->switch_mm(ppgtt
, req
);
758 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
759 /* NB: If we inhibit the restore, the context is not allowed to
760 * die because future work may end up depending on valid address
761 * space. This means we must enforce that a page table load
762 * occur when this occurs. */
763 hw_flags
= MI_RESTORE_INHIBIT
;
764 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
765 hw_flags
= MI_FORCE_RESTORE
;
769 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
770 ret
= mi_set_context(req
, hw_flags
);
774 engine
->legacy_active_context
= to
;
777 /* GEN8 does *not* require an explicit reload if the PDPs have been
778 * setup, and we do not wish to move them.
780 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
781 trace_switch_mm(engine
, to
);
782 ret
= ppgtt
->switch_mm(ppgtt
, req
);
783 /* The hardware context switch is emitted, but we haven't
784 * actually changed the state - so it's probably safe to bail
785 * here. Still, let the user know something dangerous has
793 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
795 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
796 if (!(to
->remap_slice
& (1<<i
)))
799 ret
= remap_l3(req
, i
);
803 to
->remap_slice
&= ~(1<<i
);
806 if (!to
->engine
[RCS
].initialised
) {
807 if (engine
->init_context
) {
808 ret
= engine
->init_context(req
);
812 to
->engine
[RCS
].initialised
= true;
819 * i915_switch_context() - perform a GPU context switch.
820 * @req: request for which we'll execute the context switch
822 * The context life cycle is simple. The context refcount is incremented and
823 * decremented by 1 and create and destroy. If the context is in use by the GPU,
824 * it will have a refcount > 1. This allows us to destroy the context abstract
825 * object while letting the normal object tracking destroy the backing BO.
827 * This function should not be used in execlists mode. Instead the context is
828 * switched by writing to the ELSP and requests keep a reference to their
831 int i915_switch_context(struct drm_i915_gem_request
*req
)
833 struct intel_engine_cs
*engine
= req
->engine
;
835 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
836 if (i915
.enable_execlists
)
839 if (!req
->ctx
->engine
[engine
->id
].state
) {
840 struct i915_gem_context
*to
= req
->ctx
;
841 struct i915_hw_ppgtt
*ppgtt
=
842 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
844 if (needs_pd_load_pre(ppgtt
, engine
)) {
847 trace_switch_mm(engine
, to
);
848 ret
= ppgtt
->switch_mm(ppgtt
, req
);
852 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
855 engine
->legacy_active_context
= to
;
859 return do_rcs_switch(req
);
862 static bool engine_has_kernel_context(struct intel_engine_cs
*engine
)
864 struct i915_gem_timeline
*timeline
;
866 list_for_each_entry(timeline
, &engine
->i915
->gt
.timelines
, link
) {
867 struct intel_timeline
*tl
;
869 if (timeline
== &engine
->i915
->gt
.global_timeline
)
872 tl
= &timeline
->engine
[engine
->id
];
873 if (i915_gem_active_peek(&tl
->last_request
,
874 &engine
->i915
->drm
.struct_mutex
))
878 return (!engine
->last_retired_context
||
879 i915_gem_context_is_kernel(engine
->last_retired_context
));
882 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
884 struct intel_engine_cs
*engine
;
885 struct i915_gem_timeline
*timeline
;
886 enum intel_engine_id id
;
888 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
890 i915_gem_retire_requests(dev_priv
);
892 for_each_engine(engine
, dev_priv
, id
) {
893 struct drm_i915_gem_request
*req
;
896 if (engine_has_kernel_context(engine
))
899 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
903 /* Queue this switch after all other activity */
904 list_for_each_entry(timeline
, &dev_priv
->gt
.timelines
, link
) {
905 struct drm_i915_gem_request
*prev
;
906 struct intel_timeline
*tl
;
908 tl
= &timeline
->engine
[engine
->id
];
909 prev
= i915_gem_active_raw(&tl
->last_request
,
910 &dev_priv
->drm
.struct_mutex
);
912 i915_sw_fence_await_sw_fence_gfp(&req
->submit
,
917 ret
= i915_switch_context(req
);
918 i915_add_request(req
);
926 static bool client_is_banned(struct drm_i915_file_private
*file_priv
)
928 return file_priv
->context_bans
> I915_MAX_CLIENT_CONTEXT_BANS
;
931 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
932 struct drm_file
*file
)
934 struct drm_i915_private
*dev_priv
= to_i915(dev
);
935 struct drm_i915_gem_context_create
*args
= data
;
936 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
937 struct i915_gem_context
*ctx
;
940 if (!dev_priv
->engine
[RCS
]->context_size
)
946 if (client_is_banned(file_priv
)) {
947 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
949 pid_nr(get_task_pid(current
, PIDTYPE_PID
)));
954 ret
= i915_mutex_lock_interruptible(dev
);
958 ctx
= i915_gem_create_context(dev_priv
, file_priv
);
959 mutex_unlock(&dev
->struct_mutex
);
963 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
965 args
->ctx_id
= ctx
->user_handle
;
966 DRM_DEBUG("HW context %d created\n", args
->ctx_id
);
971 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
972 struct drm_file
*file
)
974 struct drm_i915_gem_context_destroy
*args
= data
;
975 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
976 struct i915_gem_context
*ctx
;
982 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
985 ret
= i915_mutex_lock_interruptible(dev
);
989 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
991 mutex_unlock(&dev
->struct_mutex
);
995 __destroy_hw_context(ctx
, file_priv
);
996 mutex_unlock(&dev
->struct_mutex
);
998 DRM_DEBUG("HW context %d destroyed\n", args
->ctx_id
);
1002 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1003 struct drm_file
*file
)
1005 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1006 struct drm_i915_gem_context_param
*args
= data
;
1007 struct i915_gem_context
*ctx
;
1010 ret
= i915_mutex_lock_interruptible(dev
);
1014 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1016 mutex_unlock(&dev
->struct_mutex
);
1017 return PTR_ERR(ctx
);
1021 switch (args
->param
) {
1022 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1025 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1026 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1028 case I915_CONTEXT_PARAM_GTT_SIZE
:
1030 args
->value
= ctx
->ppgtt
->base
.total
;
1031 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1032 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1034 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1036 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1037 args
->value
= i915_gem_context_no_error_capture(ctx
);
1039 case I915_CONTEXT_PARAM_BANNABLE
:
1040 args
->value
= i915_gem_context_is_bannable(ctx
);
1046 mutex_unlock(&dev
->struct_mutex
);
1051 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1052 struct drm_file
*file
)
1054 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1055 struct drm_i915_gem_context_param
*args
= data
;
1056 struct i915_gem_context
*ctx
;
1059 ret
= i915_mutex_lock_interruptible(dev
);
1063 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1065 mutex_unlock(&dev
->struct_mutex
);
1066 return PTR_ERR(ctx
);
1069 switch (args
->param
) {
1070 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1073 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1077 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1078 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1081 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1084 else if (args
->value
)
1085 i915_gem_context_set_no_error_capture(ctx
);
1087 i915_gem_context_clear_no_error_capture(ctx
);
1089 case I915_CONTEXT_PARAM_BANNABLE
:
1092 else if (!capable(CAP_SYS_ADMIN
) && !args
->value
)
1094 else if (args
->value
)
1095 i915_gem_context_set_bannable(ctx
);
1097 i915_gem_context_clear_bannable(ctx
);
1103 mutex_unlock(&dev
->struct_mutex
);
1108 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1109 void *data
, struct drm_file
*file
)
1111 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1112 struct drm_i915_reset_stats
*args
= data
;
1113 struct i915_gem_context
*ctx
;
1116 if (args
->flags
|| args
->pad
)
1119 ret
= i915_mutex_lock_interruptible(dev
);
1123 ctx
= i915_gem_context_lookup(file
->driver_priv
, args
->ctx_id
);
1125 mutex_unlock(&dev
->struct_mutex
);
1126 return PTR_ERR(ctx
);
1129 if (capable(CAP_SYS_ADMIN
))
1130 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1132 args
->reset_count
= 0;
1134 args
->batch_active
= ctx
->guilty_count
;
1135 args
->batch_pending
= ctx
->active_count
;
1137 mutex_unlock(&dev
->struct_mutex
);
1142 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1143 #include "selftests/mock_context.c"
1144 #include "selftests/i915_gem_context.c"