2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
196 const enum i915_cache_level level
)
198 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
200 if (level
!= I915_CACHE_NONE
)
201 pde
|= PPAT_CACHED_PDE_INDEX
;
203 pde
|= PPAT_UNCACHED_INDEX
;
207 #define gen8_pdpe_encode gen8_pde_encode
208 #define gen8_pml4e_encode gen8_pde_encode
210 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
211 enum i915_cache_level level
,
212 bool valid
, u32 unused
)
214 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
215 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
218 case I915_CACHE_L3_LLC
:
220 pte
|= GEN6_PTE_CACHE_LLC
;
222 case I915_CACHE_NONE
:
223 pte
|= GEN6_PTE_UNCACHED
;
232 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
233 enum i915_cache_level level
,
234 bool valid
, u32 unused
)
236 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
237 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
240 case I915_CACHE_L3_LLC
:
241 pte
|= GEN7_PTE_CACHE_L3_LLC
;
244 pte
|= GEN6_PTE_CACHE_LLC
;
246 case I915_CACHE_NONE
:
247 pte
|= GEN6_PTE_UNCACHED
;
256 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
257 enum i915_cache_level level
,
258 bool valid
, u32 flags
)
260 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
261 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
263 if (!(flags
& PTE_READ_ONLY
))
264 pte
|= BYT_PTE_WRITEABLE
;
266 if (level
!= I915_CACHE_NONE
)
267 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
272 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
273 enum i915_cache_level level
,
274 bool valid
, u32 unused
)
276 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
277 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
279 if (level
!= I915_CACHE_NONE
)
280 pte
|= HSW_WB_LLC_AGE3
;
285 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
286 enum i915_cache_level level
,
287 bool valid
, u32 unused
)
289 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
290 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
293 case I915_CACHE_NONE
:
296 pte
|= HSW_WT_ELLC_LLC_AGE3
;
299 pte
|= HSW_WB_ELLC_LLC_AGE3
;
306 static int __setup_page_dma(struct drm_device
*dev
,
307 struct i915_page_dma
*p
, gfp_t flags
)
309 struct device
*device
= &dev
->pdev
->dev
;
311 p
->page
= alloc_page(flags
);
315 p
->daddr
= dma_map_page(device
,
316 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
318 if (dma_mapping_error(device
, p
->daddr
)) {
319 __free_page(p
->page
);
326 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
328 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
331 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
333 if (WARN_ON(!p
->page
))
336 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
337 __free_page(p
->page
);
338 memset(p
, 0, sizeof(*p
));
341 static void *kmap_page_dma(struct i915_page_dma
*p
)
343 return kmap_atomic(p
->page
);
346 /* We use the flushing unmap only with ppgtt structures:
347 * page directories, page tables and scratch pages.
349 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
351 /* There are only few exceptions for gen >=6. chv and bxt.
352 * And we are not sure about the latter so play safe for now.
354 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
355 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
357 kunmap_atomic(vaddr
);
360 #define kmap_px(px) kmap_page_dma(px_base(px))
361 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
363 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
364 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
365 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
366 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
368 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
372 uint64_t * const vaddr
= kmap_page_dma(p
);
374 for (i
= 0; i
< 512; i
++)
377 kunmap_page_dma(dev
, vaddr
);
380 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
381 const uint32_t val32
)
387 fill_page_dma(dev
, p
, v
);
390 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
392 struct i915_page_scratch
*sp
;
395 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
397 return ERR_PTR(-ENOMEM
);
399 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
405 set_pages_uc(px_page(sp
), 1);
410 static void free_scratch_page(struct drm_device
*dev
,
411 struct i915_page_scratch
*sp
)
413 set_pages_wb(px_page(sp
), 1);
419 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
421 struct i915_page_table
*pt
;
422 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
423 GEN8_PTES
: GEN6_PTES
;
426 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
428 return ERR_PTR(-ENOMEM
);
430 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
436 ret
= setup_px(dev
, pt
);
443 kfree(pt
->used_ptes
);
450 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
453 kfree(pt
->used_ptes
);
457 static void gen8_initialize_pt(struct i915_address_space
*vm
,
458 struct i915_page_table
*pt
)
460 gen8_pte_t scratch_pte
;
462 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
463 I915_CACHE_LLC
, true);
465 fill_px(vm
->dev
, pt
, scratch_pte
);
468 static void gen6_initialize_pt(struct i915_address_space
*vm
,
469 struct i915_page_table
*pt
)
471 gen6_pte_t scratch_pte
;
473 WARN_ON(px_dma(vm
->scratch_page
) == 0);
475 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
476 I915_CACHE_LLC
, true, 0);
478 fill32_px(vm
->dev
, pt
, scratch_pte
);
481 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
483 struct i915_page_directory
*pd
;
486 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
488 return ERR_PTR(-ENOMEM
);
490 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
491 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
495 ret
= setup_px(dev
, pd
);
502 kfree(pd
->used_pdes
);
509 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
513 kfree(pd
->used_pdes
);
518 static void gen8_initialize_pd(struct i915_address_space
*vm
,
519 struct i915_page_directory
*pd
)
521 gen8_pde_t scratch_pde
;
523 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
525 fill_px(vm
->dev
, pd
, scratch_pde
);
528 static int __pdp_init(struct drm_device
*dev
,
529 struct i915_page_directory_pointer
*pdp
)
531 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
533 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
534 sizeof(unsigned long),
536 if (!pdp
->used_pdpes
)
539 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
541 if (!pdp
->page_directory
) {
542 kfree(pdp
->used_pdpes
);
543 /* the PDP might be the statically allocated top level. Keep it
544 * as clean as possible */
545 pdp
->used_pdpes
= NULL
;
552 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
554 kfree(pdp
->used_pdpes
);
555 kfree(pdp
->page_directory
);
556 pdp
->page_directory
= NULL
;
560 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
562 struct i915_page_directory_pointer
*pdp
;
565 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
567 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
569 return ERR_PTR(-ENOMEM
);
571 ret
= __pdp_init(dev
, pdp
);
575 ret
= setup_px(dev
, pdp
);
589 static void free_pdp(struct drm_device
*dev
,
590 struct i915_page_directory_pointer
*pdp
)
593 if (USES_FULL_48BIT_PPGTT(dev
)) {
594 cleanup_px(dev
, pdp
);
600 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
601 struct i915_page_directory_pointer
*pdp
,
602 struct i915_page_directory
*pd
,
605 gen8_ppgtt_pdpe_t
*page_directorypo
;
607 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
610 page_directorypo
= kmap_px(pdp
);
611 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
612 kunmap_px(ppgtt
, page_directorypo
);
616 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
617 struct i915_pml4
*pml4
,
618 struct i915_page_directory_pointer
*pdp
,
621 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
623 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
624 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
625 kunmap_px(ppgtt
, pagemap
);
628 /* Broadwell Page Directory Pointer Descriptors */
629 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
633 struct intel_engine_cs
*ring
= req
->ring
;
638 ret
= intel_ring_begin(req
, 6);
642 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
643 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
644 intel_ring_emit(ring
, upper_32_bits(addr
));
645 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
646 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
647 intel_ring_emit(ring
, lower_32_bits(addr
));
648 intel_ring_advance(ring
);
653 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
654 struct drm_i915_gem_request
*req
)
658 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
659 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
661 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
669 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
670 struct i915_page_directory_pointer
*pdp
,
673 gen8_pte_t scratch_pte
)
675 struct i915_hw_ppgtt
*ppgtt
=
676 container_of(vm
, struct i915_hw_ppgtt
, base
);
677 gen8_pte_t
*pt_vaddr
;
678 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
679 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
680 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
681 unsigned num_entries
= length
>> PAGE_SHIFT
;
682 unsigned last_pte
, i
;
687 while (num_entries
) {
688 struct i915_page_directory
*pd
;
689 struct i915_page_table
*pt
;
691 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
694 pd
= pdp
->page_directory
[pdpe
];
696 if (WARN_ON(!pd
->page_table
[pde
]))
699 pt
= pd
->page_table
[pde
];
701 if (WARN_ON(!px_page(pt
)))
704 last_pte
= pte
+ num_entries
;
705 if (last_pte
> GEN8_PTES
)
706 last_pte
= GEN8_PTES
;
708 pt_vaddr
= kmap_px(pt
);
710 for (i
= pte
; i
< last_pte
; i
++) {
711 pt_vaddr
[i
] = scratch_pte
;
715 kunmap_px(ppgtt
, pt
);
718 if (++pde
== I915_PDES
) {
725 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
730 struct i915_hw_ppgtt
*ppgtt
=
731 container_of(vm
, struct i915_hw_ppgtt
, base
);
732 struct i915_page_directory_pointer
*pdp
= &ppgtt
->pdp
; /* FIXME: 48b */
734 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
735 I915_CACHE_LLC
, use_scratch
);
737 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
, scratch_pte
);
741 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
742 struct i915_page_directory_pointer
*pdp
,
743 struct sg_table
*pages
,
745 enum i915_cache_level cache_level
)
747 struct i915_hw_ppgtt
*ppgtt
=
748 container_of(vm
, struct i915_hw_ppgtt
, base
);
749 gen8_pte_t
*pt_vaddr
;
750 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
751 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
752 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
753 struct sg_page_iter sg_iter
;
757 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
758 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
761 if (pt_vaddr
== NULL
) {
762 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
763 struct i915_page_table
*pt
= pd
->page_table
[pde
];
764 pt_vaddr
= kmap_px(pt
);
768 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
770 if (++pte
== GEN8_PTES
) {
771 kunmap_px(ppgtt
, pt_vaddr
);
773 if (++pde
== I915_PDES
) {
782 kunmap_px(ppgtt
, pt_vaddr
);
785 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
786 struct sg_table
*pages
,
788 enum i915_cache_level cache_level
,
791 struct i915_hw_ppgtt
*ppgtt
=
792 container_of(vm
, struct i915_hw_ppgtt
, base
);
793 struct i915_page_directory_pointer
*pdp
= &ppgtt
->pdp
; /* FIXME: 48b */
795 gen8_ppgtt_insert_pte_entries(vm
, pdp
, pages
, start
, cache_level
);
798 static void gen8_free_page_tables(struct drm_device
*dev
,
799 struct i915_page_directory
*pd
)
806 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
807 if (WARN_ON(!pd
->page_table
[i
]))
810 free_pt(dev
, pd
->page_table
[i
]);
811 pd
->page_table
[i
] = NULL
;
815 static int gen8_init_scratch(struct i915_address_space
*vm
)
817 struct drm_device
*dev
= vm
->dev
;
819 vm
->scratch_page
= alloc_scratch_page(dev
);
820 if (IS_ERR(vm
->scratch_page
))
821 return PTR_ERR(vm
->scratch_page
);
823 vm
->scratch_pt
= alloc_pt(dev
);
824 if (IS_ERR(vm
->scratch_pt
)) {
825 free_scratch_page(dev
, vm
->scratch_page
);
826 return PTR_ERR(vm
->scratch_pt
);
829 vm
->scratch_pd
= alloc_pd(dev
);
830 if (IS_ERR(vm
->scratch_pd
)) {
831 free_pt(dev
, vm
->scratch_pt
);
832 free_scratch_page(dev
, vm
->scratch_page
);
833 return PTR_ERR(vm
->scratch_pd
);
836 gen8_initialize_pt(vm
, vm
->scratch_pt
);
837 gen8_initialize_pd(vm
, vm
->scratch_pd
);
842 static void gen8_free_scratch(struct i915_address_space
*vm
)
844 struct drm_device
*dev
= vm
->dev
;
846 free_pd(dev
, vm
->scratch_pd
);
847 free_pt(dev
, vm
->scratch_pt
);
848 free_scratch_page(dev
, vm
->scratch_page
);
851 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
852 struct i915_page_directory_pointer
*pdp
)
856 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
857 if (WARN_ON(!pdp
->page_directory
[i
]))
860 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
861 free_pd(dev
, pdp
->page_directory
[i
]);
867 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
871 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
872 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
875 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
878 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
881 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
883 struct i915_hw_ppgtt
*ppgtt
=
884 container_of(vm
, struct i915_hw_ppgtt
, base
);
886 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
887 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
889 gen8_ppgtt_cleanup_4lvl(ppgtt
);
891 gen8_free_scratch(vm
);
895 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
896 * @vm: Master vm structure.
897 * @pd: Page directory for this address range.
898 * @start: Starting virtual address to begin allocations.
899 * @length: Size of the allocations.
900 * @new_pts: Bitmap set by function with new allocations. Likely used by the
901 * caller to free on error.
903 * Allocate the required number of page tables. Extremely similar to
904 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
905 * the page directory boundary (instead of the page directory pointer). That
906 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
907 * possible, and likely that the caller will need to use multiple calls of this
908 * function to achieve the appropriate allocation.
910 * Return: 0 if success; negative error code otherwise.
912 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
913 struct i915_page_directory
*pd
,
916 unsigned long *new_pts
)
918 struct drm_device
*dev
= vm
->dev
;
919 struct i915_page_table
*pt
;
923 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
924 /* Don't reallocate page tables */
925 if (test_bit(pde
, pd
->used_pdes
)) {
926 /* Scratch is never allocated this way */
927 WARN_ON(pt
== vm
->scratch_pt
);
935 gen8_initialize_pt(vm
, pt
);
936 pd
->page_table
[pde
] = pt
;
937 __set_bit(pde
, new_pts
);
938 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
944 for_each_set_bit(pde
, new_pts
, I915_PDES
)
945 free_pt(dev
, pd
->page_table
[pde
]);
951 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
952 * @vm: Master vm structure.
953 * @pdp: Page directory pointer for this address range.
954 * @start: Starting virtual address to begin allocations.
955 * @length: Size of the allocations.
956 * @new_pds: Bitmap set by function with new allocations. Likely used by the
957 * caller to free on error.
959 * Allocate the required number of page directories starting at the pde index of
960 * @start, and ending at the pde index @start + @length. This function will skip
961 * over already allocated page directories within the range, and only allocate
962 * new ones, setting the appropriate pointer within the pdp as well as the
963 * correct position in the bitmap @new_pds.
965 * The function will only allocate the pages within the range for a give page
966 * directory pointer. In other words, if @start + @length straddles a virtually
967 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
968 * required by the caller, This is not currently possible, and the BUG in the
969 * code will prevent it.
971 * Return: 0 if success; negative error code otherwise.
974 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
975 struct i915_page_directory_pointer
*pdp
,
978 unsigned long *new_pds
)
980 struct drm_device
*dev
= vm
->dev
;
981 struct i915_page_directory
*pd
;
984 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
986 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
988 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
989 if (test_bit(pdpe
, pdp
->used_pdpes
))
996 gen8_initialize_pd(vm
, pd
);
997 pdp
->page_directory
[pdpe
] = pd
;
998 __set_bit(pdpe
, new_pds
);
999 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1005 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1006 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1012 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1013 * @vm: Master vm structure.
1014 * @pml4: Page map level 4 for this address range.
1015 * @start: Starting virtual address to begin allocations.
1016 * @length: Size of the allocations.
1017 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1018 * caller to free on error.
1020 * Allocate the required number of page directory pointers. Extremely similar to
1021 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1022 * The main difference is here we are limited by the pml4 boundary (instead of
1023 * the page directory pointer).
1025 * Return: 0 if success; negative error code otherwise.
1028 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1029 struct i915_pml4
*pml4
,
1032 unsigned long *new_pdps
)
1034 struct drm_device
*dev
= vm
->dev
;
1035 struct i915_page_directory_pointer
*pdp
;
1039 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1041 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1042 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1043 pdp
= alloc_pdp(dev
);
1047 pml4
->pdps
[pml4e
] = pdp
;
1048 __set_bit(pml4e
, new_pdps
);
1049 trace_i915_page_directory_pointer_entry_alloc(vm
,
1059 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1060 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1066 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
,
1071 for (i
= 0; i
< pdpes
; i
++)
1077 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1078 * of these are based on the number of PDPEs in the system.
1081 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1082 unsigned long ***new_pts
,
1087 unsigned long **pts
;
1089 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_KERNEL
);
1093 pts
= kcalloc(pdpes
, sizeof(unsigned long *), GFP_KERNEL
);
1099 for (i
= 0; i
< pdpes
; i
++) {
1100 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
1101 sizeof(unsigned long), GFP_KERNEL
);
1112 free_gen8_temp_bitmaps(pds
, pts
, pdpes
);
1116 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1117 * the page table structures, we mark them dirty so that
1118 * context switching/execlist queuing code takes extra steps
1119 * to ensure that tlbs are flushed.
1121 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1123 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1126 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1127 struct i915_page_directory_pointer
*pdp
,
1131 struct i915_hw_ppgtt
*ppgtt
=
1132 container_of(vm
, struct i915_hw_ppgtt
, base
);
1133 unsigned long *new_page_dirs
, **new_page_tables
;
1134 struct drm_device
*dev
= vm
->dev
;
1135 struct i915_page_directory
*pd
;
1136 const uint64_t orig_start
= start
;
1137 const uint64_t orig_length
= length
;
1140 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1143 /* Wrap is never okay since we can only represent 48b, and we don't
1144 * actually use the other side of the canonical address space.
1146 if (WARN_ON(start
+ length
< start
))
1149 if (WARN_ON(start
+ length
> vm
->total
))
1152 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1156 /* Do the allocations first so we can easily bail out */
1157 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1160 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1164 /* For every page directory referenced, allocate page tables */
1165 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1166 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1167 new_page_tables
[pdpe
]);
1173 length
= orig_length
;
1175 /* Allocations have completed successfully, so set the bitmaps, and do
1177 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
1178 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1179 struct i915_page_table
*pt
;
1180 uint64_t pd_len
= length
;
1181 uint64_t pd_start
= start
;
1184 /* Every pd should be allocated, we just did that above. */
1187 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1188 /* Same reasoning as pd */
1191 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1193 /* Set our used ptes within the page table */
1194 bitmap_set(pt
->used_ptes
,
1195 gen8_pte_index(pd_start
),
1196 gen8_pte_count(pd_start
, pd_len
));
1198 /* Our pde is now pointing to the pagetable, pt */
1199 __set_bit(pde
, pd
->used_pdes
);
1201 /* Map the PDE to the page table */
1202 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1204 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1205 gen8_pte_index(start
),
1206 gen8_pte_count(start
, length
),
1209 /* NB: We haven't yet mapped ptes to pages. At this
1210 * point we're still relying on insert_entries() */
1213 kunmap_px(ppgtt
, page_directory
);
1214 __set_bit(pdpe
, pdp
->used_pdpes
);
1215 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1218 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1219 mark_tlbs_dirty(ppgtt
);
1224 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
1225 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1228 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1229 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1231 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1232 mark_tlbs_dirty(ppgtt
);
1236 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1237 struct i915_pml4
*pml4
,
1241 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1242 struct i915_hw_ppgtt
*ppgtt
=
1243 container_of(vm
, struct i915_hw_ppgtt
, base
);
1244 struct i915_page_directory_pointer
*pdp
;
1245 uint64_t temp
, pml4e
;
1248 /* Do the pml4 allocations first, so we don't need to track the newly
1249 * allocated tables below the pdp */
1250 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1252 /* The pagedirectory and pagetable allocations are done in the shared 3
1253 * and 4 level code. Just allocate the pdps.
1255 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1260 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1261 "The allocation has spanned more than 512GB. "
1262 "It is highly likely this is incorrect.");
1264 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, temp
, pml4e
) {
1267 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1271 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1274 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1275 GEN8_PML4ES_PER_PML4
);
1280 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1281 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1286 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1287 uint64_t start
, uint64_t length
)
1289 struct i915_hw_ppgtt
*ppgtt
=
1290 container_of(vm
, struct i915_hw_ppgtt
, base
);
1292 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1293 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1295 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1299 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1300 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1301 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1305 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1309 ret
= gen8_init_scratch(&ppgtt
->base
);
1313 ppgtt
->base
.start
= 0;
1314 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1315 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1316 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1317 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1318 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1319 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1321 ppgtt
->switch_mm
= gen8_mm_switch
;
1323 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1324 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1328 ppgtt
->base
.total
= 1ULL << 48;
1330 ret
= __pdp_init(false, &ppgtt
->pdp
);
1334 ppgtt
->base
.total
= 1ULL << 32;
1335 if (IS_ENABLED(CONFIG_X86_32
))
1336 /* While we have a proliferation of size_t variables
1337 * we cannot represent the full ppgtt size on 32bit,
1338 * so limit it to the same size as the GGTT (currently
1341 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
1343 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1351 gen8_free_scratch(&ppgtt
->base
);
1355 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1357 struct i915_address_space
*vm
= &ppgtt
->base
;
1358 struct i915_page_table
*unused
;
1359 gen6_pte_t scratch_pte
;
1361 uint32_t pte
, pde
, temp
;
1362 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1364 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1365 I915_CACHE_LLC
, true, 0);
1367 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1369 gen6_pte_t
*pt_vaddr
;
1370 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1371 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1372 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1374 if (pd_entry
!= expected
)
1375 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1379 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1381 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1383 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1385 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1389 for (i
= 0; i
< 4; i
++)
1390 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1395 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1396 for (i
= 0; i
< 4; i
++) {
1397 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1398 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1400 seq_puts(m
, " SCRATCH ");
1404 kunmap_px(ppgtt
, pt_vaddr
);
1408 /* Write pde (index) from the page directory @pd to the page table @pt */
1409 static void gen6_write_pde(struct i915_page_directory
*pd
,
1410 const int pde
, struct i915_page_table
*pt
)
1412 /* Caller needs to make sure the write completes if necessary */
1413 struct i915_hw_ppgtt
*ppgtt
=
1414 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1417 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1418 pd_entry
|= GEN6_PDE_VALID
;
1420 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1423 /* Write all the page tables found in the ppgtt structure to incrementing page
1425 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1426 struct i915_page_directory
*pd
,
1427 uint32_t start
, uint32_t length
)
1429 struct i915_page_table
*pt
;
1432 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1433 gen6_write_pde(pd
, pde
, pt
);
1435 /* Make sure write is complete before other code can use this page
1436 * table. Also require for WC mapped PTEs */
1437 readl(dev_priv
->gtt
.gsm
);
1440 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1442 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1444 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1447 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1448 struct drm_i915_gem_request
*req
)
1450 struct intel_engine_cs
*ring
= req
->ring
;
1453 /* NB: TLBs must be flushed and invalidated before a switch */
1454 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1458 ret
= intel_ring_begin(req
, 6);
1462 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1463 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1464 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1465 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1466 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1467 intel_ring_emit(ring
, MI_NOOP
);
1468 intel_ring_advance(ring
);
1473 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1474 struct drm_i915_gem_request
*req
)
1476 struct intel_engine_cs
*ring
= req
->ring
;
1477 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1479 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1480 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1484 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1485 struct drm_i915_gem_request
*req
)
1487 struct intel_engine_cs
*ring
= req
->ring
;
1490 /* NB: TLBs must be flushed and invalidated before a switch */
1491 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1495 ret
= intel_ring_begin(req
, 6);
1499 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1500 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1501 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1502 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1503 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1504 intel_ring_emit(ring
, MI_NOOP
);
1505 intel_ring_advance(ring
);
1507 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1508 if (ring
->id
!= RCS
) {
1509 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1517 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1518 struct drm_i915_gem_request
*req
)
1520 struct intel_engine_cs
*ring
= req
->ring
;
1521 struct drm_device
*dev
= ppgtt
->base
.dev
;
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1525 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1526 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1528 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1533 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 struct intel_engine_cs
*ring
;
1539 for_each_ring(ring
, dev_priv
, j
) {
1540 I915_WRITE(RING_MODE_GEN7(ring
),
1541 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1545 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1548 struct intel_engine_cs
*ring
;
1549 uint32_t ecochk
, ecobits
;
1552 ecobits
= I915_READ(GAC_ECO_BITS
);
1553 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1555 ecochk
= I915_READ(GAM_ECOCHK
);
1556 if (IS_HASWELL(dev
)) {
1557 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1559 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1560 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1562 I915_WRITE(GAM_ECOCHK
, ecochk
);
1564 for_each_ring(ring
, dev_priv
, i
) {
1565 /* GFX_MODE is per-ring on gen7+ */
1566 I915_WRITE(RING_MODE_GEN7(ring
),
1567 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1571 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1574 uint32_t ecochk
, gab_ctl
, ecobits
;
1576 ecobits
= I915_READ(GAC_ECO_BITS
);
1577 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1578 ECOBITS_PPGTT_CACHE64B
);
1580 gab_ctl
= I915_READ(GAB_CTL
);
1581 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1583 ecochk
= I915_READ(GAM_ECOCHK
);
1584 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1586 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1589 /* PPGTT support for Sandybdrige/Gen6 and later */
1590 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1595 struct i915_hw_ppgtt
*ppgtt
=
1596 container_of(vm
, struct i915_hw_ppgtt
, base
);
1597 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1598 unsigned first_entry
= start
>> PAGE_SHIFT
;
1599 unsigned num_entries
= length
>> PAGE_SHIFT
;
1600 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1601 unsigned first_pte
= first_entry
% GEN6_PTES
;
1602 unsigned last_pte
, i
;
1604 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1605 I915_CACHE_LLC
, true, 0);
1607 while (num_entries
) {
1608 last_pte
= first_pte
+ num_entries
;
1609 if (last_pte
> GEN6_PTES
)
1610 last_pte
= GEN6_PTES
;
1612 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1614 for (i
= first_pte
; i
< last_pte
; i
++)
1615 pt_vaddr
[i
] = scratch_pte
;
1617 kunmap_px(ppgtt
, pt_vaddr
);
1619 num_entries
-= last_pte
- first_pte
;
1625 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1626 struct sg_table
*pages
,
1628 enum i915_cache_level cache_level
, u32 flags
)
1630 struct i915_hw_ppgtt
*ppgtt
=
1631 container_of(vm
, struct i915_hw_ppgtt
, base
);
1632 gen6_pte_t
*pt_vaddr
;
1633 unsigned first_entry
= start
>> PAGE_SHIFT
;
1634 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1635 unsigned act_pte
= first_entry
% GEN6_PTES
;
1636 struct sg_page_iter sg_iter
;
1639 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1640 if (pt_vaddr
== NULL
)
1641 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1644 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1645 cache_level
, true, flags
);
1647 if (++act_pte
== GEN6_PTES
) {
1648 kunmap_px(ppgtt
, pt_vaddr
);
1655 kunmap_px(ppgtt
, pt_vaddr
);
1658 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1659 uint64_t start_in
, uint64_t length_in
)
1661 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1662 struct drm_device
*dev
= vm
->dev
;
1663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1664 struct i915_hw_ppgtt
*ppgtt
=
1665 container_of(vm
, struct i915_hw_ppgtt
, base
);
1666 struct i915_page_table
*pt
;
1667 uint32_t start
, length
, start_save
, length_save
;
1671 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1674 start
= start_save
= start_in
;
1675 length
= length_save
= length_in
;
1677 bitmap_zero(new_page_tables
, I915_PDES
);
1679 /* The allocation is done in two stages so that we can bail out with
1680 * minimal amount of pain. The first stage finds new page tables that
1681 * need allocation. The second stage marks use ptes within the page
1684 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1685 if (pt
!= vm
->scratch_pt
) {
1686 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1690 /* We've already allocated a page table */
1691 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1699 gen6_initialize_pt(vm
, pt
);
1701 ppgtt
->pd
.page_table
[pde
] = pt
;
1702 __set_bit(pde
, new_page_tables
);
1703 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1707 length
= length_save
;
1709 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1710 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1712 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1713 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1714 gen6_pte_count(start
, length
));
1716 if (__test_and_clear_bit(pde
, new_page_tables
))
1717 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1719 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1720 gen6_pte_index(start
),
1721 gen6_pte_count(start
, length
),
1723 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1727 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1729 /* Make sure write is complete before other code can use this page
1730 * table. Also require for WC mapped PTEs */
1731 readl(dev_priv
->gtt
.gsm
);
1733 mark_tlbs_dirty(ppgtt
);
1737 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1738 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1740 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1741 free_pt(vm
->dev
, pt
);
1744 mark_tlbs_dirty(ppgtt
);
1748 static int gen6_init_scratch(struct i915_address_space
*vm
)
1750 struct drm_device
*dev
= vm
->dev
;
1752 vm
->scratch_page
= alloc_scratch_page(dev
);
1753 if (IS_ERR(vm
->scratch_page
))
1754 return PTR_ERR(vm
->scratch_page
);
1756 vm
->scratch_pt
= alloc_pt(dev
);
1757 if (IS_ERR(vm
->scratch_pt
)) {
1758 free_scratch_page(dev
, vm
->scratch_page
);
1759 return PTR_ERR(vm
->scratch_pt
);
1762 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1767 static void gen6_free_scratch(struct i915_address_space
*vm
)
1769 struct drm_device
*dev
= vm
->dev
;
1771 free_pt(dev
, vm
->scratch_pt
);
1772 free_scratch_page(dev
, vm
->scratch_page
);
1775 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1777 struct i915_hw_ppgtt
*ppgtt
=
1778 container_of(vm
, struct i915_hw_ppgtt
, base
);
1779 struct i915_page_table
*pt
;
1782 drm_mm_remove_node(&ppgtt
->node
);
1784 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1785 if (pt
!= vm
->scratch_pt
)
1786 free_pt(ppgtt
->base
.dev
, pt
);
1789 gen6_free_scratch(vm
);
1792 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1794 struct i915_address_space
*vm
= &ppgtt
->base
;
1795 struct drm_device
*dev
= ppgtt
->base
.dev
;
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1797 bool retried
= false;
1800 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1801 * allocator works in address space sizes, so it's multiplied by page
1802 * size. We allocate at the top of the GTT to avoid fragmentation.
1804 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1806 ret
= gen6_init_scratch(vm
);
1811 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1812 &ppgtt
->node
, GEN6_PD_SIZE
,
1814 0, dev_priv
->gtt
.base
.total
,
1816 if (ret
== -ENOSPC
&& !retried
) {
1817 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1818 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1820 0, dev_priv
->gtt
.base
.total
,
1833 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1834 DRM_DEBUG("Forced to use aperture for PDEs\n");
1839 gen6_free_scratch(vm
);
1843 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1845 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1848 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1849 uint64_t start
, uint64_t length
)
1851 struct i915_page_table
*unused
;
1854 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1855 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
1858 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1860 struct drm_device
*dev
= ppgtt
->base
.dev
;
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1866 ppgtt
->switch_mm
= gen6_mm_switch
;
1867 } else if (IS_HASWELL(dev
)) {
1868 ppgtt
->switch_mm
= hsw_mm_switch
;
1869 } else if (IS_GEN7(dev
)) {
1870 ppgtt
->switch_mm
= gen7_mm_switch
;
1874 if (intel_vgpu_active(dev
))
1875 ppgtt
->switch_mm
= vgpu_mm_switch
;
1877 ret
= gen6_ppgtt_alloc(ppgtt
);
1881 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1882 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1883 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1884 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1885 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1886 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1887 ppgtt
->base
.start
= 0;
1888 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1889 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1891 ppgtt
->pd
.base
.ggtt_offset
=
1892 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1894 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1895 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1897 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1899 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1901 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1902 ppgtt
->node
.size
>> 20,
1903 ppgtt
->node
.start
/ PAGE_SIZE
);
1905 DRM_DEBUG("Adding PPGTT at offset %x\n",
1906 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1911 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1913 ppgtt
->base
.dev
= dev
;
1915 if (INTEL_INFO(dev
)->gen
< 8)
1916 return gen6_ppgtt_init(ppgtt
);
1918 return gen8_ppgtt_init(ppgtt
);
1921 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1926 ret
= __hw_ppgtt_init(dev
, ppgtt
);
1928 kref_init(&ppgtt
->ref
);
1929 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1931 i915_init_vm(dev_priv
, &ppgtt
->base
);
1937 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1939 /* In the case of execlists, PPGTT is enabled by the context descriptor
1940 * and the PDPs are contained within the context itself. We don't
1941 * need to do anything here. */
1942 if (i915
.enable_execlists
)
1945 if (!USES_PPGTT(dev
))
1949 gen6_ppgtt_enable(dev
);
1950 else if (IS_GEN7(dev
))
1951 gen7_ppgtt_enable(dev
);
1952 else if (INTEL_INFO(dev
)->gen
>= 8)
1953 gen8_ppgtt_enable(dev
);
1955 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1960 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1962 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1963 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1965 if (i915
.enable_execlists
)
1971 return ppgtt
->switch_mm(ppgtt
, req
);
1974 struct i915_hw_ppgtt
*
1975 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1977 struct i915_hw_ppgtt
*ppgtt
;
1980 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1982 return ERR_PTR(-ENOMEM
);
1984 ret
= i915_ppgtt_init(dev
, ppgtt
);
1987 return ERR_PTR(ret
);
1990 ppgtt
->file_priv
= fpriv
;
1992 trace_i915_ppgtt_create(&ppgtt
->base
);
1997 void i915_ppgtt_release(struct kref
*kref
)
1999 struct i915_hw_ppgtt
*ppgtt
=
2000 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2002 trace_i915_ppgtt_release(&ppgtt
->base
);
2004 /* vmas should already be unbound */
2005 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2006 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2008 list_del(&ppgtt
->base
.global_link
);
2009 drm_mm_takedown(&ppgtt
->base
.mm
);
2011 ppgtt
->base
.cleanup(&ppgtt
->base
);
2015 extern int intel_iommu_gfx_mapped
;
2016 /* Certain Gen5 chipsets require require idling the GPU before
2017 * unmapping anything from the GTT when VT-d is enabled.
2019 static bool needs_idle_maps(struct drm_device
*dev
)
2021 #ifdef CONFIG_INTEL_IOMMU
2022 /* Query intel_iommu to see if we need the workaround. Presumably that
2025 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
2031 static bool do_idling(struct drm_i915_private
*dev_priv
)
2033 bool ret
= dev_priv
->mm
.interruptible
;
2035 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
2036 dev_priv
->mm
.interruptible
= false;
2037 if (i915_gpu_idle(dev_priv
->dev
)) {
2038 DRM_ERROR("Couldn't idle GPU\n");
2039 /* Wait a bit, in hopes it avoids the hang */
2047 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
2049 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2050 dev_priv
->mm
.interruptible
= interruptible
;
2053 void i915_check_and_clear_faults(struct drm_device
*dev
)
2055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2056 struct intel_engine_cs
*ring
;
2059 if (INTEL_INFO(dev
)->gen
< 6)
2062 for_each_ring(ring
, dev_priv
, i
) {
2064 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
2065 if (fault_reg
& RING_FAULT_VALID
) {
2066 DRM_DEBUG_DRIVER("Unexpected fault\n"
2068 "\tAddress space: %s\n"
2071 fault_reg
& PAGE_MASK
,
2072 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2073 RING_FAULT_SRCID(fault_reg
),
2074 RING_FAULT_FAULT_TYPE(fault_reg
));
2075 I915_WRITE(RING_FAULT_REG(ring
),
2076 fault_reg
& ~RING_FAULT_VALID
);
2079 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
2082 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2084 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
2085 intel_gtt_chipset_flush();
2087 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2088 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2092 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2096 /* Don't bother messing with faults pre GEN6 as we have little
2097 * documentation supporting that it's a good idea.
2099 if (INTEL_INFO(dev
)->gen
< 6)
2102 i915_check_and_clear_faults(dev
);
2104 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2105 dev_priv
->gtt
.base
.start
,
2106 dev_priv
->gtt
.base
.total
,
2109 i915_ggtt_flush(dev_priv
);
2112 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2114 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2115 obj
->pages
->sgl
, obj
->pages
->nents
,
2116 PCI_DMA_BIDIRECTIONAL
))
2122 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2127 iowrite32((u32
)pte
, addr
);
2128 iowrite32(pte
>> 32, addr
+ 4);
2132 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2133 struct sg_table
*st
,
2135 enum i915_cache_level level
, u32 unused
)
2137 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2138 unsigned first_entry
= start
>> PAGE_SHIFT
;
2139 gen8_pte_t __iomem
*gtt_entries
=
2140 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2142 struct sg_page_iter sg_iter
;
2143 dma_addr_t addr
= 0; /* shut up gcc */
2145 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2146 addr
= sg_dma_address(sg_iter
.sg
) +
2147 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
2148 gen8_set_pte(>t_entries
[i
],
2149 gen8_pte_encode(addr
, level
, true));
2154 * XXX: This serves as a posting read to make sure that the PTE has
2155 * actually been updated. There is some concern that even though
2156 * registers and PTEs are within the same BAR that they are potentially
2157 * of NUMA access patterns. Therefore, even with the way we assume
2158 * hardware should work, we must keep this posting read for paranoia.
2161 WARN_ON(readq(>t_entries
[i
-1])
2162 != gen8_pte_encode(addr
, level
, true));
2164 /* This next bit makes the above posting read even more important. We
2165 * want to flush the TLBs only after we're certain all the PTE updates
2168 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2169 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2173 * Binds an object into the global gtt with the specified cache level. The object
2174 * will be accessible to the GPU via commands whose operands reference offsets
2175 * within the global GTT as well as accessible by the GPU through the GMADR
2176 * mapped BAR (dev_priv->mm.gtt->gtt).
2178 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2179 struct sg_table
*st
,
2181 enum i915_cache_level level
, u32 flags
)
2183 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2184 unsigned first_entry
= start
>> PAGE_SHIFT
;
2185 gen6_pte_t __iomem
*gtt_entries
=
2186 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
2188 struct sg_page_iter sg_iter
;
2189 dma_addr_t addr
= 0;
2191 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2192 addr
= sg_page_iter_dma_address(&sg_iter
);
2193 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
2197 /* XXX: This serves as a posting read to make sure that the PTE has
2198 * actually been updated. There is some concern that even though
2199 * registers and PTEs are within the same BAR that they are potentially
2200 * of NUMA access patterns. Therefore, even with the way we assume
2201 * hardware should work, we must keep this posting read for paranoia.
2204 unsigned long gtt
= readl(>t_entries
[i
-1]);
2205 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
2208 /* This next bit makes the above posting read even more important. We
2209 * want to flush the TLBs only after we're certain all the PTE updates
2212 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2213 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2216 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2221 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2222 unsigned first_entry
= start
>> PAGE_SHIFT
;
2223 unsigned num_entries
= length
>> PAGE_SHIFT
;
2224 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2225 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2226 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2229 if (WARN(num_entries
> max_entries
,
2230 "First entry = %d; Num entries = %d (max=%d)\n",
2231 first_entry
, num_entries
, max_entries
))
2232 num_entries
= max_entries
;
2234 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2237 for (i
= 0; i
< num_entries
; i
++)
2238 gen8_set_pte(>t_base
[i
], scratch_pte
);
2242 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2247 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2248 unsigned first_entry
= start
>> PAGE_SHIFT
;
2249 unsigned num_entries
= length
>> PAGE_SHIFT
;
2250 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2251 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
2252 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
2255 if (WARN(num_entries
> max_entries
,
2256 "First entry = %d; Num entries = %d (max=%d)\n",
2257 first_entry
, num_entries
, max_entries
))
2258 num_entries
= max_entries
;
2260 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2261 I915_CACHE_LLC
, use_scratch
, 0);
2263 for (i
= 0; i
< num_entries
; i
++)
2264 iowrite32(scratch_pte
, >t_base
[i
]);
2268 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2269 struct sg_table
*pages
,
2271 enum i915_cache_level cache_level
, u32 unused
)
2273 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2274 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2276 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2280 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2285 unsigned first_entry
= start
>> PAGE_SHIFT
;
2286 unsigned num_entries
= length
>> PAGE_SHIFT
;
2287 intel_gtt_clear_range(first_entry
, num_entries
);
2290 static int ggtt_bind_vma(struct i915_vma
*vma
,
2291 enum i915_cache_level cache_level
,
2294 struct drm_device
*dev
= vma
->vm
->dev
;
2295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2296 struct drm_i915_gem_object
*obj
= vma
->obj
;
2297 struct sg_table
*pages
= obj
->pages
;
2301 ret
= i915_get_ggtt_vma_pages(vma
);
2304 pages
= vma
->ggtt_view
.pages
;
2306 /* Currently applicable only to VLV */
2308 pte_flags
|= PTE_READ_ONLY
;
2311 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
2312 vma
->vm
->insert_entries(vma
->vm
, pages
,
2314 cache_level
, pte_flags
);
2316 /* Note the inconsistency here is due to absence of the
2317 * aliasing ppgtt on gen4 and earlier. Though we always
2318 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2319 * without the appgtt, we cannot honour that request and so
2320 * must substitute it with a global binding. Since we do this
2321 * behind the upper layers back, we need to explicitly set
2322 * the bound flag ourselves.
2324 vma
->bound
|= GLOBAL_BIND
;
2328 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
2329 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2330 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2332 cache_level
, pte_flags
);
2338 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2340 struct drm_device
*dev
= vma
->vm
->dev
;
2341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 struct drm_i915_gem_object
*obj
= vma
->obj
;
2343 const uint64_t size
= min_t(uint64_t,
2347 if (vma
->bound
& GLOBAL_BIND
) {
2348 vma
->vm
->clear_range(vma
->vm
,
2354 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2355 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2357 appgtt
->base
.clear_range(&appgtt
->base
,
2364 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2366 struct drm_device
*dev
= obj
->base
.dev
;
2367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2370 interruptible
= do_idling(dev_priv
);
2372 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2373 PCI_DMA_BIDIRECTIONAL
);
2375 undo_idling(dev_priv
, interruptible
);
2378 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2379 unsigned long color
,
2383 if (node
->color
!= color
)
2386 if (!list_empty(&node
->node_list
)) {
2387 node
= list_entry(node
->node_list
.next
,
2390 if (node
->allocated
&& node
->color
!= color
)
2395 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2396 unsigned long start
,
2397 unsigned long mappable_end
,
2400 /* Let GEM Manage all of the aperture.
2402 * However, leave one page at the end still bound to the scratch page.
2403 * There are a number of places where the hardware apparently prefetches
2404 * past the end of the object, and we've seen multiple hangs with the
2405 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2406 * aperture. One page should be enough to keep any prefetching inside
2409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2410 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2411 struct drm_mm_node
*entry
;
2412 struct drm_i915_gem_object
*obj
;
2413 unsigned long hole_start
, hole_end
;
2416 BUG_ON(mappable_end
> end
);
2418 /* Subtract the guard page ... */
2419 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2421 dev_priv
->gtt
.base
.start
= start
;
2422 dev_priv
->gtt
.base
.total
= end
- start
;
2424 if (intel_vgpu_active(dev
)) {
2425 ret
= intel_vgt_balloon(dev
);
2431 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2433 /* Mark any preallocated objects as occupied */
2434 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2435 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2437 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2438 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2440 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2441 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2443 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2446 vma
->bound
|= GLOBAL_BIND
;
2449 /* Clear any non-preallocated blocks */
2450 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2451 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2452 hole_start
, hole_end
);
2453 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2454 hole_end
- hole_start
, true);
2457 /* And finally clear the reserved guard page */
2458 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2460 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2461 struct i915_hw_ppgtt
*ppgtt
;
2463 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2467 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2469 ppgtt
->base
.cleanup(&ppgtt
->base
);
2474 if (ppgtt
->base
.allocate_va_range
)
2475 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2478 ppgtt
->base
.cleanup(&ppgtt
->base
);
2483 ppgtt
->base
.clear_range(&ppgtt
->base
,
2488 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2494 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2497 u64 gtt_size
, mappable_size
;
2499 gtt_size
= dev_priv
->gtt
.base
.total
;
2500 mappable_size
= dev_priv
->gtt
.mappable_end
;
2502 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2505 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2508 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2510 if (dev_priv
->mm
.aliasing_ppgtt
) {
2511 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2513 ppgtt
->base
.cleanup(&ppgtt
->base
);
2516 if (drm_mm_initialized(&vm
->mm
)) {
2517 if (intel_vgpu_active(dev
))
2518 intel_vgt_deballoon();
2520 drm_mm_takedown(&vm
->mm
);
2521 list_del(&vm
->global_link
);
2527 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2529 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2530 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2531 return snb_gmch_ctl
<< 20;
2534 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2536 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2537 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2539 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2541 #ifdef CONFIG_X86_32
2542 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2543 if (bdw_gmch_ctl
> 4)
2547 return bdw_gmch_ctl
<< 20;
2550 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2552 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2553 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2556 return 1 << (20 + gmch_ctrl
);
2561 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2563 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2564 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2565 return snb_gmch_ctl
<< 25; /* 32 MB units */
2568 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2570 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2571 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2572 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2575 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2577 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2578 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2581 * 0x0 to 0x10: 32MB increments starting at 0MB
2582 * 0x11 to 0x16: 4MB increments starting at 8MB
2583 * 0x17 to 0x1d: 4MB increments start at 36MB
2585 if (gmch_ctrl
< 0x11)
2586 return gmch_ctrl
<< 25;
2587 else if (gmch_ctrl
< 0x17)
2588 return (gmch_ctrl
- 0x11 + 2) << 22;
2590 return (gmch_ctrl
- 0x17 + 9) << 22;
2593 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2595 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2596 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2598 if (gen9_gmch_ctl
< 0xf0)
2599 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2601 /* 4MB increments starting at 0xf0 for 4MB */
2602 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2605 static int ggtt_probe_common(struct drm_device
*dev
,
2608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2609 struct i915_page_scratch
*scratch_page
;
2610 phys_addr_t gtt_phys_addr
;
2612 /* For Modern GENs the PTEs and register space are split in the BAR */
2613 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2614 (pci_resource_len(dev
->pdev
, 0) / 2);
2617 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2618 * dropped. For WC mappings in general we have 64 byte burst writes
2619 * when the WC buffer is flushed, so we can't use it, but have to
2620 * resort to an uncached mapping. The WC issue is easily caught by the
2621 * readback check when writing GTT PTE entries.
2623 if (IS_BROXTON(dev
))
2624 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2626 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2627 if (!dev_priv
->gtt
.gsm
) {
2628 DRM_ERROR("Failed to map the gtt page table\n");
2632 scratch_page
= alloc_scratch_page(dev
);
2633 if (IS_ERR(scratch_page
)) {
2634 DRM_ERROR("Scratch setup failed\n");
2635 /* iounmap will also get called at remove, but meh */
2636 iounmap(dev_priv
->gtt
.gsm
);
2637 return PTR_ERR(scratch_page
);
2640 dev_priv
->gtt
.base
.scratch_page
= scratch_page
;
2645 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2646 * bits. When using advanced contexts each context stores its own PAT, but
2647 * writing this data shouldn't be harmful even in those cases. */
2648 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2652 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2653 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2654 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2655 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2656 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2657 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2658 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2659 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2661 if (!USES_PPGTT(dev_priv
->dev
))
2662 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2663 * so RTL will always use the value corresponding to
2665 * So let's disable cache for GGTT to avoid screen corruptions.
2666 * MOCS still can be used though.
2667 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2668 * before this patch, i.e. the same uncached + snooping access
2669 * like on gen6/7 seems to be in effect.
2670 * - So this just fixes blitter/render access. Again it looks
2671 * like it's not just uncached access, but uncached + snooping.
2672 * So we can still hold onto all our assumptions wrt cpu
2673 * clflushing on LLC machines.
2675 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2677 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2678 * write would work. */
2679 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2680 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2683 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2688 * Map WB on BDW to snooped on CHV.
2690 * Only the snoop bit has meaning for CHV, the rest is
2693 * The hardware will never snoop for certain types of accesses:
2694 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2695 * - PPGTT page tables
2696 * - some other special cycles
2698 * As with BDW, we also need to consider the following for GT accesses:
2699 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2700 * so RTL will always use the value corresponding to
2702 * Which means we must set the snoop bit in PAT entry 0
2703 * in order to keep the global status page working.
2705 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2709 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2710 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2711 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2712 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2714 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2715 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2718 static int gen8_gmch_probe(struct drm_device
*dev
,
2721 phys_addr_t
*mappable_base
,
2724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2729 /* TODO: We're not aware of mappable constraints on gen8 yet */
2730 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2731 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2733 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2734 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2736 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2738 if (INTEL_INFO(dev
)->gen
>= 9) {
2739 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2740 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2741 } else if (IS_CHERRYVIEW(dev
)) {
2742 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2743 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2745 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2746 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2749 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2751 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2752 chv_setup_private_ppat(dev_priv
);
2754 bdw_setup_private_ppat(dev_priv
);
2756 ret
= ggtt_probe_common(dev
, gtt_size
);
2758 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2759 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2760 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2761 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2766 static int gen6_gmch_probe(struct drm_device
*dev
,
2769 phys_addr_t
*mappable_base
,
2772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2773 unsigned int gtt_size
;
2777 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2778 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2780 /* 64/512MB is the current min/max we actually know of, but this is just
2781 * a coarse sanity check.
2783 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2784 DRM_ERROR("Unknown GMADR size (%llx)\n",
2785 dev_priv
->gtt
.mappable_end
);
2789 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2790 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2791 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2793 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2795 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2796 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2798 ret
= ggtt_probe_common(dev
, gtt_size
);
2800 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2801 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2802 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2803 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2808 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2811 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2814 free_scratch_page(vm
->dev
, vm
->scratch_page
);
2817 static int i915_gmch_probe(struct drm_device
*dev
,
2820 phys_addr_t
*mappable_base
,
2823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2826 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2828 DRM_ERROR("failed to set up gmch\n");
2832 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2834 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2835 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2836 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2837 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2838 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2840 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2841 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2846 static void i915_gmch_remove(struct i915_address_space
*vm
)
2848 intel_gmch_remove();
2851 int i915_gem_gtt_init(struct drm_device
*dev
)
2853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2854 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2857 if (INTEL_INFO(dev
)->gen
<= 5) {
2858 gtt
->gtt_probe
= i915_gmch_probe
;
2859 gtt
->base
.cleanup
= i915_gmch_remove
;
2860 } else if (INTEL_INFO(dev
)->gen
< 8) {
2861 gtt
->gtt_probe
= gen6_gmch_probe
;
2862 gtt
->base
.cleanup
= gen6_gmch_remove
;
2863 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2864 gtt
->base
.pte_encode
= iris_pte_encode
;
2865 else if (IS_HASWELL(dev
))
2866 gtt
->base
.pte_encode
= hsw_pte_encode
;
2867 else if (IS_VALLEYVIEW(dev
))
2868 gtt
->base
.pte_encode
= byt_pte_encode
;
2869 else if (INTEL_INFO(dev
)->gen
>= 7)
2870 gtt
->base
.pte_encode
= ivb_pte_encode
;
2872 gtt
->base
.pte_encode
= snb_pte_encode
;
2874 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2875 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2878 gtt
->base
.dev
= dev
;
2880 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2881 >t
->mappable_base
, >t
->mappable_end
);
2885 /* GMADR is the PCI mmio aperture into the global GTT. */
2886 DRM_INFO("Memory usable by graphics device = %lluM\n",
2887 gtt
->base
.total
>> 20);
2888 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
2889 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2890 #ifdef CONFIG_INTEL_IOMMU
2891 if (intel_iommu_gfx_mapped
)
2892 DRM_INFO("VT-d active for gfx access\n");
2895 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2896 * user's requested state against the hardware/driver capabilities. We
2897 * do this now so that we can print out any log messages once rather
2898 * than every time we check intel_enable_ppgtt().
2900 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2901 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2906 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2909 struct drm_i915_gem_object
*obj
;
2910 struct i915_address_space
*vm
;
2911 struct i915_vma
*vma
;
2914 i915_check_and_clear_faults(dev
);
2916 /* First fill our portion of the GTT with scratch pages */
2917 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2918 dev_priv
->gtt
.base
.start
,
2919 dev_priv
->gtt
.base
.total
,
2922 /* Cache flush objects bound into GGTT and rebind them. */
2923 vm
= &dev_priv
->gtt
.base
;
2924 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2926 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2930 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
2937 i915_gem_clflush_object(obj
, obj
->pin_display
);
2940 if (INTEL_INFO(dev
)->gen
>= 8) {
2941 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2942 chv_setup_private_ppat(dev_priv
);
2944 bdw_setup_private_ppat(dev_priv
);
2949 if (USES_PPGTT(dev
)) {
2950 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2951 /* TODO: Perhaps it shouldn't be gen6 specific */
2953 struct i915_hw_ppgtt
*ppgtt
=
2954 container_of(vm
, struct i915_hw_ppgtt
,
2957 if (i915_is_ggtt(vm
))
2958 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2960 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2961 0, ppgtt
->base
.total
);
2965 i915_ggtt_flush(dev_priv
);
2968 static struct i915_vma
*
2969 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2970 struct i915_address_space
*vm
,
2971 const struct i915_ggtt_view
*ggtt_view
)
2973 struct i915_vma
*vma
;
2975 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2976 return ERR_PTR(-EINVAL
);
2978 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
2980 return ERR_PTR(-ENOMEM
);
2982 INIT_LIST_HEAD(&vma
->vma_link
);
2983 INIT_LIST_HEAD(&vma
->mm_list
);
2984 INIT_LIST_HEAD(&vma
->exec_list
);
2988 if (i915_is_ggtt(vm
))
2989 vma
->ggtt_view
= *ggtt_view
;
2991 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2992 if (!i915_is_ggtt(vm
))
2993 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2999 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3000 struct i915_address_space
*vm
)
3002 struct i915_vma
*vma
;
3004 vma
= i915_gem_obj_to_vma(obj
, vm
);
3006 vma
= __i915_gem_vma_create(obj
, vm
,
3007 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3013 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3014 const struct i915_ggtt_view
*view
)
3016 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
3017 struct i915_vma
*vma
;
3020 return ERR_PTR(-EINVAL
);
3022 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3028 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
3035 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
3036 struct sg_table
*st
)
3038 unsigned int column
, row
;
3039 unsigned int src_idx
;
3040 struct scatterlist
*sg
= st
->sgl
;
3044 for (column
= 0; column
< width
; column
++) {
3045 src_idx
= width
* (height
- 1) + column
;
3046 for (row
= 0; row
< height
; row
++) {
3048 /* We don't need the pages, but need to initialize
3049 * the entries so the sg list can be happily traversed.
3050 * The only thing we need are DMA addresses.
3052 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3053 sg_dma_address(sg
) = in
[src_idx
];
3054 sg_dma_len(sg
) = PAGE_SIZE
;
3061 static struct sg_table
*
3062 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
3063 struct drm_i915_gem_object
*obj
)
3065 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
3066 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
3067 struct sg_page_iter sg_iter
;
3069 dma_addr_t
*page_addr_list
;
3070 struct sg_table
*st
;
3073 /* Allocate a temporary list of source pages for random access. */
3074 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
3075 sizeof(dma_addr_t
));
3076 if (!page_addr_list
)
3077 return ERR_PTR(ret
);
3079 /* Allocate target SG list. */
3080 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3084 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
3088 /* Populate source page list from the object. */
3090 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
3091 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
3095 /* Rotate the pages. */
3096 rotate_pages(page_addr_list
,
3097 rot_info
->width_pages
, rot_info
->height_pages
,
3101 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
3102 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
3103 rot_info
->pixel_format
, rot_info
->width_pages
,
3104 rot_info
->height_pages
, size_pages
);
3106 drm_free_large(page_addr_list
);
3113 drm_free_large(page_addr_list
);
3116 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
3117 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
3118 rot_info
->pixel_format
, rot_info
->width_pages
,
3119 rot_info
->height_pages
, size_pages
);
3120 return ERR_PTR(ret
);
3123 static struct sg_table
*
3124 intel_partial_pages(const struct i915_ggtt_view
*view
,
3125 struct drm_i915_gem_object
*obj
)
3127 struct sg_table
*st
;
3128 struct scatterlist
*sg
;
3129 struct sg_page_iter obj_sg_iter
;
3132 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3136 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3142 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3143 view
->params
.partial
.offset
)
3145 if (st
->nents
>= view
->params
.partial
.size
)
3148 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3149 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3150 sg_dma_len(sg
) = PAGE_SIZE
;
3161 return ERR_PTR(ret
);
3165 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3169 if (vma
->ggtt_view
.pages
)
3172 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3173 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3174 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3175 vma
->ggtt_view
.pages
=
3176 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
3177 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3178 vma
->ggtt_view
.pages
=
3179 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3181 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3182 vma
->ggtt_view
.type
);
3184 if (!vma
->ggtt_view
.pages
) {
3185 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3186 vma
->ggtt_view
.type
);
3188 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3189 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3190 vma
->ggtt_view
.pages
= NULL
;
3191 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3192 vma
->ggtt_view
.type
, ret
);
3199 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3201 * @cache_level: mapping cache level
3202 * @flags: flags like global or local mapping
3204 * DMA addresses are taken from the scatter-gather table of this object (or of
3205 * this VMA in case of non-default GGTT views) and PTE entries set up.
3206 * Note that DMA addresses are also the only part of the SG table we care about.
3208 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3214 if (WARN_ON(flags
== 0))
3218 if (flags
& PIN_GLOBAL
)
3219 bind_flags
|= GLOBAL_BIND
;
3220 if (flags
& PIN_USER
)
3221 bind_flags
|= LOCAL_BIND
;
3223 if (flags
& PIN_UPDATE
)
3224 bind_flags
|= vma
->bound
;
3226 bind_flags
&= ~vma
->bound
;
3228 if (bind_flags
== 0)
3231 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3232 trace_i915_va_alloc(vma
->vm
,
3235 VM_TO_TRACE_NAME(vma
->vm
));
3237 /* XXX: i915_vma_pin() will fix this +- hack */
3239 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3247 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3251 vma
->bound
|= bind_flags
;
3257 * i915_ggtt_view_size - Get the size of a GGTT view.
3258 * @obj: Object the view is of.
3259 * @view: The view in question.
3261 * @return The size of the GGTT view in bytes.
3264 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3265 const struct i915_ggtt_view
*view
)
3267 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3268 return obj
->base
.size
;
3269 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3270 return view
->rotation_info
.size
;
3271 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3272 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3274 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3275 return obj
->base
.size
;