1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
143 u32 val = I915_READ(reg); \
145 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
147 I915_WRITE((reg), 0xffffffff); \
149 I915_WRITE((reg), 0xffffffff); \
154 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
155 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
156 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
157 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
158 POSTING_READ(GEN8_##type##_IMR(which)); \
161 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
162 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
163 I915_WRITE(type##IER, (ier_val)); \
164 I915_WRITE(type##IMR, (imr_val)); \
165 POSTING_READ(type##IMR); \
168 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
170 /* For display hotplug interrupt */
172 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
178 assert_spin_locked(&dev_priv
->irq_lock
);
179 WARN_ON(bits
& ~mask
);
181 val
= I915_READ(PORT_HOTPLUG_EN
);
184 I915_WRITE(PORT_HOTPLUG_EN
, val
);
188 * i915_hotplug_interrupt_update - update hotplug interrupt enable
189 * @dev_priv: driver private
190 * @mask: bits to update
191 * @bits: bits to enable
192 * NOTE: the HPD enable bits are modified both inside and outside
193 * of an interrupt context. To avoid that read-modify-write cycles
194 * interfer, these bits are protected by a spinlock. Since this
195 * function is usually not called from a context where the lock is
196 * held already, this function acquires the lock itself. A non-locking
197 * version is also available.
199 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
203 spin_lock_irq(&dev_priv
->irq_lock
);
204 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
205 spin_unlock_irq(&dev_priv
->irq_lock
);
209 * ilk_update_display_irq - update DEIMR
210 * @dev_priv: driver private
211 * @interrupt_mask: mask of interrupt bits to update
212 * @enabled_irq_mask: mask of interrupt bits to enable
214 static void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
215 uint32_t interrupt_mask
,
216 uint32_t enabled_irq_mask
)
220 assert_spin_locked(&dev_priv
->irq_lock
);
222 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
224 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
227 new_val
= dev_priv
->irq_mask
;
228 new_val
&= ~interrupt_mask
;
229 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
231 if (new_val
!= dev_priv
->irq_mask
) {
232 dev_priv
->irq_mask
= new_val
;
233 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
239 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
241 ilk_update_display_irq(dev_priv
, mask
, mask
);
245 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
247 ilk_update_display_irq(dev_priv
, mask
, 0);
251 * ilk_update_gt_irq - update GTIMR
252 * @dev_priv: driver private
253 * @interrupt_mask: mask of interrupt bits to update
254 * @enabled_irq_mask: mask of interrupt bits to enable
256 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
257 uint32_t interrupt_mask
,
258 uint32_t enabled_irq_mask
)
260 assert_spin_locked(&dev_priv
->irq_lock
);
262 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
264 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
267 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
268 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
269 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
273 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
275 ilk_update_gt_irq(dev_priv
, mask
, mask
);
278 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
280 ilk_update_gt_irq(dev_priv
, mask
, 0);
283 static u32
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
285 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
288 static u32
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
290 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
293 static u32
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
295 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
299 * snb_update_pm_irq - update GEN6_PMIMR
300 * @dev_priv: driver private
301 * @interrupt_mask: mask of interrupt bits to update
302 * @enabled_irq_mask: mask of interrupt bits to enable
304 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
305 uint32_t interrupt_mask
,
306 uint32_t enabled_irq_mask
)
310 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
312 assert_spin_locked(&dev_priv
->irq_lock
);
314 new_val
= dev_priv
->pm_irq_mask
;
315 new_val
&= ~interrupt_mask
;
316 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
318 if (new_val
!= dev_priv
->pm_irq_mask
) {
319 dev_priv
->pm_irq_mask
= new_val
;
320 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
321 POSTING_READ(gen6_pm_imr(dev_priv
));
325 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
327 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
330 snb_update_pm_irq(dev_priv
, mask
, mask
);
333 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
336 snb_update_pm_irq(dev_priv
, mask
, 0);
339 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
341 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
344 __gen6_disable_pm_irq(dev_priv
, mask
);
347 void gen6_reset_rps_interrupts(struct drm_device
*dev
)
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
350 uint32_t reg
= gen6_pm_iir(dev_priv
);
352 spin_lock_irq(&dev_priv
->irq_lock
);
353 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
354 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
356 dev_priv
->rps
.pm_iir
= 0;
357 spin_unlock_irq(&dev_priv
->irq_lock
);
360 void gen6_enable_rps_interrupts(struct drm_device
*dev
)
362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
364 spin_lock_irq(&dev_priv
->irq_lock
);
366 WARN_ON(dev_priv
->rps
.pm_iir
);
367 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
368 dev_priv
->rps
.interrupts_enabled
= true;
369 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
370 dev_priv
->pm_rps_events
);
371 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
373 spin_unlock_irq(&dev_priv
->irq_lock
);
376 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
379 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
380 * if GEN6_PM_UP_EI_EXPIRED is masked.
382 * TODO: verify if this can be reproduced on VLV,CHV.
384 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
385 mask
&= ~GEN6_PM_RP_UP_EI_EXPIRED
;
387 if (INTEL_INFO(dev_priv
)->gen
>= 8)
388 mask
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
393 void gen6_disable_rps_interrupts(struct drm_device
*dev
)
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 spin_lock_irq(&dev_priv
->irq_lock
);
398 dev_priv
->rps
.interrupts_enabled
= false;
399 spin_unlock_irq(&dev_priv
->irq_lock
);
401 cancel_work_sync(&dev_priv
->rps
.work
);
403 spin_lock_irq(&dev_priv
->irq_lock
);
405 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
407 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
408 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
409 ~dev_priv
->pm_rps_events
);
411 spin_unlock_irq(&dev_priv
->irq_lock
);
413 synchronize_irq(dev
->irq
);
417 * bdw_update_port_irq - update DE port interrupt
418 * @dev_priv: driver private
419 * @interrupt_mask: mask of interrupt bits to update
420 * @enabled_irq_mask: mask of interrupt bits to enable
422 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
423 uint32_t interrupt_mask
,
424 uint32_t enabled_irq_mask
)
429 assert_spin_locked(&dev_priv
->irq_lock
);
431 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
433 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
436 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
439 new_val
&= ~interrupt_mask
;
440 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
442 if (new_val
!= old_val
) {
443 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
444 POSTING_READ(GEN8_DE_PORT_IMR
);
449 * ibx_display_interrupt_update - update SDEIMR
450 * @dev_priv: driver private
451 * @interrupt_mask: mask of interrupt bits to update
452 * @enabled_irq_mask: mask of interrupt bits to enable
454 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
455 uint32_t interrupt_mask
,
456 uint32_t enabled_irq_mask
)
458 uint32_t sdeimr
= I915_READ(SDEIMR
);
459 sdeimr
&= ~interrupt_mask
;
460 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
462 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
464 assert_spin_locked(&dev_priv
->irq_lock
);
466 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
469 I915_WRITE(SDEIMR
, sdeimr
);
470 POSTING_READ(SDEIMR
);
474 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
475 u32 enable_mask
, u32 status_mask
)
477 u32 reg
= PIPESTAT(pipe
);
478 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
480 assert_spin_locked(&dev_priv
->irq_lock
);
481 WARN_ON(!intel_irqs_enabled(dev_priv
));
483 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
484 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
485 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
486 pipe_name(pipe
), enable_mask
, status_mask
))
489 if ((pipestat
& enable_mask
) == enable_mask
)
492 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
494 /* Enable the interrupt, clear any pending status */
495 pipestat
|= enable_mask
| status_mask
;
496 I915_WRITE(reg
, pipestat
);
501 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
502 u32 enable_mask
, u32 status_mask
)
504 u32 reg
= PIPESTAT(pipe
);
505 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
507 assert_spin_locked(&dev_priv
->irq_lock
);
508 WARN_ON(!intel_irqs_enabled(dev_priv
));
510 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
511 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
512 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
513 pipe_name(pipe
), enable_mask
, status_mask
))
516 if ((pipestat
& enable_mask
) == 0)
519 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
521 pipestat
&= ~enable_mask
;
522 I915_WRITE(reg
, pipestat
);
526 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
528 u32 enable_mask
= status_mask
<< 16;
531 * On pipe A we don't support the PSR interrupt yet,
532 * on pipe B and C the same bit MBZ.
534 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
537 * On pipe B and C we don't support the PSR interrupt yet, on pipe
538 * A the same bit is for perf counters which we don't use either.
540 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
543 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
544 SPRITE0_FLIP_DONE_INT_EN_VLV
|
545 SPRITE1_FLIP_DONE_INT_EN_VLV
);
546 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
547 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
548 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
549 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
555 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
560 if (IS_VALLEYVIEW(dev_priv
->dev
))
561 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
564 enable_mask
= status_mask
<< 16;
565 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
569 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
574 if (IS_VALLEYVIEW(dev_priv
->dev
))
575 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
578 enable_mask
= status_mask
<< 16;
579 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
583 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
585 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
592 spin_lock_irq(&dev_priv
->irq_lock
);
594 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
595 if (INTEL_INFO(dev
)->gen
>= 4)
596 i915_enable_pipestat(dev_priv
, PIPE_A
,
597 PIPE_LEGACY_BLC_EVENT_STATUS
);
599 spin_unlock_irq(&dev_priv
->irq_lock
);
603 * This timing diagram depicts the video signal in and
604 * around the vertical blanking period.
606 * Assumptions about the fictitious mode used in this example:
608 * vsync_start = vblank_start + 1
609 * vsync_end = vblank_start + 2
610 * vtotal = vblank_start + 3
613 * latch double buffered registers
614 * increment frame counter (ctg+)
615 * generate start of vblank interrupt (gen4+)
618 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
619 * | may be shifted forward 1-3 extra lines via PIPECONF
621 * | | start of vsync:
622 * | | generate vsync interrupt
624 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
625 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
626 * ----va---> <-----------------vb--------------------> <--------va-------------
627 * | | <----vs-----> |
628 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
629 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
630 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
632 * last visible pixel first visible pixel
633 * | increment frame counter (gen3/4)
634 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
636 * x = horizontal active
637 * _ = horizontal blanking
638 * hs = horizontal sync
639 * va = vertical active
640 * vb = vertical blanking
642 * vbs = vblank_start (number)
645 * - most events happen at the start of horizontal sync
646 * - frame start happens at the start of horizontal blank, 1-4 lines
647 * (depending on PIPECONF settings) after the start of vblank
648 * - gen3/4 pixel and frame counter are synchronized with the start
649 * of horizontal active on the first line of vertical active
652 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
654 /* Gen2 doesn't have a hardware frame counter */
658 /* Called from drm generic code, passed a 'crtc', which
659 * we use as a pipe index
661 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
664 unsigned long high_frame
;
665 unsigned long low_frame
;
666 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
667 struct intel_crtc
*intel_crtc
=
668 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
669 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
671 htotal
= mode
->crtc_htotal
;
672 hsync_start
= mode
->crtc_hsync_start
;
673 vbl_start
= mode
->crtc_vblank_start
;
674 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
675 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
677 /* Convert to pixel count */
680 /* Start of vblank event occurs at start of hsync */
681 vbl_start
-= htotal
- hsync_start
;
683 high_frame
= PIPEFRAME(pipe
);
684 low_frame
= PIPEFRAMEPIXEL(pipe
);
687 * High & low register fields aren't synchronized, so make sure
688 * we get a low value that's stable across two reads of the high
692 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
693 low
= I915_READ(low_frame
);
694 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
695 } while (high1
!= high2
);
697 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
698 pixel
= low
& PIPE_PIXEL_MASK
;
699 low
>>= PIPE_FRAME_LOW_SHIFT
;
702 * The frame counter increments at beginning of active.
703 * Cook up a vblank counter by also checking the pixel
704 * counter against vblank start.
706 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
709 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
714 return I915_READ(reg
);
717 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
718 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
720 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
722 struct drm_device
*dev
= crtc
->base
.dev
;
723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
724 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
725 enum pipe pipe
= crtc
->pipe
;
726 int position
, vtotal
;
728 vtotal
= mode
->crtc_vtotal
;
729 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
733 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
735 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
738 * See update_scanline_offset() for the details on the
739 * scanline_offset adjustment.
741 return (position
+ crtc
->scanline_offset
) % vtotal
;
744 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
745 unsigned int flags
, int *vpos
, int *hpos
,
746 ktime_t
*stime
, ktime_t
*etime
)
748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
749 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
750 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
751 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
753 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
756 unsigned long irqflags
;
758 if (WARN_ON(!mode
->crtc_clock
)) {
759 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
760 "pipe %c\n", pipe_name(pipe
));
764 htotal
= mode
->crtc_htotal
;
765 hsync_start
= mode
->crtc_hsync_start
;
766 vtotal
= mode
->crtc_vtotal
;
767 vbl_start
= mode
->crtc_vblank_start
;
768 vbl_end
= mode
->crtc_vblank_end
;
770 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
771 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
776 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
779 * Lock uncore.lock, as we will do multiple timing critical raw
780 * register reads, potentially with preemption disabled, so the
781 * following code must not block on uncore.lock.
783 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
785 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
787 /* Get optional system timestamp before query. */
789 *stime
= ktime_get();
791 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
792 /* No obvious pixelcount register. Only query vertical
793 * scanout position from Display scan line register.
795 position
= __intel_get_crtc_scanline(intel_crtc
);
797 /* Have access to pixelcount since start of frame.
798 * We can split this into vertical and horizontal
801 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
803 /* convert to pixel counts */
809 * In interlaced modes, the pixel counter counts all pixels,
810 * so one field will have htotal more pixels. In order to avoid
811 * the reported position from jumping backwards when the pixel
812 * counter is beyond the length of the shorter field, just
813 * clamp the position the length of the shorter field. This
814 * matches how the scanline counter based position works since
815 * the scanline counter doesn't count the two half lines.
817 if (position
>= vtotal
)
818 position
= vtotal
- 1;
821 * Start of vblank interrupt is triggered at start of hsync,
822 * just prior to the first active line of vblank. However we
823 * consider lines to start at the leading edge of horizontal
824 * active. So, should we get here before we've crossed into
825 * the horizontal active of the first line in vblank, we would
826 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
827 * always add htotal-hsync_start to the current pixel position.
829 position
= (position
+ htotal
- hsync_start
) % vtotal
;
832 /* Get optional system timestamp after query. */
834 *etime
= ktime_get();
836 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
838 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
840 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
843 * While in vblank, position will be negative
844 * counting up towards 0 at vbl_end. And outside
845 * vblank, position will be positive counting
848 if (position
>= vbl_start
)
851 position
+= vtotal
- vbl_end
;
853 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
857 *vpos
= position
/ htotal
;
858 *hpos
= position
- (*vpos
* htotal
);
863 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
868 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
870 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
871 unsigned long irqflags
;
874 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
875 position
= __intel_get_crtc_scanline(crtc
);
876 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
881 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
883 struct timeval
*vblank_time
,
886 struct drm_crtc
*crtc
;
888 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
889 DRM_ERROR("Invalid crtc %d\n", pipe
);
893 /* Get drm_crtc to timestamp: */
894 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
896 DRM_ERROR("Invalid crtc %d\n", pipe
);
900 if (!crtc
->hwmode
.crtc_clock
) {
901 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
905 /* Helper routine in DRM core does all the work: */
906 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
912 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
915 u32 busy_up
, busy_down
, max_avg
, min_avg
;
918 spin_lock(&mchdev_lock
);
920 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
922 new_delay
= dev_priv
->ips
.cur_delay
;
924 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
925 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
926 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
927 max_avg
= I915_READ(RCBMAXAVG
);
928 min_avg
= I915_READ(RCBMINAVG
);
930 /* Handle RCS change request from hw */
931 if (busy_up
> max_avg
) {
932 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
933 new_delay
= dev_priv
->ips
.cur_delay
- 1;
934 if (new_delay
< dev_priv
->ips
.max_delay
)
935 new_delay
= dev_priv
->ips
.max_delay
;
936 } else if (busy_down
< min_avg
) {
937 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
938 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
939 if (new_delay
> dev_priv
->ips
.min_delay
)
940 new_delay
= dev_priv
->ips
.min_delay
;
943 if (ironlake_set_drps(dev
, new_delay
))
944 dev_priv
->ips
.cur_delay
= new_delay
;
946 spin_unlock(&mchdev_lock
);
951 static void notify_ring(struct intel_engine_cs
*ring
)
953 if (!intel_ring_initialized(ring
))
956 trace_i915_gem_request_notify(ring
);
958 wake_up_all(&ring
->irq_queue
);
961 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
962 struct intel_rps_ei
*ei
)
964 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
965 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
966 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
969 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
970 const struct intel_rps_ei
*old
,
971 const struct intel_rps_ei
*now
,
976 if (old
->cz_clock
== 0)
979 time
= now
->cz_clock
- old
->cz_clock
;
980 time
*= threshold
* dev_priv
->mem_freq
;
982 /* Workload can be split between render + media, e.g. SwapBuffers
983 * being blitted in X after being rendered in mesa. To account for
984 * this we need to combine both engines into our activity counter.
986 c0
= now
->render_c0
- old
->render_c0
;
987 c0
+= now
->media_c0
- old
->media_c0
;
988 c0
*= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC
* 4 / 1000;
993 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
995 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
996 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
999 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1001 struct intel_rps_ei now
;
1004 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1007 vlv_c0_read(dev_priv
, &now
);
1008 if (now
.cz_clock
== 0)
1011 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1012 if (!vlv_c0_above(dev_priv
,
1013 &dev_priv
->rps
.down_ei
, &now
,
1014 dev_priv
->rps
.down_threshold
))
1015 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1016 dev_priv
->rps
.down_ei
= now
;
1019 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1020 if (vlv_c0_above(dev_priv
,
1021 &dev_priv
->rps
.up_ei
, &now
,
1022 dev_priv
->rps
.up_threshold
))
1023 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1024 dev_priv
->rps
.up_ei
= now
;
1030 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1032 struct intel_engine_cs
*ring
;
1035 for_each_ring(ring
, dev_priv
, i
)
1036 if (ring
->irq_refcount
)
1042 static void gen6_pm_rps_work(struct work_struct
*work
)
1044 struct drm_i915_private
*dev_priv
=
1045 container_of(work
, struct drm_i915_private
, rps
.work
);
1047 int new_delay
, adj
, min
, max
;
1050 spin_lock_irq(&dev_priv
->irq_lock
);
1051 /* Speed up work cancelation during disabling rps interrupts. */
1052 if (!dev_priv
->rps
.interrupts_enabled
) {
1053 spin_unlock_irq(&dev_priv
->irq_lock
);
1056 pm_iir
= dev_priv
->rps
.pm_iir
;
1057 dev_priv
->rps
.pm_iir
= 0;
1058 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1059 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1060 client_boost
= dev_priv
->rps
.client_boost
;
1061 dev_priv
->rps
.client_boost
= false;
1062 spin_unlock_irq(&dev_priv
->irq_lock
);
1064 /* Make sure we didn't queue anything we're not going to process. */
1065 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1067 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1070 mutex_lock(&dev_priv
->rps
.hw_lock
);
1072 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1074 adj
= dev_priv
->rps
.last_adj
;
1075 new_delay
= dev_priv
->rps
.cur_freq
;
1076 min
= dev_priv
->rps
.min_freq_softlimit
;
1077 max
= dev_priv
->rps
.max_freq_softlimit
;
1080 new_delay
= dev_priv
->rps
.max_freq_softlimit
;
1082 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1085 else /* CHV needs even encode values */
1086 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1088 * For better performance, jump directly
1089 * to RPe if we're below it.
1091 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1092 new_delay
= dev_priv
->rps
.efficient_freq
;
1095 } else if (any_waiters(dev_priv
)) {
1097 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1098 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1099 new_delay
= dev_priv
->rps
.efficient_freq
;
1101 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1103 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1106 else /* CHV needs even encode values */
1107 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1108 } else { /* unknown event */
1112 dev_priv
->rps
.last_adj
= adj
;
1114 /* sysfs frequency interfaces may have snuck in while servicing the
1118 new_delay
= clamp_t(int, new_delay
, min
, max
);
1120 intel_set_rps(dev_priv
->dev
, new_delay
);
1122 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1127 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1129 * @work: workqueue struct
1131 * Doesn't actually do anything except notify userspace. As a consequence of
1132 * this event, userspace should try to remap the bad rows since statistically
1133 * it is likely the same row is more likely to go bad again.
1135 static void ivybridge_parity_work(struct work_struct
*work
)
1137 struct drm_i915_private
*dev_priv
=
1138 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1139 u32 error_status
, row
, bank
, subbank
;
1140 char *parity_event
[6];
1144 /* We must turn off DOP level clock gating to access the L3 registers.
1145 * In order to prevent a get/put style interface, acquire struct mutex
1146 * any time we access those registers.
1148 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1150 /* If we've screwed up tracking, just let the interrupt fire again */
1151 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1154 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1155 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1156 POSTING_READ(GEN7_MISCCPCTL
);
1158 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1162 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1165 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1167 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1169 error_status
= I915_READ(reg
);
1170 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1171 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1172 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1174 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1177 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1178 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1179 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1180 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1181 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1182 parity_event
[5] = NULL
;
1184 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1185 KOBJ_CHANGE
, parity_event
);
1187 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1188 slice
, row
, bank
, subbank
);
1190 kfree(parity_event
[4]);
1191 kfree(parity_event
[3]);
1192 kfree(parity_event
[2]);
1193 kfree(parity_event
[1]);
1196 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1199 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1200 spin_lock_irq(&dev_priv
->irq_lock
);
1201 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1202 spin_unlock_irq(&dev_priv
->irq_lock
);
1204 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1207 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1211 if (!HAS_L3_DPF(dev
))
1214 spin_lock(&dev_priv
->irq_lock
);
1215 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1216 spin_unlock(&dev_priv
->irq_lock
);
1218 iir
&= GT_PARITY_ERROR(dev
);
1219 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1220 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1222 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1223 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1225 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1228 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1229 struct drm_i915_private
*dev_priv
,
1233 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1234 notify_ring(&dev_priv
->ring
[RCS
]);
1235 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1236 notify_ring(&dev_priv
->ring
[VCS
]);
1239 static void snb_gt_irq_handler(struct drm_device
*dev
,
1240 struct drm_i915_private
*dev_priv
,
1245 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1246 notify_ring(&dev_priv
->ring
[RCS
]);
1247 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1248 notify_ring(&dev_priv
->ring
[VCS
]);
1249 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1250 notify_ring(&dev_priv
->ring
[BCS
]);
1252 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1253 GT_BSD_CS_ERROR_INTERRUPT
|
1254 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1255 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1257 if (gt_iir
& GT_PARITY_ERROR(dev
))
1258 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1261 static irqreturn_t
gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1264 irqreturn_t ret
= IRQ_NONE
;
1266 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1267 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(0));
1269 I915_WRITE_FW(GEN8_GT_IIR(0), tmp
);
1272 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
))
1273 intel_lrc_irq_handler(&dev_priv
->ring
[RCS
]);
1274 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
))
1275 notify_ring(&dev_priv
->ring
[RCS
]);
1277 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
))
1278 intel_lrc_irq_handler(&dev_priv
->ring
[BCS
]);
1279 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
))
1280 notify_ring(&dev_priv
->ring
[BCS
]);
1282 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1285 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1286 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(1));
1288 I915_WRITE_FW(GEN8_GT_IIR(1), tmp
);
1291 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
))
1292 intel_lrc_irq_handler(&dev_priv
->ring
[VCS
]);
1293 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
))
1294 notify_ring(&dev_priv
->ring
[VCS
]);
1296 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
))
1297 intel_lrc_irq_handler(&dev_priv
->ring
[VCS2
]);
1298 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
))
1299 notify_ring(&dev_priv
->ring
[VCS2
]);
1301 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1304 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1305 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(3));
1307 I915_WRITE_FW(GEN8_GT_IIR(3), tmp
);
1310 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
))
1311 intel_lrc_irq_handler(&dev_priv
->ring
[VECS
]);
1312 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
))
1313 notify_ring(&dev_priv
->ring
[VECS
]);
1315 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1318 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1319 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(2));
1320 if (tmp
& dev_priv
->pm_rps_events
) {
1321 I915_WRITE_FW(GEN8_GT_IIR(2),
1322 tmp
& dev_priv
->pm_rps_events
);
1324 gen6_rps_irq_handler(dev_priv
, tmp
);
1326 DRM_ERROR("The master control interrupt lied (PM)!\n");
1332 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1336 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1338 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1340 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1346 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1350 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1356 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1360 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1362 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1364 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1366 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1372 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1376 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1382 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1386 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1388 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1390 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1396 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1400 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1402 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1404 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1411 * Get a bit mask of pins that have triggered, and which ones may be long.
1412 * This can be called multiple times with the same masks to accumulate
1413 * hotplug detection results from several registers.
1415 * Note that the caller is expected to zero out the masks initially.
1417 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1418 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1419 const u32 hpd
[HPD_NUM_PINS
],
1420 bool long_pulse_detect(enum port port
, u32 val
))
1425 for_each_hpd_pin(i
) {
1426 if ((hpd
[i
] & hotplug_trigger
) == 0)
1429 *pin_mask
|= BIT(i
);
1431 if (!intel_hpd_pin_to_port(i
, &port
))
1434 if (long_pulse_detect(port
, dig_hotplug_reg
))
1435 *long_mask
|= BIT(i
);
1438 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1439 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1443 static void gmbus_irq_handler(struct drm_device
*dev
)
1445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1447 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1450 static void dp_aux_irq_handler(struct drm_device
*dev
)
1452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1454 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1457 #if defined(CONFIG_DEBUG_FS)
1458 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1459 uint32_t crc0
, uint32_t crc1
,
1460 uint32_t crc2
, uint32_t crc3
,
1463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1465 struct intel_pipe_crc_entry
*entry
;
1468 spin_lock(&pipe_crc
->lock
);
1470 if (!pipe_crc
->entries
) {
1471 spin_unlock(&pipe_crc
->lock
);
1472 DRM_DEBUG_KMS("spurious interrupt\n");
1476 head
= pipe_crc
->head
;
1477 tail
= pipe_crc
->tail
;
1479 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1480 spin_unlock(&pipe_crc
->lock
);
1481 DRM_ERROR("CRC buffer overflowing\n");
1485 entry
= &pipe_crc
->entries
[head
];
1487 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1488 entry
->crc
[0] = crc0
;
1489 entry
->crc
[1] = crc1
;
1490 entry
->crc
[2] = crc2
;
1491 entry
->crc
[3] = crc3
;
1492 entry
->crc
[4] = crc4
;
1494 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1495 pipe_crc
->head
= head
;
1497 spin_unlock(&pipe_crc
->lock
);
1499 wake_up_interruptible(&pipe_crc
->wq
);
1503 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1504 uint32_t crc0
, uint32_t crc1
,
1505 uint32_t crc2
, uint32_t crc3
,
1510 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1514 display_pipe_crc_irq_handler(dev
, pipe
,
1515 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1519 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 display_pipe_crc_irq_handler(dev
, pipe
,
1524 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1525 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1526 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1527 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1528 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1531 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1534 uint32_t res1
, res2
;
1536 if (INTEL_INFO(dev
)->gen
>= 3)
1537 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1541 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1542 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1546 display_pipe_crc_irq_handler(dev
, pipe
,
1547 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1548 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1549 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1553 /* The RPS events need forcewake, so we add them to a work queue and mask their
1554 * IMR bits until the work is done. Other interrupts can be processed without
1555 * the work queue. */
1556 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1558 if (pm_iir
& dev_priv
->pm_rps_events
) {
1559 spin_lock(&dev_priv
->irq_lock
);
1560 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1561 if (dev_priv
->rps
.interrupts_enabled
) {
1562 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1563 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1565 spin_unlock(&dev_priv
->irq_lock
);
1568 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1571 if (HAS_VEBOX(dev_priv
->dev
)) {
1572 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1573 notify_ring(&dev_priv
->ring
[VECS
]);
1575 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1576 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1580 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1582 if (!drm_handle_vblank(dev
, pipe
))
1588 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1591 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1594 spin_lock(&dev_priv
->irq_lock
);
1595 for_each_pipe(dev_priv
, pipe
) {
1597 u32 mask
, iir_bit
= 0;
1600 * PIPESTAT bits get signalled even when the interrupt is
1601 * disabled with the mask bits, and some of the status bits do
1602 * not generate interrupts at all (like the underrun bit). Hence
1603 * we need to be careful that we only handle what we want to
1607 /* fifo underruns are filterered in the underrun handler. */
1608 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1612 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1615 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1618 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1622 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1627 reg
= PIPESTAT(pipe
);
1628 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1629 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1632 * Clear the PIPE*STAT regs before the IIR
1634 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1635 PIPESTAT_INT_STATUS_MASK
))
1636 I915_WRITE(reg
, pipe_stats
[pipe
]);
1638 spin_unlock(&dev_priv
->irq_lock
);
1640 for_each_pipe(dev_priv
, pipe
) {
1641 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1642 intel_pipe_handle_vblank(dev
, pipe
))
1643 intel_check_page_flip(dev
, pipe
);
1645 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1646 intel_prepare_page_flip(dev
, pipe
);
1647 intel_finish_page_flip(dev
, pipe
);
1650 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1651 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1653 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1654 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1657 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1658 gmbus_irq_handler(dev
);
1661 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1664 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1665 u32 pin_mask
= 0, long_mask
= 0;
1667 if (!hotplug_status
)
1670 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1672 * Make sure hotplug status is cleared before we clear IIR, or else we
1673 * may miss hotplug events.
1675 POSTING_READ(PORT_HOTPLUG_STAT
);
1677 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
1678 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1680 if (hotplug_trigger
) {
1681 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1682 hotplug_trigger
, hpd_status_g4x
,
1683 i9xx_port_hotplug_long_detect
);
1685 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1688 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1689 dp_aux_irq_handler(dev
);
1691 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1693 if (hotplug_trigger
) {
1694 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1695 hotplug_trigger
, hpd_status_g4x
,
1696 i9xx_port_hotplug_long_detect
);
1698 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1703 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1705 struct drm_device
*dev
= arg
;
1706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1707 u32 iir
, gt_iir
, pm_iir
;
1708 irqreturn_t ret
= IRQ_NONE
;
1710 if (!intel_irqs_enabled(dev_priv
))
1714 /* Find, clear, then process each source of interrupt */
1716 gt_iir
= I915_READ(GTIIR
);
1718 I915_WRITE(GTIIR
, gt_iir
);
1720 pm_iir
= I915_READ(GEN6_PMIIR
);
1722 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1724 iir
= I915_READ(VLV_IIR
);
1726 /* Consume port before clearing IIR or we'll miss events */
1727 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1728 i9xx_hpd_irq_handler(dev
);
1729 I915_WRITE(VLV_IIR
, iir
);
1732 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1738 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1740 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1741 /* Call regardless, as some status bits might not be
1742 * signalled in iir */
1743 valleyview_pipestat_irq_handler(dev
, iir
);
1750 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1752 struct drm_device
*dev
= arg
;
1753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1754 u32 master_ctl
, iir
;
1755 irqreturn_t ret
= IRQ_NONE
;
1757 if (!intel_irqs_enabled(dev_priv
))
1761 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1762 iir
= I915_READ(VLV_IIR
);
1764 if (master_ctl
== 0 && iir
== 0)
1769 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1771 /* Find, clear, then process each source of interrupt */
1774 /* Consume port before clearing IIR or we'll miss events */
1775 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1776 i9xx_hpd_irq_handler(dev
);
1777 I915_WRITE(VLV_IIR
, iir
);
1780 gen8_gt_irq_handler(dev_priv
, master_ctl
);
1782 /* Call regardless, as some status bits might not be
1783 * signalled in iir */
1784 valleyview_pipestat_irq_handler(dev
, iir
);
1786 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1787 POSTING_READ(GEN8_MASTER_IRQ
);
1793 static void ibx_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
1794 const u32 hpd
[HPD_NUM_PINS
])
1796 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1797 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1799 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1800 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1802 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1803 dig_hotplug_reg
, hpd
,
1804 pch_port_hotplug_long_detect
);
1806 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1809 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1813 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1815 if (hotplug_trigger
)
1816 ibx_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1818 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1819 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1820 SDE_AUDIO_POWER_SHIFT
);
1821 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1825 if (pch_iir
& SDE_AUX_MASK
)
1826 dp_aux_irq_handler(dev
);
1828 if (pch_iir
& SDE_GMBUS
)
1829 gmbus_irq_handler(dev
);
1831 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1832 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1834 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1835 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1837 if (pch_iir
& SDE_POISON
)
1838 DRM_ERROR("PCH poison interrupt\n");
1840 if (pch_iir
& SDE_FDI_MASK
)
1841 for_each_pipe(dev_priv
, pipe
)
1842 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1844 I915_READ(FDI_RX_IIR(pipe
)));
1846 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1847 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1849 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1850 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1852 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1853 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1855 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1856 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1859 static void ivb_err_int_handler(struct drm_device
*dev
)
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1862 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1865 if (err_int
& ERR_INT_POISON
)
1866 DRM_ERROR("Poison interrupt\n");
1868 for_each_pipe(dev_priv
, pipe
) {
1869 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1870 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1872 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1873 if (IS_IVYBRIDGE(dev
))
1874 ivb_pipe_crc_irq_handler(dev
, pipe
);
1876 hsw_pipe_crc_irq_handler(dev
, pipe
);
1880 I915_WRITE(GEN7_ERR_INT
, err_int
);
1883 static void cpt_serr_int_handler(struct drm_device
*dev
)
1885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1886 u32 serr_int
= I915_READ(SERR_INT
);
1888 if (serr_int
& SERR_INT_POISON
)
1889 DRM_ERROR("PCH poison interrupt\n");
1891 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1892 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1894 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1895 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1897 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1898 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
1900 I915_WRITE(SERR_INT
, serr_int
);
1903 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1907 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1909 if (hotplug_trigger
)
1910 ibx_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1912 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1913 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1914 SDE_AUDIO_POWER_SHIFT_CPT
);
1915 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1919 if (pch_iir
& SDE_AUX_MASK_CPT
)
1920 dp_aux_irq_handler(dev
);
1922 if (pch_iir
& SDE_GMBUS_CPT
)
1923 gmbus_irq_handler(dev
);
1925 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1926 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1928 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1929 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1931 if (pch_iir
& SDE_FDI_MASK_CPT
)
1932 for_each_pipe(dev_priv
, pipe
)
1933 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1935 I915_READ(FDI_RX_IIR(pipe
)));
1937 if (pch_iir
& SDE_ERROR_CPT
)
1938 cpt_serr_int_handler(dev
);
1941 static void spt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1944 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
1945 ~SDE_PORTE_HOTPLUG_SPT
;
1946 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
1947 u32 pin_mask
= 0, long_mask
= 0;
1949 if (hotplug_trigger
) {
1950 u32 dig_hotplug_reg
;
1952 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1953 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1955 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1956 dig_hotplug_reg
, hpd_spt
,
1957 spt_port_hotplug_long_detect
);
1960 if (hotplug2_trigger
) {
1961 u32 dig_hotplug_reg
;
1963 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
1964 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
1966 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
1967 dig_hotplug_reg
, hpd_spt
,
1968 spt_port_hotplug2_long_detect
);
1972 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1974 if (pch_iir
& SDE_GMBUS_CPT
)
1975 gmbus_irq_handler(dev
);
1978 static void ilk_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
1979 const u32 hpd
[HPD_NUM_PINS
])
1981 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1982 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1984 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
1985 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
1987 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1988 dig_hotplug_reg
, hpd
,
1989 ilk_port_hotplug_long_detect
);
1991 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1994 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1998 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2000 if (hotplug_trigger
)
2001 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ilk
);
2003 if (de_iir
& DE_AUX_CHANNEL_A
)
2004 dp_aux_irq_handler(dev
);
2006 if (de_iir
& DE_GSE
)
2007 intel_opregion_asle_intr(dev
);
2009 if (de_iir
& DE_POISON
)
2010 DRM_ERROR("Poison interrupt\n");
2012 for_each_pipe(dev_priv
, pipe
) {
2013 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2014 intel_pipe_handle_vblank(dev
, pipe
))
2015 intel_check_page_flip(dev
, pipe
);
2017 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2018 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2020 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2021 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2023 /* plane/pipes map 1:1 on ilk+ */
2024 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2025 intel_prepare_page_flip(dev
, pipe
);
2026 intel_finish_page_flip_plane(dev
, pipe
);
2030 /* check event from PCH */
2031 if (de_iir
& DE_PCH_EVENT
) {
2032 u32 pch_iir
= I915_READ(SDEIIR
);
2034 if (HAS_PCH_CPT(dev
))
2035 cpt_irq_handler(dev
, pch_iir
);
2037 ibx_irq_handler(dev
, pch_iir
);
2039 /* should clear PCH hotplug event before clear CPU irq */
2040 I915_WRITE(SDEIIR
, pch_iir
);
2043 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2044 ironlake_rps_change_irq_handler(dev
);
2047 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2051 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2053 if (hotplug_trigger
)
2054 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ivb
);
2056 if (de_iir
& DE_ERR_INT_IVB
)
2057 ivb_err_int_handler(dev
);
2059 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2060 dp_aux_irq_handler(dev
);
2062 if (de_iir
& DE_GSE_IVB
)
2063 intel_opregion_asle_intr(dev
);
2065 for_each_pipe(dev_priv
, pipe
) {
2066 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2067 intel_pipe_handle_vblank(dev
, pipe
))
2068 intel_check_page_flip(dev
, pipe
);
2070 /* plane/pipes map 1:1 on ilk+ */
2071 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2072 intel_prepare_page_flip(dev
, pipe
);
2073 intel_finish_page_flip_plane(dev
, pipe
);
2077 /* check event from PCH */
2078 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2079 u32 pch_iir
= I915_READ(SDEIIR
);
2081 cpt_irq_handler(dev
, pch_iir
);
2083 /* clear PCH hotplug event before clear CPU irq */
2084 I915_WRITE(SDEIIR
, pch_iir
);
2089 * To handle irqs with the minimum potential races with fresh interrupts, we:
2090 * 1 - Disable Master Interrupt Control.
2091 * 2 - Find the source(s) of the interrupt.
2092 * 3 - Clear the Interrupt Identity bits (IIR).
2093 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2094 * 5 - Re-enable Master Interrupt Control.
2096 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2098 struct drm_device
*dev
= arg
;
2099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2100 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2101 irqreturn_t ret
= IRQ_NONE
;
2103 if (!intel_irqs_enabled(dev_priv
))
2106 /* We get interrupts on unclaimed registers, so check for this before we
2107 * do any I915_{READ,WRITE}. */
2108 intel_uncore_check_errors(dev
);
2110 /* disable master interrupt before clearing iir */
2111 de_ier
= I915_READ(DEIER
);
2112 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2113 POSTING_READ(DEIER
);
2115 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2116 * interrupts will will be stored on its back queue, and then we'll be
2117 * able to process them after we restore SDEIER (as soon as we restore
2118 * it, we'll get an interrupt if SDEIIR still has something to process
2119 * due to its back queue). */
2120 if (!HAS_PCH_NOP(dev
)) {
2121 sde_ier
= I915_READ(SDEIER
);
2122 I915_WRITE(SDEIER
, 0);
2123 POSTING_READ(SDEIER
);
2126 /* Find, clear, then process each source of interrupt */
2128 gt_iir
= I915_READ(GTIIR
);
2130 I915_WRITE(GTIIR
, gt_iir
);
2132 if (INTEL_INFO(dev
)->gen
>= 6)
2133 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2135 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2138 de_iir
= I915_READ(DEIIR
);
2140 I915_WRITE(DEIIR
, de_iir
);
2142 if (INTEL_INFO(dev
)->gen
>= 7)
2143 ivb_display_irq_handler(dev
, de_iir
);
2145 ilk_display_irq_handler(dev
, de_iir
);
2148 if (INTEL_INFO(dev
)->gen
>= 6) {
2149 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2151 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2153 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2157 I915_WRITE(DEIER
, de_ier
);
2158 POSTING_READ(DEIER
);
2159 if (!HAS_PCH_NOP(dev
)) {
2160 I915_WRITE(SDEIER
, sde_ier
);
2161 POSTING_READ(SDEIER
);
2167 static void bxt_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
2168 const u32 hpd
[HPD_NUM_PINS
])
2170 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2171 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2173 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2174 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2176 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2177 dig_hotplug_reg
, hpd
,
2178 bxt_port_hotplug_long_detect
);
2180 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2183 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2185 struct drm_device
*dev
= arg
;
2186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2188 irqreturn_t ret
= IRQ_NONE
;
2191 u32 aux_mask
= GEN8_AUX_CHANNEL_A
;
2193 if (!intel_irqs_enabled(dev_priv
))
2196 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2197 aux_mask
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
2200 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2201 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2205 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2207 /* Find, clear, then process each source of interrupt */
2209 ret
= gen8_gt_irq_handler(dev_priv
, master_ctl
);
2211 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2212 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2214 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2216 if (tmp
& GEN8_DE_MISC_GSE
)
2217 intel_opregion_asle_intr(dev
);
2219 DRM_ERROR("Unexpected DE Misc interrupt\n");
2222 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2225 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2226 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2229 u32 hotplug_trigger
= 0;
2231 if (IS_BROXTON(dev_priv
))
2232 hotplug_trigger
= tmp
& BXT_DE_PORT_HOTPLUG_MASK
;
2233 else if (IS_BROADWELL(dev_priv
))
2234 hotplug_trigger
= tmp
& GEN8_PORT_DP_A_HOTPLUG
;
2236 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2239 if (tmp
& aux_mask
) {
2240 dp_aux_irq_handler(dev
);
2244 if (hotplug_trigger
) {
2245 if (IS_BROXTON(dev
))
2246 bxt_hpd_irq_handler(dev
, hotplug_trigger
, hpd_bxt
);
2248 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_bdw
);
2252 if (IS_BROXTON(dev
) && (tmp
& BXT_DE_PORT_GMBUS
)) {
2253 gmbus_irq_handler(dev
);
2258 DRM_ERROR("Unexpected DE Port interrupt\n");
2261 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2264 for_each_pipe(dev_priv
, pipe
) {
2265 uint32_t pipe_iir
, flip_done
= 0, fault_errors
= 0;
2267 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2270 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2273 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2275 if (pipe_iir
& GEN8_PIPE_VBLANK
&&
2276 intel_pipe_handle_vblank(dev
, pipe
))
2277 intel_check_page_flip(dev
, pipe
);
2279 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2280 flip_done
= pipe_iir
& GEN9_PIPE_PLANE1_FLIP_DONE
;
2282 flip_done
= pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
;
2285 intel_prepare_page_flip(dev
, pipe
);
2286 intel_finish_page_flip_plane(dev
, pipe
);
2289 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2290 hsw_pipe_crc_irq_handler(dev
, pipe
);
2292 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2293 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
2297 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2298 fault_errors
= pipe_iir
& GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2300 fault_errors
= pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2303 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2305 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2307 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2310 if (HAS_PCH_SPLIT(dev
) && !HAS_PCH_NOP(dev
) &&
2311 master_ctl
& GEN8_DE_PCH_IRQ
) {
2313 * FIXME(BDW): Assume for now that the new interrupt handling
2314 * scheme also closed the SDE interrupt handling race we've seen
2315 * on older pch-split platforms. But this needs testing.
2317 u32 pch_iir
= I915_READ(SDEIIR
);
2319 I915_WRITE(SDEIIR
, pch_iir
);
2322 if (HAS_PCH_SPT(dev_priv
))
2323 spt_irq_handler(dev
, pch_iir
);
2325 cpt_irq_handler(dev
, pch_iir
);
2327 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2331 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2332 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2337 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2338 bool reset_completed
)
2340 struct intel_engine_cs
*ring
;
2344 * Notify all waiters for GPU completion events that reset state has
2345 * been changed, and that they need to restart their wait after
2346 * checking for potential errors (and bail out to drop locks if there is
2347 * a gpu reset pending so that i915_error_work_func can acquire them).
2350 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2351 for_each_ring(ring
, dev_priv
, i
)
2352 wake_up_all(&ring
->irq_queue
);
2354 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2355 wake_up_all(&dev_priv
->pending_flip_queue
);
2358 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2359 * reset state is cleared.
2361 if (reset_completed
)
2362 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2366 * i915_reset_and_wakeup - do process context error handling work
2368 * Fire an error uevent so userspace can see that a hang or error
2371 static void i915_reset_and_wakeup(struct drm_device
*dev
)
2373 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2374 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
2375 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2376 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2377 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2380 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2383 * Note that there's only one work item which does gpu resets, so we
2384 * need not worry about concurrent gpu resets potentially incrementing
2385 * error->reset_counter twice. We only need to take care of another
2386 * racing irq/hangcheck declaring the gpu dead for a second time. A
2387 * quick check for that is good enough: schedule_work ensures the
2388 * correct ordering between hang detection and this work item, and since
2389 * the reset in-progress bit is only ever set by code outside of this
2390 * work we don't need to worry about any other races.
2392 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2393 DRM_DEBUG_DRIVER("resetting chip\n");
2394 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2398 * In most cases it's guaranteed that we get here with an RPM
2399 * reference held, for example because there is a pending GPU
2400 * request that won't finish until the reset is done. This
2401 * isn't the case at least when we get here by doing a
2402 * simulated reset via debugs, so get an RPM reference.
2404 intel_runtime_pm_get(dev_priv
);
2406 intel_prepare_reset(dev
);
2409 * All state reset _must_ be completed before we update the
2410 * reset counter, for otherwise waiters might miss the reset
2411 * pending state and not properly drop locks, resulting in
2412 * deadlocks with the reset work.
2414 ret
= i915_reset(dev
);
2416 intel_finish_reset(dev
);
2418 intel_runtime_pm_put(dev_priv
);
2422 * After all the gem state is reset, increment the reset
2423 * counter and wake up everyone waiting for the reset to
2426 * Since unlock operations are a one-sided barrier only,
2427 * we need to insert a barrier here to order any seqno
2429 * the counter increment.
2431 smp_mb__before_atomic();
2432 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2434 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2435 KOBJ_CHANGE
, reset_done_event
);
2437 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2441 * Note: The wake_up also serves as a memory barrier so that
2442 * waiters see the update value of the reset counter atomic_t.
2444 i915_error_wake_up(dev_priv
, true);
2448 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2451 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2452 u32 eir
= I915_READ(EIR
);
2458 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2460 i915_get_extra_instdone(dev
, instdone
);
2463 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2464 u32 ipeir
= I915_READ(IPEIR_I965
);
2466 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2467 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2468 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2469 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2470 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2471 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2472 I915_WRITE(IPEIR_I965
, ipeir
);
2473 POSTING_READ(IPEIR_I965
);
2475 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2476 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2477 pr_err("page table error\n");
2478 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2479 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2480 POSTING_READ(PGTBL_ER
);
2484 if (!IS_GEN2(dev
)) {
2485 if (eir
& I915_ERROR_PAGE_TABLE
) {
2486 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2487 pr_err("page table error\n");
2488 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2489 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2490 POSTING_READ(PGTBL_ER
);
2494 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2495 pr_err("memory refresh error:\n");
2496 for_each_pipe(dev_priv
, pipe
)
2497 pr_err("pipe %c stat: 0x%08x\n",
2498 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2499 /* pipestat has already been acked */
2501 if (eir
& I915_ERROR_INSTRUCTION
) {
2502 pr_err("instruction error\n");
2503 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2504 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2505 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2506 if (INTEL_INFO(dev
)->gen
< 4) {
2507 u32 ipeir
= I915_READ(IPEIR
);
2509 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2510 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2511 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2512 I915_WRITE(IPEIR
, ipeir
);
2513 POSTING_READ(IPEIR
);
2515 u32 ipeir
= I915_READ(IPEIR_I965
);
2517 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2518 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2519 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2520 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2521 I915_WRITE(IPEIR_I965
, ipeir
);
2522 POSTING_READ(IPEIR_I965
);
2526 I915_WRITE(EIR
, eir
);
2528 eir
= I915_READ(EIR
);
2531 * some errors might have become stuck,
2534 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2535 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2536 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2541 * i915_handle_error - handle a gpu error
2544 * Do some basic checking of regsiter state at error time and
2545 * dump it to the syslog. Also call i915_capture_error_state() to make
2546 * sure we get a record and make it available in debugfs. Fire a uevent
2547 * so userspace knows something bad happened (should trigger collection
2548 * of a ring dump etc.).
2550 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2551 const char *fmt
, ...)
2553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2557 va_start(args
, fmt
);
2558 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2561 i915_capture_error_state(dev
, wedged
, error_msg
);
2562 i915_report_and_clear_eir(dev
);
2565 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2566 &dev_priv
->gpu_error
.reset_counter
);
2569 * Wakeup waiting processes so that the reset function
2570 * i915_reset_and_wakeup doesn't deadlock trying to grab
2571 * various locks. By bumping the reset counter first, the woken
2572 * processes will see a reset in progress and back off,
2573 * releasing their locks and then wait for the reset completion.
2574 * We must do this for _all_ gpu waiters that might hold locks
2575 * that the reset work needs to acquire.
2577 * Note: The wake_up serves as the required memory barrier to
2578 * ensure that the waiters see the updated value of the reset
2581 i915_error_wake_up(dev_priv
, false);
2584 i915_reset_and_wakeup(dev
);
2587 /* Called from drm generic code, passed 'crtc' which
2588 * we use as a pipe index
2590 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2593 unsigned long irqflags
;
2595 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2596 if (INTEL_INFO(dev
)->gen
>= 4)
2597 i915_enable_pipestat(dev_priv
, pipe
,
2598 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2600 i915_enable_pipestat(dev_priv
, pipe
,
2601 PIPE_VBLANK_INTERRUPT_STATUS
);
2602 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2607 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2610 unsigned long irqflags
;
2611 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2612 DE_PIPE_VBLANK(pipe
);
2614 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2615 ironlake_enable_display_irq(dev_priv
, bit
);
2616 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2621 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2624 unsigned long irqflags
;
2626 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2627 i915_enable_pipestat(dev_priv
, pipe
,
2628 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2629 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2634 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2637 unsigned long irqflags
;
2639 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2640 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2641 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2642 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2643 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2647 /* Called from drm generic code, passed 'crtc' which
2648 * we use as a pipe index
2650 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2653 unsigned long irqflags
;
2655 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2656 i915_disable_pipestat(dev_priv
, pipe
,
2657 PIPE_VBLANK_INTERRUPT_STATUS
|
2658 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2659 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2662 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2665 unsigned long irqflags
;
2666 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2667 DE_PIPE_VBLANK(pipe
);
2669 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2670 ironlake_disable_display_irq(dev_priv
, bit
);
2671 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2674 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2677 unsigned long irqflags
;
2679 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2680 i915_disable_pipestat(dev_priv
, pipe
,
2681 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2682 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2685 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2688 unsigned long irqflags
;
2690 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2691 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2692 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2693 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2694 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2698 ring_idle(struct intel_engine_cs
*ring
, u32 seqno
)
2700 return (list_empty(&ring
->request_list
) ||
2701 i915_seqno_passed(seqno
, ring
->last_submitted_seqno
));
2705 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2707 if (INTEL_INFO(dev
)->gen
>= 8) {
2708 return (ipehr
>> 23) == 0x1c;
2710 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2711 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2712 MI_SEMAPHORE_REGISTER
);
2716 static struct intel_engine_cs
*
2717 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring
, u32 ipehr
, u64 offset
)
2719 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2720 struct intel_engine_cs
*signaller
;
2723 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2724 for_each_ring(signaller
, dev_priv
, i
) {
2725 if (ring
== signaller
)
2728 if (offset
== signaller
->semaphore
.signal_ggtt
[ring
->id
])
2732 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2734 for_each_ring(signaller
, dev_priv
, i
) {
2735 if(ring
== signaller
)
2738 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[ring
->id
])
2743 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2744 ring
->id
, ipehr
, offset
);
2749 static struct intel_engine_cs
*
2750 semaphore_waits_for(struct intel_engine_cs
*ring
, u32
*seqno
)
2752 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2753 u32 cmd
, ipehr
, head
;
2757 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2758 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2762 * HEAD is likely pointing to the dword after the actual command,
2763 * so scan backwards until we find the MBOX. But limit it to just 3
2764 * or 4 dwords depending on the semaphore wait command size.
2765 * Note that we don't care about ACTHD here since that might
2766 * point at at batch, and semaphores are always emitted into the
2767 * ringbuffer itself.
2769 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2770 backwards
= (INTEL_INFO(ring
->dev
)->gen
>= 8) ? 5 : 4;
2772 for (i
= backwards
; i
; --i
) {
2774 * Be paranoid and presume the hw has gone off into the wild -
2775 * our ring is smaller than what the hardware (and hence
2776 * HEAD_ADDR) allows. Also handles wrap-around.
2778 head
&= ring
->buffer
->size
- 1;
2780 /* This here seems to blow up */
2781 cmd
= ioread32(ring
->buffer
->virtual_start
+ head
);
2791 *seqno
= ioread32(ring
->buffer
->virtual_start
+ head
+ 4) + 1;
2792 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2793 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 12);
2795 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 8);
2797 return semaphore_wait_to_signaller_ring(ring
, ipehr
, offset
);
2800 static int semaphore_passed(struct intel_engine_cs
*ring
)
2802 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2803 struct intel_engine_cs
*signaller
;
2806 ring
->hangcheck
.deadlock
++;
2808 signaller
= semaphore_waits_for(ring
, &seqno
);
2809 if (signaller
== NULL
)
2812 /* Prevent pathological recursion due to driver bugs */
2813 if (signaller
->hangcheck
.deadlock
>= I915_NUM_RINGS
)
2816 if (i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
))
2819 /* cursory check for an unkickable deadlock */
2820 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2821 semaphore_passed(signaller
) < 0)
2827 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2829 struct intel_engine_cs
*ring
;
2832 for_each_ring(ring
, dev_priv
, i
)
2833 ring
->hangcheck
.deadlock
= 0;
2836 static enum intel_ring_hangcheck_action
2837 ring_stuck(struct intel_engine_cs
*ring
, u64 acthd
)
2839 struct drm_device
*dev
= ring
->dev
;
2840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2843 if (acthd
!= ring
->hangcheck
.acthd
) {
2844 if (acthd
> ring
->hangcheck
.max_acthd
) {
2845 ring
->hangcheck
.max_acthd
= acthd
;
2846 return HANGCHECK_ACTIVE
;
2849 return HANGCHECK_ACTIVE_LOOP
;
2853 return HANGCHECK_HUNG
;
2855 /* Is the chip hanging on a WAIT_FOR_EVENT?
2856 * If so we can simply poke the RB_WAIT bit
2857 * and break the hang. This should work on
2858 * all but the second generation chipsets.
2860 tmp
= I915_READ_CTL(ring
);
2861 if (tmp
& RING_WAIT
) {
2862 i915_handle_error(dev
, false,
2863 "Kicking stuck wait on %s",
2865 I915_WRITE_CTL(ring
, tmp
);
2866 return HANGCHECK_KICK
;
2869 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2870 switch (semaphore_passed(ring
)) {
2872 return HANGCHECK_HUNG
;
2874 i915_handle_error(dev
, false,
2875 "Kicking stuck semaphore on %s",
2877 I915_WRITE_CTL(ring
, tmp
);
2878 return HANGCHECK_KICK
;
2880 return HANGCHECK_WAIT
;
2884 return HANGCHECK_HUNG
;
2888 * This is called when the chip hasn't reported back with completed
2889 * batchbuffers in a long time. We keep track per ring seqno progress and
2890 * if there are no progress, hangcheck score for that ring is increased.
2891 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2892 * we kick the ring. If we see no progress on three subsequent calls
2893 * we assume chip is wedged and try to fix it by resetting the chip.
2895 static void i915_hangcheck_elapsed(struct work_struct
*work
)
2897 struct drm_i915_private
*dev_priv
=
2898 container_of(work
, typeof(*dev_priv
),
2899 gpu_error
.hangcheck_work
.work
);
2900 struct drm_device
*dev
= dev_priv
->dev
;
2901 struct intel_engine_cs
*ring
;
2903 int busy_count
= 0, rings_hung
= 0;
2904 bool stuck
[I915_NUM_RINGS
] = { 0 };
2909 if (!i915
.enable_hangcheck
)
2912 for_each_ring(ring
, dev_priv
, i
) {
2917 semaphore_clear_deadlocks(dev_priv
);
2919 seqno
= ring
->get_seqno(ring
, false);
2920 acthd
= intel_ring_get_active_head(ring
);
2922 if (ring
->hangcheck
.seqno
== seqno
) {
2923 if (ring_idle(ring
, seqno
)) {
2924 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2926 if (waitqueue_active(&ring
->irq_queue
)) {
2927 /* Issue a wake-up to catch stuck h/w. */
2928 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2929 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2930 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2933 DRM_INFO("Fake missed irq on %s\n",
2935 wake_up_all(&ring
->irq_queue
);
2937 /* Safeguard against driver failure */
2938 ring
->hangcheck
.score
+= BUSY
;
2942 /* We always increment the hangcheck score
2943 * if the ring is busy and still processing
2944 * the same request, so that no single request
2945 * can run indefinitely (such as a chain of
2946 * batches). The only time we do not increment
2947 * the hangcheck score on this ring, if this
2948 * ring is in a legitimate wait for another
2949 * ring. In that case the waiting ring is a
2950 * victim and we want to be sure we catch the
2951 * right culprit. Then every time we do kick
2952 * the ring, add a small increment to the
2953 * score so that we can catch a batch that is
2954 * being repeatedly kicked and so responsible
2955 * for stalling the machine.
2957 ring
->hangcheck
.action
= ring_stuck(ring
,
2960 switch (ring
->hangcheck
.action
) {
2961 case HANGCHECK_IDLE
:
2962 case HANGCHECK_WAIT
:
2963 case HANGCHECK_ACTIVE
:
2965 case HANGCHECK_ACTIVE_LOOP
:
2966 ring
->hangcheck
.score
+= BUSY
;
2968 case HANGCHECK_KICK
:
2969 ring
->hangcheck
.score
+= KICK
;
2971 case HANGCHECK_HUNG
:
2972 ring
->hangcheck
.score
+= HUNG
;
2978 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2980 /* Gradually reduce the count so that we catch DoS
2981 * attempts across multiple batches.
2983 if (ring
->hangcheck
.score
> 0)
2984 ring
->hangcheck
.score
--;
2986 ring
->hangcheck
.acthd
= ring
->hangcheck
.max_acthd
= 0;
2989 ring
->hangcheck
.seqno
= seqno
;
2990 ring
->hangcheck
.acthd
= acthd
;
2994 for_each_ring(ring
, dev_priv
, i
) {
2995 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
2996 DRM_INFO("%s on %s\n",
2997 stuck
[i
] ? "stuck" : "no progress",
3004 return i915_handle_error(dev
, true, "Ring hung");
3007 /* Reset timer case chip hangs without another request
3009 i915_queue_hangcheck(dev
);
3012 void i915_queue_hangcheck(struct drm_device
*dev
)
3014 struct i915_gpu_error
*e
= &to_i915(dev
)->gpu_error
;
3016 if (!i915
.enable_hangcheck
)
3019 /* Don't continually defer the hangcheck so that it is always run at
3020 * least once after work has been scheduled on any ring. Otherwise,
3021 * we will ignore a hung ring if a second ring is kept busy.
3024 queue_delayed_work(e
->hangcheck_wq
, &e
->hangcheck_work
,
3025 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
));
3028 static void ibx_irq_reset(struct drm_device
*dev
)
3030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3032 if (HAS_PCH_NOP(dev
))
3035 GEN5_IRQ_RESET(SDE
);
3037 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3038 I915_WRITE(SERR_INT
, 0xffffffff);
3042 * SDEIER is also touched by the interrupt handler to work around missed PCH
3043 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3044 * instead we unconditionally enable all PCH interrupt sources here, but then
3045 * only unmask them as needed with SDEIMR.
3047 * This function needs to be called before interrupts are enabled.
3049 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3053 if (HAS_PCH_NOP(dev
))
3056 WARN_ON(I915_READ(SDEIER
) != 0);
3057 I915_WRITE(SDEIER
, 0xffffffff);
3058 POSTING_READ(SDEIER
);
3061 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3066 if (INTEL_INFO(dev
)->gen
>= 6)
3067 GEN5_IRQ_RESET(GEN6_PM
);
3072 static void ironlake_irq_reset(struct drm_device
*dev
)
3074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3076 I915_WRITE(HWSTAM
, 0xffffffff);
3080 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3082 gen5_gt_irq_reset(dev
);
3087 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3091 i915_hotplug_interrupt_update(dev_priv
, 0xFFFFFFFF, 0);
3092 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3094 for_each_pipe(dev_priv
, pipe
)
3095 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3097 GEN5_IRQ_RESET(VLV_
);
3100 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3105 I915_WRITE(VLV_IMR
, 0);
3106 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3107 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3108 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3110 gen5_gt_irq_reset(dev
);
3112 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3114 vlv_display_irq_reset(dev_priv
);
3117 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3119 GEN8_IRQ_RESET_NDX(GT
, 0);
3120 GEN8_IRQ_RESET_NDX(GT
, 1);
3121 GEN8_IRQ_RESET_NDX(GT
, 2);
3122 GEN8_IRQ_RESET_NDX(GT
, 3);
3125 static void gen8_irq_reset(struct drm_device
*dev
)
3127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3130 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3131 POSTING_READ(GEN8_MASTER_IRQ
);
3133 gen8_gt_irq_reset(dev_priv
);
3135 for_each_pipe(dev_priv
, pipe
)
3136 if (intel_display_power_is_enabled(dev_priv
,
3137 POWER_DOMAIN_PIPE(pipe
)))
3138 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3140 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3141 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3142 GEN5_IRQ_RESET(GEN8_PCU_
);
3144 if (HAS_PCH_SPLIT(dev
))
3148 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3149 unsigned int pipe_mask
)
3151 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3153 spin_lock_irq(&dev_priv
->irq_lock
);
3154 if (pipe_mask
& 1 << PIPE_A
)
3155 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_A
,
3156 dev_priv
->de_irq_mask
[PIPE_A
],
3157 ~dev_priv
->de_irq_mask
[PIPE_A
] | extra_ier
);
3158 if (pipe_mask
& 1 << PIPE_B
)
3159 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_B
,
3160 dev_priv
->de_irq_mask
[PIPE_B
],
3161 ~dev_priv
->de_irq_mask
[PIPE_B
] | extra_ier
);
3162 if (pipe_mask
& 1 << PIPE_C
)
3163 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_C
,
3164 dev_priv
->de_irq_mask
[PIPE_C
],
3165 ~dev_priv
->de_irq_mask
[PIPE_C
] | extra_ier
);
3166 spin_unlock_irq(&dev_priv
->irq_lock
);
3169 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3173 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3174 POSTING_READ(GEN8_MASTER_IRQ
);
3176 gen8_gt_irq_reset(dev_priv
);
3178 GEN5_IRQ_RESET(GEN8_PCU_
);
3180 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3182 vlv_display_irq_reset(dev_priv
);
3185 static u32
intel_hpd_enabled_irqs(struct drm_device
*dev
,
3186 const u32 hpd
[HPD_NUM_PINS
])
3188 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3189 struct intel_encoder
*encoder
;
3190 u32 enabled_irqs
= 0;
3192 for_each_intel_encoder(dev
, encoder
)
3193 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3194 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3196 return enabled_irqs
;
3199 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3202 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3204 if (HAS_PCH_IBX(dev
)) {
3205 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3206 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ibx
);
3208 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3209 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_cpt
);
3212 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3215 * Enable digital hotplug on the PCH, and configure the DP short pulse
3216 * duration to 2ms (which is the minimum in the Display Port spec).
3217 * The pulse duration bits are reserved on LPT+.
3219 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3220 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3221 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3222 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3223 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3225 * When CPU and PCH are on the same package, port A
3226 * HPD must be enabled in both north and south.
3228 if (HAS_PCH_LPT_LP(dev
))
3229 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3230 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3233 static void spt_hpd_irq_setup(struct drm_device
*dev
)
3235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3236 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3238 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3239 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_spt
);
3241 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3243 /* Enable digital hotplug on the PCH */
3244 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3245 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3246 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3247 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3249 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3250 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3251 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3254 static void ilk_hpd_irq_setup(struct drm_device
*dev
)
3256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3257 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3259 if (INTEL_INFO(dev
)->gen
>= 8) {
3260 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3261 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_bdw
);
3263 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3264 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3265 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3266 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ivb
);
3268 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3270 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3271 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ilk
);
3273 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3277 * Enable digital hotplug on the CPU, and configure the DP short pulse
3278 * duration to 2ms (which is the minimum in the Display Port spec)
3279 * The pulse duration bits are reserved on HSW+.
3281 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3282 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3283 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3284 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3286 ibx_hpd_irq_setup(dev
);
3289 static void bxt_hpd_irq_setup(struct drm_device
*dev
)
3291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3292 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3294 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_bxt
);
3295 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3297 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3299 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3300 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3301 PORTA_HOTPLUG_ENABLE
;
3302 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3305 static void ibx_irq_postinstall(struct drm_device
*dev
)
3307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3310 if (HAS_PCH_NOP(dev
))
3313 if (HAS_PCH_IBX(dev
))
3314 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3316 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3318 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3319 I915_WRITE(SDEIMR
, ~mask
);
3322 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3325 u32 pm_irqs
, gt_irqs
;
3327 pm_irqs
= gt_irqs
= 0;
3329 dev_priv
->gt_irq_mask
= ~0;
3330 if (HAS_L3_DPF(dev
)) {
3331 /* L3 parity interrupt is always unmasked. */
3332 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3333 gt_irqs
|= GT_PARITY_ERROR(dev
);
3336 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3338 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3339 ILK_BSD_USER_INTERRUPT
;
3341 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3344 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3346 if (INTEL_INFO(dev
)->gen
>= 6) {
3348 * RPS interrupts will get enabled/disabled on demand when RPS
3349 * itself is enabled/disabled.
3352 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3354 dev_priv
->pm_irq_mask
= 0xffffffff;
3355 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3359 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3362 u32 display_mask
, extra_mask
;
3364 if (INTEL_INFO(dev
)->gen
>= 7) {
3365 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3366 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3367 DE_PLANEB_FLIP_DONE_IVB
|
3368 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3369 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3370 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3371 DE_DP_A_HOTPLUG_IVB
);
3373 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3374 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3376 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3378 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3379 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3383 dev_priv
->irq_mask
= ~display_mask
;
3385 I915_WRITE(HWSTAM
, 0xeffe);
3387 ibx_irq_pre_postinstall(dev
);
3389 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3391 gen5_gt_irq_postinstall(dev
);
3393 ibx_irq_postinstall(dev
);
3395 if (IS_IRONLAKE_M(dev
)) {
3396 /* Enable PCU event interrupts
3398 * spinlocking not required here for correctness since interrupt
3399 * setup is guaranteed to run in single-threaded context. But we
3400 * need it to make the assert_spin_locked happy. */
3401 spin_lock_irq(&dev_priv
->irq_lock
);
3402 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3403 spin_unlock_irq(&dev_priv
->irq_lock
);
3409 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3415 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3416 PIPE_FIFO_UNDERRUN_STATUS
;
3418 for_each_pipe(dev_priv
, pipe
)
3419 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3420 POSTING_READ(PIPESTAT(PIPE_A
));
3422 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3423 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3425 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3426 for_each_pipe(dev_priv
, pipe
)
3427 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3429 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3430 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3431 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3432 if (IS_CHERRYVIEW(dev_priv
))
3433 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3434 dev_priv
->irq_mask
&= ~iir_mask
;
3436 I915_WRITE(VLV_IIR
, iir_mask
);
3437 I915_WRITE(VLV_IIR
, iir_mask
);
3438 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3439 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3440 POSTING_READ(VLV_IMR
);
3443 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3449 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3450 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3451 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3452 if (IS_CHERRYVIEW(dev_priv
))
3453 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3455 dev_priv
->irq_mask
|= iir_mask
;
3456 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3457 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3458 I915_WRITE(VLV_IIR
, iir_mask
);
3459 I915_WRITE(VLV_IIR
, iir_mask
);
3460 POSTING_READ(VLV_IIR
);
3462 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3463 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3465 i915_disable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3466 for_each_pipe(dev_priv
, pipe
)
3467 i915_disable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3469 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3470 PIPE_FIFO_UNDERRUN_STATUS
;
3472 for_each_pipe(dev_priv
, pipe
)
3473 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3474 POSTING_READ(PIPESTAT(PIPE_A
));
3477 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3479 assert_spin_locked(&dev_priv
->irq_lock
);
3481 if (dev_priv
->display_irqs_enabled
)
3484 dev_priv
->display_irqs_enabled
= true;
3486 if (intel_irqs_enabled(dev_priv
))
3487 valleyview_display_irqs_install(dev_priv
);
3490 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3492 assert_spin_locked(&dev_priv
->irq_lock
);
3494 if (!dev_priv
->display_irqs_enabled
)
3497 dev_priv
->display_irqs_enabled
= false;
3499 if (intel_irqs_enabled(dev_priv
))
3500 valleyview_display_irqs_uninstall(dev_priv
);
3503 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3505 dev_priv
->irq_mask
= ~0;
3507 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3508 POSTING_READ(PORT_HOTPLUG_EN
);
3510 I915_WRITE(VLV_IIR
, 0xffffffff);
3511 I915_WRITE(VLV_IIR
, 0xffffffff);
3512 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3513 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3514 POSTING_READ(VLV_IMR
);
3516 /* Interrupt setup is already guaranteed to be single-threaded, this is
3517 * just to make the assert_spin_locked check happy. */
3518 spin_lock_irq(&dev_priv
->irq_lock
);
3519 if (dev_priv
->display_irqs_enabled
)
3520 valleyview_display_irqs_install(dev_priv
);
3521 spin_unlock_irq(&dev_priv
->irq_lock
);
3524 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3528 vlv_display_irq_postinstall(dev_priv
);
3530 gen5_gt_irq_postinstall(dev
);
3532 /* ack & enable invalid PTE error interrupts */
3533 #if 0 /* FIXME: add support to irq handler for checking these bits */
3534 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3535 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3538 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3543 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3545 /* These are interrupts we'll toggle with the ring mask register */
3546 uint32_t gt_interrupts
[] = {
3547 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3548 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3549 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3550 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3551 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3552 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3553 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3554 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3555 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3557 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3558 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3561 dev_priv
->pm_irq_mask
= 0xffffffff;
3562 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3563 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3565 * RPS interrupts will get enabled/disabled on demand when RPS itself
3566 * is enabled/disabled.
3568 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3569 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3572 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3574 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3575 uint32_t de_pipe_enables
;
3576 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3577 u32 de_port_enables
;
3580 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3581 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3582 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3583 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3585 if (IS_BROXTON(dev_priv
))
3586 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3588 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3589 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3592 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3593 GEN8_PIPE_FIFO_UNDERRUN
;
3595 de_port_enables
= de_port_masked
;
3596 if (IS_BROXTON(dev_priv
))
3597 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3598 else if (IS_BROADWELL(dev_priv
))
3599 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3601 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3602 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3603 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3605 for_each_pipe(dev_priv
, pipe
)
3606 if (intel_display_power_is_enabled(dev_priv
,
3607 POWER_DOMAIN_PIPE(pipe
)))
3608 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3609 dev_priv
->de_irq_mask
[pipe
],
3612 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3615 static int gen8_irq_postinstall(struct drm_device
*dev
)
3617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3619 if (HAS_PCH_SPLIT(dev
))
3620 ibx_irq_pre_postinstall(dev
);
3622 gen8_gt_irq_postinstall(dev_priv
);
3623 gen8_de_irq_postinstall(dev_priv
);
3625 if (HAS_PCH_SPLIT(dev
))
3626 ibx_irq_postinstall(dev
);
3628 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3629 POSTING_READ(GEN8_MASTER_IRQ
);
3634 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3638 vlv_display_irq_postinstall(dev_priv
);
3640 gen8_gt_irq_postinstall(dev_priv
);
3642 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3643 POSTING_READ(GEN8_MASTER_IRQ
);
3648 static void gen8_irq_uninstall(struct drm_device
*dev
)
3650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3655 gen8_irq_reset(dev
);
3658 static void vlv_display_irq_uninstall(struct drm_i915_private
*dev_priv
)
3660 /* Interrupt setup is already guaranteed to be single-threaded, this is
3661 * just to make the assert_spin_locked check happy. */
3662 spin_lock_irq(&dev_priv
->irq_lock
);
3663 if (dev_priv
->display_irqs_enabled
)
3664 valleyview_display_irqs_uninstall(dev_priv
);
3665 spin_unlock_irq(&dev_priv
->irq_lock
);
3667 vlv_display_irq_reset(dev_priv
);
3669 dev_priv
->irq_mask
= ~0;
3672 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3679 I915_WRITE(VLV_MASTER_IER
, 0);
3681 gen5_gt_irq_reset(dev
);
3683 I915_WRITE(HWSTAM
, 0xffffffff);
3685 vlv_display_irq_uninstall(dev_priv
);
3688 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3696 POSTING_READ(GEN8_MASTER_IRQ
);
3698 gen8_gt_irq_reset(dev_priv
);
3700 GEN5_IRQ_RESET(GEN8_PCU_
);
3702 vlv_display_irq_uninstall(dev_priv
);
3705 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3712 ironlake_irq_reset(dev
);
3715 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3720 for_each_pipe(dev_priv
, pipe
)
3721 I915_WRITE(PIPESTAT(pipe
), 0);
3722 I915_WRITE16(IMR
, 0xffff);
3723 I915_WRITE16(IER
, 0x0);
3724 POSTING_READ16(IER
);
3727 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3732 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3734 /* Unmask the interrupts that we always want on. */
3735 dev_priv
->irq_mask
=
3736 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3737 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3738 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3739 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3740 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3743 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3744 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3745 I915_USER_INTERRUPT
);
3746 POSTING_READ16(IER
);
3748 /* Interrupt setup is already guaranteed to be single-threaded, this is
3749 * just to make the assert_spin_locked check happy. */
3750 spin_lock_irq(&dev_priv
->irq_lock
);
3751 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3752 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3753 spin_unlock_irq(&dev_priv
->irq_lock
);
3759 * Returns true when a page flip has completed.
3761 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3762 int plane
, int pipe
, u32 iir
)
3764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3765 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3767 if (!intel_pipe_handle_vblank(dev
, pipe
))
3770 if ((iir
& flip_pending
) == 0)
3771 goto check_page_flip
;
3773 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3774 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3775 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3776 * the flip is completed (no longer pending). Since this doesn't raise
3777 * an interrupt per se, we watch for the change at vblank.
3779 if (I915_READ16(ISR
) & flip_pending
)
3780 goto check_page_flip
;
3782 intel_prepare_page_flip(dev
, plane
);
3783 intel_finish_page_flip(dev
, pipe
);
3787 intel_check_page_flip(dev
, pipe
);
3791 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3793 struct drm_device
*dev
= arg
;
3794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3799 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3800 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3802 if (!intel_irqs_enabled(dev_priv
))
3805 iir
= I915_READ16(IIR
);
3809 while (iir
& ~flip_mask
) {
3810 /* Can't rely on pipestat interrupt bit in iir as it might
3811 * have been cleared after the pipestat interrupt was received.
3812 * It doesn't set the bit in iir again, but it still produces
3813 * interrupts (for non-MSI).
3815 spin_lock(&dev_priv
->irq_lock
);
3816 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3817 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3819 for_each_pipe(dev_priv
, pipe
) {
3820 int reg
= PIPESTAT(pipe
);
3821 pipe_stats
[pipe
] = I915_READ(reg
);
3824 * Clear the PIPE*STAT regs before the IIR
3826 if (pipe_stats
[pipe
] & 0x8000ffff)
3827 I915_WRITE(reg
, pipe_stats
[pipe
]);
3829 spin_unlock(&dev_priv
->irq_lock
);
3831 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3832 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3834 if (iir
& I915_USER_INTERRUPT
)
3835 notify_ring(&dev_priv
->ring
[RCS
]);
3837 for_each_pipe(dev_priv
, pipe
) {
3842 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3843 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3844 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3846 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3847 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3849 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3850 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3860 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3865 for_each_pipe(dev_priv
, pipe
) {
3866 /* Clear enable bits; then clear status bits */
3867 I915_WRITE(PIPESTAT(pipe
), 0);
3868 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3870 I915_WRITE16(IMR
, 0xffff);
3871 I915_WRITE16(IER
, 0x0);
3872 I915_WRITE16(IIR
, I915_READ16(IIR
));
3875 static void i915_irq_preinstall(struct drm_device
* dev
)
3877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3880 if (I915_HAS_HOTPLUG(dev
)) {
3881 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3882 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3885 I915_WRITE16(HWSTAM
, 0xeffe);
3886 for_each_pipe(dev_priv
, pipe
)
3887 I915_WRITE(PIPESTAT(pipe
), 0);
3888 I915_WRITE(IMR
, 0xffffffff);
3889 I915_WRITE(IER
, 0x0);
3893 static int i915_irq_postinstall(struct drm_device
*dev
)
3895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3898 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3900 /* Unmask the interrupts that we always want on. */
3901 dev_priv
->irq_mask
=
3902 ~(I915_ASLE_INTERRUPT
|
3903 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3904 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3905 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3906 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3909 I915_ASLE_INTERRUPT
|
3910 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3911 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3912 I915_USER_INTERRUPT
;
3914 if (I915_HAS_HOTPLUG(dev
)) {
3915 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3916 POSTING_READ(PORT_HOTPLUG_EN
);
3918 /* Enable in IER... */
3919 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3920 /* and unmask in IMR */
3921 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3924 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3925 I915_WRITE(IER
, enable_mask
);
3928 i915_enable_asle_pipestat(dev
);
3930 /* Interrupt setup is already guaranteed to be single-threaded, this is
3931 * just to make the assert_spin_locked check happy. */
3932 spin_lock_irq(&dev_priv
->irq_lock
);
3933 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3934 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3935 spin_unlock_irq(&dev_priv
->irq_lock
);
3941 * Returns true when a page flip has completed.
3943 static bool i915_handle_vblank(struct drm_device
*dev
,
3944 int plane
, int pipe
, u32 iir
)
3946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3947 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3949 if (!intel_pipe_handle_vblank(dev
, pipe
))
3952 if ((iir
& flip_pending
) == 0)
3953 goto check_page_flip
;
3955 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3956 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3957 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3958 * the flip is completed (no longer pending). Since this doesn't raise
3959 * an interrupt per se, we watch for the change at vblank.
3961 if (I915_READ(ISR
) & flip_pending
)
3962 goto check_page_flip
;
3964 intel_prepare_page_flip(dev
, plane
);
3965 intel_finish_page_flip(dev
, pipe
);
3969 intel_check_page_flip(dev
, pipe
);
3973 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3975 struct drm_device
*dev
= arg
;
3976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3977 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3979 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3980 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3981 int pipe
, ret
= IRQ_NONE
;
3983 if (!intel_irqs_enabled(dev_priv
))
3986 iir
= I915_READ(IIR
);
3988 bool irq_received
= (iir
& ~flip_mask
) != 0;
3989 bool blc_event
= false;
3991 /* Can't rely on pipestat interrupt bit in iir as it might
3992 * have been cleared after the pipestat interrupt was received.
3993 * It doesn't set the bit in iir again, but it still produces
3994 * interrupts (for non-MSI).
3996 spin_lock(&dev_priv
->irq_lock
);
3997 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3998 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4000 for_each_pipe(dev_priv
, pipe
) {
4001 int reg
= PIPESTAT(pipe
);
4002 pipe_stats
[pipe
] = I915_READ(reg
);
4004 /* Clear the PIPE*STAT regs before the IIR */
4005 if (pipe_stats
[pipe
] & 0x8000ffff) {
4006 I915_WRITE(reg
, pipe_stats
[pipe
]);
4007 irq_received
= true;
4010 spin_unlock(&dev_priv
->irq_lock
);
4015 /* Consume port. Then clear IIR or we'll miss events */
4016 if (I915_HAS_HOTPLUG(dev
) &&
4017 iir
& I915_DISPLAY_PORT_INTERRUPT
)
4018 i9xx_hpd_irq_handler(dev
);
4020 I915_WRITE(IIR
, iir
& ~flip_mask
);
4021 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4023 if (iir
& I915_USER_INTERRUPT
)
4024 notify_ring(&dev_priv
->ring
[RCS
]);
4026 for_each_pipe(dev_priv
, pipe
) {
4031 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4032 i915_handle_vblank(dev
, plane
, pipe
, iir
))
4033 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4035 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4038 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4039 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4041 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4042 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4046 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4047 intel_opregion_asle_intr(dev
);
4049 /* With MSI, interrupts are only generated when iir
4050 * transitions from zero to nonzero. If another bit got
4051 * set while we were handling the existing iir bits, then
4052 * we would never get another interrupt.
4054 * This is fine on non-MSI as well, as if we hit this path
4055 * we avoid exiting the interrupt handler only to generate
4058 * Note that for MSI this could cause a stray interrupt report
4059 * if an interrupt landed in the time between writing IIR and
4060 * the posting read. This should be rare enough to never
4061 * trigger the 99% of 100,000 interrupts test for disabling
4066 } while (iir
& ~flip_mask
);
4071 static void i915_irq_uninstall(struct drm_device
* dev
)
4073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4076 if (I915_HAS_HOTPLUG(dev
)) {
4077 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4078 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4081 I915_WRITE16(HWSTAM
, 0xffff);
4082 for_each_pipe(dev_priv
, pipe
) {
4083 /* Clear enable bits; then clear status bits */
4084 I915_WRITE(PIPESTAT(pipe
), 0);
4085 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4087 I915_WRITE(IMR
, 0xffffffff);
4088 I915_WRITE(IER
, 0x0);
4090 I915_WRITE(IIR
, I915_READ(IIR
));
4093 static void i965_irq_preinstall(struct drm_device
* dev
)
4095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4098 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4099 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4101 I915_WRITE(HWSTAM
, 0xeffe);
4102 for_each_pipe(dev_priv
, pipe
)
4103 I915_WRITE(PIPESTAT(pipe
), 0);
4104 I915_WRITE(IMR
, 0xffffffff);
4105 I915_WRITE(IER
, 0x0);
4109 static int i965_irq_postinstall(struct drm_device
*dev
)
4111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4115 /* Unmask the interrupts that we always want on. */
4116 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4117 I915_DISPLAY_PORT_INTERRUPT
|
4118 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4119 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4120 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4121 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4122 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4124 enable_mask
= ~dev_priv
->irq_mask
;
4125 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4126 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4127 enable_mask
|= I915_USER_INTERRUPT
;
4130 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4132 /* Interrupt setup is already guaranteed to be single-threaded, this is
4133 * just to make the assert_spin_locked check happy. */
4134 spin_lock_irq(&dev_priv
->irq_lock
);
4135 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4136 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4137 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4138 spin_unlock_irq(&dev_priv
->irq_lock
);
4141 * Enable some error detection, note the instruction error mask
4142 * bit is reserved, so we leave it masked.
4145 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4146 GM45_ERROR_MEM_PRIV
|
4147 GM45_ERROR_CP_PRIV
|
4148 I915_ERROR_MEMORY_REFRESH
);
4150 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4151 I915_ERROR_MEMORY_REFRESH
);
4153 I915_WRITE(EMR
, error_mask
);
4155 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4156 I915_WRITE(IER
, enable_mask
);
4159 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4160 POSTING_READ(PORT_HOTPLUG_EN
);
4162 i915_enable_asle_pipestat(dev
);
4167 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4172 assert_spin_locked(&dev_priv
->irq_lock
);
4174 /* Note HDMI and DP share hotplug bits */
4175 /* enable bits are the same for all generations */
4176 hotplug_en
= intel_hpd_enabled_irqs(dev
, hpd_mask_i915
);
4177 /* Programming the CRT detection parameters tends
4178 to generate a spurious hotplug event about three
4179 seconds later. So just do it once.
4182 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4183 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4185 /* Ignore TV since it's buggy */
4186 i915_hotplug_interrupt_update_locked(dev_priv
,
4187 (HOTPLUG_INT_EN_MASK
4188 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
),
4192 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4194 struct drm_device
*dev
= arg
;
4195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4197 u32 pipe_stats
[I915_MAX_PIPES
];
4198 int ret
= IRQ_NONE
, pipe
;
4200 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4201 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4203 if (!intel_irqs_enabled(dev_priv
))
4206 iir
= I915_READ(IIR
);
4209 bool irq_received
= (iir
& ~flip_mask
) != 0;
4210 bool blc_event
= false;
4212 /* Can't rely on pipestat interrupt bit in iir as it might
4213 * have been cleared after the pipestat interrupt was received.
4214 * It doesn't set the bit in iir again, but it still produces
4215 * interrupts (for non-MSI).
4217 spin_lock(&dev_priv
->irq_lock
);
4218 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4219 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4221 for_each_pipe(dev_priv
, pipe
) {
4222 int reg
= PIPESTAT(pipe
);
4223 pipe_stats
[pipe
] = I915_READ(reg
);
4226 * Clear the PIPE*STAT regs before the IIR
4228 if (pipe_stats
[pipe
] & 0x8000ffff) {
4229 I915_WRITE(reg
, pipe_stats
[pipe
]);
4230 irq_received
= true;
4233 spin_unlock(&dev_priv
->irq_lock
);
4240 /* Consume port. Then clear IIR or we'll miss events */
4241 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4242 i9xx_hpd_irq_handler(dev
);
4244 I915_WRITE(IIR
, iir
& ~flip_mask
);
4245 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4247 if (iir
& I915_USER_INTERRUPT
)
4248 notify_ring(&dev_priv
->ring
[RCS
]);
4249 if (iir
& I915_BSD_USER_INTERRUPT
)
4250 notify_ring(&dev_priv
->ring
[VCS
]);
4252 for_each_pipe(dev_priv
, pipe
) {
4253 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4254 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4255 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4257 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4260 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4261 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4263 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4264 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4267 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4268 intel_opregion_asle_intr(dev
);
4270 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4271 gmbus_irq_handler(dev
);
4273 /* With MSI, interrupts are only generated when iir
4274 * transitions from zero to nonzero. If another bit got
4275 * set while we were handling the existing iir bits, then
4276 * we would never get another interrupt.
4278 * This is fine on non-MSI as well, as if we hit this path
4279 * we avoid exiting the interrupt handler only to generate
4282 * Note that for MSI this could cause a stray interrupt report
4283 * if an interrupt landed in the time between writing IIR and
4284 * the posting read. This should be rare enough to never
4285 * trigger the 99% of 100,000 interrupts test for disabling
4294 static void i965_irq_uninstall(struct drm_device
* dev
)
4296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4302 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4303 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4305 I915_WRITE(HWSTAM
, 0xffffffff);
4306 for_each_pipe(dev_priv
, pipe
)
4307 I915_WRITE(PIPESTAT(pipe
), 0);
4308 I915_WRITE(IMR
, 0xffffffff);
4309 I915_WRITE(IER
, 0x0);
4311 for_each_pipe(dev_priv
, pipe
)
4312 I915_WRITE(PIPESTAT(pipe
),
4313 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4314 I915_WRITE(IIR
, I915_READ(IIR
));
4318 * intel_irq_init - initializes irq support
4319 * @dev_priv: i915 device instance
4321 * This function initializes all the irq support including work items, timers
4322 * and all the vtables. It does not setup the interrupt itself though.
4324 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4326 struct drm_device
*dev
= dev_priv
->dev
;
4328 intel_hpd_init_work(dev_priv
);
4330 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4331 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4333 /* Let's track the enabled rps events */
4334 if (IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
4335 /* WaGsvRC0ResidencyMethod:vlv */
4336 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4338 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4340 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4341 i915_hangcheck_elapsed
);
4343 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4345 if (IS_GEN2(dev_priv
)) {
4346 dev
->max_vblank_count
= 0;
4347 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4348 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4349 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4350 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4352 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4353 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4357 * Opt out of the vblank disable timer on everything except gen2.
4358 * Gen2 doesn't have a hardware frame counter and so depends on
4359 * vblank interrupts to produce sane vblank seuquence numbers.
4361 if (!IS_GEN2(dev_priv
))
4362 dev
->vblank_disable_immediate
= true;
4364 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4365 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4367 if (IS_CHERRYVIEW(dev_priv
)) {
4368 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4369 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4370 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4371 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4372 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4373 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4374 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4375 } else if (IS_VALLEYVIEW(dev_priv
)) {
4376 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4377 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4378 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4379 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4380 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4381 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4382 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4383 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4384 dev
->driver
->irq_handler
= gen8_irq_handler
;
4385 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4386 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4387 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4388 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4389 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4390 if (IS_BROXTON(dev
))
4391 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4392 else if (HAS_PCH_SPT(dev
))
4393 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4395 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4396 } else if (HAS_PCH_SPLIT(dev
)) {
4397 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4398 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4399 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4400 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4401 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4402 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4403 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4405 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4406 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4407 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4408 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4409 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4410 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4411 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4412 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4413 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4414 dev
->driver
->irq_handler
= i915_irq_handler
;
4416 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4417 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4418 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4419 dev
->driver
->irq_handler
= i965_irq_handler
;
4421 if (I915_HAS_HOTPLUG(dev_priv
))
4422 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4423 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4424 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4429 * intel_irq_install - enables the hardware interrupt
4430 * @dev_priv: i915 device instance
4432 * This function enables the hardware interrupt handling, but leaves the hotplug
4433 * handling still disabled. It is called after intel_irq_init().
4435 * In the driver load and resume code we need working interrupts in a few places
4436 * but don't want to deal with the hassle of concurrent probe and hotplug
4437 * workers. Hence the split into this two-stage approach.
4439 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4442 * We enable some interrupt sources in our postinstall hooks, so mark
4443 * interrupts as enabled _before_ actually enabling them to avoid
4444 * special cases in our ordering checks.
4446 dev_priv
->pm
.irqs_enabled
= true;
4448 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4452 * intel_irq_uninstall - finilizes all irq handling
4453 * @dev_priv: i915 device instance
4455 * This stops interrupt and hotplug handling and unregisters and frees all
4456 * resources acquired in the init functions.
4458 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4460 drm_irq_uninstall(dev_priv
->dev
);
4461 intel_hpd_cancel_work(dev_priv
);
4462 dev_priv
->pm
.irqs_enabled
= false;
4466 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4467 * @dev_priv: i915 device instance
4469 * This function is used to disable interrupts at runtime, both in the runtime
4470 * pm and the system suspend/resume code.
4472 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4474 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4475 dev_priv
->pm
.irqs_enabled
= false;
4476 synchronize_irq(dev_priv
->dev
->irq
);
4480 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4481 * @dev_priv: i915 device instance
4483 * This function is used to enable interrupts at runtime, both in the runtime
4484 * pm and the system suspend/resume code.
4486 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4488 dev_priv
->pm
.irqs_enabled
= true;
4489 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4490 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);