1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_irq.h>
38 #include "display/intel_display_types.h"
39 #include "display/intel_fifo_underrun.h"
40 #include "display/intel_hotplug.h"
41 #include "display/intel_lpe_audio.h"
42 #include "display/intel_psr.h"
44 #include "gt/intel_breadcrumbs.h"
45 #include "gt/intel_gt.h"
46 #include "gt/intel_gt_irq.h"
47 #include "gt/intel_gt_pm_irq.h"
48 #include "gt/intel_rps.h"
52 #include "i915_trace.h"
56 * DOC: interrupt handling
58 * These functions provide the basic support for enabling and disabling the
59 * interrupt handling support. There's a lot more functionality in i915_irq.c
60 * and related files, but that will be described in separate chapters.
63 typedef bool (*long_pulse_detect_func
)(enum hpd_pin pin
, u32 val
);
65 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
66 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
69 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
70 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
73 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
74 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
77 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
78 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
79 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
80 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
81 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
82 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
,
85 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
86 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
87 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
88 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
89 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
90 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
93 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
94 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
95 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
96 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
97 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
98 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
,
101 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
102 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
103 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
104 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
105 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
106 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
107 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
,
110 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
111 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
112 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
113 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
114 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
115 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
116 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
,
119 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
120 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
121 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
122 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
123 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
124 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
125 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
,
128 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
129 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
130 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
131 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
,
134 static const u32 hpd_gen11
[HPD_NUM_PINS
] = {
135 [HPD_PORT_TC1
] = GEN11_TC_HOTPLUG(PORT_TC1
) | GEN11_TBT_HOTPLUG(PORT_TC1
),
136 [HPD_PORT_TC2
] = GEN11_TC_HOTPLUG(PORT_TC2
) | GEN11_TBT_HOTPLUG(PORT_TC2
),
137 [HPD_PORT_TC3
] = GEN11_TC_HOTPLUG(PORT_TC3
) | GEN11_TBT_HOTPLUG(PORT_TC3
),
138 [HPD_PORT_TC4
] = GEN11_TC_HOTPLUG(PORT_TC4
) | GEN11_TBT_HOTPLUG(PORT_TC4
),
139 [HPD_PORT_TC5
] = GEN11_TC_HOTPLUG(PORT_TC5
) | GEN11_TBT_HOTPLUG(PORT_TC5
),
140 [HPD_PORT_TC6
] = GEN11_TC_HOTPLUG(PORT_TC6
) | GEN11_TBT_HOTPLUG(PORT_TC6
),
143 static const u32 hpd_icp
[HPD_NUM_PINS
] = {
144 [HPD_PORT_A
] = SDE_DDI_HOTPLUG_ICP(PORT_A
),
145 [HPD_PORT_B
] = SDE_DDI_HOTPLUG_ICP(PORT_B
),
146 [HPD_PORT_C
] = SDE_DDI_HOTPLUG_ICP(PORT_C
),
147 [HPD_PORT_TC1
] = SDE_TC_HOTPLUG_ICP(PORT_TC1
),
148 [HPD_PORT_TC2
] = SDE_TC_HOTPLUG_ICP(PORT_TC2
),
149 [HPD_PORT_TC3
] = SDE_TC_HOTPLUG_ICP(PORT_TC3
),
150 [HPD_PORT_TC4
] = SDE_TC_HOTPLUG_ICP(PORT_TC4
),
151 [HPD_PORT_TC5
] = SDE_TC_HOTPLUG_ICP(PORT_TC5
),
152 [HPD_PORT_TC6
] = SDE_TC_HOTPLUG_ICP(PORT_TC6
),
155 static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv
)
157 struct i915_hotplug
*hpd
= &dev_priv
->hotplug
;
159 if (HAS_GMCH(dev_priv
)) {
160 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
161 IS_CHERRYVIEW(dev_priv
))
162 hpd
->hpd
= hpd_status_g4x
;
164 hpd
->hpd
= hpd_status_i915
;
168 if (INTEL_GEN(dev_priv
) >= 11)
169 hpd
->hpd
= hpd_gen11
;
170 else if (IS_GEN9_LP(dev_priv
))
172 else if (INTEL_GEN(dev_priv
) >= 8)
174 else if (INTEL_GEN(dev_priv
) >= 7)
179 if (!HAS_PCH_SPLIT(dev_priv
) || HAS_PCH_NOP(dev_priv
))
182 if (HAS_PCH_TGP(dev_priv
) || HAS_PCH_JSP(dev_priv
) ||
183 HAS_PCH_ICP(dev_priv
) || HAS_PCH_MCC(dev_priv
))
184 hpd
->pch_hpd
= hpd_icp
;
185 else if (HAS_PCH_CNP(dev_priv
) || HAS_PCH_SPT(dev_priv
))
186 hpd
->pch_hpd
= hpd_spt
;
187 else if (HAS_PCH_LPT(dev_priv
) || HAS_PCH_CPT(dev_priv
))
188 hpd
->pch_hpd
= hpd_cpt
;
189 else if (HAS_PCH_IBX(dev_priv
))
190 hpd
->pch_hpd
= hpd_ibx
;
192 MISSING_CASE(INTEL_PCH_TYPE(dev_priv
));
196 intel_handle_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
198 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
200 drm_crtc_handle_vblank(&crtc
->base
);
203 void gen3_irq_reset(struct intel_uncore
*uncore
, i915_reg_t imr
,
204 i915_reg_t iir
, i915_reg_t ier
)
206 intel_uncore_write(uncore
, imr
, 0xffffffff);
207 intel_uncore_posting_read(uncore
, imr
);
209 intel_uncore_write(uncore
, ier
, 0);
211 /* IIR can theoretically queue up two events. Be paranoid. */
212 intel_uncore_write(uncore
, iir
, 0xffffffff);
213 intel_uncore_posting_read(uncore
, iir
);
214 intel_uncore_write(uncore
, iir
, 0xffffffff);
215 intel_uncore_posting_read(uncore
, iir
);
218 void gen2_irq_reset(struct intel_uncore
*uncore
)
220 intel_uncore_write16(uncore
, GEN2_IMR
, 0xffff);
221 intel_uncore_posting_read16(uncore
, GEN2_IMR
);
223 intel_uncore_write16(uncore
, GEN2_IER
, 0);
225 /* IIR can theoretically queue up two events. Be paranoid. */
226 intel_uncore_write16(uncore
, GEN2_IIR
, 0xffff);
227 intel_uncore_posting_read16(uncore
, GEN2_IIR
);
228 intel_uncore_write16(uncore
, GEN2_IIR
, 0xffff);
229 intel_uncore_posting_read16(uncore
, GEN2_IIR
);
233 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
235 static void gen3_assert_iir_is_zero(struct intel_uncore
*uncore
, i915_reg_t reg
)
237 u32 val
= intel_uncore_read(uncore
, reg
);
242 drm_WARN(&uncore
->i915
->drm
, 1,
243 "Interrupt register 0x%x is not zero: 0x%08x\n",
244 i915_mmio_reg_offset(reg
), val
);
245 intel_uncore_write(uncore
, reg
, 0xffffffff);
246 intel_uncore_posting_read(uncore
, reg
);
247 intel_uncore_write(uncore
, reg
, 0xffffffff);
248 intel_uncore_posting_read(uncore
, reg
);
251 static void gen2_assert_iir_is_zero(struct intel_uncore
*uncore
)
253 u16 val
= intel_uncore_read16(uncore
, GEN2_IIR
);
258 drm_WARN(&uncore
->i915
->drm
, 1,
259 "Interrupt register 0x%x is not zero: 0x%08x\n",
260 i915_mmio_reg_offset(GEN2_IIR
), val
);
261 intel_uncore_write16(uncore
, GEN2_IIR
, 0xffff);
262 intel_uncore_posting_read16(uncore
, GEN2_IIR
);
263 intel_uncore_write16(uncore
, GEN2_IIR
, 0xffff);
264 intel_uncore_posting_read16(uncore
, GEN2_IIR
);
267 void gen3_irq_init(struct intel_uncore
*uncore
,
268 i915_reg_t imr
, u32 imr_val
,
269 i915_reg_t ier
, u32 ier_val
,
272 gen3_assert_iir_is_zero(uncore
, iir
);
274 intel_uncore_write(uncore
, ier
, ier_val
);
275 intel_uncore_write(uncore
, imr
, imr_val
);
276 intel_uncore_posting_read(uncore
, imr
);
279 void gen2_irq_init(struct intel_uncore
*uncore
,
280 u32 imr_val
, u32 ier_val
)
282 gen2_assert_iir_is_zero(uncore
);
284 intel_uncore_write16(uncore
, GEN2_IER
, ier_val
);
285 intel_uncore_write16(uncore
, GEN2_IMR
, imr_val
);
286 intel_uncore_posting_read16(uncore
, GEN2_IMR
);
289 /* For display hotplug interrupt */
291 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
297 lockdep_assert_held(&dev_priv
->irq_lock
);
298 drm_WARN_ON(&dev_priv
->drm
, bits
& ~mask
);
300 val
= I915_READ(PORT_HOTPLUG_EN
);
303 I915_WRITE(PORT_HOTPLUG_EN
, val
);
307 * i915_hotplug_interrupt_update - update hotplug interrupt enable
308 * @dev_priv: driver private
309 * @mask: bits to update
310 * @bits: bits to enable
311 * NOTE: the HPD enable bits are modified both inside and outside
312 * of an interrupt context. To avoid that read-modify-write cycles
313 * interfer, these bits are protected by a spinlock. Since this
314 * function is usually not called from a context where the lock is
315 * held already, this function acquires the lock itself. A non-locking
316 * version is also available.
318 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
322 spin_lock_irq(&dev_priv
->irq_lock
);
323 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
324 spin_unlock_irq(&dev_priv
->irq_lock
);
328 * ilk_update_display_irq - update DEIMR
329 * @dev_priv: driver private
330 * @interrupt_mask: mask of interrupt bits to update
331 * @enabled_irq_mask: mask of interrupt bits to enable
333 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
335 u32 enabled_irq_mask
)
339 lockdep_assert_held(&dev_priv
->irq_lock
);
341 drm_WARN_ON(&dev_priv
->drm
, enabled_irq_mask
& ~interrupt_mask
);
343 if (drm_WARN_ON(&dev_priv
->drm
, !intel_irqs_enabled(dev_priv
)))
346 new_val
= dev_priv
->irq_mask
;
347 new_val
&= ~interrupt_mask
;
348 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
350 if (new_val
!= dev_priv
->irq_mask
) {
351 dev_priv
->irq_mask
= new_val
;
352 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
358 * bdw_update_port_irq - update DE port interrupt
359 * @dev_priv: driver private
360 * @interrupt_mask: mask of interrupt bits to update
361 * @enabled_irq_mask: mask of interrupt bits to enable
363 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
365 u32 enabled_irq_mask
)
370 lockdep_assert_held(&dev_priv
->irq_lock
);
372 drm_WARN_ON(&dev_priv
->drm
, enabled_irq_mask
& ~interrupt_mask
);
374 if (drm_WARN_ON(&dev_priv
->drm
, !intel_irqs_enabled(dev_priv
)))
377 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
380 new_val
&= ~interrupt_mask
;
381 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
383 if (new_val
!= old_val
) {
384 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
385 POSTING_READ(GEN8_DE_PORT_IMR
);
390 * bdw_update_pipe_irq - update DE pipe interrupt
391 * @dev_priv: driver private
392 * @pipe: pipe whose interrupt to update
393 * @interrupt_mask: mask of interrupt bits to update
394 * @enabled_irq_mask: mask of interrupt bits to enable
396 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
399 u32 enabled_irq_mask
)
403 lockdep_assert_held(&dev_priv
->irq_lock
);
405 drm_WARN_ON(&dev_priv
->drm
, enabled_irq_mask
& ~interrupt_mask
);
407 if (drm_WARN_ON(&dev_priv
->drm
, !intel_irqs_enabled(dev_priv
)))
410 new_val
= dev_priv
->de_irq_mask
[pipe
];
411 new_val
&= ~interrupt_mask
;
412 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
414 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
415 dev_priv
->de_irq_mask
[pipe
] = new_val
;
416 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
417 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
422 * ibx_display_interrupt_update - update SDEIMR
423 * @dev_priv: driver private
424 * @interrupt_mask: mask of interrupt bits to update
425 * @enabled_irq_mask: mask of interrupt bits to enable
427 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
429 u32 enabled_irq_mask
)
431 u32 sdeimr
= I915_READ(SDEIMR
);
432 sdeimr
&= ~interrupt_mask
;
433 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
435 drm_WARN_ON(&dev_priv
->drm
, enabled_irq_mask
& ~interrupt_mask
);
437 lockdep_assert_held(&dev_priv
->irq_lock
);
439 if (drm_WARN_ON(&dev_priv
->drm
, !intel_irqs_enabled(dev_priv
)))
442 I915_WRITE(SDEIMR
, sdeimr
);
443 POSTING_READ(SDEIMR
);
446 u32
i915_pipestat_enable_mask(struct drm_i915_private
*dev_priv
,
449 u32 status_mask
= dev_priv
->pipestat_irq_mask
[pipe
];
450 u32 enable_mask
= status_mask
<< 16;
452 lockdep_assert_held(&dev_priv
->irq_lock
);
454 if (INTEL_GEN(dev_priv
) < 5)
458 * On pipe A we don't support the PSR interrupt yet,
459 * on pipe B and C the same bit MBZ.
461 if (drm_WARN_ON_ONCE(&dev_priv
->drm
,
462 status_mask
& PIPE_A_PSR_STATUS_VLV
))
465 * On pipe B and C we don't support the PSR interrupt yet, on pipe
466 * A the same bit is for perf counters which we don't use either.
468 if (drm_WARN_ON_ONCE(&dev_priv
->drm
,
469 status_mask
& PIPE_B_PSR_STATUS_VLV
))
472 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
473 SPRITE0_FLIP_DONE_INT_EN_VLV
|
474 SPRITE1_FLIP_DONE_INT_EN_VLV
);
475 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
476 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
477 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
478 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
481 drm_WARN_ONCE(&dev_priv
->drm
,
482 enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
483 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
484 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
485 pipe_name(pipe
), enable_mask
, status_mask
);
490 void i915_enable_pipestat(struct drm_i915_private
*dev_priv
,
491 enum pipe pipe
, u32 status_mask
)
493 i915_reg_t reg
= PIPESTAT(pipe
);
496 drm_WARN_ONCE(&dev_priv
->drm
, status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
497 "pipe %c: status_mask=0x%x\n",
498 pipe_name(pipe
), status_mask
);
500 lockdep_assert_held(&dev_priv
->irq_lock
);
501 drm_WARN_ON(&dev_priv
->drm
, !intel_irqs_enabled(dev_priv
));
503 if ((dev_priv
->pipestat_irq_mask
[pipe
] & status_mask
) == status_mask
)
506 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
507 enable_mask
= i915_pipestat_enable_mask(dev_priv
, pipe
);
509 I915_WRITE(reg
, enable_mask
| status_mask
);
513 void i915_disable_pipestat(struct drm_i915_private
*dev_priv
,
514 enum pipe pipe
, u32 status_mask
)
516 i915_reg_t reg
= PIPESTAT(pipe
);
519 drm_WARN_ONCE(&dev_priv
->drm
, status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
520 "pipe %c: status_mask=0x%x\n",
521 pipe_name(pipe
), status_mask
);
523 lockdep_assert_held(&dev_priv
->irq_lock
);
524 drm_WARN_ON(&dev_priv
->drm
, !intel_irqs_enabled(dev_priv
));
526 if ((dev_priv
->pipestat_irq_mask
[pipe
] & status_mask
) == 0)
529 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
530 enable_mask
= i915_pipestat_enable_mask(dev_priv
, pipe
);
532 I915_WRITE(reg
, enable_mask
| status_mask
);
536 static bool i915_has_asle(struct drm_i915_private
*dev_priv
)
538 if (!dev_priv
->opregion
.asle
)
541 return IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
545 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
546 * @dev_priv: i915 device private
548 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
550 if (!i915_has_asle(dev_priv
))
553 spin_lock_irq(&dev_priv
->irq_lock
);
555 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
556 if (INTEL_GEN(dev_priv
) >= 4)
557 i915_enable_pipestat(dev_priv
, PIPE_A
,
558 PIPE_LEGACY_BLC_EVENT_STATUS
);
560 spin_unlock_irq(&dev_priv
->irq_lock
);
564 * This timing diagram depicts the video signal in and
565 * around the vertical blanking period.
567 * Assumptions about the fictitious mode used in this example:
569 * vsync_start = vblank_start + 1
570 * vsync_end = vblank_start + 2
571 * vtotal = vblank_start + 3
574 * latch double buffered registers
575 * increment frame counter (ctg+)
576 * generate start of vblank interrupt (gen4+)
579 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
580 * | may be shifted forward 1-3 extra lines via PIPECONF
582 * | | start of vsync:
583 * | | generate vsync interrupt
585 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
586 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
587 * ----va---> <-----------------vb--------------------> <--------va-------------
588 * | | <----vs-----> |
589 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
590 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
591 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
593 * last visible pixel first visible pixel
594 * | increment frame counter (gen3/4)
595 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
597 * x = horizontal active
598 * _ = horizontal blanking
599 * hs = horizontal sync
600 * va = vertical active
601 * vb = vertical blanking
603 * vbs = vblank_start (number)
606 * - most events happen at the start of horizontal sync
607 * - frame start happens at the start of horizontal blank, 1-4 lines
608 * (depending on PIPECONF settings) after the start of vblank
609 * - gen3/4 pixel and frame counter are synchronized with the start
610 * of horizontal active on the first line of vertical active
613 /* Called from drm generic code, passed a 'crtc', which
614 * we use as a pipe index
616 u32
i915_get_vblank_counter(struct drm_crtc
*crtc
)
618 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
619 struct drm_vblank_crtc
*vblank
= &dev_priv
->drm
.vblank
[drm_crtc_index(crtc
)];
620 const struct drm_display_mode
*mode
= &vblank
->hwmode
;
621 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
622 i915_reg_t high_frame
, low_frame
;
623 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
624 unsigned long irqflags
;
627 * On i965gm TV output the frame counter only works up to
628 * the point when we enable the TV encoder. After that the
629 * frame counter ceases to work and reads zero. We need a
630 * vblank wait before enabling the TV encoder and so we
631 * have to enable vblank interrupts while the frame counter
632 * is still in a working state. However the core vblank code
633 * does not like us returning non-zero frame counter values
634 * when we've told it that we don't have a working frame
635 * counter. Thus we must stop non-zero values leaking out.
637 if (!vblank
->max_vblank_count
)
640 htotal
= mode
->crtc_htotal
;
641 hsync_start
= mode
->crtc_hsync_start
;
642 vbl_start
= mode
->crtc_vblank_start
;
643 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
644 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
646 /* Convert to pixel count */
649 /* Start of vblank event occurs at start of hsync */
650 vbl_start
-= htotal
- hsync_start
;
652 high_frame
= PIPEFRAME(pipe
);
653 low_frame
= PIPEFRAMEPIXEL(pipe
);
655 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
658 * High & low register fields aren't synchronized, so make sure
659 * we get a low value that's stable across two reads of the high
663 high1
= intel_de_read_fw(dev_priv
, high_frame
) & PIPE_FRAME_HIGH_MASK
;
664 low
= intel_de_read_fw(dev_priv
, low_frame
);
665 high2
= intel_de_read_fw(dev_priv
, high_frame
) & PIPE_FRAME_HIGH_MASK
;
666 } while (high1
!= high2
);
668 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
670 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
671 pixel
= low
& PIPE_PIXEL_MASK
;
672 low
>>= PIPE_FRAME_LOW_SHIFT
;
675 * The frame counter increments at beginning of active.
676 * Cook up a vblank counter by also checking the pixel
677 * counter against vblank start.
679 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
682 u32
g4x_get_vblank_counter(struct drm_crtc
*crtc
)
684 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
685 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
687 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
691 * On certain encoders on certain platforms, pipe
692 * scanline register will not work to get the scanline,
693 * since the timings are driven from the PORT or issues
694 * with scanline register updates.
695 * This function will use Framestamp and current
696 * timestamp registers to calculate the scanline.
698 static u32
__intel_get_crtc_scanline_from_timestamp(struct intel_crtc
*crtc
)
700 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
701 struct drm_vblank_crtc
*vblank
=
702 &crtc
->base
.dev
->vblank
[drm_crtc_index(&crtc
->base
)];
703 const struct drm_display_mode
*mode
= &vblank
->hwmode
;
704 u32 vblank_start
= mode
->crtc_vblank_start
;
705 u32 vtotal
= mode
->crtc_vtotal
;
706 u32 htotal
= mode
->crtc_htotal
;
707 u32 clock
= mode
->crtc_clock
;
708 u32 scanline
, scan_prev_time
, scan_curr_time
, scan_post_time
;
711 * To avoid the race condition where we might cross into the
712 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
713 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
714 * during the same frame.
718 * This field provides read back of the display
719 * pipe frame time stamp. The time stamp value
720 * is sampled at every start of vertical blank.
722 scan_prev_time
= intel_de_read_fw(dev_priv
,
723 PIPE_FRMTMSTMP(crtc
->pipe
));
726 * The TIMESTAMP_CTR register has the current
729 scan_curr_time
= intel_de_read_fw(dev_priv
, IVB_TIMESTAMP_CTR
);
731 scan_post_time
= intel_de_read_fw(dev_priv
,
732 PIPE_FRMTMSTMP(crtc
->pipe
));
733 } while (scan_post_time
!= scan_prev_time
);
735 scanline
= div_u64(mul_u32_u32(scan_curr_time
- scan_prev_time
,
736 clock
), 1000 * htotal
);
737 scanline
= min(scanline
, vtotal
- 1);
738 scanline
= (scanline
+ vblank_start
) % vtotal
;
744 * intel_de_read_fw(), only for fast reads of display block, no need for
747 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
749 struct drm_device
*dev
= crtc
->base
.dev
;
750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
751 const struct drm_display_mode
*mode
;
752 struct drm_vblank_crtc
*vblank
;
753 enum pipe pipe
= crtc
->pipe
;
754 int position
, vtotal
;
759 vblank
= &crtc
->base
.dev
->vblank
[drm_crtc_index(&crtc
->base
)];
760 mode
= &vblank
->hwmode
;
762 if (crtc
->mode_flags
& I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP
)
763 return __intel_get_crtc_scanline_from_timestamp(crtc
);
765 vtotal
= mode
->crtc_vtotal
;
766 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
769 if (IS_GEN(dev_priv
, 2))
770 position
= intel_de_read_fw(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
772 position
= intel_de_read_fw(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
775 * On HSW, the DSL reg (0x70000) appears to return 0 if we
776 * read it just before the start of vblank. So try it again
777 * so we don't accidentally end up spanning a vblank frame
778 * increment, causing the pipe_update_end() code to squak at us.
780 * The nature of this problem means we can't simply check the ISR
781 * bit and return the vblank start value; nor can we use the scanline
782 * debug register in the transcoder as it appears to have the same
783 * problem. We may need to extend this to include other platforms,
784 * but so far testing only shows the problem on HSW.
786 if (HAS_DDI(dev_priv
) && !position
) {
789 for (i
= 0; i
< 100; i
++) {
791 temp
= intel_de_read_fw(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
792 if (temp
!= position
) {
800 * See update_scanline_offset() for the details on the
801 * scanline_offset adjustment.
803 return (position
+ crtc
->scanline_offset
) % vtotal
;
806 static bool i915_get_crtc_scanoutpos(struct drm_crtc
*_crtc
,
808 int *vpos
, int *hpos
,
809 ktime_t
*stime
, ktime_t
*etime
,
810 const struct drm_display_mode
*mode
)
812 struct drm_device
*dev
= _crtc
->dev
;
813 struct drm_i915_private
*dev_priv
= to_i915(dev
);
814 struct intel_crtc
*crtc
= to_intel_crtc(_crtc
);
815 enum pipe pipe
= crtc
->pipe
;
817 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
818 unsigned long irqflags
;
819 bool use_scanline_counter
= INTEL_GEN(dev_priv
) >= 5 ||
820 IS_G4X(dev_priv
) || IS_GEN(dev_priv
, 2) ||
821 crtc
->mode_flags
& I915_MODE_FLAG_USE_SCANLINE_COUNTER
;
823 if (drm_WARN_ON(&dev_priv
->drm
, !mode
->crtc_clock
)) {
824 drm_dbg(&dev_priv
->drm
,
825 "trying to get scanoutpos for disabled "
826 "pipe %c\n", pipe_name(pipe
));
830 htotal
= mode
->crtc_htotal
;
831 hsync_start
= mode
->crtc_hsync_start
;
832 vtotal
= mode
->crtc_vtotal
;
833 vbl_start
= mode
->crtc_vblank_start
;
834 vbl_end
= mode
->crtc_vblank_end
;
836 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
837 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
843 * Lock uncore.lock, as we will do multiple timing critical raw
844 * register reads, potentially with preemption disabled, so the
845 * following code must not block on uncore.lock.
847 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
849 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
851 /* Get optional system timestamp before query. */
853 *stime
= ktime_get();
855 if (use_scanline_counter
) {
856 /* No obvious pixelcount register. Only query vertical
857 * scanout position from Display scan line register.
859 position
= __intel_get_crtc_scanline(crtc
);
861 /* Have access to pixelcount since start of frame.
862 * We can split this into vertical and horizontal
865 position
= (intel_de_read_fw(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
867 /* convert to pixel counts */
873 * In interlaced modes, the pixel counter counts all pixels,
874 * so one field will have htotal more pixels. In order to avoid
875 * the reported position from jumping backwards when the pixel
876 * counter is beyond the length of the shorter field, just
877 * clamp the position the length of the shorter field. This
878 * matches how the scanline counter based position works since
879 * the scanline counter doesn't count the two half lines.
881 if (position
>= vtotal
)
882 position
= vtotal
- 1;
885 * Start of vblank interrupt is triggered at start of hsync,
886 * just prior to the first active line of vblank. However we
887 * consider lines to start at the leading edge of horizontal
888 * active. So, should we get here before we've crossed into
889 * the horizontal active of the first line in vblank, we would
890 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
891 * always add htotal-hsync_start to the current pixel position.
893 position
= (position
+ htotal
- hsync_start
) % vtotal
;
896 /* Get optional system timestamp after query. */
898 *etime
= ktime_get();
900 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
902 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
905 * While in vblank, position will be negative
906 * counting up towards 0 at vbl_end. And outside
907 * vblank, position will be positive counting
910 if (position
>= vbl_start
)
913 position
+= vtotal
- vbl_end
;
915 if (use_scanline_counter
) {
919 *vpos
= position
/ htotal
;
920 *hpos
= position
- (*vpos
* htotal
);
926 bool intel_crtc_get_vblank_timestamp(struct drm_crtc
*crtc
, int *max_error
,
927 ktime_t
*vblank_time
, bool in_vblank_irq
)
929 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
930 crtc
, max_error
, vblank_time
, in_vblank_irq
,
931 i915_get_crtc_scanoutpos
);
934 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
936 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
937 unsigned long irqflags
;
940 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
941 position
= __intel_get_crtc_scanline(crtc
);
942 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
948 * ivb_parity_work - Workqueue called when a parity error interrupt
950 * @work: workqueue struct
952 * Doesn't actually do anything except notify userspace. As a consequence of
953 * this event, userspace should try to remap the bad rows since statistically
954 * it is likely the same row is more likely to go bad again.
956 static void ivb_parity_work(struct work_struct
*work
)
958 struct drm_i915_private
*dev_priv
=
959 container_of(work
, typeof(*dev_priv
), l3_parity
.error_work
);
960 struct intel_gt
*gt
= &dev_priv
->gt
;
961 u32 error_status
, row
, bank
, subbank
;
962 char *parity_event
[6];
966 /* We must turn off DOP level clock gating to access the L3 registers.
967 * In order to prevent a get/put style interface, acquire struct mutex
968 * any time we access those registers.
970 mutex_lock(&dev_priv
->drm
.struct_mutex
);
972 /* If we've screwed up tracking, just let the interrupt fire again */
973 if (drm_WARN_ON(&dev_priv
->drm
, !dev_priv
->l3_parity
.which_slice
))
976 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
977 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
978 POSTING_READ(GEN7_MISCCPCTL
);
980 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
984 if (drm_WARN_ON_ONCE(&dev_priv
->drm
,
985 slice
>= NUM_L3_SLICES(dev_priv
)))
988 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
990 reg
= GEN7_L3CDERRST1(slice
);
992 error_status
= I915_READ(reg
);
993 row
= GEN7_PARITY_ERROR_ROW(error_status
);
994 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
995 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
997 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1000 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1001 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1002 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1003 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1004 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1005 parity_event
[5] = NULL
;
1007 kobject_uevent_env(&dev_priv
->drm
.primary
->kdev
->kobj
,
1008 KOBJ_CHANGE
, parity_event
);
1010 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1011 slice
, row
, bank
, subbank
);
1013 kfree(parity_event
[4]);
1014 kfree(parity_event
[3]);
1015 kfree(parity_event
[2]);
1016 kfree(parity_event
[1]);
1019 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1022 drm_WARN_ON(&dev_priv
->drm
, dev_priv
->l3_parity
.which_slice
);
1023 spin_lock_irq(>
->irq_lock
);
1024 gen5_gt_enable_irq(gt
, GT_PARITY_ERROR(dev_priv
));
1025 spin_unlock_irq(>
->irq_lock
);
1027 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1030 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1034 return val
& GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1
);
1036 return val
& GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2
);
1038 return val
& GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3
);
1040 return val
& GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4
);
1042 return val
& GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5
);
1044 return val
& GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6
);
1050 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1054 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1056 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1058 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1064 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1068 return val
& SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A
);
1070 return val
& SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B
);
1072 return val
& SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C
);
1078 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1082 return val
& ICP_TC_HPD_LONG_DETECT(PORT_TC1
);
1084 return val
& ICP_TC_HPD_LONG_DETECT(PORT_TC2
);
1086 return val
& ICP_TC_HPD_LONG_DETECT(PORT_TC3
);
1088 return val
& ICP_TC_HPD_LONG_DETECT(PORT_TC4
);
1090 return val
& ICP_TC_HPD_LONG_DETECT(PORT_TC5
);
1092 return val
& ICP_TC_HPD_LONG_DETECT(PORT_TC6
);
1098 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin
, u32 val
)
1102 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1108 static bool spt_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1112 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1114 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1116 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1118 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1124 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1128 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1134 static bool pch_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1138 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1140 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1142 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1148 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin
, u32 val
)
1152 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1154 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1156 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1163 * Get a bit mask of pins that have triggered, and which ones may be long.
1164 * This can be called multiple times with the same masks to accumulate
1165 * hotplug detection results from several registers.
1167 * Note that the caller is expected to zero out the masks initially.
1169 static void intel_get_hpd_pins(struct drm_i915_private
*dev_priv
,
1170 u32
*pin_mask
, u32
*long_mask
,
1171 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1172 const u32 hpd
[HPD_NUM_PINS
],
1173 bool long_pulse_detect(enum hpd_pin pin
, u32 val
))
1177 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask
) < HPD_NUM_PINS
);
1179 for_each_hpd_pin(pin
) {
1180 if ((hpd
[pin
] & hotplug_trigger
) == 0)
1183 *pin_mask
|= BIT(pin
);
1185 if (long_pulse_detect(pin
, dig_hotplug_reg
))
1186 *long_mask
|= BIT(pin
);
1189 drm_dbg(&dev_priv
->drm
,
1190 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1191 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
, *long_mask
);
1195 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1197 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1200 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1202 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1205 #if defined(CONFIG_DEBUG_FS)
1206 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1212 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1213 struct intel_pipe_crc
*pipe_crc
= &crtc
->pipe_crc
;
1214 u32 crcs
[5] = { crc0
, crc1
, crc2
, crc3
, crc4
};
1216 trace_intel_pipe_crc(crtc
, crcs
);
1218 spin_lock(&pipe_crc
->lock
);
1220 * For some not yet identified reason, the first CRC is
1221 * bonkers. So let's just wait for the next vblank and read
1222 * out the buggy result.
1224 * On GEN8+ sometimes the second CRC is bonkers as well, so
1225 * don't trust that one either.
1227 if (pipe_crc
->skipped
<= 0 ||
1228 (INTEL_GEN(dev_priv
) >= 8 && pipe_crc
->skipped
== 1)) {
1229 pipe_crc
->skipped
++;
1230 spin_unlock(&pipe_crc
->lock
);
1233 spin_unlock(&pipe_crc
->lock
);
1235 drm_crtc_add_crc_entry(&crtc
->base
, true,
1236 drm_crtc_accurate_vblank_count(&crtc
->base
),
1241 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1249 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1252 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1253 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1257 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1260 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1261 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1262 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1263 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1264 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1265 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1268 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1273 if (INTEL_GEN(dev_priv
) >= 3)
1274 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1278 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1279 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1283 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1284 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1285 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1286 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1290 static void i9xx_pipestat_irq_reset(struct drm_i915_private
*dev_priv
)
1294 for_each_pipe(dev_priv
, pipe
) {
1295 I915_WRITE(PIPESTAT(pipe
),
1296 PIPESTAT_INT_STATUS_MASK
|
1297 PIPE_FIFO_UNDERRUN_STATUS
);
1299 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
1303 static void i9xx_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1304 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1308 spin_lock(&dev_priv
->irq_lock
);
1310 if (!dev_priv
->display_irqs_enabled
) {
1311 spin_unlock(&dev_priv
->irq_lock
);
1315 for_each_pipe(dev_priv
, pipe
) {
1317 u32 status_mask
, enable_mask
, iir_bit
= 0;
1320 * PIPESTAT bits get signalled even when the interrupt is
1321 * disabled with the mask bits, and some of the status bits do
1322 * not generate interrupts at all (like the underrun bit). Hence
1323 * we need to be careful that we only handle what we want to
1327 /* fifo underruns are filterered in the underrun handler. */
1328 status_mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1333 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1336 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1339 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1343 status_mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1348 reg
= PIPESTAT(pipe
);
1349 pipe_stats
[pipe
] = I915_READ(reg
) & status_mask
;
1350 enable_mask
= i915_pipestat_enable_mask(dev_priv
, pipe
);
1353 * Clear the PIPE*STAT regs before the IIR
1355 * Toggle the enable bits to make sure we get an
1356 * edge in the ISR pipe event bit if we don't clear
1357 * all the enabled status bits. Otherwise the edge
1358 * triggered IIR on i965/g4x wouldn't notice that
1359 * an interrupt is still pending.
1361 if (pipe_stats
[pipe
]) {
1362 I915_WRITE(reg
, pipe_stats
[pipe
]);
1363 I915_WRITE(reg
, enable_mask
);
1366 spin_unlock(&dev_priv
->irq_lock
);
1369 static void i8xx_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1370 u16 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1374 for_each_pipe(dev_priv
, pipe
) {
1375 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1376 intel_handle_vblank(dev_priv
, pipe
);
1378 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1379 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1381 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1382 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1386 static void i915_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1387 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1389 bool blc_event
= false;
1392 for_each_pipe(dev_priv
, pipe
) {
1393 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1394 intel_handle_vblank(dev_priv
, pipe
);
1396 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
1399 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1400 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1402 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1403 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1406 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
1407 intel_opregion_asle_intr(dev_priv
);
1410 static void i965_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1411 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1413 bool blc_event
= false;
1416 for_each_pipe(dev_priv
, pipe
) {
1417 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
)
1418 intel_handle_vblank(dev_priv
, pipe
);
1420 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
1423 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1424 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1426 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1427 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1430 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
1431 intel_opregion_asle_intr(dev_priv
);
1433 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1434 gmbus_irq_handler(dev_priv
);
1437 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1438 u32 pipe_stats
[I915_MAX_PIPES
])
1442 for_each_pipe(dev_priv
, pipe
) {
1443 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
)
1444 intel_handle_vblank(dev_priv
, pipe
);
1446 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1447 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1449 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1450 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1453 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1454 gmbus_irq_handler(dev_priv
);
1457 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1459 u32 hotplug_status
= 0, hotplug_status_mask
;
1462 if (IS_G4X(dev_priv
) ||
1463 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1464 hotplug_status_mask
= HOTPLUG_INT_STATUS_G4X
|
1465 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
;
1467 hotplug_status_mask
= HOTPLUG_INT_STATUS_I915
;
1470 * We absolutely have to clear all the pending interrupt
1471 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1472 * interrupt bit won't have an edge, and the i965/g4x
1473 * edge triggered IIR will not notice that an interrupt
1474 * is still pending. We can't use PORT_HOTPLUG_EN to
1475 * guarantee the edge as the act of toggling the enable
1476 * bits can itself generate a new hotplug interrupt :(
1478 for (i
= 0; i
< 10; i
++) {
1479 u32 tmp
= I915_READ(PORT_HOTPLUG_STAT
) & hotplug_status_mask
;
1482 return hotplug_status
;
1484 hotplug_status
|= tmp
;
1485 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1488 drm_WARN_ONCE(&dev_priv
->drm
, 1,
1489 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1490 I915_READ(PORT_HOTPLUG_STAT
));
1492 return hotplug_status
;
1495 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1498 u32 pin_mask
= 0, long_mask
= 0;
1499 u32 hotplug_trigger
;
1501 if (IS_G4X(dev_priv
) ||
1502 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1503 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1505 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1507 if (hotplug_trigger
) {
1508 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1509 hotplug_trigger
, hotplug_trigger
,
1510 dev_priv
->hotplug
.hpd
,
1511 i9xx_port_hotplug_long_detect
);
1513 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1516 if ((IS_G4X(dev_priv
) ||
1517 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1518 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1519 dp_aux_irq_handler(dev_priv
);
1522 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1524 struct drm_i915_private
*dev_priv
= arg
;
1525 irqreturn_t ret
= IRQ_NONE
;
1527 if (!intel_irqs_enabled(dev_priv
))
1530 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1531 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1534 u32 iir
, gt_iir
, pm_iir
;
1535 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1536 u32 hotplug_status
= 0;
1539 gt_iir
= I915_READ(GTIIR
);
1540 pm_iir
= I915_READ(GEN6_PMIIR
);
1541 iir
= I915_READ(VLV_IIR
);
1543 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1549 * Theory on interrupt generation, based on empirical evidence:
1551 * x = ((VLV_IIR & VLV_IER) ||
1552 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1553 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1555 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1556 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1557 * guarantee the CPU interrupt will be raised again even if we
1558 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1559 * bits this time around.
1561 I915_WRITE(VLV_MASTER_IER
, 0);
1562 ier
= I915_READ(VLV_IER
);
1563 I915_WRITE(VLV_IER
, 0);
1566 I915_WRITE(GTIIR
, gt_iir
);
1568 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1570 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1571 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1573 /* Call regardless, as some status bits might not be
1574 * signalled in iir */
1575 i9xx_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1577 if (iir
& (I915_LPE_PIPE_A_INTERRUPT
|
1578 I915_LPE_PIPE_B_INTERRUPT
))
1579 intel_lpe_audio_irq_handler(dev_priv
);
1582 * VLV_IIR is single buffered, and reflects the level
1583 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1586 I915_WRITE(VLV_IIR
, iir
);
1588 I915_WRITE(VLV_IER
, ier
);
1589 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1592 gen6_gt_irq_handler(&dev_priv
->gt
, gt_iir
);
1594 gen6_rps_irq_handler(&dev_priv
->gt
.rps
, pm_iir
);
1597 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1599 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1602 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1607 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1609 struct drm_i915_private
*dev_priv
= arg
;
1610 irqreturn_t ret
= IRQ_NONE
;
1612 if (!intel_irqs_enabled(dev_priv
))
1615 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1616 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1619 u32 master_ctl
, iir
;
1620 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1621 u32 hotplug_status
= 0;
1624 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1625 iir
= I915_READ(VLV_IIR
);
1627 if (master_ctl
== 0 && iir
== 0)
1633 * Theory on interrupt generation, based on empirical evidence:
1635 * x = ((VLV_IIR & VLV_IER) ||
1636 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1637 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1639 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1640 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1641 * guarantee the CPU interrupt will be raised again even if we
1642 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1643 * bits this time around.
1645 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1646 ier
= I915_READ(VLV_IER
);
1647 I915_WRITE(VLV_IER
, 0);
1649 gen8_gt_irq_handler(&dev_priv
->gt
, master_ctl
);
1651 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1652 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1654 /* Call regardless, as some status bits might not be
1655 * signalled in iir */
1656 i9xx_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1658 if (iir
& (I915_LPE_PIPE_A_INTERRUPT
|
1659 I915_LPE_PIPE_B_INTERRUPT
|
1660 I915_LPE_PIPE_C_INTERRUPT
))
1661 intel_lpe_audio_irq_handler(dev_priv
);
1664 * VLV_IIR is single buffered, and reflects the level
1665 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1668 I915_WRITE(VLV_IIR
, iir
);
1670 I915_WRITE(VLV_IER
, ier
);
1671 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1674 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1676 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1679 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1684 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1685 u32 hotplug_trigger
)
1687 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1690 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1691 * unless we touch the hotplug register, even if hotplug_trigger is
1692 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1695 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1696 if (!hotplug_trigger
) {
1697 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1698 PORTD_HOTPLUG_STATUS_MASK
|
1699 PORTC_HOTPLUG_STATUS_MASK
|
1700 PORTB_HOTPLUG_STATUS_MASK
;
1701 dig_hotplug_reg
&= ~mask
;
1704 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1705 if (!hotplug_trigger
)
1708 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1709 hotplug_trigger
, dig_hotplug_reg
,
1710 dev_priv
->hotplug
.pch_hpd
,
1711 pch_port_hotplug_long_detect
);
1713 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1716 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1719 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1721 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
);
1723 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1724 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1725 SDE_AUDIO_POWER_SHIFT
);
1726 drm_dbg(&dev_priv
->drm
, "PCH audio power change on port %d\n",
1730 if (pch_iir
& SDE_AUX_MASK
)
1731 dp_aux_irq_handler(dev_priv
);
1733 if (pch_iir
& SDE_GMBUS
)
1734 gmbus_irq_handler(dev_priv
);
1736 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1737 drm_dbg(&dev_priv
->drm
, "PCH HDCP audio interrupt\n");
1739 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1740 drm_dbg(&dev_priv
->drm
, "PCH transcoder audio interrupt\n");
1742 if (pch_iir
& SDE_POISON
)
1743 drm_err(&dev_priv
->drm
, "PCH poison interrupt\n");
1745 if (pch_iir
& SDE_FDI_MASK
) {
1746 for_each_pipe(dev_priv
, pipe
)
1747 drm_dbg(&dev_priv
->drm
, " pipe %c FDI IIR: 0x%08x\n",
1749 I915_READ(FDI_RX_IIR(pipe
)));
1752 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1753 drm_dbg(&dev_priv
->drm
, "PCH transcoder CRC done interrupt\n");
1755 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1756 drm_dbg(&dev_priv
->drm
,
1757 "PCH transcoder CRC error interrupt\n");
1759 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1760 intel_pch_fifo_underrun_irq_handler(dev_priv
, PIPE_A
);
1762 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1763 intel_pch_fifo_underrun_irq_handler(dev_priv
, PIPE_B
);
1766 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
1768 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1771 if (err_int
& ERR_INT_POISON
)
1772 drm_err(&dev_priv
->drm
, "Poison interrupt\n");
1774 for_each_pipe(dev_priv
, pipe
) {
1775 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1776 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1778 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1779 if (IS_IVYBRIDGE(dev_priv
))
1780 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
1782 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
1786 I915_WRITE(GEN7_ERR_INT
, err_int
);
1789 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
1791 u32 serr_int
= I915_READ(SERR_INT
);
1794 if (serr_int
& SERR_INT_POISON
)
1795 drm_err(&dev_priv
->drm
, "PCH poison interrupt\n");
1797 for_each_pipe(dev_priv
, pipe
)
1798 if (serr_int
& SERR_INT_TRANS_FIFO_UNDERRUN(pipe
))
1799 intel_pch_fifo_underrun_irq_handler(dev_priv
, pipe
);
1801 I915_WRITE(SERR_INT
, serr_int
);
1804 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1807 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1809 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
);
1811 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1812 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1813 SDE_AUDIO_POWER_SHIFT_CPT
);
1814 drm_dbg(&dev_priv
->drm
, "PCH audio power change on port %c\n",
1818 if (pch_iir
& SDE_AUX_MASK_CPT
)
1819 dp_aux_irq_handler(dev_priv
);
1821 if (pch_iir
& SDE_GMBUS_CPT
)
1822 gmbus_irq_handler(dev_priv
);
1824 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1825 drm_dbg(&dev_priv
->drm
, "Audio CP request interrupt\n");
1827 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1828 drm_dbg(&dev_priv
->drm
, "Audio CP change interrupt\n");
1830 if (pch_iir
& SDE_FDI_MASK_CPT
) {
1831 for_each_pipe(dev_priv
, pipe
)
1832 drm_dbg(&dev_priv
->drm
, " pipe %c FDI IIR: 0x%08x\n",
1834 I915_READ(FDI_RX_IIR(pipe
)));
1837 if (pch_iir
& SDE_ERROR_CPT
)
1838 cpt_serr_int_handler(dev_priv
);
1841 static void icp_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1843 u32 ddi_hotplug_trigger
, tc_hotplug_trigger
;
1844 u32 pin_mask
= 0, long_mask
= 0;
1846 if (HAS_PCH_TGP(dev_priv
)) {
1847 ddi_hotplug_trigger
= pch_iir
& SDE_DDI_MASK_TGP
;
1848 tc_hotplug_trigger
= pch_iir
& SDE_TC_MASK_TGP
;
1849 } else if (HAS_PCH_JSP(dev_priv
)) {
1850 ddi_hotplug_trigger
= pch_iir
& SDE_DDI_MASK_TGP
;
1851 tc_hotplug_trigger
= 0;
1852 } else if (HAS_PCH_MCC(dev_priv
)) {
1853 ddi_hotplug_trigger
= pch_iir
& SDE_DDI_MASK_ICP
;
1854 tc_hotplug_trigger
= pch_iir
& SDE_TC_HOTPLUG_ICP(PORT_TC1
);
1856 drm_WARN(&dev_priv
->drm
, !HAS_PCH_ICP(dev_priv
),
1857 "Unrecognized PCH type 0x%x\n",
1858 INTEL_PCH_TYPE(dev_priv
));
1860 ddi_hotplug_trigger
= pch_iir
& SDE_DDI_MASK_ICP
;
1861 tc_hotplug_trigger
= pch_iir
& SDE_TC_MASK_ICP
;
1864 if (ddi_hotplug_trigger
) {
1865 u32 dig_hotplug_reg
;
1867 dig_hotplug_reg
= I915_READ(SHOTPLUG_CTL_DDI
);
1868 I915_WRITE(SHOTPLUG_CTL_DDI
, dig_hotplug_reg
);
1870 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1871 ddi_hotplug_trigger
, dig_hotplug_reg
,
1872 dev_priv
->hotplug
.pch_hpd
,
1873 icp_ddi_port_hotplug_long_detect
);
1876 if (tc_hotplug_trigger
) {
1877 u32 dig_hotplug_reg
;
1879 dig_hotplug_reg
= I915_READ(SHOTPLUG_CTL_TC
);
1880 I915_WRITE(SHOTPLUG_CTL_TC
, dig_hotplug_reg
);
1882 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1883 tc_hotplug_trigger
, dig_hotplug_reg
,
1884 dev_priv
->hotplug
.pch_hpd
,
1885 icp_tc_port_hotplug_long_detect
);
1889 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1891 if (pch_iir
& SDE_GMBUS_ICP
)
1892 gmbus_irq_handler(dev_priv
);
1895 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1897 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
1898 ~SDE_PORTE_HOTPLUG_SPT
;
1899 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
1900 u32 pin_mask
= 0, long_mask
= 0;
1902 if (hotplug_trigger
) {
1903 u32 dig_hotplug_reg
;
1905 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1906 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1908 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1909 hotplug_trigger
, dig_hotplug_reg
,
1910 dev_priv
->hotplug
.pch_hpd
,
1911 spt_port_hotplug_long_detect
);
1914 if (hotplug2_trigger
) {
1915 u32 dig_hotplug_reg
;
1917 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
1918 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
1920 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1921 hotplug2_trigger
, dig_hotplug_reg
,
1922 dev_priv
->hotplug
.pch_hpd
,
1923 spt_port_hotplug2_long_detect
);
1927 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1929 if (pch_iir
& SDE_GMBUS_CPT
)
1930 gmbus_irq_handler(dev_priv
);
1933 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1934 u32 hotplug_trigger
)
1936 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1938 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
1939 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
1941 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
1942 hotplug_trigger
, dig_hotplug_reg
,
1943 dev_priv
->hotplug
.hpd
,
1944 ilk_port_hotplug_long_detect
);
1946 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1949 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
1953 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
1955 if (hotplug_trigger
)
1956 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
);
1958 if (de_iir
& DE_AUX_CHANNEL_A
)
1959 dp_aux_irq_handler(dev_priv
);
1961 if (de_iir
& DE_GSE
)
1962 intel_opregion_asle_intr(dev_priv
);
1964 if (de_iir
& DE_POISON
)
1965 drm_err(&dev_priv
->drm
, "Poison interrupt\n");
1967 for_each_pipe(dev_priv
, pipe
) {
1968 if (de_iir
& DE_PIPE_VBLANK(pipe
))
1969 intel_handle_vblank(dev_priv
, pipe
);
1971 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
1972 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1974 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
1975 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1978 /* check event from PCH */
1979 if (de_iir
& DE_PCH_EVENT
) {
1980 u32 pch_iir
= I915_READ(SDEIIR
);
1982 if (HAS_PCH_CPT(dev_priv
))
1983 cpt_irq_handler(dev_priv
, pch_iir
);
1985 ibx_irq_handler(dev_priv
, pch_iir
);
1987 /* should clear PCH hotplug event before clear CPU irq */
1988 I915_WRITE(SDEIIR
, pch_iir
);
1991 if (IS_GEN(dev_priv
, 5) && de_iir
& DE_PCU_EVENT
)
1992 gen5_rps_irq_handler(&dev_priv
->gt
.rps
);
1995 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
1999 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2001 if (hotplug_trigger
)
2002 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
);
2004 if (de_iir
& DE_ERR_INT_IVB
)
2005 ivb_err_int_handler(dev_priv
);
2007 if (de_iir
& DE_EDP_PSR_INT_HSW
) {
2008 u32 psr_iir
= I915_READ(EDP_PSR_IIR
);
2010 intel_psr_irq_handler(dev_priv
, psr_iir
);
2011 I915_WRITE(EDP_PSR_IIR
, psr_iir
);
2014 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2015 dp_aux_irq_handler(dev_priv
);
2017 if (de_iir
& DE_GSE_IVB
)
2018 intel_opregion_asle_intr(dev_priv
);
2020 for_each_pipe(dev_priv
, pipe
) {
2021 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)))
2022 intel_handle_vblank(dev_priv
, pipe
);
2025 /* check event from PCH */
2026 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2027 u32 pch_iir
= I915_READ(SDEIIR
);
2029 cpt_irq_handler(dev_priv
, pch_iir
);
2031 /* clear PCH hotplug event before clear CPU irq */
2032 I915_WRITE(SDEIIR
, pch_iir
);
2037 * To handle irqs with the minimum potential races with fresh interrupts, we:
2038 * 1 - Disable Master Interrupt Control.
2039 * 2 - Find the source(s) of the interrupt.
2040 * 3 - Clear the Interrupt Identity bits (IIR).
2041 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2042 * 5 - Re-enable Master Interrupt Control.
2044 static irqreturn_t
ilk_irq_handler(int irq
, void *arg
)
2046 struct drm_i915_private
*i915
= arg
;
2047 void __iomem
* const regs
= i915
->uncore
.regs
;
2048 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2049 irqreturn_t ret
= IRQ_NONE
;
2051 if (unlikely(!intel_irqs_enabled(i915
)))
2054 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2055 disable_rpm_wakeref_asserts(&i915
->runtime_pm
);
2057 /* disable master interrupt before clearing iir */
2058 de_ier
= raw_reg_read(regs
, DEIER
);
2059 raw_reg_write(regs
, DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2061 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2062 * interrupts will will be stored on its back queue, and then we'll be
2063 * able to process them after we restore SDEIER (as soon as we restore
2064 * it, we'll get an interrupt if SDEIIR still has something to process
2065 * due to its back queue). */
2066 if (!HAS_PCH_NOP(i915
)) {
2067 sde_ier
= raw_reg_read(regs
, SDEIER
);
2068 raw_reg_write(regs
, SDEIER
, 0);
2071 /* Find, clear, then process each source of interrupt */
2073 gt_iir
= raw_reg_read(regs
, GTIIR
);
2075 raw_reg_write(regs
, GTIIR
, gt_iir
);
2076 if (INTEL_GEN(i915
) >= 6)
2077 gen6_gt_irq_handler(&i915
->gt
, gt_iir
);
2079 gen5_gt_irq_handler(&i915
->gt
, gt_iir
);
2083 de_iir
= raw_reg_read(regs
, DEIIR
);
2085 raw_reg_write(regs
, DEIIR
, de_iir
);
2086 if (INTEL_GEN(i915
) >= 7)
2087 ivb_display_irq_handler(i915
, de_iir
);
2089 ilk_display_irq_handler(i915
, de_iir
);
2093 if (INTEL_GEN(i915
) >= 6) {
2094 u32 pm_iir
= raw_reg_read(regs
, GEN6_PMIIR
);
2096 raw_reg_write(regs
, GEN6_PMIIR
, pm_iir
);
2097 gen6_rps_irq_handler(&i915
->gt
.rps
, pm_iir
);
2102 raw_reg_write(regs
, DEIER
, de_ier
);
2104 raw_reg_write(regs
, SDEIER
, sde_ier
);
2106 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2107 enable_rpm_wakeref_asserts(&i915
->runtime_pm
);
2112 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2113 u32 hotplug_trigger
)
2115 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2117 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2118 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2120 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
2121 hotplug_trigger
, dig_hotplug_reg
,
2122 dev_priv
->hotplug
.hpd
,
2123 bxt_port_hotplug_long_detect
);
2125 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2128 static void gen11_hpd_irq_handler(struct drm_i915_private
*dev_priv
, u32 iir
)
2130 u32 pin_mask
= 0, long_mask
= 0;
2131 u32 trigger_tc
= iir
& GEN11_DE_TC_HOTPLUG_MASK
;
2132 u32 trigger_tbt
= iir
& GEN11_DE_TBT_HOTPLUG_MASK
;
2135 u32 dig_hotplug_reg
;
2137 dig_hotplug_reg
= I915_READ(GEN11_TC_HOTPLUG_CTL
);
2138 I915_WRITE(GEN11_TC_HOTPLUG_CTL
, dig_hotplug_reg
);
2140 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
2141 trigger_tc
, dig_hotplug_reg
,
2142 dev_priv
->hotplug
.hpd
,
2143 gen11_port_hotplug_long_detect
);
2147 u32 dig_hotplug_reg
;
2149 dig_hotplug_reg
= I915_READ(GEN11_TBT_HOTPLUG_CTL
);
2150 I915_WRITE(GEN11_TBT_HOTPLUG_CTL
, dig_hotplug_reg
);
2152 intel_get_hpd_pins(dev_priv
, &pin_mask
, &long_mask
,
2153 trigger_tbt
, dig_hotplug_reg
,
2154 dev_priv
->hotplug
.hpd
,
2155 gen11_port_hotplug_long_detect
);
2159 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2161 drm_err(&dev_priv
->drm
,
2162 "Unexpected DE HPD interrupt 0x%08x\n", iir
);
2165 static u32
gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv
)
2169 if (INTEL_GEN(dev_priv
) >= 12)
2170 return TGL_DE_PORT_AUX_DDIA
|
2171 TGL_DE_PORT_AUX_DDIB
|
2172 TGL_DE_PORT_AUX_DDIC
|
2173 TGL_DE_PORT_AUX_USBC1
|
2174 TGL_DE_PORT_AUX_USBC2
|
2175 TGL_DE_PORT_AUX_USBC3
|
2176 TGL_DE_PORT_AUX_USBC4
|
2177 TGL_DE_PORT_AUX_USBC5
|
2178 TGL_DE_PORT_AUX_USBC6
;
2181 mask
= GEN8_AUX_CHANNEL_A
;
2182 if (INTEL_GEN(dev_priv
) >= 9)
2183 mask
|= GEN9_AUX_CHANNEL_B
|
2184 GEN9_AUX_CHANNEL_C
|
2187 if (IS_CNL_WITH_PORT_F(dev_priv
) || IS_GEN(dev_priv
, 11))
2188 mask
|= CNL_AUX_CHANNEL_F
;
2190 if (IS_GEN(dev_priv
, 11))
2191 mask
|= ICL_AUX_CHANNEL_E
;
2196 static u32
gen8_de_pipe_fault_mask(struct drm_i915_private
*dev_priv
)
2198 if (IS_ROCKETLAKE(dev_priv
))
2199 return RKL_DE_PIPE_IRQ_FAULT_ERRORS
;
2200 else if (INTEL_GEN(dev_priv
) >= 11)
2201 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS
;
2202 else if (INTEL_GEN(dev_priv
) >= 9)
2203 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2205 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2209 gen8_de_misc_irq_handler(struct drm_i915_private
*dev_priv
, u32 iir
)
2213 if (iir
& GEN8_DE_MISC_GSE
) {
2214 intel_opregion_asle_intr(dev_priv
);
2218 if (iir
& GEN8_DE_EDP_PSR
) {
2222 if (INTEL_GEN(dev_priv
) >= 12)
2223 iir_reg
= TRANS_PSR_IIR(dev_priv
->psr
.transcoder
);
2225 iir_reg
= EDP_PSR_IIR
;
2227 psr_iir
= I915_READ(iir_reg
);
2228 I915_WRITE(iir_reg
, psr_iir
);
2233 intel_psr_irq_handler(dev_priv
, psr_iir
);
2237 drm_err(&dev_priv
->drm
, "Unexpected DE Misc interrupt\n");
2241 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2243 irqreturn_t ret
= IRQ_NONE
;
2247 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2248 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2250 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2252 gen8_de_misc_irq_handler(dev_priv
, iir
);
2254 drm_err(&dev_priv
->drm
,
2255 "The master control interrupt lied (DE MISC)!\n");
2259 if (INTEL_GEN(dev_priv
) >= 11 && (master_ctl
& GEN11_DE_HPD_IRQ
)) {
2260 iir
= I915_READ(GEN11_DE_HPD_IIR
);
2262 I915_WRITE(GEN11_DE_HPD_IIR
, iir
);
2264 gen11_hpd_irq_handler(dev_priv
, iir
);
2266 drm_err(&dev_priv
->drm
,
2267 "The master control interrupt lied, (DE HPD)!\n");
2271 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2272 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2277 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2280 if (iir
& gen8_de_port_aux_mask(dev_priv
)) {
2281 dp_aux_irq_handler(dev_priv
);
2285 if (IS_GEN9_LP(dev_priv
)) {
2286 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2288 bxt_hpd_irq_handler(dev_priv
, tmp_mask
);
2291 } else if (IS_BROADWELL(dev_priv
)) {
2292 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2294 ilk_hpd_irq_handler(dev_priv
, tmp_mask
);
2299 if (IS_GEN9_LP(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2300 gmbus_irq_handler(dev_priv
);
2305 drm_err(&dev_priv
->drm
,
2306 "Unexpected DE Port interrupt\n");
2309 drm_err(&dev_priv
->drm
,
2310 "The master control interrupt lied (DE PORT)!\n");
2313 for_each_pipe(dev_priv
, pipe
) {
2316 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2319 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2321 drm_err(&dev_priv
->drm
,
2322 "The master control interrupt lied (DE PIPE)!\n");
2327 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2329 if (iir
& GEN8_PIPE_VBLANK
)
2330 intel_handle_vblank(dev_priv
, pipe
);
2332 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2333 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2335 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2336 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2338 fault_errors
= iir
& gen8_de_pipe_fault_mask(dev_priv
);
2340 drm_err(&dev_priv
->drm
,
2341 "Fault errors on pipe %c: 0x%08x\n",
2346 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2347 master_ctl
& GEN8_DE_PCH_IRQ
) {
2349 * FIXME(BDW): Assume for now that the new interrupt handling
2350 * scheme also closed the SDE interrupt handling race we've seen
2351 * on older pch-split platforms. But this needs testing.
2353 iir
= I915_READ(SDEIIR
);
2355 I915_WRITE(SDEIIR
, iir
);
2358 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
)
2359 icp_irq_handler(dev_priv
, iir
);
2360 else if (INTEL_PCH_TYPE(dev_priv
) >= PCH_SPT
)
2361 spt_irq_handler(dev_priv
, iir
);
2363 cpt_irq_handler(dev_priv
, iir
);
2366 * Like on previous PCH there seems to be something
2367 * fishy going on with forwarding PCH interrupts.
2369 drm_dbg(&dev_priv
->drm
,
2370 "The master control interrupt lied (SDE)!\n");
2377 static inline u32
gen8_master_intr_disable(void __iomem
* const regs
)
2379 raw_reg_write(regs
, GEN8_MASTER_IRQ
, 0);
2382 * Now with master disabled, get a sample of level indications
2383 * for this interrupt. Indications will be cleared on related acks.
2384 * New indications can and will light up during processing,
2385 * and will generate new interrupt after enabling master.
2387 return raw_reg_read(regs
, GEN8_MASTER_IRQ
);
2390 static inline void gen8_master_intr_enable(void __iomem
* const regs
)
2392 raw_reg_write(regs
, GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2395 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2397 struct drm_i915_private
*dev_priv
= arg
;
2398 void __iomem
* const regs
= dev_priv
->uncore
.regs
;
2401 if (!intel_irqs_enabled(dev_priv
))
2404 master_ctl
= gen8_master_intr_disable(regs
);
2406 gen8_master_intr_enable(regs
);
2410 /* Find, queue (onto bottom-halves), then clear each source */
2411 gen8_gt_irq_handler(&dev_priv
->gt
, master_ctl
);
2413 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2414 if (master_ctl
& ~GEN8_GT_IRQS
) {
2415 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2416 gen8_de_irq_handler(dev_priv
, master_ctl
);
2417 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2420 gen8_master_intr_enable(regs
);
2426 gen11_gu_misc_irq_ack(struct intel_gt
*gt
, const u32 master_ctl
)
2428 void __iomem
* const regs
= gt
->uncore
->regs
;
2431 if (!(master_ctl
& GEN11_GU_MISC_IRQ
))
2434 iir
= raw_reg_read(regs
, GEN11_GU_MISC_IIR
);
2436 raw_reg_write(regs
, GEN11_GU_MISC_IIR
, iir
);
2442 gen11_gu_misc_irq_handler(struct intel_gt
*gt
, const u32 iir
)
2444 if (iir
& GEN11_GU_MISC_GSE
)
2445 intel_opregion_asle_intr(gt
->i915
);
2448 static inline u32
gen11_master_intr_disable(void __iomem
* const regs
)
2450 raw_reg_write(regs
, GEN11_GFX_MSTR_IRQ
, 0);
2453 * Now with master disabled, get a sample of level indications
2454 * for this interrupt. Indications will be cleared on related acks.
2455 * New indications can and will light up during processing,
2456 * and will generate new interrupt after enabling master.
2458 return raw_reg_read(regs
, GEN11_GFX_MSTR_IRQ
);
2461 static inline void gen11_master_intr_enable(void __iomem
* const regs
)
2463 raw_reg_write(regs
, GEN11_GFX_MSTR_IRQ
, GEN11_MASTER_IRQ
);
2467 gen11_display_irq_handler(struct drm_i915_private
*i915
)
2469 void __iomem
* const regs
= i915
->uncore
.regs
;
2470 const u32 disp_ctl
= raw_reg_read(regs
, GEN11_DISPLAY_INT_CTL
);
2472 disable_rpm_wakeref_asserts(&i915
->runtime_pm
);
2474 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2475 * for the display related bits.
2477 raw_reg_write(regs
, GEN11_DISPLAY_INT_CTL
, 0x0);
2478 gen8_de_irq_handler(i915
, disp_ctl
);
2479 raw_reg_write(regs
, GEN11_DISPLAY_INT_CTL
,
2480 GEN11_DISPLAY_IRQ_ENABLE
);
2482 enable_rpm_wakeref_asserts(&i915
->runtime_pm
);
2485 static __always_inline irqreturn_t
2486 __gen11_irq_handler(struct drm_i915_private
* const i915
,
2487 u32 (*intr_disable
)(void __iomem
* const regs
),
2488 void (*intr_enable
)(void __iomem
* const regs
))
2490 void __iomem
* const regs
= i915
->uncore
.regs
;
2491 struct intel_gt
*gt
= &i915
->gt
;
2495 if (!intel_irqs_enabled(i915
))
2498 master_ctl
= intr_disable(regs
);
2504 /* Find, queue (onto bottom-halves), then clear each source */
2505 gen11_gt_irq_handler(gt
, master_ctl
);
2507 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2508 if (master_ctl
& GEN11_DISPLAY_IRQ
)
2509 gen11_display_irq_handler(i915
);
2511 gu_misc_iir
= gen11_gu_misc_irq_ack(gt
, master_ctl
);
2515 gen11_gu_misc_irq_handler(gt
, gu_misc_iir
);
2520 static irqreturn_t
gen11_irq_handler(int irq
, void *arg
)
2522 return __gen11_irq_handler(arg
,
2523 gen11_master_intr_disable
,
2524 gen11_master_intr_enable
);
2527 static u32
dg1_master_intr_disable_and_ack(void __iomem
* const regs
)
2531 /* First disable interrupts */
2532 raw_reg_write(regs
, DG1_MSTR_UNIT_INTR
, 0);
2534 /* Get the indication levels and ack the master unit */
2535 val
= raw_reg_read(regs
, DG1_MSTR_UNIT_INTR
);
2539 raw_reg_write(regs
, DG1_MSTR_UNIT_INTR
, val
);
2542 * Now with master disabled, get a sample of level indications
2543 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2544 * out as this bit doesn't exist anymore for DG1
2546 val
= raw_reg_read(regs
, GEN11_GFX_MSTR_IRQ
) & ~GEN11_MASTER_IRQ
;
2550 raw_reg_write(regs
, GEN11_GFX_MSTR_IRQ
, val
);
2555 static inline void dg1_master_intr_enable(void __iomem
* const regs
)
2557 raw_reg_write(regs
, DG1_MSTR_UNIT_INTR
, DG1_MSTR_IRQ
);
2560 static irqreturn_t
dg1_irq_handler(int irq
, void *arg
)
2562 return __gen11_irq_handler(arg
,
2563 dg1_master_intr_disable_and_ack
,
2564 dg1_master_intr_enable
);
2567 /* Called from drm generic code, passed 'crtc' which
2568 * we use as a pipe index
2570 int i8xx_enable_vblank(struct drm_crtc
*crtc
)
2572 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2573 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2574 unsigned long irqflags
;
2576 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2577 i915_enable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_STATUS
);
2578 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2583 int i915gm_enable_vblank(struct drm_crtc
*crtc
)
2585 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2588 * Vblank interrupts fail to wake the device up from C2+.
2589 * Disabling render clock gating during C-states avoids
2590 * the problem. There is a small power cost so we do this
2591 * only when vblank interrupts are actually enabled.
2593 if (dev_priv
->vblank_enabled
++ == 0)
2594 I915_WRITE(SCPD0
, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE
));
2596 return i8xx_enable_vblank(crtc
);
2599 int i965_enable_vblank(struct drm_crtc
*crtc
)
2601 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2602 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2603 unsigned long irqflags
;
2605 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2606 i915_enable_pipestat(dev_priv
, pipe
,
2607 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2608 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2613 int ilk_enable_vblank(struct drm_crtc
*crtc
)
2615 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2616 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2617 unsigned long irqflags
;
2618 u32 bit
= INTEL_GEN(dev_priv
) >= 7 ?
2619 DE_PIPE_VBLANK_IVB(pipe
) : DE_PIPE_VBLANK(pipe
);
2621 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2622 ilk_enable_display_irq(dev_priv
, bit
);
2623 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2625 /* Even though there is no DMC, frame counter can get stuck when
2626 * PSR is active as no frames are generated.
2628 if (HAS_PSR(dev_priv
))
2629 drm_crtc_vblank_restore(crtc
);
2634 int bdw_enable_vblank(struct drm_crtc
*crtc
)
2636 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2637 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2638 unsigned long irqflags
;
2640 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2641 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2642 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2644 /* Even if there is no DMC, frame counter can get stuck when
2645 * PSR is active as no frames are generated, so check only for PSR.
2647 if (HAS_PSR(dev_priv
))
2648 drm_crtc_vblank_restore(crtc
);
2653 /* Called from drm generic code, passed 'crtc' which
2654 * we use as a pipe index
2656 void i8xx_disable_vblank(struct drm_crtc
*crtc
)
2658 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2659 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2660 unsigned long irqflags
;
2662 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2663 i915_disable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_STATUS
);
2664 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2667 void i915gm_disable_vblank(struct drm_crtc
*crtc
)
2669 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2671 i8xx_disable_vblank(crtc
);
2673 if (--dev_priv
->vblank_enabled
== 0)
2674 I915_WRITE(SCPD0
, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE
));
2677 void i965_disable_vblank(struct drm_crtc
*crtc
)
2679 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2680 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2681 unsigned long irqflags
;
2683 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2684 i915_disable_pipestat(dev_priv
, pipe
,
2685 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2686 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2689 void ilk_disable_vblank(struct drm_crtc
*crtc
)
2691 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2692 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2693 unsigned long irqflags
;
2694 u32 bit
= INTEL_GEN(dev_priv
) >= 7 ?
2695 DE_PIPE_VBLANK_IVB(pipe
) : DE_PIPE_VBLANK(pipe
);
2697 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2698 ilk_disable_display_irq(dev_priv
, bit
);
2699 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2702 void bdw_disable_vblank(struct drm_crtc
*crtc
)
2704 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2705 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
2706 unsigned long irqflags
;
2708 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2709 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2710 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2713 static void ibx_irq_reset(struct drm_i915_private
*dev_priv
)
2715 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2717 if (HAS_PCH_NOP(dev_priv
))
2720 GEN3_IRQ_RESET(uncore
, SDE
);
2722 if (HAS_PCH_CPT(dev_priv
) || HAS_PCH_LPT(dev_priv
))
2723 I915_WRITE(SERR_INT
, 0xffffffff);
2727 * SDEIER is also touched by the interrupt handler to work around missed PCH
2728 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2729 * instead we unconditionally enable all PCH interrupt sources here, but then
2730 * only unmask them as needed with SDEIMR.
2732 * This function needs to be called before interrupts are enabled.
2734 static void ibx_irq_pre_postinstall(struct drm_i915_private
*dev_priv
)
2736 if (HAS_PCH_NOP(dev_priv
))
2739 drm_WARN_ON(&dev_priv
->drm
, I915_READ(SDEIER
) != 0);
2740 I915_WRITE(SDEIER
, 0xffffffff);
2741 POSTING_READ(SDEIER
);
2744 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
2746 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2748 if (IS_CHERRYVIEW(dev_priv
))
2749 intel_uncore_write(uncore
, DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
2751 intel_uncore_write(uncore
, DPINVGTT
, DPINVGTT_STATUS_MASK
);
2753 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
2754 intel_uncore_write(uncore
, PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2756 i9xx_pipestat_irq_reset(dev_priv
);
2758 GEN3_IRQ_RESET(uncore
, VLV_
);
2759 dev_priv
->irq_mask
= ~0u;
2762 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
2764 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2770 pipestat_mask
= PIPE_CRC_DONE_INTERRUPT_STATUS
;
2772 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
2773 for_each_pipe(dev_priv
, pipe
)
2774 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
2776 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
2777 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2778 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2779 I915_LPE_PIPE_A_INTERRUPT
|
2780 I915_LPE_PIPE_B_INTERRUPT
;
2782 if (IS_CHERRYVIEW(dev_priv
))
2783 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
|
2784 I915_LPE_PIPE_C_INTERRUPT
;
2786 drm_WARN_ON(&dev_priv
->drm
, dev_priv
->irq_mask
!= ~0u);
2788 dev_priv
->irq_mask
= ~enable_mask
;
2790 GEN3_IRQ_INIT(uncore
, VLV_
, dev_priv
->irq_mask
, enable_mask
);
2795 static void ilk_irq_reset(struct drm_i915_private
*dev_priv
)
2797 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2799 GEN3_IRQ_RESET(uncore
, DE
);
2800 if (IS_GEN(dev_priv
, 7))
2801 intel_uncore_write(uncore
, GEN7_ERR_INT
, 0xffffffff);
2803 if (IS_HASWELL(dev_priv
)) {
2804 intel_uncore_write(uncore
, EDP_PSR_IMR
, 0xffffffff);
2805 intel_uncore_write(uncore
, EDP_PSR_IIR
, 0xffffffff);
2808 gen5_gt_irq_reset(&dev_priv
->gt
);
2810 ibx_irq_reset(dev_priv
);
2813 static void valleyview_irq_reset(struct drm_i915_private
*dev_priv
)
2815 I915_WRITE(VLV_MASTER_IER
, 0);
2816 POSTING_READ(VLV_MASTER_IER
);
2818 gen5_gt_irq_reset(&dev_priv
->gt
);
2820 spin_lock_irq(&dev_priv
->irq_lock
);
2821 if (dev_priv
->display_irqs_enabled
)
2822 vlv_display_irq_reset(dev_priv
);
2823 spin_unlock_irq(&dev_priv
->irq_lock
);
2826 static void gen8_irq_reset(struct drm_i915_private
*dev_priv
)
2828 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2831 gen8_master_intr_disable(dev_priv
->uncore
.regs
);
2833 gen8_gt_irq_reset(&dev_priv
->gt
);
2835 intel_uncore_write(uncore
, EDP_PSR_IMR
, 0xffffffff);
2836 intel_uncore_write(uncore
, EDP_PSR_IIR
, 0xffffffff);
2838 for_each_pipe(dev_priv
, pipe
)
2839 if (intel_display_power_is_enabled(dev_priv
,
2840 POWER_DOMAIN_PIPE(pipe
)))
2841 GEN8_IRQ_RESET_NDX(uncore
, DE_PIPE
, pipe
);
2843 GEN3_IRQ_RESET(uncore
, GEN8_DE_PORT_
);
2844 GEN3_IRQ_RESET(uncore
, GEN8_DE_MISC_
);
2845 GEN3_IRQ_RESET(uncore
, GEN8_PCU_
);
2847 if (HAS_PCH_SPLIT(dev_priv
))
2848 ibx_irq_reset(dev_priv
);
2851 static void gen11_display_irq_reset(struct drm_i915_private
*dev_priv
)
2853 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2855 u32 trans_mask
= BIT(TRANSCODER_A
) | BIT(TRANSCODER_B
) |
2856 BIT(TRANSCODER_C
) | BIT(TRANSCODER_D
);
2858 intel_uncore_write(uncore
, GEN11_DISPLAY_INT_CTL
, 0);
2860 if (INTEL_GEN(dev_priv
) >= 12) {
2861 enum transcoder trans
;
2863 for_each_cpu_transcoder_masked(dev_priv
, trans
, trans_mask
) {
2864 enum intel_display_power_domain domain
;
2866 domain
= POWER_DOMAIN_TRANSCODER(trans
);
2867 if (!intel_display_power_is_enabled(dev_priv
, domain
))
2870 intel_uncore_write(uncore
, TRANS_PSR_IMR(trans
), 0xffffffff);
2871 intel_uncore_write(uncore
, TRANS_PSR_IIR(trans
), 0xffffffff);
2874 intel_uncore_write(uncore
, EDP_PSR_IMR
, 0xffffffff);
2875 intel_uncore_write(uncore
, EDP_PSR_IIR
, 0xffffffff);
2878 for_each_pipe(dev_priv
, pipe
)
2879 if (intel_display_power_is_enabled(dev_priv
,
2880 POWER_DOMAIN_PIPE(pipe
)))
2881 GEN8_IRQ_RESET_NDX(uncore
, DE_PIPE
, pipe
);
2883 GEN3_IRQ_RESET(uncore
, GEN8_DE_PORT_
);
2884 GEN3_IRQ_RESET(uncore
, GEN8_DE_MISC_
);
2885 GEN3_IRQ_RESET(uncore
, GEN11_DE_HPD_
);
2887 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
)
2888 GEN3_IRQ_RESET(uncore
, SDE
);
2890 /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
2891 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
) {
2892 intel_uncore_rmw(uncore
, SOUTH_CHICKEN1
,
2893 SBCLK_RUN_REFCLK_DIS
, SBCLK_RUN_REFCLK_DIS
);
2894 intel_uncore_rmw(uncore
, SOUTH_CHICKEN1
,
2895 SBCLK_RUN_REFCLK_DIS
, 0);
2899 static void gen11_irq_reset(struct drm_i915_private
*dev_priv
)
2901 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2903 if (HAS_MASTER_UNIT_IRQ(dev_priv
))
2904 dg1_master_intr_disable_and_ack(dev_priv
->uncore
.regs
);
2906 gen11_master_intr_disable(dev_priv
->uncore
.regs
);
2908 gen11_gt_irq_reset(&dev_priv
->gt
);
2909 gen11_display_irq_reset(dev_priv
);
2911 GEN3_IRQ_RESET(uncore
, GEN11_GU_MISC_
);
2912 GEN3_IRQ_RESET(uncore
, GEN8_PCU_
);
2915 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
2918 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2920 u32 extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
2923 spin_lock_irq(&dev_priv
->irq_lock
);
2925 if (!intel_irqs_enabled(dev_priv
)) {
2926 spin_unlock_irq(&dev_priv
->irq_lock
);
2930 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
2931 GEN8_IRQ_INIT_NDX(uncore
, DE_PIPE
, pipe
,
2932 dev_priv
->de_irq_mask
[pipe
],
2933 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
2935 spin_unlock_irq(&dev_priv
->irq_lock
);
2938 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
2941 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2944 spin_lock_irq(&dev_priv
->irq_lock
);
2946 if (!intel_irqs_enabled(dev_priv
)) {
2947 spin_unlock_irq(&dev_priv
->irq_lock
);
2951 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
2952 GEN8_IRQ_RESET_NDX(uncore
, DE_PIPE
, pipe
);
2954 spin_unlock_irq(&dev_priv
->irq_lock
);
2956 /* make sure we're done processing display irqs */
2957 intel_synchronize_irq(dev_priv
);
2960 static void cherryview_irq_reset(struct drm_i915_private
*dev_priv
)
2962 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
2964 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2965 POSTING_READ(GEN8_MASTER_IRQ
);
2967 gen8_gt_irq_reset(&dev_priv
->gt
);
2969 GEN3_IRQ_RESET(uncore
, GEN8_PCU_
);
2971 spin_lock_irq(&dev_priv
->irq_lock
);
2972 if (dev_priv
->display_irqs_enabled
)
2973 vlv_display_irq_reset(dev_priv
);
2974 spin_unlock_irq(&dev_priv
->irq_lock
);
2977 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
2978 const u32 hpd
[HPD_NUM_PINS
])
2980 struct intel_encoder
*encoder
;
2981 u32 enabled_irqs
= 0;
2983 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
2984 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
2985 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
2987 return enabled_irqs
;
2990 static u32
intel_hpd_hotplug_irqs(struct drm_i915_private
*dev_priv
,
2991 const u32 hpd
[HPD_NUM_PINS
])
2993 struct intel_encoder
*encoder
;
2994 u32 hotplug_irqs
= 0;
2996 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
2997 hotplug_irqs
|= hpd
[encoder
->hpd_pin
];
2999 return hotplug_irqs
;
3002 static void ibx_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3007 * Enable digital hotplug on the PCH, and configure the DP short pulse
3008 * duration to 2ms (which is the minimum in the Display Port spec).
3009 * The pulse duration bits are reserved on LPT+.
3011 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3012 hotplug
&= ~(PORTB_PULSE_DURATION_MASK
|
3013 PORTC_PULSE_DURATION_MASK
|
3014 PORTD_PULSE_DURATION_MASK
);
3015 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3016 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3017 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3019 * When CPU and PCH are on the same package, port A
3020 * HPD must be enabled in both north and south.
3022 if (HAS_PCH_LPT_LP(dev_priv
))
3023 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3024 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3027 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3029 u32 hotplug_irqs
, enabled_irqs
;
3031 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, dev_priv
->hotplug
.pch_hpd
);
3032 hotplug_irqs
= intel_hpd_hotplug_irqs(dev_priv
, dev_priv
->hotplug
.pch_hpd
);
3034 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3036 ibx_hpd_detection_setup(dev_priv
);
3039 static void icp_ddi_hpd_detection_setup(struct drm_i915_private
*dev_priv
,
3044 hotplug
= I915_READ(SHOTPLUG_CTL_DDI
);
3045 hotplug
|= enable_mask
;
3046 I915_WRITE(SHOTPLUG_CTL_DDI
, hotplug
);
3049 static void icp_tc_hpd_detection_setup(struct drm_i915_private
*dev_priv
,
3054 hotplug
= I915_READ(SHOTPLUG_CTL_TC
);
3055 hotplug
|= enable_mask
;
3056 I915_WRITE(SHOTPLUG_CTL_TC
, hotplug
);
3059 static void icp_hpd_irq_setup(struct drm_i915_private
*dev_priv
,
3060 u32 ddi_enable_mask
, u32 tc_enable_mask
)
3062 u32 hotplug_irqs
, enabled_irqs
;
3064 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, dev_priv
->hotplug
.pch_hpd
);
3065 hotplug_irqs
= intel_hpd_hotplug_irqs(dev_priv
, dev_priv
->hotplug
.pch_hpd
);
3067 if (INTEL_PCH_TYPE(dev_priv
) <= PCH_TGP
)
3068 I915_WRITE(SHPD_FILTER_CNT
, SHPD_FILTER_CNT_500_ADJ
);
3070 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3072 icp_ddi_hpd_detection_setup(dev_priv
, ddi_enable_mask
);
3074 icp_tc_hpd_detection_setup(dev_priv
, tc_enable_mask
);
3078 * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3079 * equivalent of SDE.
3081 static void mcc_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3083 icp_hpd_irq_setup(dev_priv
,
3084 ICP_DDI_HPD_ENABLE_MASK
, ICP_TC_HPD_ENABLE(PORT_TC1
));
3088 * JSP behaves exactly the same as MCC above except that port C is mapped to
3089 * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
3090 * masks & tables rather than ICP's masks & tables.
3092 static void jsp_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3094 icp_hpd_irq_setup(dev_priv
,
3095 TGP_DDI_HPD_ENABLE_MASK
, 0);
3098 static void gen11_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3102 hotplug
= I915_READ(GEN11_TC_HOTPLUG_CTL
);
3103 hotplug
|= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1
) |
3104 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2
) |
3105 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3
) |
3106 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4
) |
3107 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5
) |
3108 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6
);
3109 I915_WRITE(GEN11_TC_HOTPLUG_CTL
, hotplug
);
3111 hotplug
= I915_READ(GEN11_TBT_HOTPLUG_CTL
);
3112 hotplug
|= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1
) |
3113 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2
) |
3114 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3
) |
3115 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4
) |
3116 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5
) |
3117 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6
);
3118 I915_WRITE(GEN11_TBT_HOTPLUG_CTL
, hotplug
);
3121 static void gen11_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3123 u32 hotplug_irqs
, enabled_irqs
;
3126 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, dev_priv
->hotplug
.hpd
);
3127 hotplug_irqs
= intel_hpd_hotplug_irqs(dev_priv
, dev_priv
->hotplug
.hpd
);
3129 val
= I915_READ(GEN11_DE_HPD_IMR
);
3130 val
&= ~hotplug_irqs
;
3131 val
|= ~enabled_irqs
& hotplug_irqs
;
3132 I915_WRITE(GEN11_DE_HPD_IMR
, val
);
3133 POSTING_READ(GEN11_DE_HPD_IMR
);
3135 gen11_hpd_detection_setup(dev_priv
);
3137 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_TGP
)
3138 icp_hpd_irq_setup(dev_priv
,
3139 TGP_DDI_HPD_ENABLE_MASK
, TGP_TC_HPD_ENABLE_MASK
);
3140 else if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
)
3141 icp_hpd_irq_setup(dev_priv
,
3142 ICP_DDI_HPD_ENABLE_MASK
, ICP_TC_HPD_ENABLE_MASK
);
3145 static void spt_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3149 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3150 if (HAS_PCH_CNP(dev_priv
)) {
3151 val
= I915_READ(SOUTH_CHICKEN1
);
3152 val
&= ~CHASSIS_CLK_REQ_DURATION_MASK
;
3153 val
|= CHASSIS_CLK_REQ_DURATION(0xf);
3154 I915_WRITE(SOUTH_CHICKEN1
, val
);
3157 /* Enable digital hotplug on the PCH */
3158 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3159 hotplug
|= PORTA_HOTPLUG_ENABLE
|
3160 PORTB_HOTPLUG_ENABLE
|
3161 PORTC_HOTPLUG_ENABLE
|
3162 PORTD_HOTPLUG_ENABLE
;
3163 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3165 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3166 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3167 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3170 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3172 u32 hotplug_irqs
, enabled_irqs
;
3174 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_CNP
)
3175 I915_WRITE(SHPD_FILTER_CNT
, SHPD_FILTER_CNT_500_ADJ
);
3177 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, dev_priv
->hotplug
.pch_hpd
);
3178 hotplug_irqs
= intel_hpd_hotplug_irqs(dev_priv
, dev_priv
->hotplug
.pch_hpd
);
3180 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3182 spt_hpd_detection_setup(dev_priv
);
3185 static void ilk_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3190 * Enable digital hotplug on the CPU, and configure the DP short pulse
3191 * duration to 2ms (which is the minimum in the Display Port spec)
3192 * The pulse duration bits are reserved on HSW+.
3194 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3195 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3196 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
|
3197 DIGITAL_PORTA_PULSE_DURATION_2ms
;
3198 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3201 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3203 u32 hotplug_irqs
, enabled_irqs
;
3205 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, dev_priv
->hotplug
.hpd
);
3206 hotplug_irqs
= intel_hpd_hotplug_irqs(dev_priv
, dev_priv
->hotplug
.hpd
);
3208 if (INTEL_GEN(dev_priv
) >= 8)
3209 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3211 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3213 ilk_hpd_detection_setup(dev_priv
);
3215 ibx_hpd_irq_setup(dev_priv
);
3218 static void __bxt_hpd_detection_setup(struct drm_i915_private
*dev_priv
,
3223 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3224 hotplug
|= PORTA_HOTPLUG_ENABLE
|
3225 PORTB_HOTPLUG_ENABLE
|
3226 PORTC_HOTPLUG_ENABLE
;
3228 drm_dbg_kms(&dev_priv
->drm
,
3229 "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3230 hotplug
, enabled_irqs
);
3231 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3234 * For BXT invert bit has to be set based on AOB design
3235 * for HPD detection logic, update it based on VBT fields.
3237 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3238 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3239 hotplug
|= BXT_DDIA_HPD_INVERT
;
3240 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3241 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3242 hotplug
|= BXT_DDIB_HPD_INVERT
;
3243 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3244 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3245 hotplug
|= BXT_DDIC_HPD_INVERT
;
3247 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3250 static void bxt_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3252 __bxt_hpd_detection_setup(dev_priv
, BXT_DE_PORT_HOTPLUG_MASK
);
3255 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3257 u32 hotplug_irqs
, enabled_irqs
;
3259 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, dev_priv
->hotplug
.hpd
);
3260 hotplug_irqs
= intel_hpd_hotplug_irqs(dev_priv
, dev_priv
->hotplug
.hpd
);
3262 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3264 __bxt_hpd_detection_setup(dev_priv
, enabled_irqs
);
3267 static void ibx_irq_postinstall(struct drm_i915_private
*dev_priv
)
3271 if (HAS_PCH_NOP(dev_priv
))
3274 if (HAS_PCH_IBX(dev_priv
))
3275 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3276 else if (HAS_PCH_CPT(dev_priv
) || HAS_PCH_LPT(dev_priv
))
3277 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3279 mask
= SDE_GMBUS_CPT
;
3281 gen3_assert_iir_is_zero(&dev_priv
->uncore
, SDEIIR
);
3282 I915_WRITE(SDEIMR
, ~mask
);
3284 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
3285 HAS_PCH_LPT(dev_priv
))
3286 ibx_hpd_detection_setup(dev_priv
);
3288 spt_hpd_detection_setup(dev_priv
);
3291 static void ilk_irq_postinstall(struct drm_i915_private
*dev_priv
)
3293 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3294 u32 display_mask
, extra_mask
;
3296 if (INTEL_GEN(dev_priv
) >= 7) {
3297 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3298 DE_PCH_EVENT_IVB
| DE_AUX_CHANNEL_A_IVB
);
3299 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3300 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3301 DE_DP_A_HOTPLUG_IVB
);
3303 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3304 DE_AUX_CHANNEL_A
| DE_PIPEB_CRC_DONE
|
3305 DE_PIPEA_CRC_DONE
| DE_POISON
);
3306 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3307 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3311 if (IS_HASWELL(dev_priv
)) {
3312 gen3_assert_iir_is_zero(uncore
, EDP_PSR_IIR
);
3313 display_mask
|= DE_EDP_PSR_INT_HSW
;
3316 dev_priv
->irq_mask
= ~display_mask
;
3318 ibx_irq_pre_postinstall(dev_priv
);
3320 GEN3_IRQ_INIT(uncore
, DE
, dev_priv
->irq_mask
,
3321 display_mask
| extra_mask
);
3323 gen5_gt_irq_postinstall(&dev_priv
->gt
);
3325 ilk_hpd_detection_setup(dev_priv
);
3327 ibx_irq_postinstall(dev_priv
);
3329 if (IS_IRONLAKE_M(dev_priv
)) {
3330 /* Enable PCU event interrupts
3332 * spinlocking not required here for correctness since interrupt
3333 * setup is guaranteed to run in single-threaded context. But we
3334 * need it to make the assert_spin_locked happy. */
3335 spin_lock_irq(&dev_priv
->irq_lock
);
3336 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3337 spin_unlock_irq(&dev_priv
->irq_lock
);
3341 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3343 lockdep_assert_held(&dev_priv
->irq_lock
);
3345 if (dev_priv
->display_irqs_enabled
)
3348 dev_priv
->display_irqs_enabled
= true;
3350 if (intel_irqs_enabled(dev_priv
)) {
3351 vlv_display_irq_reset(dev_priv
);
3352 vlv_display_irq_postinstall(dev_priv
);
3356 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3358 lockdep_assert_held(&dev_priv
->irq_lock
);
3360 if (!dev_priv
->display_irqs_enabled
)
3363 dev_priv
->display_irqs_enabled
= false;
3365 if (intel_irqs_enabled(dev_priv
))
3366 vlv_display_irq_reset(dev_priv
);
3370 static void valleyview_irq_postinstall(struct drm_i915_private
*dev_priv
)
3372 gen5_gt_irq_postinstall(&dev_priv
->gt
);
3374 spin_lock_irq(&dev_priv
->irq_lock
);
3375 if (dev_priv
->display_irqs_enabled
)
3376 vlv_display_irq_postinstall(dev_priv
);
3377 spin_unlock_irq(&dev_priv
->irq_lock
);
3379 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3380 POSTING_READ(VLV_MASTER_IER
);
3383 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3385 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3387 u32 de_pipe_masked
= gen8_de_pipe_fault_mask(dev_priv
) |
3388 GEN8_PIPE_CDCLK_CRC_DONE
;
3389 u32 de_pipe_enables
;
3390 u32 de_port_masked
= gen8_de_port_aux_mask(dev_priv
);
3391 u32 de_port_enables
;
3392 u32 de_misc_masked
= GEN8_DE_EDP_PSR
;
3393 u32 trans_mask
= BIT(TRANSCODER_A
) | BIT(TRANSCODER_B
) |
3394 BIT(TRANSCODER_C
) | BIT(TRANSCODER_D
);
3397 if (INTEL_GEN(dev_priv
) <= 10)
3398 de_misc_masked
|= GEN8_DE_MISC_GSE
;
3400 if (IS_GEN9_LP(dev_priv
))
3401 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3403 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3404 GEN8_PIPE_FIFO_UNDERRUN
;
3406 de_port_enables
= de_port_masked
;
3407 if (IS_GEN9_LP(dev_priv
))
3408 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3409 else if (IS_BROADWELL(dev_priv
))
3410 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3412 if (INTEL_GEN(dev_priv
) >= 12) {
3413 enum transcoder trans
;
3415 for_each_cpu_transcoder_masked(dev_priv
, trans
, trans_mask
) {
3416 enum intel_display_power_domain domain
;
3418 domain
= POWER_DOMAIN_TRANSCODER(trans
);
3419 if (!intel_display_power_is_enabled(dev_priv
, domain
))
3422 gen3_assert_iir_is_zero(uncore
, TRANS_PSR_IIR(trans
));
3425 gen3_assert_iir_is_zero(uncore
, EDP_PSR_IIR
);
3428 for_each_pipe(dev_priv
, pipe
) {
3429 dev_priv
->de_irq_mask
[pipe
] = ~de_pipe_masked
;
3431 if (intel_display_power_is_enabled(dev_priv
,
3432 POWER_DOMAIN_PIPE(pipe
)))
3433 GEN8_IRQ_INIT_NDX(uncore
, DE_PIPE
, pipe
,
3434 dev_priv
->de_irq_mask
[pipe
],
3438 GEN3_IRQ_INIT(uncore
, GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3439 GEN3_IRQ_INIT(uncore
, GEN8_DE_MISC_
, ~de_misc_masked
, de_misc_masked
);
3441 if (INTEL_GEN(dev_priv
) >= 11) {
3442 u32 de_hpd_masked
= 0;
3443 u32 de_hpd_enables
= GEN11_DE_TC_HOTPLUG_MASK
|
3444 GEN11_DE_TBT_HOTPLUG_MASK
;
3446 GEN3_IRQ_INIT(uncore
, GEN11_DE_HPD_
, ~de_hpd_masked
,
3448 gen11_hpd_detection_setup(dev_priv
);
3449 } else if (IS_GEN9_LP(dev_priv
)) {
3450 bxt_hpd_detection_setup(dev_priv
);
3451 } else if (IS_BROADWELL(dev_priv
)) {
3452 ilk_hpd_detection_setup(dev_priv
);
3456 static void gen8_irq_postinstall(struct drm_i915_private
*dev_priv
)
3458 if (HAS_PCH_SPLIT(dev_priv
))
3459 ibx_irq_pre_postinstall(dev_priv
);
3461 gen8_gt_irq_postinstall(&dev_priv
->gt
);
3462 gen8_de_irq_postinstall(dev_priv
);
3464 if (HAS_PCH_SPLIT(dev_priv
))
3465 ibx_irq_postinstall(dev_priv
);
3467 gen8_master_intr_enable(dev_priv
->uncore
.regs
);
3470 static void icp_irq_postinstall(struct drm_i915_private
*dev_priv
)
3472 u32 mask
= SDE_GMBUS_ICP
;
3474 drm_WARN_ON(&dev_priv
->drm
, I915_READ(SDEIER
) != 0);
3475 I915_WRITE(SDEIER
, 0xffffffff);
3476 POSTING_READ(SDEIER
);
3478 gen3_assert_iir_is_zero(&dev_priv
->uncore
, SDEIIR
);
3479 I915_WRITE(SDEIMR
, ~mask
);
3481 if (HAS_PCH_TGP(dev_priv
)) {
3482 icp_ddi_hpd_detection_setup(dev_priv
, TGP_DDI_HPD_ENABLE_MASK
);
3483 icp_tc_hpd_detection_setup(dev_priv
, TGP_TC_HPD_ENABLE_MASK
);
3484 } else if (HAS_PCH_JSP(dev_priv
)) {
3485 icp_ddi_hpd_detection_setup(dev_priv
, TGP_DDI_HPD_ENABLE_MASK
);
3486 } else if (HAS_PCH_MCC(dev_priv
)) {
3487 icp_ddi_hpd_detection_setup(dev_priv
, ICP_DDI_HPD_ENABLE_MASK
);
3488 icp_tc_hpd_detection_setup(dev_priv
, ICP_TC_HPD_ENABLE(PORT_TC1
));
3490 icp_ddi_hpd_detection_setup(dev_priv
, ICP_DDI_HPD_ENABLE_MASK
);
3491 icp_tc_hpd_detection_setup(dev_priv
, ICP_TC_HPD_ENABLE_MASK
);
3495 static void gen11_irq_postinstall(struct drm_i915_private
*dev_priv
)
3497 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3498 u32 gu_misc_masked
= GEN11_GU_MISC_GSE
;
3500 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
)
3501 icp_irq_postinstall(dev_priv
);
3503 gen11_gt_irq_postinstall(&dev_priv
->gt
);
3504 gen8_de_irq_postinstall(dev_priv
);
3506 GEN3_IRQ_INIT(uncore
, GEN11_GU_MISC_
, ~gu_misc_masked
, gu_misc_masked
);
3508 I915_WRITE(GEN11_DISPLAY_INT_CTL
, GEN11_DISPLAY_IRQ_ENABLE
);
3510 if (HAS_MASTER_UNIT_IRQ(dev_priv
)) {
3511 dg1_master_intr_enable(uncore
->regs
);
3512 POSTING_READ(DG1_MSTR_UNIT_INTR
);
3514 gen11_master_intr_enable(uncore
->regs
);
3515 POSTING_READ(GEN11_GFX_MSTR_IRQ
);
3519 static void cherryview_irq_postinstall(struct drm_i915_private
*dev_priv
)
3521 gen8_gt_irq_postinstall(&dev_priv
->gt
);
3523 spin_lock_irq(&dev_priv
->irq_lock
);
3524 if (dev_priv
->display_irqs_enabled
)
3525 vlv_display_irq_postinstall(dev_priv
);
3526 spin_unlock_irq(&dev_priv
->irq_lock
);
3528 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3529 POSTING_READ(GEN8_MASTER_IRQ
);
3532 static void i8xx_irq_reset(struct drm_i915_private
*dev_priv
)
3534 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3536 i9xx_pipestat_irq_reset(dev_priv
);
3538 GEN2_IRQ_RESET(uncore
);
3541 static void i8xx_irq_postinstall(struct drm_i915_private
*dev_priv
)
3543 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3546 intel_uncore_write16(uncore
,
3548 ~(I915_ERROR_PAGE_TABLE
|
3549 I915_ERROR_MEMORY_REFRESH
));
3551 /* Unmask the interrupts that we always want on. */
3552 dev_priv
->irq_mask
=
3553 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3554 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3555 I915_MASTER_ERROR_INTERRUPT
);
3558 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3559 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3560 I915_MASTER_ERROR_INTERRUPT
|
3561 I915_USER_INTERRUPT
;
3563 GEN2_IRQ_INIT(uncore
, dev_priv
->irq_mask
, enable_mask
);
3565 /* Interrupt setup is already guaranteed to be single-threaded, this is
3566 * just to make the assert_spin_locked check happy. */
3567 spin_lock_irq(&dev_priv
->irq_lock
);
3568 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3569 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3570 spin_unlock_irq(&dev_priv
->irq_lock
);
3573 static void i8xx_error_irq_ack(struct drm_i915_private
*i915
,
3574 u16
*eir
, u16
*eir_stuck
)
3576 struct intel_uncore
*uncore
= &i915
->uncore
;
3579 *eir
= intel_uncore_read16(uncore
, EIR
);
3582 intel_uncore_write16(uncore
, EIR
, *eir
);
3584 *eir_stuck
= intel_uncore_read16(uncore
, EIR
);
3585 if (*eir_stuck
== 0)
3589 * Toggle all EMR bits to make sure we get an edge
3590 * in the ISR master error bit if we don't clear
3591 * all the EIR bits. Otherwise the edge triggered
3592 * IIR on i965/g4x wouldn't notice that an interrupt
3593 * is still pending. Also some EIR bits can't be
3594 * cleared except by handling the underlying error
3595 * (or by a GPU reset) so we mask any bit that
3598 emr
= intel_uncore_read16(uncore
, EMR
);
3599 intel_uncore_write16(uncore
, EMR
, 0xffff);
3600 intel_uncore_write16(uncore
, EMR
, emr
| *eir_stuck
);
3603 static void i8xx_error_irq_handler(struct drm_i915_private
*dev_priv
,
3604 u16 eir
, u16 eir_stuck
)
3606 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir
);
3609 drm_dbg(&dev_priv
->drm
, "EIR stuck: 0x%04x, masked\n",
3613 static void i9xx_error_irq_ack(struct drm_i915_private
*dev_priv
,
3614 u32
*eir
, u32
*eir_stuck
)
3618 *eir
= I915_READ(EIR
);
3620 I915_WRITE(EIR
, *eir
);
3622 *eir_stuck
= I915_READ(EIR
);
3623 if (*eir_stuck
== 0)
3627 * Toggle all EMR bits to make sure we get an edge
3628 * in the ISR master error bit if we don't clear
3629 * all the EIR bits. Otherwise the edge triggered
3630 * IIR on i965/g4x wouldn't notice that an interrupt
3631 * is still pending. Also some EIR bits can't be
3632 * cleared except by handling the underlying error
3633 * (or by a GPU reset) so we mask any bit that
3636 emr
= I915_READ(EMR
);
3637 I915_WRITE(EMR
, 0xffffffff);
3638 I915_WRITE(EMR
, emr
| *eir_stuck
);
3641 static void i9xx_error_irq_handler(struct drm_i915_private
*dev_priv
,
3642 u32 eir
, u32 eir_stuck
)
3644 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir
);
3647 drm_dbg(&dev_priv
->drm
, "EIR stuck: 0x%08x, masked\n",
3651 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3653 struct drm_i915_private
*dev_priv
= arg
;
3654 irqreturn_t ret
= IRQ_NONE
;
3656 if (!intel_irqs_enabled(dev_priv
))
3659 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3660 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
3663 u32 pipe_stats
[I915_MAX_PIPES
] = {};
3664 u16 eir
= 0, eir_stuck
= 0;
3667 iir
= intel_uncore_read16(&dev_priv
->uncore
, GEN2_IIR
);
3673 /* Call regardless, as some status bits might not be
3674 * signalled in iir */
3675 i9xx_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
3677 if (iir
& I915_MASTER_ERROR_INTERRUPT
)
3678 i8xx_error_irq_ack(dev_priv
, &eir
, &eir_stuck
);
3680 intel_uncore_write16(&dev_priv
->uncore
, GEN2_IIR
, iir
);
3682 if (iir
& I915_USER_INTERRUPT
)
3683 intel_engine_signal_breadcrumbs(dev_priv
->gt
.engine
[RCS0
]);
3685 if (iir
& I915_MASTER_ERROR_INTERRUPT
)
3686 i8xx_error_irq_handler(dev_priv
, eir
, eir_stuck
);
3688 i8xx_pipestat_irq_handler(dev_priv
, iir
, pipe_stats
);
3691 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
3696 static void i915_irq_reset(struct drm_i915_private
*dev_priv
)
3698 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3700 if (I915_HAS_HOTPLUG(dev_priv
)) {
3701 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3702 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3705 i9xx_pipestat_irq_reset(dev_priv
);
3707 GEN3_IRQ_RESET(uncore
, GEN2_
);
3710 static void i915_irq_postinstall(struct drm_i915_private
*dev_priv
)
3712 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3715 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
|
3716 I915_ERROR_MEMORY_REFRESH
));
3718 /* Unmask the interrupts that we always want on. */
3719 dev_priv
->irq_mask
=
3720 ~(I915_ASLE_INTERRUPT
|
3721 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3722 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3723 I915_MASTER_ERROR_INTERRUPT
);
3726 I915_ASLE_INTERRUPT
|
3727 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3728 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3729 I915_MASTER_ERROR_INTERRUPT
|
3730 I915_USER_INTERRUPT
;
3732 if (I915_HAS_HOTPLUG(dev_priv
)) {
3733 /* Enable in IER... */
3734 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3735 /* and unmask in IMR */
3736 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3739 GEN3_IRQ_INIT(uncore
, GEN2_
, dev_priv
->irq_mask
, enable_mask
);
3741 /* Interrupt setup is already guaranteed to be single-threaded, this is
3742 * just to make the assert_spin_locked check happy. */
3743 spin_lock_irq(&dev_priv
->irq_lock
);
3744 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3745 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3746 spin_unlock_irq(&dev_priv
->irq_lock
);
3748 i915_enable_asle_pipestat(dev_priv
);
3751 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3753 struct drm_i915_private
*dev_priv
= arg
;
3754 irqreturn_t ret
= IRQ_NONE
;
3756 if (!intel_irqs_enabled(dev_priv
))
3759 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3760 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
3763 u32 pipe_stats
[I915_MAX_PIPES
] = {};
3764 u32 eir
= 0, eir_stuck
= 0;
3765 u32 hotplug_status
= 0;
3768 iir
= I915_READ(GEN2_IIR
);
3774 if (I915_HAS_HOTPLUG(dev_priv
) &&
3775 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3776 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
3778 /* Call regardless, as some status bits might not be
3779 * signalled in iir */
3780 i9xx_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
3782 if (iir
& I915_MASTER_ERROR_INTERRUPT
)
3783 i9xx_error_irq_ack(dev_priv
, &eir
, &eir_stuck
);
3785 I915_WRITE(GEN2_IIR
, iir
);
3787 if (iir
& I915_USER_INTERRUPT
)
3788 intel_engine_signal_breadcrumbs(dev_priv
->gt
.engine
[RCS0
]);
3790 if (iir
& I915_MASTER_ERROR_INTERRUPT
)
3791 i9xx_error_irq_handler(dev_priv
, eir
, eir_stuck
);
3794 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
3796 i915_pipestat_irq_handler(dev_priv
, iir
, pipe_stats
);
3799 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
3804 static void i965_irq_reset(struct drm_i915_private
*dev_priv
)
3806 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3808 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3809 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3811 i9xx_pipestat_irq_reset(dev_priv
);
3813 GEN3_IRQ_RESET(uncore
, GEN2_
);
3816 static void i965_irq_postinstall(struct drm_i915_private
*dev_priv
)
3818 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
3823 * Enable some error detection, note the instruction error mask
3824 * bit is reserved, so we leave it masked.
3826 if (IS_G4X(dev_priv
)) {
3827 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3828 GM45_ERROR_MEM_PRIV
|
3829 GM45_ERROR_CP_PRIV
|
3830 I915_ERROR_MEMORY_REFRESH
);
3832 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3833 I915_ERROR_MEMORY_REFRESH
);
3835 I915_WRITE(EMR
, error_mask
);
3837 /* Unmask the interrupts that we always want on. */
3838 dev_priv
->irq_mask
=
3839 ~(I915_ASLE_INTERRUPT
|
3840 I915_DISPLAY_PORT_INTERRUPT
|
3841 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3842 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3843 I915_MASTER_ERROR_INTERRUPT
);
3846 I915_ASLE_INTERRUPT
|
3847 I915_DISPLAY_PORT_INTERRUPT
|
3848 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3849 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3850 I915_MASTER_ERROR_INTERRUPT
|
3851 I915_USER_INTERRUPT
;
3853 if (IS_G4X(dev_priv
))
3854 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3856 GEN3_IRQ_INIT(uncore
, GEN2_
, dev_priv
->irq_mask
, enable_mask
);
3858 /* Interrupt setup is already guaranteed to be single-threaded, this is
3859 * just to make the assert_spin_locked check happy. */
3860 spin_lock_irq(&dev_priv
->irq_lock
);
3861 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3862 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3863 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3864 spin_unlock_irq(&dev_priv
->irq_lock
);
3866 i915_enable_asle_pipestat(dev_priv
);
3869 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3873 lockdep_assert_held(&dev_priv
->irq_lock
);
3875 /* Note HDMI and DP share hotplug bits */
3876 /* enable bits are the same for all generations */
3877 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
3878 /* Programming the CRT detection parameters tends
3879 to generate a spurious hotplug event about three
3880 seconds later. So just do it once.
3882 if (IS_G4X(dev_priv
))
3883 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3884 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3886 /* Ignore TV since it's buggy */
3887 i915_hotplug_interrupt_update_locked(dev_priv
,
3888 HOTPLUG_INT_EN_MASK
|
3889 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
3890 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
3894 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3896 struct drm_i915_private
*dev_priv
= arg
;
3897 irqreturn_t ret
= IRQ_NONE
;
3899 if (!intel_irqs_enabled(dev_priv
))
3902 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3903 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
3906 u32 pipe_stats
[I915_MAX_PIPES
] = {};
3907 u32 eir
= 0, eir_stuck
= 0;
3908 u32 hotplug_status
= 0;
3911 iir
= I915_READ(GEN2_IIR
);
3917 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
3918 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
3920 /* Call regardless, as some status bits might not be
3921 * signalled in iir */
3922 i9xx_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
3924 if (iir
& I915_MASTER_ERROR_INTERRUPT
)
3925 i9xx_error_irq_ack(dev_priv
, &eir
, &eir_stuck
);
3927 I915_WRITE(GEN2_IIR
, iir
);
3929 if (iir
& I915_USER_INTERRUPT
)
3930 intel_engine_signal_breadcrumbs(dev_priv
->gt
.engine
[RCS0
]);
3932 if (iir
& I915_BSD_USER_INTERRUPT
)
3933 intel_engine_signal_breadcrumbs(dev_priv
->gt
.engine
[VCS0
]);
3935 if (iir
& I915_MASTER_ERROR_INTERRUPT
)
3936 i9xx_error_irq_handler(dev_priv
, eir
, eir_stuck
);
3939 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
3941 i965_pipestat_irq_handler(dev_priv
, iir
, pipe_stats
);
3944 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
3950 * intel_irq_init - initializes irq support
3951 * @dev_priv: i915 device instance
3953 * This function initializes all the irq support including work items, timers
3954 * and all the vtables. It does not setup the interrupt itself though.
3956 void intel_irq_init(struct drm_i915_private
*dev_priv
)
3958 struct drm_device
*dev
= &dev_priv
->drm
;
3961 intel_hpd_init_pins(dev_priv
);
3963 intel_hpd_init_work(dev_priv
);
3965 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivb_parity_work
);
3966 for (i
= 0; i
< MAX_L3_SLICES
; ++i
)
3967 dev_priv
->l3_parity
.remap_info
[i
] = NULL
;
3969 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
3970 if (HAS_GT_UC(dev_priv
) && INTEL_GEN(dev_priv
) < 11)
3971 dev_priv
->gt
.pm_guc_events
= GUC_INTR_GUC2HOST
<< 16;
3973 dev
->vblank_disable_immediate
= true;
3975 /* Most platforms treat the display irq block as an always-on
3976 * power domain. vlv/chv can disable it at runtime and need
3977 * special care to avoid writing any of the display block registers
3978 * outside of the power domain. We defer setting up the display irqs
3979 * in this case to the runtime pm.
3981 dev_priv
->display_irqs_enabled
= true;
3982 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3983 dev_priv
->display_irqs_enabled
= false;
3985 dev_priv
->hotplug
.hpd_storm_threshold
= HPD_STORM_DEFAULT_THRESHOLD
;
3986 /* If we have MST support, we want to avoid doing short HPD IRQ storm
3987 * detection, as short HPD storms will occur as a natural part of
3988 * sideband messaging with MST.
3989 * On older platforms however, IRQ storms can occur with both long and
3990 * short pulses, as seen on some G4x systems.
3992 dev_priv
->hotplug
.hpd_short_storm_enabled
= !HAS_DP_MST(dev_priv
);
3994 if (HAS_GMCH(dev_priv
)) {
3995 if (I915_HAS_HOTPLUG(dev_priv
))
3996 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3998 if (HAS_PCH_JSP(dev_priv
))
3999 dev_priv
->display
.hpd_irq_setup
= jsp_hpd_irq_setup
;
4000 else if (HAS_PCH_MCC(dev_priv
))
4001 dev_priv
->display
.hpd_irq_setup
= mcc_hpd_irq_setup
;
4002 else if (INTEL_GEN(dev_priv
) >= 11)
4003 dev_priv
->display
.hpd_irq_setup
= gen11_hpd_irq_setup
;
4004 else if (IS_GEN9_LP(dev_priv
))
4005 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4006 else if (INTEL_PCH_TYPE(dev_priv
) >= PCH_SPT
)
4007 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4009 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4014 * intel_irq_fini - deinitializes IRQ support
4015 * @i915: i915 device instance
4017 * This function deinitializes all the IRQ support.
4019 void intel_irq_fini(struct drm_i915_private
*i915
)
4023 for (i
= 0; i
< MAX_L3_SLICES
; ++i
)
4024 kfree(i915
->l3_parity
.remap_info
[i
]);
4027 static irq_handler_t
intel_irq_handler(struct drm_i915_private
*dev_priv
)
4029 if (HAS_GMCH(dev_priv
)) {
4030 if (IS_CHERRYVIEW(dev_priv
))
4031 return cherryview_irq_handler
;
4032 else if (IS_VALLEYVIEW(dev_priv
))
4033 return valleyview_irq_handler
;
4034 else if (IS_GEN(dev_priv
, 4))
4035 return i965_irq_handler
;
4036 else if (IS_GEN(dev_priv
, 3))
4037 return i915_irq_handler
;
4039 return i8xx_irq_handler
;
4041 if (HAS_MASTER_UNIT_IRQ(dev_priv
))
4042 return dg1_irq_handler
;
4043 if (INTEL_GEN(dev_priv
) >= 11)
4044 return gen11_irq_handler
;
4045 else if (INTEL_GEN(dev_priv
) >= 8)
4046 return gen8_irq_handler
;
4048 return ilk_irq_handler
;
4052 static void intel_irq_reset(struct drm_i915_private
*dev_priv
)
4054 if (HAS_GMCH(dev_priv
)) {
4055 if (IS_CHERRYVIEW(dev_priv
))
4056 cherryview_irq_reset(dev_priv
);
4057 else if (IS_VALLEYVIEW(dev_priv
))
4058 valleyview_irq_reset(dev_priv
);
4059 else if (IS_GEN(dev_priv
, 4))
4060 i965_irq_reset(dev_priv
);
4061 else if (IS_GEN(dev_priv
, 3))
4062 i915_irq_reset(dev_priv
);
4064 i8xx_irq_reset(dev_priv
);
4066 if (INTEL_GEN(dev_priv
) >= 11)
4067 gen11_irq_reset(dev_priv
);
4068 else if (INTEL_GEN(dev_priv
) >= 8)
4069 gen8_irq_reset(dev_priv
);
4071 ilk_irq_reset(dev_priv
);
4075 static void intel_irq_postinstall(struct drm_i915_private
*dev_priv
)
4077 if (HAS_GMCH(dev_priv
)) {
4078 if (IS_CHERRYVIEW(dev_priv
))
4079 cherryview_irq_postinstall(dev_priv
);
4080 else if (IS_VALLEYVIEW(dev_priv
))
4081 valleyview_irq_postinstall(dev_priv
);
4082 else if (IS_GEN(dev_priv
, 4))
4083 i965_irq_postinstall(dev_priv
);
4084 else if (IS_GEN(dev_priv
, 3))
4085 i915_irq_postinstall(dev_priv
);
4087 i8xx_irq_postinstall(dev_priv
);
4089 if (INTEL_GEN(dev_priv
) >= 11)
4090 gen11_irq_postinstall(dev_priv
);
4091 else if (INTEL_GEN(dev_priv
) >= 8)
4092 gen8_irq_postinstall(dev_priv
);
4094 ilk_irq_postinstall(dev_priv
);
4099 * intel_irq_install - enables the hardware interrupt
4100 * @dev_priv: i915 device instance
4102 * This function enables the hardware interrupt handling, but leaves the hotplug
4103 * handling still disabled. It is called after intel_irq_init().
4105 * In the driver load and resume code we need working interrupts in a few places
4106 * but don't want to deal with the hassle of concurrent probe and hotplug
4107 * workers. Hence the split into this two-stage approach.
4109 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4111 int irq
= dev_priv
->drm
.pdev
->irq
;
4115 * We enable some interrupt sources in our postinstall hooks, so mark
4116 * interrupts as enabled _before_ actually enabling them to avoid
4117 * special cases in our ordering checks.
4119 dev_priv
->runtime_pm
.irqs_enabled
= true;
4121 dev_priv
->drm
.irq_enabled
= true;
4123 intel_irq_reset(dev_priv
);
4125 ret
= request_irq(irq
, intel_irq_handler(dev_priv
),
4126 IRQF_SHARED
, DRIVER_NAME
, dev_priv
);
4128 dev_priv
->drm
.irq_enabled
= false;
4132 intel_irq_postinstall(dev_priv
);
4138 * intel_irq_uninstall - finilizes all irq handling
4139 * @dev_priv: i915 device instance
4141 * This stops interrupt and hotplug handling and unregisters and frees all
4142 * resources acquired in the init functions.
4144 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4146 int irq
= dev_priv
->drm
.pdev
->irq
;
4149 * FIXME we can get called twice during driver probe
4150 * error handling as well as during driver remove due to
4151 * intel_modeset_driver_remove() calling us out of sequence.
4152 * Would be nice if it didn't do that...
4154 if (!dev_priv
->drm
.irq_enabled
)
4157 dev_priv
->drm
.irq_enabled
= false;
4159 intel_irq_reset(dev_priv
);
4161 free_irq(irq
, dev_priv
);
4163 intel_hpd_cancel_work(dev_priv
);
4164 dev_priv
->runtime_pm
.irqs_enabled
= false;
4168 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4169 * @dev_priv: i915 device instance
4171 * This function is used to disable interrupts at runtime, both in the runtime
4172 * pm and the system suspend/resume code.
4174 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4176 intel_irq_reset(dev_priv
);
4177 dev_priv
->runtime_pm
.irqs_enabled
= false;
4178 intel_synchronize_irq(dev_priv
);
4182 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4183 * @dev_priv: i915 device instance
4185 * This function is used to enable interrupts at runtime, both in the runtime
4186 * pm and the system suspend/resume code.
4188 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4190 dev_priv
->runtime_pm
.irqs_enabled
= true;
4191 intel_irq_reset(dev_priv
);
4192 intel_irq_postinstall(dev_priv
);
4195 bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
4198 * We only use drm_irq_uninstall() at unload and VT switch, so
4199 * this is the only thing we need to check.
4201 return dev_priv
->runtime_pm
.irqs_enabled
;
4204 void intel_synchronize_irq(struct drm_i915_private
*i915
)
4206 synchronize_irq(i915
->drm
.pdev
->irq
);