2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private
*dev_priv
,
55 struct intel_cdclk_state
*cdclk_state
)
57 cdclk_state
->cdclk
= 133333;
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private
*dev_priv
,
61 struct intel_cdclk_state
*cdclk_state
)
63 cdclk_state
->cdclk
= 200000;
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private
*dev_priv
,
67 struct intel_cdclk_state
*cdclk_state
)
69 cdclk_state
->cdclk
= 266667;
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private
*dev_priv
,
73 struct intel_cdclk_state
*cdclk_state
)
75 cdclk_state
->cdclk
= 333333;
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private
*dev_priv
,
79 struct intel_cdclk_state
*cdclk_state
)
81 cdclk_state
->cdclk
= 400000;
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private
*dev_priv
,
85 struct intel_cdclk_state
*cdclk_state
)
87 cdclk_state
->cdclk
= 450000;
90 static void i85x_get_cdclk(struct drm_i915_private
*dev_priv
,
91 struct intel_cdclk_state
*cdclk_state
)
93 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
101 if (pdev
->revision
== 0x1) {
102 cdclk_state
->cdclk
= 133333;
106 pci_bus_read_config_word(pdev
->bus
,
107 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
112 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
113 case GC_CLOCK_133_200
:
114 case GC_CLOCK_133_200_2
:
115 case GC_CLOCK_100_200
:
116 cdclk_state
->cdclk
= 200000;
118 case GC_CLOCK_166_250
:
119 cdclk_state
->cdclk
= 250000;
121 case GC_CLOCK_100_133
:
122 cdclk_state
->cdclk
= 133333;
124 case GC_CLOCK_133_266
:
125 case GC_CLOCK_133_266_2
:
126 case GC_CLOCK_166_266
:
127 cdclk_state
->cdclk
= 266667;
132 static void i915gm_get_cdclk(struct drm_i915_private
*dev_priv
,
133 struct intel_cdclk_state
*cdclk_state
)
135 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
138 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
140 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
) {
141 cdclk_state
->cdclk
= 133333;
145 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ
:
147 cdclk_state
->cdclk
= 333333;
150 case GC_DISPLAY_CLOCK_190_200_MHZ
:
151 cdclk_state
->cdclk
= 190000;
156 static void i945gm_get_cdclk(struct drm_i915_private
*dev_priv
,
157 struct intel_cdclk_state
*cdclk_state
)
159 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
162 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
164 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
) {
165 cdclk_state
->cdclk
= 133333;
169 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ
:
171 cdclk_state
->cdclk
= 320000;
174 case GC_DISPLAY_CLOCK_190_200_MHZ
:
175 cdclk_state
->cdclk
= 200000;
180 static unsigned int intel_hpll_vco(struct drm_i915_private
*dev_priv
)
182 static const unsigned int blb_vco
[8] = {
189 static const unsigned int pnv_vco
[8] = {
196 static const unsigned int cl_vco
[8] = {
205 static const unsigned int elk_vco
[8] = {
211 static const unsigned int ctg_vco
[8] = {
219 const unsigned int *vco_table
;
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv
))
226 else if (IS_G45(dev_priv
))
228 else if (IS_I965GM(dev_priv
))
230 else if (IS_PINEVIEW(dev_priv
))
232 else if (IS_G33(dev_priv
))
237 tmp
= I915_READ(IS_MOBILE(dev_priv
) ? HPLLVCO_MOBILE
: HPLLVCO
);
239 vco
= vco_table
[tmp
& 0x7];
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
248 static void g33_get_cdclk(struct drm_i915_private
*dev_priv
,
249 struct intel_cdclk_state
*cdclk_state
)
251 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
252 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
253 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
254 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
255 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
256 const uint8_t *div_table
;
257 unsigned int cdclk_sel
;
260 cdclk_state
->vco
= intel_hpll_vco(dev_priv
);
262 pci_read_config_word(pdev
, GCFGC
, &tmp
);
264 cdclk_sel
= (tmp
>> 4) & 0x7;
266 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
269 switch (cdclk_state
->vco
) {
271 div_table
= div_3200
;
274 div_table
= div_4000
;
277 div_table
= div_4800
;
280 div_table
= div_5333
;
286 cdclk_state
->cdclk
= DIV_ROUND_CLOSEST(cdclk_state
->vco
,
287 div_table
[cdclk_sel
]);
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
292 cdclk_state
->vco
, tmp
);
293 cdclk_state
->cdclk
= 190476;
296 static void pnv_get_cdclk(struct drm_i915_private
*dev_priv
,
297 struct intel_cdclk_state
*cdclk_state
)
299 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
302 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
304 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
306 cdclk_state
->cdclk
= 266667;
308 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
309 cdclk_state
->cdclk
= 333333;
311 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
312 cdclk_state
->cdclk
= 444444;
314 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
315 cdclk_state
->cdclk
= 200000;
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
319 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
320 cdclk_state
->cdclk
= 133333;
322 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
323 cdclk_state
->cdclk
= 166667;
328 static void i965gm_get_cdclk(struct drm_i915_private
*dev_priv
,
329 struct intel_cdclk_state
*cdclk_state
)
331 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
332 static const uint8_t div_3200
[] = { 16, 10, 8 };
333 static const uint8_t div_4000
[] = { 20, 12, 10 };
334 static const uint8_t div_5333
[] = { 24, 16, 14 };
335 const uint8_t *div_table
;
336 unsigned int cdclk_sel
;
339 cdclk_state
->vco
= intel_hpll_vco(dev_priv
);
341 pci_read_config_word(pdev
, GCFGC
, &tmp
);
343 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
345 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
348 switch (cdclk_state
->vco
) {
350 div_table
= div_3200
;
353 div_table
= div_4000
;
356 div_table
= div_5333
;
362 cdclk_state
->cdclk
= DIV_ROUND_CLOSEST(cdclk_state
->vco
,
363 div_table
[cdclk_sel
]);
367 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
368 cdclk_state
->vco
, tmp
);
369 cdclk_state
->cdclk
= 200000;
372 static void gm45_get_cdclk(struct drm_i915_private
*dev_priv
,
373 struct intel_cdclk_state
*cdclk_state
)
375 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
376 unsigned int cdclk_sel
;
379 cdclk_state
->vco
= intel_hpll_vco(dev_priv
);
381 pci_read_config_word(pdev
, GCFGC
, &tmp
);
383 cdclk_sel
= (tmp
>> 12) & 0x1;
385 switch (cdclk_state
->vco
) {
389 cdclk_state
->cdclk
= cdclk_sel
? 333333 : 222222;
392 cdclk_state
->cdclk
= cdclk_sel
? 320000 : 228571;
395 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
396 cdclk_state
->vco
, tmp
);
397 cdclk_state
->cdclk
= 222222;
402 static void hsw_get_cdclk(struct drm_i915_private
*dev_priv
,
403 struct intel_cdclk_state
*cdclk_state
)
405 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
406 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
408 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
409 cdclk_state
->cdclk
= 800000;
410 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
411 cdclk_state
->cdclk
= 450000;
412 else if (freq
== LCPLL_CLK_FREQ_450
)
413 cdclk_state
->cdclk
= 450000;
414 else if (IS_HSW_ULT(dev_priv
))
415 cdclk_state
->cdclk
= 337500;
417 cdclk_state
->cdclk
= 540000;
420 static int vlv_calc_cdclk(struct drm_i915_private
*dev_priv
, int min_cdclk
)
422 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ?
426 * We seem to get an unstable or solid color picture at 200MHz.
427 * Not sure what's wrong. For now use 200MHz only when all pipes
430 if (IS_VALLEYVIEW(dev_priv
) && min_cdclk
> freq_320
)
432 else if (min_cdclk
> 266667)
434 else if (min_cdclk
> 0)
440 static void vlv_get_cdclk(struct drm_i915_private
*dev_priv
,
441 struct intel_cdclk_state
*cdclk_state
)
443 cdclk_state
->vco
= vlv_get_hpll_vco(dev_priv
);
444 cdclk_state
->cdclk
= vlv_get_cck_clock(dev_priv
, "cdclk",
445 CCK_DISPLAY_CLOCK_CONTROL
,
449 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
451 unsigned int credits
, default_credits
;
453 if (IS_CHERRYVIEW(dev_priv
))
454 default_credits
= PFI_CREDIT(12);
456 default_credits
= PFI_CREDIT(8);
458 if (dev_priv
->cdclk
.hw
.cdclk
>= dev_priv
->czclk_freq
) {
459 /* CHV suggested value is 31 or 63 */
460 if (IS_CHERRYVIEW(dev_priv
))
461 credits
= PFI_CREDIT_63
;
463 credits
= PFI_CREDIT(15);
465 credits
= default_credits
;
469 * WA - write default credits before re-programming
470 * FIXME: should we also set the resend bit here?
472 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
475 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
476 credits
| PFI_CREDIT_RESEND
);
479 * FIXME is this guaranteed to clear
480 * immediately or should we poll for it?
482 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
485 static void vlv_set_cdclk(struct drm_i915_private
*dev_priv
,
486 const struct intel_cdclk_state
*cdclk_state
)
488 int cdclk
= cdclk_state
->cdclk
;
491 /* There are cases where we can end up here with power domains
492 * off and a CDCLK frequency other than the minimum, like when
493 * issuing a modeset without actually changing any display after
494 * a system suspend. So grab the PIPE-A domain, which covers
495 * the HW blocks needed for the following programming.
497 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
499 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
501 else if (cdclk
== 266667)
506 mutex_lock(&dev_priv
->pcu_lock
);
507 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
508 val
&= ~DSPFREQGUAR_MASK
;
509 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
510 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
511 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
512 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
514 DRM_ERROR("timed out waiting for CDclk change\n");
516 mutex_unlock(&dev_priv
->pcu_lock
);
518 mutex_lock(&dev_priv
->sb_lock
);
520 if (cdclk
== 400000) {
523 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1,
526 /* adjust cdclk divider */
527 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
528 val
&= ~CCK_FREQUENCY_VALUES
;
530 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
532 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
533 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
535 DRM_ERROR("timed out waiting for CDclk change\n");
538 /* adjust self-refresh exit latency value */
539 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
543 * For high bandwidth configs, we set a higher latency in the bunit
544 * so that the core display fetch happens in time to avoid underruns.
547 val
|= 4500 / 250; /* 4.5 usec */
549 val
|= 3000 / 250; /* 3.0 usec */
550 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
552 mutex_unlock(&dev_priv
->sb_lock
);
554 intel_update_cdclk(dev_priv
);
556 vlv_program_pfi_credits(dev_priv
);
558 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
561 static void chv_set_cdclk(struct drm_i915_private
*dev_priv
,
562 const struct intel_cdclk_state
*cdclk_state
)
564 int cdclk
= cdclk_state
->cdclk
;
578 /* There are cases where we can end up here with power domains
579 * off and a CDCLK frequency other than the minimum, like when
580 * issuing a modeset without actually changing any display after
581 * a system suspend. So grab the PIPE-A domain, which covers
582 * the HW blocks needed for the following programming.
584 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
587 * Specs are full of misinformation, but testing on actual
588 * hardware has shown that we just need to write the desired
589 * CCK divider into the Punit register.
591 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
593 mutex_lock(&dev_priv
->pcu_lock
);
594 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
595 val
&= ~DSPFREQGUAR_MASK_CHV
;
596 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
597 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
598 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
599 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
601 DRM_ERROR("timed out waiting for CDclk change\n");
603 mutex_unlock(&dev_priv
->pcu_lock
);
605 intel_update_cdclk(dev_priv
);
607 vlv_program_pfi_credits(dev_priv
);
609 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
612 static int bdw_calc_cdclk(int min_cdclk
)
614 if (min_cdclk
> 540000)
616 else if (min_cdclk
> 450000)
618 else if (min_cdclk
> 337500)
624 static void bdw_get_cdclk(struct drm_i915_private
*dev_priv
,
625 struct intel_cdclk_state
*cdclk_state
)
627 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
628 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
630 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
631 cdclk_state
->cdclk
= 800000;
632 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
633 cdclk_state
->cdclk
= 450000;
634 else if (freq
== LCPLL_CLK_FREQ_450
)
635 cdclk_state
->cdclk
= 450000;
636 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
637 cdclk_state
->cdclk
= 540000;
638 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
639 cdclk_state
->cdclk
= 337500;
641 cdclk_state
->cdclk
= 675000;
644 static void bdw_set_cdclk(struct drm_i915_private
*dev_priv
,
645 const struct intel_cdclk_state
*cdclk_state
)
647 int cdclk
= cdclk_state
->cdclk
;
651 if (WARN((I915_READ(LCPLL_CTL
) &
652 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
653 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
654 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
655 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
656 "trying to change cdclk frequency with cdclk not enabled\n"))
659 mutex_lock(&dev_priv
->pcu_lock
);
660 ret
= sandybridge_pcode_write(dev_priv
,
661 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
662 mutex_unlock(&dev_priv
->pcu_lock
);
664 DRM_ERROR("failed to inform pcode about cdclk change\n");
668 val
= I915_READ(LCPLL_CTL
);
669 val
|= LCPLL_CD_SOURCE_FCLK
;
670 I915_WRITE(LCPLL_CTL
, val
);
673 * According to the spec, it should be enough to poll for this 1 us.
674 * However, extensive testing shows that this can take longer.
676 if (wait_for_us(I915_READ(LCPLL_CTL
) &
677 LCPLL_CD_SOURCE_FCLK_DONE
, 100))
678 DRM_ERROR("Switching to FCLK failed\n");
680 val
= I915_READ(LCPLL_CTL
);
681 val
&= ~LCPLL_CLK_FREQ_MASK
;
685 val
|= LCPLL_CLK_FREQ_450
;
689 val
|= LCPLL_CLK_FREQ_54O_BDW
;
693 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
697 val
|= LCPLL_CLK_FREQ_675_BDW
;
701 WARN(1, "invalid cdclk frequency\n");
705 I915_WRITE(LCPLL_CTL
, val
);
707 val
= I915_READ(LCPLL_CTL
);
708 val
&= ~LCPLL_CD_SOURCE_FCLK
;
709 I915_WRITE(LCPLL_CTL
, val
);
711 if (wait_for_us((I915_READ(LCPLL_CTL
) &
712 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
713 DRM_ERROR("Switching back to LCPLL failed\n");
715 mutex_lock(&dev_priv
->pcu_lock
);
716 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
717 mutex_unlock(&dev_priv
->pcu_lock
);
719 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
721 intel_update_cdclk(dev_priv
);
723 WARN(cdclk
!= dev_priv
->cdclk
.hw
.cdclk
,
724 "cdclk requested %d kHz but got %d kHz\n",
725 cdclk
, dev_priv
->cdclk
.hw
.cdclk
);
728 static int skl_calc_cdclk(int min_cdclk
, int vco
)
730 if (vco
== 8640000) {
731 if (min_cdclk
> 540000)
733 else if (min_cdclk
> 432000)
735 else if (min_cdclk
> 308571)
740 if (min_cdclk
> 540000)
742 else if (min_cdclk
> 450000)
744 else if (min_cdclk
> 337500)
751 static void skl_dpll0_update(struct drm_i915_private
*dev_priv
,
752 struct intel_cdclk_state
*cdclk_state
)
756 cdclk_state
->ref
= 24000;
757 cdclk_state
->vco
= 0;
759 val
= I915_READ(LCPLL1_CTL
);
760 if ((val
& LCPLL_PLL_ENABLE
) == 0)
763 if (WARN_ON((val
& LCPLL_PLL_LOCK
) == 0))
766 val
= I915_READ(DPLL_CTRL1
);
768 if (WARN_ON((val
& (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) |
769 DPLL_CTRL1_SSC(SKL_DPLL0
) |
770 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
))) !=
771 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
)))
774 switch (val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) {
775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, SKL_DPLL0
):
776 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, SKL_DPLL0
):
777 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, SKL_DPLL0
):
778 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, SKL_DPLL0
):
779 cdclk_state
->vco
= 8100000;
781 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, SKL_DPLL0
):
782 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, SKL_DPLL0
):
783 cdclk_state
->vco
= 8640000;
786 MISSING_CASE(val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
791 static void skl_get_cdclk(struct drm_i915_private
*dev_priv
,
792 struct intel_cdclk_state
*cdclk_state
)
796 skl_dpll0_update(dev_priv
, cdclk_state
);
798 cdclk_state
->cdclk
= cdclk_state
->ref
;
800 if (cdclk_state
->vco
== 0)
803 cdctl
= I915_READ(CDCLK_CTL
);
805 if (cdclk_state
->vco
== 8640000) {
806 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
807 case CDCLK_FREQ_450_432
:
808 cdclk_state
->cdclk
= 432000;
810 case CDCLK_FREQ_337_308
:
811 cdclk_state
->cdclk
= 308571;
814 cdclk_state
->cdclk
= 540000;
816 case CDCLK_FREQ_675_617
:
817 cdclk_state
->cdclk
= 617143;
820 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
824 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
825 case CDCLK_FREQ_450_432
:
826 cdclk_state
->cdclk
= 450000;
828 case CDCLK_FREQ_337_308
:
829 cdclk_state
->cdclk
= 337500;
832 cdclk_state
->cdclk
= 540000;
834 case CDCLK_FREQ_675_617
:
835 cdclk_state
->cdclk
= 675000;
838 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
844 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
845 static int skl_cdclk_decimal(int cdclk
)
847 return DIV_ROUND_CLOSEST(cdclk
- 1000, 500);
850 static void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
,
853 bool changed
= dev_priv
->skl_preferred_vco_freq
!= vco
;
855 dev_priv
->skl_preferred_vco_freq
= vco
;
858 intel_update_max_cdclk(dev_priv
);
861 static void skl_dpll0_enable(struct drm_i915_private
*dev_priv
, int vco
)
865 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
868 * We always enable DPLL0 with the lowest link rate possible, but still
869 * taking into account the VCO required to operate the eDP panel at the
870 * desired frequency. The usual DP link rates operate with a VCO of
871 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
872 * The modeset code is responsible for the selection of the exact link
873 * rate later on, with the constraint of choosing a frequency that
876 val
= I915_READ(DPLL_CTRL1
);
878 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
879 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
880 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
882 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
885 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
888 I915_WRITE(DPLL_CTRL1
, val
);
889 POSTING_READ(DPLL_CTRL1
);
891 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
893 if (intel_wait_for_register(dev_priv
,
894 LCPLL1_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
896 DRM_ERROR("DPLL0 not locked\n");
898 dev_priv
->cdclk
.hw
.vco
= vco
;
900 /* We'll want to keep using the current vco from now on. */
901 skl_set_preferred_cdclk_vco(dev_priv
, vco
);
904 static void skl_dpll0_disable(struct drm_i915_private
*dev_priv
)
906 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
907 if (intel_wait_for_register(dev_priv
,
908 LCPLL1_CTL
, LCPLL_PLL_LOCK
, 0,
910 DRM_ERROR("Couldn't disable DPLL0\n");
912 dev_priv
->cdclk
.hw
.vco
= 0;
915 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
,
916 const struct intel_cdclk_state
*cdclk_state
)
918 int cdclk
= cdclk_state
->cdclk
;
919 int vco
= cdclk_state
->vco
;
920 u32 freq_select
, pcu_ack
, cdclk_ctl
;
923 WARN_ON((cdclk
== 24000) != (vco
== 0));
925 mutex_lock(&dev_priv
->pcu_lock
);
926 ret
= skl_pcode_request(dev_priv
, SKL_PCODE_CDCLK_CONTROL
,
927 SKL_CDCLK_PREPARE_FOR_CHANGE
,
928 SKL_CDCLK_READY_FOR_CHANGE
,
929 SKL_CDCLK_READY_FOR_CHANGE
, 3);
930 mutex_unlock(&dev_priv
->pcu_lock
);
932 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
937 /* Choose frequency for this cdclk */
941 freq_select
= CDCLK_FREQ_450_432
;
945 freq_select
= CDCLK_FREQ_540
;
951 freq_select
= CDCLK_FREQ_337_308
;
956 freq_select
= CDCLK_FREQ_675_617
;
961 if (dev_priv
->cdclk
.hw
.vco
!= 0 &&
962 dev_priv
->cdclk
.hw
.vco
!= vco
)
963 skl_dpll0_disable(dev_priv
);
965 cdclk_ctl
= I915_READ(CDCLK_CTL
);
967 if (dev_priv
->cdclk
.hw
.vco
!= vco
) {
968 /* Wa Display #1183: skl,kbl,cfl */
969 cdclk_ctl
&= ~(CDCLK_FREQ_SEL_MASK
| CDCLK_FREQ_DECIMAL_MASK
);
970 cdclk_ctl
|= freq_select
| skl_cdclk_decimal(cdclk
);
971 I915_WRITE(CDCLK_CTL
, cdclk_ctl
);
974 /* Wa Display #1183: skl,kbl,cfl */
975 cdclk_ctl
|= CDCLK_DIVMUX_CD_OVERRIDE
;
976 I915_WRITE(CDCLK_CTL
, cdclk_ctl
);
977 POSTING_READ(CDCLK_CTL
);
979 if (dev_priv
->cdclk
.hw
.vco
!= vco
)
980 skl_dpll0_enable(dev_priv
, vco
);
982 /* Wa Display #1183: skl,kbl,cfl */
983 cdclk_ctl
&= ~(CDCLK_FREQ_SEL_MASK
| CDCLK_FREQ_DECIMAL_MASK
);
984 I915_WRITE(CDCLK_CTL
, cdclk_ctl
);
986 cdclk_ctl
|= freq_select
| skl_cdclk_decimal(cdclk
);
987 I915_WRITE(CDCLK_CTL
, cdclk_ctl
);
989 /* Wa Display #1183: skl,kbl,cfl */
990 cdclk_ctl
&= ~CDCLK_DIVMUX_CD_OVERRIDE
;
991 I915_WRITE(CDCLK_CTL
, cdclk_ctl
);
992 POSTING_READ(CDCLK_CTL
);
994 /* inform PCU of the change */
995 mutex_lock(&dev_priv
->pcu_lock
);
996 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
997 mutex_unlock(&dev_priv
->pcu_lock
);
999 intel_update_cdclk(dev_priv
);
1002 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
1004 uint32_t cdctl
, expected
;
1007 * check if the pre-os initialized the display
1008 * There is SWF18 scratchpad register defined which is set by the
1009 * pre-os which can be used by the OS drivers to check the status
1011 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1014 intel_update_cdclk(dev_priv
);
1015 /* Is PLL enabled and locked ? */
1016 if (dev_priv
->cdclk
.hw
.vco
== 0 ||
1017 dev_priv
->cdclk
.hw
.cdclk
== dev_priv
->cdclk
.hw
.ref
)
1020 /* DPLL okay; verify the cdclock
1022 * Noticed in some instances that the freq selection is correct but
1023 * decimal part is programmed wrong from BIOS where pre-os does not
1024 * enable display. Verify the same as well.
1026 cdctl
= I915_READ(CDCLK_CTL
);
1027 expected
= (cdctl
& CDCLK_FREQ_SEL_MASK
) |
1028 skl_cdclk_decimal(dev_priv
->cdclk
.hw
.cdclk
);
1029 if (cdctl
== expected
)
1030 /* All well; nothing to sanitize */
1034 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1036 /* force cdclk programming */
1037 dev_priv
->cdclk
.hw
.cdclk
= 0;
1038 /* force full PLL disable + enable */
1039 dev_priv
->cdclk
.hw
.vco
= -1;
1043 * skl_init_cdclk - Initialize CDCLK on SKL
1044 * @dev_priv: i915 device
1046 * Initialize CDCLK for SKL and derivatives. This is generally
1047 * done only during the display core initialization sequence,
1048 * after which the DMC will take care of turning CDCLK off/on
1051 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
1053 struct intel_cdclk_state cdclk_state
;
1055 skl_sanitize_cdclk(dev_priv
);
1057 if (dev_priv
->cdclk
.hw
.cdclk
!= 0 &&
1058 dev_priv
->cdclk
.hw
.vco
!= 0) {
1060 * Use the current vco as our initial
1061 * guess as to what the preferred vco is.
1063 if (dev_priv
->skl_preferred_vco_freq
== 0)
1064 skl_set_preferred_cdclk_vco(dev_priv
,
1065 dev_priv
->cdclk
.hw
.vco
);
1069 cdclk_state
= dev_priv
->cdclk
.hw
;
1071 cdclk_state
.vco
= dev_priv
->skl_preferred_vco_freq
;
1072 if (cdclk_state
.vco
== 0)
1073 cdclk_state
.vco
= 8100000;
1074 cdclk_state
.cdclk
= skl_calc_cdclk(0, cdclk_state
.vco
);
1076 skl_set_cdclk(dev_priv
, &cdclk_state
);
1080 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1081 * @dev_priv: i915 device
1083 * Uninitialize CDCLK for SKL and derivatives. This is done only
1084 * during the display core uninitialization sequence.
1086 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
1088 struct intel_cdclk_state cdclk_state
= dev_priv
->cdclk
.hw
;
1090 cdclk_state
.cdclk
= cdclk_state
.ref
;
1091 cdclk_state
.vco
= 0;
1093 skl_set_cdclk(dev_priv
, &cdclk_state
);
1096 static int bxt_calc_cdclk(int min_cdclk
)
1098 if (min_cdclk
> 576000)
1100 else if (min_cdclk
> 384000)
1102 else if (min_cdclk
> 288000)
1104 else if (min_cdclk
> 144000)
1110 static int glk_calc_cdclk(int min_cdclk
)
1112 if (min_cdclk
> 158400)
1114 else if (min_cdclk
> 79200)
1120 static int bxt_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
1124 if (cdclk
== dev_priv
->cdclk
.hw
.ref
)
1129 MISSING_CASE(cdclk
);
1141 return dev_priv
->cdclk
.hw
.ref
* ratio
;
1144 static int glk_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
1148 if (cdclk
== dev_priv
->cdclk
.hw
.ref
)
1153 MISSING_CASE(cdclk
);
1161 return dev_priv
->cdclk
.hw
.ref
* ratio
;
1164 static void bxt_de_pll_update(struct drm_i915_private
*dev_priv
,
1165 struct intel_cdclk_state
*cdclk_state
)
1169 cdclk_state
->ref
= 19200;
1170 cdclk_state
->vco
= 0;
1172 val
= I915_READ(BXT_DE_PLL_ENABLE
);
1173 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
1176 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
1179 val
= I915_READ(BXT_DE_PLL_CTL
);
1180 cdclk_state
->vco
= (val
& BXT_DE_PLL_RATIO_MASK
) * cdclk_state
->ref
;
1183 static void bxt_get_cdclk(struct drm_i915_private
*dev_priv
,
1184 struct intel_cdclk_state
*cdclk_state
)
1189 bxt_de_pll_update(dev_priv
, cdclk_state
);
1191 cdclk_state
->cdclk
= cdclk_state
->ref
;
1193 if (cdclk_state
->vco
== 0)
1196 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
1199 case BXT_CDCLK_CD2X_DIV_SEL_1
:
1202 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
1203 WARN(IS_GEMINILAKE(dev_priv
), "Unsupported divider\n");
1206 case BXT_CDCLK_CD2X_DIV_SEL_2
:
1209 case BXT_CDCLK_CD2X_DIV_SEL_4
:
1213 MISSING_CASE(divider
);
1217 cdclk_state
->cdclk
= DIV_ROUND_CLOSEST(cdclk_state
->vco
, div
);
1220 static void bxt_de_pll_disable(struct drm_i915_private
*dev_priv
)
1222 I915_WRITE(BXT_DE_PLL_ENABLE
, 0);
1225 if (intel_wait_for_register(dev_priv
,
1226 BXT_DE_PLL_ENABLE
, BXT_DE_PLL_LOCK
, 0,
1228 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1230 dev_priv
->cdclk
.hw
.vco
= 0;
1233 static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
1235 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk
.hw
.ref
);
1238 val
= I915_READ(BXT_DE_PLL_CTL
);
1239 val
&= ~BXT_DE_PLL_RATIO_MASK
;
1240 val
|= BXT_DE_PLL_RATIO(ratio
);
1241 I915_WRITE(BXT_DE_PLL_CTL
, val
);
1243 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
1246 if (intel_wait_for_register(dev_priv
,
1251 DRM_ERROR("timeout waiting for DE PLL lock\n");
1253 dev_priv
->cdclk
.hw
.vco
= vco
;
1256 static void bxt_set_cdclk(struct drm_i915_private
*dev_priv
,
1257 const struct intel_cdclk_state
*cdclk_state
)
1259 int cdclk
= cdclk_state
->cdclk
;
1260 int vco
= cdclk_state
->vco
;
1264 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1265 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
1267 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
1270 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
1273 WARN(IS_GEMINILAKE(dev_priv
), "Unsupported divider\n");
1274 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
1277 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
1280 WARN_ON(cdclk
!= dev_priv
->cdclk
.hw
.ref
);
1283 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
1287 mutex_lock(&dev_priv
->pcu_lock
);
1289 * Inform power controller of upcoming frequency change. BSpec
1290 * requires us to wait up to 150usec, but that leads to timeouts;
1291 * the 2ms used here is based on experiment.
1293 ret
= sandybridge_pcode_write_timeout(dev_priv
,
1294 HSW_PCODE_DE_WRITE_FREQ_REQ
,
1296 mutex_unlock(&dev_priv
->pcu_lock
);
1299 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1304 if (dev_priv
->cdclk
.hw
.vco
!= 0 &&
1305 dev_priv
->cdclk
.hw
.vco
!= vco
)
1306 bxt_de_pll_disable(dev_priv
);
1308 if (dev_priv
->cdclk
.hw
.vco
!= vco
)
1309 bxt_de_pll_enable(dev_priv
, vco
);
1311 val
= divider
| skl_cdclk_decimal(cdclk
);
1313 * FIXME if only the cd2x divider needs changing, it could be done
1314 * without shutting off the pipe (if only one pipe is active).
1316 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
1318 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1321 if (cdclk
>= 500000)
1322 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
1323 I915_WRITE(CDCLK_CTL
, val
);
1325 mutex_lock(&dev_priv
->pcu_lock
);
1327 * The timeout isn't specified, the 2ms used here is based on
1329 * FIXME: Waiting for the request completion could be delayed until
1330 * the next PCODE request based on BSpec.
1332 ret
= sandybridge_pcode_write_timeout(dev_priv
,
1333 HSW_PCODE_DE_WRITE_FREQ_REQ
,
1334 DIV_ROUND_UP(cdclk
, 25000), 2000);
1335 mutex_unlock(&dev_priv
->pcu_lock
);
1338 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1343 intel_update_cdclk(dev_priv
);
1346 static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
1348 u32 cdctl
, expected
;
1350 intel_update_cdclk(dev_priv
);
1352 if (dev_priv
->cdclk
.hw
.vco
== 0 ||
1353 dev_priv
->cdclk
.hw
.cdclk
== dev_priv
->cdclk
.hw
.ref
)
1356 /* DPLL okay; verify the cdclock
1358 * Some BIOS versions leave an incorrect decimal frequency value and
1359 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1360 * so sanitize this register.
1362 cdctl
= I915_READ(CDCLK_CTL
);
1364 * Let's ignore the pipe field, since BIOS could have configured the
1365 * dividers both synching to an active pipe, or asynchronously
1368 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
1370 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
1371 skl_cdclk_decimal(dev_priv
->cdclk
.hw
.cdclk
);
1373 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1376 if (dev_priv
->cdclk
.hw
.cdclk
>= 500000)
1377 expected
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
1379 if (cdctl
== expected
)
1380 /* All well; nothing to sanitize */
1384 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1386 /* force cdclk programming */
1387 dev_priv
->cdclk
.hw
.cdclk
= 0;
1389 /* force full PLL disable + enable */
1390 dev_priv
->cdclk
.hw
.vco
= -1;
1394 * bxt_init_cdclk - Initialize CDCLK on BXT
1395 * @dev_priv: i915 device
1397 * Initialize CDCLK for BXT and derivatives. This is generally
1398 * done only during the display core initialization sequence,
1399 * after which the DMC will take care of turning CDCLK off/on
1402 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
)
1404 struct intel_cdclk_state cdclk_state
;
1406 bxt_sanitize_cdclk(dev_priv
);
1408 if (dev_priv
->cdclk
.hw
.cdclk
!= 0 &&
1409 dev_priv
->cdclk
.hw
.vco
!= 0)
1412 cdclk_state
= dev_priv
->cdclk
.hw
;
1416 * - The initial CDCLK needs to be read from VBT.
1417 * Need to make this change after VBT has changes for BXT.
1419 if (IS_GEMINILAKE(dev_priv
)) {
1420 cdclk_state
.cdclk
= glk_calc_cdclk(0);
1421 cdclk_state
.vco
= glk_de_pll_vco(dev_priv
, cdclk_state
.cdclk
);
1423 cdclk_state
.cdclk
= bxt_calc_cdclk(0);
1424 cdclk_state
.vco
= bxt_de_pll_vco(dev_priv
, cdclk_state
.cdclk
);
1427 bxt_set_cdclk(dev_priv
, &cdclk_state
);
1431 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1432 * @dev_priv: i915 device
1434 * Uninitialize CDCLK for BXT and derivatives. This is done only
1435 * during the display core uninitialization sequence.
1437 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
)
1439 struct intel_cdclk_state cdclk_state
= dev_priv
->cdclk
.hw
;
1441 cdclk_state
.cdclk
= cdclk_state
.ref
;
1442 cdclk_state
.vco
= 0;
1444 bxt_set_cdclk(dev_priv
, &cdclk_state
);
1447 static int cnl_calc_cdclk(int min_cdclk
)
1449 if (min_cdclk
> 336000)
1451 else if (min_cdclk
> 168000)
1457 static void cnl_cdclk_pll_update(struct drm_i915_private
*dev_priv
,
1458 struct intel_cdclk_state
*cdclk_state
)
1462 if (I915_READ(SKL_DSSM
) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz
)
1463 cdclk_state
->ref
= 24000;
1465 cdclk_state
->ref
= 19200;
1467 cdclk_state
->vco
= 0;
1469 val
= I915_READ(BXT_DE_PLL_ENABLE
);
1470 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
1473 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
1476 cdclk_state
->vco
= (val
& CNL_CDCLK_PLL_RATIO_MASK
) * cdclk_state
->ref
;
1479 static void cnl_get_cdclk(struct drm_i915_private
*dev_priv
,
1480 struct intel_cdclk_state
*cdclk_state
)
1485 cnl_cdclk_pll_update(dev_priv
, cdclk_state
);
1487 cdclk_state
->cdclk
= cdclk_state
->ref
;
1489 if (cdclk_state
->vco
== 0)
1492 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
1495 case BXT_CDCLK_CD2X_DIV_SEL_1
:
1498 case BXT_CDCLK_CD2X_DIV_SEL_2
:
1502 MISSING_CASE(divider
);
1506 cdclk_state
->cdclk
= DIV_ROUND_CLOSEST(cdclk_state
->vco
, div
);
1509 static void cnl_cdclk_pll_disable(struct drm_i915_private
*dev_priv
)
1513 val
= I915_READ(BXT_DE_PLL_ENABLE
);
1514 val
&= ~BXT_DE_PLL_PLL_ENABLE
;
1515 I915_WRITE(BXT_DE_PLL_ENABLE
, val
);
1518 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
) == 0, 1))
1519 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1521 dev_priv
->cdclk
.hw
.vco
= 0;
1524 static void cnl_cdclk_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
1526 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk
.hw
.ref
);
1529 val
= CNL_CDCLK_PLL_RATIO(ratio
);
1530 I915_WRITE(BXT_DE_PLL_ENABLE
, val
);
1532 val
|= BXT_DE_PLL_PLL_ENABLE
;
1533 I915_WRITE(BXT_DE_PLL_ENABLE
, val
);
1536 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
) != 0, 1))
1537 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1539 dev_priv
->cdclk
.hw
.vco
= vco
;
1542 static void cnl_set_cdclk(struct drm_i915_private
*dev_priv
,
1543 const struct intel_cdclk_state
*cdclk_state
)
1545 int cdclk
= cdclk_state
->cdclk
;
1546 int vco
= cdclk_state
->vco
;
1547 u32 val
, divider
, pcu_ack
;
1550 mutex_lock(&dev_priv
->pcu_lock
);
1551 ret
= skl_pcode_request(dev_priv
, SKL_PCODE_CDCLK_CONTROL
,
1552 SKL_CDCLK_PREPARE_FOR_CHANGE
,
1553 SKL_CDCLK_READY_FOR_CHANGE
,
1554 SKL_CDCLK_READY_FOR_CHANGE
, 3);
1555 mutex_unlock(&dev_priv
->pcu_lock
);
1557 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1562 /* cdclk = vco / 2 / div{1,2} */
1563 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
1565 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
1568 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
1571 WARN_ON(cdclk
!= dev_priv
->cdclk
.hw
.ref
);
1574 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
1591 if (dev_priv
->cdclk
.hw
.vco
!= 0 &&
1592 dev_priv
->cdclk
.hw
.vco
!= vco
)
1593 cnl_cdclk_pll_disable(dev_priv
);
1595 if (dev_priv
->cdclk
.hw
.vco
!= vco
)
1596 cnl_cdclk_pll_enable(dev_priv
, vco
);
1598 val
= divider
| skl_cdclk_decimal(cdclk
);
1600 * FIXME if only the cd2x divider needs changing, it could be done
1601 * without shutting off the pipe (if only one pipe is active).
1603 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
1604 I915_WRITE(CDCLK_CTL
, val
);
1606 /* inform PCU of the change */
1607 mutex_lock(&dev_priv
->pcu_lock
);
1608 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
1609 mutex_unlock(&dev_priv
->pcu_lock
);
1611 intel_update_cdclk(dev_priv
);
1614 static int cnl_cdclk_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
1618 if (cdclk
== dev_priv
->cdclk
.hw
.ref
)
1623 MISSING_CASE(cdclk
);
1626 ratio
= dev_priv
->cdclk
.hw
.ref
== 19200 ? 35 : 28;
1629 ratio
= dev_priv
->cdclk
.hw
.ref
== 19200 ? 55 : 44;
1633 return dev_priv
->cdclk
.hw
.ref
* ratio
;
1636 static void cnl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
1638 u32 cdctl
, expected
;
1640 intel_update_cdclk(dev_priv
);
1642 if (dev_priv
->cdclk
.hw
.vco
== 0 ||
1643 dev_priv
->cdclk
.hw
.cdclk
== dev_priv
->cdclk
.hw
.ref
)
1646 /* DPLL okay; verify the cdclock
1648 * Some BIOS versions leave an incorrect decimal frequency value and
1649 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1650 * so sanitize this register.
1652 cdctl
= I915_READ(CDCLK_CTL
);
1654 * Let's ignore the pipe field, since BIOS could have configured the
1655 * dividers both synching to an active pipe, or asynchronously
1658 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
1660 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
1661 skl_cdclk_decimal(dev_priv
->cdclk
.hw
.cdclk
);
1663 if (cdctl
== expected
)
1664 /* All well; nothing to sanitize */
1668 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1670 /* force cdclk programming */
1671 dev_priv
->cdclk
.hw
.cdclk
= 0;
1673 /* force full PLL disable + enable */
1674 dev_priv
->cdclk
.hw
.vco
= -1;
1678 * cnl_init_cdclk - Initialize CDCLK on CNL
1679 * @dev_priv: i915 device
1681 * Initialize CDCLK for CNL. This is generally
1682 * done only during the display core initialization sequence,
1683 * after which the DMC will take care of turning CDCLK off/on
1686 void cnl_init_cdclk(struct drm_i915_private
*dev_priv
)
1688 struct intel_cdclk_state cdclk_state
;
1690 cnl_sanitize_cdclk(dev_priv
);
1692 if (dev_priv
->cdclk
.hw
.cdclk
!= 0 &&
1693 dev_priv
->cdclk
.hw
.vco
!= 0)
1696 cdclk_state
= dev_priv
->cdclk
.hw
;
1698 cdclk_state
.cdclk
= cnl_calc_cdclk(0);
1699 cdclk_state
.vco
= cnl_cdclk_pll_vco(dev_priv
, cdclk_state
.cdclk
);
1701 cnl_set_cdclk(dev_priv
, &cdclk_state
);
1705 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1706 * @dev_priv: i915 device
1708 * Uninitialize CDCLK for CNL. This is done only
1709 * during the display core uninitialization sequence.
1711 void cnl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
1713 struct intel_cdclk_state cdclk_state
= dev_priv
->cdclk
.hw
;
1715 cdclk_state
.cdclk
= cdclk_state
.ref
;
1716 cdclk_state
.vco
= 0;
1718 cnl_set_cdclk(dev_priv
, &cdclk_state
);
1722 * intel_cdclk_state_compare - Determine if two CDCLK states differ
1723 * @a: first CDCLK state
1724 * @b: second CDCLK state
1727 * True if the CDCLK states are identical, false if they differ.
1729 bool intel_cdclk_state_compare(const struct intel_cdclk_state
*a
,
1730 const struct intel_cdclk_state
*b
)
1732 return memcmp(a
, b
, sizeof(*a
)) == 0;
1736 * intel_set_cdclk - Push the CDCLK state to the hardware
1737 * @dev_priv: i915 device
1738 * @cdclk_state: new CDCLK state
1740 * Program the hardware based on the passed in CDCLK state,
1743 void intel_set_cdclk(struct drm_i915_private
*dev_priv
,
1744 const struct intel_cdclk_state
*cdclk_state
)
1746 if (intel_cdclk_state_compare(&dev_priv
->cdclk
.hw
, cdclk_state
))
1749 if (WARN_ON_ONCE(!dev_priv
->display
.set_cdclk
))
1752 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1753 cdclk_state
->cdclk
, cdclk_state
->vco
,
1756 dev_priv
->display
.set_cdclk(dev_priv
, cdclk_state
);
1759 static int intel_pixel_rate_to_cdclk(struct drm_i915_private
*dev_priv
,
1762 if (INTEL_GEN(dev_priv
) >= 10)
1764 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1765 * once DDI clock voltage requirements are
1766 * handled correctly.
1769 else if (IS_GEMINILAKE(dev_priv
))
1771 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1772 * as a temporary workaround. Use a higher cdclk instead. (Note that
1773 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1776 return DIV_ROUND_UP(pixel_rate
* 100, 2 * 99);
1777 else if (IS_GEN9(dev_priv
) ||
1778 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
1780 else if (IS_CHERRYVIEW(dev_priv
))
1781 return DIV_ROUND_UP(pixel_rate
* 100, 95);
1783 return DIV_ROUND_UP(pixel_rate
* 100, 90);
1786 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state
*crtc_state
)
1788 struct drm_i915_private
*dev_priv
=
1789 to_i915(crtc_state
->base
.crtc
->dev
);
1792 if (!crtc_state
->base
.enable
)
1795 min_cdclk
= intel_pixel_rate_to_cdclk(dev_priv
, crtc_state
->pixel_rate
);
1797 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1798 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
1799 min_cdclk
= DIV_ROUND_UP(min_cdclk
* 100, 95);
1801 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1802 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1803 * there may be audio corruption or screen corruption." This cdclk
1804 * restriction for GLK is 316.8 MHz.
1806 if (intel_crtc_has_dp_encoder(crtc_state
) &&
1807 crtc_state
->has_audio
&&
1808 crtc_state
->port_clock
>= 540000 &&
1809 crtc_state
->lane_count
== 4) {
1810 if (IS_CANNONLAKE(dev_priv
) || IS_GEMINILAKE(dev_priv
)) {
1811 /* Display WA #1145: glk,cnl */
1812 min_cdclk
= max(316800, min_cdclk
);
1813 } else if (IS_GEN9(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1814 /* Display WA #1144: skl,bxt */
1815 min_cdclk
= max(432000, min_cdclk
);
1820 * According to BSpec, "The CD clock frequency must be at least twice
1821 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1823 * FIXME: Check the actual, not default, BCLK being used.
1825 * FIXME: This does not depend on ->has_audio because the higher CDCLK
1826 * is required for audio probe, also when there are no audio capable
1827 * displays connected at probe time. This leads to unnecessarily high
1828 * CDCLK when audio is not required.
1830 * FIXME: This limit is only applied when there are displays connected
1831 * at probe time. If we probe without displays, we'll still end up using
1832 * the platform minimum CDCLK, failing audio probe.
1834 if (INTEL_GEN(dev_priv
) >= 9)
1835 min_cdclk
= max(2 * 96000, min_cdclk
);
1837 if (min_cdclk
> dev_priv
->max_cdclk_freq
) {
1838 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1839 min_cdclk
, dev_priv
->max_cdclk_freq
);
1846 static int intel_compute_min_cdclk(struct drm_atomic_state
*state
)
1848 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
1849 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
1850 struct intel_crtc
*crtc
;
1851 struct intel_crtc_state
*crtc_state
;
1855 memcpy(intel_state
->min_cdclk
, dev_priv
->min_cdclk
,
1856 sizeof(intel_state
->min_cdclk
));
1858 for_each_new_intel_crtc_in_state(intel_state
, crtc
, crtc_state
, i
) {
1859 min_cdclk
= intel_crtc_compute_min_cdclk(crtc_state
);
1863 intel_state
->min_cdclk
[i
] = min_cdclk
;
1867 for_each_pipe(dev_priv
, pipe
)
1868 min_cdclk
= max(intel_state
->min_cdclk
[pipe
], min_cdclk
);
1873 static int vlv_modeset_calc_cdclk(struct drm_atomic_state
*state
)
1875 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
1876 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
1877 int min_cdclk
, cdclk
;
1879 min_cdclk
= intel_compute_min_cdclk(state
);
1883 cdclk
= vlv_calc_cdclk(dev_priv
, min_cdclk
);
1885 intel_state
->cdclk
.logical
.cdclk
= cdclk
;
1887 if (!intel_state
->active_crtcs
) {
1888 cdclk
= vlv_calc_cdclk(dev_priv
, 0);
1890 intel_state
->cdclk
.actual
.cdclk
= cdclk
;
1892 intel_state
->cdclk
.actual
=
1893 intel_state
->cdclk
.logical
;
1899 static int bdw_modeset_calc_cdclk(struct drm_atomic_state
*state
)
1901 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
1902 int min_cdclk
, cdclk
;
1904 min_cdclk
= intel_compute_min_cdclk(state
);
1909 * FIXME should also account for plane ratio
1910 * once 64bpp pixel formats are supported.
1912 cdclk
= bdw_calc_cdclk(min_cdclk
);
1914 intel_state
->cdclk
.logical
.cdclk
= cdclk
;
1916 if (!intel_state
->active_crtcs
) {
1917 cdclk
= bdw_calc_cdclk(0);
1919 intel_state
->cdclk
.actual
.cdclk
= cdclk
;
1921 intel_state
->cdclk
.actual
=
1922 intel_state
->cdclk
.logical
;
1928 static int skl_dpll0_vco(struct intel_atomic_state
*intel_state
)
1930 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
1931 struct intel_crtc
*crtc
;
1932 struct intel_crtc_state
*crtc_state
;
1935 vco
= intel_state
->cdclk
.logical
.vco
;
1937 vco
= dev_priv
->skl_preferred_vco_freq
;
1939 for_each_new_intel_crtc_in_state(intel_state
, crtc
, crtc_state
, i
) {
1940 if (!crtc_state
->base
.enable
)
1943 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_EDP
))
1947 * DPLL0 VCO may need to be adjusted to get the correct
1948 * clock for eDP. This will affect cdclk as well.
1950 switch (crtc_state
->port_clock
/ 2) {
1964 static int skl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
1966 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
1967 int min_cdclk
, cdclk
, vco
;
1969 min_cdclk
= intel_compute_min_cdclk(state
);
1973 vco
= skl_dpll0_vco(intel_state
);
1976 * FIXME should also account for plane ratio
1977 * once 64bpp pixel formats are supported.
1979 cdclk
= skl_calc_cdclk(min_cdclk
, vco
);
1981 intel_state
->cdclk
.logical
.vco
= vco
;
1982 intel_state
->cdclk
.logical
.cdclk
= cdclk
;
1984 if (!intel_state
->active_crtcs
) {
1985 cdclk
= skl_calc_cdclk(0, vco
);
1987 intel_state
->cdclk
.actual
.vco
= vco
;
1988 intel_state
->cdclk
.actual
.cdclk
= cdclk
;
1990 intel_state
->cdclk
.actual
=
1991 intel_state
->cdclk
.logical
;
1997 static int bxt_modeset_calc_cdclk(struct drm_atomic_state
*state
)
1999 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
2000 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
2001 int min_cdclk
, cdclk
, vco
;
2003 min_cdclk
= intel_compute_min_cdclk(state
);
2007 if (IS_GEMINILAKE(dev_priv
)) {
2008 cdclk
= glk_calc_cdclk(min_cdclk
);
2009 vco
= glk_de_pll_vco(dev_priv
, cdclk
);
2011 cdclk
= bxt_calc_cdclk(min_cdclk
);
2012 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
2015 intel_state
->cdclk
.logical
.vco
= vco
;
2016 intel_state
->cdclk
.logical
.cdclk
= cdclk
;
2018 if (!intel_state
->active_crtcs
) {
2019 if (IS_GEMINILAKE(dev_priv
)) {
2020 cdclk
= glk_calc_cdclk(0);
2021 vco
= glk_de_pll_vco(dev_priv
, cdclk
);
2023 cdclk
= bxt_calc_cdclk(0);
2024 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
2027 intel_state
->cdclk
.actual
.vco
= vco
;
2028 intel_state
->cdclk
.actual
.cdclk
= cdclk
;
2030 intel_state
->cdclk
.actual
=
2031 intel_state
->cdclk
.logical
;
2037 static int cnl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
2039 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
2040 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
2041 int min_cdclk
, cdclk
, vco
;
2043 min_cdclk
= intel_compute_min_cdclk(state
);
2047 cdclk
= cnl_calc_cdclk(min_cdclk
);
2048 vco
= cnl_cdclk_pll_vco(dev_priv
, cdclk
);
2050 intel_state
->cdclk
.logical
.vco
= vco
;
2051 intel_state
->cdclk
.logical
.cdclk
= cdclk
;
2053 if (!intel_state
->active_crtcs
) {
2054 cdclk
= cnl_calc_cdclk(0);
2055 vco
= cnl_cdclk_pll_vco(dev_priv
, cdclk
);
2057 intel_state
->cdclk
.actual
.vco
= vco
;
2058 intel_state
->cdclk
.actual
.cdclk
= cdclk
;
2060 intel_state
->cdclk
.actual
=
2061 intel_state
->cdclk
.logical
;
2067 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
2069 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
2071 if (INTEL_GEN(dev_priv
) >= 10)
2073 * FIXME: Allow '2 * max_cdclk_freq'
2074 * once DDI clock voltage requirements are
2075 * handled correctly.
2077 return max_cdclk_freq
;
2078 else if (IS_GEMINILAKE(dev_priv
))
2080 * FIXME: Limiting to 99% as a temporary workaround. See
2081 * intel_min_cdclk() for details.
2083 return 2 * max_cdclk_freq
* 99 / 100;
2084 else if (IS_GEN9(dev_priv
) ||
2085 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
2086 return max_cdclk_freq
;
2087 else if (IS_CHERRYVIEW(dev_priv
))
2088 return max_cdclk_freq
*95/100;
2089 else if (INTEL_INFO(dev_priv
)->gen
< 4)
2090 return 2*max_cdclk_freq
*90/100;
2092 return max_cdclk_freq
*90/100;
2096 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2097 * @dev_priv: i915 device
2099 * Determine the maximum CDCLK frequency the platform supports, and also
2100 * derive the maximum dot clock frequency the maximum CDCLK frequency
2103 void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
)
2105 if (IS_CANNONLAKE(dev_priv
)) {
2106 dev_priv
->max_cdclk_freq
= 528000;
2107 } else if (IS_GEN9_BC(dev_priv
)) {
2108 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
2111 vco
= dev_priv
->skl_preferred_vco_freq
;
2112 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
2115 * Use the lower (vco 8640) cdclk values as a
2116 * first guess. skl_calc_cdclk() will correct it
2117 * if the preferred vco is 8100 instead.
2119 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
2121 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
2123 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
2128 dev_priv
->max_cdclk_freq
= skl_calc_cdclk(max_cdclk
, vco
);
2129 } else if (IS_GEMINILAKE(dev_priv
)) {
2130 dev_priv
->max_cdclk_freq
= 316800;
2131 } else if (IS_BROXTON(dev_priv
)) {
2132 dev_priv
->max_cdclk_freq
= 624000;
2133 } else if (IS_BROADWELL(dev_priv
)) {
2135 * FIXME with extra cooling we can allow
2136 * 540 MHz for ULX and 675 Mhz for ULT.
2137 * How can we know if extra cooling is
2138 * available? PCI ID, VTB, something else?
2140 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
2141 dev_priv
->max_cdclk_freq
= 450000;
2142 else if (IS_BDW_ULX(dev_priv
))
2143 dev_priv
->max_cdclk_freq
= 450000;
2144 else if (IS_BDW_ULT(dev_priv
))
2145 dev_priv
->max_cdclk_freq
= 540000;
2147 dev_priv
->max_cdclk_freq
= 675000;
2148 } else if (IS_CHERRYVIEW(dev_priv
)) {
2149 dev_priv
->max_cdclk_freq
= 320000;
2150 } else if (IS_VALLEYVIEW(dev_priv
)) {
2151 dev_priv
->max_cdclk_freq
= 400000;
2153 /* otherwise assume cdclk is fixed */
2154 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk
.hw
.cdclk
;
2157 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
2159 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2160 dev_priv
->max_cdclk_freq
);
2162 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2163 dev_priv
->max_dotclk_freq
);
2167 * intel_update_cdclk - Determine the current CDCLK frequency
2168 * @dev_priv: i915 device
2170 * Determine the current CDCLK frequency.
2172 void intel_update_cdclk(struct drm_i915_private
*dev_priv
)
2174 dev_priv
->display
.get_cdclk(dev_priv
, &dev_priv
->cdclk
.hw
);
2176 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2177 dev_priv
->cdclk
.hw
.cdclk
, dev_priv
->cdclk
.hw
.vco
,
2178 dev_priv
->cdclk
.hw
.ref
);
2181 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2182 * Programmng [sic] note: bit[9:2] should be programmed to the number
2183 * of cdclk that generates 4MHz reference clock freq which is used to
2184 * generate GMBus clock. This will vary with the cdclk freq.
2186 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2187 I915_WRITE(GMBUSFREQ_VLV
,
2188 DIV_ROUND_UP(dev_priv
->cdclk
.hw
.cdclk
, 1000));
2191 static int cnp_rawclk(struct drm_i915_private
*dev_priv
)
2194 int divider
, fraction
;
2196 if (I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_RAW_FREQUENCY
) {
2206 rawclk
= CNP_RAWCLK_DIV((divider
/ 1000) - 1);
2208 rawclk
|= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2211 I915_WRITE(PCH_RAWCLK_FREQ
, rawclk
);
2212 return divider
+ fraction
;
2215 static int pch_rawclk(struct drm_i915_private
*dev_priv
)
2217 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
2220 static int vlv_hrawclk(struct drm_i915_private
*dev_priv
)
2222 /* RAWCLK_FREQ_VLV register updated from power well code */
2223 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
2224 CCK_DISPLAY_REF_CLOCK_CONTROL
);
2227 static int g4x_hrawclk(struct drm_i915_private
*dev_priv
)
2231 /* hrawclock is 1/4 the FSB frequency */
2232 clkcfg
= I915_READ(CLKCFG
);
2233 switch (clkcfg
& CLKCFG_FSB_MASK
) {
2234 case CLKCFG_FSB_400
:
2236 case CLKCFG_FSB_533
:
2238 case CLKCFG_FSB_667
:
2240 case CLKCFG_FSB_800
:
2242 case CLKCFG_FSB_1067
:
2243 case CLKCFG_FSB_1067_ALT
:
2245 case CLKCFG_FSB_1333
:
2246 case CLKCFG_FSB_1333_ALT
:
2254 * intel_update_rawclk - Determine the current RAWCLK frequency
2255 * @dev_priv: i915 device
2257 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2258 * frequency clock so this needs to done only once.
2260 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
2263 if (HAS_PCH_CNP(dev_priv
))
2264 dev_priv
->rawclk_freq
= cnp_rawclk(dev_priv
);
2265 else if (HAS_PCH_SPLIT(dev_priv
))
2266 dev_priv
->rawclk_freq
= pch_rawclk(dev_priv
);
2267 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2268 dev_priv
->rawclk_freq
= vlv_hrawclk(dev_priv
);
2269 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
2270 dev_priv
->rawclk_freq
= g4x_hrawclk(dev_priv
);
2272 /* no rawclk on other platforms, or no need to know it */
2275 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
2279 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2280 * @dev_priv: i915 device
2282 void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv
)
2284 if (IS_CHERRYVIEW(dev_priv
)) {
2285 dev_priv
->display
.set_cdclk
= chv_set_cdclk
;
2286 dev_priv
->display
.modeset_calc_cdclk
=
2287 vlv_modeset_calc_cdclk
;
2288 } else if (IS_VALLEYVIEW(dev_priv
)) {
2289 dev_priv
->display
.set_cdclk
= vlv_set_cdclk
;
2290 dev_priv
->display
.modeset_calc_cdclk
=
2291 vlv_modeset_calc_cdclk
;
2292 } else if (IS_BROADWELL(dev_priv
)) {
2293 dev_priv
->display
.set_cdclk
= bdw_set_cdclk
;
2294 dev_priv
->display
.modeset_calc_cdclk
=
2295 bdw_modeset_calc_cdclk
;
2296 } else if (IS_GEN9_LP(dev_priv
)) {
2297 dev_priv
->display
.set_cdclk
= bxt_set_cdclk
;
2298 dev_priv
->display
.modeset_calc_cdclk
=
2299 bxt_modeset_calc_cdclk
;
2300 } else if (IS_GEN9_BC(dev_priv
)) {
2301 dev_priv
->display
.set_cdclk
= skl_set_cdclk
;
2302 dev_priv
->display
.modeset_calc_cdclk
=
2303 skl_modeset_calc_cdclk
;
2304 } else if (IS_CANNONLAKE(dev_priv
)) {
2305 dev_priv
->display
.set_cdclk
= cnl_set_cdclk
;
2306 dev_priv
->display
.modeset_calc_cdclk
=
2307 cnl_modeset_calc_cdclk
;
2310 if (IS_CANNONLAKE(dev_priv
))
2311 dev_priv
->display
.get_cdclk
= cnl_get_cdclk
;
2312 else if (IS_GEN9_BC(dev_priv
))
2313 dev_priv
->display
.get_cdclk
= skl_get_cdclk
;
2314 else if (IS_GEN9_LP(dev_priv
))
2315 dev_priv
->display
.get_cdclk
= bxt_get_cdclk
;
2316 else if (IS_BROADWELL(dev_priv
))
2317 dev_priv
->display
.get_cdclk
= bdw_get_cdclk
;
2318 else if (IS_HASWELL(dev_priv
))
2319 dev_priv
->display
.get_cdclk
= hsw_get_cdclk
;
2320 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2321 dev_priv
->display
.get_cdclk
= vlv_get_cdclk
;
2322 else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
2323 dev_priv
->display
.get_cdclk
= fixed_400mhz_get_cdclk
;
2324 else if (IS_GEN5(dev_priv
))
2325 dev_priv
->display
.get_cdclk
= fixed_450mhz_get_cdclk
;
2326 else if (IS_GM45(dev_priv
))
2327 dev_priv
->display
.get_cdclk
= gm45_get_cdclk
;
2328 else if (IS_G45(dev_priv
))
2329 dev_priv
->display
.get_cdclk
= g33_get_cdclk
;
2330 else if (IS_I965GM(dev_priv
))
2331 dev_priv
->display
.get_cdclk
= i965gm_get_cdclk
;
2332 else if (IS_I965G(dev_priv
))
2333 dev_priv
->display
.get_cdclk
= fixed_400mhz_get_cdclk
;
2334 else if (IS_PINEVIEW(dev_priv
))
2335 dev_priv
->display
.get_cdclk
= pnv_get_cdclk
;
2336 else if (IS_G33(dev_priv
))
2337 dev_priv
->display
.get_cdclk
= g33_get_cdclk
;
2338 else if (IS_I945GM(dev_priv
))
2339 dev_priv
->display
.get_cdclk
= i945gm_get_cdclk
;
2340 else if (IS_I945G(dev_priv
))
2341 dev_priv
->display
.get_cdclk
= fixed_400mhz_get_cdclk
;
2342 else if (IS_I915GM(dev_priv
))
2343 dev_priv
->display
.get_cdclk
= i915gm_get_cdclk
;
2344 else if (IS_I915G(dev_priv
))
2345 dev_priv
->display
.get_cdclk
= fixed_333mhz_get_cdclk
;
2346 else if (IS_I865G(dev_priv
))
2347 dev_priv
->display
.get_cdclk
= fixed_266mhz_get_cdclk
;
2348 else if (IS_I85X(dev_priv
))
2349 dev_priv
->display
.get_cdclk
= i85x_get_cdclk
;
2350 else if (IS_I845G(dev_priv
))
2351 dev_priv
->display
.get_cdclk
= fixed_200mhz_get_cdclk
;
2353 WARN(!IS_I830(dev_priv
),
2354 "Unknown platform. Assuming 133 MHz CDCLK\n");
2355 dev_priv
->display
.get_cdclk
= fixed_133mhz_get_cdclk
;