2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 #include "intel_drv.h"
27 #define CTM_COEFF_SIGN (1ULL << 63)
29 #define CTM_COEFF_1_0 (1ULL << 32)
30 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
31 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
32 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
33 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
34 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
39 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
40 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
42 #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256)
45 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
46 * format). This macro takes the coefficient we want transformed and the
47 * number of fractional bits.
49 * We only have a 9 bits precision window which slides depending on the value
50 * of the CTM coefficient and we write the value from bit 3. We also round the
53 #define I9XX_CSC_COEFF_FP(coeff, fbits) \
54 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
56 #define I9XX_CSC_COEFF_LIMITED_RANGE \
57 I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
58 #define I9XX_CSC_COEFF_1_0 \
59 ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
61 static bool crtc_state_is_legacy(struct drm_crtc_state
*state
)
63 return !state
->degamma_lut
&&
66 state
->gamma_lut
->length
== LEGACY_LUT_LENGTH
;
70 * When using limited range, multiply the matrix given by userspace by
71 * the matrix that we would use for the limited range. We do the
72 * multiplication in U2.30 format.
74 static void ctm_mult_by_limited(uint64_t *result
, int64_t *input
)
78 for (i
= 0; i
< 9; i
++)
81 for (i
= 0; i
< 3; i
++) {
82 int64_t user_coeff
= input
[i
* 3 + i
];
83 uint64_t limited_coeff
= CTM_COEFF_LIMITED_RANGE
>> 2;
84 uint64_t abs_coeff
= clamp_val(CTM_COEFF_ABS(user_coeff
),
86 CTM_COEFF_4_0
- 1) >> 2;
88 result
[i
* 3 + i
] = (limited_coeff
* abs_coeff
) >> 27;
89 if (CTM_COEFF_NEGATIVE(user_coeff
))
90 result
[i
* 3 + i
] |= CTM_COEFF_SIGN
;
94 /* Set up the pipe CSC unit. */
95 static void i9xx_load_csc_matrix(struct drm_crtc_state
*crtc_state
)
97 struct drm_crtc
*crtc
= crtc_state
->crtc
;
98 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
99 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
100 int i
, pipe
= intel_crtc
->pipe
;
101 uint16_t coeffs
[9] = { 0, };
102 struct intel_crtc_state
*intel_crtc_state
= to_intel_crtc_state(crtc_state
);
104 if (crtc_state
->ctm
) {
105 struct drm_color_ctm
*ctm
=
106 (struct drm_color_ctm
*)crtc_state
->ctm
->data
;
107 uint64_t input
[9] = { 0, };
109 if (intel_crtc_state
->limited_color_range
) {
110 ctm_mult_by_limited(input
, ctm
->matrix
);
112 for (i
= 0; i
< ARRAY_SIZE(input
); i
++)
113 input
[i
] = ctm
->matrix
[i
];
117 * Convert fixed point S31.32 input to format supported by the
120 for (i
= 0; i
< ARRAY_SIZE(coeffs
); i
++) {
121 uint64_t abs_coeff
= ((1ULL << 63) - 1) & input
[i
];
124 * Clamp input value to min/max supported by
127 abs_coeff
= clamp_val(abs_coeff
, 0, CTM_COEFF_4_0
- 1);
130 if (CTM_COEFF_NEGATIVE(input
[i
]))
131 coeffs
[i
] |= 1 << 15;
133 if (abs_coeff
< CTM_COEFF_0_125
)
134 coeffs
[i
] |= (3 << 12) |
135 I9XX_CSC_COEFF_FP(abs_coeff
, 12);
136 else if (abs_coeff
< CTM_COEFF_0_25
)
137 coeffs
[i
] |= (2 << 12) |
138 I9XX_CSC_COEFF_FP(abs_coeff
, 11);
139 else if (abs_coeff
< CTM_COEFF_0_5
)
140 coeffs
[i
] |= (1 << 12) |
141 I9XX_CSC_COEFF_FP(abs_coeff
, 10);
142 else if (abs_coeff
< CTM_COEFF_1_0
)
143 coeffs
[i
] |= I9XX_CSC_COEFF_FP(abs_coeff
, 9);
144 else if (abs_coeff
< CTM_COEFF_2_0
)
145 coeffs
[i
] |= (7 << 12) |
146 I9XX_CSC_COEFF_FP(abs_coeff
, 8);
148 coeffs
[i
] |= (6 << 12) |
149 I9XX_CSC_COEFF_FP(abs_coeff
, 7);
153 * Load an identity matrix if no coefficients are provided.
155 * TODO: Check what kind of values actually come out of the
156 * pipe with these coeff/postoff values and adjust to get the
157 * best accuracy. Perhaps we even need to take the bpc value
158 * into consideration.
160 for (i
= 0; i
< 3; i
++) {
161 if (intel_crtc_state
->limited_color_range
)
163 I9XX_CSC_COEFF_LIMITED_RANGE
;
165 coeffs
[i
* 3 + i
] = I9XX_CSC_COEFF_1_0
;
169 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeffs
[0] << 16 | coeffs
[1]);
170 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), coeffs
[2] << 16);
172 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeffs
[3] << 16 | coeffs
[4]);
173 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), coeffs
[5] << 16);
175 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), coeffs
[6] << 16 | coeffs
[7]);
176 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeffs
[8] << 16);
178 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
179 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
180 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
182 if (INTEL_GEN(dev_priv
) > 6) {
183 uint16_t postoff
= 0;
185 if (intel_crtc_state
->limited_color_range
)
186 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
188 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
189 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
190 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
192 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
194 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
196 if (intel_crtc_state
->limited_color_range
)
197 mode
|= CSC_BLACK_SCREEN_OFFSET
;
199 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
204 * Set up the pipe CSC unit on CherryView.
206 static void cherryview_load_csc_matrix(struct drm_crtc_state
*state
)
208 struct drm_crtc
*crtc
= state
->crtc
;
209 struct drm_device
*dev
= crtc
->dev
;
210 struct drm_i915_private
*dev_priv
= to_i915(dev
);
211 int pipe
= to_intel_crtc(crtc
)->pipe
;
215 struct drm_color_ctm
*ctm
=
216 (struct drm_color_ctm
*) state
->ctm
->data
;
217 uint16_t coeffs
[9] = { 0, };
220 for (i
= 0; i
< ARRAY_SIZE(coeffs
); i
++) {
222 ((1ULL << 63) - 1) & ctm
->matrix
[i
];
224 /* Round coefficient. */
225 abs_coeff
+= 1 << (32 - 13);
226 /* Clamp to hardware limits. */
227 abs_coeff
= clamp_val(abs_coeff
, 0, CTM_COEFF_8_0
- 1);
229 /* Write coefficients in S3.12 format. */
230 if (ctm
->matrix
[i
] & (1ULL << 63))
232 coeffs
[i
] |= ((abs_coeff
>> 32) & 7) << 12;
233 coeffs
[i
] |= (abs_coeff
>> 20) & 0xfff;
236 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe
),
237 coeffs
[1] << 16 | coeffs
[0]);
238 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe
),
239 coeffs
[3] << 16 | coeffs
[2]);
240 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe
),
241 coeffs
[5] << 16 | coeffs
[4]);
242 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe
),
243 coeffs
[7] << 16 | coeffs
[6]);
244 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe
), coeffs
[8]);
247 mode
= (state
->ctm
? CGM_PIPE_MODE_CSC
: 0);
248 if (!crtc_state_is_legacy(state
)) {
249 mode
|= (state
->degamma_lut
? CGM_PIPE_MODE_DEGAMMA
: 0) |
250 (state
->gamma_lut
? CGM_PIPE_MODE_GAMMA
: 0);
252 I915_WRITE(CGM_PIPE_MODE(pipe
), mode
);
255 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
)
257 struct drm_device
*dev
= crtc_state
->crtc
->dev
;
258 struct drm_i915_private
*dev_priv
= to_i915(dev
);
260 if (dev_priv
->display
.load_csc_matrix
)
261 dev_priv
->display
.load_csc_matrix(crtc_state
);
264 /* Loads the legacy palette/gamma unit for the CRTC. */
265 static void i9xx_load_luts_internal(struct drm_crtc
*crtc
,
266 struct drm_property_blob
*blob
,
267 struct intel_crtc_state
*crtc_state
)
269 struct drm_device
*dev
= crtc
->dev
;
270 struct drm_i915_private
*dev_priv
= to_i915(dev
);
271 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
272 enum pipe pipe
= intel_crtc
->pipe
;
275 if (HAS_GMCH_DISPLAY(dev_priv
)) {
276 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
))
277 assert_dsi_pll_enabled(dev_priv
);
279 assert_pll_enabled(dev_priv
, pipe
);
283 struct drm_color_lut
*lut
= (struct drm_color_lut
*) blob
->data
;
284 for (i
= 0; i
< 256; i
++) {
286 (drm_color_lut_extract(lut
[i
].red
, 8) << 16) |
287 (drm_color_lut_extract(lut
[i
].green
, 8) << 8) |
288 drm_color_lut_extract(lut
[i
].blue
, 8);
290 if (HAS_GMCH_DISPLAY(dev_priv
))
291 I915_WRITE(PALETTE(pipe
, i
), word
);
293 I915_WRITE(LGC_PALETTE(pipe
, i
), word
);
296 for (i
= 0; i
< 256; i
++) {
297 uint32_t word
= (i
<< 16) | (i
<< 8) | i
;
299 if (HAS_GMCH_DISPLAY(dev_priv
))
300 I915_WRITE(PALETTE(pipe
, i
), word
);
302 I915_WRITE(LGC_PALETTE(pipe
, i
), word
);
307 static void i9xx_load_luts(struct drm_crtc_state
*crtc_state
)
309 i9xx_load_luts_internal(crtc_state
->crtc
, crtc_state
->gamma_lut
,
310 to_intel_crtc_state(crtc_state
));
313 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
314 static void haswell_load_luts(struct drm_crtc_state
*crtc_state
)
316 struct drm_crtc
*crtc
= crtc_state
->crtc
;
317 struct drm_device
*dev
= crtc
->dev
;
318 struct drm_i915_private
*dev_priv
= to_i915(dev
);
319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
320 struct intel_crtc_state
*intel_crtc_state
=
321 to_intel_crtc_state(crtc_state
);
322 bool reenable_ips
= false;
325 * Workaround : Do not read or write the pipe palette/gamma data while
326 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
328 if (IS_HASWELL(dev_priv
) && intel_crtc_state
->ips_enabled
&&
329 (intel_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)) {
330 hsw_disable_ips(intel_crtc
);
334 intel_crtc_state
->gamma_mode
= GAMMA_MODE_MODE_8BIT
;
335 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
337 i9xx_load_luts(crtc_state
);
340 hsw_enable_ips(intel_crtc
);
343 static void bdw_load_degamma_lut(struct drm_crtc_state
*state
)
345 struct drm_i915_private
*dev_priv
= to_i915(state
->crtc
->dev
);
346 enum pipe pipe
= to_intel_crtc(state
->crtc
)->pipe
;
347 uint32_t i
, lut_size
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
;
349 I915_WRITE(PREC_PAL_INDEX(pipe
),
350 PAL_PREC_SPLIT_MODE
| PAL_PREC_AUTO_INCREMENT
);
352 if (state
->degamma_lut
) {
353 struct drm_color_lut
*lut
=
354 (struct drm_color_lut
*) state
->degamma_lut
->data
;
356 for (i
= 0; i
< lut_size
; i
++) {
358 drm_color_lut_extract(lut
[i
].red
, 10) << 20 |
359 drm_color_lut_extract(lut
[i
].green
, 10) << 10 |
360 drm_color_lut_extract(lut
[i
].blue
, 10);
362 I915_WRITE(PREC_PAL_DATA(pipe
), word
);
365 for (i
= 0; i
< lut_size
; i
++) {
366 uint32_t v
= (i
* ((1 << 10) - 1)) / (lut_size
- 1);
368 I915_WRITE(PREC_PAL_DATA(pipe
),
369 (v
<< 20) | (v
<< 10) | v
);
374 static void bdw_load_gamma_lut(struct drm_crtc_state
*state
, u32 offset
)
376 struct drm_i915_private
*dev_priv
= to_i915(state
->crtc
->dev
);
377 enum pipe pipe
= to_intel_crtc(state
->crtc
)->pipe
;
378 uint32_t i
, lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
380 WARN_ON(offset
& ~PAL_PREC_INDEX_VALUE_MASK
);
382 I915_WRITE(PREC_PAL_INDEX(pipe
),
383 (offset
? PAL_PREC_SPLIT_MODE
: 0) |
384 PAL_PREC_AUTO_INCREMENT
|
387 if (state
->gamma_lut
) {
388 struct drm_color_lut
*lut
=
389 (struct drm_color_lut
*) state
->gamma_lut
->data
;
391 for (i
= 0; i
< lut_size
; i
++) {
393 (drm_color_lut_extract(lut
[i
].red
, 10) << 20) |
394 (drm_color_lut_extract(lut
[i
].green
, 10) << 10) |
395 drm_color_lut_extract(lut
[i
].blue
, 10);
397 I915_WRITE(PREC_PAL_DATA(pipe
), word
);
400 /* Program the max register to clamp values > 1.0. */
401 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 0),
402 drm_color_lut_extract(lut
[i
].red
, 16));
403 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 1),
404 drm_color_lut_extract(lut
[i
].green
, 16));
405 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 2),
406 drm_color_lut_extract(lut
[i
].blue
, 16));
408 for (i
= 0; i
< lut_size
; i
++) {
409 uint32_t v
= (i
* ((1 << 10) - 1)) / (lut_size
- 1);
411 I915_WRITE(PREC_PAL_DATA(pipe
),
412 (v
<< 20) | (v
<< 10) | v
);
415 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 0), (1 << 16) - 1);
416 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 1), (1 << 16) - 1);
417 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 2), (1 << 16) - 1);
421 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
422 static void broadwell_load_luts(struct drm_crtc_state
*state
)
424 struct drm_i915_private
*dev_priv
= to_i915(state
->crtc
->dev
);
425 struct intel_crtc_state
*intel_state
= to_intel_crtc_state(state
);
426 enum pipe pipe
= to_intel_crtc(state
->crtc
)->pipe
;
428 if (crtc_state_is_legacy(state
)) {
429 haswell_load_luts(state
);
433 bdw_load_degamma_lut(state
);
434 bdw_load_gamma_lut(state
,
435 INTEL_INFO(dev_priv
)->color
.degamma_lut_size
);
437 intel_state
->gamma_mode
= GAMMA_MODE_MODE_SPLIT
;
438 I915_WRITE(GAMMA_MODE(pipe
), GAMMA_MODE_MODE_SPLIT
);
439 POSTING_READ(GAMMA_MODE(pipe
));
442 * Reset the index, otherwise it prevents the legacy palette to be
445 I915_WRITE(PREC_PAL_INDEX(pipe
), 0);
448 static void glk_load_degamma_lut(struct drm_crtc_state
*state
)
450 struct drm_i915_private
*dev_priv
= to_i915(state
->crtc
->dev
);
451 enum pipe pipe
= to_intel_crtc(state
->crtc
)->pipe
;
452 const uint32_t lut_size
= 33;
456 * When setting the auto-increment bit, the hardware seems to
457 * ignore the index bits, so we need to reset it to index 0
460 I915_WRITE(PRE_CSC_GAMC_INDEX(pipe
), 0);
461 I915_WRITE(PRE_CSC_GAMC_INDEX(pipe
), PRE_CSC_GAMC_AUTO_INCREMENT
);
464 * FIXME: The pipe degamma table in geminilake doesn't support
465 * different values per channel, so this just loads a linear table.
467 for (i
= 0; i
< lut_size
; i
++) {
468 uint32_t v
= (i
* (1 << 16)) / (lut_size
- 1);
470 I915_WRITE(PRE_CSC_GAMC_DATA(pipe
), v
);
473 /* Clamp values > 1.0. */
475 I915_WRITE(PRE_CSC_GAMC_DATA(pipe
), (1 << 16));
478 static void glk_load_luts(struct drm_crtc_state
*state
)
480 struct drm_crtc
*crtc
= state
->crtc
;
481 struct drm_device
*dev
= crtc
->dev
;
482 struct drm_i915_private
*dev_priv
= to_i915(dev
);
483 struct intel_crtc_state
*intel_state
= to_intel_crtc_state(state
);
484 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
486 glk_load_degamma_lut(state
);
488 if (crtc_state_is_legacy(state
)) {
489 haswell_load_luts(state
);
493 bdw_load_gamma_lut(state
, 0);
495 intel_state
->gamma_mode
= GAMMA_MODE_MODE_10BIT
;
496 I915_WRITE(GAMMA_MODE(pipe
), GAMMA_MODE_MODE_10BIT
);
497 POSTING_READ(GAMMA_MODE(pipe
));
500 /* Loads the palette/gamma unit for the CRTC on CherryView. */
501 static void cherryview_load_luts(struct drm_crtc_state
*state
)
503 struct drm_crtc
*crtc
= state
->crtc
;
504 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
505 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
506 struct drm_color_lut
*lut
;
507 uint32_t i
, lut_size
;
508 uint32_t word0
, word1
;
510 if (crtc_state_is_legacy(state
)) {
511 /* Turn off degamma/gamma on CGM block. */
512 I915_WRITE(CGM_PIPE_MODE(pipe
),
513 (state
->ctm
? CGM_PIPE_MODE_CSC
: 0));
514 i9xx_load_luts_internal(crtc
, state
->gamma_lut
,
515 to_intel_crtc_state(state
));
519 if (state
->degamma_lut
) {
520 lut
= (struct drm_color_lut
*) state
->degamma_lut
->data
;
521 lut_size
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
;
522 for (i
= 0; i
< lut_size
; i
++) {
523 /* Write LUT in U0.14 format. */
525 (drm_color_lut_extract(lut
[i
].green
, 14) << 16) |
526 drm_color_lut_extract(lut
[i
].blue
, 14);
527 word1
= drm_color_lut_extract(lut
[i
].red
, 14);
529 I915_WRITE(CGM_PIPE_DEGAMMA(pipe
, i
, 0), word0
);
530 I915_WRITE(CGM_PIPE_DEGAMMA(pipe
, i
, 1), word1
);
534 if (state
->gamma_lut
) {
535 lut
= (struct drm_color_lut
*) state
->gamma_lut
->data
;
536 lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
537 for (i
= 0; i
< lut_size
; i
++) {
538 /* Write LUT in U0.10 format. */
540 (drm_color_lut_extract(lut
[i
].green
, 10) << 16) |
541 drm_color_lut_extract(lut
[i
].blue
, 10);
542 word1
= drm_color_lut_extract(lut
[i
].red
, 10);
544 I915_WRITE(CGM_PIPE_GAMMA(pipe
, i
, 0), word0
);
545 I915_WRITE(CGM_PIPE_GAMMA(pipe
, i
, 1), word1
);
549 I915_WRITE(CGM_PIPE_MODE(pipe
),
550 (state
->ctm
? CGM_PIPE_MODE_CSC
: 0) |
551 (state
->degamma_lut
? CGM_PIPE_MODE_DEGAMMA
: 0) |
552 (state
->gamma_lut
? CGM_PIPE_MODE_GAMMA
: 0));
555 * Also program a linear LUT in the legacy block (behind the
558 i9xx_load_luts_internal(crtc
, NULL
, to_intel_crtc_state(state
));
561 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
)
563 struct drm_device
*dev
= crtc_state
->crtc
->dev
;
564 struct drm_i915_private
*dev_priv
= to_i915(dev
);
566 dev_priv
->display
.load_luts(crtc_state
);
569 int intel_color_check(struct drm_crtc
*crtc
,
570 struct drm_crtc_state
*crtc_state
)
572 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
573 size_t gamma_length
, degamma_length
;
575 degamma_length
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
*
576 sizeof(struct drm_color_lut
);
577 gamma_length
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
*
578 sizeof(struct drm_color_lut
);
581 * We allow both degamma & gamma luts at the right size or
584 if ((!crtc_state
->degamma_lut
||
585 crtc_state
->degamma_lut
->length
== degamma_length
) &&
586 (!crtc_state
->gamma_lut
||
587 crtc_state
->gamma_lut
->length
== gamma_length
))
591 * We also allow no degamma lut and a gamma lut at the legacy
592 * size (256 entries).
594 if (!crtc_state
->degamma_lut
&&
595 crtc_state
->gamma_lut
&&
596 crtc_state
->gamma_lut
->length
== LEGACY_LUT_LENGTH
)
602 void intel_color_init(struct drm_crtc
*crtc
)
604 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
606 drm_mode_crtc_set_gamma_size(crtc
, 256);
608 if (IS_CHERRYVIEW(dev_priv
)) {
609 dev_priv
->display
.load_csc_matrix
= cherryview_load_csc_matrix
;
610 dev_priv
->display
.load_luts
= cherryview_load_luts
;
611 } else if (IS_HASWELL(dev_priv
)) {
612 dev_priv
->display
.load_csc_matrix
= i9xx_load_csc_matrix
;
613 dev_priv
->display
.load_luts
= haswell_load_luts
;
614 } else if (IS_BROADWELL(dev_priv
) || IS_GEN9_BC(dev_priv
) ||
615 IS_BROXTON(dev_priv
)) {
616 dev_priv
->display
.load_csc_matrix
= i9xx_load_csc_matrix
;
617 dev_priv
->display
.load_luts
= broadwell_load_luts
;
618 } else if (IS_GEMINILAKE(dev_priv
)) {
619 dev_priv
->display
.load_csc_matrix
= i9xx_load_csc_matrix
;
620 dev_priv
->display
.load_luts
= glk_load_luts
;
622 dev_priv
->display
.load_luts
= i9xx_load_luts
;
625 /* Enable color management support when we have degamma & gamma LUTs. */
626 if (INTEL_INFO(dev_priv
)->color
.degamma_lut_size
!= 0 &&
627 INTEL_INFO(dev_priv
)->color
.gamma_lut_size
!= 0)
628 drm_crtc_enable_color_mgmt(crtc
,
629 INTEL_INFO(dev_priv
)->color
.degamma_lut_size
,
631 INTEL_INFO(dev_priv
)->color
.gamma_lut_size
);