]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/i915/intel_ddi.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915/cnl: DDI - PLL mapping
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48 };
49
50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
64 };
65
66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
76 };
77
78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
92 };
93
94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
104 };
105
106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
116 };
117
118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
128 };
129
130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
142 };
143
144 /* Skylake H and S */
145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x000000DF, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake U */
158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159 { 0x0000201B, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x1 },
162 { 0x80009010, 0x000000C0, 0x1 },
163 { 0x0000201B, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
166 { 0x00002016, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x1 },
168 };
169
170 /* Skylake Y */
171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000CD, 0x3 },
175 { 0x80009010, 0x000000C0, 0x3 },
176 { 0x00000018, 0x0000009D, 0x0 },
177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
179 { 0x00000018, 0x00000088, 0x0 },
180 { 0x80005012, 0x000000C0, 0x3 },
181 };
182
183 /* Kabylake H and S */
184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194 };
195
196 /* Kabylake U */
197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207 };
208
209 /* Kabylake Y */
210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220 };
221
222 /*
223 * Skylake/Kabylake H and S
224 * eDP 1.4 low vswing translation parameters
225 */
226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237 };
238
239 /*
240 * Skylake/Kabylake U
241 * eDP 1.4 low vswing translation parameters
242 */
243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
254 };
255
256 /*
257 * Skylake/Kabylake Y
258 * eDP 1.4 low vswing translation parameters
259 */
260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271 };
272
273 /* Skylake/Kabylake U, H and S */
274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
281 { 0x80006012, 0x000000CD, 0x1 },
282 { 0x00000018, 0x000000DF, 0x0 },
283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
286 };
287
288 /* Skylake/Kabylake Y */
289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
292 { 0x80007011, 0x000000CB, 0x3 },
293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
296 { 0x80006013, 0x000000C0, 0x3 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
301 };
302
303 struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309 };
310
311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
323 };
324
325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337 };
338
339 /* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354 };
355
356 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
357 {
358 switch (encoder->type) {
359 case INTEL_OUTPUT_DP_MST:
360 return enc_to_mst(&encoder->base)->primary->port;
361 case INTEL_OUTPUT_DP:
362 case INTEL_OUTPUT_EDP:
363 case INTEL_OUTPUT_HDMI:
364 case INTEL_OUTPUT_UNKNOWN:
365 return enc_to_dig_port(&encoder->base)->port;
366 case INTEL_OUTPUT_ANALOG:
367 return PORT_E;
368 default:
369 MISSING_CASE(encoder->type);
370 return PORT_A;
371 }
372 }
373
374 static const struct ddi_buf_trans *
375 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
376 {
377 if (dev_priv->vbt.edp.low_vswing) {
378 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
379 return bdw_ddi_translations_edp;
380 } else {
381 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
382 return bdw_ddi_translations_dp;
383 }
384 }
385
386 static const struct ddi_buf_trans *
387 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
388 {
389 if (IS_SKL_ULX(dev_priv)) {
390 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
391 return skl_y_ddi_translations_dp;
392 } else if (IS_SKL_ULT(dev_priv)) {
393 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
394 return skl_u_ddi_translations_dp;
395 } else {
396 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
397 return skl_ddi_translations_dp;
398 }
399 }
400
401 static const struct ddi_buf_trans *
402 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
403 {
404 if (IS_KBL_ULX(dev_priv)) {
405 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
406 return kbl_y_ddi_translations_dp;
407 } else if (IS_KBL_ULT(dev_priv)) {
408 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
409 return kbl_u_ddi_translations_dp;
410 } else {
411 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
412 return kbl_ddi_translations_dp;
413 }
414 }
415
416 static const struct ddi_buf_trans *
417 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
418 {
419 if (dev_priv->vbt.edp.low_vswing) {
420 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
421 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
422 return skl_y_ddi_translations_edp;
423 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
424 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
425 return skl_u_ddi_translations_edp;
426 } else {
427 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
428 return skl_ddi_translations_edp;
429 }
430 }
431
432 if (IS_KABYLAKE(dev_priv))
433 return kbl_get_buf_trans_dp(dev_priv, n_entries);
434 else
435 return skl_get_buf_trans_dp(dev_priv, n_entries);
436 }
437
438 static const struct ddi_buf_trans *
439 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
440 {
441 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
442 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
443 return skl_y_ddi_translations_hdmi;
444 } else {
445 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
446 return skl_ddi_translations_hdmi;
447 }
448 }
449
450 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
451 {
452 int n_hdmi_entries;
453 int hdmi_level;
454 int hdmi_default_entry;
455
456 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
457
458 if (IS_GEN9_LP(dev_priv))
459 return hdmi_level;
460
461 if (IS_GEN9_BC(dev_priv)) {
462 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
463 hdmi_default_entry = 8;
464 } else if (IS_BROADWELL(dev_priv)) {
465 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
466 hdmi_default_entry = 7;
467 } else if (IS_HASWELL(dev_priv)) {
468 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
469 hdmi_default_entry = 6;
470 } else {
471 WARN(1, "ddi translation table missing\n");
472 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
473 hdmi_default_entry = 7;
474 }
475
476 /* Choose a good default if VBT is badly populated */
477 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
478 hdmi_level >= n_hdmi_entries)
479 hdmi_level = hdmi_default_entry;
480
481 return hdmi_level;
482 }
483
484 static const struct ddi_buf_trans *
485 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
486 int *n_entries)
487 {
488 if (IS_KABYLAKE(dev_priv)) {
489 return kbl_get_buf_trans_dp(dev_priv, n_entries);
490 } else if (IS_SKYLAKE(dev_priv)) {
491 return skl_get_buf_trans_dp(dev_priv, n_entries);
492 } else if (IS_BROADWELL(dev_priv)) {
493 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
494 return bdw_ddi_translations_dp;
495 } else if (IS_HASWELL(dev_priv)) {
496 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
497 return hsw_ddi_translations_dp;
498 }
499
500 *n_entries = 0;
501 return NULL;
502 }
503
504 static const struct ddi_buf_trans *
505 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
506 int *n_entries)
507 {
508 if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
509 return skl_get_buf_trans_edp(dev_priv, n_entries);
510 } else if (IS_BROADWELL(dev_priv)) {
511 return bdw_get_buf_trans_edp(dev_priv, n_entries);
512 } else if (IS_HASWELL(dev_priv)) {
513 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
514 return hsw_ddi_translations_dp;
515 }
516
517 *n_entries = 0;
518 return NULL;
519 }
520
521 static const struct ddi_buf_trans *
522 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
523 int *n_entries)
524 {
525 if (IS_BROADWELL(dev_priv)) {
526 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
527 return hsw_ddi_translations_fdi;
528 } else if (IS_HASWELL(dev_priv)) {
529 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
530 return hsw_ddi_translations_fdi;
531 }
532
533 *n_entries = 0;
534 return NULL;
535 }
536
537 /*
538 * Starting with Haswell, DDI port buffers must be programmed with correct
539 * values in advance. This function programs the correct values for
540 * DP/eDP/FDI use cases.
541 */
542 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
543 {
544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
545 u32 iboost_bit = 0;
546 int i, n_entries;
547 enum port port = intel_ddi_get_encoder_port(encoder);
548 const struct ddi_buf_trans *ddi_translations;
549
550 if (IS_GEN9_LP(dev_priv))
551 return;
552
553 switch (encoder->type) {
554 case INTEL_OUTPUT_EDP:
555 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
556 &n_entries);
557 break;
558 case INTEL_OUTPUT_DP:
559 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
560 &n_entries);
561 break;
562 case INTEL_OUTPUT_ANALOG:
563 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
564 &n_entries);
565 break;
566 default:
567 MISSING_CASE(encoder->type);
568 return;
569 }
570
571 if (IS_GEN9_BC(dev_priv)) {
572 /* If we're boosting the current, set bit 31 of trans1 */
573 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
574 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
575
576 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
577 port != PORT_A && port != PORT_E &&
578 n_entries > 9))
579 n_entries = 9;
580 }
581
582 for (i = 0; i < n_entries; i++) {
583 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
584 ddi_translations[i].trans1 | iboost_bit);
585 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
586 ddi_translations[i].trans2);
587 }
588 }
589
590 /*
591 * Starting with Haswell, DDI port buffers must be programmed with correct
592 * values in advance. This function programs the correct values for
593 * HDMI/DVI use cases.
594 */
595 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
596 {
597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
598 u32 iboost_bit = 0;
599 int n_hdmi_entries, hdmi_level;
600 enum port port = intel_ddi_get_encoder_port(encoder);
601 const struct ddi_buf_trans *ddi_translations_hdmi;
602
603 if (IS_GEN9_LP(dev_priv))
604 return;
605
606 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
607
608 if (IS_GEN9_BC(dev_priv)) {
609 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
610
611 /* If we're boosting the current, set bit 31 of trans1 */
612 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
613 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
614 } else if (IS_BROADWELL(dev_priv)) {
615 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
616 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
617 } else if (IS_HASWELL(dev_priv)) {
618 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
619 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
620 } else {
621 WARN(1, "ddi translation table missing\n");
622 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
623 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
624 }
625
626 /* Entry 9 is for HDMI: */
627 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
628 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
629 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
630 ddi_translations_hdmi[hdmi_level].trans2);
631 }
632
633 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
634 enum port port)
635 {
636 i915_reg_t reg = DDI_BUF_CTL(port);
637 int i;
638
639 for (i = 0; i < 16; i++) {
640 udelay(1);
641 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
642 return;
643 }
644 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
645 }
646
647 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
648 {
649 switch (pll->id) {
650 case DPLL_ID_WRPLL1:
651 return PORT_CLK_SEL_WRPLL1;
652 case DPLL_ID_WRPLL2:
653 return PORT_CLK_SEL_WRPLL2;
654 case DPLL_ID_SPLL:
655 return PORT_CLK_SEL_SPLL;
656 case DPLL_ID_LCPLL_810:
657 return PORT_CLK_SEL_LCPLL_810;
658 case DPLL_ID_LCPLL_1350:
659 return PORT_CLK_SEL_LCPLL_1350;
660 case DPLL_ID_LCPLL_2700:
661 return PORT_CLK_SEL_LCPLL_2700;
662 default:
663 MISSING_CASE(pll->id);
664 return PORT_CLK_SEL_NONE;
665 }
666 }
667
668 /* Starting with Haswell, different DDI ports can work in FDI mode for
669 * connection to the PCH-located connectors. For this, it is necessary to train
670 * both the DDI port and PCH receiver for the desired DDI buffer settings.
671 *
672 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
673 * please note that when FDI mode is active on DDI E, it shares 2 lines with
674 * DDI A (which is used for eDP)
675 */
676
677 void hsw_fdi_link_train(struct intel_crtc *crtc,
678 const struct intel_crtc_state *crtc_state)
679 {
680 struct drm_device *dev = crtc->base.dev;
681 struct drm_i915_private *dev_priv = to_i915(dev);
682 struct intel_encoder *encoder;
683 u32 temp, i, rx_ctl_val, ddi_pll_sel;
684
685 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
686 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
687 intel_prepare_dp_ddi_buffers(encoder);
688 }
689
690 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
691 * mode set "sequence for CRT port" document:
692 * - TP1 to TP2 time with the default value
693 * - FDI delay to 90h
694 *
695 * WaFDIAutoLinkSetTimingOverrride:hsw
696 */
697 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
698 FDI_RX_PWRDN_LANE0_VAL(2) |
699 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
700
701 /* Enable the PCH Receiver FDI PLL */
702 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
703 FDI_RX_PLL_ENABLE |
704 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
705 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
706 POSTING_READ(FDI_RX_CTL(PIPE_A));
707 udelay(220);
708
709 /* Switch from Rawclk to PCDclk */
710 rx_ctl_val |= FDI_PCDCLK;
711 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
712
713 /* Configure Port Clock Select */
714 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
715 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
716 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
717
718 /* Start the training iterating through available voltages and emphasis,
719 * testing each value twice. */
720 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
721 /* Configure DP_TP_CTL with auto-training */
722 I915_WRITE(DP_TP_CTL(PORT_E),
723 DP_TP_CTL_FDI_AUTOTRAIN |
724 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
725 DP_TP_CTL_LINK_TRAIN_PAT1 |
726 DP_TP_CTL_ENABLE);
727
728 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
729 * DDI E does not support port reversal, the functionality is
730 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
731 * port reversal bit */
732 I915_WRITE(DDI_BUF_CTL(PORT_E),
733 DDI_BUF_CTL_ENABLE |
734 ((crtc_state->fdi_lanes - 1) << 1) |
735 DDI_BUF_TRANS_SELECT(i / 2));
736 POSTING_READ(DDI_BUF_CTL(PORT_E));
737
738 udelay(600);
739
740 /* Program PCH FDI Receiver TU */
741 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
742
743 /* Enable PCH FDI Receiver with auto-training */
744 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
745 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
746 POSTING_READ(FDI_RX_CTL(PIPE_A));
747
748 /* Wait for FDI receiver lane calibration */
749 udelay(30);
750
751 /* Unset FDI_RX_MISC pwrdn lanes */
752 temp = I915_READ(FDI_RX_MISC(PIPE_A));
753 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
754 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
755 POSTING_READ(FDI_RX_MISC(PIPE_A));
756
757 /* Wait for FDI auto training time */
758 udelay(5);
759
760 temp = I915_READ(DP_TP_STATUS(PORT_E));
761 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
762 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
763 break;
764 }
765
766 /*
767 * Leave things enabled even if we failed to train FDI.
768 * Results in less fireworks from the state checker.
769 */
770 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
771 DRM_ERROR("FDI link training failed!\n");
772 break;
773 }
774
775 rx_ctl_val &= ~FDI_RX_ENABLE;
776 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
777 POSTING_READ(FDI_RX_CTL(PIPE_A));
778
779 temp = I915_READ(DDI_BUF_CTL(PORT_E));
780 temp &= ~DDI_BUF_CTL_ENABLE;
781 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
782 POSTING_READ(DDI_BUF_CTL(PORT_E));
783
784 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
785 temp = I915_READ(DP_TP_CTL(PORT_E));
786 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
787 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
788 I915_WRITE(DP_TP_CTL(PORT_E), temp);
789 POSTING_READ(DP_TP_CTL(PORT_E));
790
791 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
792
793 /* Reset FDI_RX_MISC pwrdn lanes */
794 temp = I915_READ(FDI_RX_MISC(PIPE_A));
795 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
796 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
797 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
798 POSTING_READ(FDI_RX_MISC(PIPE_A));
799 }
800
801 /* Enable normal pixel sending for FDI */
802 I915_WRITE(DP_TP_CTL(PORT_E),
803 DP_TP_CTL_FDI_AUTOTRAIN |
804 DP_TP_CTL_LINK_TRAIN_NORMAL |
805 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
806 DP_TP_CTL_ENABLE);
807 }
808
809 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
810 {
811 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
812 struct intel_digital_port *intel_dig_port =
813 enc_to_dig_port(&encoder->base);
814
815 intel_dp->DP = intel_dig_port->saved_port_bits |
816 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
817 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
818 }
819
820 static struct intel_encoder *
821 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
822 {
823 struct drm_device *dev = crtc->base.dev;
824 struct intel_encoder *encoder, *ret = NULL;
825 int num_encoders = 0;
826
827 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
828 ret = encoder;
829 num_encoders++;
830 }
831
832 if (num_encoders != 1)
833 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
834 pipe_name(crtc->pipe));
835
836 BUG_ON(ret == NULL);
837 return ret;
838 }
839
840 /* Finds the only possible encoder associated with the given CRTC. */
841 struct intel_encoder *
842 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
843 {
844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
845 struct intel_encoder *ret = NULL;
846 struct drm_atomic_state *state;
847 struct drm_connector *connector;
848 struct drm_connector_state *connector_state;
849 int num_encoders = 0;
850 int i;
851
852 state = crtc_state->base.state;
853
854 for_each_new_connector_in_state(state, connector, connector_state, i) {
855 if (connector_state->crtc != crtc_state->base.crtc)
856 continue;
857
858 ret = to_intel_encoder(connector_state->best_encoder);
859 num_encoders++;
860 }
861
862 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
863 pipe_name(crtc->pipe));
864
865 BUG_ON(ret == NULL);
866 return ret;
867 }
868
869 #define LC_FREQ 2700
870
871 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
872 i915_reg_t reg)
873 {
874 int refclk = LC_FREQ;
875 int n, p, r;
876 u32 wrpll;
877
878 wrpll = I915_READ(reg);
879 switch (wrpll & WRPLL_PLL_REF_MASK) {
880 case WRPLL_PLL_SSC:
881 case WRPLL_PLL_NON_SSC:
882 /*
883 * We could calculate spread here, but our checking
884 * code only cares about 5% accuracy, and spread is a max of
885 * 0.5% downspread.
886 */
887 refclk = 135;
888 break;
889 case WRPLL_PLL_LCPLL:
890 refclk = LC_FREQ;
891 break;
892 default:
893 WARN(1, "bad wrpll refclk\n");
894 return 0;
895 }
896
897 r = wrpll & WRPLL_DIVIDER_REF_MASK;
898 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
899 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
900
901 /* Convert to KHz, p & r have a fixed point portion */
902 return (refclk * n * 100) / (p * r);
903 }
904
905 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
906 uint32_t dpll)
907 {
908 i915_reg_t cfgcr1_reg, cfgcr2_reg;
909 uint32_t cfgcr1_val, cfgcr2_val;
910 uint32_t p0, p1, p2, dco_freq;
911
912 cfgcr1_reg = DPLL_CFGCR1(dpll);
913 cfgcr2_reg = DPLL_CFGCR2(dpll);
914
915 cfgcr1_val = I915_READ(cfgcr1_reg);
916 cfgcr2_val = I915_READ(cfgcr2_reg);
917
918 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
919 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
920
921 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
922 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
923 else
924 p1 = 1;
925
926
927 switch (p0) {
928 case DPLL_CFGCR2_PDIV_1:
929 p0 = 1;
930 break;
931 case DPLL_CFGCR2_PDIV_2:
932 p0 = 2;
933 break;
934 case DPLL_CFGCR2_PDIV_3:
935 p0 = 3;
936 break;
937 case DPLL_CFGCR2_PDIV_7:
938 p0 = 7;
939 break;
940 }
941
942 switch (p2) {
943 case DPLL_CFGCR2_KDIV_5:
944 p2 = 5;
945 break;
946 case DPLL_CFGCR2_KDIV_2:
947 p2 = 2;
948 break;
949 case DPLL_CFGCR2_KDIV_3:
950 p2 = 3;
951 break;
952 case DPLL_CFGCR2_KDIV_1:
953 p2 = 1;
954 break;
955 }
956
957 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
958
959 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
960 1000) / 0x8000;
961
962 return dco_freq / (p0 * p1 * p2 * 5);
963 }
964
965 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
966 {
967 int dotclock;
968
969 if (pipe_config->has_pch_encoder)
970 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
971 &pipe_config->fdi_m_n);
972 else if (intel_crtc_has_dp_encoder(pipe_config))
973 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
974 &pipe_config->dp_m_n);
975 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
976 dotclock = pipe_config->port_clock * 2 / 3;
977 else
978 dotclock = pipe_config->port_clock;
979
980 if (pipe_config->pixel_multiplier)
981 dotclock /= pipe_config->pixel_multiplier;
982
983 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
984 }
985
986 static void skl_ddi_clock_get(struct intel_encoder *encoder,
987 struct intel_crtc_state *pipe_config)
988 {
989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
990 int link_clock = 0;
991 uint32_t dpll_ctl1, dpll;
992
993 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
994
995 dpll_ctl1 = I915_READ(DPLL_CTRL1);
996
997 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
998 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
999 } else {
1000 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1001 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1002
1003 switch (link_clock) {
1004 case DPLL_CTRL1_LINK_RATE_810:
1005 link_clock = 81000;
1006 break;
1007 case DPLL_CTRL1_LINK_RATE_1080:
1008 link_clock = 108000;
1009 break;
1010 case DPLL_CTRL1_LINK_RATE_1350:
1011 link_clock = 135000;
1012 break;
1013 case DPLL_CTRL1_LINK_RATE_1620:
1014 link_clock = 162000;
1015 break;
1016 case DPLL_CTRL1_LINK_RATE_2160:
1017 link_clock = 216000;
1018 break;
1019 case DPLL_CTRL1_LINK_RATE_2700:
1020 link_clock = 270000;
1021 break;
1022 default:
1023 WARN(1, "Unsupported link rate\n");
1024 break;
1025 }
1026 link_clock *= 2;
1027 }
1028
1029 pipe_config->port_clock = link_clock;
1030
1031 ddi_dotclock_get(pipe_config);
1032 }
1033
1034 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1035 struct intel_crtc_state *pipe_config)
1036 {
1037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1038 int link_clock = 0;
1039 u32 val, pll;
1040
1041 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1042 switch (val & PORT_CLK_SEL_MASK) {
1043 case PORT_CLK_SEL_LCPLL_810:
1044 link_clock = 81000;
1045 break;
1046 case PORT_CLK_SEL_LCPLL_1350:
1047 link_clock = 135000;
1048 break;
1049 case PORT_CLK_SEL_LCPLL_2700:
1050 link_clock = 270000;
1051 break;
1052 case PORT_CLK_SEL_WRPLL1:
1053 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1054 break;
1055 case PORT_CLK_SEL_WRPLL2:
1056 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1057 break;
1058 case PORT_CLK_SEL_SPLL:
1059 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1060 if (pll == SPLL_PLL_FREQ_810MHz)
1061 link_clock = 81000;
1062 else if (pll == SPLL_PLL_FREQ_1350MHz)
1063 link_clock = 135000;
1064 else if (pll == SPLL_PLL_FREQ_2700MHz)
1065 link_clock = 270000;
1066 else {
1067 WARN(1, "bad spll freq\n");
1068 return;
1069 }
1070 break;
1071 default:
1072 WARN(1, "bad port clock sel\n");
1073 return;
1074 }
1075
1076 pipe_config->port_clock = link_clock * 2;
1077
1078 ddi_dotclock_get(pipe_config);
1079 }
1080
1081 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1082 enum intel_dpll_id dpll)
1083 {
1084 struct intel_shared_dpll *pll;
1085 struct intel_dpll_hw_state *state;
1086 struct dpll clock;
1087
1088 /* For DDI ports we always use a shared PLL. */
1089 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1090 return 0;
1091
1092 pll = &dev_priv->shared_dplls[dpll];
1093 state = &pll->state.hw_state;
1094
1095 clock.m1 = 2;
1096 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1097 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1098 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1099 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1100 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1101 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1102
1103 return chv_calc_dpll_params(100000, &clock);
1104 }
1105
1106 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1107 struct intel_crtc_state *pipe_config)
1108 {
1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1110 enum port port = intel_ddi_get_encoder_port(encoder);
1111 uint32_t dpll = port;
1112
1113 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1114
1115 ddi_dotclock_get(pipe_config);
1116 }
1117
1118 void intel_ddi_clock_get(struct intel_encoder *encoder,
1119 struct intel_crtc_state *pipe_config)
1120 {
1121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1122
1123 if (INTEL_GEN(dev_priv) <= 8)
1124 hsw_ddi_clock_get(encoder, pipe_config);
1125 else if (IS_GEN9_BC(dev_priv))
1126 skl_ddi_clock_get(encoder, pipe_config);
1127 else if (IS_GEN9_LP(dev_priv))
1128 bxt_ddi_clock_get(encoder, pipe_config);
1129 }
1130
1131 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1132 {
1133 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1134 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1135 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1136 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1137 int type = encoder->type;
1138 uint32_t temp;
1139
1140 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1141 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1142
1143 temp = TRANS_MSA_SYNC_CLK;
1144 switch (crtc_state->pipe_bpp) {
1145 case 18:
1146 temp |= TRANS_MSA_6_BPC;
1147 break;
1148 case 24:
1149 temp |= TRANS_MSA_8_BPC;
1150 break;
1151 case 30:
1152 temp |= TRANS_MSA_10_BPC;
1153 break;
1154 case 36:
1155 temp |= TRANS_MSA_12_BPC;
1156 break;
1157 default:
1158 BUG();
1159 }
1160 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1161 }
1162 }
1163
1164 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1165 bool state)
1166 {
1167 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1168 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1169 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1170 uint32_t temp;
1171 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1172 if (state == true)
1173 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1174 else
1175 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1176 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1177 }
1178
1179 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1180 {
1181 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1182 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1183 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1184 enum pipe pipe = crtc->pipe;
1185 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1186 enum port port = intel_ddi_get_encoder_port(encoder);
1187 int type = encoder->type;
1188 uint32_t temp;
1189
1190 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1191 temp = TRANS_DDI_FUNC_ENABLE;
1192 temp |= TRANS_DDI_SELECT_PORT(port);
1193
1194 switch (crtc_state->pipe_bpp) {
1195 case 18:
1196 temp |= TRANS_DDI_BPC_6;
1197 break;
1198 case 24:
1199 temp |= TRANS_DDI_BPC_8;
1200 break;
1201 case 30:
1202 temp |= TRANS_DDI_BPC_10;
1203 break;
1204 case 36:
1205 temp |= TRANS_DDI_BPC_12;
1206 break;
1207 default:
1208 BUG();
1209 }
1210
1211 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1212 temp |= TRANS_DDI_PVSYNC;
1213 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1214 temp |= TRANS_DDI_PHSYNC;
1215
1216 if (cpu_transcoder == TRANSCODER_EDP) {
1217 switch (pipe) {
1218 case PIPE_A:
1219 /* On Haswell, can only use the always-on power well for
1220 * eDP when not using the panel fitter, and when not
1221 * using motion blur mitigation (which we don't
1222 * support). */
1223 if (IS_HASWELL(dev_priv) &&
1224 (crtc_state->pch_pfit.enabled ||
1225 crtc_state->pch_pfit.force_thru))
1226 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1227 else
1228 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1229 break;
1230 case PIPE_B:
1231 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1232 break;
1233 case PIPE_C:
1234 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1235 break;
1236 default:
1237 BUG();
1238 break;
1239 }
1240 }
1241
1242 if (type == INTEL_OUTPUT_HDMI) {
1243 if (crtc_state->has_hdmi_sink)
1244 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1245 else
1246 temp |= TRANS_DDI_MODE_SELECT_DVI;
1247
1248 if (crtc_state->hdmi_scrambling)
1249 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1250 if (crtc_state->hdmi_high_tmds_clock_ratio)
1251 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1252 } else if (type == INTEL_OUTPUT_ANALOG) {
1253 temp |= TRANS_DDI_MODE_SELECT_FDI;
1254 temp |= (crtc_state->fdi_lanes - 1) << 1;
1255 } else if (type == INTEL_OUTPUT_DP ||
1256 type == INTEL_OUTPUT_EDP) {
1257 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1258 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1259 } else if (type == INTEL_OUTPUT_DP_MST) {
1260 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1261 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1262 } else {
1263 WARN(1, "Invalid encoder type %d for pipe %c\n",
1264 encoder->type, pipe_name(pipe));
1265 }
1266
1267 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1268 }
1269
1270 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1271 enum transcoder cpu_transcoder)
1272 {
1273 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1274 uint32_t val = I915_READ(reg);
1275
1276 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1277 val |= TRANS_DDI_PORT_NONE;
1278 I915_WRITE(reg, val);
1279 }
1280
1281 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1282 {
1283 struct drm_device *dev = intel_connector->base.dev;
1284 struct drm_i915_private *dev_priv = to_i915(dev);
1285 struct intel_encoder *encoder = intel_connector->encoder;
1286 int type = intel_connector->base.connector_type;
1287 enum port port = intel_ddi_get_encoder_port(encoder);
1288 enum pipe pipe = 0;
1289 enum transcoder cpu_transcoder;
1290 uint32_t tmp;
1291 bool ret;
1292
1293 if (!intel_display_power_get_if_enabled(dev_priv,
1294 encoder->power_domain))
1295 return false;
1296
1297 if (!encoder->get_hw_state(encoder, &pipe)) {
1298 ret = false;
1299 goto out;
1300 }
1301
1302 if (port == PORT_A)
1303 cpu_transcoder = TRANSCODER_EDP;
1304 else
1305 cpu_transcoder = (enum transcoder) pipe;
1306
1307 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1308
1309 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1310 case TRANS_DDI_MODE_SELECT_HDMI:
1311 case TRANS_DDI_MODE_SELECT_DVI:
1312 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1313 break;
1314
1315 case TRANS_DDI_MODE_SELECT_DP_SST:
1316 ret = type == DRM_MODE_CONNECTOR_eDP ||
1317 type == DRM_MODE_CONNECTOR_DisplayPort;
1318 break;
1319
1320 case TRANS_DDI_MODE_SELECT_DP_MST:
1321 /* if the transcoder is in MST state then
1322 * connector isn't connected */
1323 ret = false;
1324 break;
1325
1326 case TRANS_DDI_MODE_SELECT_FDI:
1327 ret = type == DRM_MODE_CONNECTOR_VGA;
1328 break;
1329
1330 default:
1331 ret = false;
1332 break;
1333 }
1334
1335 out:
1336 intel_display_power_put(dev_priv, encoder->power_domain);
1337
1338 return ret;
1339 }
1340
1341 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1342 enum pipe *pipe)
1343 {
1344 struct drm_device *dev = encoder->base.dev;
1345 struct drm_i915_private *dev_priv = to_i915(dev);
1346 enum port port = intel_ddi_get_encoder_port(encoder);
1347 u32 tmp;
1348 int i;
1349 bool ret;
1350
1351 if (!intel_display_power_get_if_enabled(dev_priv,
1352 encoder->power_domain))
1353 return false;
1354
1355 ret = false;
1356
1357 tmp = I915_READ(DDI_BUF_CTL(port));
1358
1359 if (!(tmp & DDI_BUF_CTL_ENABLE))
1360 goto out;
1361
1362 if (port == PORT_A) {
1363 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1364
1365 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1366 case TRANS_DDI_EDP_INPUT_A_ON:
1367 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1368 *pipe = PIPE_A;
1369 break;
1370 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1371 *pipe = PIPE_B;
1372 break;
1373 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1374 *pipe = PIPE_C;
1375 break;
1376 }
1377
1378 ret = true;
1379
1380 goto out;
1381 }
1382
1383 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1384 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1385
1386 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1387 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1388 TRANS_DDI_MODE_SELECT_DP_MST)
1389 goto out;
1390
1391 *pipe = i;
1392 ret = true;
1393
1394 goto out;
1395 }
1396 }
1397
1398 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1399
1400 out:
1401 if (ret && IS_GEN9_LP(dev_priv)) {
1402 tmp = I915_READ(BXT_PHY_CTL(port));
1403 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1404 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1405 DRM_ERROR("Port %c enabled but PHY powered down? "
1406 "(PHY_CTL %08x)\n", port_name(port), tmp);
1407 }
1408
1409 intel_display_power_put(dev_priv, encoder->power_domain);
1410
1411 return ret;
1412 }
1413
1414 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1415 {
1416 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1417 enum pipe pipe;
1418
1419 if (intel_ddi_get_hw_state(encoder, &pipe))
1420 return BIT_ULL(dig_port->ddi_io_power_domain);
1421
1422 return 0;
1423 }
1424
1425 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1426 {
1427 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1430 enum port port = intel_ddi_get_encoder_port(encoder);
1431 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1432
1433 if (cpu_transcoder != TRANSCODER_EDP)
1434 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1435 TRANS_CLK_SEL_PORT(port));
1436 }
1437
1438 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1439 {
1440 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1441 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1442
1443 if (cpu_transcoder != TRANSCODER_EDP)
1444 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1445 TRANS_CLK_SEL_DISABLED);
1446 }
1447
1448 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1449 enum port port, uint8_t iboost)
1450 {
1451 u32 tmp;
1452
1453 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1454 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1455 if (iboost)
1456 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1457 else
1458 tmp |= BALANCE_LEG_DISABLE(port);
1459 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1460 }
1461
1462 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1463 {
1464 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1465 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1466 enum port port = intel_dig_port->port;
1467 int type = encoder->type;
1468 const struct ddi_buf_trans *ddi_translations;
1469 uint8_t iboost;
1470 uint8_t dp_iboost, hdmi_iboost;
1471 int n_entries;
1472
1473 /* VBT may override standard boost values */
1474 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1475 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1476
1477 if (type == INTEL_OUTPUT_DP) {
1478 if (dp_iboost) {
1479 iboost = dp_iboost;
1480 } else {
1481 if (IS_KABYLAKE(dev_priv))
1482 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1483 &n_entries);
1484 else
1485 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1486 &n_entries);
1487 iboost = ddi_translations[level].i_boost;
1488 }
1489 } else if (type == INTEL_OUTPUT_EDP) {
1490 if (dp_iboost) {
1491 iboost = dp_iboost;
1492 } else {
1493 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1494
1495 if (WARN_ON(port != PORT_A &&
1496 port != PORT_E && n_entries > 9))
1497 n_entries = 9;
1498
1499 iboost = ddi_translations[level].i_boost;
1500 }
1501 } else if (type == INTEL_OUTPUT_HDMI) {
1502 if (hdmi_iboost) {
1503 iboost = hdmi_iboost;
1504 } else {
1505 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1506 iboost = ddi_translations[level].i_boost;
1507 }
1508 } else {
1509 return;
1510 }
1511
1512 /* Make sure that the requested I_boost is valid */
1513 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1514 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1515 return;
1516 }
1517
1518 _skl_ddi_set_iboost(dev_priv, port, iboost);
1519
1520 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1521 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1522 }
1523
1524 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1525 u32 level, enum port port, int type)
1526 {
1527 const struct bxt_ddi_buf_trans *ddi_translations;
1528 u32 n_entries, i;
1529
1530 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1531 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1532 ddi_translations = bxt_ddi_translations_edp;
1533 } else if (type == INTEL_OUTPUT_DP
1534 || type == INTEL_OUTPUT_EDP) {
1535 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1536 ddi_translations = bxt_ddi_translations_dp;
1537 } else if (type == INTEL_OUTPUT_HDMI) {
1538 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1539 ddi_translations = bxt_ddi_translations_hdmi;
1540 } else {
1541 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1542 type);
1543 return;
1544 }
1545
1546 /* Check if default value has to be used */
1547 if (level >= n_entries ||
1548 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1549 for (i = 0; i < n_entries; i++) {
1550 if (ddi_translations[i].default_index) {
1551 level = i;
1552 break;
1553 }
1554 }
1555 }
1556
1557 bxt_ddi_phy_set_signal_level(dev_priv, port,
1558 ddi_translations[level].margin,
1559 ddi_translations[level].scale,
1560 ddi_translations[level].enable,
1561 ddi_translations[level].deemphasis);
1562 }
1563
1564 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1565 {
1566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1567 int n_entries;
1568
1569 if (encoder->type == INTEL_OUTPUT_EDP)
1570 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1571 else
1572 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1573
1574 if (WARN_ON(n_entries < 1))
1575 n_entries = 1;
1576 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1577 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1578
1579 return index_to_dp_signal_levels[n_entries - 1] &
1580 DP_TRAIN_VOLTAGE_SWING_MASK;
1581 }
1582
1583 static uint32_t translate_signal_level(int signal_levels)
1584 {
1585 int i;
1586
1587 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1588 if (index_to_dp_signal_levels[i] == signal_levels)
1589 return i;
1590 }
1591
1592 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1593 signal_levels);
1594
1595 return 0;
1596 }
1597
1598 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1599 {
1600 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1601 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1602 struct intel_encoder *encoder = &dport->base;
1603 uint8_t train_set = intel_dp->train_set[0];
1604 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1605 DP_TRAIN_PRE_EMPHASIS_MASK);
1606 enum port port = dport->port;
1607 uint32_t level;
1608
1609 level = translate_signal_level(signal_levels);
1610
1611 if (IS_GEN9_BC(dev_priv))
1612 skl_ddi_set_iboost(encoder, level);
1613 else if (IS_GEN9_LP(dev_priv))
1614 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1615
1616 return DDI_BUF_TRANS_SELECT(level);
1617 }
1618
1619 static void intel_ddi_clk_select(struct intel_encoder *encoder,
1620 struct intel_shared_dpll *pll)
1621 {
1622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1623 enum port port = intel_ddi_get_encoder_port(encoder);
1624 uint32_t val;
1625
1626 if (WARN_ON(!pll))
1627 return;
1628
1629 if (IS_CANNONLAKE(dev_priv)) {
1630 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
1631 val = I915_READ(DPCLKA_CFGCR0);
1632 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
1633 I915_WRITE(DPCLKA_CFGCR0, val);
1634
1635 /*
1636 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
1637 * This step and the step before must be done with separate
1638 * register writes.
1639 */
1640 val = I915_READ(DPCLKA_CFGCR0);
1641 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
1642 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
1643 I915_WRITE(DPCLKA_CFGCR0, val);
1644 } else if (IS_GEN9_BC(dev_priv)) {
1645 /* DDI -> PLL mapping */
1646 val = I915_READ(DPLL_CTRL2);
1647
1648 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1649 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1650 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
1651 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1652
1653 I915_WRITE(DPLL_CTRL2, val);
1654
1655 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1656 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1657 }
1658 }
1659
1660 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
1661 int link_rate, uint32_t lane_count,
1662 struct intel_shared_dpll *pll,
1663 bool link_mst)
1664 {
1665 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1666 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1667 enum port port = intel_ddi_get_encoder_port(encoder);
1668 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1669
1670 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
1671
1672 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
1673 link_mst);
1674 if (encoder->type == INTEL_OUTPUT_EDP)
1675 intel_edp_panel_on(intel_dp);
1676
1677 intel_ddi_clk_select(encoder, pll);
1678
1679 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
1680
1681 intel_prepare_dp_ddi_buffers(encoder);
1682 intel_ddi_init_dp_buf_reg(encoder);
1683 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1684 intel_dp_start_link_train(intel_dp);
1685 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
1686 intel_dp_stop_link_train(intel_dp);
1687 }
1688
1689 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
1690 bool has_hdmi_sink,
1691 const struct intel_crtc_state *crtc_state,
1692 const struct drm_connector_state *conn_state,
1693 struct intel_shared_dpll *pll)
1694 {
1695 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1697 struct drm_encoder *drm_encoder = &encoder->base;
1698 enum port port = intel_ddi_get_encoder_port(encoder);
1699 int level = intel_ddi_hdmi_level(dev_priv, port);
1700 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1701
1702 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1703 intel_ddi_clk_select(encoder, pll);
1704
1705 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
1706
1707 intel_prepare_hdmi_ddi_buffers(encoder);
1708 if (IS_GEN9_BC(dev_priv))
1709 skl_ddi_set_iboost(encoder, level);
1710 else if (IS_GEN9_LP(dev_priv))
1711 bxt_ddi_vswing_sequence(dev_priv, level, port,
1712 INTEL_OUTPUT_HDMI);
1713
1714 intel_hdmi->set_infoframes(drm_encoder,
1715 has_hdmi_sink,
1716 crtc_state, conn_state);
1717 }
1718
1719 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
1720 struct intel_crtc_state *pipe_config,
1721 struct drm_connector_state *conn_state)
1722 {
1723 int type = encoder->type;
1724
1725 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1726 intel_ddi_pre_enable_dp(encoder,
1727 pipe_config->port_clock,
1728 pipe_config->lane_count,
1729 pipe_config->shared_dpll,
1730 intel_crtc_has_type(pipe_config,
1731 INTEL_OUTPUT_DP_MST));
1732 }
1733 if (type == INTEL_OUTPUT_HDMI) {
1734 intel_ddi_pre_enable_hdmi(encoder,
1735 pipe_config->has_hdmi_sink,
1736 pipe_config, conn_state,
1737 pipe_config->shared_dpll);
1738 }
1739 }
1740
1741 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
1742 struct intel_crtc_state *old_crtc_state,
1743 struct drm_connector_state *old_conn_state)
1744 {
1745 struct drm_encoder *encoder = &intel_encoder->base;
1746 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1747 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1748 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1749 struct intel_dp *intel_dp = NULL;
1750 int type = intel_encoder->type;
1751 uint32_t val;
1752 bool wait = false;
1753
1754 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
1755
1756 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1757 intel_dp = enc_to_intel_dp(encoder);
1758 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1759 }
1760
1761 val = I915_READ(DDI_BUF_CTL(port));
1762 if (val & DDI_BUF_CTL_ENABLE) {
1763 val &= ~DDI_BUF_CTL_ENABLE;
1764 I915_WRITE(DDI_BUF_CTL(port), val);
1765 wait = true;
1766 }
1767
1768 val = I915_READ(DP_TP_CTL(port));
1769 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1770 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1771 I915_WRITE(DP_TP_CTL(port), val);
1772
1773 if (wait)
1774 intel_wait_ddi_buf_idle(dev_priv, port);
1775
1776 if (intel_dp) {
1777 intel_edp_panel_vdd_on(intel_dp);
1778 intel_edp_panel_off(intel_dp);
1779 }
1780
1781 if (dig_port)
1782 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
1783
1784 if (IS_CANNONLAKE(dev_priv))
1785 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
1786 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
1787 else if (IS_GEN9_BC(dev_priv))
1788 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1789 DPLL_CTRL2_DDI_CLK_OFF(port)));
1790 else if (INTEL_GEN(dev_priv) < 9)
1791 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1792
1793 if (type == INTEL_OUTPUT_HDMI) {
1794 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1795
1796 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1797 }
1798 }
1799
1800 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
1801 struct intel_crtc_state *old_crtc_state,
1802 struct drm_connector_state *old_conn_state)
1803 {
1804 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1805 uint32_t val;
1806
1807 /*
1808 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
1809 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
1810 * step 13 is the correct place for it. Step 18 is where it was
1811 * originally before the BUN.
1812 */
1813 val = I915_READ(FDI_RX_CTL(PIPE_A));
1814 val &= ~FDI_RX_ENABLE;
1815 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1816
1817 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
1818
1819 val = I915_READ(FDI_RX_MISC(PIPE_A));
1820 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1821 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1822 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1823
1824 val = I915_READ(FDI_RX_CTL(PIPE_A));
1825 val &= ~FDI_PCDCLK;
1826 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1827
1828 val = I915_READ(FDI_RX_CTL(PIPE_A));
1829 val &= ~FDI_RX_PLL_ENABLE;
1830 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1831 }
1832
1833 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
1834 struct intel_crtc_state *pipe_config,
1835 struct drm_connector_state *conn_state)
1836 {
1837 struct drm_encoder *encoder = &intel_encoder->base;
1838 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1839 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1840 int type = intel_encoder->type;
1841
1842 if (type == INTEL_OUTPUT_HDMI) {
1843 struct intel_digital_port *intel_dig_port =
1844 enc_to_dig_port(encoder);
1845 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
1846 bool scrambling = pipe_config->hdmi_scrambling;
1847
1848 intel_hdmi_handle_sink_scrambling(intel_encoder,
1849 conn_state->connector,
1850 clock_ratio, scrambling);
1851
1852 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1853 * are ignored so nothing special needs to be done besides
1854 * enabling the port.
1855 */
1856 I915_WRITE(DDI_BUF_CTL(port),
1857 intel_dig_port->saved_port_bits |
1858 DDI_BUF_CTL_ENABLE);
1859 } else if (type == INTEL_OUTPUT_EDP) {
1860 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1861
1862 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
1863 intel_dp_stop_link_train(intel_dp);
1864
1865 intel_edp_backlight_on(pipe_config, conn_state);
1866 intel_psr_enable(intel_dp);
1867 intel_edp_drrs_enable(intel_dp, pipe_config);
1868 }
1869
1870 if (pipe_config->has_audio)
1871 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
1872 }
1873
1874 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
1875 struct intel_crtc_state *old_crtc_state,
1876 struct drm_connector_state *old_conn_state)
1877 {
1878 struct drm_encoder *encoder = &intel_encoder->base;
1879 int type = intel_encoder->type;
1880
1881 if (old_crtc_state->has_audio)
1882 intel_audio_codec_disable(intel_encoder);
1883
1884 if (type == INTEL_OUTPUT_HDMI) {
1885 intel_hdmi_handle_sink_scrambling(intel_encoder,
1886 old_conn_state->connector,
1887 false, false);
1888 }
1889
1890 if (type == INTEL_OUTPUT_EDP) {
1891 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1892
1893 intel_edp_drrs_disable(intel_dp, old_crtc_state);
1894 intel_psr_disable(intel_dp);
1895 intel_edp_backlight_off(old_conn_state);
1896 }
1897 }
1898
1899 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
1900 struct intel_crtc_state *pipe_config,
1901 struct drm_connector_state *conn_state)
1902 {
1903 uint8_t mask = pipe_config->lane_lat_optim_mask;
1904
1905 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
1906 }
1907
1908 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
1909 {
1910 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1911 struct drm_i915_private *dev_priv =
1912 to_i915(intel_dig_port->base.base.dev);
1913 enum port port = intel_dig_port->port;
1914 uint32_t val;
1915 bool wait = false;
1916
1917 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1918 val = I915_READ(DDI_BUF_CTL(port));
1919 if (val & DDI_BUF_CTL_ENABLE) {
1920 val &= ~DDI_BUF_CTL_ENABLE;
1921 I915_WRITE(DDI_BUF_CTL(port), val);
1922 wait = true;
1923 }
1924
1925 val = I915_READ(DP_TP_CTL(port));
1926 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1927 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1928 I915_WRITE(DP_TP_CTL(port), val);
1929 POSTING_READ(DP_TP_CTL(port));
1930
1931 if (wait)
1932 intel_wait_ddi_buf_idle(dev_priv, port);
1933 }
1934
1935 val = DP_TP_CTL_ENABLE |
1936 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1937 if (intel_dp->link_mst)
1938 val |= DP_TP_CTL_MODE_MST;
1939 else {
1940 val |= DP_TP_CTL_MODE_SST;
1941 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1942 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1943 }
1944 I915_WRITE(DP_TP_CTL(port), val);
1945 POSTING_READ(DP_TP_CTL(port));
1946
1947 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1948 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1949 POSTING_READ(DDI_BUF_CTL(port));
1950
1951 udelay(600);
1952 }
1953
1954 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1955 struct intel_crtc *intel_crtc)
1956 {
1957 u32 temp;
1958
1959 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1960 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1961 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
1962 return true;
1963 }
1964 return false;
1965 }
1966
1967 void intel_ddi_get_config(struct intel_encoder *encoder,
1968 struct intel_crtc_state *pipe_config)
1969 {
1970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1971 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1972 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1973 struct intel_hdmi *intel_hdmi;
1974 u32 temp, flags = 0;
1975
1976 /* XXX: DSI transcoder paranoia */
1977 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
1978 return;
1979
1980 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1981 if (temp & TRANS_DDI_PHSYNC)
1982 flags |= DRM_MODE_FLAG_PHSYNC;
1983 else
1984 flags |= DRM_MODE_FLAG_NHSYNC;
1985 if (temp & TRANS_DDI_PVSYNC)
1986 flags |= DRM_MODE_FLAG_PVSYNC;
1987 else
1988 flags |= DRM_MODE_FLAG_NVSYNC;
1989
1990 pipe_config->base.adjusted_mode.flags |= flags;
1991
1992 switch (temp & TRANS_DDI_BPC_MASK) {
1993 case TRANS_DDI_BPC_6:
1994 pipe_config->pipe_bpp = 18;
1995 break;
1996 case TRANS_DDI_BPC_8:
1997 pipe_config->pipe_bpp = 24;
1998 break;
1999 case TRANS_DDI_BPC_10:
2000 pipe_config->pipe_bpp = 30;
2001 break;
2002 case TRANS_DDI_BPC_12:
2003 pipe_config->pipe_bpp = 36;
2004 break;
2005 default:
2006 break;
2007 }
2008
2009 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2010 case TRANS_DDI_MODE_SELECT_HDMI:
2011 pipe_config->has_hdmi_sink = true;
2012 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2013
2014 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2015 pipe_config->has_infoframe = true;
2016
2017 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2018 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2019 pipe_config->hdmi_scrambling = true;
2020 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2021 pipe_config->hdmi_high_tmds_clock_ratio = true;
2022 /* fall through */
2023 case TRANS_DDI_MODE_SELECT_DVI:
2024 pipe_config->lane_count = 4;
2025 break;
2026 case TRANS_DDI_MODE_SELECT_FDI:
2027 break;
2028 case TRANS_DDI_MODE_SELECT_DP_SST:
2029 case TRANS_DDI_MODE_SELECT_DP_MST:
2030 pipe_config->lane_count =
2031 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2032 intel_dp_get_m_n(intel_crtc, pipe_config);
2033 break;
2034 default:
2035 break;
2036 }
2037
2038 pipe_config->has_audio =
2039 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2040
2041 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2042 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2043 /*
2044 * This is a big fat ugly hack.
2045 *
2046 * Some machines in UEFI boot mode provide us a VBT that has 18
2047 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2048 * unknown we fail to light up. Yet the same BIOS boots up with
2049 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2050 * max, not what it tells us to use.
2051 *
2052 * Note: This will still be broken if the eDP panel is not lit
2053 * up by the BIOS, and thus we can't get the mode at module
2054 * load.
2055 */
2056 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2057 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2058 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2059 }
2060
2061 intel_ddi_clock_get(encoder, pipe_config);
2062
2063 if (IS_GEN9_LP(dev_priv))
2064 pipe_config->lane_lat_optim_mask =
2065 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2066 }
2067
2068 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2069 struct intel_crtc_state *pipe_config,
2070 struct drm_connector_state *conn_state)
2071 {
2072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2073 int type = encoder->type;
2074 int port = intel_ddi_get_encoder_port(encoder);
2075 int ret;
2076
2077 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2078
2079 if (port == PORT_A)
2080 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2081
2082 if (type == INTEL_OUTPUT_HDMI)
2083 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2084 else
2085 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2086
2087 if (IS_GEN9_LP(dev_priv) && ret)
2088 pipe_config->lane_lat_optim_mask =
2089 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2090 pipe_config->lane_count);
2091
2092 return ret;
2093
2094 }
2095
2096 static const struct drm_encoder_funcs intel_ddi_funcs = {
2097 .reset = intel_dp_encoder_reset,
2098 .destroy = intel_dp_encoder_destroy,
2099 };
2100
2101 static struct intel_connector *
2102 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2103 {
2104 struct intel_connector *connector;
2105 enum port port = intel_dig_port->port;
2106
2107 connector = intel_connector_alloc();
2108 if (!connector)
2109 return NULL;
2110
2111 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2112 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2113 kfree(connector);
2114 return NULL;
2115 }
2116
2117 return connector;
2118 }
2119
2120 static struct intel_connector *
2121 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2122 {
2123 struct intel_connector *connector;
2124 enum port port = intel_dig_port->port;
2125
2126 connector = intel_connector_alloc();
2127 if (!connector)
2128 return NULL;
2129
2130 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2131 intel_hdmi_init_connector(intel_dig_port, connector);
2132
2133 return connector;
2134 }
2135
2136 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2137 {
2138 struct intel_digital_port *intel_dig_port;
2139 struct intel_encoder *intel_encoder;
2140 struct drm_encoder *encoder;
2141 bool init_hdmi, init_dp, init_lspcon = false;
2142 int max_lanes;
2143
2144 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2145 switch (port) {
2146 case PORT_A:
2147 max_lanes = 4;
2148 break;
2149 case PORT_E:
2150 max_lanes = 0;
2151 break;
2152 default:
2153 max_lanes = 4;
2154 break;
2155 }
2156 } else {
2157 switch (port) {
2158 case PORT_A:
2159 max_lanes = 2;
2160 break;
2161 case PORT_E:
2162 max_lanes = 2;
2163 break;
2164 default:
2165 max_lanes = 4;
2166 break;
2167 }
2168 }
2169
2170 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2171 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2172 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2173
2174 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2175 /*
2176 * Lspcon device needs to be driven with DP connector
2177 * with special detection sequence. So make sure DP
2178 * is initialized before lspcon.
2179 */
2180 init_dp = true;
2181 init_lspcon = true;
2182 init_hdmi = false;
2183 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2184 }
2185
2186 if (!init_dp && !init_hdmi) {
2187 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2188 port_name(port));
2189 return;
2190 }
2191
2192 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2193 if (!intel_dig_port)
2194 return;
2195
2196 intel_encoder = &intel_dig_port->base;
2197 encoder = &intel_encoder->base;
2198
2199 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2200 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2201
2202 intel_encoder->compute_config = intel_ddi_compute_config;
2203 intel_encoder->enable = intel_enable_ddi;
2204 if (IS_GEN9_LP(dev_priv))
2205 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2206 intel_encoder->pre_enable = intel_ddi_pre_enable;
2207 intel_encoder->disable = intel_disable_ddi;
2208 intel_encoder->post_disable = intel_ddi_post_disable;
2209 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2210 intel_encoder->get_config = intel_ddi_get_config;
2211 intel_encoder->suspend = intel_dp_encoder_suspend;
2212 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2213
2214 intel_dig_port->port = port;
2215 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2216 (DDI_BUF_PORT_REVERSAL |
2217 DDI_A_4_LANES);
2218
2219 switch (port) {
2220 case PORT_A:
2221 intel_dig_port->ddi_io_power_domain =
2222 POWER_DOMAIN_PORT_DDI_A_IO;
2223 break;
2224 case PORT_B:
2225 intel_dig_port->ddi_io_power_domain =
2226 POWER_DOMAIN_PORT_DDI_B_IO;
2227 break;
2228 case PORT_C:
2229 intel_dig_port->ddi_io_power_domain =
2230 POWER_DOMAIN_PORT_DDI_C_IO;
2231 break;
2232 case PORT_D:
2233 intel_dig_port->ddi_io_power_domain =
2234 POWER_DOMAIN_PORT_DDI_D_IO;
2235 break;
2236 case PORT_E:
2237 intel_dig_port->ddi_io_power_domain =
2238 POWER_DOMAIN_PORT_DDI_E_IO;
2239 break;
2240 default:
2241 MISSING_CASE(port);
2242 }
2243
2244 /*
2245 * Bspec says that DDI_A_4_LANES is the only supported configuration
2246 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2247 * wasn't lit up at boot. Force this bit on in our internal
2248 * configuration so that we use the proper lane count for our
2249 * calculations.
2250 */
2251 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2252 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2253 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2254 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2255 max_lanes = 4;
2256 }
2257 }
2258
2259 intel_dig_port->max_lanes = max_lanes;
2260
2261 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2262 intel_encoder->power_domain = intel_port_to_power_domain(port);
2263 intel_encoder->port = port;
2264 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2265 intel_encoder->cloneable = 0;
2266
2267 if (init_dp) {
2268 if (!intel_ddi_init_dp_connector(intel_dig_port))
2269 goto err;
2270
2271 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2272 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2273 }
2274
2275 /* In theory we don't need the encoder->type check, but leave it just in
2276 * case we have some really bad VBTs... */
2277 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2278 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2279 goto err;
2280 }
2281
2282 if (init_lspcon) {
2283 if (lspcon_init(intel_dig_port))
2284 /* TODO: handle hdmi info frame part */
2285 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2286 port_name(port));
2287 else
2288 /*
2289 * LSPCON init faied, but DP init was success, so
2290 * lets try to drive as DP++ port.
2291 */
2292 DRM_ERROR("LSPCON init failed on port %c\n",
2293 port_name(port));
2294 }
2295
2296 return;
2297
2298 err:
2299 drm_encoder_cleanup(encoder);
2300 kfree(intel_dig_port);
2301 }
ubuntu-bionic-kernel mirror