]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Rip out legacy page_flip completion/irq handling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev,
124 struct drm_modeset_acquire_ctx *ctx);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126
127 struct intel_limit {
128 struct {
129 int min, max;
130 } dot, vco, n, m, m1, m2, p, p1;
131
132 struct {
133 int dot_limit;
134 int p2_slow, p2_fast;
135 } p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154 {
155 u32 val;
156 int divider;
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 }
170
171 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
172 const char *name, u32 reg)
173 {
174 if (dev_priv->hpll_freq == 0)
175 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
176
177 return vlv_get_cck_clock(dev_priv, name, reg,
178 dev_priv->hpll_freq);
179 }
180
181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 {
183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
184 return;
185
186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
187 CCK_CZ_CLOCK_CONTROL);
188
189 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
190 }
191
192 static inline u32 /* units of 100MHz */
193 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
194 const struct intel_crtc_state *pipe_config)
195 {
196 if (HAS_DDI(dev_priv))
197 return pipe_config->port_clock; /* SPLL */
198 else if (IS_GEN5(dev_priv))
199 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
200 else
201 return 270000;
202 }
203
204 static const struct intel_limit intel_limits_i8xx_dac = {
205 .dot = { .min = 25000, .max = 350000 },
206 .vco = { .min = 908000, .max = 1512000 },
207 .n = { .min = 2, .max = 16 },
208 .m = { .min = 96, .max = 140 },
209 .m1 = { .min = 18, .max = 26 },
210 .m2 = { .min = 6, .max = 16 },
211 .p = { .min = 4, .max = 128 },
212 .p1 = { .min = 2, .max = 33 },
213 .p2 = { .dot_limit = 165000,
214 .p2_slow = 4, .p2_fast = 2 },
215 };
216
217 static const struct intel_limit intel_limits_i8xx_dvo = {
218 .dot = { .min = 25000, .max = 350000 },
219 .vco = { .min = 908000, .max = 1512000 },
220 .n = { .min = 2, .max = 16 },
221 .m = { .min = 96, .max = 140 },
222 .m1 = { .min = 18, .max = 26 },
223 .m2 = { .min = 6, .max = 16 },
224 .p = { .min = 4, .max = 128 },
225 .p1 = { .min = 2, .max = 33 },
226 .p2 = { .dot_limit = 165000,
227 .p2_slow = 4, .p2_fast = 4 },
228 };
229
230 static const struct intel_limit intel_limits_i8xx_lvds = {
231 .dot = { .min = 25000, .max = 350000 },
232 .vco = { .min = 908000, .max = 1512000 },
233 .n = { .min = 2, .max = 16 },
234 .m = { .min = 96, .max = 140 },
235 .m1 = { .min = 18, .max = 26 },
236 .m2 = { .min = 6, .max = 16 },
237 .p = { .min = 4, .max = 128 },
238 .p1 = { .min = 1, .max = 6 },
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 14, .p2_fast = 7 },
241 };
242
243 static const struct intel_limit intel_limits_i9xx_sdvo = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1400000, .max = 2800000 },
246 .n = { .min = 1, .max = 6 },
247 .m = { .min = 70, .max = 120 },
248 .m1 = { .min = 8, .max = 18 },
249 .m2 = { .min = 3, .max = 7 },
250 .p = { .min = 5, .max = 80 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 200000,
253 .p2_slow = 10, .p2_fast = 5 },
254 };
255
256 static const struct intel_limit intel_limits_i9xx_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1400000, .max = 2800000 },
259 .n = { .min = 1, .max = 6 },
260 .m = { .min = 70, .max = 120 },
261 .m1 = { .min = 8, .max = 18 },
262 .m2 = { .min = 3, .max = 7 },
263 .p = { .min = 7, .max = 98 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 7 },
267 };
268
269
270 static const struct intel_limit intel_limits_g4x_sdvo = {
271 .dot = { .min = 25000, .max = 270000 },
272 .vco = { .min = 1750000, .max = 3500000},
273 .n = { .min = 1, .max = 4 },
274 .m = { .min = 104, .max = 138 },
275 .m1 = { .min = 17, .max = 23 },
276 .m2 = { .min = 5, .max = 11 },
277 .p = { .min = 10, .max = 30 },
278 .p1 = { .min = 1, .max = 3},
279 .p2 = { .dot_limit = 270000,
280 .p2_slow = 10,
281 .p2_fast = 10
282 },
283 };
284
285 static const struct intel_limit intel_limits_g4x_hdmi = {
286 .dot = { .min = 22000, .max = 400000 },
287 .vco = { .min = 1750000, .max = 3500000},
288 .n = { .min = 1, .max = 4 },
289 .m = { .min = 104, .max = 138 },
290 .m1 = { .min = 16, .max = 23 },
291 .m2 = { .min = 5, .max = 11 },
292 .p = { .min = 5, .max = 80 },
293 .p1 = { .min = 1, .max = 8},
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 10, .p2_fast = 5 },
296 };
297
298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
299 .dot = { .min = 20000, .max = 115000 },
300 .vco = { .min = 1750000, .max = 3500000 },
301 .n = { .min = 1, .max = 3 },
302 .m = { .min = 104, .max = 138 },
303 .m1 = { .min = 17, .max = 23 },
304 .m2 = { .min = 5, .max = 11 },
305 .p = { .min = 28, .max = 112 },
306 .p1 = { .min = 2, .max = 8 },
307 .p2 = { .dot_limit = 0,
308 .p2_slow = 14, .p2_fast = 14
309 },
310 };
311
312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
313 .dot = { .min = 80000, .max = 224000 },
314 .vco = { .min = 1750000, .max = 3500000 },
315 .n = { .min = 1, .max = 3 },
316 .m = { .min = 104, .max = 138 },
317 .m1 = { .min = 17, .max = 23 },
318 .m2 = { .min = 5, .max = 11 },
319 .p = { .min = 14, .max = 42 },
320 .p1 = { .min = 2, .max = 6 },
321 .p2 = { .dot_limit = 0,
322 .p2_slow = 7, .p2_fast = 7
323 },
324 };
325
326 static const struct intel_limit intel_limits_pineview_sdvo = {
327 .dot = { .min = 20000, .max = 400000},
328 .vco = { .min = 1700000, .max = 3500000 },
329 /* Pineview's Ncounter is a ring counter */
330 .n = { .min = 3, .max = 6 },
331 .m = { .min = 2, .max = 256 },
332 /* Pineview only has one combined m divider, which we treat as m2. */
333 .m1 = { .min = 0, .max = 0 },
334 .m2 = { .min = 0, .max = 254 },
335 .p = { .min = 5, .max = 80 },
336 .p1 = { .min = 1, .max = 8 },
337 .p2 = { .dot_limit = 200000,
338 .p2_slow = 10, .p2_fast = 5 },
339 };
340
341 static const struct intel_limit intel_limits_pineview_lvds = {
342 .dot = { .min = 20000, .max = 400000 },
343 .vco = { .min = 1700000, .max = 3500000 },
344 .n = { .min = 3, .max = 6 },
345 .m = { .min = 2, .max = 256 },
346 .m1 = { .min = 0, .max = 0 },
347 .m2 = { .min = 0, .max = 254 },
348 .p = { .min = 7, .max = 112 },
349 .p1 = { .min = 1, .max = 8 },
350 .p2 = { .dot_limit = 112000,
351 .p2_slow = 14, .p2_fast = 14 },
352 };
353
354 /* Ironlake / Sandybridge
355 *
356 * We calculate clock using (register_value + 2) for N/M1/M2, so here
357 * the range value for them is (actual_value - 2).
358 */
359 static const struct intel_limit intel_limits_ironlake_dac = {
360 .dot = { .min = 25000, .max = 350000 },
361 .vco = { .min = 1760000, .max = 3510000 },
362 .n = { .min = 1, .max = 5 },
363 .m = { .min = 79, .max = 127 },
364 .m1 = { .min = 12, .max = 22 },
365 .m2 = { .min = 5, .max = 9 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 225000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
373 .dot = { .min = 25000, .max = 350000 },
374 .vco = { .min = 1760000, .max = 3510000 },
375 .n = { .min = 1, .max = 3 },
376 .m = { .min = 79, .max = 118 },
377 .m1 = { .min = 12, .max = 22 },
378 .m2 = { .min = 5, .max = 9 },
379 .p = { .min = 28, .max = 112 },
380 .p1 = { .min = 2, .max = 8 },
381 .p2 = { .dot_limit = 225000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
386 .dot = { .min = 25000, .max = 350000 },
387 .vco = { .min = 1760000, .max = 3510000 },
388 .n = { .min = 1, .max = 3 },
389 .m = { .min = 79, .max = 127 },
390 .m1 = { .min = 12, .max = 22 },
391 .m2 = { .min = 5, .max = 9 },
392 .p = { .min = 14, .max = 56 },
393 .p1 = { .min = 2, .max = 8 },
394 .p2 = { .dot_limit = 225000,
395 .p2_slow = 7, .p2_fast = 7 },
396 };
397
398 /* LVDS 100mhz refclk limits. */
399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
400 .dot = { .min = 25000, .max = 350000 },
401 .vco = { .min = 1760000, .max = 3510000 },
402 .n = { .min = 1, .max = 2 },
403 .m = { .min = 79, .max = 126 },
404 .m1 = { .min = 12, .max = 22 },
405 .m2 = { .min = 5, .max = 9 },
406 .p = { .min = 28, .max = 112 },
407 .p1 = { .min = 2, .max = 8 },
408 .p2 = { .dot_limit = 225000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 3 },
416 .m = { .min = 79, .max = 126 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 14, .max = 42 },
420 .p1 = { .min = 2, .max = 6 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 7, .p2_fast = 7 },
423 };
424
425 static const struct intel_limit intel_limits_vlv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
433 .vco = { .min = 4000000, .max = 6000000 },
434 .n = { .min = 1, .max = 7 },
435 .m1 = { .min = 2, .max = 3 },
436 .m2 = { .min = 11, .max = 156 },
437 .p1 = { .min = 2, .max = 3 },
438 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
439 };
440
441 static const struct intel_limit intel_limits_chv = {
442 /*
443 * These are the data rate limits (measured in fast clocks)
444 * since those are the strictest limits we have. The fast
445 * clock and actual rate limits are more relaxed, so checking
446 * them would make no difference.
447 */
448 .dot = { .min = 25000 * 5, .max = 540000 * 5},
449 .vco = { .min = 4800000, .max = 6480000 },
450 .n = { .min = 1, .max = 1 },
451 .m1 = { .min = 2, .max = 2 },
452 .m2 = { .min = 24 << 22, .max = 175 << 22 },
453 .p1 = { .min = 2, .max = 4 },
454 .p2 = { .p2_slow = 1, .p2_fast = 14 },
455 };
456
457 static const struct intel_limit intel_limits_bxt = {
458 /* FIXME: find real dot limits */
459 .dot = { .min = 0, .max = INT_MAX },
460 .vco = { .min = 4800000, .max = 6700000 },
461 .n = { .min = 1, .max = 1 },
462 .m1 = { .min = 2, .max = 2 },
463 /* FIXME: find real m2 limits */
464 .m2 = { .min = 2 << 22, .max = 255 << 22 },
465 .p1 = { .min = 2, .max = 4 },
466 .p2 = { .p2_slow = 1, .p2_fast = 20 },
467 };
468
469 static bool
470 needs_modeset(struct drm_crtc_state *state)
471 {
472 return drm_atomic_crtc_needs_modeset(state);
473 }
474
475 /*
476 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
477 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
478 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
479 * The helpers' return value is the rate of the clock that is fed to the
480 * display engine's pipe which can be the above fast dot clock rate or a
481 * divided-down version of it.
482 */
483 /* m1 is reserved as 0 in Pineview, n is a ring counter */
484 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
485 {
486 clock->m = clock->m2 + 2;
487 clock->p = clock->p1 * clock->p2;
488 if (WARN_ON(clock->n == 0 || clock->p == 0))
489 return 0;
490 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
491 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
492
493 return clock->dot;
494 }
495
496 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
497 {
498 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
499 }
500
501 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
502 {
503 clock->m = i9xx_dpll_compute_m(clock);
504 clock->p = clock->p1 * clock->p2;
505 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
506 return 0;
507 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
508 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
509
510 return clock->dot;
511 }
512
513 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
514 {
515 clock->m = clock->m1 * clock->m2;
516 clock->p = clock->p1 * clock->p2;
517 if (WARN_ON(clock->n == 0 || clock->p == 0))
518 return 0;
519 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
520 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
521
522 return clock->dot / 5;
523 }
524
525 int chv_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = clock->m1 * clock->m2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
532 clock->n << 22);
533 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534
535 return clock->dot / 5;
536 }
537
538 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 /**
540 * Returns whether the given set of divisors are valid for a given refclk with
541 * the given connectors.
542 */
543
544 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
545 const struct intel_limit *limit,
546 const struct dpll *clock)
547 {
548 if (clock->n < limit->n.min || limit->n.max < clock->n)
549 INTELPllInvalid("n out of range\n");
550 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
551 INTELPllInvalid("p1 out of range\n");
552 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
553 INTELPllInvalid("m2 out of range\n");
554 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
555 INTELPllInvalid("m1 out of range\n");
556
557 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
558 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
561
562 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
563 !IS_GEN9_LP(dev_priv)) {
564 if (clock->p < limit->p.min || limit->p.max < clock->p)
565 INTELPllInvalid("p out of range\n");
566 if (clock->m < limit->m.min || limit->m.max < clock->m)
567 INTELPllInvalid("m out of range\n");
568 }
569
570 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
571 INTELPllInvalid("vco out of range\n");
572 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
573 * connector, etc., rather than just a single range.
574 */
575 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
576 INTELPllInvalid("dot out of range\n");
577
578 return true;
579 }
580
581 static int
582 i9xx_select_p2_div(const struct intel_limit *limit,
583 const struct intel_crtc_state *crtc_state,
584 int target)
585 {
586 struct drm_device *dev = crtc_state->base.crtc->dev;
587
588 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 /*
590 * For LVDS just rely on its current settings for dual-channel.
591 * We haven't figured out how to reliably set up different
592 * single/dual channel state, if we even can.
593 */
594 if (intel_is_dual_link_lvds(dev))
595 return limit->p2.p2_fast;
596 else
597 return limit->p2.p2_slow;
598 } else {
599 if (target < limit->p2.dot_limit)
600 return limit->p2.p2_slow;
601 else
602 return limit->p2.p2_fast;
603 }
604 }
605
606 /*
607 * Returns a set of divisors for the desired target clock with the given
608 * refclk, or FALSE. The returned values represent the clock equation:
609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
610 *
611 * Target and reference clocks are specified in kHz.
612 *
613 * If match_clock is provided, then best_clock P divider must match the P
614 * divider from @match_clock used for LVDS downclocking.
615 */
616 static bool
617 i9xx_find_best_dpll(const struct intel_limit *limit,
618 struct intel_crtc_state *crtc_state,
619 int target, int refclk, struct dpll *match_clock,
620 struct dpll *best_clock)
621 {
622 struct drm_device *dev = crtc_state->base.crtc->dev;
623 struct dpll clock;
624 int err = target;
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_calc_dpll_params(refclk, &clock);
643 if (!intel_PLL_is_valid(to_i915(dev),
644 limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 pnv_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 for (clock.n = limit->n.min;
693 clock.n <= limit->n.max; clock.n++) {
694 for (clock.p1 = limit->p1.min;
695 clock.p1 <= limit->p1.max; clock.p1++) {
696 int this_err;
697
698 pnv_calc_dpll_params(refclk, &clock);
699 if (!intel_PLL_is_valid(to_i915(dev),
700 limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 /*
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724 *
725 * Target and reference clocks are specified in kHz.
726 *
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
729 */
730 static bool
731 g4x_find_best_dpll(const struct intel_limit *limit,
732 struct intel_crtc_state *crtc_state,
733 int target, int refclk, struct dpll *match_clock,
734 struct dpll *best_clock)
735 {
736 struct drm_device *dev = crtc_state->base.crtc->dev;
737 struct dpll clock;
738 int max_n;
739 bool found = false;
740 /* approximately equals target * 0.00585 */
741 int err_most = (target >> 8) + (target >> 9);
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_calc_dpll_params(refclk, &clock);
760 if (!intel_PLL_is_valid(to_i915(dev),
761 limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const struct dpll *calculated_clock,
785 const struct dpll *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(to_i915(dev))) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 /*
820 * Returns a set of divisors for the desired target clock with the given
821 * refclk, or FALSE. The returned values represent the clock equation:
822 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 */
824 static bool
825 vlv_find_best_dpll(const struct intel_limit *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, struct dpll *match_clock,
828 struct dpll *best_clock)
829 {
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct dpll clock;
833 unsigned int bestppm = 1000000;
834 /* min update 19.2 MHz */
835 int max_n = min(limit->n.max, refclk / 19200);
836 bool found = false;
837
838 target *= 5; /* fast clock */
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
844 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
845 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
846 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
847 clock.p = clock.p1 * clock.p2;
848 /* based on hardware requirement, prefer bigger m1,m2 values */
849 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
850 unsigned int ppm;
851
852 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
853 refclk * clock.m1);
854
855 vlv_calc_dpll_params(refclk, &clock);
856
857 if (!intel_PLL_is_valid(to_i915(dev),
858 limit,
859 &clock))
860 continue;
861
862 if (!vlv_PLL_is_optimal(dev, target,
863 &clock,
864 best_clock,
865 bestppm, &ppm))
866 continue;
867
868 *best_clock = clock;
869 bestppm = ppm;
870 found = true;
871 }
872 }
873 }
874 }
875
876 return found;
877 }
878
879 /*
880 * Returns a set of divisors for the desired target clock with the given
881 * refclk, or FALSE. The returned values represent the clock equation:
882 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
883 */
884 static bool
885 chv_find_best_dpll(const struct intel_limit *limit,
886 struct intel_crtc_state *crtc_state,
887 int target, int refclk, struct dpll *match_clock,
888 struct dpll *best_clock)
889 {
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
891 struct drm_device *dev = crtc->base.dev;
892 unsigned int best_error_ppm;
893 struct dpll clock;
894 uint64_t m2;
895 int found = false;
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 best_error_ppm = 1000000;
899
900 /*
901 * Based on hardware doc, the n always set to 1, and m1 always
902 * set to 2. If requires to support 200Mhz refclk, we need to
903 * revisit this because n may not 1 anymore.
904 */
905 clock.n = 1, clock.m1 = 2;
906 target *= 5; /* fast clock */
907
908 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
909 for (clock.p2 = limit->p2.p2_fast;
910 clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 unsigned int error_ppm;
913
914 clock.p = clock.p1 * clock.p2;
915
916 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
917 clock.n) << 22, refclk * clock.m1);
918
919 if (m2 > INT_MAX/clock.m1)
920 continue;
921
922 clock.m2 = m2;
923
924 chv_calc_dpll_params(refclk, &clock);
925
926 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
927 continue;
928
929 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
930 best_error_ppm, &error_ppm))
931 continue;
932
933 *best_clock = clock;
934 best_error_ppm = error_ppm;
935 found = true;
936 }
937 }
938
939 return found;
940 }
941
942 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
943 struct dpll *best_clock)
944 {
945 int refclk = 100000;
946 const struct intel_limit *limit = &intel_limits_bxt;
947
948 return chv_find_best_dpll(limit, crtc_state,
949 target_clock, refclk, NULL, best_clock);
950 }
951
952 bool intel_crtc_active(struct intel_crtc *crtc)
953 {
954 /* Be paranoid as we can arrive here with only partial
955 * state retrieved from the hardware during setup.
956 *
957 * We can ditch the adjusted_mode.crtc_clock check as soon
958 * as Haswell has gained clock readout/fastboot support.
959 *
960 * We can ditch the crtc->primary->fb check as soon as we can
961 * properly reconstruct framebuffers.
962 *
963 * FIXME: The intel_crtc->active here should be switched to
964 * crtc->state->active once we have proper CRTC states wired up
965 * for atomic.
966 */
967 return crtc->active && crtc->base.primary->state->fb &&
968 crtc->config->base.adjusted_mode.crtc_clock;
969 }
970
971 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
972 enum pipe pipe)
973 {
974 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
975
976 return crtc->config->cpu_transcoder;
977 }
978
979 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
980 {
981 i915_reg_t reg = PIPEDSL(pipe);
982 u32 line1, line2;
983 u32 line_mask;
984
985 if (IS_GEN2(dev_priv))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 line1 = I915_READ(reg) & line_mask;
991 msleep(5);
992 line2 = I915_READ(reg) & line_mask;
993
994 return line1 == line2;
995 }
996
997 /*
998 * intel_wait_for_pipe_off - wait for pipe to turn off
999 * @crtc: crtc whose pipe to wait for
1000 *
1001 * After disabling a pipe, we can't wait for vblank in the usual way,
1002 * spinning on the vblank interrupt status bit, since we won't actually
1003 * see an interrupt when the pipe is disabled.
1004 *
1005 * On Gen4 and above:
1006 * wait for the pipe register state bit to turn off
1007 *
1008 * Otherwise:
1009 * wait for the display line value to settle (it usually
1010 * ends up stopping at the start of the next frame).
1011 *
1012 */
1013 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 {
1015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1016 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1017 enum pipe pipe = crtc->pipe;
1018
1019 if (INTEL_GEN(dev_priv) >= 4) {
1020 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021
1022 /* Wait for the Pipe State to go off */
1023 if (intel_wait_for_register(dev_priv,
1024 reg, I965_PIPECONF_ACTIVE, 0,
1025 100))
1026 WARN(1, "pipe_off wait timed out\n");
1027 } else {
1028 /* Wait for the display line to settle */
1029 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 }
1032 }
1033
1034 /* Only for pre-ILK configs */
1035 void assert_pll(struct drm_i915_private *dev_priv,
1036 enum pipe pipe, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 val = I915_READ(DPLL(pipe));
1042 cur_state = !!(val & DPLL_VCO_ENABLE);
1043 I915_STATE_WARN(cur_state != state,
1044 "PLL state assertion failure (expected %s, current %s)\n",
1045 onoff(state), onoff(cur_state));
1046 }
1047
1048 /* XXX: the dsi pll is shared between MIPI DSI ports */
1049 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1050 {
1051 u32 val;
1052 bool cur_state;
1053
1054 mutex_lock(&dev_priv->sb_lock);
1055 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1056 mutex_unlock(&dev_priv->sb_lock);
1057
1058 cur_state = val & DSI_PLL_VCO_EN;
1059 I915_STATE_WARN(cur_state != state,
1060 "DSI PLL state assertion failure (expected %s, current %s)\n",
1061 onoff(state), onoff(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 bool cur_state;
1068 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1069 pipe);
1070
1071 if (HAS_DDI(dev_priv)) {
1072 /* DDI does not have a specific FDI_TX register */
1073 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1074 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075 } else {
1076 u32 val = I915_READ(FDI_TX_CTL(pipe));
1077 cur_state = !!(val & FDI_TX_ENABLE);
1078 }
1079 I915_STATE_WARN(cur_state != state,
1080 "FDI TX state assertion failure (expected %s, current %s)\n",
1081 onoff(state), onoff(cur_state));
1082 }
1083 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1084 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085
1086 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 u32 val;
1090 bool cur_state;
1091
1092 val = I915_READ(FDI_RX_CTL(pipe));
1093 cur_state = !!(val & FDI_RX_ENABLE);
1094 I915_STATE_WARN(cur_state != state,
1095 "FDI RX state assertion failure (expected %s, current %s)\n",
1096 onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1099 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100
1101 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1102 enum pipe pipe)
1103 {
1104 u32 val;
1105
1106 /* ILK FDI PLL is always enabled */
1107 if (IS_GEN5(dev_priv))
1108 return;
1109
1110 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1111 if (HAS_DDI(dev_priv))
1112 return;
1113
1114 val = I915_READ(FDI_TX_CTL(pipe));
1115 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1116 }
1117
1118 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1123
1124 val = I915_READ(FDI_RX_CTL(pipe));
1125 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1126 I915_STATE_WARN(cur_state != state,
1127 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1128 onoff(state), onoff(cur_state));
1129 }
1130
1131 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133 i915_reg_t pp_reg;
1134 u32 val;
1135 enum pipe panel_pipe = PIPE_A;
1136 bool locked = true;
1137
1138 if (WARN_ON(HAS_DDI(dev_priv)))
1139 return;
1140
1141 if (HAS_PCH_SPLIT(dev_priv)) {
1142 u32 port_sel;
1143
1144 pp_reg = PP_CONTROL(0);
1145 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146
1147 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1148 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1149 panel_pipe = PIPE_B;
1150 /* XXX: else fix for eDP */
1151 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152 /* presumably write lock depends on pipe, not port select */
1153 pp_reg = PP_CONTROL(pipe);
1154 panel_pipe = pipe;
1155 } else {
1156 pp_reg = PP_CONTROL(0);
1157 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1158 panel_pipe = PIPE_B;
1159 }
1160
1161 val = I915_READ(pp_reg);
1162 if (!(val & PANEL_POWER_ON) ||
1163 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1164 locked = false;
1165
1166 I915_STATE_WARN(panel_pipe == pipe && locked,
1167 "panel assertion failure, pipe %c regs locked\n",
1168 pipe_name(pipe));
1169 }
1170
1171 static void assert_cursor(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1173 {
1174 bool cur_state;
1175
1176 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1177 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178 else
1179 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180
1181 I915_STATE_WARN(cur_state != state,
1182 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1183 pipe_name(pipe), onoff(state), onoff(cur_state));
1184 }
1185 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1186 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187
1188 void assert_pipe(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 bool cur_state;
1192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 pipe);
1194 enum intel_display_power_domain power_domain;
1195
1196 /* we keep both pipes enabled on 830 */
1197 if (IS_I830(dev_priv))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552 int i;
1553
1554 assert_pipe_disabled(dev_priv, crtc->pipe);
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 /* Enable DVO 2x clock on both PLLs if necessary */
1561 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562 /*
1563 * It appears to be important that we don't enable this
1564 * for the current pipe before otherwise configuring the
1565 * PLL. No idea how this should be handled if multiple
1566 * DVO outputs are enabled simultaneosly.
1567 */
1568 dpll |= DPLL_DVO_2X_MODE;
1569 I915_WRITE(DPLL(!crtc->pipe),
1570 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1571 }
1572
1573 /*
1574 * Apparently we need to have VGA mode enabled prior to changing
1575 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1576 * dividers, even though the register value does change.
1577 */
1578 I915_WRITE(reg, 0);
1579
1580 I915_WRITE(reg, dpll);
1581
1582 /* Wait for the clocks to stabilize. */
1583 POSTING_READ(reg);
1584 udelay(150);
1585
1586 if (INTEL_GEN(dev_priv) >= 4) {
1587 I915_WRITE(DPLL_MD(crtc->pipe),
1588 crtc->config->dpll_hw_state.dpll_md);
1589 } else {
1590 /* The pixel multiplier can only be updated once the
1591 * DPLL is enabled and the clocks are stable.
1592 *
1593 * So write it again.
1594 */
1595 I915_WRITE(reg, dpll);
1596 }
1597
1598 /* We do this three times for luck */
1599 for (i = 0; i < 3; i++) {
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150); /* wait for warmup */
1603 }
1604 }
1605
1606 /**
1607 * i9xx_disable_pll - disable a PLL
1608 * @dev_priv: i915 private structure
1609 * @pipe: pipe PLL to disable
1610 *
1611 * Disable the PLL for @pipe, making sure the pipe is off first.
1612 *
1613 * Note! This is for pre-ILK only.
1614 */
1615 static void i9xx_disable_pll(struct intel_crtc *crtc)
1616 {
1617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618 enum pipe pipe = crtc->pipe;
1619
1620 /* Disable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev_priv) &&
1622 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1623 !intel_num_dvo_pipes(dev_priv)) {
1624 I915_WRITE(DPLL(PIPE_B),
1625 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1626 I915_WRITE(DPLL(PIPE_A),
1627 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1628 }
1629
1630 /* Don't disable pipe or pipe PLLs if needed */
1631 if (IS_I830(dev_priv))
1632 return;
1633
1634 /* Make sure the pipe isn't still relying on us */
1635 assert_pipe_disabled(dev_priv, pipe);
1636
1637 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1638 POSTING_READ(DPLL(pipe));
1639 }
1640
1641 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1642 {
1643 u32 val;
1644
1645 /* Make sure the pipe isn't still relying on us */
1646 assert_pipe_disabled(dev_priv, pipe);
1647
1648 val = DPLL_INTEGRATED_REF_CLK_VLV |
1649 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1650 if (pipe != PIPE_A)
1651 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1652
1653 I915_WRITE(DPLL(pipe), val);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660 u32 val;
1661
1662 /* Make sure the pipe isn't still relying on us */
1663 assert_pipe_disabled(dev_priv, pipe);
1664
1665 val = DPLL_SSC_REF_CLK_CHV |
1666 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1667 if (pipe != PIPE_A)
1668 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1669
1670 I915_WRITE(DPLL(pipe), val);
1671 POSTING_READ(DPLL(pipe));
1672
1673 mutex_lock(&dev_priv->sb_lock);
1674
1675 /* Disable 10bit clock to display controller */
1676 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1677 val &= ~DPIO_DCLKP_EN;
1678 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1679
1680 mutex_unlock(&dev_priv->sb_lock);
1681 }
1682
1683 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1684 struct intel_digital_port *dport,
1685 unsigned int expected_mask)
1686 {
1687 u32 port_mask;
1688 i915_reg_t dpll_reg;
1689
1690 switch (dport->port) {
1691 case PORT_B:
1692 port_mask = DPLL_PORTB_READY_MASK;
1693 dpll_reg = DPLL(0);
1694 break;
1695 case PORT_C:
1696 port_mask = DPLL_PORTC_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 expected_mask <<= 4;
1699 break;
1700 case PORT_D:
1701 port_mask = DPLL_PORTD_READY_MASK;
1702 dpll_reg = DPIO_PHY_STATUS;
1703 break;
1704 default:
1705 BUG();
1706 }
1707
1708 if (intel_wait_for_register(dev_priv,
1709 dpll_reg, port_mask, expected_mask,
1710 1000))
1711 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1712 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1713 }
1714
1715 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1716 enum pipe pipe)
1717 {
1718 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1719 pipe);
1720 i915_reg_t reg;
1721 uint32_t val, pipeconf_val;
1722
1723 /* Make sure PCH DPLL is enabled */
1724 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, pipe);
1728 assert_fdi_rx_enabled(dev_priv, pipe);
1729
1730 if (HAS_PCH_CPT(dev_priv)) {
1731 /* Workaround: Set the timing override bit before enabling the
1732 * pch transcoder. */
1733 reg = TRANS_CHICKEN2(pipe);
1734 val = I915_READ(reg);
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(reg, val);
1737 }
1738
1739 reg = PCH_TRANSCONF(pipe);
1740 val = I915_READ(reg);
1741 pipeconf_val = I915_READ(PIPECONF(pipe));
1742
1743 if (HAS_PCH_IBX(dev_priv)) {
1744 /*
1745 * Make the BPC in transcoder be consistent with
1746 * that in pipeconf reg. For HDMI we must use 8bpc
1747 * here for both 8bpc and 12bpc.
1748 */
1749 val &= ~PIPECONF_BPC_MASK;
1750 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1751 val |= PIPECONF_8BPC;
1752 else
1753 val |= pipeconf_val & PIPECONF_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv) &&
1759 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else
1764 val |= TRANS_PROGRESSIVE;
1765
1766 I915_WRITE(reg, val | TRANS_ENABLE);
1767 if (intel_wait_for_register(dev_priv,
1768 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1769 100))
1770 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1771 }
1772
1773 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 enum transcoder cpu_transcoder)
1775 {
1776 u32 val, pipeconf_val;
1777
1778 /* FDI must be feeding us bits for PCH ports */
1779 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1780 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1781
1782 /* Workaround: set timing override bit. */
1783 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1785 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786
1787 val = TRANS_ENABLE;
1788 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1789
1790 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1791 PIPECONF_INTERLACED_ILK)
1792 val |= TRANS_INTERLACED;
1793 else
1794 val |= TRANS_PROGRESSIVE;
1795
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 if (intel_wait_for_register(dev_priv,
1798 LPT_TRANSCONF,
1799 TRANS_STATE_ENABLE,
1800 TRANS_STATE_ENABLE,
1801 100))
1802 DRM_ERROR("Failed to enable PCH transcoder\n");
1803 }
1804
1805 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 i915_reg_t reg;
1809 uint32_t val;
1810
1811 /* FDI relies on the transcoder */
1812 assert_fdi_tx_disabled(dev_priv, pipe);
1813 assert_fdi_rx_disabled(dev_priv, pipe);
1814
1815 /* Ports must be off as well */
1816 assert_pch_ports_disabled(dev_priv, pipe);
1817
1818 reg = PCH_TRANSCONF(pipe);
1819 val = I915_READ(reg);
1820 val &= ~TRANS_ENABLE;
1821 I915_WRITE(reg, val);
1822 /* wait for PCH transcoder off, transcoder state */
1823 if (intel_wait_for_register(dev_priv,
1824 reg, TRANS_STATE_ENABLE, 0,
1825 50))
1826 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1827
1828 if (HAS_PCH_CPT(dev_priv)) {
1829 /* Workaround: Clear the timing override chicken bit again. */
1830 reg = TRANS_CHICKEN2(pipe);
1831 val = I915_READ(reg);
1832 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1833 I915_WRITE(reg, val);
1834 }
1835 }
1836
1837 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1838 {
1839 u32 val;
1840
1841 val = I915_READ(LPT_TRANSCONF);
1842 val &= ~TRANS_ENABLE;
1843 I915_WRITE(LPT_TRANSCONF, val);
1844 /* wait for PCH transcoder off, transcoder state */
1845 if (intel_wait_for_register(dev_priv,
1846 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1847 50))
1848 DRM_ERROR("Failed to disable PCH transcoder\n");
1849
1850 /* Workaround: clear timing override bit. */
1851 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1852 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1853 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1854 }
1855
1856 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1857 {
1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859
1860 WARN_ON(!crtc->config->has_pch_encoder);
1861
1862 if (HAS_PCH_LPT(dev_priv))
1863 return PIPE_A;
1864 else
1865 return crtc->pipe;
1866 }
1867
1868 /**
1869 * intel_enable_pipe - enable a pipe, asserting requirements
1870 * @crtc: crtc responsible for the pipe
1871 *
1872 * Enable @crtc's pipe, making sure that various hardware specific requirements
1873 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1874 */
1875 static void intel_enable_pipe(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = to_i915(dev);
1879 enum pipe pipe = crtc->pipe;
1880 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1881 i915_reg_t reg;
1882 u32 val;
1883
1884 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1885
1886 assert_planes_disabled(dev_priv, pipe);
1887 assert_cursor_disabled(dev_priv, pipe);
1888 assert_sprites_disabled(dev_priv, pipe);
1889
1890 /*
1891 * A pipe without a PLL won't actually be able to drive bits from
1892 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1893 * need the check.
1894 */
1895 if (HAS_GMCH_DISPLAY(dev_priv)) {
1896 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1897 assert_dsi_pll_enabled(dev_priv);
1898 else
1899 assert_pll_enabled(dev_priv, pipe);
1900 } else {
1901 if (crtc->config->has_pch_encoder) {
1902 /* if driving the PCH, we need FDI enabled */
1903 assert_fdi_rx_pll_enabled(dev_priv,
1904 intel_crtc_pch_transcoder(crtc));
1905 assert_fdi_tx_pll_enabled(dev_priv,
1906 (enum pipe) cpu_transcoder);
1907 }
1908 /* FIXME: assert CPU port conditions for SNB+ */
1909 }
1910
1911 reg = PIPECONF(cpu_transcoder);
1912 val = I915_READ(reg);
1913 if (val & PIPECONF_ENABLE) {
1914 /* we keep both pipes enabled on 830 */
1915 WARN_ON(!IS_I830(dev_priv));
1916 return;
1917 }
1918
1919 I915_WRITE(reg, val | PIPECONF_ENABLE);
1920 POSTING_READ(reg);
1921
1922 /*
1923 * Until the pipe starts DSL will read as 0, which would cause
1924 * an apparent vblank timestamp jump, which messes up also the
1925 * frame count when it's derived from the timestamps. So let's
1926 * wait for the pipe to start properly before we call
1927 * drm_crtc_vblank_on()
1928 */
1929 if (dev->max_vblank_count == 0 &&
1930 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1931 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1932 }
1933
1934 /**
1935 * intel_disable_pipe - disable a pipe, asserting requirements
1936 * @crtc: crtc whose pipes is to be disabled
1937 *
1938 * Disable the pipe of @crtc, making sure that various hardware
1939 * specific requirements are met, if applicable, e.g. plane
1940 * disabled, panel fitter off, etc.
1941 *
1942 * Will wait until the pipe has shut down before returning.
1943 */
1944 static void intel_disable_pipe(struct intel_crtc *crtc)
1945 {
1946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1948 enum pipe pipe = crtc->pipe;
1949 i915_reg_t reg;
1950 u32 val;
1951
1952 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1953
1954 /*
1955 * Make sure planes won't keep trying to pump pixels to us,
1956 * or we might hang the display.
1957 */
1958 assert_planes_disabled(dev_priv, pipe);
1959 assert_cursor_disabled(dev_priv, pipe);
1960 assert_sprites_disabled(dev_priv, pipe);
1961
1962 reg = PIPECONF(cpu_transcoder);
1963 val = I915_READ(reg);
1964 if ((val & PIPECONF_ENABLE) == 0)
1965 return;
1966
1967 /*
1968 * Double wide has implications for planes
1969 * so best keep it disabled when not needed.
1970 */
1971 if (crtc->config->double_wide)
1972 val &= ~PIPECONF_DOUBLE_WIDE;
1973
1974 /* Don't disable pipe or pipe PLLs if needed */
1975 if (!IS_I830(dev_priv))
1976 val &= ~PIPECONF_ENABLE;
1977
1978 I915_WRITE(reg, val);
1979 if ((val & PIPECONF_ENABLE) == 0)
1980 intel_wait_for_pipe_off(crtc);
1981 }
1982
1983 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1984 {
1985 return IS_GEN2(dev_priv) ? 2048 : 4096;
1986 }
1987
1988 static unsigned int
1989 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1990 {
1991 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1992 unsigned int cpp = fb->format->cpp[plane];
1993
1994 switch (fb->modifier) {
1995 case DRM_FORMAT_MOD_LINEAR:
1996 return cpp;
1997 case I915_FORMAT_MOD_X_TILED:
1998 if (IS_GEN2(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Y_TILED:
2003 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Yf_TILED:
2008 switch (cpp) {
2009 case 1:
2010 return 64;
2011 case 2:
2012 case 4:
2013 return 128;
2014 case 8:
2015 case 16:
2016 return 256;
2017 default:
2018 MISSING_CASE(cpp);
2019 return cpp;
2020 }
2021 break;
2022 default:
2023 MISSING_CASE(fb->modifier);
2024 return cpp;
2025 }
2026 }
2027
2028 static unsigned int
2029 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2030 {
2031 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2032 return 1;
2033 else
2034 return intel_tile_size(to_i915(fb->dev)) /
2035 intel_tile_width_bytes(fb, plane);
2036 }
2037
2038 /* Return the tile dimensions in pixel units */
2039 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2040 unsigned int *tile_width,
2041 unsigned int *tile_height)
2042 {
2043 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2044 unsigned int cpp = fb->format->cpp[plane];
2045
2046 *tile_width = tile_width_bytes / cpp;
2047 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2048 }
2049
2050 unsigned int
2051 intel_fb_align_height(const struct drm_framebuffer *fb,
2052 int plane, unsigned int height)
2053 {
2054 unsigned int tile_height = intel_tile_height(fb, plane);
2055
2056 return ALIGN(height, tile_height);
2057 }
2058
2059 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2060 {
2061 unsigned int size = 0;
2062 int i;
2063
2064 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2065 size += rot_info->plane[i].width * rot_info->plane[i].height;
2066
2067 return size;
2068 }
2069
2070 static void
2071 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2072 const struct drm_framebuffer *fb,
2073 unsigned int rotation)
2074 {
2075 view->type = I915_GGTT_VIEW_NORMAL;
2076 if (drm_rotation_90_or_270(rotation)) {
2077 view->type = I915_GGTT_VIEW_ROTATED;
2078 view->rotated = to_intel_framebuffer(fb)->rot_info;
2079 }
2080 }
2081
2082 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2083 {
2084 if (IS_I830(dev_priv))
2085 return 16 * 1024;
2086 else if (IS_I85X(dev_priv))
2087 return 256;
2088 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2089 return 32;
2090 else
2091 return 4 * 1024;
2092 }
2093
2094 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2095 {
2096 if (INTEL_INFO(dev_priv)->gen >= 9)
2097 return 256 * 1024;
2098 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2099 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2100 return 128 * 1024;
2101 else if (INTEL_INFO(dev_priv)->gen >= 4)
2102 return 4 * 1024;
2103 else
2104 return 0;
2105 }
2106
2107 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2108 int plane)
2109 {
2110 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2111
2112 /* AUX_DIST needs only 4K alignment */
2113 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2114 return 4096;
2115
2116 switch (fb->modifier) {
2117 case DRM_FORMAT_MOD_LINEAR:
2118 return intel_linear_alignment(dev_priv);
2119 case I915_FORMAT_MOD_X_TILED:
2120 if (INTEL_GEN(dev_priv) >= 9)
2121 return 256 * 1024;
2122 return 0;
2123 case I915_FORMAT_MOD_Y_TILED:
2124 case I915_FORMAT_MOD_Yf_TILED:
2125 return 1 * 1024 * 1024;
2126 default:
2127 MISSING_CASE(fb->modifier);
2128 return 0;
2129 }
2130 }
2131
2132 struct i915_vma *
2133 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2134 {
2135 struct drm_device *dev = fb->dev;
2136 struct drm_i915_private *dev_priv = to_i915(dev);
2137 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2138 struct i915_ggtt_view view;
2139 struct i915_vma *vma;
2140 u32 alignment;
2141
2142 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2143
2144 alignment = intel_surf_alignment(fb, 0);
2145
2146 intel_fill_fb_ggtt_view(&view, fb, rotation);
2147
2148 /* Note that the w/a also requires 64 PTE of padding following the
2149 * bo. We currently fill all unused PTE with the shadow page and so
2150 * we should always have valid PTE following the scanout preventing
2151 * the VT-d warning.
2152 */
2153 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2154 alignment = 256 * 1024;
2155
2156 /*
2157 * Global gtt pte registers are special registers which actually forward
2158 * writes to a chunk of system memory. Which means that there is no risk
2159 * that the register values disappear as soon as we call
2160 * intel_runtime_pm_put(), so it is correct to wrap only the
2161 * pin/unpin/fence and not more.
2162 */
2163 intel_runtime_pm_get(dev_priv);
2164
2165 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2166 if (IS_ERR(vma))
2167 goto err;
2168
2169 if (i915_vma_is_map_and_fenceable(vma)) {
2170 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2171 * fence, whereas 965+ only requires a fence if using
2172 * framebuffer compression. For simplicity, we always, when
2173 * possible, install a fence as the cost is not that onerous.
2174 *
2175 * If we fail to fence the tiled scanout, then either the
2176 * modeset will reject the change (which is highly unlikely as
2177 * the affected systems, all but one, do not have unmappable
2178 * space) or we will not be able to enable full powersaving
2179 * techniques (also likely not to apply due to various limits
2180 * FBC and the like impose on the size of the buffer, which
2181 * presumably we violated anyway with this unmappable buffer).
2182 * Anyway, it is presumably better to stumble onwards with
2183 * something and try to run the system in a "less than optimal"
2184 * mode that matches the user configuration.
2185 */
2186 if (i915_vma_get_fence(vma) == 0)
2187 i915_vma_pin_fence(vma);
2188 }
2189
2190 i915_vma_get(vma);
2191 err:
2192 intel_runtime_pm_put(dev_priv);
2193 return vma;
2194 }
2195
2196 void intel_unpin_fb_vma(struct i915_vma *vma)
2197 {
2198 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2199
2200 i915_vma_unpin_fence(vma);
2201 i915_gem_object_unpin_from_display_plane(vma);
2202 i915_vma_put(vma);
2203 }
2204
2205 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2206 unsigned int rotation)
2207 {
2208 if (drm_rotation_90_or_270(rotation))
2209 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2210 else
2211 return fb->pitches[plane];
2212 }
2213
2214 /*
2215 * Convert the x/y offsets into a linear offset.
2216 * Only valid with 0/180 degree rotation, which is fine since linear
2217 * offset is only used with linear buffers on pre-hsw and tiled buffers
2218 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2219 */
2220 u32 intel_fb_xy_to_linear(int x, int y,
2221 const struct intel_plane_state *state,
2222 int plane)
2223 {
2224 const struct drm_framebuffer *fb = state->base.fb;
2225 unsigned int cpp = fb->format->cpp[plane];
2226 unsigned int pitch = fb->pitches[plane];
2227
2228 return y * pitch + x * cpp;
2229 }
2230
2231 /*
2232 * Add the x/y offsets derived from fb->offsets[] to the user
2233 * specified plane src x/y offsets. The resulting x/y offsets
2234 * specify the start of scanout from the beginning of the gtt mapping.
2235 */
2236 void intel_add_fb_offsets(int *x, int *y,
2237 const struct intel_plane_state *state,
2238 int plane)
2239
2240 {
2241 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2242 unsigned int rotation = state->base.rotation;
2243
2244 if (drm_rotation_90_or_270(rotation)) {
2245 *x += intel_fb->rotated[plane].x;
2246 *y += intel_fb->rotated[plane].y;
2247 } else {
2248 *x += intel_fb->normal[plane].x;
2249 *y += intel_fb->normal[plane].y;
2250 }
2251 }
2252
2253 /*
2254 * Input tile dimensions and pitch must already be
2255 * rotated to match x and y, and in pixel units.
2256 */
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258 unsigned int tile_width,
2259 unsigned int tile_height,
2260 unsigned int tile_size,
2261 unsigned int pitch_tiles,
2262 u32 old_offset,
2263 u32 new_offset)
2264 {
2265 unsigned int pitch_pixels = pitch_tiles * tile_width;
2266 unsigned int tiles;
2267
2268 WARN_ON(old_offset & (tile_size - 1));
2269 WARN_ON(new_offset & (tile_size - 1));
2270 WARN_ON(new_offset > old_offset);
2271
2272 tiles = (old_offset - new_offset) / tile_size;
2273
2274 *y += tiles / pitch_tiles * tile_height;
2275 *x += tiles % pitch_tiles * tile_width;
2276
2277 /* minimize x in case it got needlessly big */
2278 *y += *x / pitch_pixels * tile_height;
2279 *x %= pitch_pixels;
2280
2281 return new_offset;
2282 }
2283
2284 /*
2285 * Adjust the tile offset by moving the difference into
2286 * the x/y offsets.
2287 */
2288 static u32 intel_adjust_tile_offset(int *x, int *y,
2289 const struct intel_plane_state *state, int plane,
2290 u32 old_offset, u32 new_offset)
2291 {
2292 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2293 const struct drm_framebuffer *fb = state->base.fb;
2294 unsigned int cpp = fb->format->cpp[plane];
2295 unsigned int rotation = state->base.rotation;
2296 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2297
2298 WARN_ON(new_offset > old_offset);
2299
2300 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2301 unsigned int tile_size, tile_width, tile_height;
2302 unsigned int pitch_tiles;
2303
2304 tile_size = intel_tile_size(dev_priv);
2305 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2306
2307 if (drm_rotation_90_or_270(rotation)) {
2308 pitch_tiles = pitch / tile_height;
2309 swap(tile_width, tile_height);
2310 } else {
2311 pitch_tiles = pitch / (tile_width * cpp);
2312 }
2313
2314 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2315 tile_size, pitch_tiles,
2316 old_offset, new_offset);
2317 } else {
2318 old_offset += *y * pitch + *x * cpp;
2319
2320 *y = (old_offset - new_offset) / pitch;
2321 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2322 }
2323
2324 return new_offset;
2325 }
2326
2327 /*
2328 * Computes the linear offset to the base tile and adjusts
2329 * x, y. bytes per pixel is assumed to be a power-of-two.
2330 *
2331 * In the 90/270 rotated case, x and y are assumed
2332 * to be already rotated to match the rotated GTT view, and
2333 * pitch is the tile_height aligned framebuffer height.
2334 *
2335 * This function is used when computing the derived information
2336 * under intel_framebuffer, so using any of that information
2337 * here is not allowed. Anything under drm_framebuffer can be
2338 * used. This is why the user has to pass in the pitch since it
2339 * is specified in the rotated orientation.
2340 */
2341 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2342 int *x, int *y,
2343 const struct drm_framebuffer *fb, int plane,
2344 unsigned int pitch,
2345 unsigned int rotation,
2346 u32 alignment)
2347 {
2348 uint64_t fb_modifier = fb->modifier;
2349 unsigned int cpp = fb->format->cpp[plane];
2350 u32 offset, offset_aligned;
2351
2352 if (alignment)
2353 alignment--;
2354
2355 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int tile_rows, tiles, pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2361
2362 if (drm_rotation_90_or_270(rotation)) {
2363 pitch_tiles = pitch / tile_height;
2364 swap(tile_width, tile_height);
2365 } else {
2366 pitch_tiles = pitch / (tile_width * cpp);
2367 }
2368
2369 tile_rows = *y / tile_height;
2370 *y %= tile_height;
2371
2372 tiles = *x / tile_width;
2373 *x %= tile_width;
2374
2375 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2376 offset_aligned = offset & ~alignment;
2377
2378 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2379 tile_size, pitch_tiles,
2380 offset, offset_aligned);
2381 } else {
2382 offset = *y * pitch + *x * cpp;
2383 offset_aligned = offset & ~alignment;
2384
2385 *y = (offset & alignment) / pitch;
2386 *x = ((offset & alignment) - *y * pitch) / cpp;
2387 }
2388
2389 return offset_aligned;
2390 }
2391
2392 u32 intel_compute_tile_offset(int *x, int *y,
2393 const struct intel_plane_state *state,
2394 int plane)
2395 {
2396 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2397 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2398 const struct drm_framebuffer *fb = state->base.fb;
2399 unsigned int rotation = state->base.rotation;
2400 int pitch = intel_fb_pitch(fb, plane, rotation);
2401 u32 alignment;
2402
2403 if (intel_plane->id == PLANE_CURSOR)
2404 alignment = intel_cursor_alignment(dev_priv);
2405 else
2406 alignment = intel_surf_alignment(fb, plane);
2407
2408 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2409 rotation, alignment);
2410 }
2411
2412 /* Convert the fb->offset[] linear offset into x/y offsets */
2413 static void intel_fb_offset_to_xy(int *x, int *y,
2414 const struct drm_framebuffer *fb, int plane)
2415 {
2416 unsigned int cpp = fb->format->cpp[plane];
2417 unsigned int pitch = fb->pitches[plane];
2418 u32 linear_offset = fb->offsets[plane];
2419
2420 *y = linear_offset / pitch;
2421 *x = linear_offset % pitch / cpp;
2422 }
2423
2424 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2425 {
2426 switch (fb_modifier) {
2427 case I915_FORMAT_MOD_X_TILED:
2428 return I915_TILING_X;
2429 case I915_FORMAT_MOD_Y_TILED:
2430 return I915_TILING_Y;
2431 default:
2432 return I915_TILING_NONE;
2433 }
2434 }
2435
2436 static int
2437 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2438 struct drm_framebuffer *fb)
2439 {
2440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2441 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2442 u32 gtt_offset_rotated = 0;
2443 unsigned int max_size = 0;
2444 int i, num_planes = fb->format->num_planes;
2445 unsigned int tile_size = intel_tile_size(dev_priv);
2446
2447 for (i = 0; i < num_planes; i++) {
2448 unsigned int width, height;
2449 unsigned int cpp, size;
2450 u32 offset;
2451 int x, y;
2452
2453 cpp = fb->format->cpp[i];
2454 width = drm_framebuffer_plane_width(fb->width, fb, i);
2455 height = drm_framebuffer_plane_height(fb->height, fb, i);
2456
2457 intel_fb_offset_to_xy(&x, &y, fb, i);
2458
2459 /*
2460 * The fence (if used) is aligned to the start of the object
2461 * so having the framebuffer wrap around across the edge of the
2462 * fenced region doesn't really work. We have no API to configure
2463 * the fence start offset within the object (nor could we probably
2464 * on gen2/3). So it's just easier if we just require that the
2465 * fb layout agrees with the fence layout. We already check that the
2466 * fb stride matches the fence stride elsewhere.
2467 */
2468 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2469 (x + width) * cpp > fb->pitches[i]) {
2470 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2471 i, fb->offsets[i]);
2472 return -EINVAL;
2473 }
2474
2475 /*
2476 * First pixel of the framebuffer from
2477 * the start of the normal gtt mapping.
2478 */
2479 intel_fb->normal[i].x = x;
2480 intel_fb->normal[i].y = y;
2481
2482 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2483 fb, i, fb->pitches[i],
2484 DRM_MODE_ROTATE_0, tile_size);
2485 offset /= tile_size;
2486
2487 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2488 unsigned int tile_width, tile_height;
2489 unsigned int pitch_tiles;
2490 struct drm_rect r;
2491
2492 intel_tile_dims(fb, i, &tile_width, &tile_height);
2493
2494 rot_info->plane[i].offset = offset;
2495 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2496 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2497 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2498
2499 intel_fb->rotated[i].pitch =
2500 rot_info->plane[i].height * tile_height;
2501
2502 /* how many tiles does this plane need */
2503 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2504 /*
2505 * If the plane isn't horizontally tile aligned,
2506 * we need one more tile.
2507 */
2508 if (x != 0)
2509 size++;
2510
2511 /* rotate the x/y offsets to match the GTT view */
2512 r.x1 = x;
2513 r.y1 = y;
2514 r.x2 = x + width;
2515 r.y2 = y + height;
2516 drm_rect_rotate(&r,
2517 rot_info->plane[i].width * tile_width,
2518 rot_info->plane[i].height * tile_height,
2519 DRM_MODE_ROTATE_270);
2520 x = r.x1;
2521 y = r.y1;
2522
2523 /* rotate the tile dimensions to match the GTT view */
2524 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2525 swap(tile_width, tile_height);
2526
2527 /*
2528 * We only keep the x/y offsets, so push all of the
2529 * gtt offset into the x/y offsets.
2530 */
2531 _intel_adjust_tile_offset(&x, &y,
2532 tile_width, tile_height,
2533 tile_size, pitch_tiles,
2534 gtt_offset_rotated * tile_size, 0);
2535
2536 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2537
2538 /*
2539 * First pixel of the framebuffer from
2540 * the start of the rotated gtt mapping.
2541 */
2542 intel_fb->rotated[i].x = x;
2543 intel_fb->rotated[i].y = y;
2544 } else {
2545 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2546 x * cpp, tile_size);
2547 }
2548
2549 /* how many tiles in total needed in the bo */
2550 max_size = max(max_size, offset + size);
2551 }
2552
2553 if (max_size * tile_size > intel_fb->obj->base.size) {
2554 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2555 max_size * tile_size, intel_fb->obj->base.size);
2556 return -EINVAL;
2557 }
2558
2559 return 0;
2560 }
2561
2562 static int i9xx_format_to_fourcc(int format)
2563 {
2564 switch (format) {
2565 case DISPPLANE_8BPP:
2566 return DRM_FORMAT_C8;
2567 case DISPPLANE_BGRX555:
2568 return DRM_FORMAT_XRGB1555;
2569 case DISPPLANE_BGRX565:
2570 return DRM_FORMAT_RGB565;
2571 default:
2572 case DISPPLANE_BGRX888:
2573 return DRM_FORMAT_XRGB8888;
2574 case DISPPLANE_RGBX888:
2575 return DRM_FORMAT_XBGR8888;
2576 case DISPPLANE_BGRX101010:
2577 return DRM_FORMAT_XRGB2101010;
2578 case DISPPLANE_RGBX101010:
2579 return DRM_FORMAT_XBGR2101010;
2580 }
2581 }
2582
2583 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2584 {
2585 switch (format) {
2586 case PLANE_CTL_FORMAT_RGB_565:
2587 return DRM_FORMAT_RGB565;
2588 default:
2589 case PLANE_CTL_FORMAT_XRGB_8888:
2590 if (rgb_order) {
2591 if (alpha)
2592 return DRM_FORMAT_ABGR8888;
2593 else
2594 return DRM_FORMAT_XBGR8888;
2595 } else {
2596 if (alpha)
2597 return DRM_FORMAT_ARGB8888;
2598 else
2599 return DRM_FORMAT_XRGB8888;
2600 }
2601 case PLANE_CTL_FORMAT_XRGB_2101010:
2602 if (rgb_order)
2603 return DRM_FORMAT_XBGR2101010;
2604 else
2605 return DRM_FORMAT_XRGB2101010;
2606 }
2607 }
2608
2609 static bool
2610 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2611 struct intel_initial_plane_config *plane_config)
2612 {
2613 struct drm_device *dev = crtc->base.dev;
2614 struct drm_i915_private *dev_priv = to_i915(dev);
2615 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2616 struct drm_i915_gem_object *obj = NULL;
2617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2618 struct drm_framebuffer *fb = &plane_config->fb->base;
2619 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2620 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2621 PAGE_SIZE);
2622
2623 size_aligned -= base_aligned;
2624
2625 if (plane_config->size == 0)
2626 return false;
2627
2628 /* If the FB is too big, just don't use it since fbdev is not very
2629 * important and we should probably use that space with FBC or other
2630 * features. */
2631 if (size_aligned * 2 > ggtt->stolen_usable_size)
2632 return false;
2633
2634 mutex_lock(&dev->struct_mutex);
2635 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2636 base_aligned,
2637 base_aligned,
2638 size_aligned);
2639 mutex_unlock(&dev->struct_mutex);
2640 if (!obj)
2641 return false;
2642
2643 if (plane_config->tiling == I915_TILING_X)
2644 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2645
2646 mode_cmd.pixel_format = fb->format->format;
2647 mode_cmd.width = fb->width;
2648 mode_cmd.height = fb->height;
2649 mode_cmd.pitches[0] = fb->pitches[0];
2650 mode_cmd.modifier[0] = fb->modifier;
2651 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2652
2653 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2654 DRM_DEBUG_KMS("intel fb init failed\n");
2655 goto out_unref_obj;
2656 }
2657
2658
2659 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2660 return true;
2661
2662 out_unref_obj:
2663 i915_gem_object_put(obj);
2664 return false;
2665 }
2666
2667 static void
2668 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2669 struct intel_plane_state *plane_state,
2670 bool visible)
2671 {
2672 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2673
2674 plane_state->base.visible = visible;
2675
2676 /* FIXME pre-g4x don't work like this */
2677 if (visible) {
2678 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2679 crtc_state->active_planes |= BIT(plane->id);
2680 } else {
2681 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2682 crtc_state->active_planes &= ~BIT(plane->id);
2683 }
2684
2685 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2686 crtc_state->base.crtc->name,
2687 crtc_state->active_planes);
2688 }
2689
2690 static void
2691 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2692 struct intel_initial_plane_config *plane_config)
2693 {
2694 struct drm_device *dev = intel_crtc->base.dev;
2695 struct drm_i915_private *dev_priv = to_i915(dev);
2696 struct drm_crtc *c;
2697 struct drm_i915_gem_object *obj;
2698 struct drm_plane *primary = intel_crtc->base.primary;
2699 struct drm_plane_state *plane_state = primary->state;
2700 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2701 struct intel_plane *intel_plane = to_intel_plane(primary);
2702 struct intel_plane_state *intel_state =
2703 to_intel_plane_state(plane_state);
2704 struct drm_framebuffer *fb;
2705
2706 if (!plane_config->fb)
2707 return;
2708
2709 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2710 fb = &plane_config->fb->base;
2711 goto valid_fb;
2712 }
2713
2714 kfree(plane_config->fb);
2715
2716 /*
2717 * Failed to alloc the obj, check to see if we should share
2718 * an fb with another CRTC instead
2719 */
2720 for_each_crtc(dev, c) {
2721 struct intel_plane_state *state;
2722
2723 if (c == &intel_crtc->base)
2724 continue;
2725
2726 if (!to_intel_crtc(c)->active)
2727 continue;
2728
2729 state = to_intel_plane_state(c->primary->state);
2730 if (!state->vma)
2731 continue;
2732
2733 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2734 fb = c->primary->fb;
2735 drm_framebuffer_reference(fb);
2736 goto valid_fb;
2737 }
2738 }
2739
2740 /*
2741 * We've failed to reconstruct the BIOS FB. Current display state
2742 * indicates that the primary plane is visible, but has a NULL FB,
2743 * which will lead to problems later if we don't fix it up. The
2744 * simplest solution is to just disable the primary plane now and
2745 * pretend the BIOS never had it enabled.
2746 */
2747 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2748 to_intel_plane_state(plane_state),
2749 false);
2750 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2751 trace_intel_disable_plane(primary, intel_crtc);
2752 intel_plane->disable_plane(intel_plane, intel_crtc);
2753
2754 return;
2755
2756 valid_fb:
2757 mutex_lock(&dev->struct_mutex);
2758 intel_state->vma =
2759 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2760 mutex_unlock(&dev->struct_mutex);
2761 if (IS_ERR(intel_state->vma)) {
2762 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2763 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2764
2765 intel_state->vma = NULL;
2766 drm_framebuffer_unreference(fb);
2767 return;
2768 }
2769
2770 plane_state->src_x = 0;
2771 plane_state->src_y = 0;
2772 plane_state->src_w = fb->width << 16;
2773 plane_state->src_h = fb->height << 16;
2774
2775 plane_state->crtc_x = 0;
2776 plane_state->crtc_y = 0;
2777 plane_state->crtc_w = fb->width;
2778 plane_state->crtc_h = fb->height;
2779
2780 intel_state->base.src = drm_plane_state_src(plane_state);
2781 intel_state->base.dst = drm_plane_state_dest(plane_state);
2782
2783 obj = intel_fb_obj(fb);
2784 if (i915_gem_object_is_tiled(obj))
2785 dev_priv->preserve_bios_swizzle = true;
2786
2787 drm_framebuffer_reference(fb);
2788 primary->fb = primary->state->fb = fb;
2789 primary->crtc = primary->state->crtc = &intel_crtc->base;
2790
2791 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2792 to_intel_plane_state(plane_state),
2793 true);
2794
2795 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2796 &obj->frontbuffer_bits);
2797 }
2798
2799 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2800 unsigned int rotation)
2801 {
2802 int cpp = fb->format->cpp[plane];
2803
2804 switch (fb->modifier) {
2805 case DRM_FORMAT_MOD_LINEAR:
2806 case I915_FORMAT_MOD_X_TILED:
2807 switch (cpp) {
2808 case 8:
2809 return 4096;
2810 case 4:
2811 case 2:
2812 case 1:
2813 return 8192;
2814 default:
2815 MISSING_CASE(cpp);
2816 break;
2817 }
2818 break;
2819 case I915_FORMAT_MOD_Y_TILED:
2820 case I915_FORMAT_MOD_Yf_TILED:
2821 switch (cpp) {
2822 case 8:
2823 return 2048;
2824 case 4:
2825 return 4096;
2826 case 2:
2827 case 1:
2828 return 8192;
2829 default:
2830 MISSING_CASE(cpp);
2831 break;
2832 }
2833 break;
2834 default:
2835 MISSING_CASE(fb->modifier);
2836 }
2837
2838 return 2048;
2839 }
2840
2841 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2842 {
2843 const struct drm_framebuffer *fb = plane_state->base.fb;
2844 unsigned int rotation = plane_state->base.rotation;
2845 int x = plane_state->base.src.x1 >> 16;
2846 int y = plane_state->base.src.y1 >> 16;
2847 int w = drm_rect_width(&plane_state->base.src) >> 16;
2848 int h = drm_rect_height(&plane_state->base.src) >> 16;
2849 int max_width = skl_max_plane_width(fb, 0, rotation);
2850 int max_height = 4096;
2851 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2852
2853 if (w > max_width || h > max_height) {
2854 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2855 w, h, max_width, max_height);
2856 return -EINVAL;
2857 }
2858
2859 intel_add_fb_offsets(&x, &y, plane_state, 0);
2860 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2861 alignment = intel_surf_alignment(fb, 0);
2862
2863 /*
2864 * AUX surface offset is specified as the distance from the
2865 * main surface offset, and it must be non-negative. Make
2866 * sure that is what we will get.
2867 */
2868 if (offset > aux_offset)
2869 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2870 offset, aux_offset & ~(alignment - 1));
2871
2872 /*
2873 * When using an X-tiled surface, the plane blows up
2874 * if the x offset + width exceed the stride.
2875 *
2876 * TODO: linear and Y-tiled seem fine, Yf untested,
2877 */
2878 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2879 int cpp = fb->format->cpp[0];
2880
2881 while ((x + w) * cpp > fb->pitches[0]) {
2882 if (offset == 0) {
2883 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2884 return -EINVAL;
2885 }
2886
2887 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2888 offset, offset - alignment);
2889 }
2890 }
2891
2892 plane_state->main.offset = offset;
2893 plane_state->main.x = x;
2894 plane_state->main.y = y;
2895
2896 return 0;
2897 }
2898
2899 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2900 {
2901 const struct drm_framebuffer *fb = plane_state->base.fb;
2902 unsigned int rotation = plane_state->base.rotation;
2903 int max_width = skl_max_plane_width(fb, 1, rotation);
2904 int max_height = 4096;
2905 int x = plane_state->base.src.x1 >> 17;
2906 int y = plane_state->base.src.y1 >> 17;
2907 int w = drm_rect_width(&plane_state->base.src) >> 17;
2908 int h = drm_rect_height(&plane_state->base.src) >> 17;
2909 u32 offset;
2910
2911 intel_add_fb_offsets(&x, &y, plane_state, 1);
2912 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2913
2914 /* FIXME not quite sure how/if these apply to the chroma plane */
2915 if (w > max_width || h > max_height) {
2916 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2917 w, h, max_width, max_height);
2918 return -EINVAL;
2919 }
2920
2921 plane_state->aux.offset = offset;
2922 plane_state->aux.x = x;
2923 plane_state->aux.y = y;
2924
2925 return 0;
2926 }
2927
2928 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2929 {
2930 const struct drm_framebuffer *fb = plane_state->base.fb;
2931 unsigned int rotation = plane_state->base.rotation;
2932 int ret;
2933
2934 if (!plane_state->base.visible)
2935 return 0;
2936
2937 /* Rotate src coordinates to match rotated GTT view */
2938 if (drm_rotation_90_or_270(rotation))
2939 drm_rect_rotate(&plane_state->base.src,
2940 fb->width << 16, fb->height << 16,
2941 DRM_MODE_ROTATE_270);
2942
2943 /*
2944 * Handle the AUX surface first since
2945 * the main surface setup depends on it.
2946 */
2947 if (fb->format->format == DRM_FORMAT_NV12) {
2948 ret = skl_check_nv12_aux_surface(plane_state);
2949 if (ret)
2950 return ret;
2951 } else {
2952 plane_state->aux.offset = ~0xfff;
2953 plane_state->aux.x = 0;
2954 plane_state->aux.y = 0;
2955 }
2956
2957 ret = skl_check_main_surface(plane_state);
2958 if (ret)
2959 return ret;
2960
2961 return 0;
2962 }
2963
2964 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2965 const struct intel_plane_state *plane_state)
2966 {
2967 struct drm_i915_private *dev_priv =
2968 to_i915(plane_state->base.plane->dev);
2969 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2970 const struct drm_framebuffer *fb = plane_state->base.fb;
2971 unsigned int rotation = plane_state->base.rotation;
2972 u32 dspcntr;
2973
2974 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2975
2976 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2977 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2978 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2979
2980 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2981 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2982
2983 if (INTEL_GEN(dev_priv) < 4)
2984 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2985
2986 switch (fb->format->format) {
2987 case DRM_FORMAT_C8:
2988 dspcntr |= DISPPLANE_8BPP;
2989 break;
2990 case DRM_FORMAT_XRGB1555:
2991 dspcntr |= DISPPLANE_BGRX555;
2992 break;
2993 case DRM_FORMAT_RGB565:
2994 dspcntr |= DISPPLANE_BGRX565;
2995 break;
2996 case DRM_FORMAT_XRGB8888:
2997 dspcntr |= DISPPLANE_BGRX888;
2998 break;
2999 case DRM_FORMAT_XBGR8888:
3000 dspcntr |= DISPPLANE_RGBX888;
3001 break;
3002 case DRM_FORMAT_XRGB2101010:
3003 dspcntr |= DISPPLANE_BGRX101010;
3004 break;
3005 case DRM_FORMAT_XBGR2101010:
3006 dspcntr |= DISPPLANE_RGBX101010;
3007 break;
3008 default:
3009 MISSING_CASE(fb->format->format);
3010 return 0;
3011 }
3012
3013 if (INTEL_GEN(dev_priv) >= 4 &&
3014 fb->modifier == I915_FORMAT_MOD_X_TILED)
3015 dspcntr |= DISPPLANE_TILED;
3016
3017 if (rotation & DRM_MODE_ROTATE_180)
3018 dspcntr |= DISPPLANE_ROTATE_180;
3019
3020 if (rotation & DRM_MODE_REFLECT_X)
3021 dspcntr |= DISPPLANE_MIRROR;
3022
3023 return dspcntr;
3024 }
3025
3026 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3027 {
3028 struct drm_i915_private *dev_priv =
3029 to_i915(plane_state->base.plane->dev);
3030 int src_x = plane_state->base.src.x1 >> 16;
3031 int src_y = plane_state->base.src.y1 >> 16;
3032 u32 offset;
3033
3034 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3035
3036 if (INTEL_GEN(dev_priv) >= 4)
3037 offset = intel_compute_tile_offset(&src_x, &src_y,
3038 plane_state, 0);
3039 else
3040 offset = 0;
3041
3042 /* HSW/BDW do this automagically in hardware */
3043 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3044 unsigned int rotation = plane_state->base.rotation;
3045 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3046 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3047
3048 if (rotation & DRM_MODE_ROTATE_180) {
3049 src_x += src_w - 1;
3050 src_y += src_h - 1;
3051 } else if (rotation & DRM_MODE_REFLECT_X) {
3052 src_x += src_w - 1;
3053 }
3054 }
3055
3056 plane_state->main.offset = offset;
3057 plane_state->main.x = src_x;
3058 plane_state->main.y = src_y;
3059
3060 return 0;
3061 }
3062
3063 static void i9xx_update_primary_plane(struct intel_plane *primary,
3064 const struct intel_crtc_state *crtc_state,
3065 const struct intel_plane_state *plane_state)
3066 {
3067 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3069 const struct drm_framebuffer *fb = plane_state->base.fb;
3070 enum plane plane = primary->plane;
3071 u32 linear_offset;
3072 u32 dspcntr = plane_state->ctl;
3073 i915_reg_t reg = DSPCNTR(plane);
3074 int x = plane_state->main.x;
3075 int y = plane_state->main.y;
3076 unsigned long irqflags;
3077
3078 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3079
3080 if (INTEL_GEN(dev_priv) >= 4)
3081 crtc->dspaddr_offset = plane_state->main.offset;
3082 else
3083 crtc->dspaddr_offset = linear_offset;
3084
3085 crtc->adjusted_x = x;
3086 crtc->adjusted_y = y;
3087
3088 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3089
3090 if (INTEL_GEN(dev_priv) < 4) {
3091 /* pipesrc and dspsize control the size that is scaled from,
3092 * which should always be the user's requested size.
3093 */
3094 I915_WRITE_FW(DSPSIZE(plane),
3095 ((crtc_state->pipe_src_h - 1) << 16) |
3096 (crtc_state->pipe_src_w - 1));
3097 I915_WRITE_FW(DSPPOS(plane), 0);
3098 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3099 I915_WRITE_FW(PRIMSIZE(plane),
3100 ((crtc_state->pipe_src_h - 1) << 16) |
3101 (crtc_state->pipe_src_w - 1));
3102 I915_WRITE_FW(PRIMPOS(plane), 0);
3103 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3104 }
3105
3106 I915_WRITE_FW(reg, dspcntr);
3107
3108 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3109 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3110 I915_WRITE_FW(DSPSURF(plane),
3111 intel_plane_ggtt_offset(plane_state) +
3112 crtc->dspaddr_offset);
3113 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3114 } else if (INTEL_GEN(dev_priv) >= 4) {
3115 I915_WRITE_FW(DSPSURF(plane),
3116 intel_plane_ggtt_offset(plane_state) +
3117 crtc->dspaddr_offset);
3118 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3119 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3120 } else {
3121 I915_WRITE_FW(DSPADDR(plane),
3122 intel_plane_ggtt_offset(plane_state) +
3123 crtc->dspaddr_offset);
3124 }
3125 POSTING_READ_FW(reg);
3126
3127 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3128 }
3129
3130 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3131 struct intel_crtc *crtc)
3132 {
3133 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3134 enum plane plane = primary->plane;
3135 unsigned long irqflags;
3136
3137 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3138
3139 I915_WRITE_FW(DSPCNTR(plane), 0);
3140 if (INTEL_INFO(dev_priv)->gen >= 4)
3141 I915_WRITE_FW(DSPSURF(plane), 0);
3142 else
3143 I915_WRITE_FW(DSPADDR(plane), 0);
3144 POSTING_READ_FW(DSPCNTR(plane));
3145
3146 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3147 }
3148
3149 static u32
3150 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3151 {
3152 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3153 return 64;
3154 else
3155 return intel_tile_width_bytes(fb, plane);
3156 }
3157
3158 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3159 {
3160 struct drm_device *dev = intel_crtc->base.dev;
3161 struct drm_i915_private *dev_priv = to_i915(dev);
3162
3163 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3164 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3165 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3166 }
3167
3168 /*
3169 * This function detaches (aka. unbinds) unused scalers in hardware
3170 */
3171 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3172 {
3173 struct intel_crtc_scaler_state *scaler_state;
3174 int i;
3175
3176 scaler_state = &intel_crtc->config->scaler_state;
3177
3178 /* loop through and disable scalers that aren't in use */
3179 for (i = 0; i < intel_crtc->num_scalers; i++) {
3180 if (!scaler_state->scalers[i].in_use)
3181 skl_detach_scaler(intel_crtc, i);
3182 }
3183 }
3184
3185 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3186 unsigned int rotation)
3187 {
3188 u32 stride;
3189
3190 if (plane >= fb->format->num_planes)
3191 return 0;
3192
3193 stride = intel_fb_pitch(fb, plane, rotation);
3194
3195 /*
3196 * The stride is either expressed as a multiple of 64 bytes chunks for
3197 * linear buffers or in number of tiles for tiled buffers.
3198 */
3199 if (drm_rotation_90_or_270(rotation))
3200 stride /= intel_tile_height(fb, plane);
3201 else
3202 stride /= intel_fb_stride_alignment(fb, plane);
3203
3204 return stride;
3205 }
3206
3207 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3208 {
3209 switch (pixel_format) {
3210 case DRM_FORMAT_C8:
3211 return PLANE_CTL_FORMAT_INDEXED;
3212 case DRM_FORMAT_RGB565:
3213 return PLANE_CTL_FORMAT_RGB_565;
3214 case DRM_FORMAT_XBGR8888:
3215 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3216 case DRM_FORMAT_XRGB8888:
3217 return PLANE_CTL_FORMAT_XRGB_8888;
3218 /*
3219 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3220 * to be already pre-multiplied. We need to add a knob (or a different
3221 * DRM_FORMAT) for user-space to configure that.
3222 */
3223 case DRM_FORMAT_ABGR8888:
3224 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3225 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3226 case DRM_FORMAT_ARGB8888:
3227 return PLANE_CTL_FORMAT_XRGB_8888 |
3228 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3229 case DRM_FORMAT_XRGB2101010:
3230 return PLANE_CTL_FORMAT_XRGB_2101010;
3231 case DRM_FORMAT_XBGR2101010:
3232 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3233 case DRM_FORMAT_YUYV:
3234 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3235 case DRM_FORMAT_YVYU:
3236 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3237 case DRM_FORMAT_UYVY:
3238 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3239 case DRM_FORMAT_VYUY:
3240 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3241 default:
3242 MISSING_CASE(pixel_format);
3243 }
3244
3245 return 0;
3246 }
3247
3248 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3249 {
3250 switch (fb_modifier) {
3251 case DRM_FORMAT_MOD_LINEAR:
3252 break;
3253 case I915_FORMAT_MOD_X_TILED:
3254 return PLANE_CTL_TILED_X;
3255 case I915_FORMAT_MOD_Y_TILED:
3256 return PLANE_CTL_TILED_Y;
3257 case I915_FORMAT_MOD_Yf_TILED:
3258 return PLANE_CTL_TILED_YF;
3259 default:
3260 MISSING_CASE(fb_modifier);
3261 }
3262
3263 return 0;
3264 }
3265
3266 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3267 {
3268 switch (rotation) {
3269 case DRM_MODE_ROTATE_0:
3270 break;
3271 /*
3272 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3273 * while i915 HW rotation is clockwise, thats why this swapping.
3274 */
3275 case DRM_MODE_ROTATE_90:
3276 return PLANE_CTL_ROTATE_270;
3277 case DRM_MODE_ROTATE_180:
3278 return PLANE_CTL_ROTATE_180;
3279 case DRM_MODE_ROTATE_270:
3280 return PLANE_CTL_ROTATE_90;
3281 default:
3282 MISSING_CASE(rotation);
3283 }
3284
3285 return 0;
3286 }
3287
3288 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3289 const struct intel_plane_state *plane_state)
3290 {
3291 struct drm_i915_private *dev_priv =
3292 to_i915(plane_state->base.plane->dev);
3293 const struct drm_framebuffer *fb = plane_state->base.fb;
3294 unsigned int rotation = plane_state->base.rotation;
3295 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3296 u32 plane_ctl;
3297
3298 plane_ctl = PLANE_CTL_ENABLE;
3299
3300 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3301 plane_ctl |=
3302 PLANE_CTL_PIPE_GAMMA_ENABLE |
3303 PLANE_CTL_PIPE_CSC_ENABLE |
3304 PLANE_CTL_PLANE_GAMMA_DISABLE;
3305 }
3306
3307 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3308 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3309 plane_ctl |= skl_plane_ctl_rotation(rotation);
3310
3311 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3312 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3313 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3314 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3315
3316 return plane_ctl;
3317 }
3318
3319 static void skylake_update_primary_plane(struct intel_plane *plane,
3320 const struct intel_crtc_state *crtc_state,
3321 const struct intel_plane_state *plane_state)
3322 {
3323 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3325 const struct drm_framebuffer *fb = plane_state->base.fb;
3326 enum plane_id plane_id = plane->id;
3327 enum pipe pipe = plane->pipe;
3328 u32 plane_ctl = plane_state->ctl;
3329 unsigned int rotation = plane_state->base.rotation;
3330 u32 stride = skl_plane_stride(fb, 0, rotation);
3331 u32 surf_addr = plane_state->main.offset;
3332 int scaler_id = plane_state->scaler_id;
3333 int src_x = plane_state->main.x;
3334 int src_y = plane_state->main.y;
3335 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3336 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3337 int dst_x = plane_state->base.dst.x1;
3338 int dst_y = plane_state->base.dst.y1;
3339 int dst_w = drm_rect_width(&plane_state->base.dst);
3340 int dst_h = drm_rect_height(&plane_state->base.dst);
3341 unsigned long irqflags;
3342
3343 /* Sizes are 0 based */
3344 src_w--;
3345 src_h--;
3346 dst_w--;
3347 dst_h--;
3348
3349 crtc->dspaddr_offset = surf_addr;
3350
3351 crtc->adjusted_x = src_x;
3352 crtc->adjusted_y = src_y;
3353
3354 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3355
3356 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3357 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3358 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3359 PLANE_COLOR_PIPE_CSC_ENABLE |
3360 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3361 }
3362
3363 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3364 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3365 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3366 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3367
3368 if (scaler_id >= 0) {
3369 uint32_t ps_ctrl = 0;
3370
3371 WARN_ON(!dst_w || !dst_h);
3372 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3373 crtc_state->scaler_state.scalers[scaler_id].mode;
3374 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3375 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3376 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3377 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3378 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3379 } else {
3380 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3381 }
3382
3383 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3384 intel_plane_ggtt_offset(plane_state) + surf_addr);
3385
3386 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3387
3388 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3389 }
3390
3391 static void skylake_disable_primary_plane(struct intel_plane *primary,
3392 struct intel_crtc *crtc)
3393 {
3394 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3395 enum plane_id plane_id = primary->id;
3396 enum pipe pipe = primary->pipe;
3397 unsigned long irqflags;
3398
3399 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3400
3401 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3402 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3403 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3404
3405 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3406 }
3407
3408 static int
3409 __intel_display_resume(struct drm_device *dev,
3410 struct drm_atomic_state *state,
3411 struct drm_modeset_acquire_ctx *ctx)
3412 {
3413 struct drm_crtc_state *crtc_state;
3414 struct drm_crtc *crtc;
3415 int i, ret;
3416
3417 intel_modeset_setup_hw_state(dev, ctx);
3418 i915_redisable_vga(to_i915(dev));
3419
3420 if (!state)
3421 return 0;
3422
3423 /*
3424 * We've duplicated the state, pointers to the old state are invalid.
3425 *
3426 * Don't attempt to use the old state until we commit the duplicated state.
3427 */
3428 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3429 /*
3430 * Force recalculation even if we restore
3431 * current state. With fast modeset this may not result
3432 * in a modeset when the state is compatible.
3433 */
3434 crtc_state->mode_changed = true;
3435 }
3436
3437 /* ignore any reset values/BIOS leftovers in the WM registers */
3438 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3439 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3440
3441 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3442
3443 WARN_ON(ret == -EDEADLK);
3444 return ret;
3445 }
3446
3447 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3448 {
3449 return intel_has_gpu_reset(dev_priv) &&
3450 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3451 }
3452
3453 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3454 {
3455 struct drm_device *dev = &dev_priv->drm;
3456 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3457 struct drm_atomic_state *state;
3458 int ret;
3459
3460
3461 /* reset doesn't touch the display */
3462 if (!i915.force_reset_modeset_test &&
3463 !gpu_reset_clobbers_display(dev_priv))
3464 return;
3465
3466 /*
3467 * Need mode_config.mutex so that we don't
3468 * trample ongoing ->detect() and whatnot.
3469 */
3470 mutex_lock(&dev->mode_config.mutex);
3471 drm_modeset_acquire_init(ctx, 0);
3472 while (1) {
3473 ret = drm_modeset_lock_all_ctx(dev, ctx);
3474 if (ret != -EDEADLK)
3475 break;
3476
3477 drm_modeset_backoff(ctx);
3478 }
3479 /*
3480 * Disabling the crtcs gracefully seems nicer. Also the
3481 * g33 docs say we should at least disable all the planes.
3482 */
3483 state = drm_atomic_helper_duplicate_state(dev, ctx);
3484 if (IS_ERR(state)) {
3485 ret = PTR_ERR(state);
3486 DRM_ERROR("Duplicating state failed with %i\n", ret);
3487 return;
3488 }
3489
3490 ret = drm_atomic_helper_disable_all(dev, ctx);
3491 if (ret) {
3492 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3493 drm_atomic_state_put(state);
3494 return;
3495 }
3496
3497 dev_priv->modeset_restore_state = state;
3498 state->acquire_ctx = ctx;
3499 }
3500
3501 void intel_finish_reset(struct drm_i915_private *dev_priv)
3502 {
3503 struct drm_device *dev = &dev_priv->drm;
3504 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3505 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3506 int ret;
3507
3508 /* reset doesn't touch the display */
3509 if (!i915.force_reset_modeset_test &&
3510 !gpu_reset_clobbers_display(dev_priv))
3511 return;
3512
3513 if (!state)
3514 goto unlock;
3515
3516 dev_priv->modeset_restore_state = NULL;
3517
3518 /* reset doesn't touch the display */
3519 if (!gpu_reset_clobbers_display(dev_priv)) {
3520 /* for testing only restore the display */
3521 ret = __intel_display_resume(dev, state, ctx);
3522 if (ret)
3523 DRM_ERROR("Restoring old state failed with %i\n", ret);
3524 } else {
3525 /*
3526 * The display has been reset as well,
3527 * so need a full re-initialization.
3528 */
3529 intel_runtime_pm_disable_interrupts(dev_priv);
3530 intel_runtime_pm_enable_interrupts(dev_priv);
3531
3532 intel_pps_unlock_regs_wa(dev_priv);
3533 intel_modeset_init_hw(dev);
3534
3535 spin_lock_irq(&dev_priv->irq_lock);
3536 if (dev_priv->display.hpd_irq_setup)
3537 dev_priv->display.hpd_irq_setup(dev_priv);
3538 spin_unlock_irq(&dev_priv->irq_lock);
3539
3540 ret = __intel_display_resume(dev, state, ctx);
3541 if (ret)
3542 DRM_ERROR("Restoring old state failed with %i\n", ret);
3543
3544 intel_hpd_init(dev_priv);
3545 }
3546
3547 drm_atomic_state_put(state);
3548 unlock:
3549 drm_modeset_drop_locks(ctx);
3550 drm_modeset_acquire_fini(ctx);
3551 mutex_unlock(&dev->mode_config.mutex);
3552 }
3553
3554 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3555 {
3556 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3557
3558 if (i915_reset_backoff(error))
3559 return true;
3560
3561 if (crtc->reset_count != i915_reset_count(error))
3562 return true;
3563
3564 return false;
3565 }
3566
3567 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3568 {
3569 struct drm_device *dev = crtc->dev;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 bool pending;
3572
3573 if (abort_flip_on_reset(intel_crtc))
3574 return false;
3575
3576 spin_lock_irq(&dev->event_lock);
3577 pending = to_intel_crtc(crtc)->flip_work != NULL;
3578 spin_unlock_irq(&dev->event_lock);
3579
3580 return pending;
3581 }
3582
3583 static void intel_update_pipe_config(struct intel_crtc *crtc,
3584 struct intel_crtc_state *old_crtc_state)
3585 {
3586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3587 struct intel_crtc_state *pipe_config =
3588 to_intel_crtc_state(crtc->base.state);
3589
3590 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3591 crtc->base.mode = crtc->base.state->mode;
3592
3593 /*
3594 * Update pipe size and adjust fitter if needed: the reason for this is
3595 * that in compute_mode_changes we check the native mode (not the pfit
3596 * mode) to see if we can flip rather than do a full mode set. In the
3597 * fastboot case, we'll flip, but if we don't update the pipesrc and
3598 * pfit state, we'll end up with a big fb scanned out into the wrong
3599 * sized surface.
3600 */
3601
3602 I915_WRITE(PIPESRC(crtc->pipe),
3603 ((pipe_config->pipe_src_w - 1) << 16) |
3604 (pipe_config->pipe_src_h - 1));
3605
3606 /* on skylake this is done by detaching scalers */
3607 if (INTEL_GEN(dev_priv) >= 9) {
3608 skl_detach_scalers(crtc);
3609
3610 if (pipe_config->pch_pfit.enabled)
3611 skylake_pfit_enable(crtc);
3612 } else if (HAS_PCH_SPLIT(dev_priv)) {
3613 if (pipe_config->pch_pfit.enabled)
3614 ironlake_pfit_enable(crtc);
3615 else if (old_crtc_state->pch_pfit.enabled)
3616 ironlake_pfit_disable(crtc, true);
3617 }
3618 }
3619
3620 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3621 {
3622 struct drm_device *dev = crtc->base.dev;
3623 struct drm_i915_private *dev_priv = to_i915(dev);
3624 int pipe = crtc->pipe;
3625 i915_reg_t reg;
3626 u32 temp;
3627
3628 /* enable normal train */
3629 reg = FDI_TX_CTL(pipe);
3630 temp = I915_READ(reg);
3631 if (IS_IVYBRIDGE(dev_priv)) {
3632 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3633 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3634 } else {
3635 temp &= ~FDI_LINK_TRAIN_NONE;
3636 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3637 }
3638 I915_WRITE(reg, temp);
3639
3640 reg = FDI_RX_CTL(pipe);
3641 temp = I915_READ(reg);
3642 if (HAS_PCH_CPT(dev_priv)) {
3643 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3644 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3645 } else {
3646 temp &= ~FDI_LINK_TRAIN_NONE;
3647 temp |= FDI_LINK_TRAIN_NONE;
3648 }
3649 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3650
3651 /* wait one idle pattern time */
3652 POSTING_READ(reg);
3653 udelay(1000);
3654
3655 /* IVB wants error correction enabled */
3656 if (IS_IVYBRIDGE(dev_priv))
3657 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3658 FDI_FE_ERRC_ENABLE);
3659 }
3660
3661 /* The FDI link training functions for ILK/Ibexpeak. */
3662 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3663 const struct intel_crtc_state *crtc_state)
3664 {
3665 struct drm_device *dev = crtc->base.dev;
3666 struct drm_i915_private *dev_priv = to_i915(dev);
3667 int pipe = crtc->pipe;
3668 i915_reg_t reg;
3669 u32 temp, tries;
3670
3671 /* FDI needs bits from pipe first */
3672 assert_pipe_enabled(dev_priv, pipe);
3673
3674 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3675 for train result */
3676 reg = FDI_RX_IMR(pipe);
3677 temp = I915_READ(reg);
3678 temp &= ~FDI_RX_SYMBOL_LOCK;
3679 temp &= ~FDI_RX_BIT_LOCK;
3680 I915_WRITE(reg, temp);
3681 I915_READ(reg);
3682 udelay(150);
3683
3684 /* enable CPU FDI TX and PCH FDI RX */
3685 reg = FDI_TX_CTL(pipe);
3686 temp = I915_READ(reg);
3687 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3688 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3689 temp &= ~FDI_LINK_TRAIN_NONE;
3690 temp |= FDI_LINK_TRAIN_PATTERN_1;
3691 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_NONE;
3696 temp |= FDI_LINK_TRAIN_PATTERN_1;
3697 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3698
3699 POSTING_READ(reg);
3700 udelay(150);
3701
3702 /* Ironlake workaround, enable clock pointer after FDI enable*/
3703 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3704 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3705 FDI_RX_PHASE_SYNC_POINTER_EN);
3706
3707 reg = FDI_RX_IIR(pipe);
3708 for (tries = 0; tries < 5; tries++) {
3709 temp = I915_READ(reg);
3710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3711
3712 if ((temp & FDI_RX_BIT_LOCK)) {
3713 DRM_DEBUG_KMS("FDI train 1 done.\n");
3714 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3715 break;
3716 }
3717 }
3718 if (tries == 5)
3719 DRM_ERROR("FDI train 1 fail!\n");
3720
3721 /* Train 2 */
3722 reg = FDI_TX_CTL(pipe);
3723 temp = I915_READ(reg);
3724 temp &= ~FDI_LINK_TRAIN_NONE;
3725 temp |= FDI_LINK_TRAIN_PATTERN_2;
3726 I915_WRITE(reg, temp);
3727
3728 reg = FDI_RX_CTL(pipe);
3729 temp = I915_READ(reg);
3730 temp &= ~FDI_LINK_TRAIN_NONE;
3731 temp |= FDI_LINK_TRAIN_PATTERN_2;
3732 I915_WRITE(reg, temp);
3733
3734 POSTING_READ(reg);
3735 udelay(150);
3736
3737 reg = FDI_RX_IIR(pipe);
3738 for (tries = 0; tries < 5; tries++) {
3739 temp = I915_READ(reg);
3740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3741
3742 if (temp & FDI_RX_SYMBOL_LOCK) {
3743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3744 DRM_DEBUG_KMS("FDI train 2 done.\n");
3745 break;
3746 }
3747 }
3748 if (tries == 5)
3749 DRM_ERROR("FDI train 2 fail!\n");
3750
3751 DRM_DEBUG_KMS("FDI train done\n");
3752
3753 }
3754
3755 static const int snb_b_fdi_train_param[] = {
3756 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3757 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3758 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3759 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3760 };
3761
3762 /* The FDI link training functions for SNB/Cougarpoint. */
3763 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3764 const struct intel_crtc_state *crtc_state)
3765 {
3766 struct drm_device *dev = crtc->base.dev;
3767 struct drm_i915_private *dev_priv = to_i915(dev);
3768 int pipe = crtc->pipe;
3769 i915_reg_t reg;
3770 u32 temp, i, retry;
3771
3772 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3773 for train result */
3774 reg = FDI_RX_IMR(pipe);
3775 temp = I915_READ(reg);
3776 temp &= ~FDI_RX_SYMBOL_LOCK;
3777 temp &= ~FDI_RX_BIT_LOCK;
3778 I915_WRITE(reg, temp);
3779
3780 POSTING_READ(reg);
3781 udelay(150);
3782
3783 /* enable CPU FDI TX and PCH FDI RX */
3784 reg = FDI_TX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3787 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3788 temp &= ~FDI_LINK_TRAIN_NONE;
3789 temp |= FDI_LINK_TRAIN_PATTERN_1;
3790 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3791 /* SNB-B */
3792 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3793 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3794
3795 I915_WRITE(FDI_RX_MISC(pipe),
3796 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3797
3798 reg = FDI_RX_CTL(pipe);
3799 temp = I915_READ(reg);
3800 if (HAS_PCH_CPT(dev_priv)) {
3801 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3802 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3803 } else {
3804 temp &= ~FDI_LINK_TRAIN_NONE;
3805 temp |= FDI_LINK_TRAIN_PATTERN_1;
3806 }
3807 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3808
3809 POSTING_READ(reg);
3810 udelay(150);
3811
3812 for (i = 0; i < 4; i++) {
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3816 temp |= snb_b_fdi_train_param[i];
3817 I915_WRITE(reg, temp);
3818
3819 POSTING_READ(reg);
3820 udelay(500);
3821
3822 for (retry = 0; retry < 5; retry++) {
3823 reg = FDI_RX_IIR(pipe);
3824 temp = I915_READ(reg);
3825 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3826 if (temp & FDI_RX_BIT_LOCK) {
3827 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3828 DRM_DEBUG_KMS("FDI train 1 done.\n");
3829 break;
3830 }
3831 udelay(50);
3832 }
3833 if (retry < 5)
3834 break;
3835 }
3836 if (i == 4)
3837 DRM_ERROR("FDI train 1 fail!\n");
3838
3839 /* Train 2 */
3840 reg = FDI_TX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 temp &= ~FDI_LINK_TRAIN_NONE;
3843 temp |= FDI_LINK_TRAIN_PATTERN_2;
3844 if (IS_GEN6(dev_priv)) {
3845 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3846 /* SNB-B */
3847 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3848 }
3849 I915_WRITE(reg, temp);
3850
3851 reg = FDI_RX_CTL(pipe);
3852 temp = I915_READ(reg);
3853 if (HAS_PCH_CPT(dev_priv)) {
3854 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3855 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3856 } else {
3857 temp &= ~FDI_LINK_TRAIN_NONE;
3858 temp |= FDI_LINK_TRAIN_PATTERN_2;
3859 }
3860 I915_WRITE(reg, temp);
3861
3862 POSTING_READ(reg);
3863 udelay(150);
3864
3865 for (i = 0; i < 4; i++) {
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3869 temp |= snb_b_fdi_train_param[i];
3870 I915_WRITE(reg, temp);
3871
3872 POSTING_READ(reg);
3873 udelay(500);
3874
3875 for (retry = 0; retry < 5; retry++) {
3876 reg = FDI_RX_IIR(pipe);
3877 temp = I915_READ(reg);
3878 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3879 if (temp & FDI_RX_SYMBOL_LOCK) {
3880 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3881 DRM_DEBUG_KMS("FDI train 2 done.\n");
3882 break;
3883 }
3884 udelay(50);
3885 }
3886 if (retry < 5)
3887 break;
3888 }
3889 if (i == 4)
3890 DRM_ERROR("FDI train 2 fail!\n");
3891
3892 DRM_DEBUG_KMS("FDI train done.\n");
3893 }
3894
3895 /* Manual link training for Ivy Bridge A0 parts */
3896 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3897 const struct intel_crtc_state *crtc_state)
3898 {
3899 struct drm_device *dev = crtc->base.dev;
3900 struct drm_i915_private *dev_priv = to_i915(dev);
3901 int pipe = crtc->pipe;
3902 i915_reg_t reg;
3903 u32 temp, i, j;
3904
3905 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3906 for train result */
3907 reg = FDI_RX_IMR(pipe);
3908 temp = I915_READ(reg);
3909 temp &= ~FDI_RX_SYMBOL_LOCK;
3910 temp &= ~FDI_RX_BIT_LOCK;
3911 I915_WRITE(reg, temp);
3912
3913 POSTING_READ(reg);
3914 udelay(150);
3915
3916 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3917 I915_READ(FDI_RX_IIR(pipe)));
3918
3919 /* Try each vswing and preemphasis setting twice before moving on */
3920 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3921 /* disable first in case we need to retry */
3922 reg = FDI_TX_CTL(pipe);
3923 temp = I915_READ(reg);
3924 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3925 temp &= ~FDI_TX_ENABLE;
3926 I915_WRITE(reg, temp);
3927
3928 reg = FDI_RX_CTL(pipe);
3929 temp = I915_READ(reg);
3930 temp &= ~FDI_LINK_TRAIN_AUTO;
3931 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3932 temp &= ~FDI_RX_ENABLE;
3933 I915_WRITE(reg, temp);
3934
3935 /* enable CPU FDI TX and PCH FDI RX */
3936 reg = FDI_TX_CTL(pipe);
3937 temp = I915_READ(reg);
3938 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3939 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3940 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3941 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3942 temp |= snb_b_fdi_train_param[j/2];
3943 temp |= FDI_COMPOSITE_SYNC;
3944 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3945
3946 I915_WRITE(FDI_RX_MISC(pipe),
3947 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3948
3949 reg = FDI_RX_CTL(pipe);
3950 temp = I915_READ(reg);
3951 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3952 temp |= FDI_COMPOSITE_SYNC;
3953 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3954
3955 POSTING_READ(reg);
3956 udelay(1); /* should be 0.5us */
3957
3958 for (i = 0; i < 4; i++) {
3959 reg = FDI_RX_IIR(pipe);
3960 temp = I915_READ(reg);
3961 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3962
3963 if (temp & FDI_RX_BIT_LOCK ||
3964 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3965 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3966 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3967 i);
3968 break;
3969 }
3970 udelay(1); /* should be 0.5us */
3971 }
3972 if (i == 4) {
3973 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3974 continue;
3975 }
3976
3977 /* Train 2 */
3978 reg = FDI_TX_CTL(pipe);
3979 temp = I915_READ(reg);
3980 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3981 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3982 I915_WRITE(reg, temp);
3983
3984 reg = FDI_RX_CTL(pipe);
3985 temp = I915_READ(reg);
3986 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3987 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3988 I915_WRITE(reg, temp);
3989
3990 POSTING_READ(reg);
3991 udelay(2); /* should be 1.5us */
3992
3993 for (i = 0; i < 4; i++) {
3994 reg = FDI_RX_IIR(pipe);
3995 temp = I915_READ(reg);
3996 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3997
3998 if (temp & FDI_RX_SYMBOL_LOCK ||
3999 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4000 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4001 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4002 i);
4003 goto train_done;
4004 }
4005 udelay(2); /* should be 1.5us */
4006 }
4007 if (i == 4)
4008 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4009 }
4010
4011 train_done:
4012 DRM_DEBUG_KMS("FDI train done.\n");
4013 }
4014
4015 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4016 {
4017 struct drm_device *dev = intel_crtc->base.dev;
4018 struct drm_i915_private *dev_priv = to_i915(dev);
4019 int pipe = intel_crtc->pipe;
4020 i915_reg_t reg;
4021 u32 temp;
4022
4023 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4024 reg = FDI_RX_CTL(pipe);
4025 temp = I915_READ(reg);
4026 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4027 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4028 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4029 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4030
4031 POSTING_READ(reg);
4032 udelay(200);
4033
4034 /* Switch from Rawclk to PCDclk */
4035 temp = I915_READ(reg);
4036 I915_WRITE(reg, temp | FDI_PCDCLK);
4037
4038 POSTING_READ(reg);
4039 udelay(200);
4040
4041 /* Enable CPU FDI TX PLL, always on for Ironlake */
4042 reg = FDI_TX_CTL(pipe);
4043 temp = I915_READ(reg);
4044 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4045 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4046
4047 POSTING_READ(reg);
4048 udelay(100);
4049 }
4050 }
4051
4052 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4053 {
4054 struct drm_device *dev = intel_crtc->base.dev;
4055 struct drm_i915_private *dev_priv = to_i915(dev);
4056 int pipe = intel_crtc->pipe;
4057 i915_reg_t reg;
4058 u32 temp;
4059
4060 /* Switch from PCDclk to Rawclk */
4061 reg = FDI_RX_CTL(pipe);
4062 temp = I915_READ(reg);
4063 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4064
4065 /* Disable CPU FDI TX PLL */
4066 reg = FDI_TX_CTL(pipe);
4067 temp = I915_READ(reg);
4068 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4069
4070 POSTING_READ(reg);
4071 udelay(100);
4072
4073 reg = FDI_RX_CTL(pipe);
4074 temp = I915_READ(reg);
4075 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4076
4077 /* Wait for the clocks to turn off. */
4078 POSTING_READ(reg);
4079 udelay(100);
4080 }
4081
4082 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4083 {
4084 struct drm_device *dev = crtc->dev;
4085 struct drm_i915_private *dev_priv = to_i915(dev);
4086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4087 int pipe = intel_crtc->pipe;
4088 i915_reg_t reg;
4089 u32 temp;
4090
4091 /* disable CPU FDI tx and PCH FDI rx */
4092 reg = FDI_TX_CTL(pipe);
4093 temp = I915_READ(reg);
4094 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4095 POSTING_READ(reg);
4096
4097 reg = FDI_RX_CTL(pipe);
4098 temp = I915_READ(reg);
4099 temp &= ~(0x7 << 16);
4100 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4101 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4102
4103 POSTING_READ(reg);
4104 udelay(100);
4105
4106 /* Ironlake workaround, disable clock pointer after downing FDI */
4107 if (HAS_PCH_IBX(dev_priv))
4108 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4109
4110 /* still set train pattern 1 */
4111 reg = FDI_TX_CTL(pipe);
4112 temp = I915_READ(reg);
4113 temp &= ~FDI_LINK_TRAIN_NONE;
4114 temp |= FDI_LINK_TRAIN_PATTERN_1;
4115 I915_WRITE(reg, temp);
4116
4117 reg = FDI_RX_CTL(pipe);
4118 temp = I915_READ(reg);
4119 if (HAS_PCH_CPT(dev_priv)) {
4120 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4121 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4122 } else {
4123 temp &= ~FDI_LINK_TRAIN_NONE;
4124 temp |= FDI_LINK_TRAIN_PATTERN_1;
4125 }
4126 /* BPC in FDI rx is consistent with that in PIPECONF */
4127 temp &= ~(0x07 << 16);
4128 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4129 I915_WRITE(reg, temp);
4130
4131 POSTING_READ(reg);
4132 udelay(100);
4133 }
4134
4135 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4136 {
4137 struct intel_crtc *crtc;
4138
4139 /* Note that we don't need to be called with mode_config.lock here
4140 * as our list of CRTC objects is static for the lifetime of the
4141 * device and so cannot disappear as we iterate. Similarly, we can
4142 * happily treat the predicates as racy, atomic checks as userspace
4143 * cannot claim and pin a new fb without at least acquring the
4144 * struct_mutex and so serialising with us.
4145 */
4146 for_each_intel_crtc(&dev_priv->drm, crtc) {
4147 if (atomic_read(&crtc->unpin_work_count) == 0)
4148 continue;
4149
4150 if (crtc->flip_work)
4151 intel_wait_for_vblank(dev_priv, crtc->pipe);
4152
4153 return true;
4154 }
4155
4156 return false;
4157 }
4158
4159 static void page_flip_completed(struct intel_crtc *intel_crtc)
4160 {
4161 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4162 struct intel_flip_work *work = intel_crtc->flip_work;
4163
4164 intel_crtc->flip_work = NULL;
4165
4166 if (work->event)
4167 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4168
4169 drm_crtc_vblank_put(&intel_crtc->base);
4170
4171 wake_up_all(&dev_priv->pending_flip_queue);
4172 trace_i915_flip_complete(intel_crtc->plane,
4173 work->pending_flip_obj);
4174
4175 queue_work(dev_priv->wq, &work->unpin_work);
4176 }
4177
4178 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4179 {
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = to_i915(dev);
4182 long ret;
4183
4184 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4185
4186 ret = wait_event_interruptible_timeout(
4187 dev_priv->pending_flip_queue,
4188 !intel_crtc_has_pending_flip(crtc),
4189 60*HZ);
4190
4191 if (ret < 0)
4192 return ret;
4193
4194 if (ret == 0) {
4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196 struct intel_flip_work *work;
4197
4198 spin_lock_irq(&dev->event_lock);
4199 work = intel_crtc->flip_work;
4200 if (work && !is_mmio_work(work)) {
4201 WARN_ONCE(1, "Removing stuck page flip\n");
4202 page_flip_completed(intel_crtc);
4203 }
4204 spin_unlock_irq(&dev->event_lock);
4205 }
4206
4207 return 0;
4208 }
4209
4210 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4211 {
4212 u32 temp;
4213
4214 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4215
4216 mutex_lock(&dev_priv->sb_lock);
4217
4218 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4219 temp |= SBI_SSCCTL_DISABLE;
4220 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4221
4222 mutex_unlock(&dev_priv->sb_lock);
4223 }
4224
4225 /* Program iCLKIP clock to the desired frequency */
4226 static void lpt_program_iclkip(struct intel_crtc *crtc)
4227 {
4228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4229 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4230 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4231 u32 temp;
4232
4233 lpt_disable_iclkip(dev_priv);
4234
4235 /* The iCLK virtual clock root frequency is in MHz,
4236 * but the adjusted_mode->crtc_clock in in KHz. To get the
4237 * divisors, it is necessary to divide one by another, so we
4238 * convert the virtual clock precision to KHz here for higher
4239 * precision.
4240 */
4241 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4242 u32 iclk_virtual_root_freq = 172800 * 1000;
4243 u32 iclk_pi_range = 64;
4244 u32 desired_divisor;
4245
4246 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4247 clock << auxdiv);
4248 divsel = (desired_divisor / iclk_pi_range) - 2;
4249 phaseinc = desired_divisor % iclk_pi_range;
4250
4251 /*
4252 * Near 20MHz is a corner case which is
4253 * out of range for the 7-bit divisor
4254 */
4255 if (divsel <= 0x7f)
4256 break;
4257 }
4258
4259 /* This should not happen with any sane values */
4260 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4261 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4262 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4263 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4264
4265 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4266 clock,
4267 auxdiv,
4268 divsel,
4269 phasedir,
4270 phaseinc);
4271
4272 mutex_lock(&dev_priv->sb_lock);
4273
4274 /* Program SSCDIVINTPHASE6 */
4275 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4276 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4277 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4278 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4279 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4280 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4281 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4282 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4283
4284 /* Program SSCAUXDIV */
4285 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4286 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4287 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4288 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4289
4290 /* Enable modulator and associated divider */
4291 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4292 temp &= ~SBI_SSCCTL_DISABLE;
4293 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4294
4295 mutex_unlock(&dev_priv->sb_lock);
4296
4297 /* Wait for initialization time */
4298 udelay(24);
4299
4300 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4301 }
4302
4303 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4304 {
4305 u32 divsel, phaseinc, auxdiv;
4306 u32 iclk_virtual_root_freq = 172800 * 1000;
4307 u32 iclk_pi_range = 64;
4308 u32 desired_divisor;
4309 u32 temp;
4310
4311 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4312 return 0;
4313
4314 mutex_lock(&dev_priv->sb_lock);
4315
4316 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4317 if (temp & SBI_SSCCTL_DISABLE) {
4318 mutex_unlock(&dev_priv->sb_lock);
4319 return 0;
4320 }
4321
4322 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4323 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4324 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4325 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4326 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4327
4328 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4329 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4330 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4331
4332 mutex_unlock(&dev_priv->sb_lock);
4333
4334 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4335
4336 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4337 desired_divisor << auxdiv);
4338 }
4339
4340 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4341 enum pipe pch_transcoder)
4342 {
4343 struct drm_device *dev = crtc->base.dev;
4344 struct drm_i915_private *dev_priv = to_i915(dev);
4345 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4346
4347 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4348 I915_READ(HTOTAL(cpu_transcoder)));
4349 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4350 I915_READ(HBLANK(cpu_transcoder)));
4351 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4352 I915_READ(HSYNC(cpu_transcoder)));
4353
4354 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4355 I915_READ(VTOTAL(cpu_transcoder)));
4356 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4357 I915_READ(VBLANK(cpu_transcoder)));
4358 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4359 I915_READ(VSYNC(cpu_transcoder)));
4360 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4361 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4362 }
4363
4364 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4365 {
4366 struct drm_i915_private *dev_priv = to_i915(dev);
4367 uint32_t temp;
4368
4369 temp = I915_READ(SOUTH_CHICKEN1);
4370 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4371 return;
4372
4373 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4374 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4375
4376 temp &= ~FDI_BC_BIFURCATION_SELECT;
4377 if (enable)
4378 temp |= FDI_BC_BIFURCATION_SELECT;
4379
4380 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4381 I915_WRITE(SOUTH_CHICKEN1, temp);
4382 POSTING_READ(SOUTH_CHICKEN1);
4383 }
4384
4385 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4386 {
4387 struct drm_device *dev = intel_crtc->base.dev;
4388
4389 switch (intel_crtc->pipe) {
4390 case PIPE_A:
4391 break;
4392 case PIPE_B:
4393 if (intel_crtc->config->fdi_lanes > 2)
4394 cpt_set_fdi_bc_bifurcation(dev, false);
4395 else
4396 cpt_set_fdi_bc_bifurcation(dev, true);
4397
4398 break;
4399 case PIPE_C:
4400 cpt_set_fdi_bc_bifurcation(dev, true);
4401
4402 break;
4403 default:
4404 BUG();
4405 }
4406 }
4407
4408 /* Return which DP Port should be selected for Transcoder DP control */
4409 static enum port
4410 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4411 {
4412 struct drm_device *dev = crtc->base.dev;
4413 struct intel_encoder *encoder;
4414
4415 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4416 if (encoder->type == INTEL_OUTPUT_DP ||
4417 encoder->type == INTEL_OUTPUT_EDP)
4418 return enc_to_dig_port(&encoder->base)->port;
4419 }
4420
4421 return -1;
4422 }
4423
4424 /*
4425 * Enable PCH resources required for PCH ports:
4426 * - PCH PLLs
4427 * - FDI training & RX/TX
4428 * - update transcoder timings
4429 * - DP transcoding bits
4430 * - transcoder
4431 */
4432 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4433 {
4434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4435 struct drm_device *dev = crtc->base.dev;
4436 struct drm_i915_private *dev_priv = to_i915(dev);
4437 int pipe = crtc->pipe;
4438 u32 temp;
4439
4440 assert_pch_transcoder_disabled(dev_priv, pipe);
4441
4442 if (IS_IVYBRIDGE(dev_priv))
4443 ivybridge_update_fdi_bc_bifurcation(crtc);
4444
4445 /* Write the TU size bits before fdi link training, so that error
4446 * detection works. */
4447 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4448 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4449
4450 /* For PCH output, training FDI link */
4451 dev_priv->display.fdi_link_train(crtc, crtc_state);
4452
4453 /* We need to program the right clock selection before writing the pixel
4454 * mutliplier into the DPLL. */
4455 if (HAS_PCH_CPT(dev_priv)) {
4456 u32 sel;
4457
4458 temp = I915_READ(PCH_DPLL_SEL);
4459 temp |= TRANS_DPLL_ENABLE(pipe);
4460 sel = TRANS_DPLLB_SEL(pipe);
4461 if (crtc_state->shared_dpll ==
4462 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4463 temp |= sel;
4464 else
4465 temp &= ~sel;
4466 I915_WRITE(PCH_DPLL_SEL, temp);
4467 }
4468
4469 /* XXX: pch pll's can be enabled any time before we enable the PCH
4470 * transcoder, and we actually should do this to not upset any PCH
4471 * transcoder that already use the clock when we share it.
4472 *
4473 * Note that enable_shared_dpll tries to do the right thing, but
4474 * get_shared_dpll unconditionally resets the pll - we need that to have
4475 * the right LVDS enable sequence. */
4476 intel_enable_shared_dpll(crtc);
4477
4478 /* set transcoder timing, panel must allow it */
4479 assert_panel_unlocked(dev_priv, pipe);
4480 ironlake_pch_transcoder_set_timings(crtc, pipe);
4481
4482 intel_fdi_normal_train(crtc);
4483
4484 /* For PCH DP, enable TRANS_DP_CTL */
4485 if (HAS_PCH_CPT(dev_priv) &&
4486 intel_crtc_has_dp_encoder(crtc_state)) {
4487 const struct drm_display_mode *adjusted_mode =
4488 &crtc_state->base.adjusted_mode;
4489 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4490 i915_reg_t reg = TRANS_DP_CTL(pipe);
4491 temp = I915_READ(reg);
4492 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4493 TRANS_DP_SYNC_MASK |
4494 TRANS_DP_BPC_MASK);
4495 temp |= TRANS_DP_OUTPUT_ENABLE;
4496 temp |= bpc << 9; /* same format but at 11:9 */
4497
4498 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4499 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4500 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4501 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4502
4503 switch (intel_trans_dp_port_sel(crtc)) {
4504 case PORT_B:
4505 temp |= TRANS_DP_PORT_SEL_B;
4506 break;
4507 case PORT_C:
4508 temp |= TRANS_DP_PORT_SEL_C;
4509 break;
4510 case PORT_D:
4511 temp |= TRANS_DP_PORT_SEL_D;
4512 break;
4513 default:
4514 BUG();
4515 }
4516
4517 I915_WRITE(reg, temp);
4518 }
4519
4520 ironlake_enable_pch_transcoder(dev_priv, pipe);
4521 }
4522
4523 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4524 {
4525 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4526 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4527 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4528
4529 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4530
4531 lpt_program_iclkip(crtc);
4532
4533 /* Set transcoder timing. */
4534 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4535
4536 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4537 }
4538
4539 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4540 {
4541 struct drm_i915_private *dev_priv = to_i915(dev);
4542 i915_reg_t dslreg = PIPEDSL(pipe);
4543 u32 temp;
4544
4545 temp = I915_READ(dslreg);
4546 udelay(500);
4547 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4548 if (wait_for(I915_READ(dslreg) != temp, 5))
4549 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4550 }
4551 }
4552
4553 static int
4554 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4555 unsigned int scaler_user, int *scaler_id,
4556 int src_w, int src_h, int dst_w, int dst_h)
4557 {
4558 struct intel_crtc_scaler_state *scaler_state =
4559 &crtc_state->scaler_state;
4560 struct intel_crtc *intel_crtc =
4561 to_intel_crtc(crtc_state->base.crtc);
4562 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4563 const struct drm_display_mode *adjusted_mode =
4564 &crtc_state->base.adjusted_mode;
4565 int need_scaling;
4566
4567 /*
4568 * Src coordinates are already rotated by 270 degrees for
4569 * the 90/270 degree plane rotation cases (to match the
4570 * GTT mapping), hence no need to account for rotation here.
4571 */
4572 need_scaling = src_w != dst_w || src_h != dst_h;
4573
4574 /*
4575 * Scaling/fitting not supported in IF-ID mode in GEN9+
4576 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4577 * Once NV12 is enabled, handle it here while allocating scaler
4578 * for NV12.
4579 */
4580 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4581 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4582 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4583 return -EINVAL;
4584 }
4585
4586 /*
4587 * if plane is being disabled or scaler is no more required or force detach
4588 * - free scaler binded to this plane/crtc
4589 * - in order to do this, update crtc->scaler_usage
4590 *
4591 * Here scaler state in crtc_state is set free so that
4592 * scaler can be assigned to other user. Actual register
4593 * update to free the scaler is done in plane/panel-fit programming.
4594 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4595 */
4596 if (force_detach || !need_scaling) {
4597 if (*scaler_id >= 0) {
4598 scaler_state->scaler_users &= ~(1 << scaler_user);
4599 scaler_state->scalers[*scaler_id].in_use = 0;
4600
4601 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4602 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4603 intel_crtc->pipe, scaler_user, *scaler_id,
4604 scaler_state->scaler_users);
4605 *scaler_id = -1;
4606 }
4607 return 0;
4608 }
4609
4610 /* range checks */
4611 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4612 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4613
4614 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4615 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4616 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4617 "size is out of scaler range\n",
4618 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4619 return -EINVAL;
4620 }
4621
4622 /* mark this plane as a scaler user in crtc_state */
4623 scaler_state->scaler_users |= (1 << scaler_user);
4624 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4625 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4626 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4627 scaler_state->scaler_users);
4628
4629 return 0;
4630 }
4631
4632 /**
4633 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4634 *
4635 * @state: crtc's scaler state
4636 *
4637 * Return
4638 * 0 - scaler_usage updated successfully
4639 * error - requested scaling cannot be supported or other error condition
4640 */
4641 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4642 {
4643 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4644
4645 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4646 &state->scaler_state.scaler_id,
4647 state->pipe_src_w, state->pipe_src_h,
4648 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4649 }
4650
4651 /**
4652 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4653 *
4654 * @state: crtc's scaler state
4655 * @plane_state: atomic plane state to update
4656 *
4657 * Return
4658 * 0 - scaler_usage updated successfully
4659 * error - requested scaling cannot be supported or other error condition
4660 */
4661 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4662 struct intel_plane_state *plane_state)
4663 {
4664
4665 struct intel_plane *intel_plane =
4666 to_intel_plane(plane_state->base.plane);
4667 struct drm_framebuffer *fb = plane_state->base.fb;
4668 int ret;
4669
4670 bool force_detach = !fb || !plane_state->base.visible;
4671
4672 ret = skl_update_scaler(crtc_state, force_detach,
4673 drm_plane_index(&intel_plane->base),
4674 &plane_state->scaler_id,
4675 drm_rect_width(&plane_state->base.src) >> 16,
4676 drm_rect_height(&plane_state->base.src) >> 16,
4677 drm_rect_width(&plane_state->base.dst),
4678 drm_rect_height(&plane_state->base.dst));
4679
4680 if (ret || plane_state->scaler_id < 0)
4681 return ret;
4682
4683 /* check colorkey */
4684 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4685 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4686 intel_plane->base.base.id,
4687 intel_plane->base.name);
4688 return -EINVAL;
4689 }
4690
4691 /* Check src format */
4692 switch (fb->format->format) {
4693 case DRM_FORMAT_RGB565:
4694 case DRM_FORMAT_XBGR8888:
4695 case DRM_FORMAT_XRGB8888:
4696 case DRM_FORMAT_ABGR8888:
4697 case DRM_FORMAT_ARGB8888:
4698 case DRM_FORMAT_XRGB2101010:
4699 case DRM_FORMAT_XBGR2101010:
4700 case DRM_FORMAT_YUYV:
4701 case DRM_FORMAT_YVYU:
4702 case DRM_FORMAT_UYVY:
4703 case DRM_FORMAT_VYUY:
4704 break;
4705 default:
4706 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4707 intel_plane->base.base.id, intel_plane->base.name,
4708 fb->base.id, fb->format->format);
4709 return -EINVAL;
4710 }
4711
4712 return 0;
4713 }
4714
4715 static void skylake_scaler_disable(struct intel_crtc *crtc)
4716 {
4717 int i;
4718
4719 for (i = 0; i < crtc->num_scalers; i++)
4720 skl_detach_scaler(crtc, i);
4721 }
4722
4723 static void skylake_pfit_enable(struct intel_crtc *crtc)
4724 {
4725 struct drm_device *dev = crtc->base.dev;
4726 struct drm_i915_private *dev_priv = to_i915(dev);
4727 int pipe = crtc->pipe;
4728 struct intel_crtc_scaler_state *scaler_state =
4729 &crtc->config->scaler_state;
4730
4731 if (crtc->config->pch_pfit.enabled) {
4732 int id;
4733
4734 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4735 return;
4736
4737 id = scaler_state->scaler_id;
4738 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4739 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4740 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4741 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4742 }
4743 }
4744
4745 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4746 {
4747 struct drm_device *dev = crtc->base.dev;
4748 struct drm_i915_private *dev_priv = to_i915(dev);
4749 int pipe = crtc->pipe;
4750
4751 if (crtc->config->pch_pfit.enabled) {
4752 /* Force use of hard-coded filter coefficients
4753 * as some pre-programmed values are broken,
4754 * e.g. x201.
4755 */
4756 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4757 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4758 PF_PIPE_SEL_IVB(pipe));
4759 else
4760 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4761 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4762 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4763 }
4764 }
4765
4766 void hsw_enable_ips(struct intel_crtc *crtc)
4767 {
4768 struct drm_device *dev = crtc->base.dev;
4769 struct drm_i915_private *dev_priv = to_i915(dev);
4770
4771 if (!crtc->config->ips_enabled)
4772 return;
4773
4774 /*
4775 * We can only enable IPS after we enable a plane and wait for a vblank
4776 * This function is called from post_plane_update, which is run after
4777 * a vblank wait.
4778 */
4779
4780 assert_plane_enabled(dev_priv, crtc->plane);
4781 if (IS_BROADWELL(dev_priv)) {
4782 mutex_lock(&dev_priv->rps.hw_lock);
4783 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4784 mutex_unlock(&dev_priv->rps.hw_lock);
4785 /* Quoting Art Runyan: "its not safe to expect any particular
4786 * value in IPS_CTL bit 31 after enabling IPS through the
4787 * mailbox." Moreover, the mailbox may return a bogus state,
4788 * so we need to just enable it and continue on.
4789 */
4790 } else {
4791 I915_WRITE(IPS_CTL, IPS_ENABLE);
4792 /* The bit only becomes 1 in the next vblank, so this wait here
4793 * is essentially intel_wait_for_vblank. If we don't have this
4794 * and don't wait for vblanks until the end of crtc_enable, then
4795 * the HW state readout code will complain that the expected
4796 * IPS_CTL value is not the one we read. */
4797 if (intel_wait_for_register(dev_priv,
4798 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4799 50))
4800 DRM_ERROR("Timed out waiting for IPS enable\n");
4801 }
4802 }
4803
4804 void hsw_disable_ips(struct intel_crtc *crtc)
4805 {
4806 struct drm_device *dev = crtc->base.dev;
4807 struct drm_i915_private *dev_priv = to_i915(dev);
4808
4809 if (!crtc->config->ips_enabled)
4810 return;
4811
4812 assert_plane_enabled(dev_priv, crtc->plane);
4813 if (IS_BROADWELL(dev_priv)) {
4814 mutex_lock(&dev_priv->rps.hw_lock);
4815 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4816 mutex_unlock(&dev_priv->rps.hw_lock);
4817 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4818 if (intel_wait_for_register(dev_priv,
4819 IPS_CTL, IPS_ENABLE, 0,
4820 42))
4821 DRM_ERROR("Timed out waiting for IPS disable\n");
4822 } else {
4823 I915_WRITE(IPS_CTL, 0);
4824 POSTING_READ(IPS_CTL);
4825 }
4826
4827 /* We need to wait for a vblank before we can disable the plane. */
4828 intel_wait_for_vblank(dev_priv, crtc->pipe);
4829 }
4830
4831 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4832 {
4833 if (intel_crtc->overlay) {
4834 struct drm_device *dev = intel_crtc->base.dev;
4835
4836 mutex_lock(&dev->struct_mutex);
4837 (void) intel_overlay_switch_off(intel_crtc->overlay);
4838 mutex_unlock(&dev->struct_mutex);
4839 }
4840
4841 /* Let userspace switch the overlay on again. In most cases userspace
4842 * has to recompute where to put it anyway.
4843 */
4844 }
4845
4846 /**
4847 * intel_post_enable_primary - Perform operations after enabling primary plane
4848 * @crtc: the CRTC whose primary plane was just enabled
4849 *
4850 * Performs potentially sleeping operations that must be done after the primary
4851 * plane is enabled, such as updating FBC and IPS. Note that this may be
4852 * called due to an explicit primary plane update, or due to an implicit
4853 * re-enable that is caused when a sprite plane is updated to no longer
4854 * completely hide the primary plane.
4855 */
4856 static void
4857 intel_post_enable_primary(struct drm_crtc *crtc)
4858 {
4859 struct drm_device *dev = crtc->dev;
4860 struct drm_i915_private *dev_priv = to_i915(dev);
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862 int pipe = intel_crtc->pipe;
4863
4864 /*
4865 * FIXME IPS should be fine as long as one plane is
4866 * enabled, but in practice it seems to have problems
4867 * when going from primary only to sprite only and vice
4868 * versa.
4869 */
4870 hsw_enable_ips(intel_crtc);
4871
4872 /*
4873 * Gen2 reports pipe underruns whenever all planes are disabled.
4874 * So don't enable underrun reporting before at least some planes
4875 * are enabled.
4876 * FIXME: Need to fix the logic to work when we turn off all planes
4877 * but leave the pipe running.
4878 */
4879 if (IS_GEN2(dev_priv))
4880 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4881
4882 /* Underruns don't always raise interrupts, so check manually. */
4883 intel_check_cpu_fifo_underruns(dev_priv);
4884 intel_check_pch_fifo_underruns(dev_priv);
4885 }
4886
4887 /* FIXME move all this to pre_plane_update() with proper state tracking */
4888 static void
4889 intel_pre_disable_primary(struct drm_crtc *crtc)
4890 {
4891 struct drm_device *dev = crtc->dev;
4892 struct drm_i915_private *dev_priv = to_i915(dev);
4893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894 int pipe = intel_crtc->pipe;
4895
4896 /*
4897 * Gen2 reports pipe underruns whenever all planes are disabled.
4898 * So diasble underrun reporting before all the planes get disabled.
4899 * FIXME: Need to fix the logic to work when we turn off all planes
4900 * but leave the pipe running.
4901 */
4902 if (IS_GEN2(dev_priv))
4903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4904
4905 /*
4906 * FIXME IPS should be fine as long as one plane is
4907 * enabled, but in practice it seems to have problems
4908 * when going from primary only to sprite only and vice
4909 * versa.
4910 */
4911 hsw_disable_ips(intel_crtc);
4912 }
4913
4914 /* FIXME get rid of this and use pre_plane_update */
4915 static void
4916 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4917 {
4918 struct drm_device *dev = crtc->dev;
4919 struct drm_i915_private *dev_priv = to_i915(dev);
4920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921 int pipe = intel_crtc->pipe;
4922
4923 intel_pre_disable_primary(crtc);
4924
4925 /*
4926 * Vblank time updates from the shadow to live plane control register
4927 * are blocked if the memory self-refresh mode is active at that
4928 * moment. So to make sure the plane gets truly disabled, disable
4929 * first the self-refresh mode. The self-refresh enable bit in turn
4930 * will be checked/applied by the HW only at the next frame start
4931 * event which is after the vblank start event, so we need to have a
4932 * wait-for-vblank between disabling the plane and the pipe.
4933 */
4934 if (HAS_GMCH_DISPLAY(dev_priv) &&
4935 intel_set_memory_cxsr(dev_priv, false))
4936 intel_wait_for_vblank(dev_priv, pipe);
4937 }
4938
4939 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4940 {
4941 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4942 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4943 struct intel_crtc_state *pipe_config =
4944 to_intel_crtc_state(crtc->base.state);
4945 struct drm_plane *primary = crtc->base.primary;
4946 struct drm_plane_state *old_pri_state =
4947 drm_atomic_get_existing_plane_state(old_state, primary);
4948
4949 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4950
4951 if (pipe_config->update_wm_post && pipe_config->base.active)
4952 intel_update_watermarks(crtc);
4953
4954 if (old_pri_state) {
4955 struct intel_plane_state *primary_state =
4956 to_intel_plane_state(primary->state);
4957 struct intel_plane_state *old_primary_state =
4958 to_intel_plane_state(old_pri_state);
4959
4960 intel_fbc_post_update(crtc);
4961
4962 if (primary_state->base.visible &&
4963 (needs_modeset(&pipe_config->base) ||
4964 !old_primary_state->base.visible))
4965 intel_post_enable_primary(&crtc->base);
4966 }
4967 }
4968
4969 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
4970 struct intel_crtc_state *pipe_config)
4971 {
4972 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4973 struct drm_device *dev = crtc->base.dev;
4974 struct drm_i915_private *dev_priv = to_i915(dev);
4975 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4976 struct drm_plane *primary = crtc->base.primary;
4977 struct drm_plane_state *old_pri_state =
4978 drm_atomic_get_existing_plane_state(old_state, primary);
4979 bool modeset = needs_modeset(&pipe_config->base);
4980 struct intel_atomic_state *old_intel_state =
4981 to_intel_atomic_state(old_state);
4982
4983 if (old_pri_state) {
4984 struct intel_plane_state *primary_state =
4985 to_intel_plane_state(primary->state);
4986 struct intel_plane_state *old_primary_state =
4987 to_intel_plane_state(old_pri_state);
4988
4989 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4990
4991 if (old_primary_state->base.visible &&
4992 (modeset || !primary_state->base.visible))
4993 intel_pre_disable_primary(&crtc->base);
4994 }
4995
4996 /*
4997 * Vblank time updates from the shadow to live plane control register
4998 * are blocked if the memory self-refresh mode is active at that
4999 * moment. So to make sure the plane gets truly disabled, disable
5000 * first the self-refresh mode. The self-refresh enable bit in turn
5001 * will be checked/applied by the HW only at the next frame start
5002 * event which is after the vblank start event, so we need to have a
5003 * wait-for-vblank between disabling the plane and the pipe.
5004 */
5005 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5006 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5007 intel_wait_for_vblank(dev_priv, crtc->pipe);
5008
5009 /*
5010 * IVB workaround: must disable low power watermarks for at least
5011 * one frame before enabling scaling. LP watermarks can be re-enabled
5012 * when scaling is disabled.
5013 *
5014 * WaCxSRDisabledForSpriteScaling:ivb
5015 */
5016 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5017 intel_wait_for_vblank(dev_priv, crtc->pipe);
5018
5019 /*
5020 * If we're doing a modeset, we're done. No need to do any pre-vblank
5021 * watermark programming here.
5022 */
5023 if (needs_modeset(&pipe_config->base))
5024 return;
5025
5026 /*
5027 * For platforms that support atomic watermarks, program the
5028 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5029 * will be the intermediate values that are safe for both pre- and
5030 * post- vblank; when vblank happens, the 'active' values will be set
5031 * to the final 'target' values and we'll do this again to get the
5032 * optimal watermarks. For gen9+ platforms, the values we program here
5033 * will be the final target values which will get automatically latched
5034 * at vblank time; no further programming will be necessary.
5035 *
5036 * If a platform hasn't been transitioned to atomic watermarks yet,
5037 * we'll continue to update watermarks the old way, if flags tell
5038 * us to.
5039 */
5040 if (dev_priv->display.initial_watermarks != NULL)
5041 dev_priv->display.initial_watermarks(old_intel_state,
5042 pipe_config);
5043 else if (pipe_config->update_wm_pre)
5044 intel_update_watermarks(crtc);
5045 }
5046
5047 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5048 {
5049 struct drm_device *dev = crtc->dev;
5050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051 struct drm_plane *p;
5052 int pipe = intel_crtc->pipe;
5053
5054 intel_crtc_dpms_overlay_disable(intel_crtc);
5055
5056 drm_for_each_plane_mask(p, dev, plane_mask)
5057 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5058
5059 /*
5060 * FIXME: Once we grow proper nuclear flip support out of this we need
5061 * to compute the mask of flip planes precisely. For the time being
5062 * consider this a flip to a NULL plane.
5063 */
5064 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5065 }
5066
5067 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5068 struct intel_crtc_state *crtc_state,
5069 struct drm_atomic_state *old_state)
5070 {
5071 struct drm_connector_state *conn_state;
5072 struct drm_connector *conn;
5073 int i;
5074
5075 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5076 struct intel_encoder *encoder =
5077 to_intel_encoder(conn_state->best_encoder);
5078
5079 if (conn_state->crtc != crtc)
5080 continue;
5081
5082 if (encoder->pre_pll_enable)
5083 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5084 }
5085 }
5086
5087 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5088 struct intel_crtc_state *crtc_state,
5089 struct drm_atomic_state *old_state)
5090 {
5091 struct drm_connector_state *conn_state;
5092 struct drm_connector *conn;
5093 int i;
5094
5095 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5096 struct intel_encoder *encoder =
5097 to_intel_encoder(conn_state->best_encoder);
5098
5099 if (conn_state->crtc != crtc)
5100 continue;
5101
5102 if (encoder->pre_enable)
5103 encoder->pre_enable(encoder, crtc_state, conn_state);
5104 }
5105 }
5106
5107 static void intel_encoders_enable(struct drm_crtc *crtc,
5108 struct intel_crtc_state *crtc_state,
5109 struct drm_atomic_state *old_state)
5110 {
5111 struct drm_connector_state *conn_state;
5112 struct drm_connector *conn;
5113 int i;
5114
5115 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5116 struct intel_encoder *encoder =
5117 to_intel_encoder(conn_state->best_encoder);
5118
5119 if (conn_state->crtc != crtc)
5120 continue;
5121
5122 encoder->enable(encoder, crtc_state, conn_state);
5123 intel_opregion_notify_encoder(encoder, true);
5124 }
5125 }
5126
5127 static void intel_encoders_disable(struct drm_crtc *crtc,
5128 struct intel_crtc_state *old_crtc_state,
5129 struct drm_atomic_state *old_state)
5130 {
5131 struct drm_connector_state *old_conn_state;
5132 struct drm_connector *conn;
5133 int i;
5134
5135 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5136 struct intel_encoder *encoder =
5137 to_intel_encoder(old_conn_state->best_encoder);
5138
5139 if (old_conn_state->crtc != crtc)
5140 continue;
5141
5142 intel_opregion_notify_encoder(encoder, false);
5143 encoder->disable(encoder, old_crtc_state, old_conn_state);
5144 }
5145 }
5146
5147 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5148 struct intel_crtc_state *old_crtc_state,
5149 struct drm_atomic_state *old_state)
5150 {
5151 struct drm_connector_state *old_conn_state;
5152 struct drm_connector *conn;
5153 int i;
5154
5155 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5156 struct intel_encoder *encoder =
5157 to_intel_encoder(old_conn_state->best_encoder);
5158
5159 if (old_conn_state->crtc != crtc)
5160 continue;
5161
5162 if (encoder->post_disable)
5163 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5164 }
5165 }
5166
5167 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5168 struct intel_crtc_state *old_crtc_state,
5169 struct drm_atomic_state *old_state)
5170 {
5171 struct drm_connector_state *old_conn_state;
5172 struct drm_connector *conn;
5173 int i;
5174
5175 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5176 struct intel_encoder *encoder =
5177 to_intel_encoder(old_conn_state->best_encoder);
5178
5179 if (old_conn_state->crtc != crtc)
5180 continue;
5181
5182 if (encoder->post_pll_disable)
5183 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5184 }
5185 }
5186
5187 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5188 struct drm_atomic_state *old_state)
5189 {
5190 struct drm_crtc *crtc = pipe_config->base.crtc;
5191 struct drm_device *dev = crtc->dev;
5192 struct drm_i915_private *dev_priv = to_i915(dev);
5193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194 int pipe = intel_crtc->pipe;
5195 struct intel_atomic_state *old_intel_state =
5196 to_intel_atomic_state(old_state);
5197
5198 if (WARN_ON(intel_crtc->active))
5199 return;
5200
5201 /*
5202 * Sometimes spurious CPU pipe underruns happen during FDI
5203 * training, at least with VGA+HDMI cloning. Suppress them.
5204 *
5205 * On ILK we get an occasional spurious CPU pipe underruns
5206 * between eDP port A enable and vdd enable. Also PCH port
5207 * enable seems to result in the occasional CPU pipe underrun.
5208 *
5209 * Spurious PCH underruns also occur during PCH enabling.
5210 */
5211 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5212 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5213 if (intel_crtc->config->has_pch_encoder)
5214 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5215
5216 if (intel_crtc->config->has_pch_encoder)
5217 intel_prepare_shared_dpll(intel_crtc);
5218
5219 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5220 intel_dp_set_m_n(intel_crtc, M1_N1);
5221
5222 intel_set_pipe_timings(intel_crtc);
5223 intel_set_pipe_src_size(intel_crtc);
5224
5225 if (intel_crtc->config->has_pch_encoder) {
5226 intel_cpu_transcoder_set_m_n(intel_crtc,
5227 &intel_crtc->config->fdi_m_n, NULL);
5228 }
5229
5230 ironlake_set_pipeconf(crtc);
5231
5232 intel_crtc->active = true;
5233
5234 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5235
5236 if (intel_crtc->config->has_pch_encoder) {
5237 /* Note: FDI PLL enabling _must_ be done before we enable the
5238 * cpu pipes, hence this is separate from all the other fdi/pch
5239 * enabling. */
5240 ironlake_fdi_pll_enable(intel_crtc);
5241 } else {
5242 assert_fdi_tx_disabled(dev_priv, pipe);
5243 assert_fdi_rx_disabled(dev_priv, pipe);
5244 }
5245
5246 ironlake_pfit_enable(intel_crtc);
5247
5248 /*
5249 * On ILK+ LUT must be loaded before the pipe is running but with
5250 * clocks enabled
5251 */
5252 intel_color_load_luts(&pipe_config->base);
5253
5254 if (dev_priv->display.initial_watermarks != NULL)
5255 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5256 intel_enable_pipe(intel_crtc);
5257
5258 if (intel_crtc->config->has_pch_encoder)
5259 ironlake_pch_enable(pipe_config);
5260
5261 assert_vblank_disabled(crtc);
5262 drm_crtc_vblank_on(crtc);
5263
5264 intel_encoders_enable(crtc, pipe_config, old_state);
5265
5266 if (HAS_PCH_CPT(dev_priv))
5267 cpt_verify_modeset(dev, intel_crtc->pipe);
5268
5269 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5270 if (intel_crtc->config->has_pch_encoder)
5271 intel_wait_for_vblank(dev_priv, pipe);
5272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5273 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5274 }
5275
5276 /* IPS only exists on ULT machines and is tied to pipe A. */
5277 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5278 {
5279 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5280 }
5281
5282 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5283 struct drm_atomic_state *old_state)
5284 {
5285 struct drm_crtc *crtc = pipe_config->base.crtc;
5286 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5288 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5289 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5290 struct intel_atomic_state *old_intel_state =
5291 to_intel_atomic_state(old_state);
5292
5293 if (WARN_ON(intel_crtc->active))
5294 return;
5295
5296 if (intel_crtc->config->has_pch_encoder)
5297 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5298
5299 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5300
5301 if (intel_crtc->config->shared_dpll)
5302 intel_enable_shared_dpll(intel_crtc);
5303
5304 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5305 intel_dp_set_m_n(intel_crtc, M1_N1);
5306
5307 if (!transcoder_is_dsi(cpu_transcoder))
5308 intel_set_pipe_timings(intel_crtc);
5309
5310 intel_set_pipe_src_size(intel_crtc);
5311
5312 if (cpu_transcoder != TRANSCODER_EDP &&
5313 !transcoder_is_dsi(cpu_transcoder)) {
5314 I915_WRITE(PIPE_MULT(cpu_transcoder),
5315 intel_crtc->config->pixel_multiplier - 1);
5316 }
5317
5318 if (intel_crtc->config->has_pch_encoder) {
5319 intel_cpu_transcoder_set_m_n(intel_crtc,
5320 &intel_crtc->config->fdi_m_n, NULL);
5321 }
5322
5323 if (!transcoder_is_dsi(cpu_transcoder))
5324 haswell_set_pipeconf(crtc);
5325
5326 haswell_set_pipemisc(crtc);
5327
5328 intel_color_set_csc(&pipe_config->base);
5329
5330 intel_crtc->active = true;
5331
5332 if (intel_crtc->config->has_pch_encoder)
5333 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5334 else
5335 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5336
5337 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5338
5339 if (intel_crtc->config->has_pch_encoder)
5340 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5341
5342 if (!transcoder_is_dsi(cpu_transcoder))
5343 intel_ddi_enable_pipe_clock(pipe_config);
5344
5345 if (INTEL_GEN(dev_priv) >= 9)
5346 skylake_pfit_enable(intel_crtc);
5347 else
5348 ironlake_pfit_enable(intel_crtc);
5349
5350 /*
5351 * On ILK+ LUT must be loaded before the pipe is running but with
5352 * clocks enabled
5353 */
5354 intel_color_load_luts(&pipe_config->base);
5355
5356 intel_ddi_set_pipe_settings(pipe_config);
5357 if (!transcoder_is_dsi(cpu_transcoder))
5358 intel_ddi_enable_transcoder_func(pipe_config);
5359
5360 if (dev_priv->display.initial_watermarks != NULL)
5361 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5362
5363 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5364 if (!transcoder_is_dsi(cpu_transcoder))
5365 intel_enable_pipe(intel_crtc);
5366
5367 if (intel_crtc->config->has_pch_encoder)
5368 lpt_pch_enable(pipe_config);
5369
5370 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5371 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5372
5373 assert_vblank_disabled(crtc);
5374 drm_crtc_vblank_on(crtc);
5375
5376 intel_encoders_enable(crtc, pipe_config, old_state);
5377
5378 if (intel_crtc->config->has_pch_encoder) {
5379 intel_wait_for_vblank(dev_priv, pipe);
5380 intel_wait_for_vblank(dev_priv, pipe);
5381 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5382 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5383 }
5384
5385 /* If we change the relative order between pipe/planes enabling, we need
5386 * to change the workaround. */
5387 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5388 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5389 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5390 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5391 }
5392 }
5393
5394 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5395 {
5396 struct drm_device *dev = crtc->base.dev;
5397 struct drm_i915_private *dev_priv = to_i915(dev);
5398 int pipe = crtc->pipe;
5399
5400 /* To avoid upsetting the power well on haswell only disable the pfit if
5401 * it's in use. The hw state code will make sure we get this right. */
5402 if (force || crtc->config->pch_pfit.enabled) {
5403 I915_WRITE(PF_CTL(pipe), 0);
5404 I915_WRITE(PF_WIN_POS(pipe), 0);
5405 I915_WRITE(PF_WIN_SZ(pipe), 0);
5406 }
5407 }
5408
5409 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5410 struct drm_atomic_state *old_state)
5411 {
5412 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5413 struct drm_device *dev = crtc->dev;
5414 struct drm_i915_private *dev_priv = to_i915(dev);
5415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5416 int pipe = intel_crtc->pipe;
5417
5418 /*
5419 * Sometimes spurious CPU pipe underruns happen when the
5420 * pipe is already disabled, but FDI RX/TX is still enabled.
5421 * Happens at least with VGA+HDMI cloning. Suppress them.
5422 */
5423 if (intel_crtc->config->has_pch_encoder) {
5424 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5425 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5426 }
5427
5428 intel_encoders_disable(crtc, old_crtc_state, old_state);
5429
5430 drm_crtc_vblank_off(crtc);
5431 assert_vblank_disabled(crtc);
5432
5433 intel_disable_pipe(intel_crtc);
5434
5435 ironlake_pfit_disable(intel_crtc, false);
5436
5437 if (intel_crtc->config->has_pch_encoder)
5438 ironlake_fdi_disable(crtc);
5439
5440 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5441
5442 if (intel_crtc->config->has_pch_encoder) {
5443 ironlake_disable_pch_transcoder(dev_priv, pipe);
5444
5445 if (HAS_PCH_CPT(dev_priv)) {
5446 i915_reg_t reg;
5447 u32 temp;
5448
5449 /* disable TRANS_DP_CTL */
5450 reg = TRANS_DP_CTL(pipe);
5451 temp = I915_READ(reg);
5452 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5453 TRANS_DP_PORT_SEL_MASK);
5454 temp |= TRANS_DP_PORT_SEL_NONE;
5455 I915_WRITE(reg, temp);
5456
5457 /* disable DPLL_SEL */
5458 temp = I915_READ(PCH_DPLL_SEL);
5459 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5460 I915_WRITE(PCH_DPLL_SEL, temp);
5461 }
5462
5463 ironlake_fdi_pll_disable(intel_crtc);
5464 }
5465
5466 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5467 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5468 }
5469
5470 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5471 struct drm_atomic_state *old_state)
5472 {
5473 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5474 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5476 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5477
5478 if (intel_crtc->config->has_pch_encoder)
5479 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5480
5481 intel_encoders_disable(crtc, old_crtc_state, old_state);
5482
5483 drm_crtc_vblank_off(crtc);
5484 assert_vblank_disabled(crtc);
5485
5486 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5487 if (!transcoder_is_dsi(cpu_transcoder))
5488 intel_disable_pipe(intel_crtc);
5489
5490 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5491 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5492
5493 if (!transcoder_is_dsi(cpu_transcoder))
5494 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5495
5496 if (INTEL_GEN(dev_priv) >= 9)
5497 skylake_scaler_disable(intel_crtc);
5498 else
5499 ironlake_pfit_disable(intel_crtc, false);
5500
5501 if (!transcoder_is_dsi(cpu_transcoder))
5502 intel_ddi_disable_pipe_clock(intel_crtc->config);
5503
5504 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5505
5506 if (old_crtc_state->has_pch_encoder)
5507 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5508 }
5509
5510 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5511 {
5512 struct drm_device *dev = crtc->base.dev;
5513 struct drm_i915_private *dev_priv = to_i915(dev);
5514 struct intel_crtc_state *pipe_config = crtc->config;
5515
5516 if (!pipe_config->gmch_pfit.control)
5517 return;
5518
5519 /*
5520 * The panel fitter should only be adjusted whilst the pipe is disabled,
5521 * according to register description and PRM.
5522 */
5523 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5524 assert_pipe_disabled(dev_priv, crtc->pipe);
5525
5526 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5527 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5528
5529 /* Border color in case we don't scale up to the full screen. Black by
5530 * default, change to something else for debugging. */
5531 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5532 }
5533
5534 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5535 {
5536 switch (port) {
5537 case PORT_A:
5538 return POWER_DOMAIN_PORT_DDI_A_LANES;
5539 case PORT_B:
5540 return POWER_DOMAIN_PORT_DDI_B_LANES;
5541 case PORT_C:
5542 return POWER_DOMAIN_PORT_DDI_C_LANES;
5543 case PORT_D:
5544 return POWER_DOMAIN_PORT_DDI_D_LANES;
5545 case PORT_E:
5546 return POWER_DOMAIN_PORT_DDI_E_LANES;
5547 default:
5548 MISSING_CASE(port);
5549 return POWER_DOMAIN_PORT_OTHER;
5550 }
5551 }
5552
5553 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5554 struct intel_crtc_state *crtc_state)
5555 {
5556 struct drm_device *dev = crtc->dev;
5557 struct drm_i915_private *dev_priv = to_i915(dev);
5558 struct drm_encoder *encoder;
5559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5560 enum pipe pipe = intel_crtc->pipe;
5561 u64 mask;
5562 enum transcoder transcoder = crtc_state->cpu_transcoder;
5563
5564 if (!crtc_state->base.active)
5565 return 0;
5566
5567 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5568 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5569 if (crtc_state->pch_pfit.enabled ||
5570 crtc_state->pch_pfit.force_thru)
5571 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5572
5573 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5574 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5575
5576 mask |= BIT_ULL(intel_encoder->power_domain);
5577 }
5578
5579 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5580 mask |= BIT(POWER_DOMAIN_AUDIO);
5581
5582 if (crtc_state->shared_dpll)
5583 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5584
5585 return mask;
5586 }
5587
5588 static u64
5589 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5590 struct intel_crtc_state *crtc_state)
5591 {
5592 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5594 enum intel_display_power_domain domain;
5595 u64 domains, new_domains, old_domains;
5596
5597 old_domains = intel_crtc->enabled_power_domains;
5598 intel_crtc->enabled_power_domains = new_domains =
5599 get_crtc_power_domains(crtc, crtc_state);
5600
5601 domains = new_domains & ~old_domains;
5602
5603 for_each_power_domain(domain, domains)
5604 intel_display_power_get(dev_priv, domain);
5605
5606 return old_domains & ~new_domains;
5607 }
5608
5609 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5610 u64 domains)
5611 {
5612 enum intel_display_power_domain domain;
5613
5614 for_each_power_domain(domain, domains)
5615 intel_display_power_put(dev_priv, domain);
5616 }
5617
5618 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5619 struct drm_atomic_state *old_state)
5620 {
5621 struct intel_atomic_state *old_intel_state =
5622 to_intel_atomic_state(old_state);
5623 struct drm_crtc *crtc = pipe_config->base.crtc;
5624 struct drm_device *dev = crtc->dev;
5625 struct drm_i915_private *dev_priv = to_i915(dev);
5626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5627 int pipe = intel_crtc->pipe;
5628
5629 if (WARN_ON(intel_crtc->active))
5630 return;
5631
5632 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5633 intel_dp_set_m_n(intel_crtc, M1_N1);
5634
5635 intel_set_pipe_timings(intel_crtc);
5636 intel_set_pipe_src_size(intel_crtc);
5637
5638 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5639 struct drm_i915_private *dev_priv = to_i915(dev);
5640
5641 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5642 I915_WRITE(CHV_CANVAS(pipe), 0);
5643 }
5644
5645 i9xx_set_pipeconf(intel_crtc);
5646
5647 intel_crtc->active = true;
5648
5649 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5650
5651 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5652
5653 if (IS_CHERRYVIEW(dev_priv)) {
5654 chv_prepare_pll(intel_crtc, intel_crtc->config);
5655 chv_enable_pll(intel_crtc, intel_crtc->config);
5656 } else {
5657 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5658 vlv_enable_pll(intel_crtc, intel_crtc->config);
5659 }
5660
5661 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5662
5663 i9xx_pfit_enable(intel_crtc);
5664
5665 intel_color_load_luts(&pipe_config->base);
5666
5667 dev_priv->display.initial_watermarks(old_intel_state,
5668 pipe_config);
5669 intel_enable_pipe(intel_crtc);
5670
5671 assert_vblank_disabled(crtc);
5672 drm_crtc_vblank_on(crtc);
5673
5674 intel_encoders_enable(crtc, pipe_config, old_state);
5675 }
5676
5677 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5678 {
5679 struct drm_device *dev = crtc->base.dev;
5680 struct drm_i915_private *dev_priv = to_i915(dev);
5681
5682 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5683 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5684 }
5685
5686 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5687 struct drm_atomic_state *old_state)
5688 {
5689 struct intel_atomic_state *old_intel_state =
5690 to_intel_atomic_state(old_state);
5691 struct drm_crtc *crtc = pipe_config->base.crtc;
5692 struct drm_device *dev = crtc->dev;
5693 struct drm_i915_private *dev_priv = to_i915(dev);
5694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5695 enum pipe pipe = intel_crtc->pipe;
5696
5697 if (WARN_ON(intel_crtc->active))
5698 return;
5699
5700 i9xx_set_pll_dividers(intel_crtc);
5701
5702 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5703 intel_dp_set_m_n(intel_crtc, M1_N1);
5704
5705 intel_set_pipe_timings(intel_crtc);
5706 intel_set_pipe_src_size(intel_crtc);
5707
5708 i9xx_set_pipeconf(intel_crtc);
5709
5710 intel_crtc->active = true;
5711
5712 if (!IS_GEN2(dev_priv))
5713 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5714
5715 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5716
5717 i9xx_enable_pll(intel_crtc);
5718
5719 i9xx_pfit_enable(intel_crtc);
5720
5721 intel_color_load_luts(&pipe_config->base);
5722
5723 if (dev_priv->display.initial_watermarks != NULL)
5724 dev_priv->display.initial_watermarks(old_intel_state,
5725 intel_crtc->config);
5726 else
5727 intel_update_watermarks(intel_crtc);
5728 intel_enable_pipe(intel_crtc);
5729
5730 assert_vblank_disabled(crtc);
5731 drm_crtc_vblank_on(crtc);
5732
5733 intel_encoders_enable(crtc, pipe_config, old_state);
5734 }
5735
5736 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5737 {
5738 struct drm_device *dev = crtc->base.dev;
5739 struct drm_i915_private *dev_priv = to_i915(dev);
5740
5741 if (!crtc->config->gmch_pfit.control)
5742 return;
5743
5744 assert_pipe_disabled(dev_priv, crtc->pipe);
5745
5746 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5747 I915_READ(PFIT_CONTROL));
5748 I915_WRITE(PFIT_CONTROL, 0);
5749 }
5750
5751 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5752 struct drm_atomic_state *old_state)
5753 {
5754 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5755 struct drm_device *dev = crtc->dev;
5756 struct drm_i915_private *dev_priv = to_i915(dev);
5757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758 int pipe = intel_crtc->pipe;
5759
5760 /*
5761 * On gen2 planes are double buffered but the pipe isn't, so we must
5762 * wait for planes to fully turn off before disabling the pipe.
5763 */
5764 if (IS_GEN2(dev_priv))
5765 intel_wait_for_vblank(dev_priv, pipe);
5766
5767 intel_encoders_disable(crtc, old_crtc_state, old_state);
5768
5769 drm_crtc_vblank_off(crtc);
5770 assert_vblank_disabled(crtc);
5771
5772 intel_disable_pipe(intel_crtc);
5773
5774 i9xx_pfit_disable(intel_crtc);
5775
5776 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5777
5778 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5779 if (IS_CHERRYVIEW(dev_priv))
5780 chv_disable_pll(dev_priv, pipe);
5781 else if (IS_VALLEYVIEW(dev_priv))
5782 vlv_disable_pll(dev_priv, pipe);
5783 else
5784 i9xx_disable_pll(intel_crtc);
5785 }
5786
5787 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5788
5789 if (!IS_GEN2(dev_priv))
5790 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5791
5792 if (!dev_priv->display.initial_watermarks)
5793 intel_update_watermarks(intel_crtc);
5794
5795 /* clock the pipe down to 640x480@60 to potentially save power */
5796 if (IS_I830(dev_priv))
5797 i830_enable_pipe(dev_priv, pipe);
5798 }
5799
5800 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5801 struct drm_modeset_acquire_ctx *ctx)
5802 {
5803 struct intel_encoder *encoder;
5804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5805 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5806 enum intel_display_power_domain domain;
5807 u64 domains;
5808 struct drm_atomic_state *state;
5809 struct intel_crtc_state *crtc_state;
5810 int ret;
5811
5812 if (!intel_crtc->active)
5813 return;
5814
5815 if (crtc->primary->state->visible) {
5816 WARN_ON(intel_crtc->flip_work);
5817
5818 intel_pre_disable_primary_noatomic(crtc);
5819
5820 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5821 crtc->primary->state->visible = false;
5822 }
5823
5824 state = drm_atomic_state_alloc(crtc->dev);
5825 if (!state) {
5826 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5827 crtc->base.id, crtc->name);
5828 return;
5829 }
5830
5831 state->acquire_ctx = ctx;
5832
5833 /* Everything's already locked, -EDEADLK can't happen. */
5834 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5835 ret = drm_atomic_add_affected_connectors(state, crtc);
5836
5837 WARN_ON(IS_ERR(crtc_state) || ret);
5838
5839 dev_priv->display.crtc_disable(crtc_state, state);
5840
5841 drm_atomic_state_put(state);
5842
5843 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5844 crtc->base.id, crtc->name);
5845
5846 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5847 crtc->state->active = false;
5848 intel_crtc->active = false;
5849 crtc->enabled = false;
5850 crtc->state->connector_mask = 0;
5851 crtc->state->encoder_mask = 0;
5852
5853 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5854 encoder->base.crtc = NULL;
5855
5856 intel_fbc_disable(intel_crtc);
5857 intel_update_watermarks(intel_crtc);
5858 intel_disable_shared_dpll(intel_crtc);
5859
5860 domains = intel_crtc->enabled_power_domains;
5861 for_each_power_domain(domain, domains)
5862 intel_display_power_put(dev_priv, domain);
5863 intel_crtc->enabled_power_domains = 0;
5864
5865 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5866 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5867 }
5868
5869 /*
5870 * turn all crtc's off, but do not adjust state
5871 * This has to be paired with a call to intel_modeset_setup_hw_state.
5872 */
5873 int intel_display_suspend(struct drm_device *dev)
5874 {
5875 struct drm_i915_private *dev_priv = to_i915(dev);
5876 struct drm_atomic_state *state;
5877 int ret;
5878
5879 state = drm_atomic_helper_suspend(dev);
5880 ret = PTR_ERR_OR_ZERO(state);
5881 if (ret)
5882 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5883 else
5884 dev_priv->modeset_restore_state = state;
5885 return ret;
5886 }
5887
5888 void intel_encoder_destroy(struct drm_encoder *encoder)
5889 {
5890 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5891
5892 drm_encoder_cleanup(encoder);
5893 kfree(intel_encoder);
5894 }
5895
5896 /* Cross check the actual hw state with our own modeset state tracking (and it's
5897 * internal consistency). */
5898 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5899 struct drm_connector_state *conn_state)
5900 {
5901 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5902
5903 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5904 connector->base.base.id,
5905 connector->base.name);
5906
5907 if (connector->get_hw_state(connector)) {
5908 struct intel_encoder *encoder = connector->encoder;
5909
5910 I915_STATE_WARN(!crtc_state,
5911 "connector enabled without attached crtc\n");
5912
5913 if (!crtc_state)
5914 return;
5915
5916 I915_STATE_WARN(!crtc_state->active,
5917 "connector is active, but attached crtc isn't\n");
5918
5919 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5920 return;
5921
5922 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5923 "atomic encoder doesn't match attached encoder\n");
5924
5925 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5926 "attached encoder crtc differs from connector crtc\n");
5927 } else {
5928 I915_STATE_WARN(crtc_state && crtc_state->active,
5929 "attached crtc is active, but connector isn't\n");
5930 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5931 "best encoder set without crtc!\n");
5932 }
5933 }
5934
5935 int intel_connector_init(struct intel_connector *connector)
5936 {
5937 struct intel_digital_connector_state *conn_state;
5938
5939 /*
5940 * Allocate enough memory to hold intel_digital_connector_state,
5941 * This might be a few bytes too many, but for connectors that don't
5942 * need it we'll free the state and allocate a smaller one on the first
5943 * succesful commit anyway.
5944 */
5945 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
5946 if (!conn_state)
5947 return -ENOMEM;
5948
5949 __drm_atomic_helper_connector_reset(&connector->base,
5950 &conn_state->base);
5951
5952 return 0;
5953 }
5954
5955 struct intel_connector *intel_connector_alloc(void)
5956 {
5957 struct intel_connector *connector;
5958
5959 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5960 if (!connector)
5961 return NULL;
5962
5963 if (intel_connector_init(connector) < 0) {
5964 kfree(connector);
5965 return NULL;
5966 }
5967
5968 return connector;
5969 }
5970
5971 /* Simple connector->get_hw_state implementation for encoders that support only
5972 * one connector and no cloning and hence the encoder state determines the state
5973 * of the connector. */
5974 bool intel_connector_get_hw_state(struct intel_connector *connector)
5975 {
5976 enum pipe pipe = 0;
5977 struct intel_encoder *encoder = connector->encoder;
5978
5979 return encoder->get_hw_state(encoder, &pipe);
5980 }
5981
5982 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5983 {
5984 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5985 return crtc_state->fdi_lanes;
5986
5987 return 0;
5988 }
5989
5990 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5991 struct intel_crtc_state *pipe_config)
5992 {
5993 struct drm_i915_private *dev_priv = to_i915(dev);
5994 struct drm_atomic_state *state = pipe_config->base.state;
5995 struct intel_crtc *other_crtc;
5996 struct intel_crtc_state *other_crtc_state;
5997
5998 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5999 pipe_name(pipe), pipe_config->fdi_lanes);
6000 if (pipe_config->fdi_lanes > 4) {
6001 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6002 pipe_name(pipe), pipe_config->fdi_lanes);
6003 return -EINVAL;
6004 }
6005
6006 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6007 if (pipe_config->fdi_lanes > 2) {
6008 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6009 pipe_config->fdi_lanes);
6010 return -EINVAL;
6011 } else {
6012 return 0;
6013 }
6014 }
6015
6016 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6017 return 0;
6018
6019 /* Ivybridge 3 pipe is really complicated */
6020 switch (pipe) {
6021 case PIPE_A:
6022 return 0;
6023 case PIPE_B:
6024 if (pipe_config->fdi_lanes <= 2)
6025 return 0;
6026
6027 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6028 other_crtc_state =
6029 intel_atomic_get_crtc_state(state, other_crtc);
6030 if (IS_ERR(other_crtc_state))
6031 return PTR_ERR(other_crtc_state);
6032
6033 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6034 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6035 pipe_name(pipe), pipe_config->fdi_lanes);
6036 return -EINVAL;
6037 }
6038 return 0;
6039 case PIPE_C:
6040 if (pipe_config->fdi_lanes > 2) {
6041 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6042 pipe_name(pipe), pipe_config->fdi_lanes);
6043 return -EINVAL;
6044 }
6045
6046 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6047 other_crtc_state =
6048 intel_atomic_get_crtc_state(state, other_crtc);
6049 if (IS_ERR(other_crtc_state))
6050 return PTR_ERR(other_crtc_state);
6051
6052 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6053 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6054 return -EINVAL;
6055 }
6056 return 0;
6057 default:
6058 BUG();
6059 }
6060 }
6061
6062 #define RETRY 1
6063 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6064 struct intel_crtc_state *pipe_config)
6065 {
6066 struct drm_device *dev = intel_crtc->base.dev;
6067 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6068 int lane, link_bw, fdi_dotclock, ret;
6069 bool needs_recompute = false;
6070
6071 retry:
6072 /* FDI is a binary signal running at ~2.7GHz, encoding
6073 * each output octet as 10 bits. The actual frequency
6074 * is stored as a divider into a 100MHz clock, and the
6075 * mode pixel clock is stored in units of 1KHz.
6076 * Hence the bw of each lane in terms of the mode signal
6077 * is:
6078 */
6079 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6080
6081 fdi_dotclock = adjusted_mode->crtc_clock;
6082
6083 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6084 pipe_config->pipe_bpp);
6085
6086 pipe_config->fdi_lanes = lane;
6087
6088 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6089 link_bw, &pipe_config->fdi_m_n, false);
6090
6091 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6092 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6093 pipe_config->pipe_bpp -= 2*3;
6094 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6095 pipe_config->pipe_bpp);
6096 needs_recompute = true;
6097 pipe_config->bw_constrained = true;
6098
6099 goto retry;
6100 }
6101
6102 if (needs_recompute)
6103 return RETRY;
6104
6105 return ret;
6106 }
6107
6108 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6109 struct intel_crtc_state *pipe_config)
6110 {
6111 if (pipe_config->pipe_bpp > 24)
6112 return false;
6113
6114 /* HSW can handle pixel rate up to cdclk? */
6115 if (IS_HASWELL(dev_priv))
6116 return true;
6117
6118 /*
6119 * We compare against max which means we must take
6120 * the increased cdclk requirement into account when
6121 * calculating the new cdclk.
6122 *
6123 * Should measure whether using a lower cdclk w/o IPS
6124 */
6125 return pipe_config->pixel_rate <=
6126 dev_priv->max_cdclk_freq * 95 / 100;
6127 }
6128
6129 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6130 struct intel_crtc_state *pipe_config)
6131 {
6132 struct drm_device *dev = crtc->base.dev;
6133 struct drm_i915_private *dev_priv = to_i915(dev);
6134
6135 pipe_config->ips_enabled = i915.enable_ips &&
6136 hsw_crtc_supports_ips(crtc) &&
6137 pipe_config_supports_ips(dev_priv, pipe_config);
6138 }
6139
6140 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6141 {
6142 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6143
6144 /* GDG double wide on either pipe, otherwise pipe A only */
6145 return INTEL_INFO(dev_priv)->gen < 4 &&
6146 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6147 }
6148
6149 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6150 {
6151 uint32_t pixel_rate;
6152
6153 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6154
6155 /*
6156 * We only use IF-ID interlacing. If we ever use
6157 * PF-ID we'll need to adjust the pixel_rate here.
6158 */
6159
6160 if (pipe_config->pch_pfit.enabled) {
6161 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6162 uint32_t pfit_size = pipe_config->pch_pfit.size;
6163
6164 pipe_w = pipe_config->pipe_src_w;
6165 pipe_h = pipe_config->pipe_src_h;
6166
6167 pfit_w = (pfit_size >> 16) & 0xFFFF;
6168 pfit_h = pfit_size & 0xFFFF;
6169 if (pipe_w < pfit_w)
6170 pipe_w = pfit_w;
6171 if (pipe_h < pfit_h)
6172 pipe_h = pfit_h;
6173
6174 if (WARN_ON(!pfit_w || !pfit_h))
6175 return pixel_rate;
6176
6177 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6178 pfit_w * pfit_h);
6179 }
6180
6181 return pixel_rate;
6182 }
6183
6184 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6185 {
6186 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6187
6188 if (HAS_GMCH_DISPLAY(dev_priv))
6189 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6190 crtc_state->pixel_rate =
6191 crtc_state->base.adjusted_mode.crtc_clock;
6192 else
6193 crtc_state->pixel_rate =
6194 ilk_pipe_pixel_rate(crtc_state);
6195 }
6196
6197 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6198 struct intel_crtc_state *pipe_config)
6199 {
6200 struct drm_device *dev = crtc->base.dev;
6201 struct drm_i915_private *dev_priv = to_i915(dev);
6202 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6203 int clock_limit = dev_priv->max_dotclk_freq;
6204
6205 if (INTEL_GEN(dev_priv) < 4) {
6206 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6207
6208 /*
6209 * Enable double wide mode when the dot clock
6210 * is > 90% of the (display) core speed.
6211 */
6212 if (intel_crtc_supports_double_wide(crtc) &&
6213 adjusted_mode->crtc_clock > clock_limit) {
6214 clock_limit = dev_priv->max_dotclk_freq;
6215 pipe_config->double_wide = true;
6216 }
6217 }
6218
6219 if (adjusted_mode->crtc_clock > clock_limit) {
6220 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6221 adjusted_mode->crtc_clock, clock_limit,
6222 yesno(pipe_config->double_wide));
6223 return -EINVAL;
6224 }
6225
6226 /*
6227 * Pipe horizontal size must be even in:
6228 * - DVO ganged mode
6229 * - LVDS dual channel mode
6230 * - Double wide pipe
6231 */
6232 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6233 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6234 pipe_config->pipe_src_w &= ~1;
6235
6236 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6237 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6238 */
6239 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6240 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6241 return -EINVAL;
6242
6243 intel_crtc_compute_pixel_rate(pipe_config);
6244
6245 if (HAS_IPS(dev_priv))
6246 hsw_compute_ips_config(crtc, pipe_config);
6247
6248 if (pipe_config->has_pch_encoder)
6249 return ironlake_fdi_compute_config(crtc, pipe_config);
6250
6251 return 0;
6252 }
6253
6254 static void
6255 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6256 {
6257 while (*num > DATA_LINK_M_N_MASK ||
6258 *den > DATA_LINK_M_N_MASK) {
6259 *num >>= 1;
6260 *den >>= 1;
6261 }
6262 }
6263
6264 static void compute_m_n(unsigned int m, unsigned int n,
6265 uint32_t *ret_m, uint32_t *ret_n,
6266 bool reduce_m_n)
6267 {
6268 /*
6269 * Reduce M/N as much as possible without loss in precision. Several DP
6270 * dongles in particular seem to be fussy about too large *link* M/N
6271 * values. The passed in values are more likely to have the least
6272 * significant bits zero than M after rounding below, so do this first.
6273 */
6274 if (reduce_m_n) {
6275 while ((m & 1) == 0 && (n & 1) == 0) {
6276 m >>= 1;
6277 n >>= 1;
6278 }
6279 }
6280
6281 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6282 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6283 intel_reduce_m_n_ratio(ret_m, ret_n);
6284 }
6285
6286 void
6287 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6288 int pixel_clock, int link_clock,
6289 struct intel_link_m_n *m_n,
6290 bool reduce_m_n)
6291 {
6292 m_n->tu = 64;
6293
6294 compute_m_n(bits_per_pixel * pixel_clock,
6295 link_clock * nlanes * 8,
6296 &m_n->gmch_m, &m_n->gmch_n,
6297 reduce_m_n);
6298
6299 compute_m_n(pixel_clock, link_clock,
6300 &m_n->link_m, &m_n->link_n,
6301 reduce_m_n);
6302 }
6303
6304 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6305 {
6306 if (i915.panel_use_ssc >= 0)
6307 return i915.panel_use_ssc != 0;
6308 return dev_priv->vbt.lvds_use_ssc
6309 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6310 }
6311
6312 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6313 {
6314 return (1 << dpll->n) << 16 | dpll->m2;
6315 }
6316
6317 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6318 {
6319 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6320 }
6321
6322 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6323 struct intel_crtc_state *crtc_state,
6324 struct dpll *reduced_clock)
6325 {
6326 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6327 u32 fp, fp2 = 0;
6328
6329 if (IS_PINEVIEW(dev_priv)) {
6330 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6331 if (reduced_clock)
6332 fp2 = pnv_dpll_compute_fp(reduced_clock);
6333 } else {
6334 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6335 if (reduced_clock)
6336 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6337 }
6338
6339 crtc_state->dpll_hw_state.fp0 = fp;
6340
6341 crtc->lowfreq_avail = false;
6342 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6343 reduced_clock) {
6344 crtc_state->dpll_hw_state.fp1 = fp2;
6345 crtc->lowfreq_avail = true;
6346 } else {
6347 crtc_state->dpll_hw_state.fp1 = fp;
6348 }
6349 }
6350
6351 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6352 pipe)
6353 {
6354 u32 reg_val;
6355
6356 /*
6357 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6358 * and set it to a reasonable value instead.
6359 */
6360 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6361 reg_val &= 0xffffff00;
6362 reg_val |= 0x00000030;
6363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6364
6365 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6366 reg_val &= 0x00ffffff;
6367 reg_val |= 0x8c000000;
6368 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6369
6370 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6371 reg_val &= 0xffffff00;
6372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6373
6374 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6375 reg_val &= 0x00ffffff;
6376 reg_val |= 0xb0000000;
6377 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6378 }
6379
6380 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6381 struct intel_link_m_n *m_n)
6382 {
6383 struct drm_device *dev = crtc->base.dev;
6384 struct drm_i915_private *dev_priv = to_i915(dev);
6385 int pipe = crtc->pipe;
6386
6387 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6388 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6389 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6390 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6391 }
6392
6393 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6394 struct intel_link_m_n *m_n,
6395 struct intel_link_m_n *m2_n2)
6396 {
6397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6398 int pipe = crtc->pipe;
6399 enum transcoder transcoder = crtc->config->cpu_transcoder;
6400
6401 if (INTEL_GEN(dev_priv) >= 5) {
6402 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6403 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6404 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6405 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6406 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6407 * for gen < 8) and if DRRS is supported (to make sure the
6408 * registers are not unnecessarily accessed).
6409 */
6410 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6411 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6412 I915_WRITE(PIPE_DATA_M2(transcoder),
6413 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6414 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6415 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6416 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6417 }
6418 } else {
6419 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6420 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6421 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6422 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6423 }
6424 }
6425
6426 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6427 {
6428 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6429
6430 if (m_n == M1_N1) {
6431 dp_m_n = &crtc->config->dp_m_n;
6432 dp_m2_n2 = &crtc->config->dp_m2_n2;
6433 } else if (m_n == M2_N2) {
6434
6435 /*
6436 * M2_N2 registers are not supported. Hence m2_n2 divider value
6437 * needs to be programmed into M1_N1.
6438 */
6439 dp_m_n = &crtc->config->dp_m2_n2;
6440 } else {
6441 DRM_ERROR("Unsupported divider value\n");
6442 return;
6443 }
6444
6445 if (crtc->config->has_pch_encoder)
6446 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6447 else
6448 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6449 }
6450
6451 static void vlv_compute_dpll(struct intel_crtc *crtc,
6452 struct intel_crtc_state *pipe_config)
6453 {
6454 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6455 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6456 if (crtc->pipe != PIPE_A)
6457 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6458
6459 /* DPLL not used with DSI, but still need the rest set up */
6460 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6461 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6462 DPLL_EXT_BUFFER_ENABLE_VLV;
6463
6464 pipe_config->dpll_hw_state.dpll_md =
6465 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6466 }
6467
6468 static void chv_compute_dpll(struct intel_crtc *crtc,
6469 struct intel_crtc_state *pipe_config)
6470 {
6471 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6472 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6473 if (crtc->pipe != PIPE_A)
6474 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6475
6476 /* DPLL not used with DSI, but still need the rest set up */
6477 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6478 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6479
6480 pipe_config->dpll_hw_state.dpll_md =
6481 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6482 }
6483
6484 static void vlv_prepare_pll(struct intel_crtc *crtc,
6485 const struct intel_crtc_state *pipe_config)
6486 {
6487 struct drm_device *dev = crtc->base.dev;
6488 struct drm_i915_private *dev_priv = to_i915(dev);
6489 enum pipe pipe = crtc->pipe;
6490 u32 mdiv;
6491 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6492 u32 coreclk, reg_val;
6493
6494 /* Enable Refclk */
6495 I915_WRITE(DPLL(pipe),
6496 pipe_config->dpll_hw_state.dpll &
6497 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6498
6499 /* No need to actually set up the DPLL with DSI */
6500 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6501 return;
6502
6503 mutex_lock(&dev_priv->sb_lock);
6504
6505 bestn = pipe_config->dpll.n;
6506 bestm1 = pipe_config->dpll.m1;
6507 bestm2 = pipe_config->dpll.m2;
6508 bestp1 = pipe_config->dpll.p1;
6509 bestp2 = pipe_config->dpll.p2;
6510
6511 /* See eDP HDMI DPIO driver vbios notes doc */
6512
6513 /* PLL B needs special handling */
6514 if (pipe == PIPE_B)
6515 vlv_pllb_recal_opamp(dev_priv, pipe);
6516
6517 /* Set up Tx target for periodic Rcomp update */
6518 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6519
6520 /* Disable target IRef on PLL */
6521 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6522 reg_val &= 0x00ffffff;
6523 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6524
6525 /* Disable fast lock */
6526 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6527
6528 /* Set idtafcrecal before PLL is enabled */
6529 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6530 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6531 mdiv |= ((bestn << DPIO_N_SHIFT));
6532 mdiv |= (1 << DPIO_K_SHIFT);
6533
6534 /*
6535 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6536 * but we don't support that).
6537 * Note: don't use the DAC post divider as it seems unstable.
6538 */
6539 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6540 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6541
6542 mdiv |= DPIO_ENABLE_CALIBRATION;
6543 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6544
6545 /* Set HBR and RBR LPF coefficients */
6546 if (pipe_config->port_clock == 162000 ||
6547 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6548 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6549 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6550 0x009f0003);
6551 else
6552 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6553 0x00d0000f);
6554
6555 if (intel_crtc_has_dp_encoder(pipe_config)) {
6556 /* Use SSC source */
6557 if (pipe == PIPE_A)
6558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6559 0x0df40000);
6560 else
6561 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6562 0x0df70000);
6563 } else { /* HDMI or VGA */
6564 /* Use bend source */
6565 if (pipe == PIPE_A)
6566 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6567 0x0df70000);
6568 else
6569 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6570 0x0df40000);
6571 }
6572
6573 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6574 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6575 if (intel_crtc_has_dp_encoder(crtc->config))
6576 coreclk |= 0x01000000;
6577 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6578
6579 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6580 mutex_unlock(&dev_priv->sb_lock);
6581 }
6582
6583 static void chv_prepare_pll(struct intel_crtc *crtc,
6584 const struct intel_crtc_state *pipe_config)
6585 {
6586 struct drm_device *dev = crtc->base.dev;
6587 struct drm_i915_private *dev_priv = to_i915(dev);
6588 enum pipe pipe = crtc->pipe;
6589 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6590 u32 loopfilter, tribuf_calcntr;
6591 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6592 u32 dpio_val;
6593 int vco;
6594
6595 /* Enable Refclk and SSC */
6596 I915_WRITE(DPLL(pipe),
6597 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6598
6599 /* No need to actually set up the DPLL with DSI */
6600 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6601 return;
6602
6603 bestn = pipe_config->dpll.n;
6604 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6605 bestm1 = pipe_config->dpll.m1;
6606 bestm2 = pipe_config->dpll.m2 >> 22;
6607 bestp1 = pipe_config->dpll.p1;
6608 bestp2 = pipe_config->dpll.p2;
6609 vco = pipe_config->dpll.vco;
6610 dpio_val = 0;
6611 loopfilter = 0;
6612
6613 mutex_lock(&dev_priv->sb_lock);
6614
6615 /* p1 and p2 divider */
6616 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6617 5 << DPIO_CHV_S1_DIV_SHIFT |
6618 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6619 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6620 1 << DPIO_CHV_K_DIV_SHIFT);
6621
6622 /* Feedback post-divider - m2 */
6623 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6624
6625 /* Feedback refclk divider - n and m1 */
6626 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6627 DPIO_CHV_M1_DIV_BY_2 |
6628 1 << DPIO_CHV_N_DIV_SHIFT);
6629
6630 /* M2 fraction division */
6631 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6632
6633 /* M2 fraction division enable */
6634 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6635 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6636 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6637 if (bestm2_frac)
6638 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6639 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6640
6641 /* Program digital lock detect threshold */
6642 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6643 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6644 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6645 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6646 if (!bestm2_frac)
6647 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6648 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6649
6650 /* Loop filter */
6651 if (vco == 5400000) {
6652 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6653 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6654 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6655 tribuf_calcntr = 0x9;
6656 } else if (vco <= 6200000) {
6657 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6658 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6659 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6660 tribuf_calcntr = 0x9;
6661 } else if (vco <= 6480000) {
6662 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6663 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6664 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6665 tribuf_calcntr = 0x8;
6666 } else {
6667 /* Not supported. Apply the same limits as in the max case */
6668 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6669 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6670 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6671 tribuf_calcntr = 0;
6672 }
6673 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6674
6675 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6676 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6677 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6678 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6679
6680 /* AFC Recal */
6681 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6682 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6683 DPIO_AFC_RECAL);
6684
6685 mutex_unlock(&dev_priv->sb_lock);
6686 }
6687
6688 /**
6689 * vlv_force_pll_on - forcibly enable just the PLL
6690 * @dev_priv: i915 private structure
6691 * @pipe: pipe PLL to enable
6692 * @dpll: PLL configuration
6693 *
6694 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6695 * in cases where we need the PLL enabled even when @pipe is not going to
6696 * be enabled.
6697 */
6698 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6699 const struct dpll *dpll)
6700 {
6701 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6702 struct intel_crtc_state *pipe_config;
6703
6704 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6705 if (!pipe_config)
6706 return -ENOMEM;
6707
6708 pipe_config->base.crtc = &crtc->base;
6709 pipe_config->pixel_multiplier = 1;
6710 pipe_config->dpll = *dpll;
6711
6712 if (IS_CHERRYVIEW(dev_priv)) {
6713 chv_compute_dpll(crtc, pipe_config);
6714 chv_prepare_pll(crtc, pipe_config);
6715 chv_enable_pll(crtc, pipe_config);
6716 } else {
6717 vlv_compute_dpll(crtc, pipe_config);
6718 vlv_prepare_pll(crtc, pipe_config);
6719 vlv_enable_pll(crtc, pipe_config);
6720 }
6721
6722 kfree(pipe_config);
6723
6724 return 0;
6725 }
6726
6727 /**
6728 * vlv_force_pll_off - forcibly disable just the PLL
6729 * @dev_priv: i915 private structure
6730 * @pipe: pipe PLL to disable
6731 *
6732 * Disable the PLL for @pipe. To be used in cases where we need
6733 * the PLL enabled even when @pipe is not going to be enabled.
6734 */
6735 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6736 {
6737 if (IS_CHERRYVIEW(dev_priv))
6738 chv_disable_pll(dev_priv, pipe);
6739 else
6740 vlv_disable_pll(dev_priv, pipe);
6741 }
6742
6743 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6744 struct intel_crtc_state *crtc_state,
6745 struct dpll *reduced_clock)
6746 {
6747 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6748 u32 dpll;
6749 struct dpll *clock = &crtc_state->dpll;
6750
6751 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6752
6753 dpll = DPLL_VGA_MODE_DIS;
6754
6755 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6756 dpll |= DPLLB_MODE_LVDS;
6757 else
6758 dpll |= DPLLB_MODE_DAC_SERIAL;
6759
6760 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6761 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6762 dpll |= (crtc_state->pixel_multiplier - 1)
6763 << SDVO_MULTIPLIER_SHIFT_HIRES;
6764 }
6765
6766 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6767 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6768 dpll |= DPLL_SDVO_HIGH_SPEED;
6769
6770 if (intel_crtc_has_dp_encoder(crtc_state))
6771 dpll |= DPLL_SDVO_HIGH_SPEED;
6772
6773 /* compute bitmask from p1 value */
6774 if (IS_PINEVIEW(dev_priv))
6775 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6776 else {
6777 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6778 if (IS_G4X(dev_priv) && reduced_clock)
6779 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6780 }
6781 switch (clock->p2) {
6782 case 5:
6783 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6784 break;
6785 case 7:
6786 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6787 break;
6788 case 10:
6789 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6790 break;
6791 case 14:
6792 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6793 break;
6794 }
6795 if (INTEL_GEN(dev_priv) >= 4)
6796 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6797
6798 if (crtc_state->sdvo_tv_clock)
6799 dpll |= PLL_REF_INPUT_TVCLKINBC;
6800 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6801 intel_panel_use_ssc(dev_priv))
6802 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6803 else
6804 dpll |= PLL_REF_INPUT_DREFCLK;
6805
6806 dpll |= DPLL_VCO_ENABLE;
6807 crtc_state->dpll_hw_state.dpll = dpll;
6808
6809 if (INTEL_GEN(dev_priv) >= 4) {
6810 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6811 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6812 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6813 }
6814 }
6815
6816 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6817 struct intel_crtc_state *crtc_state,
6818 struct dpll *reduced_clock)
6819 {
6820 struct drm_device *dev = crtc->base.dev;
6821 struct drm_i915_private *dev_priv = to_i915(dev);
6822 u32 dpll;
6823 struct dpll *clock = &crtc_state->dpll;
6824
6825 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6826
6827 dpll = DPLL_VGA_MODE_DIS;
6828
6829 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6830 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6831 } else {
6832 if (clock->p1 == 2)
6833 dpll |= PLL_P1_DIVIDE_BY_TWO;
6834 else
6835 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6836 if (clock->p2 == 4)
6837 dpll |= PLL_P2_DIVIDE_BY_4;
6838 }
6839
6840 if (!IS_I830(dev_priv) &&
6841 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6842 dpll |= DPLL_DVO_2X_MODE;
6843
6844 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6845 intel_panel_use_ssc(dev_priv))
6846 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6847 else
6848 dpll |= PLL_REF_INPUT_DREFCLK;
6849
6850 dpll |= DPLL_VCO_ENABLE;
6851 crtc_state->dpll_hw_state.dpll = dpll;
6852 }
6853
6854 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6855 {
6856 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6857 enum pipe pipe = intel_crtc->pipe;
6858 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6859 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6860 uint32_t crtc_vtotal, crtc_vblank_end;
6861 int vsyncshift = 0;
6862
6863 /* We need to be careful not to changed the adjusted mode, for otherwise
6864 * the hw state checker will get angry at the mismatch. */
6865 crtc_vtotal = adjusted_mode->crtc_vtotal;
6866 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6867
6868 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6869 /* the chip adds 2 halflines automatically */
6870 crtc_vtotal -= 1;
6871 crtc_vblank_end -= 1;
6872
6873 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6874 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6875 else
6876 vsyncshift = adjusted_mode->crtc_hsync_start -
6877 adjusted_mode->crtc_htotal / 2;
6878 if (vsyncshift < 0)
6879 vsyncshift += adjusted_mode->crtc_htotal;
6880 }
6881
6882 if (INTEL_GEN(dev_priv) > 3)
6883 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6884
6885 I915_WRITE(HTOTAL(cpu_transcoder),
6886 (adjusted_mode->crtc_hdisplay - 1) |
6887 ((adjusted_mode->crtc_htotal - 1) << 16));
6888 I915_WRITE(HBLANK(cpu_transcoder),
6889 (adjusted_mode->crtc_hblank_start - 1) |
6890 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6891 I915_WRITE(HSYNC(cpu_transcoder),
6892 (adjusted_mode->crtc_hsync_start - 1) |
6893 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6894
6895 I915_WRITE(VTOTAL(cpu_transcoder),
6896 (adjusted_mode->crtc_vdisplay - 1) |
6897 ((crtc_vtotal - 1) << 16));
6898 I915_WRITE(VBLANK(cpu_transcoder),
6899 (adjusted_mode->crtc_vblank_start - 1) |
6900 ((crtc_vblank_end - 1) << 16));
6901 I915_WRITE(VSYNC(cpu_transcoder),
6902 (adjusted_mode->crtc_vsync_start - 1) |
6903 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6904
6905 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6906 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6907 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6908 * bits. */
6909 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6910 (pipe == PIPE_B || pipe == PIPE_C))
6911 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6912
6913 }
6914
6915 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6916 {
6917 struct drm_device *dev = intel_crtc->base.dev;
6918 struct drm_i915_private *dev_priv = to_i915(dev);
6919 enum pipe pipe = intel_crtc->pipe;
6920
6921 /* pipesrc controls the size that is scaled from, which should
6922 * always be the user's requested size.
6923 */
6924 I915_WRITE(PIPESRC(pipe),
6925 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6926 (intel_crtc->config->pipe_src_h - 1));
6927 }
6928
6929 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6930 struct intel_crtc_state *pipe_config)
6931 {
6932 struct drm_device *dev = crtc->base.dev;
6933 struct drm_i915_private *dev_priv = to_i915(dev);
6934 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6935 uint32_t tmp;
6936
6937 tmp = I915_READ(HTOTAL(cpu_transcoder));
6938 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6939 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6940 tmp = I915_READ(HBLANK(cpu_transcoder));
6941 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6942 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6943 tmp = I915_READ(HSYNC(cpu_transcoder));
6944 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6945 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6946
6947 tmp = I915_READ(VTOTAL(cpu_transcoder));
6948 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6949 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6950 tmp = I915_READ(VBLANK(cpu_transcoder));
6951 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6952 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6953 tmp = I915_READ(VSYNC(cpu_transcoder));
6954 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6955 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6956
6957 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6958 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6959 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6960 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6961 }
6962 }
6963
6964 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6965 struct intel_crtc_state *pipe_config)
6966 {
6967 struct drm_device *dev = crtc->base.dev;
6968 struct drm_i915_private *dev_priv = to_i915(dev);
6969 u32 tmp;
6970
6971 tmp = I915_READ(PIPESRC(crtc->pipe));
6972 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6973 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6974
6975 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6976 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6977 }
6978
6979 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6980 struct intel_crtc_state *pipe_config)
6981 {
6982 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6983 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6984 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6985 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6986
6987 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6988 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6989 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6990 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6991
6992 mode->flags = pipe_config->base.adjusted_mode.flags;
6993 mode->type = DRM_MODE_TYPE_DRIVER;
6994
6995 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6996
6997 mode->hsync = drm_mode_hsync(mode);
6998 mode->vrefresh = drm_mode_vrefresh(mode);
6999 drm_mode_set_name(mode);
7000 }
7001
7002 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7003 {
7004 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7005 uint32_t pipeconf;
7006
7007 pipeconf = 0;
7008
7009 /* we keep both pipes enabled on 830 */
7010 if (IS_I830(dev_priv))
7011 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7012
7013 if (intel_crtc->config->double_wide)
7014 pipeconf |= PIPECONF_DOUBLE_WIDE;
7015
7016 /* only g4x and later have fancy bpc/dither controls */
7017 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7018 IS_CHERRYVIEW(dev_priv)) {
7019 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7020 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7021 pipeconf |= PIPECONF_DITHER_EN |
7022 PIPECONF_DITHER_TYPE_SP;
7023
7024 switch (intel_crtc->config->pipe_bpp) {
7025 case 18:
7026 pipeconf |= PIPECONF_6BPC;
7027 break;
7028 case 24:
7029 pipeconf |= PIPECONF_8BPC;
7030 break;
7031 case 30:
7032 pipeconf |= PIPECONF_10BPC;
7033 break;
7034 default:
7035 /* Case prevented by intel_choose_pipe_bpp_dither. */
7036 BUG();
7037 }
7038 }
7039
7040 if (HAS_PIPE_CXSR(dev_priv)) {
7041 if (intel_crtc->lowfreq_avail) {
7042 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7043 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7044 } else {
7045 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7046 }
7047 }
7048
7049 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7050 if (INTEL_GEN(dev_priv) < 4 ||
7051 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7052 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7053 else
7054 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7055 } else
7056 pipeconf |= PIPECONF_PROGRESSIVE;
7057
7058 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7059 intel_crtc->config->limited_color_range)
7060 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7061
7062 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7063 POSTING_READ(PIPECONF(intel_crtc->pipe));
7064 }
7065
7066 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7067 struct intel_crtc_state *crtc_state)
7068 {
7069 struct drm_device *dev = crtc->base.dev;
7070 struct drm_i915_private *dev_priv = to_i915(dev);
7071 const struct intel_limit *limit;
7072 int refclk = 48000;
7073
7074 memset(&crtc_state->dpll_hw_state, 0,
7075 sizeof(crtc_state->dpll_hw_state));
7076
7077 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7078 if (intel_panel_use_ssc(dev_priv)) {
7079 refclk = dev_priv->vbt.lvds_ssc_freq;
7080 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7081 }
7082
7083 limit = &intel_limits_i8xx_lvds;
7084 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7085 limit = &intel_limits_i8xx_dvo;
7086 } else {
7087 limit = &intel_limits_i8xx_dac;
7088 }
7089
7090 if (!crtc_state->clock_set &&
7091 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7092 refclk, NULL, &crtc_state->dpll)) {
7093 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7094 return -EINVAL;
7095 }
7096
7097 i8xx_compute_dpll(crtc, crtc_state, NULL);
7098
7099 return 0;
7100 }
7101
7102 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7103 struct intel_crtc_state *crtc_state)
7104 {
7105 struct drm_device *dev = crtc->base.dev;
7106 struct drm_i915_private *dev_priv = to_i915(dev);
7107 const struct intel_limit *limit;
7108 int refclk = 96000;
7109
7110 memset(&crtc_state->dpll_hw_state, 0,
7111 sizeof(crtc_state->dpll_hw_state));
7112
7113 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7114 if (intel_panel_use_ssc(dev_priv)) {
7115 refclk = dev_priv->vbt.lvds_ssc_freq;
7116 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7117 }
7118
7119 if (intel_is_dual_link_lvds(dev))
7120 limit = &intel_limits_g4x_dual_channel_lvds;
7121 else
7122 limit = &intel_limits_g4x_single_channel_lvds;
7123 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7124 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7125 limit = &intel_limits_g4x_hdmi;
7126 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7127 limit = &intel_limits_g4x_sdvo;
7128 } else {
7129 /* The option is for other outputs */
7130 limit = &intel_limits_i9xx_sdvo;
7131 }
7132
7133 if (!crtc_state->clock_set &&
7134 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7135 refclk, NULL, &crtc_state->dpll)) {
7136 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7137 return -EINVAL;
7138 }
7139
7140 i9xx_compute_dpll(crtc, crtc_state, NULL);
7141
7142 return 0;
7143 }
7144
7145 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7146 struct intel_crtc_state *crtc_state)
7147 {
7148 struct drm_device *dev = crtc->base.dev;
7149 struct drm_i915_private *dev_priv = to_i915(dev);
7150 const struct intel_limit *limit;
7151 int refclk = 96000;
7152
7153 memset(&crtc_state->dpll_hw_state, 0,
7154 sizeof(crtc_state->dpll_hw_state));
7155
7156 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7157 if (intel_panel_use_ssc(dev_priv)) {
7158 refclk = dev_priv->vbt.lvds_ssc_freq;
7159 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7160 }
7161
7162 limit = &intel_limits_pineview_lvds;
7163 } else {
7164 limit = &intel_limits_pineview_sdvo;
7165 }
7166
7167 if (!crtc_state->clock_set &&
7168 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7169 refclk, NULL, &crtc_state->dpll)) {
7170 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7171 return -EINVAL;
7172 }
7173
7174 i9xx_compute_dpll(crtc, crtc_state, NULL);
7175
7176 return 0;
7177 }
7178
7179 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7180 struct intel_crtc_state *crtc_state)
7181 {
7182 struct drm_device *dev = crtc->base.dev;
7183 struct drm_i915_private *dev_priv = to_i915(dev);
7184 const struct intel_limit *limit;
7185 int refclk = 96000;
7186
7187 memset(&crtc_state->dpll_hw_state, 0,
7188 sizeof(crtc_state->dpll_hw_state));
7189
7190 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7191 if (intel_panel_use_ssc(dev_priv)) {
7192 refclk = dev_priv->vbt.lvds_ssc_freq;
7193 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7194 }
7195
7196 limit = &intel_limits_i9xx_lvds;
7197 } else {
7198 limit = &intel_limits_i9xx_sdvo;
7199 }
7200
7201 if (!crtc_state->clock_set &&
7202 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7203 refclk, NULL, &crtc_state->dpll)) {
7204 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7205 return -EINVAL;
7206 }
7207
7208 i9xx_compute_dpll(crtc, crtc_state, NULL);
7209
7210 return 0;
7211 }
7212
7213 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7214 struct intel_crtc_state *crtc_state)
7215 {
7216 int refclk = 100000;
7217 const struct intel_limit *limit = &intel_limits_chv;
7218
7219 memset(&crtc_state->dpll_hw_state, 0,
7220 sizeof(crtc_state->dpll_hw_state));
7221
7222 if (!crtc_state->clock_set &&
7223 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7224 refclk, NULL, &crtc_state->dpll)) {
7225 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7226 return -EINVAL;
7227 }
7228
7229 chv_compute_dpll(crtc, crtc_state);
7230
7231 return 0;
7232 }
7233
7234 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7235 struct intel_crtc_state *crtc_state)
7236 {
7237 int refclk = 100000;
7238 const struct intel_limit *limit = &intel_limits_vlv;
7239
7240 memset(&crtc_state->dpll_hw_state, 0,
7241 sizeof(crtc_state->dpll_hw_state));
7242
7243 if (!crtc_state->clock_set &&
7244 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7245 refclk, NULL, &crtc_state->dpll)) {
7246 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7247 return -EINVAL;
7248 }
7249
7250 vlv_compute_dpll(crtc, crtc_state);
7251
7252 return 0;
7253 }
7254
7255 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7256 struct intel_crtc_state *pipe_config)
7257 {
7258 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7259 uint32_t tmp;
7260
7261 if (INTEL_GEN(dev_priv) <= 3 &&
7262 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7263 return;
7264
7265 tmp = I915_READ(PFIT_CONTROL);
7266 if (!(tmp & PFIT_ENABLE))
7267 return;
7268
7269 /* Check whether the pfit is attached to our pipe. */
7270 if (INTEL_GEN(dev_priv) < 4) {
7271 if (crtc->pipe != PIPE_B)
7272 return;
7273 } else {
7274 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7275 return;
7276 }
7277
7278 pipe_config->gmch_pfit.control = tmp;
7279 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7280 }
7281
7282 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7283 struct intel_crtc_state *pipe_config)
7284 {
7285 struct drm_device *dev = crtc->base.dev;
7286 struct drm_i915_private *dev_priv = to_i915(dev);
7287 int pipe = pipe_config->cpu_transcoder;
7288 struct dpll clock;
7289 u32 mdiv;
7290 int refclk = 100000;
7291
7292 /* In case of DSI, DPLL will not be used */
7293 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7294 return;
7295
7296 mutex_lock(&dev_priv->sb_lock);
7297 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7298 mutex_unlock(&dev_priv->sb_lock);
7299
7300 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7301 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7302 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7303 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7304 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7305
7306 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7307 }
7308
7309 static void
7310 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7311 struct intel_initial_plane_config *plane_config)
7312 {
7313 struct drm_device *dev = crtc->base.dev;
7314 struct drm_i915_private *dev_priv = to_i915(dev);
7315 u32 val, base, offset;
7316 int pipe = crtc->pipe, plane = crtc->plane;
7317 int fourcc, pixel_format;
7318 unsigned int aligned_height;
7319 struct drm_framebuffer *fb;
7320 struct intel_framebuffer *intel_fb;
7321
7322 val = I915_READ(DSPCNTR(plane));
7323 if (!(val & DISPLAY_PLANE_ENABLE))
7324 return;
7325
7326 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7327 if (!intel_fb) {
7328 DRM_DEBUG_KMS("failed to alloc fb\n");
7329 return;
7330 }
7331
7332 fb = &intel_fb->base;
7333
7334 fb->dev = dev;
7335
7336 if (INTEL_GEN(dev_priv) >= 4) {
7337 if (val & DISPPLANE_TILED) {
7338 plane_config->tiling = I915_TILING_X;
7339 fb->modifier = I915_FORMAT_MOD_X_TILED;
7340 }
7341 }
7342
7343 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7344 fourcc = i9xx_format_to_fourcc(pixel_format);
7345 fb->format = drm_format_info(fourcc);
7346
7347 if (INTEL_GEN(dev_priv) >= 4) {
7348 if (plane_config->tiling)
7349 offset = I915_READ(DSPTILEOFF(plane));
7350 else
7351 offset = I915_READ(DSPLINOFF(plane));
7352 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7353 } else {
7354 base = I915_READ(DSPADDR(plane));
7355 }
7356 plane_config->base = base;
7357
7358 val = I915_READ(PIPESRC(pipe));
7359 fb->width = ((val >> 16) & 0xfff) + 1;
7360 fb->height = ((val >> 0) & 0xfff) + 1;
7361
7362 val = I915_READ(DSPSTRIDE(pipe));
7363 fb->pitches[0] = val & 0xffffffc0;
7364
7365 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7366
7367 plane_config->size = fb->pitches[0] * aligned_height;
7368
7369 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7370 pipe_name(pipe), plane, fb->width, fb->height,
7371 fb->format->cpp[0] * 8, base, fb->pitches[0],
7372 plane_config->size);
7373
7374 plane_config->fb = intel_fb;
7375 }
7376
7377 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7378 struct intel_crtc_state *pipe_config)
7379 {
7380 struct drm_device *dev = crtc->base.dev;
7381 struct drm_i915_private *dev_priv = to_i915(dev);
7382 int pipe = pipe_config->cpu_transcoder;
7383 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7384 struct dpll clock;
7385 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7386 int refclk = 100000;
7387
7388 /* In case of DSI, DPLL will not be used */
7389 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7390 return;
7391
7392 mutex_lock(&dev_priv->sb_lock);
7393 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7394 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7395 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7396 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7397 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7398 mutex_unlock(&dev_priv->sb_lock);
7399
7400 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7401 clock.m2 = (pll_dw0 & 0xff) << 22;
7402 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7403 clock.m2 |= pll_dw2 & 0x3fffff;
7404 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7405 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7406 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7407
7408 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7409 }
7410
7411 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7412 struct intel_crtc_state *pipe_config)
7413 {
7414 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7415 enum intel_display_power_domain power_domain;
7416 uint32_t tmp;
7417 bool ret;
7418
7419 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7420 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7421 return false;
7422
7423 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7424 pipe_config->shared_dpll = NULL;
7425
7426 ret = false;
7427
7428 tmp = I915_READ(PIPECONF(crtc->pipe));
7429 if (!(tmp & PIPECONF_ENABLE))
7430 goto out;
7431
7432 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7433 IS_CHERRYVIEW(dev_priv)) {
7434 switch (tmp & PIPECONF_BPC_MASK) {
7435 case PIPECONF_6BPC:
7436 pipe_config->pipe_bpp = 18;
7437 break;
7438 case PIPECONF_8BPC:
7439 pipe_config->pipe_bpp = 24;
7440 break;
7441 case PIPECONF_10BPC:
7442 pipe_config->pipe_bpp = 30;
7443 break;
7444 default:
7445 break;
7446 }
7447 }
7448
7449 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7450 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7451 pipe_config->limited_color_range = true;
7452
7453 if (INTEL_GEN(dev_priv) < 4)
7454 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7455
7456 intel_get_pipe_timings(crtc, pipe_config);
7457 intel_get_pipe_src_size(crtc, pipe_config);
7458
7459 i9xx_get_pfit_config(crtc, pipe_config);
7460
7461 if (INTEL_GEN(dev_priv) >= 4) {
7462 /* No way to read it out on pipes B and C */
7463 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7464 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7465 else
7466 tmp = I915_READ(DPLL_MD(crtc->pipe));
7467 pipe_config->pixel_multiplier =
7468 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7469 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7470 pipe_config->dpll_hw_state.dpll_md = tmp;
7471 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7472 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7473 tmp = I915_READ(DPLL(crtc->pipe));
7474 pipe_config->pixel_multiplier =
7475 ((tmp & SDVO_MULTIPLIER_MASK)
7476 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7477 } else {
7478 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7479 * port and will be fixed up in the encoder->get_config
7480 * function. */
7481 pipe_config->pixel_multiplier = 1;
7482 }
7483 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7484 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7485 /*
7486 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7487 * on 830. Filter it out here so that we don't
7488 * report errors due to that.
7489 */
7490 if (IS_I830(dev_priv))
7491 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7492
7493 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7494 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7495 } else {
7496 /* Mask out read-only status bits. */
7497 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7498 DPLL_PORTC_READY_MASK |
7499 DPLL_PORTB_READY_MASK);
7500 }
7501
7502 if (IS_CHERRYVIEW(dev_priv))
7503 chv_crtc_clock_get(crtc, pipe_config);
7504 else if (IS_VALLEYVIEW(dev_priv))
7505 vlv_crtc_clock_get(crtc, pipe_config);
7506 else
7507 i9xx_crtc_clock_get(crtc, pipe_config);
7508
7509 /*
7510 * Normally the dotclock is filled in by the encoder .get_config()
7511 * but in case the pipe is enabled w/o any ports we need a sane
7512 * default.
7513 */
7514 pipe_config->base.adjusted_mode.crtc_clock =
7515 pipe_config->port_clock / pipe_config->pixel_multiplier;
7516
7517 ret = true;
7518
7519 out:
7520 intel_display_power_put(dev_priv, power_domain);
7521
7522 return ret;
7523 }
7524
7525 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7526 {
7527 struct intel_encoder *encoder;
7528 int i;
7529 u32 val, final;
7530 bool has_lvds = false;
7531 bool has_cpu_edp = false;
7532 bool has_panel = false;
7533 bool has_ck505 = false;
7534 bool can_ssc = false;
7535 bool using_ssc_source = false;
7536
7537 /* We need to take the global config into account */
7538 for_each_intel_encoder(&dev_priv->drm, encoder) {
7539 switch (encoder->type) {
7540 case INTEL_OUTPUT_LVDS:
7541 has_panel = true;
7542 has_lvds = true;
7543 break;
7544 case INTEL_OUTPUT_EDP:
7545 has_panel = true;
7546 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7547 has_cpu_edp = true;
7548 break;
7549 default:
7550 break;
7551 }
7552 }
7553
7554 if (HAS_PCH_IBX(dev_priv)) {
7555 has_ck505 = dev_priv->vbt.display_clock_mode;
7556 can_ssc = has_ck505;
7557 } else {
7558 has_ck505 = false;
7559 can_ssc = true;
7560 }
7561
7562 /* Check if any DPLLs are using the SSC source */
7563 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7564 u32 temp = I915_READ(PCH_DPLL(i));
7565
7566 if (!(temp & DPLL_VCO_ENABLE))
7567 continue;
7568
7569 if ((temp & PLL_REF_INPUT_MASK) ==
7570 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7571 using_ssc_source = true;
7572 break;
7573 }
7574 }
7575
7576 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7577 has_panel, has_lvds, has_ck505, using_ssc_source);
7578
7579 /* Ironlake: try to setup display ref clock before DPLL
7580 * enabling. This is only under driver's control after
7581 * PCH B stepping, previous chipset stepping should be
7582 * ignoring this setting.
7583 */
7584 val = I915_READ(PCH_DREF_CONTROL);
7585
7586 /* As we must carefully and slowly disable/enable each source in turn,
7587 * compute the final state we want first and check if we need to
7588 * make any changes at all.
7589 */
7590 final = val;
7591 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7592 if (has_ck505)
7593 final |= DREF_NONSPREAD_CK505_ENABLE;
7594 else
7595 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7596
7597 final &= ~DREF_SSC_SOURCE_MASK;
7598 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7599 final &= ~DREF_SSC1_ENABLE;
7600
7601 if (has_panel) {
7602 final |= DREF_SSC_SOURCE_ENABLE;
7603
7604 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7605 final |= DREF_SSC1_ENABLE;
7606
7607 if (has_cpu_edp) {
7608 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7609 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7610 else
7611 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7612 } else
7613 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7614 } else if (using_ssc_source) {
7615 final |= DREF_SSC_SOURCE_ENABLE;
7616 final |= DREF_SSC1_ENABLE;
7617 }
7618
7619 if (final == val)
7620 return;
7621
7622 /* Always enable nonspread source */
7623 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7624
7625 if (has_ck505)
7626 val |= DREF_NONSPREAD_CK505_ENABLE;
7627 else
7628 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7629
7630 if (has_panel) {
7631 val &= ~DREF_SSC_SOURCE_MASK;
7632 val |= DREF_SSC_SOURCE_ENABLE;
7633
7634 /* SSC must be turned on before enabling the CPU output */
7635 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7636 DRM_DEBUG_KMS("Using SSC on panel\n");
7637 val |= DREF_SSC1_ENABLE;
7638 } else
7639 val &= ~DREF_SSC1_ENABLE;
7640
7641 /* Get SSC going before enabling the outputs */
7642 I915_WRITE(PCH_DREF_CONTROL, val);
7643 POSTING_READ(PCH_DREF_CONTROL);
7644 udelay(200);
7645
7646 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7647
7648 /* Enable CPU source on CPU attached eDP */
7649 if (has_cpu_edp) {
7650 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7651 DRM_DEBUG_KMS("Using SSC on eDP\n");
7652 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7653 } else
7654 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7655 } else
7656 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7657
7658 I915_WRITE(PCH_DREF_CONTROL, val);
7659 POSTING_READ(PCH_DREF_CONTROL);
7660 udelay(200);
7661 } else {
7662 DRM_DEBUG_KMS("Disabling CPU source output\n");
7663
7664 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7665
7666 /* Turn off CPU output */
7667 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7668
7669 I915_WRITE(PCH_DREF_CONTROL, val);
7670 POSTING_READ(PCH_DREF_CONTROL);
7671 udelay(200);
7672
7673 if (!using_ssc_source) {
7674 DRM_DEBUG_KMS("Disabling SSC source\n");
7675
7676 /* Turn off the SSC source */
7677 val &= ~DREF_SSC_SOURCE_MASK;
7678 val |= DREF_SSC_SOURCE_DISABLE;
7679
7680 /* Turn off SSC1 */
7681 val &= ~DREF_SSC1_ENABLE;
7682
7683 I915_WRITE(PCH_DREF_CONTROL, val);
7684 POSTING_READ(PCH_DREF_CONTROL);
7685 udelay(200);
7686 }
7687 }
7688
7689 BUG_ON(val != final);
7690 }
7691
7692 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7693 {
7694 uint32_t tmp;
7695
7696 tmp = I915_READ(SOUTH_CHICKEN2);
7697 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7698 I915_WRITE(SOUTH_CHICKEN2, tmp);
7699
7700 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7701 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7702 DRM_ERROR("FDI mPHY reset assert timeout\n");
7703
7704 tmp = I915_READ(SOUTH_CHICKEN2);
7705 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7706 I915_WRITE(SOUTH_CHICKEN2, tmp);
7707
7708 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7709 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7710 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7711 }
7712
7713 /* WaMPhyProgramming:hsw */
7714 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7715 {
7716 uint32_t tmp;
7717
7718 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7719 tmp &= ~(0xFF << 24);
7720 tmp |= (0x12 << 24);
7721 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7722
7723 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7724 tmp |= (1 << 11);
7725 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7726
7727 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7728 tmp |= (1 << 11);
7729 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7730
7731 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7732 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7733 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7734
7735 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7736 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7737 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7738
7739 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7740 tmp &= ~(7 << 13);
7741 tmp |= (5 << 13);
7742 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7743
7744 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7745 tmp &= ~(7 << 13);
7746 tmp |= (5 << 13);
7747 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7748
7749 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7750 tmp &= ~0xFF;
7751 tmp |= 0x1C;
7752 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7753
7754 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7755 tmp &= ~0xFF;
7756 tmp |= 0x1C;
7757 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7758
7759 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7760 tmp &= ~(0xFF << 16);
7761 tmp |= (0x1C << 16);
7762 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7763
7764 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7765 tmp &= ~(0xFF << 16);
7766 tmp |= (0x1C << 16);
7767 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7768
7769 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7770 tmp |= (1 << 27);
7771 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7772
7773 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7774 tmp |= (1 << 27);
7775 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7776
7777 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7778 tmp &= ~(0xF << 28);
7779 tmp |= (4 << 28);
7780 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7781
7782 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7783 tmp &= ~(0xF << 28);
7784 tmp |= (4 << 28);
7785 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7786 }
7787
7788 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7789 * Programming" based on the parameters passed:
7790 * - Sequence to enable CLKOUT_DP
7791 * - Sequence to enable CLKOUT_DP without spread
7792 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7793 */
7794 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7795 bool with_spread, bool with_fdi)
7796 {
7797 uint32_t reg, tmp;
7798
7799 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7800 with_spread = true;
7801 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7802 with_fdi, "LP PCH doesn't have FDI\n"))
7803 with_fdi = false;
7804
7805 mutex_lock(&dev_priv->sb_lock);
7806
7807 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7808 tmp &= ~SBI_SSCCTL_DISABLE;
7809 tmp |= SBI_SSCCTL_PATHALT;
7810 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7811
7812 udelay(24);
7813
7814 if (with_spread) {
7815 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7816 tmp &= ~SBI_SSCCTL_PATHALT;
7817 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7818
7819 if (with_fdi) {
7820 lpt_reset_fdi_mphy(dev_priv);
7821 lpt_program_fdi_mphy(dev_priv);
7822 }
7823 }
7824
7825 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7826 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7827 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7828 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7829
7830 mutex_unlock(&dev_priv->sb_lock);
7831 }
7832
7833 /* Sequence to disable CLKOUT_DP */
7834 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7835 {
7836 uint32_t reg, tmp;
7837
7838 mutex_lock(&dev_priv->sb_lock);
7839
7840 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7841 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7842 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7843 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7844
7845 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7846 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7847 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7848 tmp |= SBI_SSCCTL_PATHALT;
7849 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7850 udelay(32);
7851 }
7852 tmp |= SBI_SSCCTL_DISABLE;
7853 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7854 }
7855
7856 mutex_unlock(&dev_priv->sb_lock);
7857 }
7858
7859 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7860
7861 static const uint16_t sscdivintphase[] = {
7862 [BEND_IDX( 50)] = 0x3B23,
7863 [BEND_IDX( 45)] = 0x3B23,
7864 [BEND_IDX( 40)] = 0x3C23,
7865 [BEND_IDX( 35)] = 0x3C23,
7866 [BEND_IDX( 30)] = 0x3D23,
7867 [BEND_IDX( 25)] = 0x3D23,
7868 [BEND_IDX( 20)] = 0x3E23,
7869 [BEND_IDX( 15)] = 0x3E23,
7870 [BEND_IDX( 10)] = 0x3F23,
7871 [BEND_IDX( 5)] = 0x3F23,
7872 [BEND_IDX( 0)] = 0x0025,
7873 [BEND_IDX( -5)] = 0x0025,
7874 [BEND_IDX(-10)] = 0x0125,
7875 [BEND_IDX(-15)] = 0x0125,
7876 [BEND_IDX(-20)] = 0x0225,
7877 [BEND_IDX(-25)] = 0x0225,
7878 [BEND_IDX(-30)] = 0x0325,
7879 [BEND_IDX(-35)] = 0x0325,
7880 [BEND_IDX(-40)] = 0x0425,
7881 [BEND_IDX(-45)] = 0x0425,
7882 [BEND_IDX(-50)] = 0x0525,
7883 };
7884
7885 /*
7886 * Bend CLKOUT_DP
7887 * steps -50 to 50 inclusive, in steps of 5
7888 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7889 * change in clock period = -(steps / 10) * 5.787 ps
7890 */
7891 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7892 {
7893 uint32_t tmp;
7894 int idx = BEND_IDX(steps);
7895
7896 if (WARN_ON(steps % 5 != 0))
7897 return;
7898
7899 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7900 return;
7901
7902 mutex_lock(&dev_priv->sb_lock);
7903
7904 if (steps % 10 != 0)
7905 tmp = 0xAAAAAAAB;
7906 else
7907 tmp = 0x00000000;
7908 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7909
7910 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7911 tmp &= 0xffff0000;
7912 tmp |= sscdivintphase[idx];
7913 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7914
7915 mutex_unlock(&dev_priv->sb_lock);
7916 }
7917
7918 #undef BEND_IDX
7919
7920 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7921 {
7922 struct intel_encoder *encoder;
7923 bool has_vga = false;
7924
7925 for_each_intel_encoder(&dev_priv->drm, encoder) {
7926 switch (encoder->type) {
7927 case INTEL_OUTPUT_ANALOG:
7928 has_vga = true;
7929 break;
7930 default:
7931 break;
7932 }
7933 }
7934
7935 if (has_vga) {
7936 lpt_bend_clkout_dp(dev_priv, 0);
7937 lpt_enable_clkout_dp(dev_priv, true, true);
7938 } else {
7939 lpt_disable_clkout_dp(dev_priv);
7940 }
7941 }
7942
7943 /*
7944 * Initialize reference clocks when the driver loads
7945 */
7946 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7947 {
7948 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7949 ironlake_init_pch_refclk(dev_priv);
7950 else if (HAS_PCH_LPT(dev_priv))
7951 lpt_init_pch_refclk(dev_priv);
7952 }
7953
7954 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7955 {
7956 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7958 int pipe = intel_crtc->pipe;
7959 uint32_t val;
7960
7961 val = 0;
7962
7963 switch (intel_crtc->config->pipe_bpp) {
7964 case 18:
7965 val |= PIPECONF_6BPC;
7966 break;
7967 case 24:
7968 val |= PIPECONF_8BPC;
7969 break;
7970 case 30:
7971 val |= PIPECONF_10BPC;
7972 break;
7973 case 36:
7974 val |= PIPECONF_12BPC;
7975 break;
7976 default:
7977 /* Case prevented by intel_choose_pipe_bpp_dither. */
7978 BUG();
7979 }
7980
7981 if (intel_crtc->config->dither)
7982 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7983
7984 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7985 val |= PIPECONF_INTERLACED_ILK;
7986 else
7987 val |= PIPECONF_PROGRESSIVE;
7988
7989 if (intel_crtc->config->limited_color_range)
7990 val |= PIPECONF_COLOR_RANGE_SELECT;
7991
7992 I915_WRITE(PIPECONF(pipe), val);
7993 POSTING_READ(PIPECONF(pipe));
7994 }
7995
7996 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7997 {
7998 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8000 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8001 u32 val = 0;
8002
8003 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8004 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8005
8006 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8007 val |= PIPECONF_INTERLACED_ILK;
8008 else
8009 val |= PIPECONF_PROGRESSIVE;
8010
8011 I915_WRITE(PIPECONF(cpu_transcoder), val);
8012 POSTING_READ(PIPECONF(cpu_transcoder));
8013 }
8014
8015 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8016 {
8017 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8019
8020 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8021 u32 val = 0;
8022
8023 switch (intel_crtc->config->pipe_bpp) {
8024 case 18:
8025 val |= PIPEMISC_DITHER_6_BPC;
8026 break;
8027 case 24:
8028 val |= PIPEMISC_DITHER_8_BPC;
8029 break;
8030 case 30:
8031 val |= PIPEMISC_DITHER_10_BPC;
8032 break;
8033 case 36:
8034 val |= PIPEMISC_DITHER_12_BPC;
8035 break;
8036 default:
8037 /* Case prevented by pipe_config_set_bpp. */
8038 BUG();
8039 }
8040
8041 if (intel_crtc->config->dither)
8042 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8043
8044 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8045 }
8046 }
8047
8048 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8049 {
8050 /*
8051 * Account for spread spectrum to avoid
8052 * oversubscribing the link. Max center spread
8053 * is 2.5%; use 5% for safety's sake.
8054 */
8055 u32 bps = target_clock * bpp * 21 / 20;
8056 return DIV_ROUND_UP(bps, link_bw * 8);
8057 }
8058
8059 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8060 {
8061 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8062 }
8063
8064 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8065 struct intel_crtc_state *crtc_state,
8066 struct dpll *reduced_clock)
8067 {
8068 struct drm_crtc *crtc = &intel_crtc->base;
8069 struct drm_device *dev = crtc->dev;
8070 struct drm_i915_private *dev_priv = to_i915(dev);
8071 u32 dpll, fp, fp2;
8072 int factor;
8073
8074 /* Enable autotuning of the PLL clock (if permissible) */
8075 factor = 21;
8076 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8077 if ((intel_panel_use_ssc(dev_priv) &&
8078 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8079 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8080 factor = 25;
8081 } else if (crtc_state->sdvo_tv_clock)
8082 factor = 20;
8083
8084 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8085
8086 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8087 fp |= FP_CB_TUNE;
8088
8089 if (reduced_clock) {
8090 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8091
8092 if (reduced_clock->m < factor * reduced_clock->n)
8093 fp2 |= FP_CB_TUNE;
8094 } else {
8095 fp2 = fp;
8096 }
8097
8098 dpll = 0;
8099
8100 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8101 dpll |= DPLLB_MODE_LVDS;
8102 else
8103 dpll |= DPLLB_MODE_DAC_SERIAL;
8104
8105 dpll |= (crtc_state->pixel_multiplier - 1)
8106 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8107
8108 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8109 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8110 dpll |= DPLL_SDVO_HIGH_SPEED;
8111
8112 if (intel_crtc_has_dp_encoder(crtc_state))
8113 dpll |= DPLL_SDVO_HIGH_SPEED;
8114
8115 /*
8116 * The high speed IO clock is only really required for
8117 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8118 * possible to share the DPLL between CRT and HDMI. Enabling
8119 * the clock needlessly does no real harm, except use up a
8120 * bit of power potentially.
8121 *
8122 * We'll limit this to IVB with 3 pipes, since it has only two
8123 * DPLLs and so DPLL sharing is the only way to get three pipes
8124 * driving PCH ports at the same time. On SNB we could do this,
8125 * and potentially avoid enabling the second DPLL, but it's not
8126 * clear if it''s a win or loss power wise. No point in doing
8127 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8128 */
8129 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8130 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8131 dpll |= DPLL_SDVO_HIGH_SPEED;
8132
8133 /* compute bitmask from p1 value */
8134 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8135 /* also FPA1 */
8136 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8137
8138 switch (crtc_state->dpll.p2) {
8139 case 5:
8140 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8141 break;
8142 case 7:
8143 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8144 break;
8145 case 10:
8146 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8147 break;
8148 case 14:
8149 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8150 break;
8151 }
8152
8153 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8154 intel_panel_use_ssc(dev_priv))
8155 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8156 else
8157 dpll |= PLL_REF_INPUT_DREFCLK;
8158
8159 dpll |= DPLL_VCO_ENABLE;
8160
8161 crtc_state->dpll_hw_state.dpll = dpll;
8162 crtc_state->dpll_hw_state.fp0 = fp;
8163 crtc_state->dpll_hw_state.fp1 = fp2;
8164 }
8165
8166 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8167 struct intel_crtc_state *crtc_state)
8168 {
8169 struct drm_device *dev = crtc->base.dev;
8170 struct drm_i915_private *dev_priv = to_i915(dev);
8171 const struct intel_limit *limit;
8172 int refclk = 120000;
8173
8174 memset(&crtc_state->dpll_hw_state, 0,
8175 sizeof(crtc_state->dpll_hw_state));
8176
8177 crtc->lowfreq_avail = false;
8178
8179 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8180 if (!crtc_state->has_pch_encoder)
8181 return 0;
8182
8183 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8184 if (intel_panel_use_ssc(dev_priv)) {
8185 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8186 dev_priv->vbt.lvds_ssc_freq);
8187 refclk = dev_priv->vbt.lvds_ssc_freq;
8188 }
8189
8190 if (intel_is_dual_link_lvds(dev)) {
8191 if (refclk == 100000)
8192 limit = &intel_limits_ironlake_dual_lvds_100m;
8193 else
8194 limit = &intel_limits_ironlake_dual_lvds;
8195 } else {
8196 if (refclk == 100000)
8197 limit = &intel_limits_ironlake_single_lvds_100m;
8198 else
8199 limit = &intel_limits_ironlake_single_lvds;
8200 }
8201 } else {
8202 limit = &intel_limits_ironlake_dac;
8203 }
8204
8205 if (!crtc_state->clock_set &&
8206 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8207 refclk, NULL, &crtc_state->dpll)) {
8208 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8209 return -EINVAL;
8210 }
8211
8212 ironlake_compute_dpll(crtc, crtc_state, NULL);
8213
8214 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8215 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8216 pipe_name(crtc->pipe));
8217 return -EINVAL;
8218 }
8219
8220 return 0;
8221 }
8222
8223 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8224 struct intel_link_m_n *m_n)
8225 {
8226 struct drm_device *dev = crtc->base.dev;
8227 struct drm_i915_private *dev_priv = to_i915(dev);
8228 enum pipe pipe = crtc->pipe;
8229
8230 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8231 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8232 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8233 & ~TU_SIZE_MASK;
8234 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8235 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8236 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8237 }
8238
8239 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8240 enum transcoder transcoder,
8241 struct intel_link_m_n *m_n,
8242 struct intel_link_m_n *m2_n2)
8243 {
8244 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8245 enum pipe pipe = crtc->pipe;
8246
8247 if (INTEL_GEN(dev_priv) >= 5) {
8248 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8249 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8250 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8251 & ~TU_SIZE_MASK;
8252 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8253 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8254 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8255 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8256 * gen < 8) and if DRRS is supported (to make sure the
8257 * registers are not unnecessarily read).
8258 */
8259 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8260 crtc->config->has_drrs) {
8261 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8262 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8263 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8264 & ~TU_SIZE_MASK;
8265 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8266 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8267 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8268 }
8269 } else {
8270 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8271 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8272 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8273 & ~TU_SIZE_MASK;
8274 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8275 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8276 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8277 }
8278 }
8279
8280 void intel_dp_get_m_n(struct intel_crtc *crtc,
8281 struct intel_crtc_state *pipe_config)
8282 {
8283 if (pipe_config->has_pch_encoder)
8284 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8285 else
8286 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8287 &pipe_config->dp_m_n,
8288 &pipe_config->dp_m2_n2);
8289 }
8290
8291 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8292 struct intel_crtc_state *pipe_config)
8293 {
8294 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8295 &pipe_config->fdi_m_n, NULL);
8296 }
8297
8298 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8299 struct intel_crtc_state *pipe_config)
8300 {
8301 struct drm_device *dev = crtc->base.dev;
8302 struct drm_i915_private *dev_priv = to_i915(dev);
8303 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8304 uint32_t ps_ctrl = 0;
8305 int id = -1;
8306 int i;
8307
8308 /* find scaler attached to this pipe */
8309 for (i = 0; i < crtc->num_scalers; i++) {
8310 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8311 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8312 id = i;
8313 pipe_config->pch_pfit.enabled = true;
8314 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8315 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8316 break;
8317 }
8318 }
8319
8320 scaler_state->scaler_id = id;
8321 if (id >= 0) {
8322 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8323 } else {
8324 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8325 }
8326 }
8327
8328 static void
8329 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8330 struct intel_initial_plane_config *plane_config)
8331 {
8332 struct drm_device *dev = crtc->base.dev;
8333 struct drm_i915_private *dev_priv = to_i915(dev);
8334 u32 val, base, offset, stride_mult, tiling;
8335 int pipe = crtc->pipe;
8336 int fourcc, pixel_format;
8337 unsigned int aligned_height;
8338 struct drm_framebuffer *fb;
8339 struct intel_framebuffer *intel_fb;
8340
8341 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8342 if (!intel_fb) {
8343 DRM_DEBUG_KMS("failed to alloc fb\n");
8344 return;
8345 }
8346
8347 fb = &intel_fb->base;
8348
8349 fb->dev = dev;
8350
8351 val = I915_READ(PLANE_CTL(pipe, 0));
8352 if (!(val & PLANE_CTL_ENABLE))
8353 goto error;
8354
8355 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8356 fourcc = skl_format_to_fourcc(pixel_format,
8357 val & PLANE_CTL_ORDER_RGBX,
8358 val & PLANE_CTL_ALPHA_MASK);
8359 fb->format = drm_format_info(fourcc);
8360
8361 tiling = val & PLANE_CTL_TILED_MASK;
8362 switch (tiling) {
8363 case PLANE_CTL_TILED_LINEAR:
8364 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8365 break;
8366 case PLANE_CTL_TILED_X:
8367 plane_config->tiling = I915_TILING_X;
8368 fb->modifier = I915_FORMAT_MOD_X_TILED;
8369 break;
8370 case PLANE_CTL_TILED_Y:
8371 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8372 break;
8373 case PLANE_CTL_TILED_YF:
8374 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8375 break;
8376 default:
8377 MISSING_CASE(tiling);
8378 goto error;
8379 }
8380
8381 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8382 plane_config->base = base;
8383
8384 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8385
8386 val = I915_READ(PLANE_SIZE(pipe, 0));
8387 fb->height = ((val >> 16) & 0xfff) + 1;
8388 fb->width = ((val >> 0) & 0x1fff) + 1;
8389
8390 val = I915_READ(PLANE_STRIDE(pipe, 0));
8391 stride_mult = intel_fb_stride_alignment(fb, 0);
8392 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8393
8394 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8395
8396 plane_config->size = fb->pitches[0] * aligned_height;
8397
8398 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8399 pipe_name(pipe), fb->width, fb->height,
8400 fb->format->cpp[0] * 8, base, fb->pitches[0],
8401 plane_config->size);
8402
8403 plane_config->fb = intel_fb;
8404 return;
8405
8406 error:
8407 kfree(intel_fb);
8408 }
8409
8410 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8411 struct intel_crtc_state *pipe_config)
8412 {
8413 struct drm_device *dev = crtc->base.dev;
8414 struct drm_i915_private *dev_priv = to_i915(dev);
8415 uint32_t tmp;
8416
8417 tmp = I915_READ(PF_CTL(crtc->pipe));
8418
8419 if (tmp & PF_ENABLE) {
8420 pipe_config->pch_pfit.enabled = true;
8421 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8422 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8423
8424 /* We currently do not free assignements of panel fitters on
8425 * ivb/hsw (since we don't use the higher upscaling modes which
8426 * differentiates them) so just WARN about this case for now. */
8427 if (IS_GEN7(dev_priv)) {
8428 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8429 PF_PIPE_SEL_IVB(crtc->pipe));
8430 }
8431 }
8432 }
8433
8434 static void
8435 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8436 struct intel_initial_plane_config *plane_config)
8437 {
8438 struct drm_device *dev = crtc->base.dev;
8439 struct drm_i915_private *dev_priv = to_i915(dev);
8440 u32 val, base, offset;
8441 int pipe = crtc->pipe;
8442 int fourcc, pixel_format;
8443 unsigned int aligned_height;
8444 struct drm_framebuffer *fb;
8445 struct intel_framebuffer *intel_fb;
8446
8447 val = I915_READ(DSPCNTR(pipe));
8448 if (!(val & DISPLAY_PLANE_ENABLE))
8449 return;
8450
8451 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8452 if (!intel_fb) {
8453 DRM_DEBUG_KMS("failed to alloc fb\n");
8454 return;
8455 }
8456
8457 fb = &intel_fb->base;
8458
8459 fb->dev = dev;
8460
8461 if (INTEL_GEN(dev_priv) >= 4) {
8462 if (val & DISPPLANE_TILED) {
8463 plane_config->tiling = I915_TILING_X;
8464 fb->modifier = I915_FORMAT_MOD_X_TILED;
8465 }
8466 }
8467
8468 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8469 fourcc = i9xx_format_to_fourcc(pixel_format);
8470 fb->format = drm_format_info(fourcc);
8471
8472 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8473 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8474 offset = I915_READ(DSPOFFSET(pipe));
8475 } else {
8476 if (plane_config->tiling)
8477 offset = I915_READ(DSPTILEOFF(pipe));
8478 else
8479 offset = I915_READ(DSPLINOFF(pipe));
8480 }
8481 plane_config->base = base;
8482
8483 val = I915_READ(PIPESRC(pipe));
8484 fb->width = ((val >> 16) & 0xfff) + 1;
8485 fb->height = ((val >> 0) & 0xfff) + 1;
8486
8487 val = I915_READ(DSPSTRIDE(pipe));
8488 fb->pitches[0] = val & 0xffffffc0;
8489
8490 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8491
8492 plane_config->size = fb->pitches[0] * aligned_height;
8493
8494 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8495 pipe_name(pipe), fb->width, fb->height,
8496 fb->format->cpp[0] * 8, base, fb->pitches[0],
8497 plane_config->size);
8498
8499 plane_config->fb = intel_fb;
8500 }
8501
8502 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8503 struct intel_crtc_state *pipe_config)
8504 {
8505 struct drm_device *dev = crtc->base.dev;
8506 struct drm_i915_private *dev_priv = to_i915(dev);
8507 enum intel_display_power_domain power_domain;
8508 uint32_t tmp;
8509 bool ret;
8510
8511 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8512 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8513 return false;
8514
8515 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8516 pipe_config->shared_dpll = NULL;
8517
8518 ret = false;
8519 tmp = I915_READ(PIPECONF(crtc->pipe));
8520 if (!(tmp & PIPECONF_ENABLE))
8521 goto out;
8522
8523 switch (tmp & PIPECONF_BPC_MASK) {
8524 case PIPECONF_6BPC:
8525 pipe_config->pipe_bpp = 18;
8526 break;
8527 case PIPECONF_8BPC:
8528 pipe_config->pipe_bpp = 24;
8529 break;
8530 case PIPECONF_10BPC:
8531 pipe_config->pipe_bpp = 30;
8532 break;
8533 case PIPECONF_12BPC:
8534 pipe_config->pipe_bpp = 36;
8535 break;
8536 default:
8537 break;
8538 }
8539
8540 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8541 pipe_config->limited_color_range = true;
8542
8543 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8544 struct intel_shared_dpll *pll;
8545 enum intel_dpll_id pll_id;
8546
8547 pipe_config->has_pch_encoder = true;
8548
8549 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8550 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8551 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8552
8553 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8554
8555 if (HAS_PCH_IBX(dev_priv)) {
8556 /*
8557 * The pipe->pch transcoder and pch transcoder->pll
8558 * mapping is fixed.
8559 */
8560 pll_id = (enum intel_dpll_id) crtc->pipe;
8561 } else {
8562 tmp = I915_READ(PCH_DPLL_SEL);
8563 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8564 pll_id = DPLL_ID_PCH_PLL_B;
8565 else
8566 pll_id= DPLL_ID_PCH_PLL_A;
8567 }
8568
8569 pipe_config->shared_dpll =
8570 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8571 pll = pipe_config->shared_dpll;
8572
8573 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8574 &pipe_config->dpll_hw_state));
8575
8576 tmp = pipe_config->dpll_hw_state.dpll;
8577 pipe_config->pixel_multiplier =
8578 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8579 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8580
8581 ironlake_pch_clock_get(crtc, pipe_config);
8582 } else {
8583 pipe_config->pixel_multiplier = 1;
8584 }
8585
8586 intel_get_pipe_timings(crtc, pipe_config);
8587 intel_get_pipe_src_size(crtc, pipe_config);
8588
8589 ironlake_get_pfit_config(crtc, pipe_config);
8590
8591 ret = true;
8592
8593 out:
8594 intel_display_power_put(dev_priv, power_domain);
8595
8596 return ret;
8597 }
8598
8599 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8600 {
8601 struct drm_device *dev = &dev_priv->drm;
8602 struct intel_crtc *crtc;
8603
8604 for_each_intel_crtc(dev, crtc)
8605 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8606 pipe_name(crtc->pipe));
8607
8608 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8609 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8610 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8611 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8612 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8613 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8614 "CPU PWM1 enabled\n");
8615 if (IS_HASWELL(dev_priv))
8616 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8617 "CPU PWM2 enabled\n");
8618 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8619 "PCH PWM1 enabled\n");
8620 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8621 "Utility pin enabled\n");
8622 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8623
8624 /*
8625 * In theory we can still leave IRQs enabled, as long as only the HPD
8626 * interrupts remain enabled. We used to check for that, but since it's
8627 * gen-specific and since we only disable LCPLL after we fully disable
8628 * the interrupts, the check below should be enough.
8629 */
8630 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8631 }
8632
8633 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8634 {
8635 if (IS_HASWELL(dev_priv))
8636 return I915_READ(D_COMP_HSW);
8637 else
8638 return I915_READ(D_COMP_BDW);
8639 }
8640
8641 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8642 {
8643 if (IS_HASWELL(dev_priv)) {
8644 mutex_lock(&dev_priv->rps.hw_lock);
8645 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8646 val))
8647 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8648 mutex_unlock(&dev_priv->rps.hw_lock);
8649 } else {
8650 I915_WRITE(D_COMP_BDW, val);
8651 POSTING_READ(D_COMP_BDW);
8652 }
8653 }
8654
8655 /*
8656 * This function implements pieces of two sequences from BSpec:
8657 * - Sequence for display software to disable LCPLL
8658 * - Sequence for display software to allow package C8+
8659 * The steps implemented here are just the steps that actually touch the LCPLL
8660 * register. Callers should take care of disabling all the display engine
8661 * functions, doing the mode unset, fixing interrupts, etc.
8662 */
8663 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8664 bool switch_to_fclk, bool allow_power_down)
8665 {
8666 uint32_t val;
8667
8668 assert_can_disable_lcpll(dev_priv);
8669
8670 val = I915_READ(LCPLL_CTL);
8671
8672 if (switch_to_fclk) {
8673 val |= LCPLL_CD_SOURCE_FCLK;
8674 I915_WRITE(LCPLL_CTL, val);
8675
8676 if (wait_for_us(I915_READ(LCPLL_CTL) &
8677 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8678 DRM_ERROR("Switching to FCLK failed\n");
8679
8680 val = I915_READ(LCPLL_CTL);
8681 }
8682
8683 val |= LCPLL_PLL_DISABLE;
8684 I915_WRITE(LCPLL_CTL, val);
8685 POSTING_READ(LCPLL_CTL);
8686
8687 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8688 DRM_ERROR("LCPLL still locked\n");
8689
8690 val = hsw_read_dcomp(dev_priv);
8691 val |= D_COMP_COMP_DISABLE;
8692 hsw_write_dcomp(dev_priv, val);
8693 ndelay(100);
8694
8695 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8696 1))
8697 DRM_ERROR("D_COMP RCOMP still in progress\n");
8698
8699 if (allow_power_down) {
8700 val = I915_READ(LCPLL_CTL);
8701 val |= LCPLL_POWER_DOWN_ALLOW;
8702 I915_WRITE(LCPLL_CTL, val);
8703 POSTING_READ(LCPLL_CTL);
8704 }
8705 }
8706
8707 /*
8708 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8709 * source.
8710 */
8711 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8712 {
8713 uint32_t val;
8714
8715 val = I915_READ(LCPLL_CTL);
8716
8717 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8718 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8719 return;
8720
8721 /*
8722 * Make sure we're not on PC8 state before disabling PC8, otherwise
8723 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8724 */
8725 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8726
8727 if (val & LCPLL_POWER_DOWN_ALLOW) {
8728 val &= ~LCPLL_POWER_DOWN_ALLOW;
8729 I915_WRITE(LCPLL_CTL, val);
8730 POSTING_READ(LCPLL_CTL);
8731 }
8732
8733 val = hsw_read_dcomp(dev_priv);
8734 val |= D_COMP_COMP_FORCE;
8735 val &= ~D_COMP_COMP_DISABLE;
8736 hsw_write_dcomp(dev_priv, val);
8737
8738 val = I915_READ(LCPLL_CTL);
8739 val &= ~LCPLL_PLL_DISABLE;
8740 I915_WRITE(LCPLL_CTL, val);
8741
8742 if (intel_wait_for_register(dev_priv,
8743 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8744 5))
8745 DRM_ERROR("LCPLL not locked yet\n");
8746
8747 if (val & LCPLL_CD_SOURCE_FCLK) {
8748 val = I915_READ(LCPLL_CTL);
8749 val &= ~LCPLL_CD_SOURCE_FCLK;
8750 I915_WRITE(LCPLL_CTL, val);
8751
8752 if (wait_for_us((I915_READ(LCPLL_CTL) &
8753 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8754 DRM_ERROR("Switching back to LCPLL failed\n");
8755 }
8756
8757 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8758 intel_update_cdclk(dev_priv);
8759 }
8760
8761 /*
8762 * Package states C8 and deeper are really deep PC states that can only be
8763 * reached when all the devices on the system allow it, so even if the graphics
8764 * device allows PC8+, it doesn't mean the system will actually get to these
8765 * states. Our driver only allows PC8+ when going into runtime PM.
8766 *
8767 * The requirements for PC8+ are that all the outputs are disabled, the power
8768 * well is disabled and most interrupts are disabled, and these are also
8769 * requirements for runtime PM. When these conditions are met, we manually do
8770 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8771 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8772 * hang the machine.
8773 *
8774 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8775 * the state of some registers, so when we come back from PC8+ we need to
8776 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8777 * need to take care of the registers kept by RC6. Notice that this happens even
8778 * if we don't put the device in PCI D3 state (which is what currently happens
8779 * because of the runtime PM support).
8780 *
8781 * For more, read "Display Sequences for Package C8" on the hardware
8782 * documentation.
8783 */
8784 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8785 {
8786 uint32_t val;
8787
8788 DRM_DEBUG_KMS("Enabling package C8+\n");
8789
8790 if (HAS_PCH_LPT_LP(dev_priv)) {
8791 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8792 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8793 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8794 }
8795
8796 lpt_disable_clkout_dp(dev_priv);
8797 hsw_disable_lcpll(dev_priv, true, true);
8798 }
8799
8800 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8801 {
8802 uint32_t val;
8803
8804 DRM_DEBUG_KMS("Disabling package C8+\n");
8805
8806 hsw_restore_lcpll(dev_priv);
8807 lpt_init_pch_refclk(dev_priv);
8808
8809 if (HAS_PCH_LPT_LP(dev_priv)) {
8810 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8811 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8812 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8813 }
8814 }
8815
8816 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8817 struct intel_crtc_state *crtc_state)
8818 {
8819 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8820 struct intel_encoder *encoder =
8821 intel_ddi_get_crtc_new_encoder(crtc_state);
8822
8823 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8824 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8825 pipe_name(crtc->pipe));
8826 return -EINVAL;
8827 }
8828 }
8829
8830 crtc->lowfreq_avail = false;
8831
8832 return 0;
8833 }
8834
8835 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8836 enum port port,
8837 struct intel_crtc_state *pipe_config)
8838 {
8839 enum intel_dpll_id id;
8840 u32 temp;
8841
8842 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8843 id = temp >> (port * 2);
8844
8845 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8846 return;
8847
8848 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8849 }
8850
8851 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8852 enum port port,
8853 struct intel_crtc_state *pipe_config)
8854 {
8855 enum intel_dpll_id id;
8856
8857 switch (port) {
8858 case PORT_A:
8859 id = DPLL_ID_SKL_DPLL0;
8860 break;
8861 case PORT_B:
8862 id = DPLL_ID_SKL_DPLL1;
8863 break;
8864 case PORT_C:
8865 id = DPLL_ID_SKL_DPLL2;
8866 break;
8867 default:
8868 DRM_ERROR("Incorrect port type\n");
8869 return;
8870 }
8871
8872 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8873 }
8874
8875 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8876 enum port port,
8877 struct intel_crtc_state *pipe_config)
8878 {
8879 enum intel_dpll_id id;
8880 u32 temp;
8881
8882 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8883 id = temp >> (port * 3 + 1);
8884
8885 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8886 return;
8887
8888 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8889 }
8890
8891 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8892 enum port port,
8893 struct intel_crtc_state *pipe_config)
8894 {
8895 enum intel_dpll_id id;
8896 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8897
8898 switch (ddi_pll_sel) {
8899 case PORT_CLK_SEL_WRPLL1:
8900 id = DPLL_ID_WRPLL1;
8901 break;
8902 case PORT_CLK_SEL_WRPLL2:
8903 id = DPLL_ID_WRPLL2;
8904 break;
8905 case PORT_CLK_SEL_SPLL:
8906 id = DPLL_ID_SPLL;
8907 break;
8908 case PORT_CLK_SEL_LCPLL_810:
8909 id = DPLL_ID_LCPLL_810;
8910 break;
8911 case PORT_CLK_SEL_LCPLL_1350:
8912 id = DPLL_ID_LCPLL_1350;
8913 break;
8914 case PORT_CLK_SEL_LCPLL_2700:
8915 id = DPLL_ID_LCPLL_2700;
8916 break;
8917 default:
8918 MISSING_CASE(ddi_pll_sel);
8919 /* fall through */
8920 case PORT_CLK_SEL_NONE:
8921 return;
8922 }
8923
8924 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8925 }
8926
8927 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8928 struct intel_crtc_state *pipe_config,
8929 u64 *power_domain_mask)
8930 {
8931 struct drm_device *dev = crtc->base.dev;
8932 struct drm_i915_private *dev_priv = to_i915(dev);
8933 enum intel_display_power_domain power_domain;
8934 u32 tmp;
8935
8936 /*
8937 * The pipe->transcoder mapping is fixed with the exception of the eDP
8938 * transcoder handled below.
8939 */
8940 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8941
8942 /*
8943 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8944 * consistency and less surprising code; it's in always on power).
8945 */
8946 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8947 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8948 enum pipe trans_edp_pipe;
8949 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8950 default:
8951 WARN(1, "unknown pipe linked to edp transcoder\n");
8952 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8953 case TRANS_DDI_EDP_INPUT_A_ON:
8954 trans_edp_pipe = PIPE_A;
8955 break;
8956 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8957 trans_edp_pipe = PIPE_B;
8958 break;
8959 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8960 trans_edp_pipe = PIPE_C;
8961 break;
8962 }
8963
8964 if (trans_edp_pipe == crtc->pipe)
8965 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8966 }
8967
8968 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8969 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8970 return false;
8971 *power_domain_mask |= BIT_ULL(power_domain);
8972
8973 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8974
8975 return tmp & PIPECONF_ENABLE;
8976 }
8977
8978 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8979 struct intel_crtc_state *pipe_config,
8980 u64 *power_domain_mask)
8981 {
8982 struct drm_device *dev = crtc->base.dev;
8983 struct drm_i915_private *dev_priv = to_i915(dev);
8984 enum intel_display_power_domain power_domain;
8985 enum port port;
8986 enum transcoder cpu_transcoder;
8987 u32 tmp;
8988
8989 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8990 if (port == PORT_A)
8991 cpu_transcoder = TRANSCODER_DSI_A;
8992 else
8993 cpu_transcoder = TRANSCODER_DSI_C;
8994
8995 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
8996 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8997 continue;
8998 *power_domain_mask |= BIT_ULL(power_domain);
8999
9000 /*
9001 * The PLL needs to be enabled with a valid divider
9002 * configuration, otherwise accessing DSI registers will hang
9003 * the machine. See BSpec North Display Engine
9004 * registers/MIPI[BXT]. We can break out here early, since we
9005 * need the same DSI PLL to be enabled for both DSI ports.
9006 */
9007 if (!intel_dsi_pll_is_enabled(dev_priv))
9008 break;
9009
9010 /* XXX: this works for video mode only */
9011 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9012 if (!(tmp & DPI_ENABLE))
9013 continue;
9014
9015 tmp = I915_READ(MIPI_CTRL(port));
9016 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9017 continue;
9018
9019 pipe_config->cpu_transcoder = cpu_transcoder;
9020 break;
9021 }
9022
9023 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9024 }
9025
9026 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9027 struct intel_crtc_state *pipe_config)
9028 {
9029 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9030 struct intel_shared_dpll *pll;
9031 enum port port;
9032 uint32_t tmp;
9033
9034 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9035
9036 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9037
9038 if (IS_CANNONLAKE(dev_priv))
9039 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9040 else if (IS_GEN9_BC(dev_priv))
9041 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9042 else if (IS_GEN9_LP(dev_priv))
9043 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9044 else
9045 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9046
9047 pll = pipe_config->shared_dpll;
9048 if (pll) {
9049 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9050 &pipe_config->dpll_hw_state));
9051 }
9052
9053 /*
9054 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9055 * DDI E. So just check whether this pipe is wired to DDI E and whether
9056 * the PCH transcoder is on.
9057 */
9058 if (INTEL_GEN(dev_priv) < 9 &&
9059 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9060 pipe_config->has_pch_encoder = true;
9061
9062 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9063 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9064 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9065
9066 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9067 }
9068 }
9069
9070 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9071 struct intel_crtc_state *pipe_config)
9072 {
9073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9074 enum intel_display_power_domain power_domain;
9075 u64 power_domain_mask;
9076 bool active;
9077
9078 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9079 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9080 return false;
9081 power_domain_mask = BIT_ULL(power_domain);
9082
9083 pipe_config->shared_dpll = NULL;
9084
9085 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9086
9087 if (IS_GEN9_LP(dev_priv) &&
9088 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9089 WARN_ON(active);
9090 active = true;
9091 }
9092
9093 if (!active)
9094 goto out;
9095
9096 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9097 haswell_get_ddi_port_state(crtc, pipe_config);
9098 intel_get_pipe_timings(crtc, pipe_config);
9099 }
9100
9101 intel_get_pipe_src_size(crtc, pipe_config);
9102
9103 pipe_config->gamma_mode =
9104 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9105
9106 if (INTEL_GEN(dev_priv) >= 9) {
9107 intel_crtc_init_scalers(crtc, pipe_config);
9108
9109 pipe_config->scaler_state.scaler_id = -1;
9110 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9111 }
9112
9113 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9114 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9115 power_domain_mask |= BIT_ULL(power_domain);
9116 if (INTEL_GEN(dev_priv) >= 9)
9117 skylake_get_pfit_config(crtc, pipe_config);
9118 else
9119 ironlake_get_pfit_config(crtc, pipe_config);
9120 }
9121
9122 if (IS_HASWELL(dev_priv))
9123 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9124 (I915_READ(IPS_CTL) & IPS_ENABLE);
9125
9126 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9127 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9128 pipe_config->pixel_multiplier =
9129 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9130 } else {
9131 pipe_config->pixel_multiplier = 1;
9132 }
9133
9134 out:
9135 for_each_power_domain(power_domain, power_domain_mask)
9136 intel_display_power_put(dev_priv, power_domain);
9137
9138 return active;
9139 }
9140
9141 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9142 {
9143 struct drm_i915_private *dev_priv =
9144 to_i915(plane_state->base.plane->dev);
9145 const struct drm_framebuffer *fb = plane_state->base.fb;
9146 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9147 u32 base;
9148
9149 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9150 base = obj->phys_handle->busaddr;
9151 else
9152 base = intel_plane_ggtt_offset(plane_state);
9153
9154 base += plane_state->main.offset;
9155
9156 /* ILK+ do this automagically */
9157 if (HAS_GMCH_DISPLAY(dev_priv) &&
9158 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9159 base += (plane_state->base.crtc_h *
9160 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9161
9162 return base;
9163 }
9164
9165 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9166 {
9167 int x = plane_state->base.crtc_x;
9168 int y = plane_state->base.crtc_y;
9169 u32 pos = 0;
9170
9171 if (x < 0) {
9172 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9173 x = -x;
9174 }
9175 pos |= x << CURSOR_X_SHIFT;
9176
9177 if (y < 0) {
9178 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9179 y = -y;
9180 }
9181 pos |= y << CURSOR_Y_SHIFT;
9182
9183 return pos;
9184 }
9185
9186 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9187 {
9188 const struct drm_mode_config *config =
9189 &plane_state->base.plane->dev->mode_config;
9190 int width = plane_state->base.crtc_w;
9191 int height = plane_state->base.crtc_h;
9192
9193 return width > 0 && width <= config->cursor_width &&
9194 height > 0 && height <= config->cursor_height;
9195 }
9196
9197 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9198 struct intel_plane_state *plane_state)
9199 {
9200 const struct drm_framebuffer *fb = plane_state->base.fb;
9201 int src_x, src_y;
9202 u32 offset;
9203 int ret;
9204
9205 ret = drm_plane_helper_check_state(&plane_state->base,
9206 &plane_state->clip,
9207 DRM_PLANE_HELPER_NO_SCALING,
9208 DRM_PLANE_HELPER_NO_SCALING,
9209 true, true);
9210 if (ret)
9211 return ret;
9212
9213 if (!fb)
9214 return 0;
9215
9216 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9217 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9218 return -EINVAL;
9219 }
9220
9221 src_x = plane_state->base.src_x >> 16;
9222 src_y = plane_state->base.src_y >> 16;
9223
9224 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9225 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9226
9227 if (src_x != 0 || src_y != 0) {
9228 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9229 return -EINVAL;
9230 }
9231
9232 plane_state->main.offset = offset;
9233
9234 return 0;
9235 }
9236
9237 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9238 const struct intel_plane_state *plane_state)
9239 {
9240 const struct drm_framebuffer *fb = plane_state->base.fb;
9241
9242 return CURSOR_ENABLE |
9243 CURSOR_GAMMA_ENABLE |
9244 CURSOR_FORMAT_ARGB |
9245 CURSOR_STRIDE(fb->pitches[0]);
9246 }
9247
9248 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9249 {
9250 int width = plane_state->base.crtc_w;
9251
9252 /*
9253 * 845g/865g are only limited by the width of their cursors,
9254 * the height is arbitrary up to the precision of the register.
9255 */
9256 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9257 }
9258
9259 static int i845_check_cursor(struct intel_plane *plane,
9260 struct intel_crtc_state *crtc_state,
9261 struct intel_plane_state *plane_state)
9262 {
9263 const struct drm_framebuffer *fb = plane_state->base.fb;
9264 int ret;
9265
9266 ret = intel_check_cursor(crtc_state, plane_state);
9267 if (ret)
9268 return ret;
9269
9270 /* if we want to turn off the cursor ignore width and height */
9271 if (!fb)
9272 return 0;
9273
9274 /* Check for which cursor types we support */
9275 if (!i845_cursor_size_ok(plane_state)) {
9276 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9277 plane_state->base.crtc_w,
9278 plane_state->base.crtc_h);
9279 return -EINVAL;
9280 }
9281
9282 switch (fb->pitches[0]) {
9283 case 256:
9284 case 512:
9285 case 1024:
9286 case 2048:
9287 break;
9288 default:
9289 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9290 fb->pitches[0]);
9291 return -EINVAL;
9292 }
9293
9294 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9295
9296 return 0;
9297 }
9298
9299 static void i845_update_cursor(struct intel_plane *plane,
9300 const struct intel_crtc_state *crtc_state,
9301 const struct intel_plane_state *plane_state)
9302 {
9303 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9304 u32 cntl = 0, base = 0, pos = 0, size = 0;
9305 unsigned long irqflags;
9306
9307 if (plane_state && plane_state->base.visible) {
9308 unsigned int width = plane_state->base.crtc_w;
9309 unsigned int height = plane_state->base.crtc_h;
9310
9311 cntl = plane_state->ctl;
9312 size = (height << 12) | width;
9313
9314 base = intel_cursor_base(plane_state);
9315 pos = intel_cursor_position(plane_state);
9316 }
9317
9318 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9319
9320 /* On these chipsets we can only modify the base/size/stride
9321 * whilst the cursor is disabled.
9322 */
9323 if (plane->cursor.base != base ||
9324 plane->cursor.size != size ||
9325 plane->cursor.cntl != cntl) {
9326 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9327 I915_WRITE_FW(CURBASE(PIPE_A), base);
9328 I915_WRITE_FW(CURSIZE, size);
9329 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9330 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9331
9332 plane->cursor.base = base;
9333 plane->cursor.size = size;
9334 plane->cursor.cntl = cntl;
9335 } else {
9336 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9337 }
9338
9339 POSTING_READ_FW(CURCNTR(PIPE_A));
9340
9341 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9342 }
9343
9344 static void i845_disable_cursor(struct intel_plane *plane,
9345 struct intel_crtc *crtc)
9346 {
9347 i845_update_cursor(plane, NULL, NULL);
9348 }
9349
9350 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9351 const struct intel_plane_state *plane_state)
9352 {
9353 struct drm_i915_private *dev_priv =
9354 to_i915(plane_state->base.plane->dev);
9355 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9356 u32 cntl;
9357
9358 cntl = MCURSOR_GAMMA_ENABLE;
9359
9360 if (HAS_DDI(dev_priv))
9361 cntl |= CURSOR_PIPE_CSC_ENABLE;
9362
9363 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9364
9365 switch (plane_state->base.crtc_w) {
9366 case 64:
9367 cntl |= CURSOR_MODE_64_ARGB_AX;
9368 break;
9369 case 128:
9370 cntl |= CURSOR_MODE_128_ARGB_AX;
9371 break;
9372 case 256:
9373 cntl |= CURSOR_MODE_256_ARGB_AX;
9374 break;
9375 default:
9376 MISSING_CASE(plane_state->base.crtc_w);
9377 return 0;
9378 }
9379
9380 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9381 cntl |= CURSOR_ROTATE_180;
9382
9383 return cntl;
9384 }
9385
9386 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9387 {
9388 struct drm_i915_private *dev_priv =
9389 to_i915(plane_state->base.plane->dev);
9390 int width = plane_state->base.crtc_w;
9391 int height = plane_state->base.crtc_h;
9392
9393 if (!intel_cursor_size_ok(plane_state))
9394 return false;
9395
9396 /* Cursor width is limited to a few power-of-two sizes */
9397 switch (width) {
9398 case 256:
9399 case 128:
9400 case 64:
9401 break;
9402 default:
9403 return false;
9404 }
9405
9406 /*
9407 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9408 * height from 8 lines up to the cursor width, when the
9409 * cursor is not rotated. Everything else requires square
9410 * cursors.
9411 */
9412 if (HAS_CUR_FBC(dev_priv) &&
9413 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9414 if (height < 8 || height > width)
9415 return false;
9416 } else {
9417 if (height != width)
9418 return false;
9419 }
9420
9421 return true;
9422 }
9423
9424 static int i9xx_check_cursor(struct intel_plane *plane,
9425 struct intel_crtc_state *crtc_state,
9426 struct intel_plane_state *plane_state)
9427 {
9428 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9429 const struct drm_framebuffer *fb = plane_state->base.fb;
9430 enum pipe pipe = plane->pipe;
9431 int ret;
9432
9433 ret = intel_check_cursor(crtc_state, plane_state);
9434 if (ret)
9435 return ret;
9436
9437 /* if we want to turn off the cursor ignore width and height */
9438 if (!fb)
9439 return 0;
9440
9441 /* Check for which cursor types we support */
9442 if (!i9xx_cursor_size_ok(plane_state)) {
9443 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9444 plane_state->base.crtc_w,
9445 plane_state->base.crtc_h);
9446 return -EINVAL;
9447 }
9448
9449 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9450 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9451 fb->pitches[0], plane_state->base.crtc_w);
9452 return -EINVAL;
9453 }
9454
9455 /*
9456 * There's something wrong with the cursor on CHV pipe C.
9457 * If it straddles the left edge of the screen then
9458 * moving it away from the edge or disabling it often
9459 * results in a pipe underrun, and often that can lead to
9460 * dead pipe (constant underrun reported, and it scans
9461 * out just a solid color). To recover from that, the
9462 * display power well must be turned off and on again.
9463 * Refuse the put the cursor into that compromised position.
9464 */
9465 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9466 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9467 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9468 return -EINVAL;
9469 }
9470
9471 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9472
9473 return 0;
9474 }
9475
9476 static void i9xx_update_cursor(struct intel_plane *plane,
9477 const struct intel_crtc_state *crtc_state,
9478 const struct intel_plane_state *plane_state)
9479 {
9480 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9481 enum pipe pipe = plane->pipe;
9482 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9483 unsigned long irqflags;
9484
9485 if (plane_state && plane_state->base.visible) {
9486 cntl = plane_state->ctl;
9487
9488 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9489 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9490
9491 base = intel_cursor_base(plane_state);
9492 pos = intel_cursor_position(plane_state);
9493 }
9494
9495 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9496
9497 /*
9498 * On some platforms writing CURCNTR first will also
9499 * cause CURPOS to be armed by the CURBASE write.
9500 * Without the CURCNTR write the CURPOS write would
9501 * arm itself. Thus we always start the full update
9502 * with a CURCNTR write.
9503 *
9504 * On other platforms CURPOS always requires the
9505 * CURBASE write to arm the update. Additonally
9506 * a write to any of the cursor register will cancel
9507 * an already armed cursor update. Thus leaving out
9508 * the CURBASE write after CURPOS could lead to a
9509 * cursor that doesn't appear to move, or even change
9510 * shape. Thus we always write CURBASE.
9511 *
9512 * CURCNTR and CUR_FBC_CTL are always
9513 * armed by the CURBASE write only.
9514 */
9515 if (plane->cursor.base != base ||
9516 plane->cursor.size != fbc_ctl ||
9517 plane->cursor.cntl != cntl) {
9518 I915_WRITE_FW(CURCNTR(pipe), cntl);
9519 if (HAS_CUR_FBC(dev_priv))
9520 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9521 I915_WRITE_FW(CURPOS(pipe), pos);
9522 I915_WRITE_FW(CURBASE(pipe), base);
9523
9524 plane->cursor.base = base;
9525 plane->cursor.size = fbc_ctl;
9526 plane->cursor.cntl = cntl;
9527 } else {
9528 I915_WRITE_FW(CURPOS(pipe), pos);
9529 I915_WRITE_FW(CURBASE(pipe), base);
9530 }
9531
9532 POSTING_READ_FW(CURBASE(pipe));
9533
9534 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9535 }
9536
9537 static void i9xx_disable_cursor(struct intel_plane *plane,
9538 struct intel_crtc *crtc)
9539 {
9540 i9xx_update_cursor(plane, NULL, NULL);
9541 }
9542
9543
9544 /* VESA 640x480x72Hz mode to set on the pipe */
9545 static struct drm_display_mode load_detect_mode = {
9546 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9547 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9548 };
9549
9550 struct drm_framebuffer *
9551 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9552 struct drm_mode_fb_cmd2 *mode_cmd)
9553 {
9554 struct intel_framebuffer *intel_fb;
9555 int ret;
9556
9557 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9558 if (!intel_fb)
9559 return ERR_PTR(-ENOMEM);
9560
9561 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9562 if (ret)
9563 goto err;
9564
9565 return &intel_fb->base;
9566
9567 err:
9568 kfree(intel_fb);
9569 return ERR_PTR(ret);
9570 }
9571
9572 static u32
9573 intel_framebuffer_pitch_for_width(int width, int bpp)
9574 {
9575 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9576 return ALIGN(pitch, 64);
9577 }
9578
9579 static u32
9580 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9581 {
9582 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9583 return PAGE_ALIGN(pitch * mode->vdisplay);
9584 }
9585
9586 static struct drm_framebuffer *
9587 intel_framebuffer_create_for_mode(struct drm_device *dev,
9588 struct drm_display_mode *mode,
9589 int depth, int bpp)
9590 {
9591 struct drm_framebuffer *fb;
9592 struct drm_i915_gem_object *obj;
9593 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9594
9595 obj = i915_gem_object_create(to_i915(dev),
9596 intel_framebuffer_size_for_mode(mode, bpp));
9597 if (IS_ERR(obj))
9598 return ERR_CAST(obj);
9599
9600 mode_cmd.width = mode->hdisplay;
9601 mode_cmd.height = mode->vdisplay;
9602 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9603 bpp);
9604 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9605
9606 fb = intel_framebuffer_create(obj, &mode_cmd);
9607 if (IS_ERR(fb))
9608 i915_gem_object_put(obj);
9609
9610 return fb;
9611 }
9612
9613 static struct drm_framebuffer *
9614 mode_fits_in_fbdev(struct drm_device *dev,
9615 struct drm_display_mode *mode)
9616 {
9617 #ifdef CONFIG_DRM_FBDEV_EMULATION
9618 struct drm_i915_private *dev_priv = to_i915(dev);
9619 struct drm_i915_gem_object *obj;
9620 struct drm_framebuffer *fb;
9621
9622 if (!dev_priv->fbdev)
9623 return NULL;
9624
9625 if (!dev_priv->fbdev->fb)
9626 return NULL;
9627
9628 obj = dev_priv->fbdev->fb->obj;
9629 BUG_ON(!obj);
9630
9631 fb = &dev_priv->fbdev->fb->base;
9632 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9633 fb->format->cpp[0] * 8))
9634 return NULL;
9635
9636 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9637 return NULL;
9638
9639 drm_framebuffer_reference(fb);
9640 return fb;
9641 #else
9642 return NULL;
9643 #endif
9644 }
9645
9646 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9647 struct drm_crtc *crtc,
9648 struct drm_display_mode *mode,
9649 struct drm_framebuffer *fb,
9650 int x, int y)
9651 {
9652 struct drm_plane_state *plane_state;
9653 int hdisplay, vdisplay;
9654 int ret;
9655
9656 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9657 if (IS_ERR(plane_state))
9658 return PTR_ERR(plane_state);
9659
9660 if (mode)
9661 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9662 else
9663 hdisplay = vdisplay = 0;
9664
9665 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9666 if (ret)
9667 return ret;
9668 drm_atomic_set_fb_for_plane(plane_state, fb);
9669 plane_state->crtc_x = 0;
9670 plane_state->crtc_y = 0;
9671 plane_state->crtc_w = hdisplay;
9672 plane_state->crtc_h = vdisplay;
9673 plane_state->src_x = x << 16;
9674 plane_state->src_y = y << 16;
9675 plane_state->src_w = hdisplay << 16;
9676 plane_state->src_h = vdisplay << 16;
9677
9678 return 0;
9679 }
9680
9681 int intel_get_load_detect_pipe(struct drm_connector *connector,
9682 struct drm_display_mode *mode,
9683 struct intel_load_detect_pipe *old,
9684 struct drm_modeset_acquire_ctx *ctx)
9685 {
9686 struct intel_crtc *intel_crtc;
9687 struct intel_encoder *intel_encoder =
9688 intel_attached_encoder(connector);
9689 struct drm_crtc *possible_crtc;
9690 struct drm_encoder *encoder = &intel_encoder->base;
9691 struct drm_crtc *crtc = NULL;
9692 struct drm_device *dev = encoder->dev;
9693 struct drm_i915_private *dev_priv = to_i915(dev);
9694 struct drm_framebuffer *fb;
9695 struct drm_mode_config *config = &dev->mode_config;
9696 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9697 struct drm_connector_state *connector_state;
9698 struct intel_crtc_state *crtc_state;
9699 int ret, i = -1;
9700
9701 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9702 connector->base.id, connector->name,
9703 encoder->base.id, encoder->name);
9704
9705 old->restore_state = NULL;
9706
9707 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9708
9709 /*
9710 * Algorithm gets a little messy:
9711 *
9712 * - if the connector already has an assigned crtc, use it (but make
9713 * sure it's on first)
9714 *
9715 * - try to find the first unused crtc that can drive this connector,
9716 * and use that if we find one
9717 */
9718
9719 /* See if we already have a CRTC for this connector */
9720 if (connector->state->crtc) {
9721 crtc = connector->state->crtc;
9722
9723 ret = drm_modeset_lock(&crtc->mutex, ctx);
9724 if (ret)
9725 goto fail;
9726
9727 /* Make sure the crtc and connector are running */
9728 goto found;
9729 }
9730
9731 /* Find an unused one (if possible) */
9732 for_each_crtc(dev, possible_crtc) {
9733 i++;
9734 if (!(encoder->possible_crtcs & (1 << i)))
9735 continue;
9736
9737 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9738 if (ret)
9739 goto fail;
9740
9741 if (possible_crtc->state->enable) {
9742 drm_modeset_unlock(&possible_crtc->mutex);
9743 continue;
9744 }
9745
9746 crtc = possible_crtc;
9747 break;
9748 }
9749
9750 /*
9751 * If we didn't find an unused CRTC, don't use any.
9752 */
9753 if (!crtc) {
9754 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9755 ret = -ENODEV;
9756 goto fail;
9757 }
9758
9759 found:
9760 intel_crtc = to_intel_crtc(crtc);
9761
9762 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9763 if (ret)
9764 goto fail;
9765
9766 state = drm_atomic_state_alloc(dev);
9767 restore_state = drm_atomic_state_alloc(dev);
9768 if (!state || !restore_state) {
9769 ret = -ENOMEM;
9770 goto fail;
9771 }
9772
9773 state->acquire_ctx = ctx;
9774 restore_state->acquire_ctx = ctx;
9775
9776 connector_state = drm_atomic_get_connector_state(state, connector);
9777 if (IS_ERR(connector_state)) {
9778 ret = PTR_ERR(connector_state);
9779 goto fail;
9780 }
9781
9782 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9783 if (ret)
9784 goto fail;
9785
9786 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9787 if (IS_ERR(crtc_state)) {
9788 ret = PTR_ERR(crtc_state);
9789 goto fail;
9790 }
9791
9792 crtc_state->base.active = crtc_state->base.enable = true;
9793
9794 if (!mode)
9795 mode = &load_detect_mode;
9796
9797 /* We need a framebuffer large enough to accommodate all accesses
9798 * that the plane may generate whilst we perform load detection.
9799 * We can not rely on the fbcon either being present (we get called
9800 * during its initialisation to detect all boot displays, or it may
9801 * not even exist) or that it is large enough to satisfy the
9802 * requested mode.
9803 */
9804 fb = mode_fits_in_fbdev(dev, mode);
9805 if (fb == NULL) {
9806 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9807 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9808 } else
9809 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9810 if (IS_ERR(fb)) {
9811 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9812 ret = PTR_ERR(fb);
9813 goto fail;
9814 }
9815
9816 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9817 if (ret)
9818 goto fail;
9819
9820 drm_framebuffer_unreference(fb);
9821
9822 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9823 if (ret)
9824 goto fail;
9825
9826 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9827 if (!ret)
9828 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9829 if (!ret)
9830 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9831 if (ret) {
9832 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9833 goto fail;
9834 }
9835
9836 ret = drm_atomic_commit(state);
9837 if (ret) {
9838 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9839 goto fail;
9840 }
9841
9842 old->restore_state = restore_state;
9843 drm_atomic_state_put(state);
9844
9845 /* let the connector get through one full cycle before testing */
9846 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9847 return true;
9848
9849 fail:
9850 if (state) {
9851 drm_atomic_state_put(state);
9852 state = NULL;
9853 }
9854 if (restore_state) {
9855 drm_atomic_state_put(restore_state);
9856 restore_state = NULL;
9857 }
9858
9859 if (ret == -EDEADLK)
9860 return ret;
9861
9862 return false;
9863 }
9864
9865 void intel_release_load_detect_pipe(struct drm_connector *connector,
9866 struct intel_load_detect_pipe *old,
9867 struct drm_modeset_acquire_ctx *ctx)
9868 {
9869 struct intel_encoder *intel_encoder =
9870 intel_attached_encoder(connector);
9871 struct drm_encoder *encoder = &intel_encoder->base;
9872 struct drm_atomic_state *state = old->restore_state;
9873 int ret;
9874
9875 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9876 connector->base.id, connector->name,
9877 encoder->base.id, encoder->name);
9878
9879 if (!state)
9880 return;
9881
9882 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9883 if (ret)
9884 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9885 drm_atomic_state_put(state);
9886 }
9887
9888 static int i9xx_pll_refclk(struct drm_device *dev,
9889 const struct intel_crtc_state *pipe_config)
9890 {
9891 struct drm_i915_private *dev_priv = to_i915(dev);
9892 u32 dpll = pipe_config->dpll_hw_state.dpll;
9893
9894 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9895 return dev_priv->vbt.lvds_ssc_freq;
9896 else if (HAS_PCH_SPLIT(dev_priv))
9897 return 120000;
9898 else if (!IS_GEN2(dev_priv))
9899 return 96000;
9900 else
9901 return 48000;
9902 }
9903
9904 /* Returns the clock of the currently programmed mode of the given pipe. */
9905 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9906 struct intel_crtc_state *pipe_config)
9907 {
9908 struct drm_device *dev = crtc->base.dev;
9909 struct drm_i915_private *dev_priv = to_i915(dev);
9910 int pipe = pipe_config->cpu_transcoder;
9911 u32 dpll = pipe_config->dpll_hw_state.dpll;
9912 u32 fp;
9913 struct dpll clock;
9914 int port_clock;
9915 int refclk = i9xx_pll_refclk(dev, pipe_config);
9916
9917 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9918 fp = pipe_config->dpll_hw_state.fp0;
9919 else
9920 fp = pipe_config->dpll_hw_state.fp1;
9921
9922 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9923 if (IS_PINEVIEW(dev_priv)) {
9924 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9925 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9926 } else {
9927 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9928 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9929 }
9930
9931 if (!IS_GEN2(dev_priv)) {
9932 if (IS_PINEVIEW(dev_priv))
9933 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9934 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9935 else
9936 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9937 DPLL_FPA01_P1_POST_DIV_SHIFT);
9938
9939 switch (dpll & DPLL_MODE_MASK) {
9940 case DPLLB_MODE_DAC_SERIAL:
9941 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9942 5 : 10;
9943 break;
9944 case DPLLB_MODE_LVDS:
9945 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9946 7 : 14;
9947 break;
9948 default:
9949 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9950 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9951 return;
9952 }
9953
9954 if (IS_PINEVIEW(dev_priv))
9955 port_clock = pnv_calc_dpll_params(refclk, &clock);
9956 else
9957 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9958 } else {
9959 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9960 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9961
9962 if (is_lvds) {
9963 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9964 DPLL_FPA01_P1_POST_DIV_SHIFT);
9965
9966 if (lvds & LVDS_CLKB_POWER_UP)
9967 clock.p2 = 7;
9968 else
9969 clock.p2 = 14;
9970 } else {
9971 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9972 clock.p1 = 2;
9973 else {
9974 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9975 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9976 }
9977 if (dpll & PLL_P2_DIVIDE_BY_4)
9978 clock.p2 = 4;
9979 else
9980 clock.p2 = 2;
9981 }
9982
9983 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9984 }
9985
9986 /*
9987 * This value includes pixel_multiplier. We will use
9988 * port_clock to compute adjusted_mode.crtc_clock in the
9989 * encoder's get_config() function.
9990 */
9991 pipe_config->port_clock = port_clock;
9992 }
9993
9994 int intel_dotclock_calculate(int link_freq,
9995 const struct intel_link_m_n *m_n)
9996 {
9997 /*
9998 * The calculation for the data clock is:
9999 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10000 * But we want to avoid losing precison if possible, so:
10001 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10002 *
10003 * and the link clock is simpler:
10004 * link_clock = (m * link_clock) / n
10005 */
10006
10007 if (!m_n->link_n)
10008 return 0;
10009
10010 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10011 }
10012
10013 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10014 struct intel_crtc_state *pipe_config)
10015 {
10016 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10017
10018 /* read out port_clock from the DPLL */
10019 i9xx_crtc_clock_get(crtc, pipe_config);
10020
10021 /*
10022 * In case there is an active pipe without active ports,
10023 * we may need some idea for the dotclock anyway.
10024 * Calculate one based on the FDI configuration.
10025 */
10026 pipe_config->base.adjusted_mode.crtc_clock =
10027 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10028 &pipe_config->fdi_m_n);
10029 }
10030
10031 /** Returns the currently programmed mode of the given pipe. */
10032 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10033 struct drm_crtc *crtc)
10034 {
10035 struct drm_i915_private *dev_priv = to_i915(dev);
10036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10037 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10038 struct drm_display_mode *mode;
10039 struct intel_crtc_state *pipe_config;
10040 int htot = I915_READ(HTOTAL(cpu_transcoder));
10041 int hsync = I915_READ(HSYNC(cpu_transcoder));
10042 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10043 int vsync = I915_READ(VSYNC(cpu_transcoder));
10044 enum pipe pipe = intel_crtc->pipe;
10045
10046 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10047 if (!mode)
10048 return NULL;
10049
10050 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10051 if (!pipe_config) {
10052 kfree(mode);
10053 return NULL;
10054 }
10055
10056 /*
10057 * Construct a pipe_config sufficient for getting the clock info
10058 * back out of crtc_clock_get.
10059 *
10060 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10061 * to use a real value here instead.
10062 */
10063 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10064 pipe_config->pixel_multiplier = 1;
10065 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10066 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10067 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10068 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10069
10070 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10071 mode->hdisplay = (htot & 0xffff) + 1;
10072 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10073 mode->hsync_start = (hsync & 0xffff) + 1;
10074 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10075 mode->vdisplay = (vtot & 0xffff) + 1;
10076 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10077 mode->vsync_start = (vsync & 0xffff) + 1;
10078 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10079
10080 drm_mode_set_name(mode);
10081
10082 kfree(pipe_config);
10083
10084 return mode;
10085 }
10086
10087 static void intel_crtc_destroy(struct drm_crtc *crtc)
10088 {
10089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10090 struct drm_device *dev = crtc->dev;
10091 struct intel_flip_work *work;
10092
10093 spin_lock_irq(&dev->event_lock);
10094 work = intel_crtc->flip_work;
10095 intel_crtc->flip_work = NULL;
10096 spin_unlock_irq(&dev->event_lock);
10097
10098 if (work) {
10099 cancel_work_sync(&work->mmio_work);
10100 cancel_work_sync(&work->unpin_work);
10101 kfree(work);
10102 }
10103
10104 drm_crtc_cleanup(crtc);
10105
10106 kfree(intel_crtc);
10107 }
10108
10109 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10110 struct intel_flip_work *work)
10111 {
10112 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10113
10114 /* Ensure that the work item is consistent when activating it ... */
10115 smp_mb__before_atomic();
10116 atomic_set(&work->pending, 1);
10117 }
10118
10119 /**
10120 * intel_wm_need_update - Check whether watermarks need updating
10121 * @plane: drm plane
10122 * @state: new plane state
10123 *
10124 * Check current plane state versus the new one to determine whether
10125 * watermarks need to be recalculated.
10126 *
10127 * Returns true or false.
10128 */
10129 static bool intel_wm_need_update(struct drm_plane *plane,
10130 struct drm_plane_state *state)
10131 {
10132 struct intel_plane_state *new = to_intel_plane_state(state);
10133 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10134
10135 /* Update watermarks on tiling or size changes. */
10136 if (new->base.visible != cur->base.visible)
10137 return true;
10138
10139 if (!cur->base.fb || !new->base.fb)
10140 return false;
10141
10142 if (cur->base.fb->modifier != new->base.fb->modifier ||
10143 cur->base.rotation != new->base.rotation ||
10144 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10145 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10146 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10147 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10148 return true;
10149
10150 return false;
10151 }
10152
10153 static bool needs_scaling(struct intel_plane_state *state)
10154 {
10155 int src_w = drm_rect_width(&state->base.src) >> 16;
10156 int src_h = drm_rect_height(&state->base.src) >> 16;
10157 int dst_w = drm_rect_width(&state->base.dst);
10158 int dst_h = drm_rect_height(&state->base.dst);
10159
10160 return (src_w != dst_w || src_h != dst_h);
10161 }
10162
10163 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10164 struct drm_plane_state *plane_state)
10165 {
10166 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10167 struct drm_crtc *crtc = crtc_state->crtc;
10168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10169 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10170 struct drm_device *dev = crtc->dev;
10171 struct drm_i915_private *dev_priv = to_i915(dev);
10172 struct intel_plane_state *old_plane_state =
10173 to_intel_plane_state(plane->base.state);
10174 bool mode_changed = needs_modeset(crtc_state);
10175 bool was_crtc_enabled = crtc->state->active;
10176 bool is_crtc_enabled = crtc_state->active;
10177 bool turn_off, turn_on, visible, was_visible;
10178 struct drm_framebuffer *fb = plane_state->fb;
10179 int ret;
10180
10181 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10182 ret = skl_update_scaler_plane(
10183 to_intel_crtc_state(crtc_state),
10184 to_intel_plane_state(plane_state));
10185 if (ret)
10186 return ret;
10187 }
10188
10189 was_visible = old_plane_state->base.visible;
10190 visible = plane_state->visible;
10191
10192 if (!was_crtc_enabled && WARN_ON(was_visible))
10193 was_visible = false;
10194
10195 /*
10196 * Visibility is calculated as if the crtc was on, but
10197 * after scaler setup everything depends on it being off
10198 * when the crtc isn't active.
10199 *
10200 * FIXME this is wrong for watermarks. Watermarks should also
10201 * be computed as if the pipe would be active. Perhaps move
10202 * per-plane wm computation to the .check_plane() hook, and
10203 * only combine the results from all planes in the current place?
10204 */
10205 if (!is_crtc_enabled) {
10206 plane_state->visible = visible = false;
10207 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10208 }
10209
10210 if (!was_visible && !visible)
10211 return 0;
10212
10213 if (fb != old_plane_state->base.fb)
10214 pipe_config->fb_changed = true;
10215
10216 turn_off = was_visible && (!visible || mode_changed);
10217 turn_on = visible && (!was_visible || mode_changed);
10218
10219 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10220 intel_crtc->base.base.id, intel_crtc->base.name,
10221 plane->base.base.id, plane->base.name,
10222 fb ? fb->base.id : -1);
10223
10224 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10225 plane->base.base.id, plane->base.name,
10226 was_visible, visible,
10227 turn_off, turn_on, mode_changed);
10228
10229 if (turn_on) {
10230 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10231 pipe_config->update_wm_pre = true;
10232
10233 /* must disable cxsr around plane enable/disable */
10234 if (plane->id != PLANE_CURSOR)
10235 pipe_config->disable_cxsr = true;
10236 } else if (turn_off) {
10237 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10238 pipe_config->update_wm_post = true;
10239
10240 /* must disable cxsr around plane enable/disable */
10241 if (plane->id != PLANE_CURSOR)
10242 pipe_config->disable_cxsr = true;
10243 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10244 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10245 /* FIXME bollocks */
10246 pipe_config->update_wm_pre = true;
10247 pipe_config->update_wm_post = true;
10248 }
10249 }
10250
10251 if (visible || was_visible)
10252 pipe_config->fb_bits |= plane->frontbuffer_bit;
10253
10254 /*
10255 * WaCxSRDisabledForSpriteScaling:ivb
10256 *
10257 * cstate->update_wm was already set above, so this flag will
10258 * take effect when we commit and program watermarks.
10259 */
10260 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10261 needs_scaling(to_intel_plane_state(plane_state)) &&
10262 !needs_scaling(old_plane_state))
10263 pipe_config->disable_lp_wm = true;
10264
10265 return 0;
10266 }
10267
10268 static bool encoders_cloneable(const struct intel_encoder *a,
10269 const struct intel_encoder *b)
10270 {
10271 /* masks could be asymmetric, so check both ways */
10272 return a == b || (a->cloneable & (1 << b->type) &&
10273 b->cloneable & (1 << a->type));
10274 }
10275
10276 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10277 struct intel_crtc *crtc,
10278 struct intel_encoder *encoder)
10279 {
10280 struct intel_encoder *source_encoder;
10281 struct drm_connector *connector;
10282 struct drm_connector_state *connector_state;
10283 int i;
10284
10285 for_each_new_connector_in_state(state, connector, connector_state, i) {
10286 if (connector_state->crtc != &crtc->base)
10287 continue;
10288
10289 source_encoder =
10290 to_intel_encoder(connector_state->best_encoder);
10291 if (!encoders_cloneable(encoder, source_encoder))
10292 return false;
10293 }
10294
10295 return true;
10296 }
10297
10298 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10299 struct drm_crtc_state *crtc_state)
10300 {
10301 struct drm_device *dev = crtc->dev;
10302 struct drm_i915_private *dev_priv = to_i915(dev);
10303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10304 struct intel_crtc_state *pipe_config =
10305 to_intel_crtc_state(crtc_state);
10306 struct drm_atomic_state *state = crtc_state->state;
10307 int ret;
10308 bool mode_changed = needs_modeset(crtc_state);
10309
10310 if (mode_changed && !crtc_state->active)
10311 pipe_config->update_wm_post = true;
10312
10313 if (mode_changed && crtc_state->enable &&
10314 dev_priv->display.crtc_compute_clock &&
10315 !WARN_ON(pipe_config->shared_dpll)) {
10316 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10317 pipe_config);
10318 if (ret)
10319 return ret;
10320 }
10321
10322 if (crtc_state->color_mgmt_changed) {
10323 ret = intel_color_check(crtc, crtc_state);
10324 if (ret)
10325 return ret;
10326
10327 /*
10328 * Changing color management on Intel hardware is
10329 * handled as part of planes update.
10330 */
10331 crtc_state->planes_changed = true;
10332 }
10333
10334 ret = 0;
10335 if (dev_priv->display.compute_pipe_wm) {
10336 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10337 if (ret) {
10338 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10339 return ret;
10340 }
10341 }
10342
10343 if (dev_priv->display.compute_intermediate_wm &&
10344 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10345 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10346 return 0;
10347
10348 /*
10349 * Calculate 'intermediate' watermarks that satisfy both the
10350 * old state and the new state. We can program these
10351 * immediately.
10352 */
10353 ret = dev_priv->display.compute_intermediate_wm(dev,
10354 intel_crtc,
10355 pipe_config);
10356 if (ret) {
10357 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10358 return ret;
10359 }
10360 } else if (dev_priv->display.compute_intermediate_wm) {
10361 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10362 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10363 }
10364
10365 if (INTEL_GEN(dev_priv) >= 9) {
10366 if (mode_changed)
10367 ret = skl_update_scaler_crtc(pipe_config);
10368
10369 if (!ret)
10370 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10371 pipe_config);
10372 if (!ret)
10373 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10374 pipe_config);
10375 }
10376
10377 return ret;
10378 }
10379
10380 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10381 .atomic_begin = intel_begin_crtc_commit,
10382 .atomic_flush = intel_finish_crtc_commit,
10383 .atomic_check = intel_crtc_atomic_check,
10384 };
10385
10386 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10387 {
10388 struct intel_connector *connector;
10389 struct drm_connector_list_iter conn_iter;
10390
10391 drm_connector_list_iter_begin(dev, &conn_iter);
10392 for_each_intel_connector_iter(connector, &conn_iter) {
10393 if (connector->base.state->crtc)
10394 drm_connector_unreference(&connector->base);
10395
10396 if (connector->base.encoder) {
10397 connector->base.state->best_encoder =
10398 connector->base.encoder;
10399 connector->base.state->crtc =
10400 connector->base.encoder->crtc;
10401
10402 drm_connector_reference(&connector->base);
10403 } else {
10404 connector->base.state->best_encoder = NULL;
10405 connector->base.state->crtc = NULL;
10406 }
10407 }
10408 drm_connector_list_iter_end(&conn_iter);
10409 }
10410
10411 static void
10412 connected_sink_compute_bpp(struct intel_connector *connector,
10413 struct intel_crtc_state *pipe_config)
10414 {
10415 const struct drm_display_info *info = &connector->base.display_info;
10416 int bpp = pipe_config->pipe_bpp;
10417
10418 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10419 connector->base.base.id,
10420 connector->base.name);
10421
10422 /* Don't use an invalid EDID bpc value */
10423 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10424 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10425 bpp, info->bpc * 3);
10426 pipe_config->pipe_bpp = info->bpc * 3;
10427 }
10428
10429 /* Clamp bpp to 8 on screens without EDID 1.4 */
10430 if (info->bpc == 0 && bpp > 24) {
10431 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10432 bpp);
10433 pipe_config->pipe_bpp = 24;
10434 }
10435 }
10436
10437 static int
10438 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10439 struct intel_crtc_state *pipe_config)
10440 {
10441 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10442 struct drm_atomic_state *state;
10443 struct drm_connector *connector;
10444 struct drm_connector_state *connector_state;
10445 int bpp, i;
10446
10447 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10448 IS_CHERRYVIEW(dev_priv)))
10449 bpp = 10*3;
10450 else if (INTEL_GEN(dev_priv) >= 5)
10451 bpp = 12*3;
10452 else
10453 bpp = 8*3;
10454
10455
10456 pipe_config->pipe_bpp = bpp;
10457
10458 state = pipe_config->base.state;
10459
10460 /* Clamp display bpp to EDID value */
10461 for_each_new_connector_in_state(state, connector, connector_state, i) {
10462 if (connector_state->crtc != &crtc->base)
10463 continue;
10464
10465 connected_sink_compute_bpp(to_intel_connector(connector),
10466 pipe_config);
10467 }
10468
10469 return bpp;
10470 }
10471
10472 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10473 {
10474 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10475 "type: 0x%x flags: 0x%x\n",
10476 mode->crtc_clock,
10477 mode->crtc_hdisplay, mode->crtc_hsync_start,
10478 mode->crtc_hsync_end, mode->crtc_htotal,
10479 mode->crtc_vdisplay, mode->crtc_vsync_start,
10480 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10481 }
10482
10483 static inline void
10484 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10485 unsigned int lane_count, struct intel_link_m_n *m_n)
10486 {
10487 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10488 id, lane_count,
10489 m_n->gmch_m, m_n->gmch_n,
10490 m_n->link_m, m_n->link_n, m_n->tu);
10491 }
10492
10493 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10494 struct intel_crtc_state *pipe_config,
10495 const char *context)
10496 {
10497 struct drm_device *dev = crtc->base.dev;
10498 struct drm_i915_private *dev_priv = to_i915(dev);
10499 struct drm_plane *plane;
10500 struct intel_plane *intel_plane;
10501 struct intel_plane_state *state;
10502 struct drm_framebuffer *fb;
10503
10504 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10505 crtc->base.base.id, crtc->base.name, context);
10506
10507 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10508 transcoder_name(pipe_config->cpu_transcoder),
10509 pipe_config->pipe_bpp, pipe_config->dither);
10510
10511 if (pipe_config->has_pch_encoder)
10512 intel_dump_m_n_config(pipe_config, "fdi",
10513 pipe_config->fdi_lanes,
10514 &pipe_config->fdi_m_n);
10515
10516 if (intel_crtc_has_dp_encoder(pipe_config)) {
10517 intel_dump_m_n_config(pipe_config, "dp m_n",
10518 pipe_config->lane_count, &pipe_config->dp_m_n);
10519 if (pipe_config->has_drrs)
10520 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10521 pipe_config->lane_count,
10522 &pipe_config->dp_m2_n2);
10523 }
10524
10525 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10526 pipe_config->has_audio, pipe_config->has_infoframe);
10527
10528 DRM_DEBUG_KMS("requested mode:\n");
10529 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10530 DRM_DEBUG_KMS("adjusted mode:\n");
10531 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10532 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10533 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10534 pipe_config->port_clock,
10535 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10536 pipe_config->pixel_rate);
10537
10538 if (INTEL_GEN(dev_priv) >= 9)
10539 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10540 crtc->num_scalers,
10541 pipe_config->scaler_state.scaler_users,
10542 pipe_config->scaler_state.scaler_id);
10543
10544 if (HAS_GMCH_DISPLAY(dev_priv))
10545 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10546 pipe_config->gmch_pfit.control,
10547 pipe_config->gmch_pfit.pgm_ratios,
10548 pipe_config->gmch_pfit.lvds_border_bits);
10549 else
10550 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10551 pipe_config->pch_pfit.pos,
10552 pipe_config->pch_pfit.size,
10553 enableddisabled(pipe_config->pch_pfit.enabled));
10554
10555 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10556 pipe_config->ips_enabled, pipe_config->double_wide);
10557
10558 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10559
10560 DRM_DEBUG_KMS("planes on this crtc\n");
10561 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10562 struct drm_format_name_buf format_name;
10563 intel_plane = to_intel_plane(plane);
10564 if (intel_plane->pipe != crtc->pipe)
10565 continue;
10566
10567 state = to_intel_plane_state(plane->state);
10568 fb = state->base.fb;
10569 if (!fb) {
10570 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10571 plane->base.id, plane->name, state->scaler_id);
10572 continue;
10573 }
10574
10575 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10576 plane->base.id, plane->name,
10577 fb->base.id, fb->width, fb->height,
10578 drm_get_format_name(fb->format->format, &format_name));
10579 if (INTEL_GEN(dev_priv) >= 9)
10580 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10581 state->scaler_id,
10582 state->base.src.x1 >> 16,
10583 state->base.src.y1 >> 16,
10584 drm_rect_width(&state->base.src) >> 16,
10585 drm_rect_height(&state->base.src) >> 16,
10586 state->base.dst.x1, state->base.dst.y1,
10587 drm_rect_width(&state->base.dst),
10588 drm_rect_height(&state->base.dst));
10589 }
10590 }
10591
10592 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10593 {
10594 struct drm_device *dev = state->dev;
10595 struct drm_connector *connector;
10596 struct drm_connector_list_iter conn_iter;
10597 unsigned int used_ports = 0;
10598 unsigned int used_mst_ports = 0;
10599
10600 /*
10601 * Walk the connector list instead of the encoder
10602 * list to detect the problem on ddi platforms
10603 * where there's just one encoder per digital port.
10604 */
10605 drm_connector_list_iter_begin(dev, &conn_iter);
10606 drm_for_each_connector_iter(connector, &conn_iter) {
10607 struct drm_connector_state *connector_state;
10608 struct intel_encoder *encoder;
10609
10610 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10611 if (!connector_state)
10612 connector_state = connector->state;
10613
10614 if (!connector_state->best_encoder)
10615 continue;
10616
10617 encoder = to_intel_encoder(connector_state->best_encoder);
10618
10619 WARN_ON(!connector_state->crtc);
10620
10621 switch (encoder->type) {
10622 unsigned int port_mask;
10623 case INTEL_OUTPUT_UNKNOWN:
10624 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10625 break;
10626 case INTEL_OUTPUT_DP:
10627 case INTEL_OUTPUT_HDMI:
10628 case INTEL_OUTPUT_EDP:
10629 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10630
10631 /* the same port mustn't appear more than once */
10632 if (used_ports & port_mask)
10633 return false;
10634
10635 used_ports |= port_mask;
10636 break;
10637 case INTEL_OUTPUT_DP_MST:
10638 used_mst_ports |=
10639 1 << enc_to_mst(&encoder->base)->primary->port;
10640 break;
10641 default:
10642 break;
10643 }
10644 }
10645 drm_connector_list_iter_end(&conn_iter);
10646
10647 /* can't mix MST and SST/HDMI on the same port */
10648 if (used_ports & used_mst_ports)
10649 return false;
10650
10651 return true;
10652 }
10653
10654 static void
10655 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10656 {
10657 struct drm_i915_private *dev_priv =
10658 to_i915(crtc_state->base.crtc->dev);
10659 struct intel_crtc_scaler_state scaler_state;
10660 struct intel_dpll_hw_state dpll_hw_state;
10661 struct intel_shared_dpll *shared_dpll;
10662 struct intel_crtc_wm_state wm_state;
10663 bool force_thru;
10664
10665 /* FIXME: before the switch to atomic started, a new pipe_config was
10666 * kzalloc'd. Code that depends on any field being zero should be
10667 * fixed, so that the crtc_state can be safely duplicated. For now,
10668 * only fields that are know to not cause problems are preserved. */
10669
10670 scaler_state = crtc_state->scaler_state;
10671 shared_dpll = crtc_state->shared_dpll;
10672 dpll_hw_state = crtc_state->dpll_hw_state;
10673 force_thru = crtc_state->pch_pfit.force_thru;
10674 if (IS_G4X(dev_priv) ||
10675 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10676 wm_state = crtc_state->wm;
10677
10678 /* Keep base drm_crtc_state intact, only clear our extended struct */
10679 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10680 memset(&crtc_state->base + 1, 0,
10681 sizeof(*crtc_state) - sizeof(crtc_state->base));
10682
10683 crtc_state->scaler_state = scaler_state;
10684 crtc_state->shared_dpll = shared_dpll;
10685 crtc_state->dpll_hw_state = dpll_hw_state;
10686 crtc_state->pch_pfit.force_thru = force_thru;
10687 if (IS_G4X(dev_priv) ||
10688 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10689 crtc_state->wm = wm_state;
10690 }
10691
10692 static int
10693 intel_modeset_pipe_config(struct drm_crtc *crtc,
10694 struct intel_crtc_state *pipe_config)
10695 {
10696 struct drm_atomic_state *state = pipe_config->base.state;
10697 struct intel_encoder *encoder;
10698 struct drm_connector *connector;
10699 struct drm_connector_state *connector_state;
10700 int base_bpp, ret = -EINVAL;
10701 int i;
10702 bool retry = true;
10703
10704 clear_intel_crtc_state(pipe_config);
10705
10706 pipe_config->cpu_transcoder =
10707 (enum transcoder) to_intel_crtc(crtc)->pipe;
10708
10709 /*
10710 * Sanitize sync polarity flags based on requested ones. If neither
10711 * positive or negative polarity is requested, treat this as meaning
10712 * negative polarity.
10713 */
10714 if (!(pipe_config->base.adjusted_mode.flags &
10715 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10716 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10717
10718 if (!(pipe_config->base.adjusted_mode.flags &
10719 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10720 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10721
10722 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10723 pipe_config);
10724 if (base_bpp < 0)
10725 goto fail;
10726
10727 /*
10728 * Determine the real pipe dimensions. Note that stereo modes can
10729 * increase the actual pipe size due to the frame doubling and
10730 * insertion of additional space for blanks between the frame. This
10731 * is stored in the crtc timings. We use the requested mode to do this
10732 * computation to clearly distinguish it from the adjusted mode, which
10733 * can be changed by the connectors in the below retry loop.
10734 */
10735 drm_mode_get_hv_timing(&pipe_config->base.mode,
10736 &pipe_config->pipe_src_w,
10737 &pipe_config->pipe_src_h);
10738
10739 for_each_new_connector_in_state(state, connector, connector_state, i) {
10740 if (connector_state->crtc != crtc)
10741 continue;
10742
10743 encoder = to_intel_encoder(connector_state->best_encoder);
10744
10745 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10746 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10747 goto fail;
10748 }
10749
10750 /*
10751 * Determine output_types before calling the .compute_config()
10752 * hooks so that the hooks can use this information safely.
10753 */
10754 pipe_config->output_types |= 1 << encoder->type;
10755 }
10756
10757 encoder_retry:
10758 /* Ensure the port clock defaults are reset when retrying. */
10759 pipe_config->port_clock = 0;
10760 pipe_config->pixel_multiplier = 1;
10761
10762 /* Fill in default crtc timings, allow encoders to overwrite them. */
10763 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10764 CRTC_STEREO_DOUBLE);
10765
10766 /* Pass our mode to the connectors and the CRTC to give them a chance to
10767 * adjust it according to limitations or connector properties, and also
10768 * a chance to reject the mode entirely.
10769 */
10770 for_each_new_connector_in_state(state, connector, connector_state, i) {
10771 if (connector_state->crtc != crtc)
10772 continue;
10773
10774 encoder = to_intel_encoder(connector_state->best_encoder);
10775
10776 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10777 DRM_DEBUG_KMS("Encoder config failure\n");
10778 goto fail;
10779 }
10780 }
10781
10782 /* Set default port clock if not overwritten by the encoder. Needs to be
10783 * done afterwards in case the encoder adjusts the mode. */
10784 if (!pipe_config->port_clock)
10785 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10786 * pipe_config->pixel_multiplier;
10787
10788 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10789 if (ret < 0) {
10790 DRM_DEBUG_KMS("CRTC fixup failed\n");
10791 goto fail;
10792 }
10793
10794 if (ret == RETRY) {
10795 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10796 ret = -EINVAL;
10797 goto fail;
10798 }
10799
10800 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10801 retry = false;
10802 goto encoder_retry;
10803 }
10804
10805 /* Dithering seems to not pass-through bits correctly when it should, so
10806 * only enable it on 6bpc panels and when its not a compliance
10807 * test requesting 6bpc video pattern.
10808 */
10809 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10810 !pipe_config->dither_force_disable;
10811 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10812 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10813
10814 fail:
10815 return ret;
10816 }
10817
10818 static void
10819 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10820 {
10821 struct drm_crtc *crtc;
10822 struct drm_crtc_state *new_crtc_state;
10823 int i;
10824
10825 /* Double check state. */
10826 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10827 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10828
10829 /*
10830 * Update legacy state to satisfy fbc code. This can
10831 * be removed when fbc uses the atomic state.
10832 */
10833 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10834 struct drm_plane_state *plane_state = crtc->primary->state;
10835
10836 crtc->primary->fb = plane_state->fb;
10837 crtc->x = plane_state->src_x >> 16;
10838 crtc->y = plane_state->src_y >> 16;
10839 }
10840 }
10841 }
10842
10843 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10844 {
10845 int diff;
10846
10847 if (clock1 == clock2)
10848 return true;
10849
10850 if (!clock1 || !clock2)
10851 return false;
10852
10853 diff = abs(clock1 - clock2);
10854
10855 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10856 return true;
10857
10858 return false;
10859 }
10860
10861 static bool
10862 intel_compare_m_n(unsigned int m, unsigned int n,
10863 unsigned int m2, unsigned int n2,
10864 bool exact)
10865 {
10866 if (m == m2 && n == n2)
10867 return true;
10868
10869 if (exact || !m || !n || !m2 || !n2)
10870 return false;
10871
10872 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
10873
10874 if (n > n2) {
10875 while (n > n2) {
10876 m2 <<= 1;
10877 n2 <<= 1;
10878 }
10879 } else if (n < n2) {
10880 while (n < n2) {
10881 m <<= 1;
10882 n <<= 1;
10883 }
10884 }
10885
10886 if (n != n2)
10887 return false;
10888
10889 return intel_fuzzy_clock_check(m, m2);
10890 }
10891
10892 static bool
10893 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
10894 struct intel_link_m_n *m2_n2,
10895 bool adjust)
10896 {
10897 if (m_n->tu == m2_n2->tu &&
10898 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
10899 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
10900 intel_compare_m_n(m_n->link_m, m_n->link_n,
10901 m2_n2->link_m, m2_n2->link_n, !adjust)) {
10902 if (adjust)
10903 *m2_n2 = *m_n;
10904
10905 return true;
10906 }
10907
10908 return false;
10909 }
10910
10911 static void __printf(3, 4)
10912 pipe_config_err(bool adjust, const char *name, const char *format, ...)
10913 {
10914 char *level;
10915 unsigned int category;
10916 struct va_format vaf;
10917 va_list args;
10918
10919 if (adjust) {
10920 level = KERN_DEBUG;
10921 category = DRM_UT_KMS;
10922 } else {
10923 level = KERN_ERR;
10924 category = DRM_UT_NONE;
10925 }
10926
10927 va_start(args, format);
10928 vaf.fmt = format;
10929 vaf.va = &args;
10930
10931 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
10932
10933 va_end(args);
10934 }
10935
10936 static bool
10937 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
10938 struct intel_crtc_state *current_config,
10939 struct intel_crtc_state *pipe_config,
10940 bool adjust)
10941 {
10942 bool ret = true;
10943
10944 #define PIPE_CONF_CHECK_X(name) \
10945 if (current_config->name != pipe_config->name) { \
10946 pipe_config_err(adjust, __stringify(name), \
10947 "(expected 0x%08x, found 0x%08x)\n", \
10948 current_config->name, \
10949 pipe_config->name); \
10950 ret = false; \
10951 }
10952
10953 #define PIPE_CONF_CHECK_I(name) \
10954 if (current_config->name != pipe_config->name) { \
10955 pipe_config_err(adjust, __stringify(name), \
10956 "(expected %i, found %i)\n", \
10957 current_config->name, \
10958 pipe_config->name); \
10959 ret = false; \
10960 }
10961
10962 #define PIPE_CONF_CHECK_P(name) \
10963 if (current_config->name != pipe_config->name) { \
10964 pipe_config_err(adjust, __stringify(name), \
10965 "(expected %p, found %p)\n", \
10966 current_config->name, \
10967 pipe_config->name); \
10968 ret = false; \
10969 }
10970
10971 #define PIPE_CONF_CHECK_M_N(name) \
10972 if (!intel_compare_link_m_n(&current_config->name, \
10973 &pipe_config->name,\
10974 adjust)) { \
10975 pipe_config_err(adjust, __stringify(name), \
10976 "(expected tu %i gmch %i/%i link %i/%i, " \
10977 "found tu %i, gmch %i/%i link %i/%i)\n", \
10978 current_config->name.tu, \
10979 current_config->name.gmch_m, \
10980 current_config->name.gmch_n, \
10981 current_config->name.link_m, \
10982 current_config->name.link_n, \
10983 pipe_config->name.tu, \
10984 pipe_config->name.gmch_m, \
10985 pipe_config->name.gmch_n, \
10986 pipe_config->name.link_m, \
10987 pipe_config->name.link_n); \
10988 ret = false; \
10989 }
10990
10991 /* This is required for BDW+ where there is only one set of registers for
10992 * switching between high and low RR.
10993 * This macro can be used whenever a comparison has to be made between one
10994 * hw state and multiple sw state variables.
10995 */
10996 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
10997 if (!intel_compare_link_m_n(&current_config->name, \
10998 &pipe_config->name, adjust) && \
10999 !intel_compare_link_m_n(&current_config->alt_name, \
11000 &pipe_config->name, adjust)) { \
11001 pipe_config_err(adjust, __stringify(name), \
11002 "(expected tu %i gmch %i/%i link %i/%i, " \
11003 "or tu %i gmch %i/%i link %i/%i, " \
11004 "found tu %i, gmch %i/%i link %i/%i)\n", \
11005 current_config->name.tu, \
11006 current_config->name.gmch_m, \
11007 current_config->name.gmch_n, \
11008 current_config->name.link_m, \
11009 current_config->name.link_n, \
11010 current_config->alt_name.tu, \
11011 current_config->alt_name.gmch_m, \
11012 current_config->alt_name.gmch_n, \
11013 current_config->alt_name.link_m, \
11014 current_config->alt_name.link_n, \
11015 pipe_config->name.tu, \
11016 pipe_config->name.gmch_m, \
11017 pipe_config->name.gmch_n, \
11018 pipe_config->name.link_m, \
11019 pipe_config->name.link_n); \
11020 ret = false; \
11021 }
11022
11023 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11024 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11025 pipe_config_err(adjust, __stringify(name), \
11026 "(%x) (expected %i, found %i)\n", \
11027 (mask), \
11028 current_config->name & (mask), \
11029 pipe_config->name & (mask)); \
11030 ret = false; \
11031 }
11032
11033 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11034 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11035 pipe_config_err(adjust, __stringify(name), \
11036 "(expected %i, found %i)\n", \
11037 current_config->name, \
11038 pipe_config->name); \
11039 ret = false; \
11040 }
11041
11042 #define PIPE_CONF_QUIRK(quirk) \
11043 ((current_config->quirks | pipe_config->quirks) & (quirk))
11044
11045 PIPE_CONF_CHECK_I(cpu_transcoder);
11046
11047 PIPE_CONF_CHECK_I(has_pch_encoder);
11048 PIPE_CONF_CHECK_I(fdi_lanes);
11049 PIPE_CONF_CHECK_M_N(fdi_m_n);
11050
11051 PIPE_CONF_CHECK_I(lane_count);
11052 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11053
11054 if (INTEL_GEN(dev_priv) < 8) {
11055 PIPE_CONF_CHECK_M_N(dp_m_n);
11056
11057 if (current_config->has_drrs)
11058 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11059 } else
11060 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11061
11062 PIPE_CONF_CHECK_X(output_types);
11063
11064 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11065 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11066 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11067 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11068 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11069 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11070
11071 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11072 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11073 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11074 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11075 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11076 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11077
11078 PIPE_CONF_CHECK_I(pixel_multiplier);
11079 PIPE_CONF_CHECK_I(has_hdmi_sink);
11080 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11081 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11082 PIPE_CONF_CHECK_I(limited_color_range);
11083
11084 PIPE_CONF_CHECK_I(hdmi_scrambling);
11085 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11086 PIPE_CONF_CHECK_I(has_infoframe);
11087
11088 PIPE_CONF_CHECK_I(has_audio);
11089
11090 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11091 DRM_MODE_FLAG_INTERLACE);
11092
11093 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11094 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11095 DRM_MODE_FLAG_PHSYNC);
11096 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11097 DRM_MODE_FLAG_NHSYNC);
11098 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11099 DRM_MODE_FLAG_PVSYNC);
11100 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11101 DRM_MODE_FLAG_NVSYNC);
11102 }
11103
11104 PIPE_CONF_CHECK_X(gmch_pfit.control);
11105 /* pfit ratios are autocomputed by the hw on gen4+ */
11106 if (INTEL_GEN(dev_priv) < 4)
11107 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11108 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11109
11110 if (!adjust) {
11111 PIPE_CONF_CHECK_I(pipe_src_w);
11112 PIPE_CONF_CHECK_I(pipe_src_h);
11113
11114 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11115 if (current_config->pch_pfit.enabled) {
11116 PIPE_CONF_CHECK_X(pch_pfit.pos);
11117 PIPE_CONF_CHECK_X(pch_pfit.size);
11118 }
11119
11120 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11121 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11122 }
11123
11124 /* BDW+ don't expose a synchronous way to read the state */
11125 if (IS_HASWELL(dev_priv))
11126 PIPE_CONF_CHECK_I(ips_enabled);
11127
11128 PIPE_CONF_CHECK_I(double_wide);
11129
11130 PIPE_CONF_CHECK_P(shared_dpll);
11131 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11132 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11133 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11134 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11135 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11136 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11137 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11138 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11139 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11140
11141 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11142 PIPE_CONF_CHECK_X(dsi_pll.div);
11143
11144 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11145 PIPE_CONF_CHECK_I(pipe_bpp);
11146
11147 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11148 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11149
11150 #undef PIPE_CONF_CHECK_X
11151 #undef PIPE_CONF_CHECK_I
11152 #undef PIPE_CONF_CHECK_P
11153 #undef PIPE_CONF_CHECK_FLAGS
11154 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11155 #undef PIPE_CONF_QUIRK
11156
11157 return ret;
11158 }
11159
11160 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11161 const struct intel_crtc_state *pipe_config)
11162 {
11163 if (pipe_config->has_pch_encoder) {
11164 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11165 &pipe_config->fdi_m_n);
11166 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11167
11168 /*
11169 * FDI already provided one idea for the dotclock.
11170 * Yell if the encoder disagrees.
11171 */
11172 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11173 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11174 fdi_dotclock, dotclock);
11175 }
11176 }
11177
11178 static void verify_wm_state(struct drm_crtc *crtc,
11179 struct drm_crtc_state *new_state)
11180 {
11181 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11182 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11183 struct skl_pipe_wm hw_wm, *sw_wm;
11184 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11185 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11187 const enum pipe pipe = intel_crtc->pipe;
11188 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11189
11190 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11191 return;
11192
11193 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11194 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11195
11196 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11197 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11198
11199 /* planes */
11200 for_each_universal_plane(dev_priv, pipe, plane) {
11201 hw_plane_wm = &hw_wm.planes[plane];
11202 sw_plane_wm = &sw_wm->planes[plane];
11203
11204 /* Watermarks */
11205 for (level = 0; level <= max_level; level++) {
11206 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11207 &sw_plane_wm->wm[level]))
11208 continue;
11209
11210 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11211 pipe_name(pipe), plane + 1, level,
11212 sw_plane_wm->wm[level].plane_en,
11213 sw_plane_wm->wm[level].plane_res_b,
11214 sw_plane_wm->wm[level].plane_res_l,
11215 hw_plane_wm->wm[level].plane_en,
11216 hw_plane_wm->wm[level].plane_res_b,
11217 hw_plane_wm->wm[level].plane_res_l);
11218 }
11219
11220 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11221 &sw_plane_wm->trans_wm)) {
11222 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11223 pipe_name(pipe), plane + 1,
11224 sw_plane_wm->trans_wm.plane_en,
11225 sw_plane_wm->trans_wm.plane_res_b,
11226 sw_plane_wm->trans_wm.plane_res_l,
11227 hw_plane_wm->trans_wm.plane_en,
11228 hw_plane_wm->trans_wm.plane_res_b,
11229 hw_plane_wm->trans_wm.plane_res_l);
11230 }
11231
11232 /* DDB */
11233 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11234 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11235
11236 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11237 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11238 pipe_name(pipe), plane + 1,
11239 sw_ddb_entry->start, sw_ddb_entry->end,
11240 hw_ddb_entry->start, hw_ddb_entry->end);
11241 }
11242 }
11243
11244 /*
11245 * cursor
11246 * If the cursor plane isn't active, we may not have updated it's ddb
11247 * allocation. In that case since the ddb allocation will be updated
11248 * once the plane becomes visible, we can skip this check
11249 */
11250 if (1) {
11251 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11252 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11253
11254 /* Watermarks */
11255 for (level = 0; level <= max_level; level++) {
11256 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11257 &sw_plane_wm->wm[level]))
11258 continue;
11259
11260 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11261 pipe_name(pipe), level,
11262 sw_plane_wm->wm[level].plane_en,
11263 sw_plane_wm->wm[level].plane_res_b,
11264 sw_plane_wm->wm[level].plane_res_l,
11265 hw_plane_wm->wm[level].plane_en,
11266 hw_plane_wm->wm[level].plane_res_b,
11267 hw_plane_wm->wm[level].plane_res_l);
11268 }
11269
11270 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11271 &sw_plane_wm->trans_wm)) {
11272 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11273 pipe_name(pipe),
11274 sw_plane_wm->trans_wm.plane_en,
11275 sw_plane_wm->trans_wm.plane_res_b,
11276 sw_plane_wm->trans_wm.plane_res_l,
11277 hw_plane_wm->trans_wm.plane_en,
11278 hw_plane_wm->trans_wm.plane_res_b,
11279 hw_plane_wm->trans_wm.plane_res_l);
11280 }
11281
11282 /* DDB */
11283 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11284 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11285
11286 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11287 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11288 pipe_name(pipe),
11289 sw_ddb_entry->start, sw_ddb_entry->end,
11290 hw_ddb_entry->start, hw_ddb_entry->end);
11291 }
11292 }
11293 }
11294
11295 static void
11296 verify_connector_state(struct drm_device *dev,
11297 struct drm_atomic_state *state,
11298 struct drm_crtc *crtc)
11299 {
11300 struct drm_connector *connector;
11301 struct drm_connector_state *new_conn_state;
11302 int i;
11303
11304 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11305 struct drm_encoder *encoder = connector->encoder;
11306 struct drm_crtc_state *crtc_state = NULL;
11307
11308 if (new_conn_state->crtc != crtc)
11309 continue;
11310
11311 if (crtc)
11312 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11313
11314 intel_connector_verify_state(crtc_state, new_conn_state);
11315
11316 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11317 "connector's atomic encoder doesn't match legacy encoder\n");
11318 }
11319 }
11320
11321 static void
11322 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11323 {
11324 struct intel_encoder *encoder;
11325 struct drm_connector *connector;
11326 struct drm_connector_state *old_conn_state, *new_conn_state;
11327 int i;
11328
11329 for_each_intel_encoder(dev, encoder) {
11330 bool enabled = false, found = false;
11331 enum pipe pipe;
11332
11333 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11334 encoder->base.base.id,
11335 encoder->base.name);
11336
11337 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11338 new_conn_state, i) {
11339 if (old_conn_state->best_encoder == &encoder->base)
11340 found = true;
11341
11342 if (new_conn_state->best_encoder != &encoder->base)
11343 continue;
11344 found = enabled = true;
11345
11346 I915_STATE_WARN(new_conn_state->crtc !=
11347 encoder->base.crtc,
11348 "connector's crtc doesn't match encoder crtc\n");
11349 }
11350
11351 if (!found)
11352 continue;
11353
11354 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11355 "encoder's enabled state mismatch "
11356 "(expected %i, found %i)\n",
11357 !!encoder->base.crtc, enabled);
11358
11359 if (!encoder->base.crtc) {
11360 bool active;
11361
11362 active = encoder->get_hw_state(encoder, &pipe);
11363 I915_STATE_WARN(active,
11364 "encoder detached but still enabled on pipe %c.\n",
11365 pipe_name(pipe));
11366 }
11367 }
11368 }
11369
11370 static void
11371 verify_crtc_state(struct drm_crtc *crtc,
11372 struct drm_crtc_state *old_crtc_state,
11373 struct drm_crtc_state *new_crtc_state)
11374 {
11375 struct drm_device *dev = crtc->dev;
11376 struct drm_i915_private *dev_priv = to_i915(dev);
11377 struct intel_encoder *encoder;
11378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11379 struct intel_crtc_state *pipe_config, *sw_config;
11380 struct drm_atomic_state *old_state;
11381 bool active;
11382
11383 old_state = old_crtc_state->state;
11384 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11385 pipe_config = to_intel_crtc_state(old_crtc_state);
11386 memset(pipe_config, 0, sizeof(*pipe_config));
11387 pipe_config->base.crtc = crtc;
11388 pipe_config->base.state = old_state;
11389
11390 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11391
11392 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11393
11394 /* we keep both pipes enabled on 830 */
11395 if (IS_I830(dev_priv))
11396 active = new_crtc_state->active;
11397
11398 I915_STATE_WARN(new_crtc_state->active != active,
11399 "crtc active state doesn't match with hw state "
11400 "(expected %i, found %i)\n", new_crtc_state->active, active);
11401
11402 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11403 "transitional active state does not match atomic hw state "
11404 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11405
11406 for_each_encoder_on_crtc(dev, crtc, encoder) {
11407 enum pipe pipe;
11408
11409 active = encoder->get_hw_state(encoder, &pipe);
11410 I915_STATE_WARN(active != new_crtc_state->active,
11411 "[ENCODER:%i] active %i with crtc active %i\n",
11412 encoder->base.base.id, active, new_crtc_state->active);
11413
11414 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11415 "Encoder connected to wrong pipe %c\n",
11416 pipe_name(pipe));
11417
11418 if (active) {
11419 pipe_config->output_types |= 1 << encoder->type;
11420 encoder->get_config(encoder, pipe_config);
11421 }
11422 }
11423
11424 intel_crtc_compute_pixel_rate(pipe_config);
11425
11426 if (!new_crtc_state->active)
11427 return;
11428
11429 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11430
11431 sw_config = to_intel_crtc_state(new_crtc_state);
11432 if (!intel_pipe_config_compare(dev_priv, sw_config,
11433 pipe_config, false)) {
11434 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11435 intel_dump_pipe_config(intel_crtc, pipe_config,
11436 "[hw state]");
11437 intel_dump_pipe_config(intel_crtc, sw_config,
11438 "[sw state]");
11439 }
11440 }
11441
11442 static void
11443 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11444 struct intel_shared_dpll *pll,
11445 struct drm_crtc *crtc,
11446 struct drm_crtc_state *new_state)
11447 {
11448 struct intel_dpll_hw_state dpll_hw_state;
11449 unsigned crtc_mask;
11450 bool active;
11451
11452 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11453
11454 DRM_DEBUG_KMS("%s\n", pll->name);
11455
11456 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11457
11458 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11459 I915_STATE_WARN(!pll->on && pll->active_mask,
11460 "pll in active use but not on in sw tracking\n");
11461 I915_STATE_WARN(pll->on && !pll->active_mask,
11462 "pll is on but not used by any active crtc\n");
11463 I915_STATE_WARN(pll->on != active,
11464 "pll on state mismatch (expected %i, found %i)\n",
11465 pll->on, active);
11466 }
11467
11468 if (!crtc) {
11469 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11470 "more active pll users than references: %x vs %x\n",
11471 pll->active_mask, pll->state.crtc_mask);
11472
11473 return;
11474 }
11475
11476 crtc_mask = 1 << drm_crtc_index(crtc);
11477
11478 if (new_state->active)
11479 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11480 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11481 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11482 else
11483 I915_STATE_WARN(pll->active_mask & crtc_mask,
11484 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11485 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11486
11487 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11488 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11489 crtc_mask, pll->state.crtc_mask);
11490
11491 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11492 &dpll_hw_state,
11493 sizeof(dpll_hw_state)),
11494 "pll hw state mismatch\n");
11495 }
11496
11497 static void
11498 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11499 struct drm_crtc_state *old_crtc_state,
11500 struct drm_crtc_state *new_crtc_state)
11501 {
11502 struct drm_i915_private *dev_priv = to_i915(dev);
11503 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11504 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11505
11506 if (new_state->shared_dpll)
11507 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11508
11509 if (old_state->shared_dpll &&
11510 old_state->shared_dpll != new_state->shared_dpll) {
11511 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11512 struct intel_shared_dpll *pll = old_state->shared_dpll;
11513
11514 I915_STATE_WARN(pll->active_mask & crtc_mask,
11515 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11516 pipe_name(drm_crtc_index(crtc)));
11517 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11518 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11519 pipe_name(drm_crtc_index(crtc)));
11520 }
11521 }
11522
11523 static void
11524 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11525 struct drm_atomic_state *state,
11526 struct drm_crtc_state *old_state,
11527 struct drm_crtc_state *new_state)
11528 {
11529 if (!needs_modeset(new_state) &&
11530 !to_intel_crtc_state(new_state)->update_pipe)
11531 return;
11532
11533 verify_wm_state(crtc, new_state);
11534 verify_connector_state(crtc->dev, state, crtc);
11535 verify_crtc_state(crtc, old_state, new_state);
11536 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11537 }
11538
11539 static void
11540 verify_disabled_dpll_state(struct drm_device *dev)
11541 {
11542 struct drm_i915_private *dev_priv = to_i915(dev);
11543 int i;
11544
11545 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11546 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11547 }
11548
11549 static void
11550 intel_modeset_verify_disabled(struct drm_device *dev,
11551 struct drm_atomic_state *state)
11552 {
11553 verify_encoder_state(dev, state);
11554 verify_connector_state(dev, state, NULL);
11555 verify_disabled_dpll_state(dev);
11556 }
11557
11558 static void update_scanline_offset(struct intel_crtc *crtc)
11559 {
11560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11561
11562 /*
11563 * The scanline counter increments at the leading edge of hsync.
11564 *
11565 * On most platforms it starts counting from vtotal-1 on the
11566 * first active line. That means the scanline counter value is
11567 * always one less than what we would expect. Ie. just after
11568 * start of vblank, which also occurs at start of hsync (on the
11569 * last active line), the scanline counter will read vblank_start-1.
11570 *
11571 * On gen2 the scanline counter starts counting from 1 instead
11572 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11573 * to keep the value positive), instead of adding one.
11574 *
11575 * On HSW+ the behaviour of the scanline counter depends on the output
11576 * type. For DP ports it behaves like most other platforms, but on HDMI
11577 * there's an extra 1 line difference. So we need to add two instead of
11578 * one to the value.
11579 *
11580 * On VLV/CHV DSI the scanline counter would appear to increment
11581 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11582 * that means we can't tell whether we're in vblank or not while
11583 * we're on that particular line. We must still set scanline_offset
11584 * to 1 so that the vblank timestamps come out correct when we query
11585 * the scanline counter from within the vblank interrupt handler.
11586 * However if queried just before the start of vblank we'll get an
11587 * answer that's slightly in the future.
11588 */
11589 if (IS_GEN2(dev_priv)) {
11590 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11591 int vtotal;
11592
11593 vtotal = adjusted_mode->crtc_vtotal;
11594 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11595 vtotal /= 2;
11596
11597 crtc->scanline_offset = vtotal - 1;
11598 } else if (HAS_DDI(dev_priv) &&
11599 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11600 crtc->scanline_offset = 2;
11601 } else
11602 crtc->scanline_offset = 1;
11603 }
11604
11605 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11606 {
11607 struct drm_device *dev = state->dev;
11608 struct drm_i915_private *dev_priv = to_i915(dev);
11609 struct drm_crtc *crtc;
11610 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11611 int i;
11612
11613 if (!dev_priv->display.crtc_compute_clock)
11614 return;
11615
11616 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11618 struct intel_shared_dpll *old_dpll =
11619 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11620
11621 if (!needs_modeset(new_crtc_state))
11622 continue;
11623
11624 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11625
11626 if (!old_dpll)
11627 continue;
11628
11629 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11630 }
11631 }
11632
11633 /*
11634 * This implements the workaround described in the "notes" section of the mode
11635 * set sequence documentation. When going from no pipes or single pipe to
11636 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11637 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11638 */
11639 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11640 {
11641 struct drm_crtc_state *crtc_state;
11642 struct intel_crtc *intel_crtc;
11643 struct drm_crtc *crtc;
11644 struct intel_crtc_state *first_crtc_state = NULL;
11645 struct intel_crtc_state *other_crtc_state = NULL;
11646 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11647 int i;
11648
11649 /* look at all crtc's that are going to be enabled in during modeset */
11650 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11651 intel_crtc = to_intel_crtc(crtc);
11652
11653 if (!crtc_state->active || !needs_modeset(crtc_state))
11654 continue;
11655
11656 if (first_crtc_state) {
11657 other_crtc_state = to_intel_crtc_state(crtc_state);
11658 break;
11659 } else {
11660 first_crtc_state = to_intel_crtc_state(crtc_state);
11661 first_pipe = intel_crtc->pipe;
11662 }
11663 }
11664
11665 /* No workaround needed? */
11666 if (!first_crtc_state)
11667 return 0;
11668
11669 /* w/a possibly needed, check how many crtc's are already enabled. */
11670 for_each_intel_crtc(state->dev, intel_crtc) {
11671 struct intel_crtc_state *pipe_config;
11672
11673 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11674 if (IS_ERR(pipe_config))
11675 return PTR_ERR(pipe_config);
11676
11677 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11678
11679 if (!pipe_config->base.active ||
11680 needs_modeset(&pipe_config->base))
11681 continue;
11682
11683 /* 2 or more enabled crtcs means no need for w/a */
11684 if (enabled_pipe != INVALID_PIPE)
11685 return 0;
11686
11687 enabled_pipe = intel_crtc->pipe;
11688 }
11689
11690 if (enabled_pipe != INVALID_PIPE)
11691 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11692 else if (other_crtc_state)
11693 other_crtc_state->hsw_workaround_pipe = first_pipe;
11694
11695 return 0;
11696 }
11697
11698 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11699 {
11700 struct drm_crtc *crtc;
11701
11702 /* Add all pipes to the state */
11703 for_each_crtc(state->dev, crtc) {
11704 struct drm_crtc_state *crtc_state;
11705
11706 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11707 if (IS_ERR(crtc_state))
11708 return PTR_ERR(crtc_state);
11709 }
11710
11711 return 0;
11712 }
11713
11714 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11715 {
11716 struct drm_crtc *crtc;
11717
11718 /*
11719 * Add all pipes to the state, and force
11720 * a modeset on all the active ones.
11721 */
11722 for_each_crtc(state->dev, crtc) {
11723 struct drm_crtc_state *crtc_state;
11724 int ret;
11725
11726 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11727 if (IS_ERR(crtc_state))
11728 return PTR_ERR(crtc_state);
11729
11730 if (!crtc_state->active || needs_modeset(crtc_state))
11731 continue;
11732
11733 crtc_state->mode_changed = true;
11734
11735 ret = drm_atomic_add_affected_connectors(state, crtc);
11736 if (ret)
11737 return ret;
11738
11739 ret = drm_atomic_add_affected_planes(state, crtc);
11740 if (ret)
11741 return ret;
11742 }
11743
11744 return 0;
11745 }
11746
11747 static int intel_modeset_checks(struct drm_atomic_state *state)
11748 {
11749 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11750 struct drm_i915_private *dev_priv = to_i915(state->dev);
11751 struct drm_crtc *crtc;
11752 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11753 int ret = 0, i;
11754
11755 if (!check_digital_port_conflicts(state)) {
11756 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11757 return -EINVAL;
11758 }
11759
11760 intel_state->modeset = true;
11761 intel_state->active_crtcs = dev_priv->active_crtcs;
11762 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11763 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11764
11765 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11766 if (new_crtc_state->active)
11767 intel_state->active_crtcs |= 1 << i;
11768 else
11769 intel_state->active_crtcs &= ~(1 << i);
11770
11771 if (old_crtc_state->active != new_crtc_state->active)
11772 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11773 }
11774
11775 /*
11776 * See if the config requires any additional preparation, e.g.
11777 * to adjust global state with pipes off. We need to do this
11778 * here so we can get the modeset_pipe updated config for the new
11779 * mode set on this crtc. For other crtcs we need to use the
11780 * adjusted_mode bits in the crtc directly.
11781 */
11782 if (dev_priv->display.modeset_calc_cdclk) {
11783 ret = dev_priv->display.modeset_calc_cdclk(state);
11784 if (ret < 0)
11785 return ret;
11786
11787 /*
11788 * Writes to dev_priv->cdclk.logical must protected by
11789 * holding all the crtc locks, even if we don't end up
11790 * touching the hardware
11791 */
11792 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11793 &intel_state->cdclk.logical)) {
11794 ret = intel_lock_all_pipes(state);
11795 if (ret < 0)
11796 return ret;
11797 }
11798
11799 /* All pipes must be switched off while we change the cdclk. */
11800 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11801 &intel_state->cdclk.actual)) {
11802 ret = intel_modeset_all_pipes(state);
11803 if (ret < 0)
11804 return ret;
11805 }
11806
11807 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11808 intel_state->cdclk.logical.cdclk,
11809 intel_state->cdclk.actual.cdclk);
11810 } else {
11811 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11812 }
11813
11814 intel_modeset_clear_plls(state);
11815
11816 if (IS_HASWELL(dev_priv))
11817 return haswell_mode_set_planes_workaround(state);
11818
11819 return 0;
11820 }
11821
11822 /*
11823 * Handle calculation of various watermark data at the end of the atomic check
11824 * phase. The code here should be run after the per-crtc and per-plane 'check'
11825 * handlers to ensure that all derived state has been updated.
11826 */
11827 static int calc_watermark_data(struct drm_atomic_state *state)
11828 {
11829 struct drm_device *dev = state->dev;
11830 struct drm_i915_private *dev_priv = to_i915(dev);
11831
11832 /* Is there platform-specific watermark information to calculate? */
11833 if (dev_priv->display.compute_global_watermarks)
11834 return dev_priv->display.compute_global_watermarks(state);
11835
11836 return 0;
11837 }
11838
11839 /**
11840 * intel_atomic_check - validate state object
11841 * @dev: drm device
11842 * @state: state to validate
11843 */
11844 static int intel_atomic_check(struct drm_device *dev,
11845 struct drm_atomic_state *state)
11846 {
11847 struct drm_i915_private *dev_priv = to_i915(dev);
11848 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11849 struct drm_crtc *crtc;
11850 struct drm_crtc_state *old_crtc_state, *crtc_state;
11851 int ret, i;
11852 bool any_ms = false;
11853
11854 ret = drm_atomic_helper_check_modeset(dev, state);
11855 if (ret)
11856 return ret;
11857
11858 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
11859 struct intel_crtc_state *pipe_config =
11860 to_intel_crtc_state(crtc_state);
11861
11862 /* Catch I915_MODE_FLAG_INHERITED */
11863 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
11864 crtc_state->mode_changed = true;
11865
11866 if (!needs_modeset(crtc_state))
11867 continue;
11868
11869 if (!crtc_state->enable) {
11870 any_ms = true;
11871 continue;
11872 }
11873
11874 /* FIXME: For only active_changed we shouldn't need to do any
11875 * state recomputation at all. */
11876
11877 ret = drm_atomic_add_affected_connectors(state, crtc);
11878 if (ret)
11879 return ret;
11880
11881 ret = intel_modeset_pipe_config(crtc, pipe_config);
11882 if (ret) {
11883 intel_dump_pipe_config(to_intel_crtc(crtc),
11884 pipe_config, "[failed]");
11885 return ret;
11886 }
11887
11888 if (i915.fastboot &&
11889 intel_pipe_config_compare(dev_priv,
11890 to_intel_crtc_state(old_crtc_state),
11891 pipe_config, true)) {
11892 crtc_state->mode_changed = false;
11893 pipe_config->update_pipe = true;
11894 }
11895
11896 if (needs_modeset(crtc_state))
11897 any_ms = true;
11898
11899 ret = drm_atomic_add_affected_planes(state, crtc);
11900 if (ret)
11901 return ret;
11902
11903 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11904 needs_modeset(crtc_state) ?
11905 "[modeset]" : "[fastset]");
11906 }
11907
11908 if (any_ms) {
11909 ret = intel_modeset_checks(state);
11910
11911 if (ret)
11912 return ret;
11913 } else {
11914 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11915 }
11916
11917 ret = drm_atomic_helper_check_planes(dev, state);
11918 if (ret)
11919 return ret;
11920
11921 intel_fbc_choose_crtc(dev_priv, state);
11922 return calc_watermark_data(state);
11923 }
11924
11925 static int intel_atomic_prepare_commit(struct drm_device *dev,
11926 struct drm_atomic_state *state)
11927 {
11928 struct drm_i915_private *dev_priv = to_i915(dev);
11929 struct drm_crtc_state *crtc_state;
11930 struct drm_crtc *crtc;
11931 int i, ret;
11932
11933 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11934 if (state->legacy_cursor_update)
11935 continue;
11936
11937 ret = intel_crtc_wait_for_pending_flips(crtc);
11938 if (ret)
11939 return ret;
11940
11941 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
11942 flush_workqueue(dev_priv->wq);
11943 }
11944
11945 ret = mutex_lock_interruptible(&dev->struct_mutex);
11946 if (ret)
11947 return ret;
11948
11949 ret = drm_atomic_helper_prepare_planes(dev, state);
11950 mutex_unlock(&dev->struct_mutex);
11951
11952 return ret;
11953 }
11954
11955 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
11956 {
11957 struct drm_device *dev = crtc->base.dev;
11958
11959 if (!dev->max_vblank_count)
11960 return drm_accurate_vblank_count(&crtc->base);
11961
11962 return dev->driver->get_vblank_counter(dev, crtc->pipe);
11963 }
11964
11965 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
11966 struct drm_i915_private *dev_priv,
11967 unsigned crtc_mask)
11968 {
11969 unsigned last_vblank_count[I915_MAX_PIPES];
11970 enum pipe pipe;
11971 int ret;
11972
11973 if (!crtc_mask)
11974 return;
11975
11976 for_each_pipe(dev_priv, pipe) {
11977 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11978 pipe);
11979
11980 if (!((1 << pipe) & crtc_mask))
11981 continue;
11982
11983 ret = drm_crtc_vblank_get(&crtc->base);
11984 if (WARN_ON(ret != 0)) {
11985 crtc_mask &= ~(1 << pipe);
11986 continue;
11987 }
11988
11989 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
11990 }
11991
11992 for_each_pipe(dev_priv, pipe) {
11993 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11994 pipe);
11995 long lret;
11996
11997 if (!((1 << pipe) & crtc_mask))
11998 continue;
11999
12000 lret = wait_event_timeout(dev->vblank[pipe].queue,
12001 last_vblank_count[pipe] !=
12002 drm_crtc_vblank_count(&crtc->base),
12003 msecs_to_jiffies(50));
12004
12005 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12006
12007 drm_crtc_vblank_put(&crtc->base);
12008 }
12009 }
12010
12011 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12012 {
12013 /* fb updated, need to unpin old fb */
12014 if (crtc_state->fb_changed)
12015 return true;
12016
12017 /* wm changes, need vblank before final wm's */
12018 if (crtc_state->update_wm_post)
12019 return true;
12020
12021 if (crtc_state->wm.need_postvbl_update)
12022 return true;
12023
12024 return false;
12025 }
12026
12027 static void intel_update_crtc(struct drm_crtc *crtc,
12028 struct drm_atomic_state *state,
12029 struct drm_crtc_state *old_crtc_state,
12030 struct drm_crtc_state *new_crtc_state,
12031 unsigned int *crtc_vblank_mask)
12032 {
12033 struct drm_device *dev = crtc->dev;
12034 struct drm_i915_private *dev_priv = to_i915(dev);
12035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12036 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12037 bool modeset = needs_modeset(new_crtc_state);
12038
12039 if (modeset) {
12040 update_scanline_offset(intel_crtc);
12041 dev_priv->display.crtc_enable(pipe_config, state);
12042 } else {
12043 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12044 pipe_config);
12045 }
12046
12047 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12048 intel_fbc_enable(
12049 intel_crtc, pipe_config,
12050 to_intel_plane_state(crtc->primary->state));
12051 }
12052
12053 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12054
12055 if (needs_vblank_wait(pipe_config))
12056 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12057 }
12058
12059 static void intel_update_crtcs(struct drm_atomic_state *state,
12060 unsigned int *crtc_vblank_mask)
12061 {
12062 struct drm_crtc *crtc;
12063 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12064 int i;
12065
12066 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12067 if (!new_crtc_state->active)
12068 continue;
12069
12070 intel_update_crtc(crtc, state, old_crtc_state,
12071 new_crtc_state, crtc_vblank_mask);
12072 }
12073 }
12074
12075 static void skl_update_crtcs(struct drm_atomic_state *state,
12076 unsigned int *crtc_vblank_mask)
12077 {
12078 struct drm_i915_private *dev_priv = to_i915(state->dev);
12079 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12080 struct drm_crtc *crtc;
12081 struct intel_crtc *intel_crtc;
12082 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12083 struct intel_crtc_state *cstate;
12084 unsigned int updated = 0;
12085 bool progress;
12086 enum pipe pipe;
12087 int i;
12088
12089 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12090
12091 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12092 /* ignore allocations for crtc's that have been turned off. */
12093 if (new_crtc_state->active)
12094 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12095
12096 /*
12097 * Whenever the number of active pipes changes, we need to make sure we
12098 * update the pipes in the right order so that their ddb allocations
12099 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12100 * cause pipe underruns and other bad stuff.
12101 */
12102 do {
12103 progress = false;
12104
12105 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12106 bool vbl_wait = false;
12107 unsigned int cmask = drm_crtc_mask(crtc);
12108
12109 intel_crtc = to_intel_crtc(crtc);
12110 cstate = to_intel_crtc_state(crtc->state);
12111 pipe = intel_crtc->pipe;
12112
12113 if (updated & cmask || !cstate->base.active)
12114 continue;
12115
12116 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12117 continue;
12118
12119 updated |= cmask;
12120 entries[i] = &cstate->wm.skl.ddb;
12121
12122 /*
12123 * If this is an already active pipe, it's DDB changed,
12124 * and this isn't the last pipe that needs updating
12125 * then we need to wait for a vblank to pass for the
12126 * new ddb allocation to take effect.
12127 */
12128 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12129 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12130 !new_crtc_state->active_changed &&
12131 intel_state->wm_results.dirty_pipes != updated)
12132 vbl_wait = true;
12133
12134 intel_update_crtc(crtc, state, old_crtc_state,
12135 new_crtc_state, crtc_vblank_mask);
12136
12137 if (vbl_wait)
12138 intel_wait_for_vblank(dev_priv, pipe);
12139
12140 progress = true;
12141 }
12142 } while (progress);
12143 }
12144
12145 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12146 {
12147 struct intel_atomic_state *state, *next;
12148 struct llist_node *freed;
12149
12150 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12151 llist_for_each_entry_safe(state, next, freed, freed)
12152 drm_atomic_state_put(&state->base);
12153 }
12154
12155 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12156 {
12157 struct drm_i915_private *dev_priv =
12158 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12159
12160 intel_atomic_helper_free_state(dev_priv);
12161 }
12162
12163 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12164 {
12165 struct drm_device *dev = state->dev;
12166 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12167 struct drm_i915_private *dev_priv = to_i915(dev);
12168 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12169 struct drm_crtc *crtc;
12170 struct intel_crtc_state *intel_cstate;
12171 bool hw_check = intel_state->modeset;
12172 u64 put_domains[I915_MAX_PIPES] = {};
12173 unsigned crtc_vblank_mask = 0;
12174 int i;
12175
12176 drm_atomic_helper_wait_for_dependencies(state);
12177
12178 if (intel_state->modeset)
12179 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12180
12181 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12183
12184 if (needs_modeset(new_crtc_state) ||
12185 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12186 hw_check = true;
12187
12188 put_domains[to_intel_crtc(crtc)->pipe] =
12189 modeset_get_crtc_power_domains(crtc,
12190 to_intel_crtc_state(new_crtc_state));
12191 }
12192
12193 if (!needs_modeset(new_crtc_state))
12194 continue;
12195
12196 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12197 to_intel_crtc_state(new_crtc_state));
12198
12199 if (old_crtc_state->active) {
12200 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12201 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12202 intel_crtc->active = false;
12203 intel_fbc_disable(intel_crtc);
12204 intel_disable_shared_dpll(intel_crtc);
12205
12206 /*
12207 * Underruns don't always raise
12208 * interrupts, so check manually.
12209 */
12210 intel_check_cpu_fifo_underruns(dev_priv);
12211 intel_check_pch_fifo_underruns(dev_priv);
12212
12213 if (!crtc->state->active) {
12214 /*
12215 * Make sure we don't call initial_watermarks
12216 * for ILK-style watermark updates.
12217 *
12218 * No clue what this is supposed to achieve.
12219 */
12220 if (INTEL_GEN(dev_priv) >= 9)
12221 dev_priv->display.initial_watermarks(intel_state,
12222 to_intel_crtc_state(crtc->state));
12223 }
12224 }
12225 }
12226
12227 /* Only after disabling all output pipelines that will be changed can we
12228 * update the the output configuration. */
12229 intel_modeset_update_crtc_state(state);
12230
12231 if (intel_state->modeset) {
12232 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12233
12234 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12235
12236 /*
12237 * SKL workaround: bspec recommends we disable the SAGV when we
12238 * have more then one pipe enabled
12239 */
12240 if (!intel_can_enable_sagv(state))
12241 intel_disable_sagv(dev_priv);
12242
12243 intel_modeset_verify_disabled(dev, state);
12244 }
12245
12246 /* Complete the events for pipes that have now been disabled */
12247 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12248 bool modeset = needs_modeset(new_crtc_state);
12249
12250 /* Complete events for now disable pipes here. */
12251 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12252 spin_lock_irq(&dev->event_lock);
12253 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12254 spin_unlock_irq(&dev->event_lock);
12255
12256 new_crtc_state->event = NULL;
12257 }
12258 }
12259
12260 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12261 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12262
12263 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12264 * already, but still need the state for the delayed optimization. To
12265 * fix this:
12266 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12267 * - schedule that vblank worker _before_ calling hw_done
12268 * - at the start of commit_tail, cancel it _synchrously
12269 * - switch over to the vblank wait helper in the core after that since
12270 * we don't need out special handling any more.
12271 */
12272 if (!state->legacy_cursor_update)
12273 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12274
12275 /*
12276 * Now that the vblank has passed, we can go ahead and program the
12277 * optimal watermarks on platforms that need two-step watermark
12278 * programming.
12279 *
12280 * TODO: Move this (and other cleanup) to an async worker eventually.
12281 */
12282 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12283 intel_cstate = to_intel_crtc_state(new_crtc_state);
12284
12285 if (dev_priv->display.optimize_watermarks)
12286 dev_priv->display.optimize_watermarks(intel_state,
12287 intel_cstate);
12288 }
12289
12290 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12291 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12292
12293 if (put_domains[i])
12294 modeset_put_power_domains(dev_priv, put_domains[i]);
12295
12296 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12297 }
12298
12299 if (intel_state->modeset && intel_can_enable_sagv(state))
12300 intel_enable_sagv(dev_priv);
12301
12302 drm_atomic_helper_commit_hw_done(state);
12303
12304 if (intel_state->modeset) {
12305 /* As one of the primary mmio accessors, KMS has a high
12306 * likelihood of triggering bugs in unclaimed access. After we
12307 * finish modesetting, see if an error has been flagged, and if
12308 * so enable debugging for the next modeset - and hope we catch
12309 * the culprit.
12310 */
12311 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12312 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12313 }
12314
12315 mutex_lock(&dev->struct_mutex);
12316 drm_atomic_helper_cleanup_planes(dev, state);
12317 mutex_unlock(&dev->struct_mutex);
12318
12319 drm_atomic_helper_commit_cleanup_done(state);
12320
12321 drm_atomic_state_put(state);
12322
12323 intel_atomic_helper_free_state(dev_priv);
12324 }
12325
12326 static void intel_atomic_commit_work(struct work_struct *work)
12327 {
12328 struct drm_atomic_state *state =
12329 container_of(work, struct drm_atomic_state, commit_work);
12330
12331 intel_atomic_commit_tail(state);
12332 }
12333
12334 static int __i915_sw_fence_call
12335 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12336 enum i915_sw_fence_notify notify)
12337 {
12338 struct intel_atomic_state *state =
12339 container_of(fence, struct intel_atomic_state, commit_ready);
12340
12341 switch (notify) {
12342 case FENCE_COMPLETE:
12343 if (state->base.commit_work.func)
12344 queue_work(system_unbound_wq, &state->base.commit_work);
12345 break;
12346
12347 case FENCE_FREE:
12348 {
12349 struct intel_atomic_helper *helper =
12350 &to_i915(state->base.dev)->atomic_helper;
12351
12352 if (llist_add(&state->freed, &helper->free_list))
12353 schedule_work(&helper->free_work);
12354 break;
12355 }
12356 }
12357
12358 return NOTIFY_DONE;
12359 }
12360
12361 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12362 {
12363 struct drm_plane_state *old_plane_state, *new_plane_state;
12364 struct drm_plane *plane;
12365 int i;
12366
12367 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12368 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12369 intel_fb_obj(new_plane_state->fb),
12370 to_intel_plane(plane)->frontbuffer_bit);
12371 }
12372
12373 /**
12374 * intel_atomic_commit - commit validated state object
12375 * @dev: DRM device
12376 * @state: the top-level driver state object
12377 * @nonblock: nonblocking commit
12378 *
12379 * This function commits a top-level state object that has been validated
12380 * with drm_atomic_helper_check().
12381 *
12382 * RETURNS
12383 * Zero for success or -errno.
12384 */
12385 static int intel_atomic_commit(struct drm_device *dev,
12386 struct drm_atomic_state *state,
12387 bool nonblock)
12388 {
12389 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12390 struct drm_i915_private *dev_priv = to_i915(dev);
12391 int ret = 0;
12392
12393 ret = drm_atomic_helper_setup_commit(state, nonblock);
12394 if (ret)
12395 return ret;
12396
12397 drm_atomic_state_get(state);
12398 i915_sw_fence_init(&intel_state->commit_ready,
12399 intel_atomic_commit_ready);
12400
12401 ret = intel_atomic_prepare_commit(dev, state);
12402 if (ret) {
12403 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12404 i915_sw_fence_commit(&intel_state->commit_ready);
12405 return ret;
12406 }
12407
12408 /*
12409 * The intel_legacy_cursor_update() fast path takes care
12410 * of avoiding the vblank waits for simple cursor
12411 * movement and flips. For cursor on/off and size changes,
12412 * we want to perform the vblank waits so that watermark
12413 * updates happen during the correct frames. Gen9+ have
12414 * double buffered watermarks and so shouldn't need this.
12415 *
12416 * Do this after drm_atomic_helper_setup_commit() and
12417 * intel_atomic_prepare_commit() because we still want
12418 * to skip the flip and fb cleanup waits. Although that
12419 * does risk yanking the mapping from under the display
12420 * engine.
12421 *
12422 * FIXME doing watermarks and fb cleanup from a vblank worker
12423 * (assuming we had any) would solve these problems.
12424 */
12425 if (INTEL_GEN(dev_priv) < 9)
12426 state->legacy_cursor_update = false;
12427
12428 drm_atomic_helper_swap_state(state, true);
12429 dev_priv->wm.distrust_bios_wm = false;
12430 intel_shared_dpll_swap_state(state);
12431 intel_atomic_track_fbs(state);
12432
12433 if (intel_state->modeset) {
12434 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
12435 sizeof(intel_state->min_pixclk));
12436 dev_priv->active_crtcs = intel_state->active_crtcs;
12437 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12438 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12439 }
12440
12441 drm_atomic_state_get(state);
12442 INIT_WORK(&state->commit_work,
12443 nonblock ? intel_atomic_commit_work : NULL);
12444
12445 i915_sw_fence_commit(&intel_state->commit_ready);
12446 if (!nonblock) {
12447 i915_sw_fence_wait(&intel_state->commit_ready);
12448 intel_atomic_commit_tail(state);
12449 }
12450
12451 return 0;
12452 }
12453
12454 static const struct drm_crtc_funcs intel_crtc_funcs = {
12455 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12456 .set_config = drm_atomic_helper_set_config,
12457 .set_property = drm_atomic_helper_crtc_set_property,
12458 .destroy = intel_crtc_destroy,
12459 .page_flip = drm_atomic_helper_page_flip,
12460 .atomic_duplicate_state = intel_crtc_duplicate_state,
12461 .atomic_destroy_state = intel_crtc_destroy_state,
12462 .set_crc_source = intel_crtc_set_crc_source,
12463 };
12464
12465 /**
12466 * intel_prepare_plane_fb - Prepare fb for usage on plane
12467 * @plane: drm plane to prepare for
12468 * @fb: framebuffer to prepare for presentation
12469 *
12470 * Prepares a framebuffer for usage on a display plane. Generally this
12471 * involves pinning the underlying object and updating the frontbuffer tracking
12472 * bits. Some older platforms need special physical address handling for
12473 * cursor planes.
12474 *
12475 * Must be called with struct_mutex held.
12476 *
12477 * Returns 0 on success, negative error code on failure.
12478 */
12479 int
12480 intel_prepare_plane_fb(struct drm_plane *plane,
12481 struct drm_plane_state *new_state)
12482 {
12483 struct intel_atomic_state *intel_state =
12484 to_intel_atomic_state(new_state->state);
12485 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12486 struct drm_framebuffer *fb = new_state->fb;
12487 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12488 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12489 int ret;
12490
12491 if (obj) {
12492 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12493 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12494 const int align = intel_cursor_alignment(dev_priv);
12495
12496 ret = i915_gem_object_attach_phys(obj, align);
12497 if (ret) {
12498 DRM_DEBUG_KMS("failed to attach phys object\n");
12499 return ret;
12500 }
12501 } else {
12502 struct i915_vma *vma;
12503
12504 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12505 if (IS_ERR(vma)) {
12506 DRM_DEBUG_KMS("failed to pin object\n");
12507 return PTR_ERR(vma);
12508 }
12509
12510 to_intel_plane_state(new_state)->vma = vma;
12511 }
12512 }
12513
12514 if (!obj && !old_obj)
12515 return 0;
12516
12517 if (old_obj) {
12518 struct drm_crtc_state *crtc_state =
12519 drm_atomic_get_existing_crtc_state(new_state->state,
12520 plane->state->crtc);
12521
12522 /* Big Hammer, we also need to ensure that any pending
12523 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12524 * current scanout is retired before unpinning the old
12525 * framebuffer. Note that we rely on userspace rendering
12526 * into the buffer attached to the pipe they are waiting
12527 * on. If not, userspace generates a GPU hang with IPEHR
12528 * point to the MI_WAIT_FOR_EVENT.
12529 *
12530 * This should only fail upon a hung GPU, in which case we
12531 * can safely continue.
12532 */
12533 if (needs_modeset(crtc_state)) {
12534 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12535 old_obj->resv, NULL,
12536 false, 0,
12537 GFP_KERNEL);
12538 if (ret < 0)
12539 return ret;
12540 }
12541 }
12542
12543 if (new_state->fence) { /* explicit fencing */
12544 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12545 new_state->fence,
12546 I915_FENCE_TIMEOUT,
12547 GFP_KERNEL);
12548 if (ret < 0)
12549 return ret;
12550 }
12551
12552 if (!obj)
12553 return 0;
12554
12555 if (!new_state->fence) { /* implicit fencing */
12556 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12557 obj->resv, NULL,
12558 false, I915_FENCE_TIMEOUT,
12559 GFP_KERNEL);
12560 if (ret < 0)
12561 return ret;
12562
12563 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12564 }
12565
12566 return 0;
12567 }
12568
12569 /**
12570 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12571 * @plane: drm plane to clean up for
12572 * @fb: old framebuffer that was on plane
12573 *
12574 * Cleans up a framebuffer that has just been removed from a plane.
12575 *
12576 * Must be called with struct_mutex held.
12577 */
12578 void
12579 intel_cleanup_plane_fb(struct drm_plane *plane,
12580 struct drm_plane_state *old_state)
12581 {
12582 struct i915_vma *vma;
12583
12584 /* Should only be called after a successful intel_prepare_plane_fb()! */
12585 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12586 if (vma)
12587 intel_unpin_fb_vma(vma);
12588 }
12589
12590 int
12591 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12592 {
12593 struct drm_i915_private *dev_priv;
12594 int max_scale;
12595 int crtc_clock, max_dotclk;
12596
12597 if (!intel_crtc || !crtc_state->base.enable)
12598 return DRM_PLANE_HELPER_NO_SCALING;
12599
12600 dev_priv = to_i915(intel_crtc->base.dev);
12601
12602 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12603 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12604
12605 if (IS_GEMINILAKE(dev_priv))
12606 max_dotclk *= 2;
12607
12608 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12609 return DRM_PLANE_HELPER_NO_SCALING;
12610
12611 /*
12612 * skl max scale is lower of:
12613 * close to 3 but not 3, -1 is for that purpose
12614 * or
12615 * cdclk/crtc_clock
12616 */
12617 max_scale = min((1 << 16) * 3 - 1,
12618 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12619
12620 return max_scale;
12621 }
12622
12623 static int
12624 intel_check_primary_plane(struct intel_plane *plane,
12625 struct intel_crtc_state *crtc_state,
12626 struct intel_plane_state *state)
12627 {
12628 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12629 struct drm_crtc *crtc = state->base.crtc;
12630 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12631 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12632 bool can_position = false;
12633 int ret;
12634
12635 if (INTEL_GEN(dev_priv) >= 9) {
12636 /* use scaler when colorkey is not required */
12637 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12638 min_scale = 1;
12639 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12640 }
12641 can_position = true;
12642 }
12643
12644 ret = drm_plane_helper_check_state(&state->base,
12645 &state->clip,
12646 min_scale, max_scale,
12647 can_position, true);
12648 if (ret)
12649 return ret;
12650
12651 if (!state->base.fb)
12652 return 0;
12653
12654 if (INTEL_GEN(dev_priv) >= 9) {
12655 ret = skl_check_plane_surface(state);
12656 if (ret)
12657 return ret;
12658
12659 state->ctl = skl_plane_ctl(crtc_state, state);
12660 } else {
12661 ret = i9xx_check_plane_surface(state);
12662 if (ret)
12663 return ret;
12664
12665 state->ctl = i9xx_plane_ctl(crtc_state, state);
12666 }
12667
12668 return 0;
12669 }
12670
12671 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12672 struct drm_crtc_state *old_crtc_state)
12673 {
12674 struct drm_device *dev = crtc->dev;
12675 struct drm_i915_private *dev_priv = to_i915(dev);
12676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12677 struct intel_crtc_state *intel_cstate =
12678 to_intel_crtc_state(crtc->state);
12679 struct intel_crtc_state *old_intel_cstate =
12680 to_intel_crtc_state(old_crtc_state);
12681 struct intel_atomic_state *old_intel_state =
12682 to_intel_atomic_state(old_crtc_state->state);
12683 bool modeset = needs_modeset(crtc->state);
12684
12685 if (!modeset &&
12686 (intel_cstate->base.color_mgmt_changed ||
12687 intel_cstate->update_pipe)) {
12688 intel_color_set_csc(crtc->state);
12689 intel_color_load_luts(crtc->state);
12690 }
12691
12692 /* Perform vblank evasion around commit operation */
12693 intel_pipe_update_start(intel_crtc);
12694
12695 if (modeset)
12696 goto out;
12697
12698 if (intel_cstate->update_pipe)
12699 intel_update_pipe_config(intel_crtc, old_intel_cstate);
12700 else if (INTEL_GEN(dev_priv) >= 9)
12701 skl_detach_scalers(intel_crtc);
12702
12703 out:
12704 if (dev_priv->display.atomic_update_watermarks)
12705 dev_priv->display.atomic_update_watermarks(old_intel_state,
12706 intel_cstate);
12707 }
12708
12709 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12710 struct drm_crtc_state *old_crtc_state)
12711 {
12712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12713
12714 intel_pipe_update_end(intel_crtc, NULL);
12715 }
12716
12717 /**
12718 * intel_plane_destroy - destroy a plane
12719 * @plane: plane to destroy
12720 *
12721 * Common destruction function for all types of planes (primary, cursor,
12722 * sprite).
12723 */
12724 void intel_plane_destroy(struct drm_plane *plane)
12725 {
12726 drm_plane_cleanup(plane);
12727 kfree(to_intel_plane(plane));
12728 }
12729
12730 const struct drm_plane_funcs intel_plane_funcs = {
12731 .update_plane = drm_atomic_helper_update_plane,
12732 .disable_plane = drm_atomic_helper_disable_plane,
12733 .destroy = intel_plane_destroy,
12734 .set_property = drm_atomic_helper_plane_set_property,
12735 .atomic_get_property = intel_plane_atomic_get_property,
12736 .atomic_set_property = intel_plane_atomic_set_property,
12737 .atomic_duplicate_state = intel_plane_duplicate_state,
12738 .atomic_destroy_state = intel_plane_destroy_state,
12739 };
12740
12741 static int
12742 intel_legacy_cursor_update(struct drm_plane *plane,
12743 struct drm_crtc *crtc,
12744 struct drm_framebuffer *fb,
12745 int crtc_x, int crtc_y,
12746 unsigned int crtc_w, unsigned int crtc_h,
12747 uint32_t src_x, uint32_t src_y,
12748 uint32_t src_w, uint32_t src_h,
12749 struct drm_modeset_acquire_ctx *ctx)
12750 {
12751 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12752 int ret;
12753 struct drm_plane_state *old_plane_state, *new_plane_state;
12754 struct intel_plane *intel_plane = to_intel_plane(plane);
12755 struct drm_framebuffer *old_fb;
12756 struct drm_crtc_state *crtc_state = crtc->state;
12757 struct i915_vma *old_vma;
12758
12759 /*
12760 * When crtc is inactive or there is a modeset pending,
12761 * wait for it to complete in the slowpath
12762 */
12763 if (!crtc_state->active || needs_modeset(crtc_state) ||
12764 to_intel_crtc_state(crtc_state)->update_pipe)
12765 goto slow;
12766
12767 old_plane_state = plane->state;
12768
12769 /*
12770 * If any parameters change that may affect watermarks,
12771 * take the slowpath. Only changing fb or position should be
12772 * in the fastpath.
12773 */
12774 if (old_plane_state->crtc != crtc ||
12775 old_plane_state->src_w != src_w ||
12776 old_plane_state->src_h != src_h ||
12777 old_plane_state->crtc_w != crtc_w ||
12778 old_plane_state->crtc_h != crtc_h ||
12779 !old_plane_state->fb != !fb)
12780 goto slow;
12781
12782 new_plane_state = intel_plane_duplicate_state(plane);
12783 if (!new_plane_state)
12784 return -ENOMEM;
12785
12786 drm_atomic_set_fb_for_plane(new_plane_state, fb);
12787
12788 new_plane_state->src_x = src_x;
12789 new_plane_state->src_y = src_y;
12790 new_plane_state->src_w = src_w;
12791 new_plane_state->src_h = src_h;
12792 new_plane_state->crtc_x = crtc_x;
12793 new_plane_state->crtc_y = crtc_y;
12794 new_plane_state->crtc_w = crtc_w;
12795 new_plane_state->crtc_h = crtc_h;
12796
12797 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
12798 to_intel_plane_state(new_plane_state));
12799 if (ret)
12800 goto out_free;
12801
12802 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12803 if (ret)
12804 goto out_free;
12805
12806 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
12807 int align = intel_cursor_alignment(dev_priv);
12808
12809 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
12810 if (ret) {
12811 DRM_DEBUG_KMS("failed to attach phys object\n");
12812 goto out_unlock;
12813 }
12814 } else {
12815 struct i915_vma *vma;
12816
12817 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
12818 if (IS_ERR(vma)) {
12819 DRM_DEBUG_KMS("failed to pin object\n");
12820
12821 ret = PTR_ERR(vma);
12822 goto out_unlock;
12823 }
12824
12825 to_intel_plane_state(new_plane_state)->vma = vma;
12826 }
12827
12828 old_fb = old_plane_state->fb;
12829 old_vma = to_intel_plane_state(old_plane_state)->vma;
12830
12831 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
12832 intel_plane->frontbuffer_bit);
12833
12834 /* Swap plane state */
12835 new_plane_state->fence = old_plane_state->fence;
12836 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
12837 new_plane_state->fence = NULL;
12838 new_plane_state->fb = old_fb;
12839 to_intel_plane_state(new_plane_state)->vma = old_vma;
12840
12841 if (plane->state->visible) {
12842 trace_intel_update_plane(plane, to_intel_crtc(crtc));
12843 intel_plane->update_plane(intel_plane,
12844 to_intel_crtc_state(crtc->state),
12845 to_intel_plane_state(plane->state));
12846 } else {
12847 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
12848 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
12849 }
12850
12851 intel_cleanup_plane_fb(plane, new_plane_state);
12852
12853 out_unlock:
12854 mutex_unlock(&dev_priv->drm.struct_mutex);
12855 out_free:
12856 intel_plane_destroy_state(plane, new_plane_state);
12857 return ret;
12858
12859 slow:
12860 return drm_atomic_helper_update_plane(plane, crtc, fb,
12861 crtc_x, crtc_y, crtc_w, crtc_h,
12862 src_x, src_y, src_w, src_h, ctx);
12863 }
12864
12865 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12866 .update_plane = intel_legacy_cursor_update,
12867 .disable_plane = drm_atomic_helper_disable_plane,
12868 .destroy = intel_plane_destroy,
12869 .set_property = drm_atomic_helper_plane_set_property,
12870 .atomic_get_property = intel_plane_atomic_get_property,
12871 .atomic_set_property = intel_plane_atomic_set_property,
12872 .atomic_duplicate_state = intel_plane_duplicate_state,
12873 .atomic_destroy_state = intel_plane_destroy_state,
12874 };
12875
12876 static struct intel_plane *
12877 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
12878 {
12879 struct intel_plane *primary = NULL;
12880 struct intel_plane_state *state = NULL;
12881 const uint32_t *intel_primary_formats;
12882 unsigned int supported_rotations;
12883 unsigned int num_formats;
12884 int ret;
12885
12886 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12887 if (!primary) {
12888 ret = -ENOMEM;
12889 goto fail;
12890 }
12891
12892 state = intel_create_plane_state(&primary->base);
12893 if (!state) {
12894 ret = -ENOMEM;
12895 goto fail;
12896 }
12897
12898 primary->base.state = &state->base;
12899
12900 primary->can_scale = false;
12901 primary->max_downscale = 1;
12902 if (INTEL_GEN(dev_priv) >= 9) {
12903 primary->can_scale = true;
12904 state->scaler_id = -1;
12905 }
12906 primary->pipe = pipe;
12907 /*
12908 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
12909 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
12910 */
12911 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
12912 primary->plane = (enum plane) !pipe;
12913 else
12914 primary->plane = (enum plane) pipe;
12915 primary->id = PLANE_PRIMARY;
12916 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
12917 primary->check_plane = intel_check_primary_plane;
12918
12919 if (INTEL_GEN(dev_priv) >= 9) {
12920 intel_primary_formats = skl_primary_formats;
12921 num_formats = ARRAY_SIZE(skl_primary_formats);
12922
12923 primary->update_plane = skylake_update_primary_plane;
12924 primary->disable_plane = skylake_disable_primary_plane;
12925 } else if (INTEL_GEN(dev_priv) >= 4) {
12926 intel_primary_formats = i965_primary_formats;
12927 num_formats = ARRAY_SIZE(i965_primary_formats);
12928
12929 primary->update_plane = i9xx_update_primary_plane;
12930 primary->disable_plane = i9xx_disable_primary_plane;
12931 } else {
12932 intel_primary_formats = i8xx_primary_formats;
12933 num_formats = ARRAY_SIZE(i8xx_primary_formats);
12934
12935 primary->update_plane = i9xx_update_primary_plane;
12936 primary->disable_plane = i9xx_disable_primary_plane;
12937 }
12938
12939 if (INTEL_GEN(dev_priv) >= 9)
12940 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12941 0, &intel_plane_funcs,
12942 intel_primary_formats, num_formats,
12943 DRM_PLANE_TYPE_PRIMARY,
12944 "plane 1%c", pipe_name(pipe));
12945 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12946 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12947 0, &intel_plane_funcs,
12948 intel_primary_formats, num_formats,
12949 DRM_PLANE_TYPE_PRIMARY,
12950 "primary %c", pipe_name(pipe));
12951 else
12952 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12953 0, &intel_plane_funcs,
12954 intel_primary_formats, num_formats,
12955 DRM_PLANE_TYPE_PRIMARY,
12956 "plane %c", plane_name(primary->plane));
12957 if (ret)
12958 goto fail;
12959
12960 if (INTEL_GEN(dev_priv) >= 9) {
12961 supported_rotations =
12962 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
12963 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
12964 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
12965 supported_rotations =
12966 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
12967 DRM_MODE_REFLECT_X;
12968 } else if (INTEL_GEN(dev_priv) >= 4) {
12969 supported_rotations =
12970 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
12971 } else {
12972 supported_rotations = DRM_MODE_ROTATE_0;
12973 }
12974
12975 if (INTEL_GEN(dev_priv) >= 4)
12976 drm_plane_create_rotation_property(&primary->base,
12977 DRM_MODE_ROTATE_0,
12978 supported_rotations);
12979
12980 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12981
12982 return primary;
12983
12984 fail:
12985 kfree(state);
12986 kfree(primary);
12987
12988 return ERR_PTR(ret);
12989 }
12990
12991 static struct intel_plane *
12992 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
12993 enum pipe pipe)
12994 {
12995 struct intel_plane *cursor = NULL;
12996 struct intel_plane_state *state = NULL;
12997 int ret;
12998
12999 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13000 if (!cursor) {
13001 ret = -ENOMEM;
13002 goto fail;
13003 }
13004
13005 state = intel_create_plane_state(&cursor->base);
13006 if (!state) {
13007 ret = -ENOMEM;
13008 goto fail;
13009 }
13010
13011 cursor->base.state = &state->base;
13012
13013 cursor->can_scale = false;
13014 cursor->max_downscale = 1;
13015 cursor->pipe = pipe;
13016 cursor->plane = pipe;
13017 cursor->id = PLANE_CURSOR;
13018 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13019
13020 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13021 cursor->update_plane = i845_update_cursor;
13022 cursor->disable_plane = i845_disable_cursor;
13023 cursor->check_plane = i845_check_cursor;
13024 } else {
13025 cursor->update_plane = i9xx_update_cursor;
13026 cursor->disable_plane = i9xx_disable_cursor;
13027 cursor->check_plane = i9xx_check_cursor;
13028 }
13029
13030 cursor->cursor.base = ~0;
13031 cursor->cursor.cntl = ~0;
13032
13033 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13034 cursor->cursor.size = ~0;
13035
13036 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13037 0, &intel_cursor_plane_funcs,
13038 intel_cursor_formats,
13039 ARRAY_SIZE(intel_cursor_formats),
13040 DRM_PLANE_TYPE_CURSOR,
13041 "cursor %c", pipe_name(pipe));
13042 if (ret)
13043 goto fail;
13044
13045 if (INTEL_GEN(dev_priv) >= 4)
13046 drm_plane_create_rotation_property(&cursor->base,
13047 DRM_MODE_ROTATE_0,
13048 DRM_MODE_ROTATE_0 |
13049 DRM_MODE_ROTATE_180);
13050
13051 if (INTEL_GEN(dev_priv) >= 9)
13052 state->scaler_id = -1;
13053
13054 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13055
13056 return cursor;
13057
13058 fail:
13059 kfree(state);
13060 kfree(cursor);
13061
13062 return ERR_PTR(ret);
13063 }
13064
13065 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13066 struct intel_crtc_state *crtc_state)
13067 {
13068 struct intel_crtc_scaler_state *scaler_state =
13069 &crtc_state->scaler_state;
13070 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13071 int i;
13072
13073 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13074 if (!crtc->num_scalers)
13075 return;
13076
13077 for (i = 0; i < crtc->num_scalers; i++) {
13078 struct intel_scaler *scaler = &scaler_state->scalers[i];
13079
13080 scaler->in_use = 0;
13081 scaler->mode = PS_SCALER_MODE_DYN;
13082 }
13083
13084 scaler_state->scaler_id = -1;
13085 }
13086
13087 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13088 {
13089 struct intel_crtc *intel_crtc;
13090 struct intel_crtc_state *crtc_state = NULL;
13091 struct intel_plane *primary = NULL;
13092 struct intel_plane *cursor = NULL;
13093 int sprite, ret;
13094
13095 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13096 if (!intel_crtc)
13097 return -ENOMEM;
13098
13099 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13100 if (!crtc_state) {
13101 ret = -ENOMEM;
13102 goto fail;
13103 }
13104 intel_crtc->config = crtc_state;
13105 intel_crtc->base.state = &crtc_state->base;
13106 crtc_state->base.crtc = &intel_crtc->base;
13107
13108 primary = intel_primary_plane_create(dev_priv, pipe);
13109 if (IS_ERR(primary)) {
13110 ret = PTR_ERR(primary);
13111 goto fail;
13112 }
13113 intel_crtc->plane_ids_mask |= BIT(primary->id);
13114
13115 for_each_sprite(dev_priv, pipe, sprite) {
13116 struct intel_plane *plane;
13117
13118 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13119 if (IS_ERR(plane)) {
13120 ret = PTR_ERR(plane);
13121 goto fail;
13122 }
13123 intel_crtc->plane_ids_mask |= BIT(plane->id);
13124 }
13125
13126 cursor = intel_cursor_plane_create(dev_priv, pipe);
13127 if (IS_ERR(cursor)) {
13128 ret = PTR_ERR(cursor);
13129 goto fail;
13130 }
13131 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13132
13133 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13134 &primary->base, &cursor->base,
13135 &intel_crtc_funcs,
13136 "pipe %c", pipe_name(pipe));
13137 if (ret)
13138 goto fail;
13139
13140 intel_crtc->pipe = pipe;
13141 intel_crtc->plane = primary->plane;
13142
13143 /* initialize shared scalers */
13144 intel_crtc_init_scalers(intel_crtc, crtc_state);
13145
13146 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13147 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13148 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13149 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13150
13151 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13152
13153 intel_color_init(&intel_crtc->base);
13154
13155 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13156
13157 return 0;
13158
13159 fail:
13160 /*
13161 * drm_mode_config_cleanup() will free up any
13162 * crtcs/planes already initialized.
13163 */
13164 kfree(crtc_state);
13165 kfree(intel_crtc);
13166
13167 return ret;
13168 }
13169
13170 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13171 {
13172 struct drm_device *dev = connector->base.dev;
13173
13174 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13175
13176 if (!connector->base.state->crtc)
13177 return INVALID_PIPE;
13178
13179 return to_intel_crtc(connector->base.state->crtc)->pipe;
13180 }
13181
13182 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13183 struct drm_file *file)
13184 {
13185 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13186 struct drm_crtc *drmmode_crtc;
13187 struct intel_crtc *crtc;
13188
13189 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13190 if (!drmmode_crtc)
13191 return -ENOENT;
13192
13193 crtc = to_intel_crtc(drmmode_crtc);
13194 pipe_from_crtc_id->pipe = crtc->pipe;
13195
13196 return 0;
13197 }
13198
13199 static int intel_encoder_clones(struct intel_encoder *encoder)
13200 {
13201 struct drm_device *dev = encoder->base.dev;
13202 struct intel_encoder *source_encoder;
13203 int index_mask = 0;
13204 int entry = 0;
13205
13206 for_each_intel_encoder(dev, source_encoder) {
13207 if (encoders_cloneable(encoder, source_encoder))
13208 index_mask |= (1 << entry);
13209
13210 entry++;
13211 }
13212
13213 return index_mask;
13214 }
13215
13216 static bool has_edp_a(struct drm_i915_private *dev_priv)
13217 {
13218 if (!IS_MOBILE(dev_priv))
13219 return false;
13220
13221 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13222 return false;
13223
13224 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13225 return false;
13226
13227 return true;
13228 }
13229
13230 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13231 {
13232 if (INTEL_GEN(dev_priv) >= 9)
13233 return false;
13234
13235 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13236 return false;
13237
13238 if (IS_CHERRYVIEW(dev_priv))
13239 return false;
13240
13241 if (HAS_PCH_LPT_H(dev_priv) &&
13242 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13243 return false;
13244
13245 /* DDI E can't be used if DDI A requires 4 lanes */
13246 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13247 return false;
13248
13249 if (!dev_priv->vbt.int_crt_support)
13250 return false;
13251
13252 return true;
13253 }
13254
13255 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13256 {
13257 int pps_num;
13258 int pps_idx;
13259
13260 if (HAS_DDI(dev_priv))
13261 return;
13262 /*
13263 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13264 * everywhere where registers can be write protected.
13265 */
13266 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13267 pps_num = 2;
13268 else
13269 pps_num = 1;
13270
13271 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13272 u32 val = I915_READ(PP_CONTROL(pps_idx));
13273
13274 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13275 I915_WRITE(PP_CONTROL(pps_idx), val);
13276 }
13277 }
13278
13279 static void intel_pps_init(struct drm_i915_private *dev_priv)
13280 {
13281 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13282 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13283 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13284 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13285 else
13286 dev_priv->pps_mmio_base = PPS_BASE;
13287
13288 intel_pps_unlock_regs_wa(dev_priv);
13289 }
13290
13291 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13292 {
13293 struct intel_encoder *encoder;
13294 bool dpd_is_edp = false;
13295
13296 intel_pps_init(dev_priv);
13297
13298 /*
13299 * intel_edp_init_connector() depends on this completing first, to
13300 * prevent the registeration of both eDP and LVDS and the incorrect
13301 * sharing of the PPS.
13302 */
13303 intel_lvds_init(dev_priv);
13304
13305 if (intel_crt_present(dev_priv))
13306 intel_crt_init(dev_priv);
13307
13308 if (IS_GEN9_LP(dev_priv)) {
13309 /*
13310 * FIXME: Broxton doesn't support port detection via the
13311 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13312 * detect the ports.
13313 */
13314 intel_ddi_init(dev_priv, PORT_A);
13315 intel_ddi_init(dev_priv, PORT_B);
13316 intel_ddi_init(dev_priv, PORT_C);
13317
13318 intel_dsi_init(dev_priv);
13319 } else if (HAS_DDI(dev_priv)) {
13320 int found;
13321
13322 /*
13323 * Haswell uses DDI functions to detect digital outputs.
13324 * On SKL pre-D0 the strap isn't connected, so we assume
13325 * it's there.
13326 */
13327 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13328 /* WaIgnoreDDIAStrap: skl */
13329 if (found || IS_GEN9_BC(dev_priv))
13330 intel_ddi_init(dev_priv, PORT_A);
13331
13332 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13333 * register */
13334 found = I915_READ(SFUSE_STRAP);
13335
13336 if (found & SFUSE_STRAP_DDIB_DETECTED)
13337 intel_ddi_init(dev_priv, PORT_B);
13338 if (found & SFUSE_STRAP_DDIC_DETECTED)
13339 intel_ddi_init(dev_priv, PORT_C);
13340 if (found & SFUSE_STRAP_DDID_DETECTED)
13341 intel_ddi_init(dev_priv, PORT_D);
13342 /*
13343 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13344 */
13345 if (IS_GEN9_BC(dev_priv) &&
13346 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13347 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13348 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13349 intel_ddi_init(dev_priv, PORT_E);
13350
13351 } else if (HAS_PCH_SPLIT(dev_priv)) {
13352 int found;
13353 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
13354
13355 if (has_edp_a(dev_priv))
13356 intel_dp_init(dev_priv, DP_A, PORT_A);
13357
13358 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13359 /* PCH SDVOB multiplex with HDMIB */
13360 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13361 if (!found)
13362 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13363 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13364 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13365 }
13366
13367 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13368 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13369
13370 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13371 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13372
13373 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13374 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13375
13376 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13377 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13378 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13379 bool has_edp, has_port;
13380
13381 /*
13382 * The DP_DETECTED bit is the latched state of the DDC
13383 * SDA pin at boot. However since eDP doesn't require DDC
13384 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13385 * eDP ports may have been muxed to an alternate function.
13386 * Thus we can't rely on the DP_DETECTED bit alone to detect
13387 * eDP ports. Consult the VBT as well as DP_DETECTED to
13388 * detect eDP ports.
13389 *
13390 * Sadly the straps seem to be missing sometimes even for HDMI
13391 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13392 * and VBT for the presence of the port. Additionally we can't
13393 * trust the port type the VBT declares as we've seen at least
13394 * HDMI ports that the VBT claim are DP or eDP.
13395 */
13396 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
13397 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13398 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13399 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13400 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13401 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13402
13403 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
13404 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13405 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13406 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13407 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13408 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13409
13410 if (IS_CHERRYVIEW(dev_priv)) {
13411 /*
13412 * eDP not supported on port D,
13413 * so no need to worry about it
13414 */
13415 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13416 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13417 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13418 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13419 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13420 }
13421
13422 intel_dsi_init(dev_priv);
13423 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13424 bool found = false;
13425
13426 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13427 DRM_DEBUG_KMS("probing SDVOB\n");
13428 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13429 if (!found && IS_G4X(dev_priv)) {
13430 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13431 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13432 }
13433
13434 if (!found && IS_G4X(dev_priv))
13435 intel_dp_init(dev_priv, DP_B, PORT_B);
13436 }
13437
13438 /* Before G4X SDVOC doesn't have its own detect register */
13439
13440 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13441 DRM_DEBUG_KMS("probing SDVOC\n");
13442 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13443 }
13444
13445 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13446
13447 if (IS_G4X(dev_priv)) {
13448 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13449 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13450 }
13451 if (IS_G4X(dev_priv))
13452 intel_dp_init(dev_priv, DP_C, PORT_C);
13453 }
13454
13455 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13456 intel_dp_init(dev_priv, DP_D, PORT_D);
13457 } else if (IS_GEN2(dev_priv))
13458 intel_dvo_init(dev_priv);
13459
13460 if (SUPPORTS_TV(dev_priv))
13461 intel_tv_init(dev_priv);
13462
13463 intel_psr_init(dev_priv);
13464
13465 for_each_intel_encoder(&dev_priv->drm, encoder) {
13466 encoder->base.possible_crtcs = encoder->crtc_mask;
13467 encoder->base.possible_clones =
13468 intel_encoder_clones(encoder);
13469 }
13470
13471 intel_init_pch_refclk(dev_priv);
13472
13473 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13474 }
13475
13476 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13477 {
13478 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13479
13480 drm_framebuffer_cleanup(fb);
13481
13482 i915_gem_object_lock(intel_fb->obj);
13483 WARN_ON(!intel_fb->obj->framebuffer_references--);
13484 i915_gem_object_unlock(intel_fb->obj);
13485
13486 i915_gem_object_put(intel_fb->obj);
13487
13488 kfree(intel_fb);
13489 }
13490
13491 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13492 struct drm_file *file,
13493 unsigned int *handle)
13494 {
13495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13496 struct drm_i915_gem_object *obj = intel_fb->obj;
13497
13498 if (obj->userptr.mm) {
13499 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13500 return -EINVAL;
13501 }
13502
13503 return drm_gem_handle_create(file, &obj->base, handle);
13504 }
13505
13506 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13507 struct drm_file *file,
13508 unsigned flags, unsigned color,
13509 struct drm_clip_rect *clips,
13510 unsigned num_clips)
13511 {
13512 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13513
13514 i915_gem_object_flush_if_display(obj);
13515 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13516
13517 return 0;
13518 }
13519
13520 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13521 .destroy = intel_user_framebuffer_destroy,
13522 .create_handle = intel_user_framebuffer_create_handle,
13523 .dirty = intel_user_framebuffer_dirty,
13524 };
13525
13526 static
13527 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13528 uint64_t fb_modifier, uint32_t pixel_format)
13529 {
13530 u32 gen = INTEL_GEN(dev_priv);
13531
13532 if (gen >= 9) {
13533 int cpp = drm_format_plane_cpp(pixel_format, 0);
13534
13535 /* "The stride in bytes must not exceed the of the size of 8K
13536 * pixels and 32K bytes."
13537 */
13538 return min(8192 * cpp, 32768);
13539 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13540 return 32*1024;
13541 } else if (gen >= 4) {
13542 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13543 return 16*1024;
13544 else
13545 return 32*1024;
13546 } else if (gen >= 3) {
13547 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13548 return 8*1024;
13549 else
13550 return 16*1024;
13551 } else {
13552 /* XXX DSPC is limited to 4k tiled */
13553 return 8*1024;
13554 }
13555 }
13556
13557 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13558 struct drm_i915_gem_object *obj,
13559 struct drm_mode_fb_cmd2 *mode_cmd)
13560 {
13561 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13562 struct drm_format_name_buf format_name;
13563 u32 pitch_limit, stride_alignment;
13564 unsigned int tiling, stride;
13565 int ret = -EINVAL;
13566
13567 i915_gem_object_lock(obj);
13568 obj->framebuffer_references++;
13569 tiling = i915_gem_object_get_tiling(obj);
13570 stride = i915_gem_object_get_stride(obj);
13571 i915_gem_object_unlock(obj);
13572
13573 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13574 /*
13575 * If there's a fence, enforce that
13576 * the fb modifier and tiling mode match.
13577 */
13578 if (tiling != I915_TILING_NONE &&
13579 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13580 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13581 goto err;
13582 }
13583 } else {
13584 if (tiling == I915_TILING_X) {
13585 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13586 } else if (tiling == I915_TILING_Y) {
13587 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13588 goto err;
13589 }
13590 }
13591
13592 /* Passed in modifier sanity checking. */
13593 switch (mode_cmd->modifier[0]) {
13594 case I915_FORMAT_MOD_Y_TILED:
13595 case I915_FORMAT_MOD_Yf_TILED:
13596 if (INTEL_GEN(dev_priv) < 9) {
13597 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13598 mode_cmd->modifier[0]);
13599 goto err;
13600 }
13601 case DRM_FORMAT_MOD_LINEAR:
13602 case I915_FORMAT_MOD_X_TILED:
13603 break;
13604 default:
13605 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13606 mode_cmd->modifier[0]);
13607 goto err;
13608 }
13609
13610 /*
13611 * gen2/3 display engine uses the fence if present,
13612 * so the tiling mode must match the fb modifier exactly.
13613 */
13614 if (INTEL_INFO(dev_priv)->gen < 4 &&
13615 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13616 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13617 goto err;
13618 }
13619
13620 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13621 mode_cmd->pixel_format);
13622 if (mode_cmd->pitches[0] > pitch_limit) {
13623 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13624 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13625 "tiled" : "linear",
13626 mode_cmd->pitches[0], pitch_limit);
13627 goto err;
13628 }
13629
13630 /*
13631 * If there's a fence, enforce that
13632 * the fb pitch and fence stride match.
13633 */
13634 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13635 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13636 mode_cmd->pitches[0], stride);
13637 goto err;
13638 }
13639
13640 /* Reject formats not supported by any plane early. */
13641 switch (mode_cmd->pixel_format) {
13642 case DRM_FORMAT_C8:
13643 case DRM_FORMAT_RGB565:
13644 case DRM_FORMAT_XRGB8888:
13645 case DRM_FORMAT_ARGB8888:
13646 break;
13647 case DRM_FORMAT_XRGB1555:
13648 if (INTEL_GEN(dev_priv) > 3) {
13649 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13650 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13651 goto err;
13652 }
13653 break;
13654 case DRM_FORMAT_ABGR8888:
13655 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13656 INTEL_GEN(dev_priv) < 9) {
13657 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13658 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13659 goto err;
13660 }
13661 break;
13662 case DRM_FORMAT_XBGR8888:
13663 case DRM_FORMAT_XRGB2101010:
13664 case DRM_FORMAT_XBGR2101010:
13665 if (INTEL_GEN(dev_priv) < 4) {
13666 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13667 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13668 goto err;
13669 }
13670 break;
13671 case DRM_FORMAT_ABGR2101010:
13672 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13673 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13674 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13675 goto err;
13676 }
13677 break;
13678 case DRM_FORMAT_YUYV:
13679 case DRM_FORMAT_UYVY:
13680 case DRM_FORMAT_YVYU:
13681 case DRM_FORMAT_VYUY:
13682 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13683 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13684 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13685 goto err;
13686 }
13687 break;
13688 default:
13689 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13690 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13691 goto err;
13692 }
13693
13694 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13695 if (mode_cmd->offsets[0] != 0)
13696 goto err;
13697
13698 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
13699 &intel_fb->base, mode_cmd);
13700
13701 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
13702 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13703 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
13704 mode_cmd->pitches[0], stride_alignment);
13705 goto err;
13706 }
13707
13708 intel_fb->obj = obj;
13709
13710 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
13711 if (ret)
13712 goto err;
13713
13714 ret = drm_framebuffer_init(obj->base.dev,
13715 &intel_fb->base,
13716 &intel_fb_funcs);
13717 if (ret) {
13718 DRM_ERROR("framebuffer init failed %d\n", ret);
13719 goto err;
13720 }
13721
13722 return 0;
13723
13724 err:
13725 i915_gem_object_lock(obj);
13726 obj->framebuffer_references--;
13727 i915_gem_object_unlock(obj);
13728 return ret;
13729 }
13730
13731 static struct drm_framebuffer *
13732 intel_user_framebuffer_create(struct drm_device *dev,
13733 struct drm_file *filp,
13734 const struct drm_mode_fb_cmd2 *user_mode_cmd)
13735 {
13736 struct drm_framebuffer *fb;
13737 struct drm_i915_gem_object *obj;
13738 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
13739
13740 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
13741 if (!obj)
13742 return ERR_PTR(-ENOENT);
13743
13744 fb = intel_framebuffer_create(obj, &mode_cmd);
13745 if (IS_ERR(fb))
13746 i915_gem_object_put(obj);
13747
13748 return fb;
13749 }
13750
13751 static void intel_atomic_state_free(struct drm_atomic_state *state)
13752 {
13753 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13754
13755 drm_atomic_state_default_release(state);
13756
13757 i915_sw_fence_fini(&intel_state->commit_ready);
13758
13759 kfree(state);
13760 }
13761
13762 static const struct drm_mode_config_funcs intel_mode_funcs = {
13763 .fb_create = intel_user_framebuffer_create,
13764 .output_poll_changed = intel_fbdev_output_poll_changed,
13765 .atomic_check = intel_atomic_check,
13766 .atomic_commit = intel_atomic_commit,
13767 .atomic_state_alloc = intel_atomic_state_alloc,
13768 .atomic_state_clear = intel_atomic_state_clear,
13769 .atomic_state_free = intel_atomic_state_free,
13770 };
13771
13772 /**
13773 * intel_init_display_hooks - initialize the display modesetting hooks
13774 * @dev_priv: device private
13775 */
13776 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
13777 {
13778 intel_init_cdclk_hooks(dev_priv);
13779
13780 if (INTEL_INFO(dev_priv)->gen >= 9) {
13781 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13782 dev_priv->display.get_initial_plane_config =
13783 skylake_get_initial_plane_config;
13784 dev_priv->display.crtc_compute_clock =
13785 haswell_crtc_compute_clock;
13786 dev_priv->display.crtc_enable = haswell_crtc_enable;
13787 dev_priv->display.crtc_disable = haswell_crtc_disable;
13788 } else if (HAS_DDI(dev_priv)) {
13789 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13790 dev_priv->display.get_initial_plane_config =
13791 ironlake_get_initial_plane_config;
13792 dev_priv->display.crtc_compute_clock =
13793 haswell_crtc_compute_clock;
13794 dev_priv->display.crtc_enable = haswell_crtc_enable;
13795 dev_priv->display.crtc_disable = haswell_crtc_disable;
13796 } else if (HAS_PCH_SPLIT(dev_priv)) {
13797 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13798 dev_priv->display.get_initial_plane_config =
13799 ironlake_get_initial_plane_config;
13800 dev_priv->display.crtc_compute_clock =
13801 ironlake_crtc_compute_clock;
13802 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13803 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13804 } else if (IS_CHERRYVIEW(dev_priv)) {
13805 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13806 dev_priv->display.get_initial_plane_config =
13807 i9xx_get_initial_plane_config;
13808 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
13809 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13810 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13811 } else if (IS_VALLEYVIEW(dev_priv)) {
13812 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13813 dev_priv->display.get_initial_plane_config =
13814 i9xx_get_initial_plane_config;
13815 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
13816 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13817 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13818 } else if (IS_G4X(dev_priv)) {
13819 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13820 dev_priv->display.get_initial_plane_config =
13821 i9xx_get_initial_plane_config;
13822 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
13823 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13824 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13825 } else if (IS_PINEVIEW(dev_priv)) {
13826 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13827 dev_priv->display.get_initial_plane_config =
13828 i9xx_get_initial_plane_config;
13829 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
13830 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13831 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13832 } else if (!IS_GEN2(dev_priv)) {
13833 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13834 dev_priv->display.get_initial_plane_config =
13835 i9xx_get_initial_plane_config;
13836 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13837 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13838 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13839 } else {
13840 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13841 dev_priv->display.get_initial_plane_config =
13842 i9xx_get_initial_plane_config;
13843 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
13844 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13845 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13846 }
13847
13848 if (IS_GEN5(dev_priv)) {
13849 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13850 } else if (IS_GEN6(dev_priv)) {
13851 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13852 } else if (IS_IVYBRIDGE(dev_priv)) {
13853 /* FIXME: detect B0+ stepping and use auto training */
13854 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13855 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
13856 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13857 }
13858
13859 if (dev_priv->info.gen >= 9)
13860 dev_priv->display.update_crtcs = skl_update_crtcs;
13861 else
13862 dev_priv->display.update_crtcs = intel_update_crtcs;
13863 }
13864
13865 /*
13866 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13867 */
13868 static void quirk_ssc_force_disable(struct drm_device *dev)
13869 {
13870 struct drm_i915_private *dev_priv = to_i915(dev);
13871 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13872 DRM_INFO("applying lvds SSC disable quirk\n");
13873 }
13874
13875 /*
13876 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13877 * brightness value
13878 */
13879 static void quirk_invert_brightness(struct drm_device *dev)
13880 {
13881 struct drm_i915_private *dev_priv = to_i915(dev);
13882 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13883 DRM_INFO("applying inverted panel brightness quirk\n");
13884 }
13885
13886 /* Some VBT's incorrectly indicate no backlight is present */
13887 static void quirk_backlight_present(struct drm_device *dev)
13888 {
13889 struct drm_i915_private *dev_priv = to_i915(dev);
13890 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13891 DRM_INFO("applying backlight present quirk\n");
13892 }
13893
13894 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
13895 * which is 300 ms greater than eDP spec T12 min.
13896 */
13897 static void quirk_increase_t12_delay(struct drm_device *dev)
13898 {
13899 struct drm_i915_private *dev_priv = to_i915(dev);
13900
13901 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
13902 DRM_INFO("Applying T12 delay quirk\n");
13903 }
13904
13905 struct intel_quirk {
13906 int device;
13907 int subsystem_vendor;
13908 int subsystem_device;
13909 void (*hook)(struct drm_device *dev);
13910 };
13911
13912 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13913 struct intel_dmi_quirk {
13914 void (*hook)(struct drm_device *dev);
13915 const struct dmi_system_id (*dmi_id_list)[];
13916 };
13917
13918 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13919 {
13920 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13921 return 1;
13922 }
13923
13924 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13925 {
13926 .dmi_id_list = &(const struct dmi_system_id[]) {
13927 {
13928 .callback = intel_dmi_reverse_brightness,
13929 .ident = "NCR Corporation",
13930 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13931 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13932 },
13933 },
13934 { } /* terminating entry */
13935 },
13936 .hook = quirk_invert_brightness,
13937 },
13938 };
13939
13940 static struct intel_quirk intel_quirks[] = {
13941 /* Lenovo U160 cannot use SSC on LVDS */
13942 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13943
13944 /* Sony Vaio Y cannot use SSC on LVDS */
13945 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13946
13947 /* Acer Aspire 5734Z must invert backlight brightness */
13948 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13949
13950 /* Acer/eMachines G725 */
13951 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13952
13953 /* Acer/eMachines e725 */
13954 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13955
13956 /* Acer/Packard Bell NCL20 */
13957 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13958
13959 /* Acer Aspire 4736Z */
13960 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13961
13962 /* Acer Aspire 5336 */
13963 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13964
13965 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13966 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13967
13968 /* Acer C720 Chromebook (Core i3 4005U) */
13969 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13970
13971 /* Apple Macbook 2,1 (Core 2 T7400) */
13972 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13973
13974 /* Apple Macbook 4,1 */
13975 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
13976
13977 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13978 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13979
13980 /* HP Chromebook 14 (Celeron 2955U) */
13981 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13982
13983 /* Dell Chromebook 11 */
13984 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13985
13986 /* Dell Chromebook 11 (2015 version) */
13987 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
13988
13989 /* Toshiba Satellite P50-C-18C */
13990 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
13991 };
13992
13993 static void intel_init_quirks(struct drm_device *dev)
13994 {
13995 struct pci_dev *d = dev->pdev;
13996 int i;
13997
13998 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13999 struct intel_quirk *q = &intel_quirks[i];
14000
14001 if (d->device == q->device &&
14002 (d->subsystem_vendor == q->subsystem_vendor ||
14003 q->subsystem_vendor == PCI_ANY_ID) &&
14004 (d->subsystem_device == q->subsystem_device ||
14005 q->subsystem_device == PCI_ANY_ID))
14006 q->hook(dev);
14007 }
14008 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14009 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14010 intel_dmi_quirks[i].hook(dev);
14011 }
14012 }
14013
14014 /* Disable the VGA plane that we never use */
14015 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14016 {
14017 struct pci_dev *pdev = dev_priv->drm.pdev;
14018 u8 sr1;
14019 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14020
14021 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14022 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14023 outb(SR01, VGA_SR_INDEX);
14024 sr1 = inb(VGA_SR_DATA);
14025 outb(sr1 | 1<<5, VGA_SR_DATA);
14026 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14027 udelay(300);
14028
14029 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14030 POSTING_READ(vga_reg);
14031 }
14032
14033 void intel_modeset_init_hw(struct drm_device *dev)
14034 {
14035 struct drm_i915_private *dev_priv = to_i915(dev);
14036
14037 intel_update_cdclk(dev_priv);
14038 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14039
14040 intel_init_clock_gating(dev_priv);
14041 }
14042
14043 /*
14044 * Calculate what we think the watermarks should be for the state we've read
14045 * out of the hardware and then immediately program those watermarks so that
14046 * we ensure the hardware settings match our internal state.
14047 *
14048 * We can calculate what we think WM's should be by creating a duplicate of the
14049 * current state (which was constructed during hardware readout) and running it
14050 * through the atomic check code to calculate new watermark values in the
14051 * state object.
14052 */
14053 static void sanitize_watermarks(struct drm_device *dev)
14054 {
14055 struct drm_i915_private *dev_priv = to_i915(dev);
14056 struct drm_atomic_state *state;
14057 struct intel_atomic_state *intel_state;
14058 struct drm_crtc *crtc;
14059 struct drm_crtc_state *cstate;
14060 struct drm_modeset_acquire_ctx ctx;
14061 int ret;
14062 int i;
14063
14064 /* Only supported on platforms that use atomic watermark design */
14065 if (!dev_priv->display.optimize_watermarks)
14066 return;
14067
14068 /*
14069 * We need to hold connection_mutex before calling duplicate_state so
14070 * that the connector loop is protected.
14071 */
14072 drm_modeset_acquire_init(&ctx, 0);
14073 retry:
14074 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14075 if (ret == -EDEADLK) {
14076 drm_modeset_backoff(&ctx);
14077 goto retry;
14078 } else if (WARN_ON(ret)) {
14079 goto fail;
14080 }
14081
14082 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14083 if (WARN_ON(IS_ERR(state)))
14084 goto fail;
14085
14086 intel_state = to_intel_atomic_state(state);
14087
14088 /*
14089 * Hardware readout is the only time we don't want to calculate
14090 * intermediate watermarks (since we don't trust the current
14091 * watermarks).
14092 */
14093 if (!HAS_GMCH_DISPLAY(dev_priv))
14094 intel_state->skip_intermediate_wm = true;
14095
14096 ret = intel_atomic_check(dev, state);
14097 if (ret) {
14098 /*
14099 * If we fail here, it means that the hardware appears to be
14100 * programmed in a way that shouldn't be possible, given our
14101 * understanding of watermark requirements. This might mean a
14102 * mistake in the hardware readout code or a mistake in the
14103 * watermark calculations for a given platform. Raise a WARN
14104 * so that this is noticeable.
14105 *
14106 * If this actually happens, we'll have to just leave the
14107 * BIOS-programmed watermarks untouched and hope for the best.
14108 */
14109 WARN(true, "Could not determine valid watermarks for inherited state\n");
14110 goto put_state;
14111 }
14112
14113 /* Write calculated watermark values back */
14114 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14115 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14116
14117 cs->wm.need_postvbl_update = true;
14118 dev_priv->display.optimize_watermarks(intel_state, cs);
14119 }
14120
14121 put_state:
14122 drm_atomic_state_put(state);
14123 fail:
14124 drm_modeset_drop_locks(&ctx);
14125 drm_modeset_acquire_fini(&ctx);
14126 }
14127
14128 int intel_modeset_init(struct drm_device *dev)
14129 {
14130 struct drm_i915_private *dev_priv = to_i915(dev);
14131 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14132 enum pipe pipe;
14133 struct intel_crtc *crtc;
14134
14135 drm_mode_config_init(dev);
14136
14137 dev->mode_config.min_width = 0;
14138 dev->mode_config.min_height = 0;
14139
14140 dev->mode_config.preferred_depth = 24;
14141 dev->mode_config.prefer_shadow = 1;
14142
14143 dev->mode_config.allow_fb_modifiers = true;
14144
14145 dev->mode_config.funcs = &intel_mode_funcs;
14146
14147 init_llist_head(&dev_priv->atomic_helper.free_list);
14148 INIT_WORK(&dev_priv->atomic_helper.free_work,
14149 intel_atomic_helper_free_state_worker);
14150
14151 intel_init_quirks(dev);
14152
14153 intel_init_pm(dev_priv);
14154
14155 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14156 return 0;
14157
14158 /*
14159 * There may be no VBT; and if the BIOS enabled SSC we can
14160 * just keep using it to avoid unnecessary flicker. Whereas if the
14161 * BIOS isn't using it, don't assume it will work even if the VBT
14162 * indicates as much.
14163 */
14164 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14165 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14166 DREF_SSC1_ENABLE);
14167
14168 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14169 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14170 bios_lvds_use_ssc ? "en" : "dis",
14171 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14172 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14173 }
14174 }
14175
14176 if (IS_GEN2(dev_priv)) {
14177 dev->mode_config.max_width = 2048;
14178 dev->mode_config.max_height = 2048;
14179 } else if (IS_GEN3(dev_priv)) {
14180 dev->mode_config.max_width = 4096;
14181 dev->mode_config.max_height = 4096;
14182 } else {
14183 dev->mode_config.max_width = 8192;
14184 dev->mode_config.max_height = 8192;
14185 }
14186
14187 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14188 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14189 dev->mode_config.cursor_height = 1023;
14190 } else if (IS_GEN2(dev_priv)) {
14191 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14192 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14193 } else {
14194 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14195 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14196 }
14197
14198 dev->mode_config.fb_base = ggtt->mappable_base;
14199
14200 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14201 INTEL_INFO(dev_priv)->num_pipes,
14202 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14203
14204 for_each_pipe(dev_priv, pipe) {
14205 int ret;
14206
14207 ret = intel_crtc_init(dev_priv, pipe);
14208 if (ret) {
14209 drm_mode_config_cleanup(dev);
14210 return ret;
14211 }
14212 }
14213
14214 intel_shared_dpll_init(dev);
14215
14216 intel_update_czclk(dev_priv);
14217 intel_modeset_init_hw(dev);
14218
14219 if (dev_priv->max_cdclk_freq == 0)
14220 intel_update_max_cdclk(dev_priv);
14221
14222 /* Just disable it once at startup */
14223 i915_disable_vga(dev_priv);
14224 intel_setup_outputs(dev_priv);
14225
14226 drm_modeset_lock_all(dev);
14227 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14228 drm_modeset_unlock_all(dev);
14229
14230 for_each_intel_crtc(dev, crtc) {
14231 struct intel_initial_plane_config plane_config = {};
14232
14233 if (!crtc->active)
14234 continue;
14235
14236 /*
14237 * Note that reserving the BIOS fb up front prevents us
14238 * from stuffing other stolen allocations like the ring
14239 * on top. This prevents some ugliness at boot time, and
14240 * can even allow for smooth boot transitions if the BIOS
14241 * fb is large enough for the active pipe configuration.
14242 */
14243 dev_priv->display.get_initial_plane_config(crtc,
14244 &plane_config);
14245
14246 /*
14247 * If the fb is shared between multiple heads, we'll
14248 * just get the first one.
14249 */
14250 intel_find_initial_plane_obj(crtc, &plane_config);
14251 }
14252
14253 /*
14254 * Make sure hardware watermarks really match the state we read out.
14255 * Note that we need to do this after reconstructing the BIOS fb's
14256 * since the watermark calculation done here will use pstate->fb.
14257 */
14258 if (!HAS_GMCH_DISPLAY(dev_priv))
14259 sanitize_watermarks(dev);
14260
14261 return 0;
14262 }
14263
14264 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14265 {
14266 /* 640x480@60Hz, ~25175 kHz */
14267 struct dpll clock = {
14268 .m1 = 18,
14269 .m2 = 7,
14270 .p1 = 13,
14271 .p2 = 4,
14272 .n = 2,
14273 };
14274 u32 dpll, fp;
14275 int i;
14276
14277 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14278
14279 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14280 pipe_name(pipe), clock.vco, clock.dot);
14281
14282 fp = i9xx_dpll_compute_fp(&clock);
14283 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14284 DPLL_VGA_MODE_DIS |
14285 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14286 PLL_P2_DIVIDE_BY_4 |
14287 PLL_REF_INPUT_DREFCLK |
14288 DPLL_VCO_ENABLE;
14289
14290 I915_WRITE(FP0(pipe), fp);
14291 I915_WRITE(FP1(pipe), fp);
14292
14293 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14294 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14295 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14296 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14297 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14298 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14299 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14300
14301 /*
14302 * Apparently we need to have VGA mode enabled prior to changing
14303 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14304 * dividers, even though the register value does change.
14305 */
14306 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14307 I915_WRITE(DPLL(pipe), dpll);
14308
14309 /* Wait for the clocks to stabilize. */
14310 POSTING_READ(DPLL(pipe));
14311 udelay(150);
14312
14313 /* The pixel multiplier can only be updated once the
14314 * DPLL is enabled and the clocks are stable.
14315 *
14316 * So write it again.
14317 */
14318 I915_WRITE(DPLL(pipe), dpll);
14319
14320 /* We do this three times for luck */
14321 for (i = 0; i < 3 ; i++) {
14322 I915_WRITE(DPLL(pipe), dpll);
14323 POSTING_READ(DPLL(pipe));
14324 udelay(150); /* wait for warmup */
14325 }
14326
14327 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14328 POSTING_READ(PIPECONF(pipe));
14329 }
14330
14331 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14332 {
14333 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14334 pipe_name(pipe));
14335
14336 assert_plane_disabled(dev_priv, PLANE_A);
14337 assert_plane_disabled(dev_priv, PLANE_B);
14338
14339 I915_WRITE(PIPECONF(pipe), 0);
14340 POSTING_READ(PIPECONF(pipe));
14341
14342 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14343 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14344
14345 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14346 POSTING_READ(DPLL(pipe));
14347 }
14348
14349 static bool
14350 intel_check_plane_mapping(struct intel_crtc *crtc)
14351 {
14352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14353 u32 val;
14354
14355 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14356 return true;
14357
14358 val = I915_READ(DSPCNTR(!crtc->plane));
14359
14360 if ((val & DISPLAY_PLANE_ENABLE) &&
14361 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14362 return false;
14363
14364 return true;
14365 }
14366
14367 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14368 {
14369 struct drm_device *dev = crtc->base.dev;
14370 struct intel_encoder *encoder;
14371
14372 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14373 return true;
14374
14375 return false;
14376 }
14377
14378 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14379 {
14380 struct drm_device *dev = encoder->base.dev;
14381 struct intel_connector *connector;
14382
14383 for_each_connector_on_encoder(dev, &encoder->base, connector)
14384 return connector;
14385
14386 return NULL;
14387 }
14388
14389 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14390 enum transcoder pch_transcoder)
14391 {
14392 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14393 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14394 }
14395
14396 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14397 struct drm_modeset_acquire_ctx *ctx)
14398 {
14399 struct drm_device *dev = crtc->base.dev;
14400 struct drm_i915_private *dev_priv = to_i915(dev);
14401 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14402
14403 /* Clear any frame start delays used for debugging left by the BIOS */
14404 if (!transcoder_is_dsi(cpu_transcoder)) {
14405 i915_reg_t reg = PIPECONF(cpu_transcoder);
14406
14407 I915_WRITE(reg,
14408 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14409 }
14410
14411 /* restore vblank interrupts to correct state */
14412 drm_crtc_vblank_reset(&crtc->base);
14413 if (crtc->active) {
14414 struct intel_plane *plane;
14415
14416 drm_crtc_vblank_on(&crtc->base);
14417
14418 /* Disable everything but the primary plane */
14419 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14420 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14421 continue;
14422
14423 trace_intel_disable_plane(&plane->base, crtc);
14424 plane->disable_plane(plane, crtc);
14425 }
14426 }
14427
14428 /* We need to sanitize the plane -> pipe mapping first because this will
14429 * disable the crtc (and hence change the state) if it is wrong. Note
14430 * that gen4+ has a fixed plane -> pipe mapping. */
14431 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14432 bool plane;
14433
14434 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14435 crtc->base.base.id, crtc->base.name);
14436
14437 /* Pipe has the wrong plane attached and the plane is active.
14438 * Temporarily change the plane mapping and disable everything
14439 * ... */
14440 plane = crtc->plane;
14441 crtc->base.primary->state->visible = true;
14442 crtc->plane = !plane;
14443 intel_crtc_disable_noatomic(&crtc->base, ctx);
14444 crtc->plane = plane;
14445 }
14446
14447 /* Adjust the state of the output pipe according to whether we
14448 * have active connectors/encoders. */
14449 if (crtc->active && !intel_crtc_has_encoders(crtc))
14450 intel_crtc_disable_noatomic(&crtc->base, ctx);
14451
14452 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14453 /*
14454 * We start out with underrun reporting disabled to avoid races.
14455 * For correct bookkeeping mark this on active crtcs.
14456 *
14457 * Also on gmch platforms we dont have any hardware bits to
14458 * disable the underrun reporting. Which means we need to start
14459 * out with underrun reporting disabled also on inactive pipes,
14460 * since otherwise we'll complain about the garbage we read when
14461 * e.g. coming up after runtime pm.
14462 *
14463 * No protection against concurrent access is required - at
14464 * worst a fifo underrun happens which also sets this to false.
14465 */
14466 crtc->cpu_fifo_underrun_disabled = true;
14467 /*
14468 * We track the PCH trancoder underrun reporting state
14469 * within the crtc. With crtc for pipe A housing the underrun
14470 * reporting state for PCH transcoder A, crtc for pipe B housing
14471 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14472 * and marking underrun reporting as disabled for the non-existing
14473 * PCH transcoders B and C would prevent enabling the south
14474 * error interrupt (see cpt_can_enable_serr_int()).
14475 */
14476 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14477 crtc->pch_fifo_underrun_disabled = true;
14478 }
14479 }
14480
14481 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14482 {
14483 struct intel_connector *connector;
14484
14485 /* We need to check both for a crtc link (meaning that the
14486 * encoder is active and trying to read from a pipe) and the
14487 * pipe itself being active. */
14488 bool has_active_crtc = encoder->base.crtc &&
14489 to_intel_crtc(encoder->base.crtc)->active;
14490
14491 connector = intel_encoder_find_connector(encoder);
14492 if (connector && !has_active_crtc) {
14493 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14494 encoder->base.base.id,
14495 encoder->base.name);
14496
14497 /* Connector is active, but has no active pipe. This is
14498 * fallout from our resume register restoring. Disable
14499 * the encoder manually again. */
14500 if (encoder->base.crtc) {
14501 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14502
14503 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14504 encoder->base.base.id,
14505 encoder->base.name);
14506 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14507 if (encoder->post_disable)
14508 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14509 }
14510 encoder->base.crtc = NULL;
14511
14512 /* Inconsistent output/port/pipe state happens presumably due to
14513 * a bug in one of the get_hw_state functions. Or someplace else
14514 * in our code, like the register restore mess on resume. Clamp
14515 * things to off as a safer default. */
14516
14517 connector->base.dpms = DRM_MODE_DPMS_OFF;
14518 connector->base.encoder = NULL;
14519 }
14520 /* Enabled encoders without active connectors will be fixed in
14521 * the crtc fixup. */
14522 }
14523
14524 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14525 {
14526 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14527
14528 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14529 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14530 i915_disable_vga(dev_priv);
14531 }
14532 }
14533
14534 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14535 {
14536 /* This function can be called both from intel_modeset_setup_hw_state or
14537 * at a very early point in our resume sequence, where the power well
14538 * structures are not yet restored. Since this function is at a very
14539 * paranoid "someone might have enabled VGA while we were not looking"
14540 * level, just check if the power well is enabled instead of trying to
14541 * follow the "don't touch the power well if we don't need it" policy
14542 * the rest of the driver uses. */
14543 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14544 return;
14545
14546 i915_redisable_vga_power_on(dev_priv);
14547
14548 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14549 }
14550
14551 static bool primary_get_hw_state(struct intel_plane *plane)
14552 {
14553 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14554
14555 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14556 }
14557
14558 /* FIXME read out full plane state for all planes */
14559 static void readout_plane_state(struct intel_crtc *crtc)
14560 {
14561 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14562 bool visible;
14563
14564 visible = crtc->active && primary_get_hw_state(primary);
14565
14566 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14567 to_intel_plane_state(primary->base.state),
14568 visible);
14569 }
14570
14571 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14572 {
14573 struct drm_i915_private *dev_priv = to_i915(dev);
14574 enum pipe pipe;
14575 struct intel_crtc *crtc;
14576 struct intel_encoder *encoder;
14577 struct intel_connector *connector;
14578 struct drm_connector_list_iter conn_iter;
14579 int i;
14580
14581 dev_priv->active_crtcs = 0;
14582
14583 for_each_intel_crtc(dev, crtc) {
14584 struct intel_crtc_state *crtc_state =
14585 to_intel_crtc_state(crtc->base.state);
14586
14587 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14588 memset(crtc_state, 0, sizeof(*crtc_state));
14589 crtc_state->base.crtc = &crtc->base;
14590
14591 crtc_state->base.active = crtc_state->base.enable =
14592 dev_priv->display.get_pipe_config(crtc, crtc_state);
14593
14594 crtc->base.enabled = crtc_state->base.enable;
14595 crtc->active = crtc_state->base.active;
14596
14597 if (crtc_state->base.active)
14598 dev_priv->active_crtcs |= 1 << crtc->pipe;
14599
14600 readout_plane_state(crtc);
14601
14602 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14603 crtc->base.base.id, crtc->base.name,
14604 enableddisabled(crtc_state->base.active));
14605 }
14606
14607 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14608 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14609
14610 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14611 &pll->state.hw_state);
14612 pll->state.crtc_mask = 0;
14613 for_each_intel_crtc(dev, crtc) {
14614 struct intel_crtc_state *crtc_state =
14615 to_intel_crtc_state(crtc->base.state);
14616
14617 if (crtc_state->base.active &&
14618 crtc_state->shared_dpll == pll)
14619 pll->state.crtc_mask |= 1 << crtc->pipe;
14620 }
14621 pll->active_mask = pll->state.crtc_mask;
14622
14623 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14624 pll->name, pll->state.crtc_mask, pll->on);
14625 }
14626
14627 for_each_intel_encoder(dev, encoder) {
14628 pipe = 0;
14629
14630 if (encoder->get_hw_state(encoder, &pipe)) {
14631 struct intel_crtc_state *crtc_state;
14632
14633 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14634 crtc_state = to_intel_crtc_state(crtc->base.state);
14635
14636 encoder->base.crtc = &crtc->base;
14637 crtc_state->output_types |= 1 << encoder->type;
14638 encoder->get_config(encoder, crtc_state);
14639 } else {
14640 encoder->base.crtc = NULL;
14641 }
14642
14643 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14644 encoder->base.base.id, encoder->base.name,
14645 enableddisabled(encoder->base.crtc),
14646 pipe_name(pipe));
14647 }
14648
14649 drm_connector_list_iter_begin(dev, &conn_iter);
14650 for_each_intel_connector_iter(connector, &conn_iter) {
14651 if (connector->get_hw_state(connector)) {
14652 connector->base.dpms = DRM_MODE_DPMS_ON;
14653
14654 encoder = connector->encoder;
14655 connector->base.encoder = &encoder->base;
14656
14657 if (encoder->base.crtc &&
14658 encoder->base.crtc->state->active) {
14659 /*
14660 * This has to be done during hardware readout
14661 * because anything calling .crtc_disable may
14662 * rely on the connector_mask being accurate.
14663 */
14664 encoder->base.crtc->state->connector_mask |=
14665 1 << drm_connector_index(&connector->base);
14666 encoder->base.crtc->state->encoder_mask |=
14667 1 << drm_encoder_index(&encoder->base);
14668 }
14669
14670 } else {
14671 connector->base.dpms = DRM_MODE_DPMS_OFF;
14672 connector->base.encoder = NULL;
14673 }
14674 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14675 connector->base.base.id, connector->base.name,
14676 enableddisabled(connector->base.encoder));
14677 }
14678 drm_connector_list_iter_end(&conn_iter);
14679
14680 for_each_intel_crtc(dev, crtc) {
14681 struct intel_crtc_state *crtc_state =
14682 to_intel_crtc_state(crtc->base.state);
14683 int pixclk = 0;
14684
14685 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
14686 if (crtc_state->base.active) {
14687 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
14688 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
14689 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
14690
14691 /*
14692 * The initial mode needs to be set in order to keep
14693 * the atomic core happy. It wants a valid mode if the
14694 * crtc's enabled, so we do the above call.
14695 *
14696 * But we don't set all the derived state fully, hence
14697 * set a flag to indicate that a full recalculation is
14698 * needed on the next commit.
14699 */
14700 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
14701
14702 intel_crtc_compute_pixel_rate(crtc_state);
14703
14704 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
14705 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14706 pixclk = crtc_state->pixel_rate;
14707 else
14708 WARN_ON(dev_priv->display.modeset_calc_cdclk);
14709
14710 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
14711 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
14712 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
14713
14714 drm_calc_timestamping_constants(&crtc->base,
14715 &crtc_state->base.adjusted_mode);
14716 update_scanline_offset(crtc);
14717 }
14718
14719 dev_priv->min_pixclk[crtc->pipe] = pixclk;
14720
14721 intel_pipe_config_sanity_check(dev_priv, crtc_state);
14722 }
14723 }
14724
14725 static void
14726 get_encoder_power_domains(struct drm_i915_private *dev_priv)
14727 {
14728 struct intel_encoder *encoder;
14729
14730 for_each_intel_encoder(&dev_priv->drm, encoder) {
14731 u64 get_domains;
14732 enum intel_display_power_domain domain;
14733
14734 if (!encoder->get_power_domains)
14735 continue;
14736
14737 get_domains = encoder->get_power_domains(encoder);
14738 for_each_power_domain(domain, get_domains)
14739 intel_display_power_get(dev_priv, domain);
14740 }
14741 }
14742
14743 /* Scan out the current hw modeset state,
14744 * and sanitizes it to the current state
14745 */
14746 static void
14747 intel_modeset_setup_hw_state(struct drm_device *dev,
14748 struct drm_modeset_acquire_ctx *ctx)
14749 {
14750 struct drm_i915_private *dev_priv = to_i915(dev);
14751 enum pipe pipe;
14752 struct intel_crtc *crtc;
14753 struct intel_encoder *encoder;
14754 int i;
14755
14756 intel_modeset_readout_hw_state(dev);
14757
14758 /* HW state is read out, now we need to sanitize this mess. */
14759 get_encoder_power_domains(dev_priv);
14760
14761 for_each_intel_encoder(dev, encoder) {
14762 intel_sanitize_encoder(encoder);
14763 }
14764
14765 for_each_pipe(dev_priv, pipe) {
14766 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14767
14768 intel_sanitize_crtc(crtc, ctx);
14769 intel_dump_pipe_config(crtc, crtc->config,
14770 "[setup_hw_state]");
14771 }
14772
14773 intel_modeset_update_connector_atomic_state(dev);
14774
14775 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14776 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14777
14778 if (!pll->on || pll->active_mask)
14779 continue;
14780
14781 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14782
14783 pll->funcs.disable(dev_priv, pll);
14784 pll->on = false;
14785 }
14786
14787 if (IS_G4X(dev_priv)) {
14788 g4x_wm_get_hw_state(dev);
14789 g4x_wm_sanitize(dev_priv);
14790 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14791 vlv_wm_get_hw_state(dev);
14792 vlv_wm_sanitize(dev_priv);
14793 } else if (IS_GEN9(dev_priv)) {
14794 skl_wm_get_hw_state(dev);
14795 } else if (HAS_PCH_SPLIT(dev_priv)) {
14796 ilk_wm_get_hw_state(dev);
14797 }
14798
14799 for_each_intel_crtc(dev, crtc) {
14800 u64 put_domains;
14801
14802 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
14803 if (WARN_ON(put_domains))
14804 modeset_put_power_domains(dev_priv, put_domains);
14805 }
14806 intel_display_set_init_power(dev_priv, false);
14807
14808 intel_power_domains_verify_state(dev_priv);
14809
14810 intel_fbc_init_pipe_state(dev_priv);
14811 }
14812
14813 void intel_display_resume(struct drm_device *dev)
14814 {
14815 struct drm_i915_private *dev_priv = to_i915(dev);
14816 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
14817 struct drm_modeset_acquire_ctx ctx;
14818 int ret;
14819
14820 dev_priv->modeset_restore_state = NULL;
14821 if (state)
14822 state->acquire_ctx = &ctx;
14823
14824 drm_modeset_acquire_init(&ctx, 0);
14825
14826 while (1) {
14827 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14828 if (ret != -EDEADLK)
14829 break;
14830
14831 drm_modeset_backoff(&ctx);
14832 }
14833
14834 if (!ret)
14835 ret = __intel_display_resume(dev, state, &ctx);
14836
14837 drm_modeset_drop_locks(&ctx);
14838 drm_modeset_acquire_fini(&ctx);
14839
14840 if (ret)
14841 DRM_ERROR("Restoring old state failed with %i\n", ret);
14842 if (state)
14843 drm_atomic_state_put(state);
14844 }
14845
14846 void intel_modeset_gem_init(struct drm_device *dev)
14847 {
14848 struct drm_i915_private *dev_priv = to_i915(dev);
14849
14850 intel_init_gt_powersave(dev_priv);
14851
14852 intel_setup_overlay(dev_priv);
14853 }
14854
14855 int intel_connector_register(struct drm_connector *connector)
14856 {
14857 struct intel_connector *intel_connector = to_intel_connector(connector);
14858 int ret;
14859
14860 ret = intel_backlight_device_register(intel_connector);
14861 if (ret)
14862 goto err;
14863
14864 return 0;
14865
14866 err:
14867 return ret;
14868 }
14869
14870 void intel_connector_unregister(struct drm_connector *connector)
14871 {
14872 struct intel_connector *intel_connector = to_intel_connector(connector);
14873
14874 intel_backlight_device_unregister(intel_connector);
14875 intel_panel_destroy_backlight(connector);
14876 }
14877
14878 void intel_modeset_cleanup(struct drm_device *dev)
14879 {
14880 struct drm_i915_private *dev_priv = to_i915(dev);
14881
14882 flush_work(&dev_priv->atomic_helper.free_work);
14883 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
14884
14885 intel_disable_gt_powersave(dev_priv);
14886
14887 /*
14888 * Interrupts and polling as the first thing to avoid creating havoc.
14889 * Too much stuff here (turning of connectors, ...) would
14890 * experience fancy races otherwise.
14891 */
14892 intel_irq_uninstall(dev_priv);
14893
14894 /*
14895 * Due to the hpd irq storm handling the hotplug work can re-arm the
14896 * poll handlers. Hence disable polling after hpd handling is shut down.
14897 */
14898 drm_kms_helper_poll_fini(dev);
14899
14900 /* poll work can call into fbdev, hence clean that up afterwards */
14901 intel_fbdev_fini(dev_priv);
14902
14903 intel_unregister_dsm_handler();
14904
14905 intel_fbc_global_disable(dev_priv);
14906
14907 /* flush any delayed tasks or pending work */
14908 flush_scheduled_work();
14909
14910 drm_mode_config_cleanup(dev);
14911
14912 intel_cleanup_overlay(dev_priv);
14913
14914 intel_cleanup_gt_powersave(dev_priv);
14915
14916 intel_teardown_gmbus(dev_priv);
14917 }
14918
14919 void intel_connector_attach_encoder(struct intel_connector *connector,
14920 struct intel_encoder *encoder)
14921 {
14922 connector->encoder = encoder;
14923 drm_mode_connector_attach_encoder(&connector->base,
14924 &encoder->base);
14925 }
14926
14927 /*
14928 * set vga decode state - true == enable VGA decode
14929 */
14930 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
14931 {
14932 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14933 u16 gmch_ctrl;
14934
14935 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14936 DRM_ERROR("failed to read control word\n");
14937 return -EIO;
14938 }
14939
14940 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14941 return 0;
14942
14943 if (state)
14944 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14945 else
14946 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14947
14948 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14949 DRM_ERROR("failed to write control word\n");
14950 return -EIO;
14951 }
14952
14953 return 0;
14954 }
14955
14956 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
14957
14958 struct intel_display_error_state {
14959
14960 u32 power_well_driver;
14961
14962 int num_transcoders;
14963
14964 struct intel_cursor_error_state {
14965 u32 control;
14966 u32 position;
14967 u32 base;
14968 u32 size;
14969 } cursor[I915_MAX_PIPES];
14970
14971 struct intel_pipe_error_state {
14972 bool power_domain_on;
14973 u32 source;
14974 u32 stat;
14975 } pipe[I915_MAX_PIPES];
14976
14977 struct intel_plane_error_state {
14978 u32 control;
14979 u32 stride;
14980 u32 size;
14981 u32 pos;
14982 u32 addr;
14983 u32 surface;
14984 u32 tile_offset;
14985 } plane[I915_MAX_PIPES];
14986
14987 struct intel_transcoder_error_state {
14988 bool power_domain_on;
14989 enum transcoder cpu_transcoder;
14990
14991 u32 conf;
14992
14993 u32 htotal;
14994 u32 hblank;
14995 u32 hsync;
14996 u32 vtotal;
14997 u32 vblank;
14998 u32 vsync;
14999 } transcoder[4];
15000 };
15001
15002 struct intel_display_error_state *
15003 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15004 {
15005 struct intel_display_error_state *error;
15006 int transcoders[] = {
15007 TRANSCODER_A,
15008 TRANSCODER_B,
15009 TRANSCODER_C,
15010 TRANSCODER_EDP,
15011 };
15012 int i;
15013
15014 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15015 return NULL;
15016
15017 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15018 if (error == NULL)
15019 return NULL;
15020
15021 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15022 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15023
15024 for_each_pipe(dev_priv, i) {
15025 error->pipe[i].power_domain_on =
15026 __intel_display_power_is_enabled(dev_priv,
15027 POWER_DOMAIN_PIPE(i));
15028 if (!error->pipe[i].power_domain_on)
15029 continue;
15030
15031 error->cursor[i].control = I915_READ(CURCNTR(i));
15032 error->cursor[i].position = I915_READ(CURPOS(i));
15033 error->cursor[i].base = I915_READ(CURBASE(i));
15034
15035 error->plane[i].control = I915_READ(DSPCNTR(i));
15036 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15037 if (INTEL_GEN(dev_priv) <= 3) {
15038 error->plane[i].size = I915_READ(DSPSIZE(i));
15039 error->plane[i].pos = I915_READ(DSPPOS(i));
15040 }
15041 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15042 error->plane[i].addr = I915_READ(DSPADDR(i));
15043 if (INTEL_GEN(dev_priv) >= 4) {
15044 error->plane[i].surface = I915_READ(DSPSURF(i));
15045 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15046 }
15047
15048 error->pipe[i].source = I915_READ(PIPESRC(i));
15049
15050 if (HAS_GMCH_DISPLAY(dev_priv))
15051 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15052 }
15053
15054 /* Note: this does not include DSI transcoders. */
15055 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15056 if (HAS_DDI(dev_priv))
15057 error->num_transcoders++; /* Account for eDP. */
15058
15059 for (i = 0; i < error->num_transcoders; i++) {
15060 enum transcoder cpu_transcoder = transcoders[i];
15061
15062 error->transcoder[i].power_domain_on =
15063 __intel_display_power_is_enabled(dev_priv,
15064 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15065 if (!error->transcoder[i].power_domain_on)
15066 continue;
15067
15068 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15069
15070 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15071 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15072 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15073 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15074 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15075 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15076 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15077 }
15078
15079 return error;
15080 }
15081
15082 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15083
15084 void
15085 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15086 struct intel_display_error_state *error)
15087 {
15088 struct drm_i915_private *dev_priv = m->i915;
15089 int i;
15090
15091 if (!error)
15092 return;
15093
15094 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15095 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15096 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15097 error->power_well_driver);
15098 for_each_pipe(dev_priv, i) {
15099 err_printf(m, "Pipe [%d]:\n", i);
15100 err_printf(m, " Power: %s\n",
15101 onoff(error->pipe[i].power_domain_on));
15102 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15103 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15104
15105 err_printf(m, "Plane [%d]:\n", i);
15106 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15107 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15108 if (INTEL_GEN(dev_priv) <= 3) {
15109 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15110 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15111 }
15112 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15113 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15114 if (INTEL_GEN(dev_priv) >= 4) {
15115 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15116 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15117 }
15118
15119 err_printf(m, "Cursor [%d]:\n", i);
15120 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15121 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15122 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15123 }
15124
15125 for (i = 0; i < error->num_transcoders; i++) {
15126 err_printf(m, "CPU transcoder: %s\n",
15127 transcoder_name(error->transcoder[i].cpu_transcoder));
15128 err_printf(m, " Power: %s\n",
15129 onoff(error->transcoder[i].power_domain_on));
15130 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15131 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15132 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15133 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15134 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15135 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15136 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15137 }
15138 }
15139
15140 #endif
ubuntu-bionic-kernel mirror