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drm/i915: Remove intel_flip_work infrastructure
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint32_t skl_primary_formats[] = {
71 DRM_FORMAT_C8,
72 DRM_FORMAT_RGB565,
73 DRM_FORMAT_XRGB8888,
74 DRM_FORMAT_XBGR8888,
75 DRM_FORMAT_ARGB8888,
76 DRM_FORMAT_ABGR8888,
77 DRM_FORMAT_XRGB2101010,
78 DRM_FORMAT_XBGR2101010,
79 DRM_FORMAT_YUYV,
80 DRM_FORMAT_YVYU,
81 DRM_FORMAT_UYVY,
82 DRM_FORMAT_VYUY,
83 };
84
85 /* Cursor formats */
86 static const uint32_t intel_cursor_formats[] = {
87 DRM_FORMAT_ARGB8888,
88 };
89
90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
93 struct intel_crtc_state *pipe_config);
94
95 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
96 struct drm_i915_gem_object *obj,
97 struct drm_mode_fb_cmd2 *mode_cmd);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev,
119 struct drm_modeset_acquire_ctx *ctx);
120 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
121
122 struct intel_limit {
123 struct {
124 int min, max;
125 } dot, vco, n, m, m1, m2, p, p1;
126
127 struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } p2;
131 };
132
133 /* returns HPLL frequency in kHz */
134 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
135 {
136 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
137
138 /* Obtain SKU information */
139 mutex_lock(&dev_priv->sb_lock);
140 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
141 CCK_FUSE_HPLL_FREQ_MASK;
142 mutex_unlock(&dev_priv->sb_lock);
143
144 return vco_freq[hpll_freq] * 1000;
145 }
146
147 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
148 const char *name, u32 reg, int ref_freq)
149 {
150 u32 val;
151 int divider;
152
153 mutex_lock(&dev_priv->sb_lock);
154 val = vlv_cck_read(dev_priv, reg);
155 mutex_unlock(&dev_priv->sb_lock);
156
157 divider = val & CCK_FREQUENCY_VALUES;
158
159 WARN((val & CCK_FREQUENCY_STATUS) !=
160 (divider << CCK_FREQUENCY_STATUS_SHIFT),
161 "%s change in progress\n", name);
162
163 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
164 }
165
166 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
167 const char *name, u32 reg)
168 {
169 if (dev_priv->hpll_freq == 0)
170 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
171
172 return vlv_get_cck_clock(dev_priv, name, reg,
173 dev_priv->hpll_freq);
174 }
175
176 static void intel_update_czclk(struct drm_i915_private *dev_priv)
177 {
178 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
179 return;
180
181 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
182 CCK_CZ_CLOCK_CONTROL);
183
184 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
185 }
186
187 static inline u32 /* units of 100MHz */
188 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
189 const struct intel_crtc_state *pipe_config)
190 {
191 if (HAS_DDI(dev_priv))
192 return pipe_config->port_clock; /* SPLL */
193 else if (IS_GEN5(dev_priv))
194 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
195 else
196 return 270000;
197 }
198
199 static const struct intel_limit intel_limits_i8xx_dac = {
200 .dot = { .min = 25000, .max = 350000 },
201 .vco = { .min = 908000, .max = 1512000 },
202 .n = { .min = 2, .max = 16 },
203 .m = { .min = 96, .max = 140 },
204 .m1 = { .min = 18, .max = 26 },
205 .m2 = { .min = 6, .max = 16 },
206 .p = { .min = 4, .max = 128 },
207 .p1 = { .min = 2, .max = 33 },
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 4, .p2_fast = 2 },
210 };
211
212 static const struct intel_limit intel_limits_i8xx_dvo = {
213 .dot = { .min = 25000, .max = 350000 },
214 .vco = { .min = 908000, .max = 1512000 },
215 .n = { .min = 2, .max = 16 },
216 .m = { .min = 96, .max = 140 },
217 .m1 = { .min = 18, .max = 26 },
218 .m2 = { .min = 6, .max = 16 },
219 .p = { .min = 4, .max = 128 },
220 .p1 = { .min = 2, .max = 33 },
221 .p2 = { .dot_limit = 165000,
222 .p2_slow = 4, .p2_fast = 4 },
223 };
224
225 static const struct intel_limit intel_limits_i8xx_lvds = {
226 .dot = { .min = 25000, .max = 350000 },
227 .vco = { .min = 908000, .max = 1512000 },
228 .n = { .min = 2, .max = 16 },
229 .m = { .min = 96, .max = 140 },
230 .m1 = { .min = 18, .max = 26 },
231 .m2 = { .min = 6, .max = 16 },
232 .p = { .min = 4, .max = 128 },
233 .p1 = { .min = 1, .max = 6 },
234 .p2 = { .dot_limit = 165000,
235 .p2_slow = 14, .p2_fast = 7 },
236 };
237
238 static const struct intel_limit intel_limits_i9xx_sdvo = {
239 .dot = { .min = 20000, .max = 400000 },
240 .vco = { .min = 1400000, .max = 2800000 },
241 .n = { .min = 1, .max = 6 },
242 .m = { .min = 70, .max = 120 },
243 .m1 = { .min = 8, .max = 18 },
244 .m2 = { .min = 3, .max = 7 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 };
250
251 static const struct intel_limit intel_limits_i9xx_lvds = {
252 .dot = { .min = 20000, .max = 400000 },
253 .vco = { .min = 1400000, .max = 2800000 },
254 .n = { .min = 1, .max = 6 },
255 .m = { .min = 70, .max = 120 },
256 .m1 = { .min = 8, .max = 18 },
257 .m2 = { .min = 3, .max = 7 },
258 .p = { .min = 7, .max = 98 },
259 .p1 = { .min = 1, .max = 8 },
260 .p2 = { .dot_limit = 112000,
261 .p2_slow = 14, .p2_fast = 7 },
262 };
263
264
265 static const struct intel_limit intel_limits_g4x_sdvo = {
266 .dot = { .min = 25000, .max = 270000 },
267 .vco = { .min = 1750000, .max = 3500000},
268 .n = { .min = 1, .max = 4 },
269 .m = { .min = 104, .max = 138 },
270 .m1 = { .min = 17, .max = 23 },
271 .m2 = { .min = 5, .max = 11 },
272 .p = { .min = 10, .max = 30 },
273 .p1 = { .min = 1, .max = 3},
274 .p2 = { .dot_limit = 270000,
275 .p2_slow = 10,
276 .p2_fast = 10
277 },
278 };
279
280 static const struct intel_limit intel_limits_g4x_hdmi = {
281 .dot = { .min = 22000, .max = 400000 },
282 .vco = { .min = 1750000, .max = 3500000},
283 .n = { .min = 1, .max = 4 },
284 .m = { .min = 104, .max = 138 },
285 .m1 = { .min = 16, .max = 23 },
286 .m2 = { .min = 5, .max = 11 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8},
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 10, .p2_fast = 5 },
291 };
292
293 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
294 .dot = { .min = 20000, .max = 115000 },
295 .vco = { .min = 1750000, .max = 3500000 },
296 .n = { .min = 1, .max = 3 },
297 .m = { .min = 104, .max = 138 },
298 .m1 = { .min = 17, .max = 23 },
299 .m2 = { .min = 5, .max = 11 },
300 .p = { .min = 28, .max = 112 },
301 .p1 = { .min = 2, .max = 8 },
302 .p2 = { .dot_limit = 0,
303 .p2_slow = 14, .p2_fast = 14
304 },
305 };
306
307 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
308 .dot = { .min = 80000, .max = 224000 },
309 .vco = { .min = 1750000, .max = 3500000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 104, .max = 138 },
312 .m1 = { .min = 17, .max = 23 },
313 .m2 = { .min = 5, .max = 11 },
314 .p = { .min = 14, .max = 42 },
315 .p1 = { .min = 2, .max = 6 },
316 .p2 = { .dot_limit = 0,
317 .p2_slow = 7, .p2_fast = 7
318 },
319 };
320
321 static const struct intel_limit intel_limits_pineview_sdvo = {
322 .dot = { .min = 20000, .max = 400000},
323 .vco = { .min = 1700000, .max = 3500000 },
324 /* Pineview's Ncounter is a ring counter */
325 .n = { .min = 3, .max = 6 },
326 .m = { .min = 2, .max = 256 },
327 /* Pineview only has one combined m divider, which we treat as m2. */
328 .m1 = { .min = 0, .max = 0 },
329 .m2 = { .min = 0, .max = 254 },
330 .p = { .min = 5, .max = 80 },
331 .p1 = { .min = 1, .max = 8 },
332 .p2 = { .dot_limit = 200000,
333 .p2_slow = 10, .p2_fast = 5 },
334 };
335
336 static const struct intel_limit intel_limits_pineview_lvds = {
337 .dot = { .min = 20000, .max = 400000 },
338 .vco = { .min = 1700000, .max = 3500000 },
339 .n = { .min = 3, .max = 6 },
340 .m = { .min = 2, .max = 256 },
341 .m1 = { .min = 0, .max = 0 },
342 .m2 = { .min = 0, .max = 254 },
343 .p = { .min = 7, .max = 112 },
344 .p1 = { .min = 1, .max = 8 },
345 .p2 = { .dot_limit = 112000,
346 .p2_slow = 14, .p2_fast = 14 },
347 };
348
349 /* Ironlake / Sandybridge
350 *
351 * We calculate clock using (register_value + 2) for N/M1/M2, so here
352 * the range value for them is (actual_value - 2).
353 */
354 static const struct intel_limit intel_limits_ironlake_dac = {
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 5 },
358 .m = { .min = 79, .max = 127 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 5, .max = 80 },
362 .p1 = { .min = 1, .max = 8 },
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 10, .p2_fast = 5 },
365 };
366
367 static const struct intel_limit intel_limits_ironlake_single_lvds = {
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 118 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 28, .max = 112 },
375 .p1 = { .min = 2, .max = 8 },
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 14, .p2_fast = 14 },
378 };
379
380 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
381 .dot = { .min = 25000, .max = 350000 },
382 .vco = { .min = 1760000, .max = 3510000 },
383 .n = { .min = 1, .max = 3 },
384 .m = { .min = 79, .max = 127 },
385 .m1 = { .min = 12, .max = 22 },
386 .m2 = { .min = 5, .max = 9 },
387 .p = { .min = 14, .max = 56 },
388 .p1 = { .min = 2, .max = 8 },
389 .p2 = { .dot_limit = 225000,
390 .p2_slow = 7, .p2_fast = 7 },
391 };
392
393 /* LVDS 100mhz refclk limits. */
394 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
395 .dot = { .min = 25000, .max = 350000 },
396 .vco = { .min = 1760000, .max = 3510000 },
397 .n = { .min = 1, .max = 2 },
398 .m = { .min = 79, .max = 126 },
399 .m1 = { .min = 12, .max = 22 },
400 .m2 = { .min = 5, .max = 9 },
401 .p = { .min = 28, .max = 112 },
402 .p1 = { .min = 2, .max = 8 },
403 .p2 = { .dot_limit = 225000,
404 .p2_slow = 14, .p2_fast = 14 },
405 };
406
407 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
408 .dot = { .min = 25000, .max = 350000 },
409 .vco = { .min = 1760000, .max = 3510000 },
410 .n = { .min = 1, .max = 3 },
411 .m = { .min = 79, .max = 126 },
412 .m1 = { .min = 12, .max = 22 },
413 .m2 = { .min = 5, .max = 9 },
414 .p = { .min = 14, .max = 42 },
415 .p1 = { .min = 2, .max = 6 },
416 .p2 = { .dot_limit = 225000,
417 .p2_slow = 7, .p2_fast = 7 },
418 };
419
420 static const struct intel_limit intel_limits_vlv = {
421 /*
422 * These are the data rate limits (measured in fast clocks)
423 * since those are the strictest limits we have. The fast
424 * clock and actual rate limits are more relaxed, so checking
425 * them would make no difference.
426 */
427 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
428 .vco = { .min = 4000000, .max = 6000000 },
429 .n = { .min = 1, .max = 7 },
430 .m1 = { .min = 2, .max = 3 },
431 .m2 = { .min = 11, .max = 156 },
432 .p1 = { .min = 2, .max = 3 },
433 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
434 };
435
436 static const struct intel_limit intel_limits_chv = {
437 /*
438 * These are the data rate limits (measured in fast clocks)
439 * since those are the strictest limits we have. The fast
440 * clock and actual rate limits are more relaxed, so checking
441 * them would make no difference.
442 */
443 .dot = { .min = 25000 * 5, .max = 540000 * 5},
444 .vco = { .min = 4800000, .max = 6480000 },
445 .n = { .min = 1, .max = 1 },
446 .m1 = { .min = 2, .max = 2 },
447 .m2 = { .min = 24 << 22, .max = 175 << 22 },
448 .p1 = { .min = 2, .max = 4 },
449 .p2 = { .p2_slow = 1, .p2_fast = 14 },
450 };
451
452 static const struct intel_limit intel_limits_bxt = {
453 /* FIXME: find real dot limits */
454 .dot = { .min = 0, .max = INT_MAX },
455 .vco = { .min = 4800000, .max = 6700000 },
456 .n = { .min = 1, .max = 1 },
457 .m1 = { .min = 2, .max = 2 },
458 /* FIXME: find real m2 limits */
459 .m2 = { .min = 2 << 22, .max = 255 << 22 },
460 .p1 = { .min = 2, .max = 4 },
461 .p2 = { .p2_slow = 1, .p2_fast = 20 },
462 };
463
464 static bool
465 needs_modeset(struct drm_crtc_state *state)
466 {
467 return drm_atomic_crtc_needs_modeset(state);
468 }
469
470 /*
471 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
472 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
473 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
474 * The helpers' return value is the rate of the clock that is fed to the
475 * display engine's pipe which can be the above fast dot clock rate or a
476 * divided-down version of it.
477 */
478 /* m1 is reserved as 0 in Pineview, n is a ring counter */
479 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
480 {
481 clock->m = clock->m2 + 2;
482 clock->p = clock->p1 * clock->p2;
483 if (WARN_ON(clock->n == 0 || clock->p == 0))
484 return 0;
485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
487
488 return clock->dot;
489 }
490
491 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
492 {
493 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
494 }
495
496 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
497 {
498 clock->m = i9xx_dpll_compute_m(clock);
499 clock->p = clock->p1 * clock->p2;
500 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
501 return 0;
502 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
503 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
504
505 return clock->dot;
506 }
507
508 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m1 * clock->m2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot / 5;
518 }
519
520 int chv_calc_dpll_params(int refclk, struct dpll *clock)
521 {
522 clock->m = clock->m1 * clock->m2;
523 clock->p = clock->p1 * clock->p2;
524 if (WARN_ON(clock->n == 0 || clock->p == 0))
525 return 0;
526 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
527 clock->n << 22);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529
530 return clock->dot / 5;
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
540 const struct intel_limit *limit,
541 const struct dpll *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
553 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
554 if (clock->m1 <= clock->m2)
555 INTELPllInvalid("m1 <= m2\n");
556
557 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
558 !IS_GEN9_LP(dev_priv)) {
559 if (clock->p < limit->p.min || limit->p.max < clock->p)
560 INTELPllInvalid("p out of range\n");
561 if (clock->m < limit->m.min || limit->m.max < clock->m)
562 INTELPllInvalid("m out of range\n");
563 }
564
565 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
566 INTELPllInvalid("vco out of range\n");
567 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
568 * connector, etc., rather than just a single range.
569 */
570 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
571 INTELPllInvalid("dot out of range\n");
572
573 return true;
574 }
575
576 static int
577 i9xx_select_p2_div(const struct intel_limit *limit,
578 const struct intel_crtc_state *crtc_state,
579 int target)
580 {
581 struct drm_device *dev = crtc_state->base.crtc->dev;
582
583 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 return limit->p2.p2_fast;
591 else
592 return limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 return limit->p2.p2_slow;
596 else
597 return limit->p2.p2_fast;
598 }
599 }
600
601 /*
602 * Returns a set of divisors for the desired target clock with the given
603 * refclk, or FALSE. The returned values represent the clock equation:
604 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
605 *
606 * Target and reference clocks are specified in kHz.
607 *
608 * If match_clock is provided, then best_clock P divider must match the P
609 * divider from @match_clock used for LVDS downclocking.
610 */
611 static bool
612 i9xx_find_best_dpll(const struct intel_limit *limit,
613 struct intel_crtc_state *crtc_state,
614 int target, int refclk, struct dpll *match_clock,
615 struct dpll *best_clock)
616 {
617 struct drm_device *dev = crtc_state->base.crtc->dev;
618 struct dpll clock;
619 int err = target;
620
621 memset(best_clock, 0, sizeof(*best_clock));
622
623 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
624
625 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
626 clock.m1++) {
627 for (clock.m2 = limit->m2.min;
628 clock.m2 <= limit->m2.max; clock.m2++) {
629 if (clock.m2 >= clock.m1)
630 break;
631 for (clock.n = limit->n.min;
632 clock.n <= limit->n.max; clock.n++) {
633 for (clock.p1 = limit->p1.min;
634 clock.p1 <= limit->p1.max; clock.p1++) {
635 int this_err;
636
637 i9xx_calc_dpll_params(refclk, &clock);
638 if (!intel_PLL_is_valid(to_i915(dev),
639 limit,
640 &clock))
641 continue;
642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657 }
658
659 /*
660 * Returns a set of divisors for the desired target clock with the given
661 * refclk, or FALSE. The returned values represent the clock equation:
662 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
663 *
664 * Target and reference clocks are specified in kHz.
665 *
666 * If match_clock is provided, then best_clock P divider must match the P
667 * divider from @match_clock used for LVDS downclocking.
668 */
669 static bool
670 pnv_find_best_dpll(const struct intel_limit *limit,
671 struct intel_crtc_state *crtc_state,
672 int target, int refclk, struct dpll *match_clock,
673 struct dpll *best_clock)
674 {
675 struct drm_device *dev = crtc_state->base.crtc->dev;
676 struct dpll clock;
677 int err = target;
678
679 memset(best_clock, 0, sizeof(*best_clock));
680
681 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
682
683 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
684 clock.m1++) {
685 for (clock.m2 = limit->m2.min;
686 clock.m2 <= limit->m2.max; clock.m2++) {
687 for (clock.n = limit->n.min;
688 clock.n <= limit->n.max; clock.n++) {
689 for (clock.p1 = limit->p1.min;
690 clock.p1 <= limit->p1.max; clock.p1++) {
691 int this_err;
692
693 pnv_calc_dpll_params(refclk, &clock);
694 if (!intel_PLL_is_valid(to_i915(dev),
695 limit,
696 &clock))
697 continue;
698 if (match_clock &&
699 clock.p != match_clock->p)
700 continue;
701
702 this_err = abs(clock.dot - target);
703 if (this_err < err) {
704 *best_clock = clock;
705 err = this_err;
706 }
707 }
708 }
709 }
710 }
711
712 return (err != target);
713 }
714
715 /*
716 * Returns a set of divisors for the desired target clock with the given
717 * refclk, or FALSE. The returned values represent the clock equation:
718 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
719 *
720 * Target and reference clocks are specified in kHz.
721 *
722 * If match_clock is provided, then best_clock P divider must match the P
723 * divider from @match_clock used for LVDS downclocking.
724 */
725 static bool
726 g4x_find_best_dpll(const struct intel_limit *limit,
727 struct intel_crtc_state *crtc_state,
728 int target, int refclk, struct dpll *match_clock,
729 struct dpll *best_clock)
730 {
731 struct drm_device *dev = crtc_state->base.crtc->dev;
732 struct dpll clock;
733 int max_n;
734 bool found = false;
735 /* approximately equals target * 0.00585 */
736 int err_most = (target >> 8) + (target >> 9);
737
738 memset(best_clock, 0, sizeof(*best_clock));
739
740 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
741
742 max_n = limit->n.max;
743 /* based on hardware requirement, prefer smaller n to precision */
744 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
745 /* based on hardware requirement, prefere larger m1,m2 */
746 for (clock.m1 = limit->m1.max;
747 clock.m1 >= limit->m1.min; clock.m1--) {
748 for (clock.m2 = limit->m2.max;
749 clock.m2 >= limit->m2.min; clock.m2--) {
750 for (clock.p1 = limit->p1.max;
751 clock.p1 >= limit->p1.min; clock.p1--) {
752 int this_err;
753
754 i9xx_calc_dpll_params(refclk, &clock);
755 if (!intel_PLL_is_valid(to_i915(dev),
756 limit,
757 &clock))
758 continue;
759
760 this_err = abs(clock.dot - target);
761 if (this_err < err_most) {
762 *best_clock = clock;
763 err_most = this_err;
764 max_n = clock.n;
765 found = true;
766 }
767 }
768 }
769 }
770 }
771 return found;
772 }
773
774 /*
775 * Check if the calculated PLL configuration is more optimal compared to the
776 * best configuration and error found so far. Return the calculated error.
777 */
778 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
779 const struct dpll *calculated_clock,
780 const struct dpll *best_clock,
781 unsigned int best_error_ppm,
782 unsigned int *error_ppm)
783 {
784 /*
785 * For CHV ignore the error and consider only the P value.
786 * Prefer a bigger P value based on HW requirements.
787 */
788 if (IS_CHERRYVIEW(to_i915(dev))) {
789 *error_ppm = 0;
790
791 return calculated_clock->p > best_clock->p;
792 }
793
794 if (WARN_ON_ONCE(!target_freq))
795 return false;
796
797 *error_ppm = div_u64(1000000ULL *
798 abs(target_freq - calculated_clock->dot),
799 target_freq);
800 /*
801 * Prefer a better P value over a better (smaller) error if the error
802 * is small. Ensure this preference for future configurations too by
803 * setting the error to 0.
804 */
805 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
806 *error_ppm = 0;
807
808 return true;
809 }
810
811 return *error_ppm + 10 < best_error_ppm;
812 }
813
814 /*
815 * Returns a set of divisors for the desired target clock with the given
816 * refclk, or FALSE. The returned values represent the clock equation:
817 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
818 */
819 static bool
820 vlv_find_best_dpll(const struct intel_limit *limit,
821 struct intel_crtc_state *crtc_state,
822 int target, int refclk, struct dpll *match_clock,
823 struct dpll *best_clock)
824 {
825 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
826 struct drm_device *dev = crtc->base.dev;
827 struct dpll clock;
828 unsigned int bestppm = 1000000;
829 /* min update 19.2 MHz */
830 int max_n = min(limit->n.max, refclk / 19200);
831 bool found = false;
832
833 target *= 5; /* fast clock */
834
835 memset(best_clock, 0, sizeof(*best_clock));
836
837 /* based on hardware requirement, prefer smaller n to precision */
838 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
839 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
840 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
841 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
842 clock.p = clock.p1 * clock.p2;
843 /* based on hardware requirement, prefer bigger m1,m2 values */
844 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
845 unsigned int ppm;
846
847 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
848 refclk * clock.m1);
849
850 vlv_calc_dpll_params(refclk, &clock);
851
852 if (!intel_PLL_is_valid(to_i915(dev),
853 limit,
854 &clock))
855 continue;
856
857 if (!vlv_PLL_is_optimal(dev, target,
858 &clock,
859 best_clock,
860 bestppm, &ppm))
861 continue;
862
863 *best_clock = clock;
864 bestppm = ppm;
865 found = true;
866 }
867 }
868 }
869 }
870
871 return found;
872 }
873
874 /*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
879 static bool
880 chv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
884 {
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
887 unsigned int best_error_ppm;
888 struct dpll clock;
889 uint64_t m2;
890 int found = false;
891
892 memset(best_clock, 0, sizeof(*best_clock));
893 best_error_ppm = 1000000;
894
895 /*
896 * Based on hardware doc, the n always set to 1, and m1 always
897 * set to 2. If requires to support 200Mhz refclk, we need to
898 * revisit this because n may not 1 anymore.
899 */
900 clock.n = 1, clock.m1 = 2;
901 target *= 5; /* fast clock */
902
903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904 for (clock.p2 = limit->p2.p2_fast;
905 clock.p2 >= limit->p2.p2_slow;
906 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
907 unsigned int error_ppm;
908
909 clock.p = clock.p1 * clock.p2;
910
911 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
912 clock.n) << 22, refclk * clock.m1);
913
914 if (m2 > INT_MAX/clock.m1)
915 continue;
916
917 clock.m2 = m2;
918
919 chv_calc_dpll_params(refclk, &clock);
920
921 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
922 continue;
923
924 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
925 best_error_ppm, &error_ppm))
926 continue;
927
928 *best_clock = clock;
929 best_error_ppm = error_ppm;
930 found = true;
931 }
932 }
933
934 return found;
935 }
936
937 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
938 struct dpll *best_clock)
939 {
940 int refclk = 100000;
941 const struct intel_limit *limit = &intel_limits_bxt;
942
943 return chv_find_best_dpll(limit, crtc_state,
944 target_clock, refclk, NULL, best_clock);
945 }
946
947 bool intel_crtc_active(struct intel_crtc *crtc)
948 {
949 /* Be paranoid as we can arrive here with only partial
950 * state retrieved from the hardware during setup.
951 *
952 * We can ditch the adjusted_mode.crtc_clock check as soon
953 * as Haswell has gained clock readout/fastboot support.
954 *
955 * We can ditch the crtc->primary->fb check as soon as we can
956 * properly reconstruct framebuffers.
957 *
958 * FIXME: The intel_crtc->active here should be switched to
959 * crtc->state->active once we have proper CRTC states wired up
960 * for atomic.
961 */
962 return crtc->active && crtc->base.primary->state->fb &&
963 crtc->config->base.adjusted_mode.crtc_clock;
964 }
965
966 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
967 enum pipe pipe)
968 {
969 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
970
971 return crtc->config->cpu_transcoder;
972 }
973
974 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
975 {
976 i915_reg_t reg = PIPEDSL(pipe);
977 u32 line1, line2;
978 u32 line_mask;
979
980 if (IS_GEN2(dev_priv))
981 line_mask = DSL_LINEMASK_GEN2;
982 else
983 line_mask = DSL_LINEMASK_GEN3;
984
985 line1 = I915_READ(reg) & line_mask;
986 msleep(5);
987 line2 = I915_READ(reg) & line_mask;
988
989 return line1 == line2;
990 }
991
992 /*
993 * intel_wait_for_pipe_off - wait for pipe to turn off
994 * @crtc: crtc whose pipe to wait for
995 *
996 * After disabling a pipe, we can't wait for vblank in the usual way,
997 * spinning on the vblank interrupt status bit, since we won't actually
998 * see an interrupt when the pipe is disabled.
999 *
1000 * On Gen4 and above:
1001 * wait for the pipe register state bit to turn off
1002 *
1003 * Otherwise:
1004 * wait for the display line value to settle (it usually
1005 * ends up stopping at the start of the next frame).
1006 *
1007 */
1008 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1009 {
1010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1011 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1012 enum pipe pipe = crtc->pipe;
1013
1014 if (INTEL_GEN(dev_priv) >= 4) {
1015 i915_reg_t reg = PIPECONF(cpu_transcoder);
1016
1017 /* Wait for the Pipe State to go off */
1018 if (intel_wait_for_register(dev_priv,
1019 reg, I965_PIPECONF_ACTIVE, 0,
1020 100))
1021 WARN(1, "pipe_off wait timed out\n");
1022 } else {
1023 /* Wait for the display line to settle */
1024 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1025 WARN(1, "pipe_off wait timed out\n");
1026 }
1027 }
1028
1029 /* Only for pre-ILK configs */
1030 void assert_pll(struct drm_i915_private *dev_priv,
1031 enum pipe pipe, bool state)
1032 {
1033 u32 val;
1034 bool cur_state;
1035
1036 val = I915_READ(DPLL(pipe));
1037 cur_state = !!(val & DPLL_VCO_ENABLE);
1038 I915_STATE_WARN(cur_state != state,
1039 "PLL state assertion failure (expected %s, current %s)\n",
1040 onoff(state), onoff(cur_state));
1041 }
1042
1043 /* XXX: the dsi pll is shared between MIPI DSI ports */
1044 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1045 {
1046 u32 val;
1047 bool cur_state;
1048
1049 mutex_lock(&dev_priv->sb_lock);
1050 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1051 mutex_unlock(&dev_priv->sb_lock);
1052
1053 cur_state = val & DSI_PLL_VCO_EN;
1054 I915_STATE_WARN(cur_state != state,
1055 "DSI PLL state assertion failure (expected %s, current %s)\n",
1056 onoff(state), onoff(cur_state));
1057 }
1058
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1061 {
1062 bool cur_state;
1063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064 pipe);
1065
1066 if (HAS_DDI(dev_priv)) {
1067 /* DDI does not have a specific FDI_TX register */
1068 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1069 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1070 } else {
1071 u32 val = I915_READ(FDI_TX_CTL(pipe));
1072 cur_state = !!(val & FDI_TX_ENABLE);
1073 }
1074 I915_STATE_WARN(cur_state != state,
1075 "FDI TX state assertion failure (expected %s, current %s)\n",
1076 onoff(state), onoff(cur_state));
1077 }
1078 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1079 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1080
1081 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1082 enum pipe pipe, bool state)
1083 {
1084 u32 val;
1085 bool cur_state;
1086
1087 val = I915_READ(FDI_RX_CTL(pipe));
1088 cur_state = !!(val & FDI_RX_ENABLE);
1089 I915_STATE_WARN(cur_state != state,
1090 "FDI RX state assertion failure (expected %s, current %s)\n",
1091 onoff(state), onoff(cur_state));
1092 }
1093 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1094 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1095
1096 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1097 enum pipe pipe)
1098 {
1099 u32 val;
1100
1101 /* ILK FDI PLL is always enabled */
1102 if (IS_GEN5(dev_priv))
1103 return;
1104
1105 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1106 if (HAS_DDI(dev_priv))
1107 return;
1108
1109 val = I915_READ(FDI_TX_CTL(pipe));
1110 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1111 }
1112
1113 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1114 enum pipe pipe, bool state)
1115 {
1116 u32 val;
1117 bool cur_state;
1118
1119 val = I915_READ(FDI_RX_CTL(pipe));
1120 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1121 I915_STATE_WARN(cur_state != state,
1122 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1123 onoff(state), onoff(cur_state));
1124 }
1125
1126 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1127 {
1128 i915_reg_t pp_reg;
1129 u32 val;
1130 enum pipe panel_pipe = PIPE_A;
1131 bool locked = true;
1132
1133 if (WARN_ON(HAS_DDI(dev_priv)))
1134 return;
1135
1136 if (HAS_PCH_SPLIT(dev_priv)) {
1137 u32 port_sel;
1138
1139 pp_reg = PP_CONTROL(0);
1140 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1141
1142 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1143 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1144 panel_pipe = PIPE_B;
1145 /* XXX: else fix for eDP */
1146 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1147 /* presumably write lock depends on pipe, not port select */
1148 pp_reg = PP_CONTROL(pipe);
1149 panel_pipe = pipe;
1150 } else {
1151 pp_reg = PP_CONTROL(0);
1152 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1153 panel_pipe = PIPE_B;
1154 }
1155
1156 val = I915_READ(pp_reg);
1157 if (!(val & PANEL_POWER_ON) ||
1158 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1159 locked = false;
1160
1161 I915_STATE_WARN(panel_pipe == pipe && locked,
1162 "panel assertion failure, pipe %c regs locked\n",
1163 pipe_name(pipe));
1164 }
1165
1166 static void assert_cursor(struct drm_i915_private *dev_priv,
1167 enum pipe pipe, bool state)
1168 {
1169 bool cur_state;
1170
1171 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1172 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1173 else
1174 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1175
1176 I915_STATE_WARN(cur_state != state,
1177 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1178 pipe_name(pipe), onoff(state), onoff(cur_state));
1179 }
1180 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1181 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1182
1183 void assert_pipe(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185 {
1186 bool cur_state;
1187 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1188 pipe);
1189 enum intel_display_power_domain power_domain;
1190
1191 /* we keep both pipes enabled on 830 */
1192 if (IS_I830(dev_priv))
1193 state = true;
1194
1195 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1196 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1197 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1198 cur_state = !!(val & PIPECONF_ENABLE);
1199
1200 intel_display_power_put(dev_priv, power_domain);
1201 } else {
1202 cur_state = false;
1203 }
1204
1205 I915_STATE_WARN(cur_state != state,
1206 "pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209
1210 static void assert_plane(struct drm_i915_private *dev_priv,
1211 enum plane plane, bool state)
1212 {
1213 u32 val;
1214 bool cur_state;
1215
1216 val = I915_READ(DSPCNTR(plane));
1217 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1218 I915_STATE_WARN(cur_state != state,
1219 "plane %c assertion failure (expected %s, current %s)\n",
1220 plane_name(plane), onoff(state), onoff(cur_state));
1221 }
1222
1223 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1224 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1225
1226 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe)
1228 {
1229 int i;
1230
1231 /* Primary planes are fixed to pipes on gen4+ */
1232 if (INTEL_GEN(dev_priv) >= 4) {
1233 u32 val = I915_READ(DSPCNTR(pipe));
1234 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1235 "plane %c assertion failure, should be disabled but not\n",
1236 plane_name(pipe));
1237 return;
1238 }
1239
1240 /* Need to check both planes against the pipe */
1241 for_each_pipe(dev_priv, i) {
1242 u32 val = I915_READ(DSPCNTR(i));
1243 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1244 DISPPLANE_SEL_PIPE_SHIFT;
1245 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1246 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1247 plane_name(i), pipe_name(pipe));
1248 }
1249 }
1250
1251 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe)
1253 {
1254 int sprite;
1255
1256 if (INTEL_GEN(dev_priv) >= 9) {
1257 for_each_sprite(dev_priv, pipe, sprite) {
1258 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1259 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1260 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1261 sprite, pipe_name(pipe));
1262 }
1263 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1264 for_each_sprite(dev_priv, pipe, sprite) {
1265 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1266 I915_STATE_WARN(val & SP_ENABLE,
1267 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1268 sprite_name(pipe, sprite), pipe_name(pipe));
1269 }
1270 } else if (INTEL_GEN(dev_priv) >= 7) {
1271 u32 val = I915_READ(SPRCTL(pipe));
1272 I915_STATE_WARN(val & SPRITE_ENABLE,
1273 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(pipe), pipe_name(pipe));
1275 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1276 u32 val = I915_READ(DVSCNTR(pipe));
1277 I915_STATE_WARN(val & DVS_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 }
1281 }
1282
1283 static void assert_vblank_disabled(struct drm_crtc *crtc)
1284 {
1285 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1286 drm_crtc_vblank_put(crtc);
1287 }
1288
1289 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe)
1291 {
1292 u32 val;
1293 bool enabled;
1294
1295 val = I915_READ(PCH_TRANSCONF(pipe));
1296 enabled = !!(val & TRANS_ENABLE);
1297 I915_STATE_WARN(enabled,
1298 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1299 pipe_name(pipe));
1300 }
1301
1302 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, u32 port_sel, u32 val)
1304 {
1305 if ((val & DP_PORT_EN) == 0)
1306 return false;
1307
1308 if (HAS_PCH_CPT(dev_priv)) {
1309 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1310 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1311 return false;
1312 } else if (IS_CHERRYVIEW(dev_priv)) {
1313 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1314 return false;
1315 } else {
1316 if ((val & DP_PIPE_MASK) != (pipe << 30))
1317 return false;
1318 }
1319 return true;
1320 }
1321
1322 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 val)
1324 {
1325 if ((val & SDVO_ENABLE) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv)) {
1329 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1330 return false;
1331 } else if (IS_CHERRYVIEW(dev_priv)) {
1332 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1333 return false;
1334 } else {
1335 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1336 return false;
1337 }
1338 return true;
1339 }
1340
1341 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 val)
1343 {
1344 if ((val & LVDS_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv)) {
1348 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1349 return false;
1350 } else {
1351 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1352 return false;
1353 }
1354 return true;
1355 }
1356
1357 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359 {
1360 if ((val & ADPA_DAC_ENABLE) == 0)
1361 return false;
1362 if (HAS_PCH_CPT(dev_priv)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1367 return false;
1368 }
1369 return true;
1370 }
1371
1372 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, i915_reg_t reg,
1374 u32 port_sel)
1375 {
1376 u32 val = I915_READ(reg);
1377 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1378 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1379 i915_mmio_reg_offset(reg), pipe_name(pipe));
1380
1381 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1382 && (val & DP_PIPEB_SELECT),
1383 "IBX PCH dp port still using transcoder B\n");
1384 }
1385
1386 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, i915_reg_t reg)
1388 {
1389 u32 val = I915_READ(reg);
1390 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1391 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1392 i915_mmio_reg_offset(reg), pipe_name(pipe));
1393
1394 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1395 && (val & SDVO_PIPE_B_SELECT),
1396 "IBX PCH hdmi port still using transcoder B\n");
1397 }
1398
1399 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401 {
1402 u32 val;
1403
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1407
1408 val = I915_READ(PCH_ADPA);
1409 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1411 pipe_name(pipe));
1412
1413 val = I915_READ(PCH_LVDS);
1414 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1415 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1421 }
1422
1423 static void _vlv_enable_pll(struct intel_crtc *crtc,
1424 const struct intel_crtc_state *pipe_config)
1425 {
1426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1427 enum pipe pipe = crtc->pipe;
1428
1429 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1430 POSTING_READ(DPLL(pipe));
1431 udelay(150);
1432
1433 if (intel_wait_for_register(dev_priv,
1434 DPLL(pipe),
1435 DPLL_LOCK_VLV,
1436 DPLL_LOCK_VLV,
1437 1))
1438 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1439 }
1440
1441 static void vlv_enable_pll(struct intel_crtc *crtc,
1442 const struct intel_crtc_state *pipe_config)
1443 {
1444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1445 enum pipe pipe = crtc->pipe;
1446
1447 assert_pipe_disabled(dev_priv, pipe);
1448
1449 /* PLL is protected by panel, make sure we can write it */
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1453 _vlv_enable_pll(crtc, pipe_config);
1454
1455 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1456 POSTING_READ(DPLL_MD(pipe));
1457 }
1458
1459
1460 static void _chv_enable_pll(struct intel_crtc *crtc,
1461 const struct intel_crtc_state *pipe_config)
1462 {
1463 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1464 enum pipe pipe = crtc->pipe;
1465 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1466 u32 tmp;
1467
1468 mutex_lock(&dev_priv->sb_lock);
1469
1470 /* Enable back the 10bit clock to display controller */
1471 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1472 tmp |= DPIO_DCLKP_EN;
1473 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1474
1475 mutex_unlock(&dev_priv->sb_lock);
1476
1477 /*
1478 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1479 */
1480 udelay(1);
1481
1482 /* Enable PLL */
1483 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1484
1485 /* Check PLL is locked */
1486 if (intel_wait_for_register(dev_priv,
1487 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1488 1))
1489 DRM_ERROR("PLL %d failed to lock\n", pipe);
1490 }
1491
1492 static void chv_enable_pll(struct intel_crtc *crtc,
1493 const struct intel_crtc_state *pipe_config)
1494 {
1495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1496 enum pipe pipe = crtc->pipe;
1497
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 /* PLL is protected by panel, make sure we can write it */
1501 assert_panel_unlocked(dev_priv, pipe);
1502
1503 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1504 _chv_enable_pll(crtc, pipe_config);
1505
1506 if (pipe != PIPE_A) {
1507 /*
1508 * WaPixelRepeatModeFixForC0:chv
1509 *
1510 * DPLLCMD is AWOL. Use chicken bits to propagate
1511 * the value from DPLLBMD to either pipe B or C.
1512 */
1513 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1514 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1515 I915_WRITE(CBR4_VLV, 0);
1516 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1517
1518 /*
1519 * DPLLB VGA mode also seems to cause problems.
1520 * We should always have it disabled.
1521 */
1522 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1523 } else {
1524 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1525 POSTING_READ(DPLL_MD(pipe));
1526 }
1527 }
1528
1529 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1530 {
1531 struct intel_crtc *crtc;
1532 int count = 0;
1533
1534 for_each_intel_crtc(&dev_priv->drm, crtc) {
1535 count += crtc->base.state->active &&
1536 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1537 }
1538
1539 return count;
1540 }
1541
1542 static void i9xx_enable_pll(struct intel_crtc *crtc)
1543 {
1544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1545 i915_reg_t reg = DPLL(crtc->pipe);
1546 u32 dpll = crtc->config->dpll_hw_state.dpll;
1547 int i;
1548
1549 assert_pipe_disabled(dev_priv, crtc->pipe);
1550
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1554
1555 /* Enable DVO 2x clock on both PLLs if necessary */
1556 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1557 /*
1558 * It appears to be important that we don't enable this
1559 * for the current pipe before otherwise configuring the
1560 * PLL. No idea how this should be handled if multiple
1561 * DVO outputs are enabled simultaneosly.
1562 */
1563 dpll |= DPLL_DVO_2X_MODE;
1564 I915_WRITE(DPLL(!crtc->pipe),
1565 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1566 }
1567
1568 /*
1569 * Apparently we need to have VGA mode enabled prior to changing
1570 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1571 * dividers, even though the register value does change.
1572 */
1573 I915_WRITE(reg, 0);
1574
1575 I915_WRITE(reg, dpll);
1576
1577 /* Wait for the clocks to stabilize. */
1578 POSTING_READ(reg);
1579 udelay(150);
1580
1581 if (INTEL_GEN(dev_priv) >= 4) {
1582 I915_WRITE(DPLL_MD(crtc->pipe),
1583 crtc->config->dpll_hw_state.dpll_md);
1584 } else {
1585 /* The pixel multiplier can only be updated once the
1586 * DPLL is enabled and the clocks are stable.
1587 *
1588 * So write it again.
1589 */
1590 I915_WRITE(reg, dpll);
1591 }
1592
1593 /* We do this three times for luck */
1594 for (i = 0; i < 3; i++) {
1595 I915_WRITE(reg, dpll);
1596 POSTING_READ(reg);
1597 udelay(150); /* wait for warmup */
1598 }
1599 }
1600
1601 /**
1602 * i9xx_disable_pll - disable a PLL
1603 * @dev_priv: i915 private structure
1604 * @pipe: pipe PLL to disable
1605 *
1606 * Disable the PLL for @pipe, making sure the pipe is off first.
1607 *
1608 * Note! This is for pre-ILK only.
1609 */
1610 static void i9xx_disable_pll(struct intel_crtc *crtc)
1611 {
1612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1613 enum pipe pipe = crtc->pipe;
1614
1615 /* Disable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev_priv) &&
1617 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1618 !intel_num_dvo_pipes(dev_priv)) {
1619 I915_WRITE(DPLL(PIPE_B),
1620 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1621 I915_WRITE(DPLL(PIPE_A),
1622 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1623 }
1624
1625 /* Don't disable pipe or pipe PLLs if needed */
1626 if (IS_I830(dev_priv))
1627 return;
1628
1629 /* Make sure the pipe isn't still relying on us */
1630 assert_pipe_disabled(dev_priv, pipe);
1631
1632 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1633 POSTING_READ(DPLL(pipe));
1634 }
1635
1636 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1637 {
1638 u32 val;
1639
1640 /* Make sure the pipe isn't still relying on us */
1641 assert_pipe_disabled(dev_priv, pipe);
1642
1643 val = DPLL_INTEGRATED_REF_CLK_VLV |
1644 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1645 if (pipe != PIPE_A)
1646 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1647
1648 I915_WRITE(DPLL(pipe), val);
1649 POSTING_READ(DPLL(pipe));
1650 }
1651
1652 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1653 {
1654 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1655 u32 val;
1656
1657 /* Make sure the pipe isn't still relying on us */
1658 assert_pipe_disabled(dev_priv, pipe);
1659
1660 val = DPLL_SSC_REF_CLK_CHV |
1661 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1662 if (pipe != PIPE_A)
1663 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1664
1665 I915_WRITE(DPLL(pipe), val);
1666 POSTING_READ(DPLL(pipe));
1667
1668 mutex_lock(&dev_priv->sb_lock);
1669
1670 /* Disable 10bit clock to display controller */
1671 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1672 val &= ~DPIO_DCLKP_EN;
1673 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1674
1675 mutex_unlock(&dev_priv->sb_lock);
1676 }
1677
1678 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1679 struct intel_digital_port *dport,
1680 unsigned int expected_mask)
1681 {
1682 u32 port_mask;
1683 i915_reg_t dpll_reg;
1684
1685 switch (dport->port) {
1686 case PORT_B:
1687 port_mask = DPLL_PORTB_READY_MASK;
1688 dpll_reg = DPLL(0);
1689 break;
1690 case PORT_C:
1691 port_mask = DPLL_PORTC_READY_MASK;
1692 dpll_reg = DPLL(0);
1693 expected_mask <<= 4;
1694 break;
1695 case PORT_D:
1696 port_mask = DPLL_PORTD_READY_MASK;
1697 dpll_reg = DPIO_PHY_STATUS;
1698 break;
1699 default:
1700 BUG();
1701 }
1702
1703 if (intel_wait_for_register(dev_priv,
1704 dpll_reg, port_mask, expected_mask,
1705 1000))
1706 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1707 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1708 }
1709
1710 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1711 enum pipe pipe)
1712 {
1713 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1714 pipe);
1715 i915_reg_t reg;
1716 uint32_t val, pipeconf_val;
1717
1718 /* Make sure PCH DPLL is enabled */
1719 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1720
1721 /* FDI must be feeding us bits for PCH ports */
1722 assert_fdi_tx_enabled(dev_priv, pipe);
1723 assert_fdi_rx_enabled(dev_priv, pipe);
1724
1725 if (HAS_PCH_CPT(dev_priv)) {
1726 /* Workaround: Set the timing override bit before enabling the
1727 * pch transcoder. */
1728 reg = TRANS_CHICKEN2(pipe);
1729 val = I915_READ(reg);
1730 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1731 I915_WRITE(reg, val);
1732 }
1733
1734 reg = PCH_TRANSCONF(pipe);
1735 val = I915_READ(reg);
1736 pipeconf_val = I915_READ(PIPECONF(pipe));
1737
1738 if (HAS_PCH_IBX(dev_priv)) {
1739 /*
1740 * Make the BPC in transcoder be consistent with
1741 * that in pipeconf reg. For HDMI we must use 8bpc
1742 * here for both 8bpc and 12bpc.
1743 */
1744 val &= ~PIPECONF_BPC_MASK;
1745 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1746 val |= PIPECONF_8BPC;
1747 else
1748 val |= pipeconf_val & PIPECONF_BPC_MASK;
1749 }
1750
1751 val &= ~TRANS_INTERLACE_MASK;
1752 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1753 if (HAS_PCH_IBX(dev_priv) &&
1754 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1755 val |= TRANS_LEGACY_INTERLACED_ILK;
1756 else
1757 val |= TRANS_INTERLACED;
1758 else
1759 val |= TRANS_PROGRESSIVE;
1760
1761 I915_WRITE(reg, val | TRANS_ENABLE);
1762 if (intel_wait_for_register(dev_priv,
1763 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1764 100))
1765 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1766 }
1767
1768 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum transcoder cpu_transcoder)
1770 {
1771 u32 val, pipeconf_val;
1772
1773 /* FDI must be feeding us bits for PCH ports */
1774 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1775 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1776
1777 /* Workaround: set timing override bit. */
1778 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1779 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1780 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1781
1782 val = TRANS_ENABLE;
1783 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1784
1785 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1786 PIPECONF_INTERLACED_ILK)
1787 val |= TRANS_INTERLACED;
1788 else
1789 val |= TRANS_PROGRESSIVE;
1790
1791 I915_WRITE(LPT_TRANSCONF, val);
1792 if (intel_wait_for_register(dev_priv,
1793 LPT_TRANSCONF,
1794 TRANS_STATE_ENABLE,
1795 TRANS_STATE_ENABLE,
1796 100))
1797 DRM_ERROR("Failed to enable PCH transcoder\n");
1798 }
1799
1800 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1801 enum pipe pipe)
1802 {
1803 i915_reg_t reg;
1804 uint32_t val;
1805
1806 /* FDI relies on the transcoder */
1807 assert_fdi_tx_disabled(dev_priv, pipe);
1808 assert_fdi_rx_disabled(dev_priv, pipe);
1809
1810 /* Ports must be off as well */
1811 assert_pch_ports_disabled(dev_priv, pipe);
1812
1813 reg = PCH_TRANSCONF(pipe);
1814 val = I915_READ(reg);
1815 val &= ~TRANS_ENABLE;
1816 I915_WRITE(reg, val);
1817 /* wait for PCH transcoder off, transcoder state */
1818 if (intel_wait_for_register(dev_priv,
1819 reg, TRANS_STATE_ENABLE, 0,
1820 50))
1821 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1822
1823 if (HAS_PCH_CPT(dev_priv)) {
1824 /* Workaround: Clear the timing override chicken bit again. */
1825 reg = TRANS_CHICKEN2(pipe);
1826 val = I915_READ(reg);
1827 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1828 I915_WRITE(reg, val);
1829 }
1830 }
1831
1832 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1833 {
1834 u32 val;
1835
1836 val = I915_READ(LPT_TRANSCONF);
1837 val &= ~TRANS_ENABLE;
1838 I915_WRITE(LPT_TRANSCONF, val);
1839 /* wait for PCH transcoder off, transcoder state */
1840 if (intel_wait_for_register(dev_priv,
1841 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1842 50))
1843 DRM_ERROR("Failed to disable PCH transcoder\n");
1844
1845 /* Workaround: clear timing override bit. */
1846 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1847 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1848 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1849 }
1850
1851 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1852 {
1853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1854
1855 WARN_ON(!crtc->config->has_pch_encoder);
1856
1857 if (HAS_PCH_LPT(dev_priv))
1858 return PIPE_A;
1859 else
1860 return crtc->pipe;
1861 }
1862
1863 /**
1864 * intel_enable_pipe - enable a pipe, asserting requirements
1865 * @crtc: crtc responsible for the pipe
1866 *
1867 * Enable @crtc's pipe, making sure that various hardware specific requirements
1868 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1869 */
1870 static void intel_enable_pipe(struct intel_crtc *crtc)
1871 {
1872 struct drm_device *dev = crtc->base.dev;
1873 struct drm_i915_private *dev_priv = to_i915(dev);
1874 enum pipe pipe = crtc->pipe;
1875 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1876 i915_reg_t reg;
1877 u32 val;
1878
1879 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1880
1881 assert_planes_disabled(dev_priv, pipe);
1882 assert_cursor_disabled(dev_priv, pipe);
1883 assert_sprites_disabled(dev_priv, pipe);
1884
1885 /*
1886 * A pipe without a PLL won't actually be able to drive bits from
1887 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1888 * need the check.
1889 */
1890 if (HAS_GMCH_DISPLAY(dev_priv)) {
1891 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1892 assert_dsi_pll_enabled(dev_priv);
1893 else
1894 assert_pll_enabled(dev_priv, pipe);
1895 } else {
1896 if (crtc->config->has_pch_encoder) {
1897 /* if driving the PCH, we need FDI enabled */
1898 assert_fdi_rx_pll_enabled(dev_priv,
1899 intel_crtc_pch_transcoder(crtc));
1900 assert_fdi_tx_pll_enabled(dev_priv,
1901 (enum pipe) cpu_transcoder);
1902 }
1903 /* FIXME: assert CPU port conditions for SNB+ */
1904 }
1905
1906 reg = PIPECONF(cpu_transcoder);
1907 val = I915_READ(reg);
1908 if (val & PIPECONF_ENABLE) {
1909 /* we keep both pipes enabled on 830 */
1910 WARN_ON(!IS_I830(dev_priv));
1911 return;
1912 }
1913
1914 I915_WRITE(reg, val | PIPECONF_ENABLE);
1915 POSTING_READ(reg);
1916
1917 /*
1918 * Until the pipe starts DSL will read as 0, which would cause
1919 * an apparent vblank timestamp jump, which messes up also the
1920 * frame count when it's derived from the timestamps. So let's
1921 * wait for the pipe to start properly before we call
1922 * drm_crtc_vblank_on()
1923 */
1924 if (dev->max_vblank_count == 0 &&
1925 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1926 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1927 }
1928
1929 /**
1930 * intel_disable_pipe - disable a pipe, asserting requirements
1931 * @crtc: crtc whose pipes is to be disabled
1932 *
1933 * Disable the pipe of @crtc, making sure that various hardware
1934 * specific requirements are met, if applicable, e.g. plane
1935 * disabled, panel fitter off, etc.
1936 *
1937 * Will wait until the pipe has shut down before returning.
1938 */
1939 static void intel_disable_pipe(struct intel_crtc *crtc)
1940 {
1941 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1942 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1943 enum pipe pipe = crtc->pipe;
1944 i915_reg_t reg;
1945 u32 val;
1946
1947 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1948
1949 /*
1950 * Make sure planes won't keep trying to pump pixels to us,
1951 * or we might hang the display.
1952 */
1953 assert_planes_disabled(dev_priv, pipe);
1954 assert_cursor_disabled(dev_priv, pipe);
1955 assert_sprites_disabled(dev_priv, pipe);
1956
1957 reg = PIPECONF(cpu_transcoder);
1958 val = I915_READ(reg);
1959 if ((val & PIPECONF_ENABLE) == 0)
1960 return;
1961
1962 /*
1963 * Double wide has implications for planes
1964 * so best keep it disabled when not needed.
1965 */
1966 if (crtc->config->double_wide)
1967 val &= ~PIPECONF_DOUBLE_WIDE;
1968
1969 /* Don't disable pipe or pipe PLLs if needed */
1970 if (!IS_I830(dev_priv))
1971 val &= ~PIPECONF_ENABLE;
1972
1973 I915_WRITE(reg, val);
1974 if ((val & PIPECONF_ENABLE) == 0)
1975 intel_wait_for_pipe_off(crtc);
1976 }
1977
1978 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1979 {
1980 return IS_GEN2(dev_priv) ? 2048 : 4096;
1981 }
1982
1983 static unsigned int
1984 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1985 {
1986 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1987 unsigned int cpp = fb->format->cpp[plane];
1988
1989 switch (fb->modifier) {
1990 case DRM_FORMAT_MOD_LINEAR:
1991 return cpp;
1992 case I915_FORMAT_MOD_X_TILED:
1993 if (IS_GEN2(dev_priv))
1994 return 128;
1995 else
1996 return 512;
1997 case I915_FORMAT_MOD_Y_TILED:
1998 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Yf_TILED:
2003 switch (cpp) {
2004 case 1:
2005 return 64;
2006 case 2:
2007 case 4:
2008 return 128;
2009 case 8:
2010 case 16:
2011 return 256;
2012 default:
2013 MISSING_CASE(cpp);
2014 return cpp;
2015 }
2016 break;
2017 default:
2018 MISSING_CASE(fb->modifier);
2019 return cpp;
2020 }
2021 }
2022
2023 static unsigned int
2024 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2025 {
2026 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2027 return 1;
2028 else
2029 return intel_tile_size(to_i915(fb->dev)) /
2030 intel_tile_width_bytes(fb, plane);
2031 }
2032
2033 /* Return the tile dimensions in pixel units */
2034 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2035 unsigned int *tile_width,
2036 unsigned int *tile_height)
2037 {
2038 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2039 unsigned int cpp = fb->format->cpp[plane];
2040
2041 *tile_width = tile_width_bytes / cpp;
2042 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2043 }
2044
2045 unsigned int
2046 intel_fb_align_height(const struct drm_framebuffer *fb,
2047 int plane, unsigned int height)
2048 {
2049 unsigned int tile_height = intel_tile_height(fb, plane);
2050
2051 return ALIGN(height, tile_height);
2052 }
2053
2054 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2055 {
2056 unsigned int size = 0;
2057 int i;
2058
2059 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2060 size += rot_info->plane[i].width * rot_info->plane[i].height;
2061
2062 return size;
2063 }
2064
2065 static void
2066 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2067 const struct drm_framebuffer *fb,
2068 unsigned int rotation)
2069 {
2070 view->type = I915_GGTT_VIEW_NORMAL;
2071 if (drm_rotation_90_or_270(rotation)) {
2072 view->type = I915_GGTT_VIEW_ROTATED;
2073 view->rotated = to_intel_framebuffer(fb)->rot_info;
2074 }
2075 }
2076
2077 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2078 {
2079 if (IS_I830(dev_priv))
2080 return 16 * 1024;
2081 else if (IS_I85X(dev_priv))
2082 return 256;
2083 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2084 return 32;
2085 else
2086 return 4 * 1024;
2087 }
2088
2089 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2090 {
2091 if (INTEL_INFO(dev_priv)->gen >= 9)
2092 return 256 * 1024;
2093 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2094 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2095 return 128 * 1024;
2096 else if (INTEL_INFO(dev_priv)->gen >= 4)
2097 return 4 * 1024;
2098 else
2099 return 0;
2100 }
2101
2102 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2103 int plane)
2104 {
2105 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2106
2107 /* AUX_DIST needs only 4K alignment */
2108 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2109 return 4096;
2110
2111 switch (fb->modifier) {
2112 case DRM_FORMAT_MOD_LINEAR:
2113 return intel_linear_alignment(dev_priv);
2114 case I915_FORMAT_MOD_X_TILED:
2115 if (INTEL_GEN(dev_priv) >= 9)
2116 return 256 * 1024;
2117 return 0;
2118 case I915_FORMAT_MOD_Y_TILED:
2119 case I915_FORMAT_MOD_Yf_TILED:
2120 return 1 * 1024 * 1024;
2121 default:
2122 MISSING_CASE(fb->modifier);
2123 return 0;
2124 }
2125 }
2126
2127 struct i915_vma *
2128 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2129 {
2130 struct drm_device *dev = fb->dev;
2131 struct drm_i915_private *dev_priv = to_i915(dev);
2132 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2133 struct i915_ggtt_view view;
2134 struct i915_vma *vma;
2135 u32 alignment;
2136
2137 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2138
2139 alignment = intel_surf_alignment(fb, 0);
2140
2141 intel_fill_fb_ggtt_view(&view, fb, rotation);
2142
2143 /* Note that the w/a also requires 64 PTE of padding following the
2144 * bo. We currently fill all unused PTE with the shadow page and so
2145 * we should always have valid PTE following the scanout preventing
2146 * the VT-d warning.
2147 */
2148 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2149 alignment = 256 * 1024;
2150
2151 /*
2152 * Global gtt pte registers are special registers which actually forward
2153 * writes to a chunk of system memory. Which means that there is no risk
2154 * that the register values disappear as soon as we call
2155 * intel_runtime_pm_put(), so it is correct to wrap only the
2156 * pin/unpin/fence and not more.
2157 */
2158 intel_runtime_pm_get(dev_priv);
2159
2160 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2161 if (IS_ERR(vma))
2162 goto err;
2163
2164 if (i915_vma_is_map_and_fenceable(vma)) {
2165 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2166 * fence, whereas 965+ only requires a fence if using
2167 * framebuffer compression. For simplicity, we always, when
2168 * possible, install a fence as the cost is not that onerous.
2169 *
2170 * If we fail to fence the tiled scanout, then either the
2171 * modeset will reject the change (which is highly unlikely as
2172 * the affected systems, all but one, do not have unmappable
2173 * space) or we will not be able to enable full powersaving
2174 * techniques (also likely not to apply due to various limits
2175 * FBC and the like impose on the size of the buffer, which
2176 * presumably we violated anyway with this unmappable buffer).
2177 * Anyway, it is presumably better to stumble onwards with
2178 * something and try to run the system in a "less than optimal"
2179 * mode that matches the user configuration.
2180 */
2181 if (i915_vma_get_fence(vma) == 0)
2182 i915_vma_pin_fence(vma);
2183 }
2184
2185 i915_vma_get(vma);
2186 err:
2187 intel_runtime_pm_put(dev_priv);
2188 return vma;
2189 }
2190
2191 void intel_unpin_fb_vma(struct i915_vma *vma)
2192 {
2193 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2194
2195 i915_vma_unpin_fence(vma);
2196 i915_gem_object_unpin_from_display_plane(vma);
2197 i915_vma_put(vma);
2198 }
2199
2200 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2201 unsigned int rotation)
2202 {
2203 if (drm_rotation_90_or_270(rotation))
2204 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2205 else
2206 return fb->pitches[plane];
2207 }
2208
2209 /*
2210 * Convert the x/y offsets into a linear offset.
2211 * Only valid with 0/180 degree rotation, which is fine since linear
2212 * offset is only used with linear buffers on pre-hsw and tiled buffers
2213 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2214 */
2215 u32 intel_fb_xy_to_linear(int x, int y,
2216 const struct intel_plane_state *state,
2217 int plane)
2218 {
2219 const struct drm_framebuffer *fb = state->base.fb;
2220 unsigned int cpp = fb->format->cpp[plane];
2221 unsigned int pitch = fb->pitches[plane];
2222
2223 return y * pitch + x * cpp;
2224 }
2225
2226 /*
2227 * Add the x/y offsets derived from fb->offsets[] to the user
2228 * specified plane src x/y offsets. The resulting x/y offsets
2229 * specify the start of scanout from the beginning of the gtt mapping.
2230 */
2231 void intel_add_fb_offsets(int *x, int *y,
2232 const struct intel_plane_state *state,
2233 int plane)
2234
2235 {
2236 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2237 unsigned int rotation = state->base.rotation;
2238
2239 if (drm_rotation_90_or_270(rotation)) {
2240 *x += intel_fb->rotated[plane].x;
2241 *y += intel_fb->rotated[plane].y;
2242 } else {
2243 *x += intel_fb->normal[plane].x;
2244 *y += intel_fb->normal[plane].y;
2245 }
2246 }
2247
2248 /*
2249 * Input tile dimensions and pitch must already be
2250 * rotated to match x and y, and in pixel units.
2251 */
2252 static u32 _intel_adjust_tile_offset(int *x, int *y,
2253 unsigned int tile_width,
2254 unsigned int tile_height,
2255 unsigned int tile_size,
2256 unsigned int pitch_tiles,
2257 u32 old_offset,
2258 u32 new_offset)
2259 {
2260 unsigned int pitch_pixels = pitch_tiles * tile_width;
2261 unsigned int tiles;
2262
2263 WARN_ON(old_offset & (tile_size - 1));
2264 WARN_ON(new_offset & (tile_size - 1));
2265 WARN_ON(new_offset > old_offset);
2266
2267 tiles = (old_offset - new_offset) / tile_size;
2268
2269 *y += tiles / pitch_tiles * tile_height;
2270 *x += tiles % pitch_tiles * tile_width;
2271
2272 /* minimize x in case it got needlessly big */
2273 *y += *x / pitch_pixels * tile_height;
2274 *x %= pitch_pixels;
2275
2276 return new_offset;
2277 }
2278
2279 /*
2280 * Adjust the tile offset by moving the difference into
2281 * the x/y offsets.
2282 */
2283 static u32 intel_adjust_tile_offset(int *x, int *y,
2284 const struct intel_plane_state *state, int plane,
2285 u32 old_offset, u32 new_offset)
2286 {
2287 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2288 const struct drm_framebuffer *fb = state->base.fb;
2289 unsigned int cpp = fb->format->cpp[plane];
2290 unsigned int rotation = state->base.rotation;
2291 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2292
2293 WARN_ON(new_offset > old_offset);
2294
2295 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2296 unsigned int tile_size, tile_width, tile_height;
2297 unsigned int pitch_tiles;
2298
2299 tile_size = intel_tile_size(dev_priv);
2300 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2301
2302 if (drm_rotation_90_or_270(rotation)) {
2303 pitch_tiles = pitch / tile_height;
2304 swap(tile_width, tile_height);
2305 } else {
2306 pitch_tiles = pitch / (tile_width * cpp);
2307 }
2308
2309 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2310 tile_size, pitch_tiles,
2311 old_offset, new_offset);
2312 } else {
2313 old_offset += *y * pitch + *x * cpp;
2314
2315 *y = (old_offset - new_offset) / pitch;
2316 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2317 }
2318
2319 return new_offset;
2320 }
2321
2322 /*
2323 * Computes the linear offset to the base tile and adjusts
2324 * x, y. bytes per pixel is assumed to be a power-of-two.
2325 *
2326 * In the 90/270 rotated case, x and y are assumed
2327 * to be already rotated to match the rotated GTT view, and
2328 * pitch is the tile_height aligned framebuffer height.
2329 *
2330 * This function is used when computing the derived information
2331 * under intel_framebuffer, so using any of that information
2332 * here is not allowed. Anything under drm_framebuffer can be
2333 * used. This is why the user has to pass in the pitch since it
2334 * is specified in the rotated orientation.
2335 */
2336 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2337 int *x, int *y,
2338 const struct drm_framebuffer *fb, int plane,
2339 unsigned int pitch,
2340 unsigned int rotation,
2341 u32 alignment)
2342 {
2343 uint64_t fb_modifier = fb->modifier;
2344 unsigned int cpp = fb->format->cpp[plane];
2345 u32 offset, offset_aligned;
2346
2347 if (alignment)
2348 alignment--;
2349
2350 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2351 unsigned int tile_size, tile_width, tile_height;
2352 unsigned int tile_rows, tiles, pitch_tiles;
2353
2354 tile_size = intel_tile_size(dev_priv);
2355 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2356
2357 if (drm_rotation_90_or_270(rotation)) {
2358 pitch_tiles = pitch / tile_height;
2359 swap(tile_width, tile_height);
2360 } else {
2361 pitch_tiles = pitch / (tile_width * cpp);
2362 }
2363
2364 tile_rows = *y / tile_height;
2365 *y %= tile_height;
2366
2367 tiles = *x / tile_width;
2368 *x %= tile_width;
2369
2370 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2371 offset_aligned = offset & ~alignment;
2372
2373 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2374 tile_size, pitch_tiles,
2375 offset, offset_aligned);
2376 } else {
2377 offset = *y * pitch + *x * cpp;
2378 offset_aligned = offset & ~alignment;
2379
2380 *y = (offset & alignment) / pitch;
2381 *x = ((offset & alignment) - *y * pitch) / cpp;
2382 }
2383
2384 return offset_aligned;
2385 }
2386
2387 u32 intel_compute_tile_offset(int *x, int *y,
2388 const struct intel_plane_state *state,
2389 int plane)
2390 {
2391 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2392 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2393 const struct drm_framebuffer *fb = state->base.fb;
2394 unsigned int rotation = state->base.rotation;
2395 int pitch = intel_fb_pitch(fb, plane, rotation);
2396 u32 alignment;
2397
2398 if (intel_plane->id == PLANE_CURSOR)
2399 alignment = intel_cursor_alignment(dev_priv);
2400 else
2401 alignment = intel_surf_alignment(fb, plane);
2402
2403 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2404 rotation, alignment);
2405 }
2406
2407 /* Convert the fb->offset[] linear offset into x/y offsets */
2408 static void intel_fb_offset_to_xy(int *x, int *y,
2409 const struct drm_framebuffer *fb, int plane)
2410 {
2411 unsigned int cpp = fb->format->cpp[plane];
2412 unsigned int pitch = fb->pitches[plane];
2413 u32 linear_offset = fb->offsets[plane];
2414
2415 *y = linear_offset / pitch;
2416 *x = linear_offset % pitch / cpp;
2417 }
2418
2419 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2420 {
2421 switch (fb_modifier) {
2422 case I915_FORMAT_MOD_X_TILED:
2423 return I915_TILING_X;
2424 case I915_FORMAT_MOD_Y_TILED:
2425 return I915_TILING_Y;
2426 default:
2427 return I915_TILING_NONE;
2428 }
2429 }
2430
2431 static int
2432 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2433 struct drm_framebuffer *fb)
2434 {
2435 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2436 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2437 u32 gtt_offset_rotated = 0;
2438 unsigned int max_size = 0;
2439 int i, num_planes = fb->format->num_planes;
2440 unsigned int tile_size = intel_tile_size(dev_priv);
2441
2442 for (i = 0; i < num_planes; i++) {
2443 unsigned int width, height;
2444 unsigned int cpp, size;
2445 u32 offset;
2446 int x, y;
2447
2448 cpp = fb->format->cpp[i];
2449 width = drm_framebuffer_plane_width(fb->width, fb, i);
2450 height = drm_framebuffer_plane_height(fb->height, fb, i);
2451
2452 intel_fb_offset_to_xy(&x, &y, fb, i);
2453
2454 /*
2455 * The fence (if used) is aligned to the start of the object
2456 * so having the framebuffer wrap around across the edge of the
2457 * fenced region doesn't really work. We have no API to configure
2458 * the fence start offset within the object (nor could we probably
2459 * on gen2/3). So it's just easier if we just require that the
2460 * fb layout agrees with the fence layout. We already check that the
2461 * fb stride matches the fence stride elsewhere.
2462 */
2463 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2464 (x + width) * cpp > fb->pitches[i]) {
2465 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2466 i, fb->offsets[i]);
2467 return -EINVAL;
2468 }
2469
2470 /*
2471 * First pixel of the framebuffer from
2472 * the start of the normal gtt mapping.
2473 */
2474 intel_fb->normal[i].x = x;
2475 intel_fb->normal[i].y = y;
2476
2477 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2478 fb, i, fb->pitches[i],
2479 DRM_MODE_ROTATE_0, tile_size);
2480 offset /= tile_size;
2481
2482 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2483 unsigned int tile_width, tile_height;
2484 unsigned int pitch_tiles;
2485 struct drm_rect r;
2486
2487 intel_tile_dims(fb, i, &tile_width, &tile_height);
2488
2489 rot_info->plane[i].offset = offset;
2490 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2491 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2492 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2493
2494 intel_fb->rotated[i].pitch =
2495 rot_info->plane[i].height * tile_height;
2496
2497 /* how many tiles does this plane need */
2498 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2499 /*
2500 * If the plane isn't horizontally tile aligned,
2501 * we need one more tile.
2502 */
2503 if (x != 0)
2504 size++;
2505
2506 /* rotate the x/y offsets to match the GTT view */
2507 r.x1 = x;
2508 r.y1 = y;
2509 r.x2 = x + width;
2510 r.y2 = y + height;
2511 drm_rect_rotate(&r,
2512 rot_info->plane[i].width * tile_width,
2513 rot_info->plane[i].height * tile_height,
2514 DRM_MODE_ROTATE_270);
2515 x = r.x1;
2516 y = r.y1;
2517
2518 /* rotate the tile dimensions to match the GTT view */
2519 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2520 swap(tile_width, tile_height);
2521
2522 /*
2523 * We only keep the x/y offsets, so push all of the
2524 * gtt offset into the x/y offsets.
2525 */
2526 _intel_adjust_tile_offset(&x, &y,
2527 tile_width, tile_height,
2528 tile_size, pitch_tiles,
2529 gtt_offset_rotated * tile_size, 0);
2530
2531 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2532
2533 /*
2534 * First pixel of the framebuffer from
2535 * the start of the rotated gtt mapping.
2536 */
2537 intel_fb->rotated[i].x = x;
2538 intel_fb->rotated[i].y = y;
2539 } else {
2540 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2541 x * cpp, tile_size);
2542 }
2543
2544 /* how many tiles in total needed in the bo */
2545 max_size = max(max_size, offset + size);
2546 }
2547
2548 if (max_size * tile_size > intel_fb->obj->base.size) {
2549 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2550 max_size * tile_size, intel_fb->obj->base.size);
2551 return -EINVAL;
2552 }
2553
2554 return 0;
2555 }
2556
2557 static int i9xx_format_to_fourcc(int format)
2558 {
2559 switch (format) {
2560 case DISPPLANE_8BPP:
2561 return DRM_FORMAT_C8;
2562 case DISPPLANE_BGRX555:
2563 return DRM_FORMAT_XRGB1555;
2564 case DISPPLANE_BGRX565:
2565 return DRM_FORMAT_RGB565;
2566 default:
2567 case DISPPLANE_BGRX888:
2568 return DRM_FORMAT_XRGB8888;
2569 case DISPPLANE_RGBX888:
2570 return DRM_FORMAT_XBGR8888;
2571 case DISPPLANE_BGRX101010:
2572 return DRM_FORMAT_XRGB2101010;
2573 case DISPPLANE_RGBX101010:
2574 return DRM_FORMAT_XBGR2101010;
2575 }
2576 }
2577
2578 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2579 {
2580 switch (format) {
2581 case PLANE_CTL_FORMAT_RGB_565:
2582 return DRM_FORMAT_RGB565;
2583 default:
2584 case PLANE_CTL_FORMAT_XRGB_8888:
2585 if (rgb_order) {
2586 if (alpha)
2587 return DRM_FORMAT_ABGR8888;
2588 else
2589 return DRM_FORMAT_XBGR8888;
2590 } else {
2591 if (alpha)
2592 return DRM_FORMAT_ARGB8888;
2593 else
2594 return DRM_FORMAT_XRGB8888;
2595 }
2596 case PLANE_CTL_FORMAT_XRGB_2101010:
2597 if (rgb_order)
2598 return DRM_FORMAT_XBGR2101010;
2599 else
2600 return DRM_FORMAT_XRGB2101010;
2601 }
2602 }
2603
2604 static bool
2605 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2606 struct intel_initial_plane_config *plane_config)
2607 {
2608 struct drm_device *dev = crtc->base.dev;
2609 struct drm_i915_private *dev_priv = to_i915(dev);
2610 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2611 struct drm_i915_gem_object *obj = NULL;
2612 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2613 struct drm_framebuffer *fb = &plane_config->fb->base;
2614 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2615 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2616 PAGE_SIZE);
2617
2618 size_aligned -= base_aligned;
2619
2620 if (plane_config->size == 0)
2621 return false;
2622
2623 /* If the FB is too big, just don't use it since fbdev is not very
2624 * important and we should probably use that space with FBC or other
2625 * features. */
2626 if (size_aligned * 2 > ggtt->stolen_usable_size)
2627 return false;
2628
2629 mutex_lock(&dev->struct_mutex);
2630 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2631 base_aligned,
2632 base_aligned,
2633 size_aligned);
2634 mutex_unlock(&dev->struct_mutex);
2635 if (!obj)
2636 return false;
2637
2638 if (plane_config->tiling == I915_TILING_X)
2639 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2640
2641 mode_cmd.pixel_format = fb->format->format;
2642 mode_cmd.width = fb->width;
2643 mode_cmd.height = fb->height;
2644 mode_cmd.pitches[0] = fb->pitches[0];
2645 mode_cmd.modifier[0] = fb->modifier;
2646 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2647
2648 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2649 DRM_DEBUG_KMS("intel fb init failed\n");
2650 goto out_unref_obj;
2651 }
2652
2653
2654 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2655 return true;
2656
2657 out_unref_obj:
2658 i915_gem_object_put(obj);
2659 return false;
2660 }
2661
2662 static void
2663 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2664 struct intel_plane_state *plane_state,
2665 bool visible)
2666 {
2667 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2668
2669 plane_state->base.visible = visible;
2670
2671 /* FIXME pre-g4x don't work like this */
2672 if (visible) {
2673 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2674 crtc_state->active_planes |= BIT(plane->id);
2675 } else {
2676 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2677 crtc_state->active_planes &= ~BIT(plane->id);
2678 }
2679
2680 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2681 crtc_state->base.crtc->name,
2682 crtc_state->active_planes);
2683 }
2684
2685 static void
2686 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2687 struct intel_initial_plane_config *plane_config)
2688 {
2689 struct drm_device *dev = intel_crtc->base.dev;
2690 struct drm_i915_private *dev_priv = to_i915(dev);
2691 struct drm_crtc *c;
2692 struct drm_i915_gem_object *obj;
2693 struct drm_plane *primary = intel_crtc->base.primary;
2694 struct drm_plane_state *plane_state = primary->state;
2695 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2696 struct intel_plane *intel_plane = to_intel_plane(primary);
2697 struct intel_plane_state *intel_state =
2698 to_intel_plane_state(plane_state);
2699 struct drm_framebuffer *fb;
2700
2701 if (!plane_config->fb)
2702 return;
2703
2704 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2705 fb = &plane_config->fb->base;
2706 goto valid_fb;
2707 }
2708
2709 kfree(plane_config->fb);
2710
2711 /*
2712 * Failed to alloc the obj, check to see if we should share
2713 * an fb with another CRTC instead
2714 */
2715 for_each_crtc(dev, c) {
2716 struct intel_plane_state *state;
2717
2718 if (c == &intel_crtc->base)
2719 continue;
2720
2721 if (!to_intel_crtc(c)->active)
2722 continue;
2723
2724 state = to_intel_plane_state(c->primary->state);
2725 if (!state->vma)
2726 continue;
2727
2728 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2729 fb = c->primary->fb;
2730 drm_framebuffer_reference(fb);
2731 goto valid_fb;
2732 }
2733 }
2734
2735 /*
2736 * We've failed to reconstruct the BIOS FB. Current display state
2737 * indicates that the primary plane is visible, but has a NULL FB,
2738 * which will lead to problems later if we don't fix it up. The
2739 * simplest solution is to just disable the primary plane now and
2740 * pretend the BIOS never had it enabled.
2741 */
2742 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2743 to_intel_plane_state(plane_state),
2744 false);
2745 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2746 trace_intel_disable_plane(primary, intel_crtc);
2747 intel_plane->disable_plane(intel_plane, intel_crtc);
2748
2749 return;
2750
2751 valid_fb:
2752 mutex_lock(&dev->struct_mutex);
2753 intel_state->vma =
2754 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2755 mutex_unlock(&dev->struct_mutex);
2756 if (IS_ERR(intel_state->vma)) {
2757 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2758 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2759
2760 intel_state->vma = NULL;
2761 drm_framebuffer_unreference(fb);
2762 return;
2763 }
2764
2765 plane_state->src_x = 0;
2766 plane_state->src_y = 0;
2767 plane_state->src_w = fb->width << 16;
2768 plane_state->src_h = fb->height << 16;
2769
2770 plane_state->crtc_x = 0;
2771 plane_state->crtc_y = 0;
2772 plane_state->crtc_w = fb->width;
2773 plane_state->crtc_h = fb->height;
2774
2775 intel_state->base.src = drm_plane_state_src(plane_state);
2776 intel_state->base.dst = drm_plane_state_dest(plane_state);
2777
2778 obj = intel_fb_obj(fb);
2779 if (i915_gem_object_is_tiled(obj))
2780 dev_priv->preserve_bios_swizzle = true;
2781
2782 drm_framebuffer_reference(fb);
2783 primary->fb = primary->state->fb = fb;
2784 primary->crtc = primary->state->crtc = &intel_crtc->base;
2785
2786 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2787 to_intel_plane_state(plane_state),
2788 true);
2789
2790 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2791 &obj->frontbuffer_bits);
2792 }
2793
2794 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2795 unsigned int rotation)
2796 {
2797 int cpp = fb->format->cpp[plane];
2798
2799 switch (fb->modifier) {
2800 case DRM_FORMAT_MOD_LINEAR:
2801 case I915_FORMAT_MOD_X_TILED:
2802 switch (cpp) {
2803 case 8:
2804 return 4096;
2805 case 4:
2806 case 2:
2807 case 1:
2808 return 8192;
2809 default:
2810 MISSING_CASE(cpp);
2811 break;
2812 }
2813 break;
2814 case I915_FORMAT_MOD_Y_TILED:
2815 case I915_FORMAT_MOD_Yf_TILED:
2816 switch (cpp) {
2817 case 8:
2818 return 2048;
2819 case 4:
2820 return 4096;
2821 case 2:
2822 case 1:
2823 return 8192;
2824 default:
2825 MISSING_CASE(cpp);
2826 break;
2827 }
2828 break;
2829 default:
2830 MISSING_CASE(fb->modifier);
2831 }
2832
2833 return 2048;
2834 }
2835
2836 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2837 {
2838 const struct drm_framebuffer *fb = plane_state->base.fb;
2839 unsigned int rotation = plane_state->base.rotation;
2840 int x = plane_state->base.src.x1 >> 16;
2841 int y = plane_state->base.src.y1 >> 16;
2842 int w = drm_rect_width(&plane_state->base.src) >> 16;
2843 int h = drm_rect_height(&plane_state->base.src) >> 16;
2844 int max_width = skl_max_plane_width(fb, 0, rotation);
2845 int max_height = 4096;
2846 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2847
2848 if (w > max_width || h > max_height) {
2849 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2850 w, h, max_width, max_height);
2851 return -EINVAL;
2852 }
2853
2854 intel_add_fb_offsets(&x, &y, plane_state, 0);
2855 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2856 alignment = intel_surf_alignment(fb, 0);
2857
2858 /*
2859 * AUX surface offset is specified as the distance from the
2860 * main surface offset, and it must be non-negative. Make
2861 * sure that is what we will get.
2862 */
2863 if (offset > aux_offset)
2864 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2865 offset, aux_offset & ~(alignment - 1));
2866
2867 /*
2868 * When using an X-tiled surface, the plane blows up
2869 * if the x offset + width exceed the stride.
2870 *
2871 * TODO: linear and Y-tiled seem fine, Yf untested,
2872 */
2873 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2874 int cpp = fb->format->cpp[0];
2875
2876 while ((x + w) * cpp > fb->pitches[0]) {
2877 if (offset == 0) {
2878 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2879 return -EINVAL;
2880 }
2881
2882 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2883 offset, offset - alignment);
2884 }
2885 }
2886
2887 plane_state->main.offset = offset;
2888 plane_state->main.x = x;
2889 plane_state->main.y = y;
2890
2891 return 0;
2892 }
2893
2894 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2895 {
2896 const struct drm_framebuffer *fb = plane_state->base.fb;
2897 unsigned int rotation = plane_state->base.rotation;
2898 int max_width = skl_max_plane_width(fb, 1, rotation);
2899 int max_height = 4096;
2900 int x = plane_state->base.src.x1 >> 17;
2901 int y = plane_state->base.src.y1 >> 17;
2902 int w = drm_rect_width(&plane_state->base.src) >> 17;
2903 int h = drm_rect_height(&plane_state->base.src) >> 17;
2904 u32 offset;
2905
2906 intel_add_fb_offsets(&x, &y, plane_state, 1);
2907 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2908
2909 /* FIXME not quite sure how/if these apply to the chroma plane */
2910 if (w > max_width || h > max_height) {
2911 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2912 w, h, max_width, max_height);
2913 return -EINVAL;
2914 }
2915
2916 plane_state->aux.offset = offset;
2917 plane_state->aux.x = x;
2918 plane_state->aux.y = y;
2919
2920 return 0;
2921 }
2922
2923 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2924 {
2925 const struct drm_framebuffer *fb = plane_state->base.fb;
2926 unsigned int rotation = plane_state->base.rotation;
2927 int ret;
2928
2929 if (!plane_state->base.visible)
2930 return 0;
2931
2932 /* Rotate src coordinates to match rotated GTT view */
2933 if (drm_rotation_90_or_270(rotation))
2934 drm_rect_rotate(&plane_state->base.src,
2935 fb->width << 16, fb->height << 16,
2936 DRM_MODE_ROTATE_270);
2937
2938 /*
2939 * Handle the AUX surface first since
2940 * the main surface setup depends on it.
2941 */
2942 if (fb->format->format == DRM_FORMAT_NV12) {
2943 ret = skl_check_nv12_aux_surface(plane_state);
2944 if (ret)
2945 return ret;
2946 } else {
2947 plane_state->aux.offset = ~0xfff;
2948 plane_state->aux.x = 0;
2949 plane_state->aux.y = 0;
2950 }
2951
2952 ret = skl_check_main_surface(plane_state);
2953 if (ret)
2954 return ret;
2955
2956 return 0;
2957 }
2958
2959 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2960 const struct intel_plane_state *plane_state)
2961 {
2962 struct drm_i915_private *dev_priv =
2963 to_i915(plane_state->base.plane->dev);
2964 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2965 const struct drm_framebuffer *fb = plane_state->base.fb;
2966 unsigned int rotation = plane_state->base.rotation;
2967 u32 dspcntr;
2968
2969 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2970
2971 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2972 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2973 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2974
2975 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2976 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2977
2978 if (INTEL_GEN(dev_priv) < 4)
2979 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2980
2981 switch (fb->format->format) {
2982 case DRM_FORMAT_C8:
2983 dspcntr |= DISPPLANE_8BPP;
2984 break;
2985 case DRM_FORMAT_XRGB1555:
2986 dspcntr |= DISPPLANE_BGRX555;
2987 break;
2988 case DRM_FORMAT_RGB565:
2989 dspcntr |= DISPPLANE_BGRX565;
2990 break;
2991 case DRM_FORMAT_XRGB8888:
2992 dspcntr |= DISPPLANE_BGRX888;
2993 break;
2994 case DRM_FORMAT_XBGR8888:
2995 dspcntr |= DISPPLANE_RGBX888;
2996 break;
2997 case DRM_FORMAT_XRGB2101010:
2998 dspcntr |= DISPPLANE_BGRX101010;
2999 break;
3000 case DRM_FORMAT_XBGR2101010:
3001 dspcntr |= DISPPLANE_RGBX101010;
3002 break;
3003 default:
3004 MISSING_CASE(fb->format->format);
3005 return 0;
3006 }
3007
3008 if (INTEL_GEN(dev_priv) >= 4 &&
3009 fb->modifier == I915_FORMAT_MOD_X_TILED)
3010 dspcntr |= DISPPLANE_TILED;
3011
3012 if (rotation & DRM_MODE_ROTATE_180)
3013 dspcntr |= DISPPLANE_ROTATE_180;
3014
3015 if (rotation & DRM_MODE_REFLECT_X)
3016 dspcntr |= DISPPLANE_MIRROR;
3017
3018 return dspcntr;
3019 }
3020
3021 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3022 {
3023 struct drm_i915_private *dev_priv =
3024 to_i915(plane_state->base.plane->dev);
3025 int src_x = plane_state->base.src.x1 >> 16;
3026 int src_y = plane_state->base.src.y1 >> 16;
3027 u32 offset;
3028
3029 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3030
3031 if (INTEL_GEN(dev_priv) >= 4)
3032 offset = intel_compute_tile_offset(&src_x, &src_y,
3033 plane_state, 0);
3034 else
3035 offset = 0;
3036
3037 /* HSW/BDW do this automagically in hardware */
3038 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3039 unsigned int rotation = plane_state->base.rotation;
3040 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3041 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3042
3043 if (rotation & DRM_MODE_ROTATE_180) {
3044 src_x += src_w - 1;
3045 src_y += src_h - 1;
3046 } else if (rotation & DRM_MODE_REFLECT_X) {
3047 src_x += src_w - 1;
3048 }
3049 }
3050
3051 plane_state->main.offset = offset;
3052 plane_state->main.x = src_x;
3053 plane_state->main.y = src_y;
3054
3055 return 0;
3056 }
3057
3058 static void i9xx_update_primary_plane(struct intel_plane *primary,
3059 const struct intel_crtc_state *crtc_state,
3060 const struct intel_plane_state *plane_state)
3061 {
3062 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3063 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3064 const struct drm_framebuffer *fb = plane_state->base.fb;
3065 enum plane plane = primary->plane;
3066 u32 linear_offset;
3067 u32 dspcntr = plane_state->ctl;
3068 i915_reg_t reg = DSPCNTR(plane);
3069 int x = plane_state->main.x;
3070 int y = plane_state->main.y;
3071 unsigned long irqflags;
3072
3073 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3074
3075 if (INTEL_GEN(dev_priv) >= 4)
3076 crtc->dspaddr_offset = plane_state->main.offset;
3077 else
3078 crtc->dspaddr_offset = linear_offset;
3079
3080 crtc->adjusted_x = x;
3081 crtc->adjusted_y = y;
3082
3083 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3084
3085 if (INTEL_GEN(dev_priv) < 4) {
3086 /* pipesrc and dspsize control the size that is scaled from,
3087 * which should always be the user's requested size.
3088 */
3089 I915_WRITE_FW(DSPSIZE(plane),
3090 ((crtc_state->pipe_src_h - 1) << 16) |
3091 (crtc_state->pipe_src_w - 1));
3092 I915_WRITE_FW(DSPPOS(plane), 0);
3093 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3094 I915_WRITE_FW(PRIMSIZE(plane),
3095 ((crtc_state->pipe_src_h - 1) << 16) |
3096 (crtc_state->pipe_src_w - 1));
3097 I915_WRITE_FW(PRIMPOS(plane), 0);
3098 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3099 }
3100
3101 I915_WRITE_FW(reg, dspcntr);
3102
3103 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3104 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3105 I915_WRITE_FW(DSPSURF(plane),
3106 intel_plane_ggtt_offset(plane_state) +
3107 crtc->dspaddr_offset);
3108 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3109 } else if (INTEL_GEN(dev_priv) >= 4) {
3110 I915_WRITE_FW(DSPSURF(plane),
3111 intel_plane_ggtt_offset(plane_state) +
3112 crtc->dspaddr_offset);
3113 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3114 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3115 } else {
3116 I915_WRITE_FW(DSPADDR(plane),
3117 intel_plane_ggtt_offset(plane_state) +
3118 crtc->dspaddr_offset);
3119 }
3120 POSTING_READ_FW(reg);
3121
3122 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3123 }
3124
3125 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3126 struct intel_crtc *crtc)
3127 {
3128 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3129 enum plane plane = primary->plane;
3130 unsigned long irqflags;
3131
3132 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3133
3134 I915_WRITE_FW(DSPCNTR(plane), 0);
3135 if (INTEL_INFO(dev_priv)->gen >= 4)
3136 I915_WRITE_FW(DSPSURF(plane), 0);
3137 else
3138 I915_WRITE_FW(DSPADDR(plane), 0);
3139 POSTING_READ_FW(DSPCNTR(plane));
3140
3141 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3142 }
3143
3144 static u32
3145 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3146 {
3147 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3148 return 64;
3149 else
3150 return intel_tile_width_bytes(fb, plane);
3151 }
3152
3153 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3154 {
3155 struct drm_device *dev = intel_crtc->base.dev;
3156 struct drm_i915_private *dev_priv = to_i915(dev);
3157
3158 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3159 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3160 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3161 }
3162
3163 /*
3164 * This function detaches (aka. unbinds) unused scalers in hardware
3165 */
3166 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3167 {
3168 struct intel_crtc_scaler_state *scaler_state;
3169 int i;
3170
3171 scaler_state = &intel_crtc->config->scaler_state;
3172
3173 /* loop through and disable scalers that aren't in use */
3174 for (i = 0; i < intel_crtc->num_scalers; i++) {
3175 if (!scaler_state->scalers[i].in_use)
3176 skl_detach_scaler(intel_crtc, i);
3177 }
3178 }
3179
3180 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3181 unsigned int rotation)
3182 {
3183 u32 stride;
3184
3185 if (plane >= fb->format->num_planes)
3186 return 0;
3187
3188 stride = intel_fb_pitch(fb, plane, rotation);
3189
3190 /*
3191 * The stride is either expressed as a multiple of 64 bytes chunks for
3192 * linear buffers or in number of tiles for tiled buffers.
3193 */
3194 if (drm_rotation_90_or_270(rotation))
3195 stride /= intel_tile_height(fb, plane);
3196 else
3197 stride /= intel_fb_stride_alignment(fb, plane);
3198
3199 return stride;
3200 }
3201
3202 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3203 {
3204 switch (pixel_format) {
3205 case DRM_FORMAT_C8:
3206 return PLANE_CTL_FORMAT_INDEXED;
3207 case DRM_FORMAT_RGB565:
3208 return PLANE_CTL_FORMAT_RGB_565;
3209 case DRM_FORMAT_XBGR8888:
3210 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3211 case DRM_FORMAT_XRGB8888:
3212 return PLANE_CTL_FORMAT_XRGB_8888;
3213 /*
3214 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3215 * to be already pre-multiplied. We need to add a knob (or a different
3216 * DRM_FORMAT) for user-space to configure that.
3217 */
3218 case DRM_FORMAT_ABGR8888:
3219 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3220 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3221 case DRM_FORMAT_ARGB8888:
3222 return PLANE_CTL_FORMAT_XRGB_8888 |
3223 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3224 case DRM_FORMAT_XRGB2101010:
3225 return PLANE_CTL_FORMAT_XRGB_2101010;
3226 case DRM_FORMAT_XBGR2101010:
3227 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3228 case DRM_FORMAT_YUYV:
3229 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3230 case DRM_FORMAT_YVYU:
3231 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3232 case DRM_FORMAT_UYVY:
3233 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3234 case DRM_FORMAT_VYUY:
3235 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3236 default:
3237 MISSING_CASE(pixel_format);
3238 }
3239
3240 return 0;
3241 }
3242
3243 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3244 {
3245 switch (fb_modifier) {
3246 case DRM_FORMAT_MOD_LINEAR:
3247 break;
3248 case I915_FORMAT_MOD_X_TILED:
3249 return PLANE_CTL_TILED_X;
3250 case I915_FORMAT_MOD_Y_TILED:
3251 return PLANE_CTL_TILED_Y;
3252 case I915_FORMAT_MOD_Yf_TILED:
3253 return PLANE_CTL_TILED_YF;
3254 default:
3255 MISSING_CASE(fb_modifier);
3256 }
3257
3258 return 0;
3259 }
3260
3261 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3262 {
3263 switch (rotation) {
3264 case DRM_MODE_ROTATE_0:
3265 break;
3266 /*
3267 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3268 * while i915 HW rotation is clockwise, thats why this swapping.
3269 */
3270 case DRM_MODE_ROTATE_90:
3271 return PLANE_CTL_ROTATE_270;
3272 case DRM_MODE_ROTATE_180:
3273 return PLANE_CTL_ROTATE_180;
3274 case DRM_MODE_ROTATE_270:
3275 return PLANE_CTL_ROTATE_90;
3276 default:
3277 MISSING_CASE(rotation);
3278 }
3279
3280 return 0;
3281 }
3282
3283 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3284 const struct intel_plane_state *plane_state)
3285 {
3286 struct drm_i915_private *dev_priv =
3287 to_i915(plane_state->base.plane->dev);
3288 const struct drm_framebuffer *fb = plane_state->base.fb;
3289 unsigned int rotation = plane_state->base.rotation;
3290 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3291 u32 plane_ctl;
3292
3293 plane_ctl = PLANE_CTL_ENABLE;
3294
3295 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3296 plane_ctl |=
3297 PLANE_CTL_PIPE_GAMMA_ENABLE |
3298 PLANE_CTL_PIPE_CSC_ENABLE |
3299 PLANE_CTL_PLANE_GAMMA_DISABLE;
3300 }
3301
3302 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3303 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3304 plane_ctl |= skl_plane_ctl_rotation(rotation);
3305
3306 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3307 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3308 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3309 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3310
3311 return plane_ctl;
3312 }
3313
3314 static void skylake_update_primary_plane(struct intel_plane *plane,
3315 const struct intel_crtc_state *crtc_state,
3316 const struct intel_plane_state *plane_state)
3317 {
3318 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3319 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3320 const struct drm_framebuffer *fb = plane_state->base.fb;
3321 enum plane_id plane_id = plane->id;
3322 enum pipe pipe = plane->pipe;
3323 u32 plane_ctl = plane_state->ctl;
3324 unsigned int rotation = plane_state->base.rotation;
3325 u32 stride = skl_plane_stride(fb, 0, rotation);
3326 u32 surf_addr = plane_state->main.offset;
3327 int scaler_id = plane_state->scaler_id;
3328 int src_x = plane_state->main.x;
3329 int src_y = plane_state->main.y;
3330 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3331 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3332 int dst_x = plane_state->base.dst.x1;
3333 int dst_y = plane_state->base.dst.y1;
3334 int dst_w = drm_rect_width(&plane_state->base.dst);
3335 int dst_h = drm_rect_height(&plane_state->base.dst);
3336 unsigned long irqflags;
3337
3338 /* Sizes are 0 based */
3339 src_w--;
3340 src_h--;
3341 dst_w--;
3342 dst_h--;
3343
3344 crtc->dspaddr_offset = surf_addr;
3345
3346 crtc->adjusted_x = src_x;
3347 crtc->adjusted_y = src_y;
3348
3349 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3350
3351 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3352 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3353 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3354 PLANE_COLOR_PIPE_CSC_ENABLE |
3355 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3356 }
3357
3358 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3359 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3360 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3361 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3362
3363 if (scaler_id >= 0) {
3364 uint32_t ps_ctrl = 0;
3365
3366 WARN_ON(!dst_w || !dst_h);
3367 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3368 crtc_state->scaler_state.scalers[scaler_id].mode;
3369 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3370 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3371 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3372 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3373 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3374 } else {
3375 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3376 }
3377
3378 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3379 intel_plane_ggtt_offset(plane_state) + surf_addr);
3380
3381 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3382
3383 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3384 }
3385
3386 static void skylake_disable_primary_plane(struct intel_plane *primary,
3387 struct intel_crtc *crtc)
3388 {
3389 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3390 enum plane_id plane_id = primary->id;
3391 enum pipe pipe = primary->pipe;
3392 unsigned long irqflags;
3393
3394 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3395
3396 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3397 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3398 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3399
3400 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3401 }
3402
3403 static int
3404 __intel_display_resume(struct drm_device *dev,
3405 struct drm_atomic_state *state,
3406 struct drm_modeset_acquire_ctx *ctx)
3407 {
3408 struct drm_crtc_state *crtc_state;
3409 struct drm_crtc *crtc;
3410 int i, ret;
3411
3412 intel_modeset_setup_hw_state(dev, ctx);
3413 i915_redisable_vga(to_i915(dev));
3414
3415 if (!state)
3416 return 0;
3417
3418 /*
3419 * We've duplicated the state, pointers to the old state are invalid.
3420 *
3421 * Don't attempt to use the old state until we commit the duplicated state.
3422 */
3423 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3424 /*
3425 * Force recalculation even if we restore
3426 * current state. With fast modeset this may not result
3427 * in a modeset when the state is compatible.
3428 */
3429 crtc_state->mode_changed = true;
3430 }
3431
3432 /* ignore any reset values/BIOS leftovers in the WM registers */
3433 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3434 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3435
3436 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3437
3438 WARN_ON(ret == -EDEADLK);
3439 return ret;
3440 }
3441
3442 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3443 {
3444 return intel_has_gpu_reset(dev_priv) &&
3445 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3446 }
3447
3448 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3449 {
3450 struct drm_device *dev = &dev_priv->drm;
3451 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3452 struct drm_atomic_state *state;
3453 int ret;
3454
3455
3456 /* reset doesn't touch the display */
3457 if (!i915.force_reset_modeset_test &&
3458 !gpu_reset_clobbers_display(dev_priv))
3459 return;
3460
3461 /*
3462 * Need mode_config.mutex so that we don't
3463 * trample ongoing ->detect() and whatnot.
3464 */
3465 mutex_lock(&dev->mode_config.mutex);
3466 drm_modeset_acquire_init(ctx, 0);
3467 while (1) {
3468 ret = drm_modeset_lock_all_ctx(dev, ctx);
3469 if (ret != -EDEADLK)
3470 break;
3471
3472 drm_modeset_backoff(ctx);
3473 }
3474 /*
3475 * Disabling the crtcs gracefully seems nicer. Also the
3476 * g33 docs say we should at least disable all the planes.
3477 */
3478 state = drm_atomic_helper_duplicate_state(dev, ctx);
3479 if (IS_ERR(state)) {
3480 ret = PTR_ERR(state);
3481 DRM_ERROR("Duplicating state failed with %i\n", ret);
3482 return;
3483 }
3484
3485 ret = drm_atomic_helper_disable_all(dev, ctx);
3486 if (ret) {
3487 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3488 drm_atomic_state_put(state);
3489 return;
3490 }
3491
3492 dev_priv->modeset_restore_state = state;
3493 state->acquire_ctx = ctx;
3494 }
3495
3496 void intel_finish_reset(struct drm_i915_private *dev_priv)
3497 {
3498 struct drm_device *dev = &dev_priv->drm;
3499 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3500 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3501 int ret;
3502
3503 /* reset doesn't touch the display */
3504 if (!i915.force_reset_modeset_test &&
3505 !gpu_reset_clobbers_display(dev_priv))
3506 return;
3507
3508 if (!state)
3509 goto unlock;
3510
3511 dev_priv->modeset_restore_state = NULL;
3512
3513 /* reset doesn't touch the display */
3514 if (!gpu_reset_clobbers_display(dev_priv)) {
3515 /* for testing only restore the display */
3516 ret = __intel_display_resume(dev, state, ctx);
3517 if (ret)
3518 DRM_ERROR("Restoring old state failed with %i\n", ret);
3519 } else {
3520 /*
3521 * The display has been reset as well,
3522 * so need a full re-initialization.
3523 */
3524 intel_runtime_pm_disable_interrupts(dev_priv);
3525 intel_runtime_pm_enable_interrupts(dev_priv);
3526
3527 intel_pps_unlock_regs_wa(dev_priv);
3528 intel_modeset_init_hw(dev);
3529
3530 spin_lock_irq(&dev_priv->irq_lock);
3531 if (dev_priv->display.hpd_irq_setup)
3532 dev_priv->display.hpd_irq_setup(dev_priv);
3533 spin_unlock_irq(&dev_priv->irq_lock);
3534
3535 ret = __intel_display_resume(dev, state, ctx);
3536 if (ret)
3537 DRM_ERROR("Restoring old state failed with %i\n", ret);
3538
3539 intel_hpd_init(dev_priv);
3540 }
3541
3542 drm_atomic_state_put(state);
3543 unlock:
3544 drm_modeset_drop_locks(ctx);
3545 drm_modeset_acquire_fini(ctx);
3546 mutex_unlock(&dev->mode_config.mutex);
3547 }
3548
3549 static void intel_update_pipe_config(struct intel_crtc *crtc,
3550 struct intel_crtc_state *old_crtc_state)
3551 {
3552 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3553 struct intel_crtc_state *pipe_config =
3554 to_intel_crtc_state(crtc->base.state);
3555
3556 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3557 crtc->base.mode = crtc->base.state->mode;
3558
3559 /*
3560 * Update pipe size and adjust fitter if needed: the reason for this is
3561 * that in compute_mode_changes we check the native mode (not the pfit
3562 * mode) to see if we can flip rather than do a full mode set. In the
3563 * fastboot case, we'll flip, but if we don't update the pipesrc and
3564 * pfit state, we'll end up with a big fb scanned out into the wrong
3565 * sized surface.
3566 */
3567
3568 I915_WRITE(PIPESRC(crtc->pipe),
3569 ((pipe_config->pipe_src_w - 1) << 16) |
3570 (pipe_config->pipe_src_h - 1));
3571
3572 /* on skylake this is done by detaching scalers */
3573 if (INTEL_GEN(dev_priv) >= 9) {
3574 skl_detach_scalers(crtc);
3575
3576 if (pipe_config->pch_pfit.enabled)
3577 skylake_pfit_enable(crtc);
3578 } else if (HAS_PCH_SPLIT(dev_priv)) {
3579 if (pipe_config->pch_pfit.enabled)
3580 ironlake_pfit_enable(crtc);
3581 else if (old_crtc_state->pch_pfit.enabled)
3582 ironlake_pfit_disable(crtc, true);
3583 }
3584 }
3585
3586 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3587 {
3588 struct drm_device *dev = crtc->base.dev;
3589 struct drm_i915_private *dev_priv = to_i915(dev);
3590 int pipe = crtc->pipe;
3591 i915_reg_t reg;
3592 u32 temp;
3593
3594 /* enable normal train */
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 if (IS_IVYBRIDGE(dev_priv)) {
3598 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3599 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3600 } else {
3601 temp &= ~FDI_LINK_TRAIN_NONE;
3602 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3603 }
3604 I915_WRITE(reg, temp);
3605
3606 reg = FDI_RX_CTL(pipe);
3607 temp = I915_READ(reg);
3608 if (HAS_PCH_CPT(dev_priv)) {
3609 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3610 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3611 } else {
3612 temp &= ~FDI_LINK_TRAIN_NONE;
3613 temp |= FDI_LINK_TRAIN_NONE;
3614 }
3615 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3616
3617 /* wait one idle pattern time */
3618 POSTING_READ(reg);
3619 udelay(1000);
3620
3621 /* IVB wants error correction enabled */
3622 if (IS_IVYBRIDGE(dev_priv))
3623 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3624 FDI_FE_ERRC_ENABLE);
3625 }
3626
3627 /* The FDI link training functions for ILK/Ibexpeak. */
3628 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3629 const struct intel_crtc_state *crtc_state)
3630 {
3631 struct drm_device *dev = crtc->base.dev;
3632 struct drm_i915_private *dev_priv = to_i915(dev);
3633 int pipe = crtc->pipe;
3634 i915_reg_t reg;
3635 u32 temp, tries;
3636
3637 /* FDI needs bits from pipe first */
3638 assert_pipe_enabled(dev_priv, pipe);
3639
3640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3641 for train result */
3642 reg = FDI_RX_IMR(pipe);
3643 temp = I915_READ(reg);
3644 temp &= ~FDI_RX_SYMBOL_LOCK;
3645 temp &= ~FDI_RX_BIT_LOCK;
3646 I915_WRITE(reg, temp);
3647 I915_READ(reg);
3648 udelay(150);
3649
3650 /* enable CPU FDI TX and PCH FDI RX */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3654 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3655 temp &= ~FDI_LINK_TRAIN_NONE;
3656 temp |= FDI_LINK_TRAIN_PATTERN_1;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3658
3659 reg = FDI_RX_CTL(pipe);
3660 temp = I915_READ(reg);
3661 temp &= ~FDI_LINK_TRAIN_NONE;
3662 temp |= FDI_LINK_TRAIN_PATTERN_1;
3663 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3664
3665 POSTING_READ(reg);
3666 udelay(150);
3667
3668 /* Ironlake workaround, enable clock pointer after FDI enable*/
3669 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3670 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3671 FDI_RX_PHASE_SYNC_POINTER_EN);
3672
3673 reg = FDI_RX_IIR(pipe);
3674 for (tries = 0; tries < 5; tries++) {
3675 temp = I915_READ(reg);
3676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678 if ((temp & FDI_RX_BIT_LOCK)) {
3679 DRM_DEBUG_KMS("FDI train 1 done.\n");
3680 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3681 break;
3682 }
3683 }
3684 if (tries == 5)
3685 DRM_ERROR("FDI train 1 fail!\n");
3686
3687 /* Train 2 */
3688 reg = FDI_TX_CTL(pipe);
3689 temp = I915_READ(reg);
3690 temp &= ~FDI_LINK_TRAIN_NONE;
3691 temp |= FDI_LINK_TRAIN_PATTERN_2;
3692 I915_WRITE(reg, temp);
3693
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_LINK_TRAIN_NONE;
3697 temp |= FDI_LINK_TRAIN_PATTERN_2;
3698 I915_WRITE(reg, temp);
3699
3700 POSTING_READ(reg);
3701 udelay(150);
3702
3703 reg = FDI_RX_IIR(pipe);
3704 for (tries = 0; tries < 5; tries++) {
3705 temp = I915_READ(reg);
3706 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3707
3708 if (temp & FDI_RX_SYMBOL_LOCK) {
3709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710 DRM_DEBUG_KMS("FDI train 2 done.\n");
3711 break;
3712 }
3713 }
3714 if (tries == 5)
3715 DRM_ERROR("FDI train 2 fail!\n");
3716
3717 DRM_DEBUG_KMS("FDI train done\n");
3718
3719 }
3720
3721 static const int snb_b_fdi_train_param[] = {
3722 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3723 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3724 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3725 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3726 };
3727
3728 /* The FDI link training functions for SNB/Cougarpoint. */
3729 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3730 const struct intel_crtc_state *crtc_state)
3731 {
3732 struct drm_device *dev = crtc->base.dev;
3733 struct drm_i915_private *dev_priv = to_i915(dev);
3734 int pipe = crtc->pipe;
3735 i915_reg_t reg;
3736 u32 temp, i, retry;
3737
3738 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3739 for train result */
3740 reg = FDI_RX_IMR(pipe);
3741 temp = I915_READ(reg);
3742 temp &= ~FDI_RX_SYMBOL_LOCK;
3743 temp &= ~FDI_RX_BIT_LOCK;
3744 I915_WRITE(reg, temp);
3745
3746 POSTING_READ(reg);
3747 udelay(150);
3748
3749 /* enable CPU FDI TX and PCH FDI RX */
3750 reg = FDI_TX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3753 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3754 temp &= ~FDI_LINK_TRAIN_NONE;
3755 temp |= FDI_LINK_TRAIN_PATTERN_1;
3756 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3757 /* SNB-B */
3758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3759 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3760
3761 I915_WRITE(FDI_RX_MISC(pipe),
3762 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3763
3764 reg = FDI_RX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 if (HAS_PCH_CPT(dev_priv)) {
3767 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3768 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3769 } else {
3770 temp &= ~FDI_LINK_TRAIN_NONE;
3771 temp |= FDI_LINK_TRAIN_PATTERN_1;
3772 }
3773 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3774
3775 POSTING_READ(reg);
3776 udelay(150);
3777
3778 for (i = 0; i < 4; i++) {
3779 reg = FDI_TX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3782 temp |= snb_b_fdi_train_param[i];
3783 I915_WRITE(reg, temp);
3784
3785 POSTING_READ(reg);
3786 udelay(500);
3787
3788 for (retry = 0; retry < 5; retry++) {
3789 reg = FDI_RX_IIR(pipe);
3790 temp = I915_READ(reg);
3791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3792 if (temp & FDI_RX_BIT_LOCK) {
3793 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3794 DRM_DEBUG_KMS("FDI train 1 done.\n");
3795 break;
3796 }
3797 udelay(50);
3798 }
3799 if (retry < 5)
3800 break;
3801 }
3802 if (i == 4)
3803 DRM_ERROR("FDI train 1 fail!\n");
3804
3805 /* Train 2 */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 temp &= ~FDI_LINK_TRAIN_NONE;
3809 temp |= FDI_LINK_TRAIN_PATTERN_2;
3810 if (IS_GEN6(dev_priv)) {
3811 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3812 /* SNB-B */
3813 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3814 }
3815 I915_WRITE(reg, temp);
3816
3817 reg = FDI_RX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 if (HAS_PCH_CPT(dev_priv)) {
3820 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3821 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3822 } else {
3823 temp &= ~FDI_LINK_TRAIN_NONE;
3824 temp |= FDI_LINK_TRAIN_PATTERN_2;
3825 }
3826 I915_WRITE(reg, temp);
3827
3828 POSTING_READ(reg);
3829 udelay(150);
3830
3831 for (i = 0; i < 4; i++) {
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3835 temp |= snb_b_fdi_train_param[i];
3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(500);
3840
3841 for (retry = 0; retry < 5; retry++) {
3842 reg = FDI_RX_IIR(pipe);
3843 temp = I915_READ(reg);
3844 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3845 if (temp & FDI_RX_SYMBOL_LOCK) {
3846 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3847 DRM_DEBUG_KMS("FDI train 2 done.\n");
3848 break;
3849 }
3850 udelay(50);
3851 }
3852 if (retry < 5)
3853 break;
3854 }
3855 if (i == 4)
3856 DRM_ERROR("FDI train 2 fail!\n");
3857
3858 DRM_DEBUG_KMS("FDI train done.\n");
3859 }
3860
3861 /* Manual link training for Ivy Bridge A0 parts */
3862 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3863 const struct intel_crtc_state *crtc_state)
3864 {
3865 struct drm_device *dev = crtc->base.dev;
3866 struct drm_i915_private *dev_priv = to_i915(dev);
3867 int pipe = crtc->pipe;
3868 i915_reg_t reg;
3869 u32 temp, i, j;
3870
3871 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3872 for train result */
3873 reg = FDI_RX_IMR(pipe);
3874 temp = I915_READ(reg);
3875 temp &= ~FDI_RX_SYMBOL_LOCK;
3876 temp &= ~FDI_RX_BIT_LOCK;
3877 I915_WRITE(reg, temp);
3878
3879 POSTING_READ(reg);
3880 udelay(150);
3881
3882 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3883 I915_READ(FDI_RX_IIR(pipe)));
3884
3885 /* Try each vswing and preemphasis setting twice before moving on */
3886 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3887 /* disable first in case we need to retry */
3888 reg = FDI_TX_CTL(pipe);
3889 temp = I915_READ(reg);
3890 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3891 temp &= ~FDI_TX_ENABLE;
3892 I915_WRITE(reg, temp);
3893
3894 reg = FDI_RX_CTL(pipe);
3895 temp = I915_READ(reg);
3896 temp &= ~FDI_LINK_TRAIN_AUTO;
3897 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3898 temp &= ~FDI_RX_ENABLE;
3899 I915_WRITE(reg, temp);
3900
3901 /* enable CPU FDI TX and PCH FDI RX */
3902 reg = FDI_TX_CTL(pipe);
3903 temp = I915_READ(reg);
3904 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3905 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3906 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3907 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908 temp |= snb_b_fdi_train_param[j/2];
3909 temp |= FDI_COMPOSITE_SYNC;
3910 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3911
3912 I915_WRITE(FDI_RX_MISC(pipe),
3913 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3914
3915 reg = FDI_RX_CTL(pipe);
3916 temp = I915_READ(reg);
3917 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3918 temp |= FDI_COMPOSITE_SYNC;
3919 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3920
3921 POSTING_READ(reg);
3922 udelay(1); /* should be 0.5us */
3923
3924 for (i = 0; i < 4; i++) {
3925 reg = FDI_RX_IIR(pipe);
3926 temp = I915_READ(reg);
3927 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3928
3929 if (temp & FDI_RX_BIT_LOCK ||
3930 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3931 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3932 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3933 i);
3934 break;
3935 }
3936 udelay(1); /* should be 0.5us */
3937 }
3938 if (i == 4) {
3939 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3940 continue;
3941 }
3942
3943 /* Train 2 */
3944 reg = FDI_TX_CTL(pipe);
3945 temp = I915_READ(reg);
3946 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3947 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3948 I915_WRITE(reg, temp);
3949
3950 reg = FDI_RX_CTL(pipe);
3951 temp = I915_READ(reg);
3952 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3953 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3954 I915_WRITE(reg, temp);
3955
3956 POSTING_READ(reg);
3957 udelay(2); /* should be 1.5us */
3958
3959 for (i = 0; i < 4; i++) {
3960 reg = FDI_RX_IIR(pipe);
3961 temp = I915_READ(reg);
3962 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3963
3964 if (temp & FDI_RX_SYMBOL_LOCK ||
3965 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3966 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3967 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3968 i);
3969 goto train_done;
3970 }
3971 udelay(2); /* should be 1.5us */
3972 }
3973 if (i == 4)
3974 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3975 }
3976
3977 train_done:
3978 DRM_DEBUG_KMS("FDI train done.\n");
3979 }
3980
3981 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3982 {
3983 struct drm_device *dev = intel_crtc->base.dev;
3984 struct drm_i915_private *dev_priv = to_i915(dev);
3985 int pipe = intel_crtc->pipe;
3986 i915_reg_t reg;
3987 u32 temp;
3988
3989 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3990 reg = FDI_RX_CTL(pipe);
3991 temp = I915_READ(reg);
3992 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3993 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3994 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3995 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3996
3997 POSTING_READ(reg);
3998 udelay(200);
3999
4000 /* Switch from Rawclk to PCDclk */
4001 temp = I915_READ(reg);
4002 I915_WRITE(reg, temp | FDI_PCDCLK);
4003
4004 POSTING_READ(reg);
4005 udelay(200);
4006
4007 /* Enable CPU FDI TX PLL, always on for Ironlake */
4008 reg = FDI_TX_CTL(pipe);
4009 temp = I915_READ(reg);
4010 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4011 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4012
4013 POSTING_READ(reg);
4014 udelay(100);
4015 }
4016 }
4017
4018 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4019 {
4020 struct drm_device *dev = intel_crtc->base.dev;
4021 struct drm_i915_private *dev_priv = to_i915(dev);
4022 int pipe = intel_crtc->pipe;
4023 i915_reg_t reg;
4024 u32 temp;
4025
4026 /* Switch from PCDclk to Rawclk */
4027 reg = FDI_RX_CTL(pipe);
4028 temp = I915_READ(reg);
4029 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4030
4031 /* Disable CPU FDI TX PLL */
4032 reg = FDI_TX_CTL(pipe);
4033 temp = I915_READ(reg);
4034 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4035
4036 POSTING_READ(reg);
4037 udelay(100);
4038
4039 reg = FDI_RX_CTL(pipe);
4040 temp = I915_READ(reg);
4041 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4042
4043 /* Wait for the clocks to turn off. */
4044 POSTING_READ(reg);
4045 udelay(100);
4046 }
4047
4048 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4049 {
4050 struct drm_device *dev = crtc->dev;
4051 struct drm_i915_private *dev_priv = to_i915(dev);
4052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053 int pipe = intel_crtc->pipe;
4054 i915_reg_t reg;
4055 u32 temp;
4056
4057 /* disable CPU FDI tx and PCH FDI rx */
4058 reg = FDI_TX_CTL(pipe);
4059 temp = I915_READ(reg);
4060 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4061 POSTING_READ(reg);
4062
4063 reg = FDI_RX_CTL(pipe);
4064 temp = I915_READ(reg);
4065 temp &= ~(0x7 << 16);
4066 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4067 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4068
4069 POSTING_READ(reg);
4070 udelay(100);
4071
4072 /* Ironlake workaround, disable clock pointer after downing FDI */
4073 if (HAS_PCH_IBX(dev_priv))
4074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4075
4076 /* still set train pattern 1 */
4077 reg = FDI_TX_CTL(pipe);
4078 temp = I915_READ(reg);
4079 temp &= ~FDI_LINK_TRAIN_NONE;
4080 temp |= FDI_LINK_TRAIN_PATTERN_1;
4081 I915_WRITE(reg, temp);
4082
4083 reg = FDI_RX_CTL(pipe);
4084 temp = I915_READ(reg);
4085 if (HAS_PCH_CPT(dev_priv)) {
4086 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4087 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4088 } else {
4089 temp &= ~FDI_LINK_TRAIN_NONE;
4090 temp |= FDI_LINK_TRAIN_PATTERN_1;
4091 }
4092 /* BPC in FDI rx is consistent with that in PIPECONF */
4093 temp &= ~(0x07 << 16);
4094 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4095 I915_WRITE(reg, temp);
4096
4097 POSTING_READ(reg);
4098 udelay(100);
4099 }
4100
4101 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4102 {
4103 struct drm_crtc *crtc;
4104 bool cleanup_done;
4105
4106 drm_for_each_crtc(crtc, &dev_priv->drm) {
4107 struct drm_crtc_commit *commit;
4108 spin_lock(&crtc->commit_lock);
4109 commit = list_first_entry_or_null(&crtc->commit_list,
4110 struct drm_crtc_commit, commit_entry);
4111 cleanup_done = commit ?
4112 try_wait_for_completion(&commit->cleanup_done) : true;
4113 spin_unlock(&crtc->commit_lock);
4114
4115 if (cleanup_done)
4116 continue;
4117
4118 drm_crtc_wait_one_vblank(crtc);
4119
4120 return true;
4121 }
4122
4123 return false;
4124 }
4125
4126 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4127 {
4128 u32 temp;
4129
4130 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4131
4132 mutex_lock(&dev_priv->sb_lock);
4133
4134 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4135 temp |= SBI_SSCCTL_DISABLE;
4136 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4137
4138 mutex_unlock(&dev_priv->sb_lock);
4139 }
4140
4141 /* Program iCLKIP clock to the desired frequency */
4142 static void lpt_program_iclkip(struct intel_crtc *crtc)
4143 {
4144 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4145 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4146 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4147 u32 temp;
4148
4149 lpt_disable_iclkip(dev_priv);
4150
4151 /* The iCLK virtual clock root frequency is in MHz,
4152 * but the adjusted_mode->crtc_clock in in KHz. To get the
4153 * divisors, it is necessary to divide one by another, so we
4154 * convert the virtual clock precision to KHz here for higher
4155 * precision.
4156 */
4157 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4158 u32 iclk_virtual_root_freq = 172800 * 1000;
4159 u32 iclk_pi_range = 64;
4160 u32 desired_divisor;
4161
4162 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4163 clock << auxdiv);
4164 divsel = (desired_divisor / iclk_pi_range) - 2;
4165 phaseinc = desired_divisor % iclk_pi_range;
4166
4167 /*
4168 * Near 20MHz is a corner case which is
4169 * out of range for the 7-bit divisor
4170 */
4171 if (divsel <= 0x7f)
4172 break;
4173 }
4174
4175 /* This should not happen with any sane values */
4176 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4177 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4178 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4179 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4180
4181 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4182 clock,
4183 auxdiv,
4184 divsel,
4185 phasedir,
4186 phaseinc);
4187
4188 mutex_lock(&dev_priv->sb_lock);
4189
4190 /* Program SSCDIVINTPHASE6 */
4191 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4192 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4193 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4194 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4195 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4196 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4197 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4198 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4199
4200 /* Program SSCAUXDIV */
4201 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4202 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4203 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4204 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4205
4206 /* Enable modulator and associated divider */
4207 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4208 temp &= ~SBI_SSCCTL_DISABLE;
4209 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4210
4211 mutex_unlock(&dev_priv->sb_lock);
4212
4213 /* Wait for initialization time */
4214 udelay(24);
4215
4216 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4217 }
4218
4219 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4220 {
4221 u32 divsel, phaseinc, auxdiv;
4222 u32 iclk_virtual_root_freq = 172800 * 1000;
4223 u32 iclk_pi_range = 64;
4224 u32 desired_divisor;
4225 u32 temp;
4226
4227 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4228 return 0;
4229
4230 mutex_lock(&dev_priv->sb_lock);
4231
4232 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4233 if (temp & SBI_SSCCTL_DISABLE) {
4234 mutex_unlock(&dev_priv->sb_lock);
4235 return 0;
4236 }
4237
4238 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4239 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4240 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4241 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4242 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4243
4244 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4245 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4246 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4247
4248 mutex_unlock(&dev_priv->sb_lock);
4249
4250 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4251
4252 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4253 desired_divisor << auxdiv);
4254 }
4255
4256 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4257 enum pipe pch_transcoder)
4258 {
4259 struct drm_device *dev = crtc->base.dev;
4260 struct drm_i915_private *dev_priv = to_i915(dev);
4261 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4262
4263 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4264 I915_READ(HTOTAL(cpu_transcoder)));
4265 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4266 I915_READ(HBLANK(cpu_transcoder)));
4267 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4268 I915_READ(HSYNC(cpu_transcoder)));
4269
4270 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4271 I915_READ(VTOTAL(cpu_transcoder)));
4272 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4273 I915_READ(VBLANK(cpu_transcoder)));
4274 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4275 I915_READ(VSYNC(cpu_transcoder)));
4276 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4277 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4278 }
4279
4280 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4281 {
4282 struct drm_i915_private *dev_priv = to_i915(dev);
4283 uint32_t temp;
4284
4285 temp = I915_READ(SOUTH_CHICKEN1);
4286 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4287 return;
4288
4289 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4290 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4291
4292 temp &= ~FDI_BC_BIFURCATION_SELECT;
4293 if (enable)
4294 temp |= FDI_BC_BIFURCATION_SELECT;
4295
4296 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4297 I915_WRITE(SOUTH_CHICKEN1, temp);
4298 POSTING_READ(SOUTH_CHICKEN1);
4299 }
4300
4301 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4302 {
4303 struct drm_device *dev = intel_crtc->base.dev;
4304
4305 switch (intel_crtc->pipe) {
4306 case PIPE_A:
4307 break;
4308 case PIPE_B:
4309 if (intel_crtc->config->fdi_lanes > 2)
4310 cpt_set_fdi_bc_bifurcation(dev, false);
4311 else
4312 cpt_set_fdi_bc_bifurcation(dev, true);
4313
4314 break;
4315 case PIPE_C:
4316 cpt_set_fdi_bc_bifurcation(dev, true);
4317
4318 break;
4319 default:
4320 BUG();
4321 }
4322 }
4323
4324 /* Return which DP Port should be selected for Transcoder DP control */
4325 static enum port
4326 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4327 {
4328 struct drm_device *dev = crtc->base.dev;
4329 struct intel_encoder *encoder;
4330
4331 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4332 if (encoder->type == INTEL_OUTPUT_DP ||
4333 encoder->type == INTEL_OUTPUT_EDP)
4334 return enc_to_dig_port(&encoder->base)->port;
4335 }
4336
4337 return -1;
4338 }
4339
4340 /*
4341 * Enable PCH resources required for PCH ports:
4342 * - PCH PLLs
4343 * - FDI training & RX/TX
4344 * - update transcoder timings
4345 * - DP transcoding bits
4346 * - transcoder
4347 */
4348 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4349 {
4350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4351 struct drm_device *dev = crtc->base.dev;
4352 struct drm_i915_private *dev_priv = to_i915(dev);
4353 int pipe = crtc->pipe;
4354 u32 temp;
4355
4356 assert_pch_transcoder_disabled(dev_priv, pipe);
4357
4358 if (IS_IVYBRIDGE(dev_priv))
4359 ivybridge_update_fdi_bc_bifurcation(crtc);
4360
4361 /* Write the TU size bits before fdi link training, so that error
4362 * detection works. */
4363 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4364 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4365
4366 /* For PCH output, training FDI link */
4367 dev_priv->display.fdi_link_train(crtc, crtc_state);
4368
4369 /* We need to program the right clock selection before writing the pixel
4370 * mutliplier into the DPLL. */
4371 if (HAS_PCH_CPT(dev_priv)) {
4372 u32 sel;
4373
4374 temp = I915_READ(PCH_DPLL_SEL);
4375 temp |= TRANS_DPLL_ENABLE(pipe);
4376 sel = TRANS_DPLLB_SEL(pipe);
4377 if (crtc_state->shared_dpll ==
4378 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4379 temp |= sel;
4380 else
4381 temp &= ~sel;
4382 I915_WRITE(PCH_DPLL_SEL, temp);
4383 }
4384
4385 /* XXX: pch pll's can be enabled any time before we enable the PCH
4386 * transcoder, and we actually should do this to not upset any PCH
4387 * transcoder that already use the clock when we share it.
4388 *
4389 * Note that enable_shared_dpll tries to do the right thing, but
4390 * get_shared_dpll unconditionally resets the pll - we need that to have
4391 * the right LVDS enable sequence. */
4392 intel_enable_shared_dpll(crtc);
4393
4394 /* set transcoder timing, panel must allow it */
4395 assert_panel_unlocked(dev_priv, pipe);
4396 ironlake_pch_transcoder_set_timings(crtc, pipe);
4397
4398 intel_fdi_normal_train(crtc);
4399
4400 /* For PCH DP, enable TRANS_DP_CTL */
4401 if (HAS_PCH_CPT(dev_priv) &&
4402 intel_crtc_has_dp_encoder(crtc_state)) {
4403 const struct drm_display_mode *adjusted_mode =
4404 &crtc_state->base.adjusted_mode;
4405 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4406 i915_reg_t reg = TRANS_DP_CTL(pipe);
4407 temp = I915_READ(reg);
4408 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4409 TRANS_DP_SYNC_MASK |
4410 TRANS_DP_BPC_MASK);
4411 temp |= TRANS_DP_OUTPUT_ENABLE;
4412 temp |= bpc << 9; /* same format but at 11:9 */
4413
4414 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4415 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4416 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4417 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4418
4419 switch (intel_trans_dp_port_sel(crtc)) {
4420 case PORT_B:
4421 temp |= TRANS_DP_PORT_SEL_B;
4422 break;
4423 case PORT_C:
4424 temp |= TRANS_DP_PORT_SEL_C;
4425 break;
4426 case PORT_D:
4427 temp |= TRANS_DP_PORT_SEL_D;
4428 break;
4429 default:
4430 BUG();
4431 }
4432
4433 I915_WRITE(reg, temp);
4434 }
4435
4436 ironlake_enable_pch_transcoder(dev_priv, pipe);
4437 }
4438
4439 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4440 {
4441 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4443 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4444
4445 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4446
4447 lpt_program_iclkip(crtc);
4448
4449 /* Set transcoder timing. */
4450 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4451
4452 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4453 }
4454
4455 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4456 {
4457 struct drm_i915_private *dev_priv = to_i915(dev);
4458 i915_reg_t dslreg = PIPEDSL(pipe);
4459 u32 temp;
4460
4461 temp = I915_READ(dslreg);
4462 udelay(500);
4463 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4464 if (wait_for(I915_READ(dslreg) != temp, 5))
4465 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4466 }
4467 }
4468
4469 static int
4470 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4471 unsigned int scaler_user, int *scaler_id,
4472 int src_w, int src_h, int dst_w, int dst_h)
4473 {
4474 struct intel_crtc_scaler_state *scaler_state =
4475 &crtc_state->scaler_state;
4476 struct intel_crtc *intel_crtc =
4477 to_intel_crtc(crtc_state->base.crtc);
4478 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4479 const struct drm_display_mode *adjusted_mode =
4480 &crtc_state->base.adjusted_mode;
4481 int need_scaling;
4482
4483 /*
4484 * Src coordinates are already rotated by 270 degrees for
4485 * the 90/270 degree plane rotation cases (to match the
4486 * GTT mapping), hence no need to account for rotation here.
4487 */
4488 need_scaling = src_w != dst_w || src_h != dst_h;
4489
4490 /*
4491 * Scaling/fitting not supported in IF-ID mode in GEN9+
4492 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4493 * Once NV12 is enabled, handle it here while allocating scaler
4494 * for NV12.
4495 */
4496 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4497 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4498 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4499 return -EINVAL;
4500 }
4501
4502 /*
4503 * if plane is being disabled or scaler is no more required or force detach
4504 * - free scaler binded to this plane/crtc
4505 * - in order to do this, update crtc->scaler_usage
4506 *
4507 * Here scaler state in crtc_state is set free so that
4508 * scaler can be assigned to other user. Actual register
4509 * update to free the scaler is done in plane/panel-fit programming.
4510 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4511 */
4512 if (force_detach || !need_scaling) {
4513 if (*scaler_id >= 0) {
4514 scaler_state->scaler_users &= ~(1 << scaler_user);
4515 scaler_state->scalers[*scaler_id].in_use = 0;
4516
4517 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4518 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4519 intel_crtc->pipe, scaler_user, *scaler_id,
4520 scaler_state->scaler_users);
4521 *scaler_id = -1;
4522 }
4523 return 0;
4524 }
4525
4526 /* range checks */
4527 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4528 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4529
4530 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4531 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4532 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4533 "size is out of scaler range\n",
4534 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4535 return -EINVAL;
4536 }
4537
4538 /* mark this plane as a scaler user in crtc_state */
4539 scaler_state->scaler_users |= (1 << scaler_user);
4540 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4541 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4542 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4543 scaler_state->scaler_users);
4544
4545 return 0;
4546 }
4547
4548 /**
4549 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4550 *
4551 * @state: crtc's scaler state
4552 *
4553 * Return
4554 * 0 - scaler_usage updated successfully
4555 * error - requested scaling cannot be supported or other error condition
4556 */
4557 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4558 {
4559 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4560
4561 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4562 &state->scaler_state.scaler_id,
4563 state->pipe_src_w, state->pipe_src_h,
4564 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4565 }
4566
4567 /**
4568 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4569 *
4570 * @state: crtc's scaler state
4571 * @plane_state: atomic plane state to update
4572 *
4573 * Return
4574 * 0 - scaler_usage updated successfully
4575 * error - requested scaling cannot be supported or other error condition
4576 */
4577 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4578 struct intel_plane_state *plane_state)
4579 {
4580
4581 struct intel_plane *intel_plane =
4582 to_intel_plane(plane_state->base.plane);
4583 struct drm_framebuffer *fb = plane_state->base.fb;
4584 int ret;
4585
4586 bool force_detach = !fb || !plane_state->base.visible;
4587
4588 ret = skl_update_scaler(crtc_state, force_detach,
4589 drm_plane_index(&intel_plane->base),
4590 &plane_state->scaler_id,
4591 drm_rect_width(&plane_state->base.src) >> 16,
4592 drm_rect_height(&plane_state->base.src) >> 16,
4593 drm_rect_width(&plane_state->base.dst),
4594 drm_rect_height(&plane_state->base.dst));
4595
4596 if (ret || plane_state->scaler_id < 0)
4597 return ret;
4598
4599 /* check colorkey */
4600 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4601 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4602 intel_plane->base.base.id,
4603 intel_plane->base.name);
4604 return -EINVAL;
4605 }
4606
4607 /* Check src format */
4608 switch (fb->format->format) {
4609 case DRM_FORMAT_RGB565:
4610 case DRM_FORMAT_XBGR8888:
4611 case DRM_FORMAT_XRGB8888:
4612 case DRM_FORMAT_ABGR8888:
4613 case DRM_FORMAT_ARGB8888:
4614 case DRM_FORMAT_XRGB2101010:
4615 case DRM_FORMAT_XBGR2101010:
4616 case DRM_FORMAT_YUYV:
4617 case DRM_FORMAT_YVYU:
4618 case DRM_FORMAT_UYVY:
4619 case DRM_FORMAT_VYUY:
4620 break;
4621 default:
4622 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4623 intel_plane->base.base.id, intel_plane->base.name,
4624 fb->base.id, fb->format->format);
4625 return -EINVAL;
4626 }
4627
4628 return 0;
4629 }
4630
4631 static void skylake_scaler_disable(struct intel_crtc *crtc)
4632 {
4633 int i;
4634
4635 for (i = 0; i < crtc->num_scalers; i++)
4636 skl_detach_scaler(crtc, i);
4637 }
4638
4639 static void skylake_pfit_enable(struct intel_crtc *crtc)
4640 {
4641 struct drm_device *dev = crtc->base.dev;
4642 struct drm_i915_private *dev_priv = to_i915(dev);
4643 int pipe = crtc->pipe;
4644 struct intel_crtc_scaler_state *scaler_state =
4645 &crtc->config->scaler_state;
4646
4647 if (crtc->config->pch_pfit.enabled) {
4648 int id;
4649
4650 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4651 return;
4652
4653 id = scaler_state->scaler_id;
4654 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4655 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4656 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4657 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4658 }
4659 }
4660
4661 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4662 {
4663 struct drm_device *dev = crtc->base.dev;
4664 struct drm_i915_private *dev_priv = to_i915(dev);
4665 int pipe = crtc->pipe;
4666
4667 if (crtc->config->pch_pfit.enabled) {
4668 /* Force use of hard-coded filter coefficients
4669 * as some pre-programmed values are broken,
4670 * e.g. x201.
4671 */
4672 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4673 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4674 PF_PIPE_SEL_IVB(pipe));
4675 else
4676 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4677 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4678 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4679 }
4680 }
4681
4682 void hsw_enable_ips(struct intel_crtc *crtc)
4683 {
4684 struct drm_device *dev = crtc->base.dev;
4685 struct drm_i915_private *dev_priv = to_i915(dev);
4686
4687 if (!crtc->config->ips_enabled)
4688 return;
4689
4690 /*
4691 * We can only enable IPS after we enable a plane and wait for a vblank
4692 * This function is called from post_plane_update, which is run after
4693 * a vblank wait.
4694 */
4695
4696 assert_plane_enabled(dev_priv, crtc->plane);
4697 if (IS_BROADWELL(dev_priv)) {
4698 mutex_lock(&dev_priv->rps.hw_lock);
4699 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4700 mutex_unlock(&dev_priv->rps.hw_lock);
4701 /* Quoting Art Runyan: "its not safe to expect any particular
4702 * value in IPS_CTL bit 31 after enabling IPS through the
4703 * mailbox." Moreover, the mailbox may return a bogus state,
4704 * so we need to just enable it and continue on.
4705 */
4706 } else {
4707 I915_WRITE(IPS_CTL, IPS_ENABLE);
4708 /* The bit only becomes 1 in the next vblank, so this wait here
4709 * is essentially intel_wait_for_vblank. If we don't have this
4710 * and don't wait for vblanks until the end of crtc_enable, then
4711 * the HW state readout code will complain that the expected
4712 * IPS_CTL value is not the one we read. */
4713 if (intel_wait_for_register(dev_priv,
4714 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4715 50))
4716 DRM_ERROR("Timed out waiting for IPS enable\n");
4717 }
4718 }
4719
4720 void hsw_disable_ips(struct intel_crtc *crtc)
4721 {
4722 struct drm_device *dev = crtc->base.dev;
4723 struct drm_i915_private *dev_priv = to_i915(dev);
4724
4725 if (!crtc->config->ips_enabled)
4726 return;
4727
4728 assert_plane_enabled(dev_priv, crtc->plane);
4729 if (IS_BROADWELL(dev_priv)) {
4730 mutex_lock(&dev_priv->rps.hw_lock);
4731 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4732 mutex_unlock(&dev_priv->rps.hw_lock);
4733 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4734 if (intel_wait_for_register(dev_priv,
4735 IPS_CTL, IPS_ENABLE, 0,
4736 42))
4737 DRM_ERROR("Timed out waiting for IPS disable\n");
4738 } else {
4739 I915_WRITE(IPS_CTL, 0);
4740 POSTING_READ(IPS_CTL);
4741 }
4742
4743 /* We need to wait for a vblank before we can disable the plane. */
4744 intel_wait_for_vblank(dev_priv, crtc->pipe);
4745 }
4746
4747 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4748 {
4749 if (intel_crtc->overlay) {
4750 struct drm_device *dev = intel_crtc->base.dev;
4751
4752 mutex_lock(&dev->struct_mutex);
4753 (void) intel_overlay_switch_off(intel_crtc->overlay);
4754 mutex_unlock(&dev->struct_mutex);
4755 }
4756
4757 /* Let userspace switch the overlay on again. In most cases userspace
4758 * has to recompute where to put it anyway.
4759 */
4760 }
4761
4762 /**
4763 * intel_post_enable_primary - Perform operations after enabling primary plane
4764 * @crtc: the CRTC whose primary plane was just enabled
4765 *
4766 * Performs potentially sleeping operations that must be done after the primary
4767 * plane is enabled, such as updating FBC and IPS. Note that this may be
4768 * called due to an explicit primary plane update, or due to an implicit
4769 * re-enable that is caused when a sprite plane is updated to no longer
4770 * completely hide the primary plane.
4771 */
4772 static void
4773 intel_post_enable_primary(struct drm_crtc *crtc)
4774 {
4775 struct drm_device *dev = crtc->dev;
4776 struct drm_i915_private *dev_priv = to_i915(dev);
4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778 int pipe = intel_crtc->pipe;
4779
4780 /*
4781 * FIXME IPS should be fine as long as one plane is
4782 * enabled, but in practice it seems to have problems
4783 * when going from primary only to sprite only and vice
4784 * versa.
4785 */
4786 hsw_enable_ips(intel_crtc);
4787
4788 /*
4789 * Gen2 reports pipe underruns whenever all planes are disabled.
4790 * So don't enable underrun reporting before at least some planes
4791 * are enabled.
4792 * FIXME: Need to fix the logic to work when we turn off all planes
4793 * but leave the pipe running.
4794 */
4795 if (IS_GEN2(dev_priv))
4796 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4797
4798 /* Underruns don't always raise interrupts, so check manually. */
4799 intel_check_cpu_fifo_underruns(dev_priv);
4800 intel_check_pch_fifo_underruns(dev_priv);
4801 }
4802
4803 /* FIXME move all this to pre_plane_update() with proper state tracking */
4804 static void
4805 intel_pre_disable_primary(struct drm_crtc *crtc)
4806 {
4807 struct drm_device *dev = crtc->dev;
4808 struct drm_i915_private *dev_priv = to_i915(dev);
4809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4810 int pipe = intel_crtc->pipe;
4811
4812 /*
4813 * Gen2 reports pipe underruns whenever all planes are disabled.
4814 * So diasble underrun reporting before all the planes get disabled.
4815 * FIXME: Need to fix the logic to work when we turn off all planes
4816 * but leave the pipe running.
4817 */
4818 if (IS_GEN2(dev_priv))
4819 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4820
4821 /*
4822 * FIXME IPS should be fine as long as one plane is
4823 * enabled, but in practice it seems to have problems
4824 * when going from primary only to sprite only and vice
4825 * versa.
4826 */
4827 hsw_disable_ips(intel_crtc);
4828 }
4829
4830 /* FIXME get rid of this and use pre_plane_update */
4831 static void
4832 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4833 {
4834 struct drm_device *dev = crtc->dev;
4835 struct drm_i915_private *dev_priv = to_i915(dev);
4836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4837 int pipe = intel_crtc->pipe;
4838
4839 intel_pre_disable_primary(crtc);
4840
4841 /*
4842 * Vblank time updates from the shadow to live plane control register
4843 * are blocked if the memory self-refresh mode is active at that
4844 * moment. So to make sure the plane gets truly disabled, disable
4845 * first the self-refresh mode. The self-refresh enable bit in turn
4846 * will be checked/applied by the HW only at the next frame start
4847 * event which is after the vblank start event, so we need to have a
4848 * wait-for-vblank between disabling the plane and the pipe.
4849 */
4850 if (HAS_GMCH_DISPLAY(dev_priv) &&
4851 intel_set_memory_cxsr(dev_priv, false))
4852 intel_wait_for_vblank(dev_priv, pipe);
4853 }
4854
4855 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4856 {
4857 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4858 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4859 struct intel_crtc_state *pipe_config =
4860 to_intel_crtc_state(crtc->base.state);
4861 struct drm_plane *primary = crtc->base.primary;
4862 struct drm_plane_state *old_pri_state =
4863 drm_atomic_get_existing_plane_state(old_state, primary);
4864
4865 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4866
4867 if (pipe_config->update_wm_post && pipe_config->base.active)
4868 intel_update_watermarks(crtc);
4869
4870 if (old_pri_state) {
4871 struct intel_plane_state *primary_state =
4872 to_intel_plane_state(primary->state);
4873 struct intel_plane_state *old_primary_state =
4874 to_intel_plane_state(old_pri_state);
4875
4876 intel_fbc_post_update(crtc);
4877
4878 if (primary_state->base.visible &&
4879 (needs_modeset(&pipe_config->base) ||
4880 !old_primary_state->base.visible))
4881 intel_post_enable_primary(&crtc->base);
4882 }
4883 }
4884
4885 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
4886 struct intel_crtc_state *pipe_config)
4887 {
4888 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4889 struct drm_device *dev = crtc->base.dev;
4890 struct drm_i915_private *dev_priv = to_i915(dev);
4891 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4892 struct drm_plane *primary = crtc->base.primary;
4893 struct drm_plane_state *old_pri_state =
4894 drm_atomic_get_existing_plane_state(old_state, primary);
4895 bool modeset = needs_modeset(&pipe_config->base);
4896 struct intel_atomic_state *old_intel_state =
4897 to_intel_atomic_state(old_state);
4898
4899 if (old_pri_state) {
4900 struct intel_plane_state *primary_state =
4901 to_intel_plane_state(primary->state);
4902 struct intel_plane_state *old_primary_state =
4903 to_intel_plane_state(old_pri_state);
4904
4905 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4906
4907 if (old_primary_state->base.visible &&
4908 (modeset || !primary_state->base.visible))
4909 intel_pre_disable_primary(&crtc->base);
4910 }
4911
4912 /*
4913 * Vblank time updates from the shadow to live plane control register
4914 * are blocked if the memory self-refresh mode is active at that
4915 * moment. So to make sure the plane gets truly disabled, disable
4916 * first the self-refresh mode. The self-refresh enable bit in turn
4917 * will be checked/applied by the HW only at the next frame start
4918 * event which is after the vblank start event, so we need to have a
4919 * wait-for-vblank between disabling the plane and the pipe.
4920 */
4921 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
4922 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
4923 intel_wait_for_vblank(dev_priv, crtc->pipe);
4924
4925 /*
4926 * IVB workaround: must disable low power watermarks for at least
4927 * one frame before enabling scaling. LP watermarks can be re-enabled
4928 * when scaling is disabled.
4929 *
4930 * WaCxSRDisabledForSpriteScaling:ivb
4931 */
4932 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
4933 intel_wait_for_vblank(dev_priv, crtc->pipe);
4934
4935 /*
4936 * If we're doing a modeset, we're done. No need to do any pre-vblank
4937 * watermark programming here.
4938 */
4939 if (needs_modeset(&pipe_config->base))
4940 return;
4941
4942 /*
4943 * For platforms that support atomic watermarks, program the
4944 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4945 * will be the intermediate values that are safe for both pre- and
4946 * post- vblank; when vblank happens, the 'active' values will be set
4947 * to the final 'target' values and we'll do this again to get the
4948 * optimal watermarks. For gen9+ platforms, the values we program here
4949 * will be the final target values which will get automatically latched
4950 * at vblank time; no further programming will be necessary.
4951 *
4952 * If a platform hasn't been transitioned to atomic watermarks yet,
4953 * we'll continue to update watermarks the old way, if flags tell
4954 * us to.
4955 */
4956 if (dev_priv->display.initial_watermarks != NULL)
4957 dev_priv->display.initial_watermarks(old_intel_state,
4958 pipe_config);
4959 else if (pipe_config->update_wm_pre)
4960 intel_update_watermarks(crtc);
4961 }
4962
4963 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4964 {
4965 struct drm_device *dev = crtc->dev;
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 struct drm_plane *p;
4968 int pipe = intel_crtc->pipe;
4969
4970 intel_crtc_dpms_overlay_disable(intel_crtc);
4971
4972 drm_for_each_plane_mask(p, dev, plane_mask)
4973 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
4974
4975 /*
4976 * FIXME: Once we grow proper nuclear flip support out of this we need
4977 * to compute the mask of flip planes precisely. For the time being
4978 * consider this a flip to a NULL plane.
4979 */
4980 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
4981 }
4982
4983 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
4984 struct intel_crtc_state *crtc_state,
4985 struct drm_atomic_state *old_state)
4986 {
4987 struct drm_connector_state *conn_state;
4988 struct drm_connector *conn;
4989 int i;
4990
4991 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
4992 struct intel_encoder *encoder =
4993 to_intel_encoder(conn_state->best_encoder);
4994
4995 if (conn_state->crtc != crtc)
4996 continue;
4997
4998 if (encoder->pre_pll_enable)
4999 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5000 }
5001 }
5002
5003 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5004 struct intel_crtc_state *crtc_state,
5005 struct drm_atomic_state *old_state)
5006 {
5007 struct drm_connector_state *conn_state;
5008 struct drm_connector *conn;
5009 int i;
5010
5011 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5012 struct intel_encoder *encoder =
5013 to_intel_encoder(conn_state->best_encoder);
5014
5015 if (conn_state->crtc != crtc)
5016 continue;
5017
5018 if (encoder->pre_enable)
5019 encoder->pre_enable(encoder, crtc_state, conn_state);
5020 }
5021 }
5022
5023 static void intel_encoders_enable(struct drm_crtc *crtc,
5024 struct intel_crtc_state *crtc_state,
5025 struct drm_atomic_state *old_state)
5026 {
5027 struct drm_connector_state *conn_state;
5028 struct drm_connector *conn;
5029 int i;
5030
5031 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5032 struct intel_encoder *encoder =
5033 to_intel_encoder(conn_state->best_encoder);
5034
5035 if (conn_state->crtc != crtc)
5036 continue;
5037
5038 encoder->enable(encoder, crtc_state, conn_state);
5039 intel_opregion_notify_encoder(encoder, true);
5040 }
5041 }
5042
5043 static void intel_encoders_disable(struct drm_crtc *crtc,
5044 struct intel_crtc_state *old_crtc_state,
5045 struct drm_atomic_state *old_state)
5046 {
5047 struct drm_connector_state *old_conn_state;
5048 struct drm_connector *conn;
5049 int i;
5050
5051 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5052 struct intel_encoder *encoder =
5053 to_intel_encoder(old_conn_state->best_encoder);
5054
5055 if (old_conn_state->crtc != crtc)
5056 continue;
5057
5058 intel_opregion_notify_encoder(encoder, false);
5059 encoder->disable(encoder, old_crtc_state, old_conn_state);
5060 }
5061 }
5062
5063 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5064 struct intel_crtc_state *old_crtc_state,
5065 struct drm_atomic_state *old_state)
5066 {
5067 struct drm_connector_state *old_conn_state;
5068 struct drm_connector *conn;
5069 int i;
5070
5071 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5072 struct intel_encoder *encoder =
5073 to_intel_encoder(old_conn_state->best_encoder);
5074
5075 if (old_conn_state->crtc != crtc)
5076 continue;
5077
5078 if (encoder->post_disable)
5079 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5080 }
5081 }
5082
5083 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5084 struct intel_crtc_state *old_crtc_state,
5085 struct drm_atomic_state *old_state)
5086 {
5087 struct drm_connector_state *old_conn_state;
5088 struct drm_connector *conn;
5089 int i;
5090
5091 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5092 struct intel_encoder *encoder =
5093 to_intel_encoder(old_conn_state->best_encoder);
5094
5095 if (old_conn_state->crtc != crtc)
5096 continue;
5097
5098 if (encoder->post_pll_disable)
5099 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5100 }
5101 }
5102
5103 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5104 struct drm_atomic_state *old_state)
5105 {
5106 struct drm_crtc *crtc = pipe_config->base.crtc;
5107 struct drm_device *dev = crtc->dev;
5108 struct drm_i915_private *dev_priv = to_i915(dev);
5109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5110 int pipe = intel_crtc->pipe;
5111 struct intel_atomic_state *old_intel_state =
5112 to_intel_atomic_state(old_state);
5113
5114 if (WARN_ON(intel_crtc->active))
5115 return;
5116
5117 /*
5118 * Sometimes spurious CPU pipe underruns happen during FDI
5119 * training, at least with VGA+HDMI cloning. Suppress them.
5120 *
5121 * On ILK we get an occasional spurious CPU pipe underruns
5122 * between eDP port A enable and vdd enable. Also PCH port
5123 * enable seems to result in the occasional CPU pipe underrun.
5124 *
5125 * Spurious PCH underruns also occur during PCH enabling.
5126 */
5127 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5128 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5129 if (intel_crtc->config->has_pch_encoder)
5130 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5131
5132 if (intel_crtc->config->has_pch_encoder)
5133 intel_prepare_shared_dpll(intel_crtc);
5134
5135 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5136 intel_dp_set_m_n(intel_crtc, M1_N1);
5137
5138 intel_set_pipe_timings(intel_crtc);
5139 intel_set_pipe_src_size(intel_crtc);
5140
5141 if (intel_crtc->config->has_pch_encoder) {
5142 intel_cpu_transcoder_set_m_n(intel_crtc,
5143 &intel_crtc->config->fdi_m_n, NULL);
5144 }
5145
5146 ironlake_set_pipeconf(crtc);
5147
5148 intel_crtc->active = true;
5149
5150 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5151
5152 if (intel_crtc->config->has_pch_encoder) {
5153 /* Note: FDI PLL enabling _must_ be done before we enable the
5154 * cpu pipes, hence this is separate from all the other fdi/pch
5155 * enabling. */
5156 ironlake_fdi_pll_enable(intel_crtc);
5157 } else {
5158 assert_fdi_tx_disabled(dev_priv, pipe);
5159 assert_fdi_rx_disabled(dev_priv, pipe);
5160 }
5161
5162 ironlake_pfit_enable(intel_crtc);
5163
5164 /*
5165 * On ILK+ LUT must be loaded before the pipe is running but with
5166 * clocks enabled
5167 */
5168 intel_color_load_luts(&pipe_config->base);
5169
5170 if (dev_priv->display.initial_watermarks != NULL)
5171 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5172 intel_enable_pipe(intel_crtc);
5173
5174 if (intel_crtc->config->has_pch_encoder)
5175 ironlake_pch_enable(pipe_config);
5176
5177 assert_vblank_disabled(crtc);
5178 drm_crtc_vblank_on(crtc);
5179
5180 intel_encoders_enable(crtc, pipe_config, old_state);
5181
5182 if (HAS_PCH_CPT(dev_priv))
5183 cpt_verify_modeset(dev, intel_crtc->pipe);
5184
5185 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5186 if (intel_crtc->config->has_pch_encoder)
5187 intel_wait_for_vblank(dev_priv, pipe);
5188 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5189 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5190 }
5191
5192 /* IPS only exists on ULT machines and is tied to pipe A. */
5193 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5194 {
5195 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5196 }
5197
5198 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5199 struct drm_atomic_state *old_state)
5200 {
5201 struct drm_crtc *crtc = pipe_config->base.crtc;
5202 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5204 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5205 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5206 struct intel_atomic_state *old_intel_state =
5207 to_intel_atomic_state(old_state);
5208
5209 if (WARN_ON(intel_crtc->active))
5210 return;
5211
5212 if (intel_crtc->config->has_pch_encoder)
5213 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5214
5215 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5216
5217 if (intel_crtc->config->shared_dpll)
5218 intel_enable_shared_dpll(intel_crtc);
5219
5220 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5221 intel_dp_set_m_n(intel_crtc, M1_N1);
5222
5223 if (!transcoder_is_dsi(cpu_transcoder))
5224 intel_set_pipe_timings(intel_crtc);
5225
5226 intel_set_pipe_src_size(intel_crtc);
5227
5228 if (cpu_transcoder != TRANSCODER_EDP &&
5229 !transcoder_is_dsi(cpu_transcoder)) {
5230 I915_WRITE(PIPE_MULT(cpu_transcoder),
5231 intel_crtc->config->pixel_multiplier - 1);
5232 }
5233
5234 if (intel_crtc->config->has_pch_encoder) {
5235 intel_cpu_transcoder_set_m_n(intel_crtc,
5236 &intel_crtc->config->fdi_m_n, NULL);
5237 }
5238
5239 if (!transcoder_is_dsi(cpu_transcoder))
5240 haswell_set_pipeconf(crtc);
5241
5242 haswell_set_pipemisc(crtc);
5243
5244 intel_color_set_csc(&pipe_config->base);
5245
5246 intel_crtc->active = true;
5247
5248 if (intel_crtc->config->has_pch_encoder)
5249 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5250 else
5251 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5252
5253 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5254
5255 if (intel_crtc->config->has_pch_encoder)
5256 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5257
5258 if (!transcoder_is_dsi(cpu_transcoder))
5259 intel_ddi_enable_pipe_clock(pipe_config);
5260
5261 if (INTEL_GEN(dev_priv) >= 9)
5262 skylake_pfit_enable(intel_crtc);
5263 else
5264 ironlake_pfit_enable(intel_crtc);
5265
5266 /*
5267 * On ILK+ LUT must be loaded before the pipe is running but with
5268 * clocks enabled
5269 */
5270 intel_color_load_luts(&pipe_config->base);
5271
5272 intel_ddi_set_pipe_settings(pipe_config);
5273 if (!transcoder_is_dsi(cpu_transcoder))
5274 intel_ddi_enable_transcoder_func(pipe_config);
5275
5276 if (dev_priv->display.initial_watermarks != NULL)
5277 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5278
5279 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5280 if (!transcoder_is_dsi(cpu_transcoder))
5281 intel_enable_pipe(intel_crtc);
5282
5283 if (intel_crtc->config->has_pch_encoder)
5284 lpt_pch_enable(pipe_config);
5285
5286 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5287 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5288
5289 assert_vblank_disabled(crtc);
5290 drm_crtc_vblank_on(crtc);
5291
5292 intel_encoders_enable(crtc, pipe_config, old_state);
5293
5294 if (intel_crtc->config->has_pch_encoder) {
5295 intel_wait_for_vblank(dev_priv, pipe);
5296 intel_wait_for_vblank(dev_priv, pipe);
5297 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5298 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5299 }
5300
5301 /* If we change the relative order between pipe/planes enabling, we need
5302 * to change the workaround. */
5303 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5304 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5305 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5306 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5307 }
5308 }
5309
5310 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5311 {
5312 struct drm_device *dev = crtc->base.dev;
5313 struct drm_i915_private *dev_priv = to_i915(dev);
5314 int pipe = crtc->pipe;
5315
5316 /* To avoid upsetting the power well on haswell only disable the pfit if
5317 * it's in use. The hw state code will make sure we get this right. */
5318 if (force || crtc->config->pch_pfit.enabled) {
5319 I915_WRITE(PF_CTL(pipe), 0);
5320 I915_WRITE(PF_WIN_POS(pipe), 0);
5321 I915_WRITE(PF_WIN_SZ(pipe), 0);
5322 }
5323 }
5324
5325 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5326 struct drm_atomic_state *old_state)
5327 {
5328 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5329 struct drm_device *dev = crtc->dev;
5330 struct drm_i915_private *dev_priv = to_i915(dev);
5331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5332 int pipe = intel_crtc->pipe;
5333
5334 /*
5335 * Sometimes spurious CPU pipe underruns happen when the
5336 * pipe is already disabled, but FDI RX/TX is still enabled.
5337 * Happens at least with VGA+HDMI cloning. Suppress them.
5338 */
5339 if (intel_crtc->config->has_pch_encoder) {
5340 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5341 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5342 }
5343
5344 intel_encoders_disable(crtc, old_crtc_state, old_state);
5345
5346 drm_crtc_vblank_off(crtc);
5347 assert_vblank_disabled(crtc);
5348
5349 intel_disable_pipe(intel_crtc);
5350
5351 ironlake_pfit_disable(intel_crtc, false);
5352
5353 if (intel_crtc->config->has_pch_encoder)
5354 ironlake_fdi_disable(crtc);
5355
5356 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5357
5358 if (intel_crtc->config->has_pch_encoder) {
5359 ironlake_disable_pch_transcoder(dev_priv, pipe);
5360
5361 if (HAS_PCH_CPT(dev_priv)) {
5362 i915_reg_t reg;
5363 u32 temp;
5364
5365 /* disable TRANS_DP_CTL */
5366 reg = TRANS_DP_CTL(pipe);
5367 temp = I915_READ(reg);
5368 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5369 TRANS_DP_PORT_SEL_MASK);
5370 temp |= TRANS_DP_PORT_SEL_NONE;
5371 I915_WRITE(reg, temp);
5372
5373 /* disable DPLL_SEL */
5374 temp = I915_READ(PCH_DPLL_SEL);
5375 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5376 I915_WRITE(PCH_DPLL_SEL, temp);
5377 }
5378
5379 ironlake_fdi_pll_disable(intel_crtc);
5380 }
5381
5382 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5383 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5384 }
5385
5386 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5387 struct drm_atomic_state *old_state)
5388 {
5389 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5390 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5392 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5393
5394 if (intel_crtc->config->has_pch_encoder)
5395 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5396
5397 intel_encoders_disable(crtc, old_crtc_state, old_state);
5398
5399 drm_crtc_vblank_off(crtc);
5400 assert_vblank_disabled(crtc);
5401
5402 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5403 if (!transcoder_is_dsi(cpu_transcoder))
5404 intel_disable_pipe(intel_crtc);
5405
5406 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5407 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5408
5409 if (!transcoder_is_dsi(cpu_transcoder))
5410 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5411
5412 if (INTEL_GEN(dev_priv) >= 9)
5413 skylake_scaler_disable(intel_crtc);
5414 else
5415 ironlake_pfit_disable(intel_crtc, false);
5416
5417 if (!transcoder_is_dsi(cpu_transcoder))
5418 intel_ddi_disable_pipe_clock(intel_crtc->config);
5419
5420 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5421
5422 if (old_crtc_state->has_pch_encoder)
5423 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5424 }
5425
5426 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5427 {
5428 struct drm_device *dev = crtc->base.dev;
5429 struct drm_i915_private *dev_priv = to_i915(dev);
5430 struct intel_crtc_state *pipe_config = crtc->config;
5431
5432 if (!pipe_config->gmch_pfit.control)
5433 return;
5434
5435 /*
5436 * The panel fitter should only be adjusted whilst the pipe is disabled,
5437 * according to register description and PRM.
5438 */
5439 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5440 assert_pipe_disabled(dev_priv, crtc->pipe);
5441
5442 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5443 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5444
5445 /* Border color in case we don't scale up to the full screen. Black by
5446 * default, change to something else for debugging. */
5447 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5448 }
5449
5450 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5451 {
5452 switch (port) {
5453 case PORT_A:
5454 return POWER_DOMAIN_PORT_DDI_A_LANES;
5455 case PORT_B:
5456 return POWER_DOMAIN_PORT_DDI_B_LANES;
5457 case PORT_C:
5458 return POWER_DOMAIN_PORT_DDI_C_LANES;
5459 case PORT_D:
5460 return POWER_DOMAIN_PORT_DDI_D_LANES;
5461 case PORT_E:
5462 return POWER_DOMAIN_PORT_DDI_E_LANES;
5463 default:
5464 MISSING_CASE(port);
5465 return POWER_DOMAIN_PORT_OTHER;
5466 }
5467 }
5468
5469 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5470 struct intel_crtc_state *crtc_state)
5471 {
5472 struct drm_device *dev = crtc->dev;
5473 struct drm_i915_private *dev_priv = to_i915(dev);
5474 struct drm_encoder *encoder;
5475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5476 enum pipe pipe = intel_crtc->pipe;
5477 u64 mask;
5478 enum transcoder transcoder = crtc_state->cpu_transcoder;
5479
5480 if (!crtc_state->base.active)
5481 return 0;
5482
5483 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5484 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5485 if (crtc_state->pch_pfit.enabled ||
5486 crtc_state->pch_pfit.force_thru)
5487 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5488
5489 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5490 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5491
5492 mask |= BIT_ULL(intel_encoder->power_domain);
5493 }
5494
5495 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5496 mask |= BIT(POWER_DOMAIN_AUDIO);
5497
5498 if (crtc_state->shared_dpll)
5499 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5500
5501 return mask;
5502 }
5503
5504 static u64
5505 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5506 struct intel_crtc_state *crtc_state)
5507 {
5508 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5510 enum intel_display_power_domain domain;
5511 u64 domains, new_domains, old_domains;
5512
5513 old_domains = intel_crtc->enabled_power_domains;
5514 intel_crtc->enabled_power_domains = new_domains =
5515 get_crtc_power_domains(crtc, crtc_state);
5516
5517 domains = new_domains & ~old_domains;
5518
5519 for_each_power_domain(domain, domains)
5520 intel_display_power_get(dev_priv, domain);
5521
5522 return old_domains & ~new_domains;
5523 }
5524
5525 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5526 u64 domains)
5527 {
5528 enum intel_display_power_domain domain;
5529
5530 for_each_power_domain(domain, domains)
5531 intel_display_power_put(dev_priv, domain);
5532 }
5533
5534 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5535 struct drm_atomic_state *old_state)
5536 {
5537 struct intel_atomic_state *old_intel_state =
5538 to_intel_atomic_state(old_state);
5539 struct drm_crtc *crtc = pipe_config->base.crtc;
5540 struct drm_device *dev = crtc->dev;
5541 struct drm_i915_private *dev_priv = to_i915(dev);
5542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5543 int pipe = intel_crtc->pipe;
5544
5545 if (WARN_ON(intel_crtc->active))
5546 return;
5547
5548 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5549 intel_dp_set_m_n(intel_crtc, M1_N1);
5550
5551 intel_set_pipe_timings(intel_crtc);
5552 intel_set_pipe_src_size(intel_crtc);
5553
5554 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5555 struct drm_i915_private *dev_priv = to_i915(dev);
5556
5557 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5558 I915_WRITE(CHV_CANVAS(pipe), 0);
5559 }
5560
5561 i9xx_set_pipeconf(intel_crtc);
5562
5563 intel_crtc->active = true;
5564
5565 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5566
5567 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5568
5569 if (IS_CHERRYVIEW(dev_priv)) {
5570 chv_prepare_pll(intel_crtc, intel_crtc->config);
5571 chv_enable_pll(intel_crtc, intel_crtc->config);
5572 } else {
5573 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5574 vlv_enable_pll(intel_crtc, intel_crtc->config);
5575 }
5576
5577 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5578
5579 i9xx_pfit_enable(intel_crtc);
5580
5581 intel_color_load_luts(&pipe_config->base);
5582
5583 dev_priv->display.initial_watermarks(old_intel_state,
5584 pipe_config);
5585 intel_enable_pipe(intel_crtc);
5586
5587 assert_vblank_disabled(crtc);
5588 drm_crtc_vblank_on(crtc);
5589
5590 intel_encoders_enable(crtc, pipe_config, old_state);
5591 }
5592
5593 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5594 {
5595 struct drm_device *dev = crtc->base.dev;
5596 struct drm_i915_private *dev_priv = to_i915(dev);
5597
5598 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5599 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5600 }
5601
5602 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5603 struct drm_atomic_state *old_state)
5604 {
5605 struct intel_atomic_state *old_intel_state =
5606 to_intel_atomic_state(old_state);
5607 struct drm_crtc *crtc = pipe_config->base.crtc;
5608 struct drm_device *dev = crtc->dev;
5609 struct drm_i915_private *dev_priv = to_i915(dev);
5610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611 enum pipe pipe = intel_crtc->pipe;
5612
5613 if (WARN_ON(intel_crtc->active))
5614 return;
5615
5616 i9xx_set_pll_dividers(intel_crtc);
5617
5618 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5619 intel_dp_set_m_n(intel_crtc, M1_N1);
5620
5621 intel_set_pipe_timings(intel_crtc);
5622 intel_set_pipe_src_size(intel_crtc);
5623
5624 i9xx_set_pipeconf(intel_crtc);
5625
5626 intel_crtc->active = true;
5627
5628 if (!IS_GEN2(dev_priv))
5629 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5630
5631 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5632
5633 i9xx_enable_pll(intel_crtc);
5634
5635 i9xx_pfit_enable(intel_crtc);
5636
5637 intel_color_load_luts(&pipe_config->base);
5638
5639 if (dev_priv->display.initial_watermarks != NULL)
5640 dev_priv->display.initial_watermarks(old_intel_state,
5641 intel_crtc->config);
5642 else
5643 intel_update_watermarks(intel_crtc);
5644 intel_enable_pipe(intel_crtc);
5645
5646 assert_vblank_disabled(crtc);
5647 drm_crtc_vblank_on(crtc);
5648
5649 intel_encoders_enable(crtc, pipe_config, old_state);
5650 }
5651
5652 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5653 {
5654 struct drm_device *dev = crtc->base.dev;
5655 struct drm_i915_private *dev_priv = to_i915(dev);
5656
5657 if (!crtc->config->gmch_pfit.control)
5658 return;
5659
5660 assert_pipe_disabled(dev_priv, crtc->pipe);
5661
5662 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5663 I915_READ(PFIT_CONTROL));
5664 I915_WRITE(PFIT_CONTROL, 0);
5665 }
5666
5667 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5668 struct drm_atomic_state *old_state)
5669 {
5670 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5671 struct drm_device *dev = crtc->dev;
5672 struct drm_i915_private *dev_priv = to_i915(dev);
5673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674 int pipe = intel_crtc->pipe;
5675
5676 /*
5677 * On gen2 planes are double buffered but the pipe isn't, so we must
5678 * wait for planes to fully turn off before disabling the pipe.
5679 */
5680 if (IS_GEN2(dev_priv))
5681 intel_wait_for_vblank(dev_priv, pipe);
5682
5683 intel_encoders_disable(crtc, old_crtc_state, old_state);
5684
5685 drm_crtc_vblank_off(crtc);
5686 assert_vblank_disabled(crtc);
5687
5688 intel_disable_pipe(intel_crtc);
5689
5690 i9xx_pfit_disable(intel_crtc);
5691
5692 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5693
5694 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5695 if (IS_CHERRYVIEW(dev_priv))
5696 chv_disable_pll(dev_priv, pipe);
5697 else if (IS_VALLEYVIEW(dev_priv))
5698 vlv_disable_pll(dev_priv, pipe);
5699 else
5700 i9xx_disable_pll(intel_crtc);
5701 }
5702
5703 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5704
5705 if (!IS_GEN2(dev_priv))
5706 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5707
5708 if (!dev_priv->display.initial_watermarks)
5709 intel_update_watermarks(intel_crtc);
5710
5711 /* clock the pipe down to 640x480@60 to potentially save power */
5712 if (IS_I830(dev_priv))
5713 i830_enable_pipe(dev_priv, pipe);
5714 }
5715
5716 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5717 struct drm_modeset_acquire_ctx *ctx)
5718 {
5719 struct intel_encoder *encoder;
5720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5721 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5722 enum intel_display_power_domain domain;
5723 u64 domains;
5724 struct drm_atomic_state *state;
5725 struct intel_crtc_state *crtc_state;
5726 int ret;
5727
5728 if (!intel_crtc->active)
5729 return;
5730
5731 if (crtc->primary->state->visible) {
5732 intel_pre_disable_primary_noatomic(crtc);
5733
5734 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5735 crtc->primary->state->visible = false;
5736 }
5737
5738 state = drm_atomic_state_alloc(crtc->dev);
5739 if (!state) {
5740 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5741 crtc->base.id, crtc->name);
5742 return;
5743 }
5744
5745 state->acquire_ctx = ctx;
5746
5747 /* Everything's already locked, -EDEADLK can't happen. */
5748 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5749 ret = drm_atomic_add_affected_connectors(state, crtc);
5750
5751 WARN_ON(IS_ERR(crtc_state) || ret);
5752
5753 dev_priv->display.crtc_disable(crtc_state, state);
5754
5755 drm_atomic_state_put(state);
5756
5757 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5758 crtc->base.id, crtc->name);
5759
5760 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5761 crtc->state->active = false;
5762 intel_crtc->active = false;
5763 crtc->enabled = false;
5764 crtc->state->connector_mask = 0;
5765 crtc->state->encoder_mask = 0;
5766
5767 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5768 encoder->base.crtc = NULL;
5769
5770 intel_fbc_disable(intel_crtc);
5771 intel_update_watermarks(intel_crtc);
5772 intel_disable_shared_dpll(intel_crtc);
5773
5774 domains = intel_crtc->enabled_power_domains;
5775 for_each_power_domain(domain, domains)
5776 intel_display_power_put(dev_priv, domain);
5777 intel_crtc->enabled_power_domains = 0;
5778
5779 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5780 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5781 }
5782
5783 /*
5784 * turn all crtc's off, but do not adjust state
5785 * This has to be paired with a call to intel_modeset_setup_hw_state.
5786 */
5787 int intel_display_suspend(struct drm_device *dev)
5788 {
5789 struct drm_i915_private *dev_priv = to_i915(dev);
5790 struct drm_atomic_state *state;
5791 int ret;
5792
5793 state = drm_atomic_helper_suspend(dev);
5794 ret = PTR_ERR_OR_ZERO(state);
5795 if (ret)
5796 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5797 else
5798 dev_priv->modeset_restore_state = state;
5799 return ret;
5800 }
5801
5802 void intel_encoder_destroy(struct drm_encoder *encoder)
5803 {
5804 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5805
5806 drm_encoder_cleanup(encoder);
5807 kfree(intel_encoder);
5808 }
5809
5810 /* Cross check the actual hw state with our own modeset state tracking (and it's
5811 * internal consistency). */
5812 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5813 struct drm_connector_state *conn_state)
5814 {
5815 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5816
5817 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5818 connector->base.base.id,
5819 connector->base.name);
5820
5821 if (connector->get_hw_state(connector)) {
5822 struct intel_encoder *encoder = connector->encoder;
5823
5824 I915_STATE_WARN(!crtc_state,
5825 "connector enabled without attached crtc\n");
5826
5827 if (!crtc_state)
5828 return;
5829
5830 I915_STATE_WARN(!crtc_state->active,
5831 "connector is active, but attached crtc isn't\n");
5832
5833 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5834 return;
5835
5836 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5837 "atomic encoder doesn't match attached encoder\n");
5838
5839 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5840 "attached encoder crtc differs from connector crtc\n");
5841 } else {
5842 I915_STATE_WARN(crtc_state && crtc_state->active,
5843 "attached crtc is active, but connector isn't\n");
5844 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5845 "best encoder set without crtc!\n");
5846 }
5847 }
5848
5849 int intel_connector_init(struct intel_connector *connector)
5850 {
5851 struct intel_digital_connector_state *conn_state;
5852
5853 /*
5854 * Allocate enough memory to hold intel_digital_connector_state,
5855 * This might be a few bytes too many, but for connectors that don't
5856 * need it we'll free the state and allocate a smaller one on the first
5857 * succesful commit anyway.
5858 */
5859 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
5860 if (!conn_state)
5861 return -ENOMEM;
5862
5863 __drm_atomic_helper_connector_reset(&connector->base,
5864 &conn_state->base);
5865
5866 return 0;
5867 }
5868
5869 struct intel_connector *intel_connector_alloc(void)
5870 {
5871 struct intel_connector *connector;
5872
5873 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5874 if (!connector)
5875 return NULL;
5876
5877 if (intel_connector_init(connector) < 0) {
5878 kfree(connector);
5879 return NULL;
5880 }
5881
5882 return connector;
5883 }
5884
5885 /* Simple connector->get_hw_state implementation for encoders that support only
5886 * one connector and no cloning and hence the encoder state determines the state
5887 * of the connector. */
5888 bool intel_connector_get_hw_state(struct intel_connector *connector)
5889 {
5890 enum pipe pipe = 0;
5891 struct intel_encoder *encoder = connector->encoder;
5892
5893 return encoder->get_hw_state(encoder, &pipe);
5894 }
5895
5896 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5897 {
5898 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5899 return crtc_state->fdi_lanes;
5900
5901 return 0;
5902 }
5903
5904 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5905 struct intel_crtc_state *pipe_config)
5906 {
5907 struct drm_i915_private *dev_priv = to_i915(dev);
5908 struct drm_atomic_state *state = pipe_config->base.state;
5909 struct intel_crtc *other_crtc;
5910 struct intel_crtc_state *other_crtc_state;
5911
5912 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5913 pipe_name(pipe), pipe_config->fdi_lanes);
5914 if (pipe_config->fdi_lanes > 4) {
5915 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5916 pipe_name(pipe), pipe_config->fdi_lanes);
5917 return -EINVAL;
5918 }
5919
5920 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
5921 if (pipe_config->fdi_lanes > 2) {
5922 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5923 pipe_config->fdi_lanes);
5924 return -EINVAL;
5925 } else {
5926 return 0;
5927 }
5928 }
5929
5930 if (INTEL_INFO(dev_priv)->num_pipes == 2)
5931 return 0;
5932
5933 /* Ivybridge 3 pipe is really complicated */
5934 switch (pipe) {
5935 case PIPE_A:
5936 return 0;
5937 case PIPE_B:
5938 if (pipe_config->fdi_lanes <= 2)
5939 return 0;
5940
5941 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
5942 other_crtc_state =
5943 intel_atomic_get_crtc_state(state, other_crtc);
5944 if (IS_ERR(other_crtc_state))
5945 return PTR_ERR(other_crtc_state);
5946
5947 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
5948 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5949 pipe_name(pipe), pipe_config->fdi_lanes);
5950 return -EINVAL;
5951 }
5952 return 0;
5953 case PIPE_C:
5954 if (pipe_config->fdi_lanes > 2) {
5955 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5956 pipe_name(pipe), pipe_config->fdi_lanes);
5957 return -EINVAL;
5958 }
5959
5960 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
5961 other_crtc_state =
5962 intel_atomic_get_crtc_state(state, other_crtc);
5963 if (IS_ERR(other_crtc_state))
5964 return PTR_ERR(other_crtc_state);
5965
5966 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
5967 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5968 return -EINVAL;
5969 }
5970 return 0;
5971 default:
5972 BUG();
5973 }
5974 }
5975
5976 #define RETRY 1
5977 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5978 struct intel_crtc_state *pipe_config)
5979 {
5980 struct drm_device *dev = intel_crtc->base.dev;
5981 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5982 int lane, link_bw, fdi_dotclock, ret;
5983 bool needs_recompute = false;
5984
5985 retry:
5986 /* FDI is a binary signal running at ~2.7GHz, encoding
5987 * each output octet as 10 bits. The actual frequency
5988 * is stored as a divider into a 100MHz clock, and the
5989 * mode pixel clock is stored in units of 1KHz.
5990 * Hence the bw of each lane in terms of the mode signal
5991 * is:
5992 */
5993 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
5994
5995 fdi_dotclock = adjusted_mode->crtc_clock;
5996
5997 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5998 pipe_config->pipe_bpp);
5999
6000 pipe_config->fdi_lanes = lane;
6001
6002 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6003 link_bw, &pipe_config->fdi_m_n, false);
6004
6005 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6006 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6007 pipe_config->pipe_bpp -= 2*3;
6008 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6009 pipe_config->pipe_bpp);
6010 needs_recompute = true;
6011 pipe_config->bw_constrained = true;
6012
6013 goto retry;
6014 }
6015
6016 if (needs_recompute)
6017 return RETRY;
6018
6019 return ret;
6020 }
6021
6022 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6023 struct intel_crtc_state *pipe_config)
6024 {
6025 if (pipe_config->pipe_bpp > 24)
6026 return false;
6027
6028 /* HSW can handle pixel rate up to cdclk? */
6029 if (IS_HASWELL(dev_priv))
6030 return true;
6031
6032 /*
6033 * We compare against max which means we must take
6034 * the increased cdclk requirement into account when
6035 * calculating the new cdclk.
6036 *
6037 * Should measure whether using a lower cdclk w/o IPS
6038 */
6039 return pipe_config->pixel_rate <=
6040 dev_priv->max_cdclk_freq * 95 / 100;
6041 }
6042
6043 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6044 struct intel_crtc_state *pipe_config)
6045 {
6046 struct drm_device *dev = crtc->base.dev;
6047 struct drm_i915_private *dev_priv = to_i915(dev);
6048
6049 pipe_config->ips_enabled = i915.enable_ips &&
6050 hsw_crtc_supports_ips(crtc) &&
6051 pipe_config_supports_ips(dev_priv, pipe_config);
6052 }
6053
6054 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6055 {
6056 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6057
6058 /* GDG double wide on either pipe, otherwise pipe A only */
6059 return INTEL_INFO(dev_priv)->gen < 4 &&
6060 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6061 }
6062
6063 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6064 {
6065 uint32_t pixel_rate;
6066
6067 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6068
6069 /*
6070 * We only use IF-ID interlacing. If we ever use
6071 * PF-ID we'll need to adjust the pixel_rate here.
6072 */
6073
6074 if (pipe_config->pch_pfit.enabled) {
6075 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6076 uint32_t pfit_size = pipe_config->pch_pfit.size;
6077
6078 pipe_w = pipe_config->pipe_src_w;
6079 pipe_h = pipe_config->pipe_src_h;
6080
6081 pfit_w = (pfit_size >> 16) & 0xFFFF;
6082 pfit_h = pfit_size & 0xFFFF;
6083 if (pipe_w < pfit_w)
6084 pipe_w = pfit_w;
6085 if (pipe_h < pfit_h)
6086 pipe_h = pfit_h;
6087
6088 if (WARN_ON(!pfit_w || !pfit_h))
6089 return pixel_rate;
6090
6091 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6092 pfit_w * pfit_h);
6093 }
6094
6095 return pixel_rate;
6096 }
6097
6098 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6099 {
6100 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6101
6102 if (HAS_GMCH_DISPLAY(dev_priv))
6103 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6104 crtc_state->pixel_rate =
6105 crtc_state->base.adjusted_mode.crtc_clock;
6106 else
6107 crtc_state->pixel_rate =
6108 ilk_pipe_pixel_rate(crtc_state);
6109 }
6110
6111 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6112 struct intel_crtc_state *pipe_config)
6113 {
6114 struct drm_device *dev = crtc->base.dev;
6115 struct drm_i915_private *dev_priv = to_i915(dev);
6116 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6117 int clock_limit = dev_priv->max_dotclk_freq;
6118
6119 if (INTEL_GEN(dev_priv) < 4) {
6120 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6121
6122 /*
6123 * Enable double wide mode when the dot clock
6124 * is > 90% of the (display) core speed.
6125 */
6126 if (intel_crtc_supports_double_wide(crtc) &&
6127 adjusted_mode->crtc_clock > clock_limit) {
6128 clock_limit = dev_priv->max_dotclk_freq;
6129 pipe_config->double_wide = true;
6130 }
6131 }
6132
6133 if (adjusted_mode->crtc_clock > clock_limit) {
6134 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6135 adjusted_mode->crtc_clock, clock_limit,
6136 yesno(pipe_config->double_wide));
6137 return -EINVAL;
6138 }
6139
6140 /*
6141 * Pipe horizontal size must be even in:
6142 * - DVO ganged mode
6143 * - LVDS dual channel mode
6144 * - Double wide pipe
6145 */
6146 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6147 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6148 pipe_config->pipe_src_w &= ~1;
6149
6150 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6151 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6152 */
6153 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6154 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6155 return -EINVAL;
6156
6157 intel_crtc_compute_pixel_rate(pipe_config);
6158
6159 if (HAS_IPS(dev_priv))
6160 hsw_compute_ips_config(crtc, pipe_config);
6161
6162 if (pipe_config->has_pch_encoder)
6163 return ironlake_fdi_compute_config(crtc, pipe_config);
6164
6165 return 0;
6166 }
6167
6168 static void
6169 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6170 {
6171 while (*num > DATA_LINK_M_N_MASK ||
6172 *den > DATA_LINK_M_N_MASK) {
6173 *num >>= 1;
6174 *den >>= 1;
6175 }
6176 }
6177
6178 static void compute_m_n(unsigned int m, unsigned int n,
6179 uint32_t *ret_m, uint32_t *ret_n,
6180 bool reduce_m_n)
6181 {
6182 /*
6183 * Reduce M/N as much as possible without loss in precision. Several DP
6184 * dongles in particular seem to be fussy about too large *link* M/N
6185 * values. The passed in values are more likely to have the least
6186 * significant bits zero than M after rounding below, so do this first.
6187 */
6188 if (reduce_m_n) {
6189 while ((m & 1) == 0 && (n & 1) == 0) {
6190 m >>= 1;
6191 n >>= 1;
6192 }
6193 }
6194
6195 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6196 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6197 intel_reduce_m_n_ratio(ret_m, ret_n);
6198 }
6199
6200 void
6201 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6202 int pixel_clock, int link_clock,
6203 struct intel_link_m_n *m_n,
6204 bool reduce_m_n)
6205 {
6206 m_n->tu = 64;
6207
6208 compute_m_n(bits_per_pixel * pixel_clock,
6209 link_clock * nlanes * 8,
6210 &m_n->gmch_m, &m_n->gmch_n,
6211 reduce_m_n);
6212
6213 compute_m_n(pixel_clock, link_clock,
6214 &m_n->link_m, &m_n->link_n,
6215 reduce_m_n);
6216 }
6217
6218 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6219 {
6220 if (i915.panel_use_ssc >= 0)
6221 return i915.panel_use_ssc != 0;
6222 return dev_priv->vbt.lvds_use_ssc
6223 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6224 }
6225
6226 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6227 {
6228 return (1 << dpll->n) << 16 | dpll->m2;
6229 }
6230
6231 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6232 {
6233 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6234 }
6235
6236 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6237 struct intel_crtc_state *crtc_state,
6238 struct dpll *reduced_clock)
6239 {
6240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6241 u32 fp, fp2 = 0;
6242
6243 if (IS_PINEVIEW(dev_priv)) {
6244 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6245 if (reduced_clock)
6246 fp2 = pnv_dpll_compute_fp(reduced_clock);
6247 } else {
6248 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6249 if (reduced_clock)
6250 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6251 }
6252
6253 crtc_state->dpll_hw_state.fp0 = fp;
6254
6255 crtc->lowfreq_avail = false;
6256 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6257 reduced_clock) {
6258 crtc_state->dpll_hw_state.fp1 = fp2;
6259 crtc->lowfreq_avail = true;
6260 } else {
6261 crtc_state->dpll_hw_state.fp1 = fp;
6262 }
6263 }
6264
6265 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6266 pipe)
6267 {
6268 u32 reg_val;
6269
6270 /*
6271 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6272 * and set it to a reasonable value instead.
6273 */
6274 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6275 reg_val &= 0xffffff00;
6276 reg_val |= 0x00000030;
6277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6278
6279 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6280 reg_val &= 0x00ffffff;
6281 reg_val |= 0x8c000000;
6282 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6283
6284 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6285 reg_val &= 0xffffff00;
6286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6287
6288 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6289 reg_val &= 0x00ffffff;
6290 reg_val |= 0xb0000000;
6291 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6292 }
6293
6294 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6295 struct intel_link_m_n *m_n)
6296 {
6297 struct drm_device *dev = crtc->base.dev;
6298 struct drm_i915_private *dev_priv = to_i915(dev);
6299 int pipe = crtc->pipe;
6300
6301 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6302 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6303 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6304 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6305 }
6306
6307 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6308 struct intel_link_m_n *m_n,
6309 struct intel_link_m_n *m2_n2)
6310 {
6311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6312 int pipe = crtc->pipe;
6313 enum transcoder transcoder = crtc->config->cpu_transcoder;
6314
6315 if (INTEL_GEN(dev_priv) >= 5) {
6316 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6317 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6318 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6319 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6320 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6321 * for gen < 8) and if DRRS is supported (to make sure the
6322 * registers are not unnecessarily accessed).
6323 */
6324 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6325 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6326 I915_WRITE(PIPE_DATA_M2(transcoder),
6327 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6328 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6329 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6330 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6331 }
6332 } else {
6333 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6334 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6335 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6336 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6337 }
6338 }
6339
6340 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6341 {
6342 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6343
6344 if (m_n == M1_N1) {
6345 dp_m_n = &crtc->config->dp_m_n;
6346 dp_m2_n2 = &crtc->config->dp_m2_n2;
6347 } else if (m_n == M2_N2) {
6348
6349 /*
6350 * M2_N2 registers are not supported. Hence m2_n2 divider value
6351 * needs to be programmed into M1_N1.
6352 */
6353 dp_m_n = &crtc->config->dp_m2_n2;
6354 } else {
6355 DRM_ERROR("Unsupported divider value\n");
6356 return;
6357 }
6358
6359 if (crtc->config->has_pch_encoder)
6360 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6361 else
6362 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6363 }
6364
6365 static void vlv_compute_dpll(struct intel_crtc *crtc,
6366 struct intel_crtc_state *pipe_config)
6367 {
6368 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6369 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6370 if (crtc->pipe != PIPE_A)
6371 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6372
6373 /* DPLL not used with DSI, but still need the rest set up */
6374 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6375 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6376 DPLL_EXT_BUFFER_ENABLE_VLV;
6377
6378 pipe_config->dpll_hw_state.dpll_md =
6379 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6380 }
6381
6382 static void chv_compute_dpll(struct intel_crtc *crtc,
6383 struct intel_crtc_state *pipe_config)
6384 {
6385 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6386 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6387 if (crtc->pipe != PIPE_A)
6388 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6389
6390 /* DPLL not used with DSI, but still need the rest set up */
6391 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6392 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6393
6394 pipe_config->dpll_hw_state.dpll_md =
6395 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6396 }
6397
6398 static void vlv_prepare_pll(struct intel_crtc *crtc,
6399 const struct intel_crtc_state *pipe_config)
6400 {
6401 struct drm_device *dev = crtc->base.dev;
6402 struct drm_i915_private *dev_priv = to_i915(dev);
6403 enum pipe pipe = crtc->pipe;
6404 u32 mdiv;
6405 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6406 u32 coreclk, reg_val;
6407
6408 /* Enable Refclk */
6409 I915_WRITE(DPLL(pipe),
6410 pipe_config->dpll_hw_state.dpll &
6411 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6412
6413 /* No need to actually set up the DPLL with DSI */
6414 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6415 return;
6416
6417 mutex_lock(&dev_priv->sb_lock);
6418
6419 bestn = pipe_config->dpll.n;
6420 bestm1 = pipe_config->dpll.m1;
6421 bestm2 = pipe_config->dpll.m2;
6422 bestp1 = pipe_config->dpll.p1;
6423 bestp2 = pipe_config->dpll.p2;
6424
6425 /* See eDP HDMI DPIO driver vbios notes doc */
6426
6427 /* PLL B needs special handling */
6428 if (pipe == PIPE_B)
6429 vlv_pllb_recal_opamp(dev_priv, pipe);
6430
6431 /* Set up Tx target for periodic Rcomp update */
6432 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6433
6434 /* Disable target IRef on PLL */
6435 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6436 reg_val &= 0x00ffffff;
6437 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6438
6439 /* Disable fast lock */
6440 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6441
6442 /* Set idtafcrecal before PLL is enabled */
6443 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6444 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6445 mdiv |= ((bestn << DPIO_N_SHIFT));
6446 mdiv |= (1 << DPIO_K_SHIFT);
6447
6448 /*
6449 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6450 * but we don't support that).
6451 * Note: don't use the DAC post divider as it seems unstable.
6452 */
6453 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6455
6456 mdiv |= DPIO_ENABLE_CALIBRATION;
6457 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6458
6459 /* Set HBR and RBR LPF coefficients */
6460 if (pipe_config->port_clock == 162000 ||
6461 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6462 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6463 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6464 0x009f0003);
6465 else
6466 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6467 0x00d0000f);
6468
6469 if (intel_crtc_has_dp_encoder(pipe_config)) {
6470 /* Use SSC source */
6471 if (pipe == PIPE_A)
6472 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6473 0x0df40000);
6474 else
6475 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6476 0x0df70000);
6477 } else { /* HDMI or VGA */
6478 /* Use bend source */
6479 if (pipe == PIPE_A)
6480 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6481 0x0df70000);
6482 else
6483 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6484 0x0df40000);
6485 }
6486
6487 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6488 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6489 if (intel_crtc_has_dp_encoder(crtc->config))
6490 coreclk |= 0x01000000;
6491 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6492
6493 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6494 mutex_unlock(&dev_priv->sb_lock);
6495 }
6496
6497 static void chv_prepare_pll(struct intel_crtc *crtc,
6498 const struct intel_crtc_state *pipe_config)
6499 {
6500 struct drm_device *dev = crtc->base.dev;
6501 struct drm_i915_private *dev_priv = to_i915(dev);
6502 enum pipe pipe = crtc->pipe;
6503 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6504 u32 loopfilter, tribuf_calcntr;
6505 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6506 u32 dpio_val;
6507 int vco;
6508
6509 /* Enable Refclk and SSC */
6510 I915_WRITE(DPLL(pipe),
6511 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6512
6513 /* No need to actually set up the DPLL with DSI */
6514 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6515 return;
6516
6517 bestn = pipe_config->dpll.n;
6518 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6519 bestm1 = pipe_config->dpll.m1;
6520 bestm2 = pipe_config->dpll.m2 >> 22;
6521 bestp1 = pipe_config->dpll.p1;
6522 bestp2 = pipe_config->dpll.p2;
6523 vco = pipe_config->dpll.vco;
6524 dpio_val = 0;
6525 loopfilter = 0;
6526
6527 mutex_lock(&dev_priv->sb_lock);
6528
6529 /* p1 and p2 divider */
6530 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6531 5 << DPIO_CHV_S1_DIV_SHIFT |
6532 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6533 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6534 1 << DPIO_CHV_K_DIV_SHIFT);
6535
6536 /* Feedback post-divider - m2 */
6537 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6538
6539 /* Feedback refclk divider - n and m1 */
6540 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6541 DPIO_CHV_M1_DIV_BY_2 |
6542 1 << DPIO_CHV_N_DIV_SHIFT);
6543
6544 /* M2 fraction division */
6545 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6546
6547 /* M2 fraction division enable */
6548 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6549 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6550 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6551 if (bestm2_frac)
6552 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6553 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6554
6555 /* Program digital lock detect threshold */
6556 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6557 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6558 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6559 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6560 if (!bestm2_frac)
6561 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6562 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6563
6564 /* Loop filter */
6565 if (vco == 5400000) {
6566 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6567 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6568 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6569 tribuf_calcntr = 0x9;
6570 } else if (vco <= 6200000) {
6571 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6572 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6573 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6574 tribuf_calcntr = 0x9;
6575 } else if (vco <= 6480000) {
6576 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6577 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6578 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6579 tribuf_calcntr = 0x8;
6580 } else {
6581 /* Not supported. Apply the same limits as in the max case */
6582 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6583 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6584 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6585 tribuf_calcntr = 0;
6586 }
6587 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6588
6589 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6590 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6591 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6592 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6593
6594 /* AFC Recal */
6595 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6596 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6597 DPIO_AFC_RECAL);
6598
6599 mutex_unlock(&dev_priv->sb_lock);
6600 }
6601
6602 /**
6603 * vlv_force_pll_on - forcibly enable just the PLL
6604 * @dev_priv: i915 private structure
6605 * @pipe: pipe PLL to enable
6606 * @dpll: PLL configuration
6607 *
6608 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6609 * in cases where we need the PLL enabled even when @pipe is not going to
6610 * be enabled.
6611 */
6612 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6613 const struct dpll *dpll)
6614 {
6615 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6616 struct intel_crtc_state *pipe_config;
6617
6618 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6619 if (!pipe_config)
6620 return -ENOMEM;
6621
6622 pipe_config->base.crtc = &crtc->base;
6623 pipe_config->pixel_multiplier = 1;
6624 pipe_config->dpll = *dpll;
6625
6626 if (IS_CHERRYVIEW(dev_priv)) {
6627 chv_compute_dpll(crtc, pipe_config);
6628 chv_prepare_pll(crtc, pipe_config);
6629 chv_enable_pll(crtc, pipe_config);
6630 } else {
6631 vlv_compute_dpll(crtc, pipe_config);
6632 vlv_prepare_pll(crtc, pipe_config);
6633 vlv_enable_pll(crtc, pipe_config);
6634 }
6635
6636 kfree(pipe_config);
6637
6638 return 0;
6639 }
6640
6641 /**
6642 * vlv_force_pll_off - forcibly disable just the PLL
6643 * @dev_priv: i915 private structure
6644 * @pipe: pipe PLL to disable
6645 *
6646 * Disable the PLL for @pipe. To be used in cases where we need
6647 * the PLL enabled even when @pipe is not going to be enabled.
6648 */
6649 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6650 {
6651 if (IS_CHERRYVIEW(dev_priv))
6652 chv_disable_pll(dev_priv, pipe);
6653 else
6654 vlv_disable_pll(dev_priv, pipe);
6655 }
6656
6657 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6658 struct intel_crtc_state *crtc_state,
6659 struct dpll *reduced_clock)
6660 {
6661 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6662 u32 dpll;
6663 struct dpll *clock = &crtc_state->dpll;
6664
6665 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6666
6667 dpll = DPLL_VGA_MODE_DIS;
6668
6669 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6670 dpll |= DPLLB_MODE_LVDS;
6671 else
6672 dpll |= DPLLB_MODE_DAC_SERIAL;
6673
6674 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6675 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6676 dpll |= (crtc_state->pixel_multiplier - 1)
6677 << SDVO_MULTIPLIER_SHIFT_HIRES;
6678 }
6679
6680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6681 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6682 dpll |= DPLL_SDVO_HIGH_SPEED;
6683
6684 if (intel_crtc_has_dp_encoder(crtc_state))
6685 dpll |= DPLL_SDVO_HIGH_SPEED;
6686
6687 /* compute bitmask from p1 value */
6688 if (IS_PINEVIEW(dev_priv))
6689 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6690 else {
6691 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6692 if (IS_G4X(dev_priv) && reduced_clock)
6693 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6694 }
6695 switch (clock->p2) {
6696 case 5:
6697 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6698 break;
6699 case 7:
6700 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6701 break;
6702 case 10:
6703 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6704 break;
6705 case 14:
6706 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6707 break;
6708 }
6709 if (INTEL_GEN(dev_priv) >= 4)
6710 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6711
6712 if (crtc_state->sdvo_tv_clock)
6713 dpll |= PLL_REF_INPUT_TVCLKINBC;
6714 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6715 intel_panel_use_ssc(dev_priv))
6716 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6717 else
6718 dpll |= PLL_REF_INPUT_DREFCLK;
6719
6720 dpll |= DPLL_VCO_ENABLE;
6721 crtc_state->dpll_hw_state.dpll = dpll;
6722
6723 if (INTEL_GEN(dev_priv) >= 4) {
6724 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6725 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6726 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6727 }
6728 }
6729
6730 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6731 struct intel_crtc_state *crtc_state,
6732 struct dpll *reduced_clock)
6733 {
6734 struct drm_device *dev = crtc->base.dev;
6735 struct drm_i915_private *dev_priv = to_i915(dev);
6736 u32 dpll;
6737 struct dpll *clock = &crtc_state->dpll;
6738
6739 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6740
6741 dpll = DPLL_VGA_MODE_DIS;
6742
6743 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6744 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6745 } else {
6746 if (clock->p1 == 2)
6747 dpll |= PLL_P1_DIVIDE_BY_TWO;
6748 else
6749 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6750 if (clock->p2 == 4)
6751 dpll |= PLL_P2_DIVIDE_BY_4;
6752 }
6753
6754 if (!IS_I830(dev_priv) &&
6755 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6756 dpll |= DPLL_DVO_2X_MODE;
6757
6758 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6759 intel_panel_use_ssc(dev_priv))
6760 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6761 else
6762 dpll |= PLL_REF_INPUT_DREFCLK;
6763
6764 dpll |= DPLL_VCO_ENABLE;
6765 crtc_state->dpll_hw_state.dpll = dpll;
6766 }
6767
6768 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6769 {
6770 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6771 enum pipe pipe = intel_crtc->pipe;
6772 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6773 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6774 uint32_t crtc_vtotal, crtc_vblank_end;
6775 int vsyncshift = 0;
6776
6777 /* We need to be careful not to changed the adjusted mode, for otherwise
6778 * the hw state checker will get angry at the mismatch. */
6779 crtc_vtotal = adjusted_mode->crtc_vtotal;
6780 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6781
6782 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6783 /* the chip adds 2 halflines automatically */
6784 crtc_vtotal -= 1;
6785 crtc_vblank_end -= 1;
6786
6787 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6788 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6789 else
6790 vsyncshift = adjusted_mode->crtc_hsync_start -
6791 adjusted_mode->crtc_htotal / 2;
6792 if (vsyncshift < 0)
6793 vsyncshift += adjusted_mode->crtc_htotal;
6794 }
6795
6796 if (INTEL_GEN(dev_priv) > 3)
6797 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6798
6799 I915_WRITE(HTOTAL(cpu_transcoder),
6800 (adjusted_mode->crtc_hdisplay - 1) |
6801 ((adjusted_mode->crtc_htotal - 1) << 16));
6802 I915_WRITE(HBLANK(cpu_transcoder),
6803 (adjusted_mode->crtc_hblank_start - 1) |
6804 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6805 I915_WRITE(HSYNC(cpu_transcoder),
6806 (adjusted_mode->crtc_hsync_start - 1) |
6807 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6808
6809 I915_WRITE(VTOTAL(cpu_transcoder),
6810 (adjusted_mode->crtc_vdisplay - 1) |
6811 ((crtc_vtotal - 1) << 16));
6812 I915_WRITE(VBLANK(cpu_transcoder),
6813 (adjusted_mode->crtc_vblank_start - 1) |
6814 ((crtc_vblank_end - 1) << 16));
6815 I915_WRITE(VSYNC(cpu_transcoder),
6816 (adjusted_mode->crtc_vsync_start - 1) |
6817 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6818
6819 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6820 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6821 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6822 * bits. */
6823 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6824 (pipe == PIPE_B || pipe == PIPE_C))
6825 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6826
6827 }
6828
6829 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6830 {
6831 struct drm_device *dev = intel_crtc->base.dev;
6832 struct drm_i915_private *dev_priv = to_i915(dev);
6833 enum pipe pipe = intel_crtc->pipe;
6834
6835 /* pipesrc controls the size that is scaled from, which should
6836 * always be the user's requested size.
6837 */
6838 I915_WRITE(PIPESRC(pipe),
6839 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6840 (intel_crtc->config->pipe_src_h - 1));
6841 }
6842
6843 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6844 struct intel_crtc_state *pipe_config)
6845 {
6846 struct drm_device *dev = crtc->base.dev;
6847 struct drm_i915_private *dev_priv = to_i915(dev);
6848 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6849 uint32_t tmp;
6850
6851 tmp = I915_READ(HTOTAL(cpu_transcoder));
6852 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6853 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6854 tmp = I915_READ(HBLANK(cpu_transcoder));
6855 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6856 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6857 tmp = I915_READ(HSYNC(cpu_transcoder));
6858 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6859 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6860
6861 tmp = I915_READ(VTOTAL(cpu_transcoder));
6862 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6863 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6864 tmp = I915_READ(VBLANK(cpu_transcoder));
6865 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6866 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6867 tmp = I915_READ(VSYNC(cpu_transcoder));
6868 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6869 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6870
6871 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6872 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6873 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6874 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6875 }
6876 }
6877
6878 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6879 struct intel_crtc_state *pipe_config)
6880 {
6881 struct drm_device *dev = crtc->base.dev;
6882 struct drm_i915_private *dev_priv = to_i915(dev);
6883 u32 tmp;
6884
6885 tmp = I915_READ(PIPESRC(crtc->pipe));
6886 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6887 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6888
6889 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6890 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6891 }
6892
6893 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6894 struct intel_crtc_state *pipe_config)
6895 {
6896 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6897 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6898 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6899 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6900
6901 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6902 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6903 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6904 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6905
6906 mode->flags = pipe_config->base.adjusted_mode.flags;
6907 mode->type = DRM_MODE_TYPE_DRIVER;
6908
6909 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6910
6911 mode->hsync = drm_mode_hsync(mode);
6912 mode->vrefresh = drm_mode_vrefresh(mode);
6913 drm_mode_set_name(mode);
6914 }
6915
6916 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6917 {
6918 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6919 uint32_t pipeconf;
6920
6921 pipeconf = 0;
6922
6923 /* we keep both pipes enabled on 830 */
6924 if (IS_I830(dev_priv))
6925 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6926
6927 if (intel_crtc->config->double_wide)
6928 pipeconf |= PIPECONF_DOUBLE_WIDE;
6929
6930 /* only g4x and later have fancy bpc/dither controls */
6931 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6932 IS_CHERRYVIEW(dev_priv)) {
6933 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6934 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6935 pipeconf |= PIPECONF_DITHER_EN |
6936 PIPECONF_DITHER_TYPE_SP;
6937
6938 switch (intel_crtc->config->pipe_bpp) {
6939 case 18:
6940 pipeconf |= PIPECONF_6BPC;
6941 break;
6942 case 24:
6943 pipeconf |= PIPECONF_8BPC;
6944 break;
6945 case 30:
6946 pipeconf |= PIPECONF_10BPC;
6947 break;
6948 default:
6949 /* Case prevented by intel_choose_pipe_bpp_dither. */
6950 BUG();
6951 }
6952 }
6953
6954 if (HAS_PIPE_CXSR(dev_priv)) {
6955 if (intel_crtc->lowfreq_avail) {
6956 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6957 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6958 } else {
6959 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6960 }
6961 }
6962
6963 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6964 if (INTEL_GEN(dev_priv) < 4 ||
6965 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6966 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6967 else
6968 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6969 } else
6970 pipeconf |= PIPECONF_PROGRESSIVE;
6971
6972 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6973 intel_crtc->config->limited_color_range)
6974 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6975
6976 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6977 POSTING_READ(PIPECONF(intel_crtc->pipe));
6978 }
6979
6980 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
6981 struct intel_crtc_state *crtc_state)
6982 {
6983 struct drm_device *dev = crtc->base.dev;
6984 struct drm_i915_private *dev_priv = to_i915(dev);
6985 const struct intel_limit *limit;
6986 int refclk = 48000;
6987
6988 memset(&crtc_state->dpll_hw_state, 0,
6989 sizeof(crtc_state->dpll_hw_state));
6990
6991 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6992 if (intel_panel_use_ssc(dev_priv)) {
6993 refclk = dev_priv->vbt.lvds_ssc_freq;
6994 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6995 }
6996
6997 limit = &intel_limits_i8xx_lvds;
6998 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
6999 limit = &intel_limits_i8xx_dvo;
7000 } else {
7001 limit = &intel_limits_i8xx_dac;
7002 }
7003
7004 if (!crtc_state->clock_set &&
7005 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7006 refclk, NULL, &crtc_state->dpll)) {
7007 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7008 return -EINVAL;
7009 }
7010
7011 i8xx_compute_dpll(crtc, crtc_state, NULL);
7012
7013 return 0;
7014 }
7015
7016 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7017 struct intel_crtc_state *crtc_state)
7018 {
7019 struct drm_device *dev = crtc->base.dev;
7020 struct drm_i915_private *dev_priv = to_i915(dev);
7021 const struct intel_limit *limit;
7022 int refclk = 96000;
7023
7024 memset(&crtc_state->dpll_hw_state, 0,
7025 sizeof(crtc_state->dpll_hw_state));
7026
7027 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7028 if (intel_panel_use_ssc(dev_priv)) {
7029 refclk = dev_priv->vbt.lvds_ssc_freq;
7030 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7031 }
7032
7033 if (intel_is_dual_link_lvds(dev))
7034 limit = &intel_limits_g4x_dual_channel_lvds;
7035 else
7036 limit = &intel_limits_g4x_single_channel_lvds;
7037 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7038 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7039 limit = &intel_limits_g4x_hdmi;
7040 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7041 limit = &intel_limits_g4x_sdvo;
7042 } else {
7043 /* The option is for other outputs */
7044 limit = &intel_limits_i9xx_sdvo;
7045 }
7046
7047 if (!crtc_state->clock_set &&
7048 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7049 refclk, NULL, &crtc_state->dpll)) {
7050 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7051 return -EINVAL;
7052 }
7053
7054 i9xx_compute_dpll(crtc, crtc_state, NULL);
7055
7056 return 0;
7057 }
7058
7059 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7060 struct intel_crtc_state *crtc_state)
7061 {
7062 struct drm_device *dev = crtc->base.dev;
7063 struct drm_i915_private *dev_priv = to_i915(dev);
7064 const struct intel_limit *limit;
7065 int refclk = 96000;
7066
7067 memset(&crtc_state->dpll_hw_state, 0,
7068 sizeof(crtc_state->dpll_hw_state));
7069
7070 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7071 if (intel_panel_use_ssc(dev_priv)) {
7072 refclk = dev_priv->vbt.lvds_ssc_freq;
7073 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7074 }
7075
7076 limit = &intel_limits_pineview_lvds;
7077 } else {
7078 limit = &intel_limits_pineview_sdvo;
7079 }
7080
7081 if (!crtc_state->clock_set &&
7082 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7083 refclk, NULL, &crtc_state->dpll)) {
7084 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7085 return -EINVAL;
7086 }
7087
7088 i9xx_compute_dpll(crtc, crtc_state, NULL);
7089
7090 return 0;
7091 }
7092
7093 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7094 struct intel_crtc_state *crtc_state)
7095 {
7096 struct drm_device *dev = crtc->base.dev;
7097 struct drm_i915_private *dev_priv = to_i915(dev);
7098 const struct intel_limit *limit;
7099 int refclk = 96000;
7100
7101 memset(&crtc_state->dpll_hw_state, 0,
7102 sizeof(crtc_state->dpll_hw_state));
7103
7104 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7105 if (intel_panel_use_ssc(dev_priv)) {
7106 refclk = dev_priv->vbt.lvds_ssc_freq;
7107 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7108 }
7109
7110 limit = &intel_limits_i9xx_lvds;
7111 } else {
7112 limit = &intel_limits_i9xx_sdvo;
7113 }
7114
7115 if (!crtc_state->clock_set &&
7116 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7117 refclk, NULL, &crtc_state->dpll)) {
7118 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7119 return -EINVAL;
7120 }
7121
7122 i9xx_compute_dpll(crtc, crtc_state, NULL);
7123
7124 return 0;
7125 }
7126
7127 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7128 struct intel_crtc_state *crtc_state)
7129 {
7130 int refclk = 100000;
7131 const struct intel_limit *limit = &intel_limits_chv;
7132
7133 memset(&crtc_state->dpll_hw_state, 0,
7134 sizeof(crtc_state->dpll_hw_state));
7135
7136 if (!crtc_state->clock_set &&
7137 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7138 refclk, NULL, &crtc_state->dpll)) {
7139 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7140 return -EINVAL;
7141 }
7142
7143 chv_compute_dpll(crtc, crtc_state);
7144
7145 return 0;
7146 }
7147
7148 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7149 struct intel_crtc_state *crtc_state)
7150 {
7151 int refclk = 100000;
7152 const struct intel_limit *limit = &intel_limits_vlv;
7153
7154 memset(&crtc_state->dpll_hw_state, 0,
7155 sizeof(crtc_state->dpll_hw_state));
7156
7157 if (!crtc_state->clock_set &&
7158 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7159 refclk, NULL, &crtc_state->dpll)) {
7160 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7161 return -EINVAL;
7162 }
7163
7164 vlv_compute_dpll(crtc, crtc_state);
7165
7166 return 0;
7167 }
7168
7169 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7170 struct intel_crtc_state *pipe_config)
7171 {
7172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7173 uint32_t tmp;
7174
7175 if (INTEL_GEN(dev_priv) <= 3 &&
7176 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7177 return;
7178
7179 tmp = I915_READ(PFIT_CONTROL);
7180 if (!(tmp & PFIT_ENABLE))
7181 return;
7182
7183 /* Check whether the pfit is attached to our pipe. */
7184 if (INTEL_GEN(dev_priv) < 4) {
7185 if (crtc->pipe != PIPE_B)
7186 return;
7187 } else {
7188 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7189 return;
7190 }
7191
7192 pipe_config->gmch_pfit.control = tmp;
7193 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7194 }
7195
7196 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7197 struct intel_crtc_state *pipe_config)
7198 {
7199 struct drm_device *dev = crtc->base.dev;
7200 struct drm_i915_private *dev_priv = to_i915(dev);
7201 int pipe = pipe_config->cpu_transcoder;
7202 struct dpll clock;
7203 u32 mdiv;
7204 int refclk = 100000;
7205
7206 /* In case of DSI, DPLL will not be used */
7207 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7208 return;
7209
7210 mutex_lock(&dev_priv->sb_lock);
7211 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7212 mutex_unlock(&dev_priv->sb_lock);
7213
7214 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7215 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7216 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7217 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7218 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7219
7220 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7221 }
7222
7223 static void
7224 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7225 struct intel_initial_plane_config *plane_config)
7226 {
7227 struct drm_device *dev = crtc->base.dev;
7228 struct drm_i915_private *dev_priv = to_i915(dev);
7229 u32 val, base, offset;
7230 int pipe = crtc->pipe, plane = crtc->plane;
7231 int fourcc, pixel_format;
7232 unsigned int aligned_height;
7233 struct drm_framebuffer *fb;
7234 struct intel_framebuffer *intel_fb;
7235
7236 val = I915_READ(DSPCNTR(plane));
7237 if (!(val & DISPLAY_PLANE_ENABLE))
7238 return;
7239
7240 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7241 if (!intel_fb) {
7242 DRM_DEBUG_KMS("failed to alloc fb\n");
7243 return;
7244 }
7245
7246 fb = &intel_fb->base;
7247
7248 fb->dev = dev;
7249
7250 if (INTEL_GEN(dev_priv) >= 4) {
7251 if (val & DISPPLANE_TILED) {
7252 plane_config->tiling = I915_TILING_X;
7253 fb->modifier = I915_FORMAT_MOD_X_TILED;
7254 }
7255 }
7256
7257 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7258 fourcc = i9xx_format_to_fourcc(pixel_format);
7259 fb->format = drm_format_info(fourcc);
7260
7261 if (INTEL_GEN(dev_priv) >= 4) {
7262 if (plane_config->tiling)
7263 offset = I915_READ(DSPTILEOFF(plane));
7264 else
7265 offset = I915_READ(DSPLINOFF(plane));
7266 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7267 } else {
7268 base = I915_READ(DSPADDR(plane));
7269 }
7270 plane_config->base = base;
7271
7272 val = I915_READ(PIPESRC(pipe));
7273 fb->width = ((val >> 16) & 0xfff) + 1;
7274 fb->height = ((val >> 0) & 0xfff) + 1;
7275
7276 val = I915_READ(DSPSTRIDE(pipe));
7277 fb->pitches[0] = val & 0xffffffc0;
7278
7279 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7280
7281 plane_config->size = fb->pitches[0] * aligned_height;
7282
7283 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7284 pipe_name(pipe), plane, fb->width, fb->height,
7285 fb->format->cpp[0] * 8, base, fb->pitches[0],
7286 plane_config->size);
7287
7288 plane_config->fb = intel_fb;
7289 }
7290
7291 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7292 struct intel_crtc_state *pipe_config)
7293 {
7294 struct drm_device *dev = crtc->base.dev;
7295 struct drm_i915_private *dev_priv = to_i915(dev);
7296 int pipe = pipe_config->cpu_transcoder;
7297 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7298 struct dpll clock;
7299 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7300 int refclk = 100000;
7301
7302 /* In case of DSI, DPLL will not be used */
7303 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7304 return;
7305
7306 mutex_lock(&dev_priv->sb_lock);
7307 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7308 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7309 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7310 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7311 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7312 mutex_unlock(&dev_priv->sb_lock);
7313
7314 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7315 clock.m2 = (pll_dw0 & 0xff) << 22;
7316 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7317 clock.m2 |= pll_dw2 & 0x3fffff;
7318 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7319 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7320 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7321
7322 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7323 }
7324
7325 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7326 struct intel_crtc_state *pipe_config)
7327 {
7328 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7329 enum intel_display_power_domain power_domain;
7330 uint32_t tmp;
7331 bool ret;
7332
7333 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7334 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7335 return false;
7336
7337 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7338 pipe_config->shared_dpll = NULL;
7339
7340 ret = false;
7341
7342 tmp = I915_READ(PIPECONF(crtc->pipe));
7343 if (!(tmp & PIPECONF_ENABLE))
7344 goto out;
7345
7346 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7347 IS_CHERRYVIEW(dev_priv)) {
7348 switch (tmp & PIPECONF_BPC_MASK) {
7349 case PIPECONF_6BPC:
7350 pipe_config->pipe_bpp = 18;
7351 break;
7352 case PIPECONF_8BPC:
7353 pipe_config->pipe_bpp = 24;
7354 break;
7355 case PIPECONF_10BPC:
7356 pipe_config->pipe_bpp = 30;
7357 break;
7358 default:
7359 break;
7360 }
7361 }
7362
7363 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7364 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7365 pipe_config->limited_color_range = true;
7366
7367 if (INTEL_GEN(dev_priv) < 4)
7368 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7369
7370 intel_get_pipe_timings(crtc, pipe_config);
7371 intel_get_pipe_src_size(crtc, pipe_config);
7372
7373 i9xx_get_pfit_config(crtc, pipe_config);
7374
7375 if (INTEL_GEN(dev_priv) >= 4) {
7376 /* No way to read it out on pipes B and C */
7377 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7378 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7379 else
7380 tmp = I915_READ(DPLL_MD(crtc->pipe));
7381 pipe_config->pixel_multiplier =
7382 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7383 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7384 pipe_config->dpll_hw_state.dpll_md = tmp;
7385 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7386 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7387 tmp = I915_READ(DPLL(crtc->pipe));
7388 pipe_config->pixel_multiplier =
7389 ((tmp & SDVO_MULTIPLIER_MASK)
7390 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7391 } else {
7392 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7393 * port and will be fixed up in the encoder->get_config
7394 * function. */
7395 pipe_config->pixel_multiplier = 1;
7396 }
7397 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7398 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7399 /*
7400 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7401 * on 830. Filter it out here so that we don't
7402 * report errors due to that.
7403 */
7404 if (IS_I830(dev_priv))
7405 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7406
7407 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7408 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7409 } else {
7410 /* Mask out read-only status bits. */
7411 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7412 DPLL_PORTC_READY_MASK |
7413 DPLL_PORTB_READY_MASK);
7414 }
7415
7416 if (IS_CHERRYVIEW(dev_priv))
7417 chv_crtc_clock_get(crtc, pipe_config);
7418 else if (IS_VALLEYVIEW(dev_priv))
7419 vlv_crtc_clock_get(crtc, pipe_config);
7420 else
7421 i9xx_crtc_clock_get(crtc, pipe_config);
7422
7423 /*
7424 * Normally the dotclock is filled in by the encoder .get_config()
7425 * but in case the pipe is enabled w/o any ports we need a sane
7426 * default.
7427 */
7428 pipe_config->base.adjusted_mode.crtc_clock =
7429 pipe_config->port_clock / pipe_config->pixel_multiplier;
7430
7431 ret = true;
7432
7433 out:
7434 intel_display_power_put(dev_priv, power_domain);
7435
7436 return ret;
7437 }
7438
7439 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7440 {
7441 struct intel_encoder *encoder;
7442 int i;
7443 u32 val, final;
7444 bool has_lvds = false;
7445 bool has_cpu_edp = false;
7446 bool has_panel = false;
7447 bool has_ck505 = false;
7448 bool can_ssc = false;
7449 bool using_ssc_source = false;
7450
7451 /* We need to take the global config into account */
7452 for_each_intel_encoder(&dev_priv->drm, encoder) {
7453 switch (encoder->type) {
7454 case INTEL_OUTPUT_LVDS:
7455 has_panel = true;
7456 has_lvds = true;
7457 break;
7458 case INTEL_OUTPUT_EDP:
7459 has_panel = true;
7460 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7461 has_cpu_edp = true;
7462 break;
7463 default:
7464 break;
7465 }
7466 }
7467
7468 if (HAS_PCH_IBX(dev_priv)) {
7469 has_ck505 = dev_priv->vbt.display_clock_mode;
7470 can_ssc = has_ck505;
7471 } else {
7472 has_ck505 = false;
7473 can_ssc = true;
7474 }
7475
7476 /* Check if any DPLLs are using the SSC source */
7477 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7478 u32 temp = I915_READ(PCH_DPLL(i));
7479
7480 if (!(temp & DPLL_VCO_ENABLE))
7481 continue;
7482
7483 if ((temp & PLL_REF_INPUT_MASK) ==
7484 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7485 using_ssc_source = true;
7486 break;
7487 }
7488 }
7489
7490 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7491 has_panel, has_lvds, has_ck505, using_ssc_source);
7492
7493 /* Ironlake: try to setup display ref clock before DPLL
7494 * enabling. This is only under driver's control after
7495 * PCH B stepping, previous chipset stepping should be
7496 * ignoring this setting.
7497 */
7498 val = I915_READ(PCH_DREF_CONTROL);
7499
7500 /* As we must carefully and slowly disable/enable each source in turn,
7501 * compute the final state we want first and check if we need to
7502 * make any changes at all.
7503 */
7504 final = val;
7505 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7506 if (has_ck505)
7507 final |= DREF_NONSPREAD_CK505_ENABLE;
7508 else
7509 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7510
7511 final &= ~DREF_SSC_SOURCE_MASK;
7512 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7513 final &= ~DREF_SSC1_ENABLE;
7514
7515 if (has_panel) {
7516 final |= DREF_SSC_SOURCE_ENABLE;
7517
7518 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7519 final |= DREF_SSC1_ENABLE;
7520
7521 if (has_cpu_edp) {
7522 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7523 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7524 else
7525 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7526 } else
7527 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7528 } else if (using_ssc_source) {
7529 final |= DREF_SSC_SOURCE_ENABLE;
7530 final |= DREF_SSC1_ENABLE;
7531 }
7532
7533 if (final == val)
7534 return;
7535
7536 /* Always enable nonspread source */
7537 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7538
7539 if (has_ck505)
7540 val |= DREF_NONSPREAD_CK505_ENABLE;
7541 else
7542 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7543
7544 if (has_panel) {
7545 val &= ~DREF_SSC_SOURCE_MASK;
7546 val |= DREF_SSC_SOURCE_ENABLE;
7547
7548 /* SSC must be turned on before enabling the CPU output */
7549 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7550 DRM_DEBUG_KMS("Using SSC on panel\n");
7551 val |= DREF_SSC1_ENABLE;
7552 } else
7553 val &= ~DREF_SSC1_ENABLE;
7554
7555 /* Get SSC going before enabling the outputs */
7556 I915_WRITE(PCH_DREF_CONTROL, val);
7557 POSTING_READ(PCH_DREF_CONTROL);
7558 udelay(200);
7559
7560 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7561
7562 /* Enable CPU source on CPU attached eDP */
7563 if (has_cpu_edp) {
7564 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7565 DRM_DEBUG_KMS("Using SSC on eDP\n");
7566 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7567 } else
7568 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7569 } else
7570 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7571
7572 I915_WRITE(PCH_DREF_CONTROL, val);
7573 POSTING_READ(PCH_DREF_CONTROL);
7574 udelay(200);
7575 } else {
7576 DRM_DEBUG_KMS("Disabling CPU source output\n");
7577
7578 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7579
7580 /* Turn off CPU output */
7581 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7582
7583 I915_WRITE(PCH_DREF_CONTROL, val);
7584 POSTING_READ(PCH_DREF_CONTROL);
7585 udelay(200);
7586
7587 if (!using_ssc_source) {
7588 DRM_DEBUG_KMS("Disabling SSC source\n");
7589
7590 /* Turn off the SSC source */
7591 val &= ~DREF_SSC_SOURCE_MASK;
7592 val |= DREF_SSC_SOURCE_DISABLE;
7593
7594 /* Turn off SSC1 */
7595 val &= ~DREF_SSC1_ENABLE;
7596
7597 I915_WRITE(PCH_DREF_CONTROL, val);
7598 POSTING_READ(PCH_DREF_CONTROL);
7599 udelay(200);
7600 }
7601 }
7602
7603 BUG_ON(val != final);
7604 }
7605
7606 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7607 {
7608 uint32_t tmp;
7609
7610 tmp = I915_READ(SOUTH_CHICKEN2);
7611 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7612 I915_WRITE(SOUTH_CHICKEN2, tmp);
7613
7614 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7615 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7616 DRM_ERROR("FDI mPHY reset assert timeout\n");
7617
7618 tmp = I915_READ(SOUTH_CHICKEN2);
7619 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7620 I915_WRITE(SOUTH_CHICKEN2, tmp);
7621
7622 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7623 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7624 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7625 }
7626
7627 /* WaMPhyProgramming:hsw */
7628 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7629 {
7630 uint32_t tmp;
7631
7632 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7633 tmp &= ~(0xFF << 24);
7634 tmp |= (0x12 << 24);
7635 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7636
7637 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7638 tmp |= (1 << 11);
7639 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7640
7641 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7642 tmp |= (1 << 11);
7643 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7644
7645 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7646 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7647 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7648
7649 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7650 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7651 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7652
7653 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7654 tmp &= ~(7 << 13);
7655 tmp |= (5 << 13);
7656 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7657
7658 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7659 tmp &= ~(7 << 13);
7660 tmp |= (5 << 13);
7661 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7662
7663 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7664 tmp &= ~0xFF;
7665 tmp |= 0x1C;
7666 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7667
7668 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7669 tmp &= ~0xFF;
7670 tmp |= 0x1C;
7671 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7672
7673 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7674 tmp &= ~(0xFF << 16);
7675 tmp |= (0x1C << 16);
7676 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7677
7678 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7679 tmp &= ~(0xFF << 16);
7680 tmp |= (0x1C << 16);
7681 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7682
7683 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7684 tmp |= (1 << 27);
7685 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7686
7687 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7688 tmp |= (1 << 27);
7689 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7690
7691 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7692 tmp &= ~(0xF << 28);
7693 tmp |= (4 << 28);
7694 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7695
7696 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7697 tmp &= ~(0xF << 28);
7698 tmp |= (4 << 28);
7699 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7700 }
7701
7702 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7703 * Programming" based on the parameters passed:
7704 * - Sequence to enable CLKOUT_DP
7705 * - Sequence to enable CLKOUT_DP without spread
7706 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7707 */
7708 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7709 bool with_spread, bool with_fdi)
7710 {
7711 uint32_t reg, tmp;
7712
7713 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7714 with_spread = true;
7715 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7716 with_fdi, "LP PCH doesn't have FDI\n"))
7717 with_fdi = false;
7718
7719 mutex_lock(&dev_priv->sb_lock);
7720
7721 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7722 tmp &= ~SBI_SSCCTL_DISABLE;
7723 tmp |= SBI_SSCCTL_PATHALT;
7724 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7725
7726 udelay(24);
7727
7728 if (with_spread) {
7729 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7730 tmp &= ~SBI_SSCCTL_PATHALT;
7731 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7732
7733 if (with_fdi) {
7734 lpt_reset_fdi_mphy(dev_priv);
7735 lpt_program_fdi_mphy(dev_priv);
7736 }
7737 }
7738
7739 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7740 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7741 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7742 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7743
7744 mutex_unlock(&dev_priv->sb_lock);
7745 }
7746
7747 /* Sequence to disable CLKOUT_DP */
7748 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7749 {
7750 uint32_t reg, tmp;
7751
7752 mutex_lock(&dev_priv->sb_lock);
7753
7754 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7755 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7756 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7757 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7758
7759 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7760 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7761 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7762 tmp |= SBI_SSCCTL_PATHALT;
7763 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7764 udelay(32);
7765 }
7766 tmp |= SBI_SSCCTL_DISABLE;
7767 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7768 }
7769
7770 mutex_unlock(&dev_priv->sb_lock);
7771 }
7772
7773 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7774
7775 static const uint16_t sscdivintphase[] = {
7776 [BEND_IDX( 50)] = 0x3B23,
7777 [BEND_IDX( 45)] = 0x3B23,
7778 [BEND_IDX( 40)] = 0x3C23,
7779 [BEND_IDX( 35)] = 0x3C23,
7780 [BEND_IDX( 30)] = 0x3D23,
7781 [BEND_IDX( 25)] = 0x3D23,
7782 [BEND_IDX( 20)] = 0x3E23,
7783 [BEND_IDX( 15)] = 0x3E23,
7784 [BEND_IDX( 10)] = 0x3F23,
7785 [BEND_IDX( 5)] = 0x3F23,
7786 [BEND_IDX( 0)] = 0x0025,
7787 [BEND_IDX( -5)] = 0x0025,
7788 [BEND_IDX(-10)] = 0x0125,
7789 [BEND_IDX(-15)] = 0x0125,
7790 [BEND_IDX(-20)] = 0x0225,
7791 [BEND_IDX(-25)] = 0x0225,
7792 [BEND_IDX(-30)] = 0x0325,
7793 [BEND_IDX(-35)] = 0x0325,
7794 [BEND_IDX(-40)] = 0x0425,
7795 [BEND_IDX(-45)] = 0x0425,
7796 [BEND_IDX(-50)] = 0x0525,
7797 };
7798
7799 /*
7800 * Bend CLKOUT_DP
7801 * steps -50 to 50 inclusive, in steps of 5
7802 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7803 * change in clock period = -(steps / 10) * 5.787 ps
7804 */
7805 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7806 {
7807 uint32_t tmp;
7808 int idx = BEND_IDX(steps);
7809
7810 if (WARN_ON(steps % 5 != 0))
7811 return;
7812
7813 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7814 return;
7815
7816 mutex_lock(&dev_priv->sb_lock);
7817
7818 if (steps % 10 != 0)
7819 tmp = 0xAAAAAAAB;
7820 else
7821 tmp = 0x00000000;
7822 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7823
7824 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7825 tmp &= 0xffff0000;
7826 tmp |= sscdivintphase[idx];
7827 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7828
7829 mutex_unlock(&dev_priv->sb_lock);
7830 }
7831
7832 #undef BEND_IDX
7833
7834 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7835 {
7836 struct intel_encoder *encoder;
7837 bool has_vga = false;
7838
7839 for_each_intel_encoder(&dev_priv->drm, encoder) {
7840 switch (encoder->type) {
7841 case INTEL_OUTPUT_ANALOG:
7842 has_vga = true;
7843 break;
7844 default:
7845 break;
7846 }
7847 }
7848
7849 if (has_vga) {
7850 lpt_bend_clkout_dp(dev_priv, 0);
7851 lpt_enable_clkout_dp(dev_priv, true, true);
7852 } else {
7853 lpt_disable_clkout_dp(dev_priv);
7854 }
7855 }
7856
7857 /*
7858 * Initialize reference clocks when the driver loads
7859 */
7860 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7861 {
7862 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7863 ironlake_init_pch_refclk(dev_priv);
7864 else if (HAS_PCH_LPT(dev_priv))
7865 lpt_init_pch_refclk(dev_priv);
7866 }
7867
7868 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7869 {
7870 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7872 int pipe = intel_crtc->pipe;
7873 uint32_t val;
7874
7875 val = 0;
7876
7877 switch (intel_crtc->config->pipe_bpp) {
7878 case 18:
7879 val |= PIPECONF_6BPC;
7880 break;
7881 case 24:
7882 val |= PIPECONF_8BPC;
7883 break;
7884 case 30:
7885 val |= PIPECONF_10BPC;
7886 break;
7887 case 36:
7888 val |= PIPECONF_12BPC;
7889 break;
7890 default:
7891 /* Case prevented by intel_choose_pipe_bpp_dither. */
7892 BUG();
7893 }
7894
7895 if (intel_crtc->config->dither)
7896 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7897
7898 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7899 val |= PIPECONF_INTERLACED_ILK;
7900 else
7901 val |= PIPECONF_PROGRESSIVE;
7902
7903 if (intel_crtc->config->limited_color_range)
7904 val |= PIPECONF_COLOR_RANGE_SELECT;
7905
7906 I915_WRITE(PIPECONF(pipe), val);
7907 POSTING_READ(PIPECONF(pipe));
7908 }
7909
7910 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7911 {
7912 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7914 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7915 u32 val = 0;
7916
7917 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
7918 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7919
7920 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7921 val |= PIPECONF_INTERLACED_ILK;
7922 else
7923 val |= PIPECONF_PROGRESSIVE;
7924
7925 I915_WRITE(PIPECONF(cpu_transcoder), val);
7926 POSTING_READ(PIPECONF(cpu_transcoder));
7927 }
7928
7929 static void haswell_set_pipemisc(struct drm_crtc *crtc)
7930 {
7931 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7933
7934 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
7935 u32 val = 0;
7936
7937 switch (intel_crtc->config->pipe_bpp) {
7938 case 18:
7939 val |= PIPEMISC_DITHER_6_BPC;
7940 break;
7941 case 24:
7942 val |= PIPEMISC_DITHER_8_BPC;
7943 break;
7944 case 30:
7945 val |= PIPEMISC_DITHER_10_BPC;
7946 break;
7947 case 36:
7948 val |= PIPEMISC_DITHER_12_BPC;
7949 break;
7950 default:
7951 /* Case prevented by pipe_config_set_bpp. */
7952 BUG();
7953 }
7954
7955 if (intel_crtc->config->dither)
7956 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7957
7958 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
7959 }
7960 }
7961
7962 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7963 {
7964 /*
7965 * Account for spread spectrum to avoid
7966 * oversubscribing the link. Max center spread
7967 * is 2.5%; use 5% for safety's sake.
7968 */
7969 u32 bps = target_clock * bpp * 21 / 20;
7970 return DIV_ROUND_UP(bps, link_bw * 8);
7971 }
7972
7973 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7974 {
7975 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7976 }
7977
7978 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7979 struct intel_crtc_state *crtc_state,
7980 struct dpll *reduced_clock)
7981 {
7982 struct drm_crtc *crtc = &intel_crtc->base;
7983 struct drm_device *dev = crtc->dev;
7984 struct drm_i915_private *dev_priv = to_i915(dev);
7985 u32 dpll, fp, fp2;
7986 int factor;
7987
7988 /* Enable autotuning of the PLL clock (if permissible) */
7989 factor = 21;
7990 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7991 if ((intel_panel_use_ssc(dev_priv) &&
7992 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7993 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
7994 factor = 25;
7995 } else if (crtc_state->sdvo_tv_clock)
7996 factor = 20;
7997
7998 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7999
8000 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8001 fp |= FP_CB_TUNE;
8002
8003 if (reduced_clock) {
8004 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8005
8006 if (reduced_clock->m < factor * reduced_clock->n)
8007 fp2 |= FP_CB_TUNE;
8008 } else {
8009 fp2 = fp;
8010 }
8011
8012 dpll = 0;
8013
8014 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8015 dpll |= DPLLB_MODE_LVDS;
8016 else
8017 dpll |= DPLLB_MODE_DAC_SERIAL;
8018
8019 dpll |= (crtc_state->pixel_multiplier - 1)
8020 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8021
8022 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8023 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8024 dpll |= DPLL_SDVO_HIGH_SPEED;
8025
8026 if (intel_crtc_has_dp_encoder(crtc_state))
8027 dpll |= DPLL_SDVO_HIGH_SPEED;
8028
8029 /*
8030 * The high speed IO clock is only really required for
8031 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8032 * possible to share the DPLL between CRT and HDMI. Enabling
8033 * the clock needlessly does no real harm, except use up a
8034 * bit of power potentially.
8035 *
8036 * We'll limit this to IVB with 3 pipes, since it has only two
8037 * DPLLs and so DPLL sharing is the only way to get three pipes
8038 * driving PCH ports at the same time. On SNB we could do this,
8039 * and potentially avoid enabling the second DPLL, but it's not
8040 * clear if it''s a win or loss power wise. No point in doing
8041 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8042 */
8043 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8044 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8045 dpll |= DPLL_SDVO_HIGH_SPEED;
8046
8047 /* compute bitmask from p1 value */
8048 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8049 /* also FPA1 */
8050 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8051
8052 switch (crtc_state->dpll.p2) {
8053 case 5:
8054 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8055 break;
8056 case 7:
8057 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8058 break;
8059 case 10:
8060 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8061 break;
8062 case 14:
8063 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8064 break;
8065 }
8066
8067 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8068 intel_panel_use_ssc(dev_priv))
8069 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8070 else
8071 dpll |= PLL_REF_INPUT_DREFCLK;
8072
8073 dpll |= DPLL_VCO_ENABLE;
8074
8075 crtc_state->dpll_hw_state.dpll = dpll;
8076 crtc_state->dpll_hw_state.fp0 = fp;
8077 crtc_state->dpll_hw_state.fp1 = fp2;
8078 }
8079
8080 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8081 struct intel_crtc_state *crtc_state)
8082 {
8083 struct drm_device *dev = crtc->base.dev;
8084 struct drm_i915_private *dev_priv = to_i915(dev);
8085 const struct intel_limit *limit;
8086 int refclk = 120000;
8087
8088 memset(&crtc_state->dpll_hw_state, 0,
8089 sizeof(crtc_state->dpll_hw_state));
8090
8091 crtc->lowfreq_avail = false;
8092
8093 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8094 if (!crtc_state->has_pch_encoder)
8095 return 0;
8096
8097 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8098 if (intel_panel_use_ssc(dev_priv)) {
8099 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8100 dev_priv->vbt.lvds_ssc_freq);
8101 refclk = dev_priv->vbt.lvds_ssc_freq;
8102 }
8103
8104 if (intel_is_dual_link_lvds(dev)) {
8105 if (refclk == 100000)
8106 limit = &intel_limits_ironlake_dual_lvds_100m;
8107 else
8108 limit = &intel_limits_ironlake_dual_lvds;
8109 } else {
8110 if (refclk == 100000)
8111 limit = &intel_limits_ironlake_single_lvds_100m;
8112 else
8113 limit = &intel_limits_ironlake_single_lvds;
8114 }
8115 } else {
8116 limit = &intel_limits_ironlake_dac;
8117 }
8118
8119 if (!crtc_state->clock_set &&
8120 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8121 refclk, NULL, &crtc_state->dpll)) {
8122 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8123 return -EINVAL;
8124 }
8125
8126 ironlake_compute_dpll(crtc, crtc_state, NULL);
8127
8128 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8129 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8130 pipe_name(crtc->pipe));
8131 return -EINVAL;
8132 }
8133
8134 return 0;
8135 }
8136
8137 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8138 struct intel_link_m_n *m_n)
8139 {
8140 struct drm_device *dev = crtc->base.dev;
8141 struct drm_i915_private *dev_priv = to_i915(dev);
8142 enum pipe pipe = crtc->pipe;
8143
8144 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8145 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8146 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8147 & ~TU_SIZE_MASK;
8148 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8149 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8150 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8151 }
8152
8153 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8154 enum transcoder transcoder,
8155 struct intel_link_m_n *m_n,
8156 struct intel_link_m_n *m2_n2)
8157 {
8158 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8159 enum pipe pipe = crtc->pipe;
8160
8161 if (INTEL_GEN(dev_priv) >= 5) {
8162 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8163 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8164 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8165 & ~TU_SIZE_MASK;
8166 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8167 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8168 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8169 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8170 * gen < 8) and if DRRS is supported (to make sure the
8171 * registers are not unnecessarily read).
8172 */
8173 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8174 crtc->config->has_drrs) {
8175 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8176 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8177 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8178 & ~TU_SIZE_MASK;
8179 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8180 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8181 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8182 }
8183 } else {
8184 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8185 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8186 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8187 & ~TU_SIZE_MASK;
8188 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8189 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8190 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8191 }
8192 }
8193
8194 void intel_dp_get_m_n(struct intel_crtc *crtc,
8195 struct intel_crtc_state *pipe_config)
8196 {
8197 if (pipe_config->has_pch_encoder)
8198 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8199 else
8200 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8201 &pipe_config->dp_m_n,
8202 &pipe_config->dp_m2_n2);
8203 }
8204
8205 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8206 struct intel_crtc_state *pipe_config)
8207 {
8208 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8209 &pipe_config->fdi_m_n, NULL);
8210 }
8211
8212 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8213 struct intel_crtc_state *pipe_config)
8214 {
8215 struct drm_device *dev = crtc->base.dev;
8216 struct drm_i915_private *dev_priv = to_i915(dev);
8217 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8218 uint32_t ps_ctrl = 0;
8219 int id = -1;
8220 int i;
8221
8222 /* find scaler attached to this pipe */
8223 for (i = 0; i < crtc->num_scalers; i++) {
8224 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8225 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8226 id = i;
8227 pipe_config->pch_pfit.enabled = true;
8228 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8229 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8230 break;
8231 }
8232 }
8233
8234 scaler_state->scaler_id = id;
8235 if (id >= 0) {
8236 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8237 } else {
8238 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8239 }
8240 }
8241
8242 static void
8243 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8244 struct intel_initial_plane_config *plane_config)
8245 {
8246 struct drm_device *dev = crtc->base.dev;
8247 struct drm_i915_private *dev_priv = to_i915(dev);
8248 u32 val, base, offset, stride_mult, tiling;
8249 int pipe = crtc->pipe;
8250 int fourcc, pixel_format;
8251 unsigned int aligned_height;
8252 struct drm_framebuffer *fb;
8253 struct intel_framebuffer *intel_fb;
8254
8255 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8256 if (!intel_fb) {
8257 DRM_DEBUG_KMS("failed to alloc fb\n");
8258 return;
8259 }
8260
8261 fb = &intel_fb->base;
8262
8263 fb->dev = dev;
8264
8265 val = I915_READ(PLANE_CTL(pipe, 0));
8266 if (!(val & PLANE_CTL_ENABLE))
8267 goto error;
8268
8269 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8270 fourcc = skl_format_to_fourcc(pixel_format,
8271 val & PLANE_CTL_ORDER_RGBX,
8272 val & PLANE_CTL_ALPHA_MASK);
8273 fb->format = drm_format_info(fourcc);
8274
8275 tiling = val & PLANE_CTL_TILED_MASK;
8276 switch (tiling) {
8277 case PLANE_CTL_TILED_LINEAR:
8278 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8279 break;
8280 case PLANE_CTL_TILED_X:
8281 plane_config->tiling = I915_TILING_X;
8282 fb->modifier = I915_FORMAT_MOD_X_TILED;
8283 break;
8284 case PLANE_CTL_TILED_Y:
8285 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8286 break;
8287 case PLANE_CTL_TILED_YF:
8288 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8289 break;
8290 default:
8291 MISSING_CASE(tiling);
8292 goto error;
8293 }
8294
8295 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8296 plane_config->base = base;
8297
8298 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8299
8300 val = I915_READ(PLANE_SIZE(pipe, 0));
8301 fb->height = ((val >> 16) & 0xfff) + 1;
8302 fb->width = ((val >> 0) & 0x1fff) + 1;
8303
8304 val = I915_READ(PLANE_STRIDE(pipe, 0));
8305 stride_mult = intel_fb_stride_alignment(fb, 0);
8306 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8307
8308 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8309
8310 plane_config->size = fb->pitches[0] * aligned_height;
8311
8312 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8313 pipe_name(pipe), fb->width, fb->height,
8314 fb->format->cpp[0] * 8, base, fb->pitches[0],
8315 plane_config->size);
8316
8317 plane_config->fb = intel_fb;
8318 return;
8319
8320 error:
8321 kfree(intel_fb);
8322 }
8323
8324 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8325 struct intel_crtc_state *pipe_config)
8326 {
8327 struct drm_device *dev = crtc->base.dev;
8328 struct drm_i915_private *dev_priv = to_i915(dev);
8329 uint32_t tmp;
8330
8331 tmp = I915_READ(PF_CTL(crtc->pipe));
8332
8333 if (tmp & PF_ENABLE) {
8334 pipe_config->pch_pfit.enabled = true;
8335 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8336 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8337
8338 /* We currently do not free assignements of panel fitters on
8339 * ivb/hsw (since we don't use the higher upscaling modes which
8340 * differentiates them) so just WARN about this case for now. */
8341 if (IS_GEN7(dev_priv)) {
8342 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8343 PF_PIPE_SEL_IVB(crtc->pipe));
8344 }
8345 }
8346 }
8347
8348 static void
8349 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8350 struct intel_initial_plane_config *plane_config)
8351 {
8352 struct drm_device *dev = crtc->base.dev;
8353 struct drm_i915_private *dev_priv = to_i915(dev);
8354 u32 val, base, offset;
8355 int pipe = crtc->pipe;
8356 int fourcc, pixel_format;
8357 unsigned int aligned_height;
8358 struct drm_framebuffer *fb;
8359 struct intel_framebuffer *intel_fb;
8360
8361 val = I915_READ(DSPCNTR(pipe));
8362 if (!(val & DISPLAY_PLANE_ENABLE))
8363 return;
8364
8365 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8366 if (!intel_fb) {
8367 DRM_DEBUG_KMS("failed to alloc fb\n");
8368 return;
8369 }
8370
8371 fb = &intel_fb->base;
8372
8373 fb->dev = dev;
8374
8375 if (INTEL_GEN(dev_priv) >= 4) {
8376 if (val & DISPPLANE_TILED) {
8377 plane_config->tiling = I915_TILING_X;
8378 fb->modifier = I915_FORMAT_MOD_X_TILED;
8379 }
8380 }
8381
8382 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8383 fourcc = i9xx_format_to_fourcc(pixel_format);
8384 fb->format = drm_format_info(fourcc);
8385
8386 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8387 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8388 offset = I915_READ(DSPOFFSET(pipe));
8389 } else {
8390 if (plane_config->tiling)
8391 offset = I915_READ(DSPTILEOFF(pipe));
8392 else
8393 offset = I915_READ(DSPLINOFF(pipe));
8394 }
8395 plane_config->base = base;
8396
8397 val = I915_READ(PIPESRC(pipe));
8398 fb->width = ((val >> 16) & 0xfff) + 1;
8399 fb->height = ((val >> 0) & 0xfff) + 1;
8400
8401 val = I915_READ(DSPSTRIDE(pipe));
8402 fb->pitches[0] = val & 0xffffffc0;
8403
8404 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8405
8406 plane_config->size = fb->pitches[0] * aligned_height;
8407
8408 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8409 pipe_name(pipe), fb->width, fb->height,
8410 fb->format->cpp[0] * 8, base, fb->pitches[0],
8411 plane_config->size);
8412
8413 plane_config->fb = intel_fb;
8414 }
8415
8416 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8417 struct intel_crtc_state *pipe_config)
8418 {
8419 struct drm_device *dev = crtc->base.dev;
8420 struct drm_i915_private *dev_priv = to_i915(dev);
8421 enum intel_display_power_domain power_domain;
8422 uint32_t tmp;
8423 bool ret;
8424
8425 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8426 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8427 return false;
8428
8429 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8430 pipe_config->shared_dpll = NULL;
8431
8432 ret = false;
8433 tmp = I915_READ(PIPECONF(crtc->pipe));
8434 if (!(tmp & PIPECONF_ENABLE))
8435 goto out;
8436
8437 switch (tmp & PIPECONF_BPC_MASK) {
8438 case PIPECONF_6BPC:
8439 pipe_config->pipe_bpp = 18;
8440 break;
8441 case PIPECONF_8BPC:
8442 pipe_config->pipe_bpp = 24;
8443 break;
8444 case PIPECONF_10BPC:
8445 pipe_config->pipe_bpp = 30;
8446 break;
8447 case PIPECONF_12BPC:
8448 pipe_config->pipe_bpp = 36;
8449 break;
8450 default:
8451 break;
8452 }
8453
8454 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8455 pipe_config->limited_color_range = true;
8456
8457 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8458 struct intel_shared_dpll *pll;
8459 enum intel_dpll_id pll_id;
8460
8461 pipe_config->has_pch_encoder = true;
8462
8463 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8464 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8465 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8466
8467 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8468
8469 if (HAS_PCH_IBX(dev_priv)) {
8470 /*
8471 * The pipe->pch transcoder and pch transcoder->pll
8472 * mapping is fixed.
8473 */
8474 pll_id = (enum intel_dpll_id) crtc->pipe;
8475 } else {
8476 tmp = I915_READ(PCH_DPLL_SEL);
8477 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8478 pll_id = DPLL_ID_PCH_PLL_B;
8479 else
8480 pll_id= DPLL_ID_PCH_PLL_A;
8481 }
8482
8483 pipe_config->shared_dpll =
8484 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8485 pll = pipe_config->shared_dpll;
8486
8487 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8488 &pipe_config->dpll_hw_state));
8489
8490 tmp = pipe_config->dpll_hw_state.dpll;
8491 pipe_config->pixel_multiplier =
8492 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8493 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8494
8495 ironlake_pch_clock_get(crtc, pipe_config);
8496 } else {
8497 pipe_config->pixel_multiplier = 1;
8498 }
8499
8500 intel_get_pipe_timings(crtc, pipe_config);
8501 intel_get_pipe_src_size(crtc, pipe_config);
8502
8503 ironlake_get_pfit_config(crtc, pipe_config);
8504
8505 ret = true;
8506
8507 out:
8508 intel_display_power_put(dev_priv, power_domain);
8509
8510 return ret;
8511 }
8512
8513 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8514 {
8515 struct drm_device *dev = &dev_priv->drm;
8516 struct intel_crtc *crtc;
8517
8518 for_each_intel_crtc(dev, crtc)
8519 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8520 pipe_name(crtc->pipe));
8521
8522 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8523 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8524 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8525 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8526 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8527 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8528 "CPU PWM1 enabled\n");
8529 if (IS_HASWELL(dev_priv))
8530 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8531 "CPU PWM2 enabled\n");
8532 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8533 "PCH PWM1 enabled\n");
8534 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8535 "Utility pin enabled\n");
8536 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8537
8538 /*
8539 * In theory we can still leave IRQs enabled, as long as only the HPD
8540 * interrupts remain enabled. We used to check for that, but since it's
8541 * gen-specific and since we only disable LCPLL after we fully disable
8542 * the interrupts, the check below should be enough.
8543 */
8544 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8545 }
8546
8547 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8548 {
8549 if (IS_HASWELL(dev_priv))
8550 return I915_READ(D_COMP_HSW);
8551 else
8552 return I915_READ(D_COMP_BDW);
8553 }
8554
8555 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8556 {
8557 if (IS_HASWELL(dev_priv)) {
8558 mutex_lock(&dev_priv->rps.hw_lock);
8559 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8560 val))
8561 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8562 mutex_unlock(&dev_priv->rps.hw_lock);
8563 } else {
8564 I915_WRITE(D_COMP_BDW, val);
8565 POSTING_READ(D_COMP_BDW);
8566 }
8567 }
8568
8569 /*
8570 * This function implements pieces of two sequences from BSpec:
8571 * - Sequence for display software to disable LCPLL
8572 * - Sequence for display software to allow package C8+
8573 * The steps implemented here are just the steps that actually touch the LCPLL
8574 * register. Callers should take care of disabling all the display engine
8575 * functions, doing the mode unset, fixing interrupts, etc.
8576 */
8577 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8578 bool switch_to_fclk, bool allow_power_down)
8579 {
8580 uint32_t val;
8581
8582 assert_can_disable_lcpll(dev_priv);
8583
8584 val = I915_READ(LCPLL_CTL);
8585
8586 if (switch_to_fclk) {
8587 val |= LCPLL_CD_SOURCE_FCLK;
8588 I915_WRITE(LCPLL_CTL, val);
8589
8590 if (wait_for_us(I915_READ(LCPLL_CTL) &
8591 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8592 DRM_ERROR("Switching to FCLK failed\n");
8593
8594 val = I915_READ(LCPLL_CTL);
8595 }
8596
8597 val |= LCPLL_PLL_DISABLE;
8598 I915_WRITE(LCPLL_CTL, val);
8599 POSTING_READ(LCPLL_CTL);
8600
8601 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8602 DRM_ERROR("LCPLL still locked\n");
8603
8604 val = hsw_read_dcomp(dev_priv);
8605 val |= D_COMP_COMP_DISABLE;
8606 hsw_write_dcomp(dev_priv, val);
8607 ndelay(100);
8608
8609 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8610 1))
8611 DRM_ERROR("D_COMP RCOMP still in progress\n");
8612
8613 if (allow_power_down) {
8614 val = I915_READ(LCPLL_CTL);
8615 val |= LCPLL_POWER_DOWN_ALLOW;
8616 I915_WRITE(LCPLL_CTL, val);
8617 POSTING_READ(LCPLL_CTL);
8618 }
8619 }
8620
8621 /*
8622 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8623 * source.
8624 */
8625 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8626 {
8627 uint32_t val;
8628
8629 val = I915_READ(LCPLL_CTL);
8630
8631 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8632 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8633 return;
8634
8635 /*
8636 * Make sure we're not on PC8 state before disabling PC8, otherwise
8637 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8638 */
8639 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8640
8641 if (val & LCPLL_POWER_DOWN_ALLOW) {
8642 val &= ~LCPLL_POWER_DOWN_ALLOW;
8643 I915_WRITE(LCPLL_CTL, val);
8644 POSTING_READ(LCPLL_CTL);
8645 }
8646
8647 val = hsw_read_dcomp(dev_priv);
8648 val |= D_COMP_COMP_FORCE;
8649 val &= ~D_COMP_COMP_DISABLE;
8650 hsw_write_dcomp(dev_priv, val);
8651
8652 val = I915_READ(LCPLL_CTL);
8653 val &= ~LCPLL_PLL_DISABLE;
8654 I915_WRITE(LCPLL_CTL, val);
8655
8656 if (intel_wait_for_register(dev_priv,
8657 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8658 5))
8659 DRM_ERROR("LCPLL not locked yet\n");
8660
8661 if (val & LCPLL_CD_SOURCE_FCLK) {
8662 val = I915_READ(LCPLL_CTL);
8663 val &= ~LCPLL_CD_SOURCE_FCLK;
8664 I915_WRITE(LCPLL_CTL, val);
8665
8666 if (wait_for_us((I915_READ(LCPLL_CTL) &
8667 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8668 DRM_ERROR("Switching back to LCPLL failed\n");
8669 }
8670
8671 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8672 intel_update_cdclk(dev_priv);
8673 }
8674
8675 /*
8676 * Package states C8 and deeper are really deep PC states that can only be
8677 * reached when all the devices on the system allow it, so even if the graphics
8678 * device allows PC8+, it doesn't mean the system will actually get to these
8679 * states. Our driver only allows PC8+ when going into runtime PM.
8680 *
8681 * The requirements for PC8+ are that all the outputs are disabled, the power
8682 * well is disabled and most interrupts are disabled, and these are also
8683 * requirements for runtime PM. When these conditions are met, we manually do
8684 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8685 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8686 * hang the machine.
8687 *
8688 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8689 * the state of some registers, so when we come back from PC8+ we need to
8690 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8691 * need to take care of the registers kept by RC6. Notice that this happens even
8692 * if we don't put the device in PCI D3 state (which is what currently happens
8693 * because of the runtime PM support).
8694 *
8695 * For more, read "Display Sequences for Package C8" on the hardware
8696 * documentation.
8697 */
8698 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8699 {
8700 uint32_t val;
8701
8702 DRM_DEBUG_KMS("Enabling package C8+\n");
8703
8704 if (HAS_PCH_LPT_LP(dev_priv)) {
8705 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8706 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8707 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8708 }
8709
8710 lpt_disable_clkout_dp(dev_priv);
8711 hsw_disable_lcpll(dev_priv, true, true);
8712 }
8713
8714 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8715 {
8716 uint32_t val;
8717
8718 DRM_DEBUG_KMS("Disabling package C8+\n");
8719
8720 hsw_restore_lcpll(dev_priv);
8721 lpt_init_pch_refclk(dev_priv);
8722
8723 if (HAS_PCH_LPT_LP(dev_priv)) {
8724 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8725 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8726 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8727 }
8728 }
8729
8730 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8731 struct intel_crtc_state *crtc_state)
8732 {
8733 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8734 struct intel_encoder *encoder =
8735 intel_ddi_get_crtc_new_encoder(crtc_state);
8736
8737 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8738 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8739 pipe_name(crtc->pipe));
8740 return -EINVAL;
8741 }
8742 }
8743
8744 crtc->lowfreq_avail = false;
8745
8746 return 0;
8747 }
8748
8749 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8750 enum port port,
8751 struct intel_crtc_state *pipe_config)
8752 {
8753 enum intel_dpll_id id;
8754 u32 temp;
8755
8756 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8757 id = temp >> (port * 2);
8758
8759 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8760 return;
8761
8762 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8763 }
8764
8765 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8766 enum port port,
8767 struct intel_crtc_state *pipe_config)
8768 {
8769 enum intel_dpll_id id;
8770
8771 switch (port) {
8772 case PORT_A:
8773 id = DPLL_ID_SKL_DPLL0;
8774 break;
8775 case PORT_B:
8776 id = DPLL_ID_SKL_DPLL1;
8777 break;
8778 case PORT_C:
8779 id = DPLL_ID_SKL_DPLL2;
8780 break;
8781 default:
8782 DRM_ERROR("Incorrect port type\n");
8783 return;
8784 }
8785
8786 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8787 }
8788
8789 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8790 enum port port,
8791 struct intel_crtc_state *pipe_config)
8792 {
8793 enum intel_dpll_id id;
8794 u32 temp;
8795
8796 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8797 id = temp >> (port * 3 + 1);
8798
8799 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8800 return;
8801
8802 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8803 }
8804
8805 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8806 enum port port,
8807 struct intel_crtc_state *pipe_config)
8808 {
8809 enum intel_dpll_id id;
8810 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8811
8812 switch (ddi_pll_sel) {
8813 case PORT_CLK_SEL_WRPLL1:
8814 id = DPLL_ID_WRPLL1;
8815 break;
8816 case PORT_CLK_SEL_WRPLL2:
8817 id = DPLL_ID_WRPLL2;
8818 break;
8819 case PORT_CLK_SEL_SPLL:
8820 id = DPLL_ID_SPLL;
8821 break;
8822 case PORT_CLK_SEL_LCPLL_810:
8823 id = DPLL_ID_LCPLL_810;
8824 break;
8825 case PORT_CLK_SEL_LCPLL_1350:
8826 id = DPLL_ID_LCPLL_1350;
8827 break;
8828 case PORT_CLK_SEL_LCPLL_2700:
8829 id = DPLL_ID_LCPLL_2700;
8830 break;
8831 default:
8832 MISSING_CASE(ddi_pll_sel);
8833 /* fall through */
8834 case PORT_CLK_SEL_NONE:
8835 return;
8836 }
8837
8838 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8839 }
8840
8841 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8842 struct intel_crtc_state *pipe_config,
8843 u64 *power_domain_mask)
8844 {
8845 struct drm_device *dev = crtc->base.dev;
8846 struct drm_i915_private *dev_priv = to_i915(dev);
8847 enum intel_display_power_domain power_domain;
8848 u32 tmp;
8849
8850 /*
8851 * The pipe->transcoder mapping is fixed with the exception of the eDP
8852 * transcoder handled below.
8853 */
8854 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8855
8856 /*
8857 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8858 * consistency and less surprising code; it's in always on power).
8859 */
8860 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8861 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8862 enum pipe trans_edp_pipe;
8863 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8864 default:
8865 WARN(1, "unknown pipe linked to edp transcoder\n");
8866 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8867 case TRANS_DDI_EDP_INPUT_A_ON:
8868 trans_edp_pipe = PIPE_A;
8869 break;
8870 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8871 trans_edp_pipe = PIPE_B;
8872 break;
8873 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8874 trans_edp_pipe = PIPE_C;
8875 break;
8876 }
8877
8878 if (trans_edp_pipe == crtc->pipe)
8879 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8880 }
8881
8882 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8883 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8884 return false;
8885 *power_domain_mask |= BIT_ULL(power_domain);
8886
8887 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8888
8889 return tmp & PIPECONF_ENABLE;
8890 }
8891
8892 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8893 struct intel_crtc_state *pipe_config,
8894 u64 *power_domain_mask)
8895 {
8896 struct drm_device *dev = crtc->base.dev;
8897 struct drm_i915_private *dev_priv = to_i915(dev);
8898 enum intel_display_power_domain power_domain;
8899 enum port port;
8900 enum transcoder cpu_transcoder;
8901 u32 tmp;
8902
8903 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8904 if (port == PORT_A)
8905 cpu_transcoder = TRANSCODER_DSI_A;
8906 else
8907 cpu_transcoder = TRANSCODER_DSI_C;
8908
8909 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
8910 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8911 continue;
8912 *power_domain_mask |= BIT_ULL(power_domain);
8913
8914 /*
8915 * The PLL needs to be enabled with a valid divider
8916 * configuration, otherwise accessing DSI registers will hang
8917 * the machine. See BSpec North Display Engine
8918 * registers/MIPI[BXT]. We can break out here early, since we
8919 * need the same DSI PLL to be enabled for both DSI ports.
8920 */
8921 if (!intel_dsi_pll_is_enabled(dev_priv))
8922 break;
8923
8924 /* XXX: this works for video mode only */
8925 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
8926 if (!(tmp & DPI_ENABLE))
8927 continue;
8928
8929 tmp = I915_READ(MIPI_CTRL(port));
8930 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
8931 continue;
8932
8933 pipe_config->cpu_transcoder = cpu_transcoder;
8934 break;
8935 }
8936
8937 return transcoder_is_dsi(pipe_config->cpu_transcoder);
8938 }
8939
8940 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8941 struct intel_crtc_state *pipe_config)
8942 {
8943 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8944 struct intel_shared_dpll *pll;
8945 enum port port;
8946 uint32_t tmp;
8947
8948 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8949
8950 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8951
8952 if (IS_CANNONLAKE(dev_priv))
8953 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
8954 else if (IS_GEN9_BC(dev_priv))
8955 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8956 else if (IS_GEN9_LP(dev_priv))
8957 bxt_get_ddi_pll(dev_priv, port, pipe_config);
8958 else
8959 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8960
8961 pll = pipe_config->shared_dpll;
8962 if (pll) {
8963 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8964 &pipe_config->dpll_hw_state));
8965 }
8966
8967 /*
8968 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8969 * DDI E. So just check whether this pipe is wired to DDI E and whether
8970 * the PCH transcoder is on.
8971 */
8972 if (INTEL_GEN(dev_priv) < 9 &&
8973 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8974 pipe_config->has_pch_encoder = true;
8975
8976 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8977 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8978 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8979
8980 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8981 }
8982 }
8983
8984 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8985 struct intel_crtc_state *pipe_config)
8986 {
8987 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8988 enum intel_display_power_domain power_domain;
8989 u64 power_domain_mask;
8990 bool active;
8991
8992 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8993 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8994 return false;
8995 power_domain_mask = BIT_ULL(power_domain);
8996
8997 pipe_config->shared_dpll = NULL;
8998
8999 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9000
9001 if (IS_GEN9_LP(dev_priv) &&
9002 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9003 WARN_ON(active);
9004 active = true;
9005 }
9006
9007 if (!active)
9008 goto out;
9009
9010 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9011 haswell_get_ddi_port_state(crtc, pipe_config);
9012 intel_get_pipe_timings(crtc, pipe_config);
9013 }
9014
9015 intel_get_pipe_src_size(crtc, pipe_config);
9016
9017 pipe_config->gamma_mode =
9018 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9019
9020 if (INTEL_GEN(dev_priv) >= 9) {
9021 intel_crtc_init_scalers(crtc, pipe_config);
9022
9023 pipe_config->scaler_state.scaler_id = -1;
9024 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9025 }
9026
9027 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9028 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9029 power_domain_mask |= BIT_ULL(power_domain);
9030 if (INTEL_GEN(dev_priv) >= 9)
9031 skylake_get_pfit_config(crtc, pipe_config);
9032 else
9033 ironlake_get_pfit_config(crtc, pipe_config);
9034 }
9035
9036 if (IS_HASWELL(dev_priv))
9037 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9038 (I915_READ(IPS_CTL) & IPS_ENABLE);
9039
9040 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9041 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9042 pipe_config->pixel_multiplier =
9043 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9044 } else {
9045 pipe_config->pixel_multiplier = 1;
9046 }
9047
9048 out:
9049 for_each_power_domain(power_domain, power_domain_mask)
9050 intel_display_power_put(dev_priv, power_domain);
9051
9052 return active;
9053 }
9054
9055 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9056 {
9057 struct drm_i915_private *dev_priv =
9058 to_i915(plane_state->base.plane->dev);
9059 const struct drm_framebuffer *fb = plane_state->base.fb;
9060 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9061 u32 base;
9062
9063 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9064 base = obj->phys_handle->busaddr;
9065 else
9066 base = intel_plane_ggtt_offset(plane_state);
9067
9068 base += plane_state->main.offset;
9069
9070 /* ILK+ do this automagically */
9071 if (HAS_GMCH_DISPLAY(dev_priv) &&
9072 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9073 base += (plane_state->base.crtc_h *
9074 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9075
9076 return base;
9077 }
9078
9079 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9080 {
9081 int x = plane_state->base.crtc_x;
9082 int y = plane_state->base.crtc_y;
9083 u32 pos = 0;
9084
9085 if (x < 0) {
9086 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9087 x = -x;
9088 }
9089 pos |= x << CURSOR_X_SHIFT;
9090
9091 if (y < 0) {
9092 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9093 y = -y;
9094 }
9095 pos |= y << CURSOR_Y_SHIFT;
9096
9097 return pos;
9098 }
9099
9100 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9101 {
9102 const struct drm_mode_config *config =
9103 &plane_state->base.plane->dev->mode_config;
9104 int width = plane_state->base.crtc_w;
9105 int height = plane_state->base.crtc_h;
9106
9107 return width > 0 && width <= config->cursor_width &&
9108 height > 0 && height <= config->cursor_height;
9109 }
9110
9111 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9112 struct intel_plane_state *plane_state)
9113 {
9114 const struct drm_framebuffer *fb = plane_state->base.fb;
9115 int src_x, src_y;
9116 u32 offset;
9117 int ret;
9118
9119 ret = drm_plane_helper_check_state(&plane_state->base,
9120 &plane_state->clip,
9121 DRM_PLANE_HELPER_NO_SCALING,
9122 DRM_PLANE_HELPER_NO_SCALING,
9123 true, true);
9124 if (ret)
9125 return ret;
9126
9127 if (!fb)
9128 return 0;
9129
9130 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9131 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9132 return -EINVAL;
9133 }
9134
9135 src_x = plane_state->base.src_x >> 16;
9136 src_y = plane_state->base.src_y >> 16;
9137
9138 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9139 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9140
9141 if (src_x != 0 || src_y != 0) {
9142 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9143 return -EINVAL;
9144 }
9145
9146 plane_state->main.offset = offset;
9147
9148 return 0;
9149 }
9150
9151 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9152 const struct intel_plane_state *plane_state)
9153 {
9154 const struct drm_framebuffer *fb = plane_state->base.fb;
9155
9156 return CURSOR_ENABLE |
9157 CURSOR_GAMMA_ENABLE |
9158 CURSOR_FORMAT_ARGB |
9159 CURSOR_STRIDE(fb->pitches[0]);
9160 }
9161
9162 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9163 {
9164 int width = plane_state->base.crtc_w;
9165
9166 /*
9167 * 845g/865g are only limited by the width of their cursors,
9168 * the height is arbitrary up to the precision of the register.
9169 */
9170 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9171 }
9172
9173 static int i845_check_cursor(struct intel_plane *plane,
9174 struct intel_crtc_state *crtc_state,
9175 struct intel_plane_state *plane_state)
9176 {
9177 const struct drm_framebuffer *fb = plane_state->base.fb;
9178 int ret;
9179
9180 ret = intel_check_cursor(crtc_state, plane_state);
9181 if (ret)
9182 return ret;
9183
9184 /* if we want to turn off the cursor ignore width and height */
9185 if (!fb)
9186 return 0;
9187
9188 /* Check for which cursor types we support */
9189 if (!i845_cursor_size_ok(plane_state)) {
9190 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9191 plane_state->base.crtc_w,
9192 plane_state->base.crtc_h);
9193 return -EINVAL;
9194 }
9195
9196 switch (fb->pitches[0]) {
9197 case 256:
9198 case 512:
9199 case 1024:
9200 case 2048:
9201 break;
9202 default:
9203 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9204 fb->pitches[0]);
9205 return -EINVAL;
9206 }
9207
9208 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9209
9210 return 0;
9211 }
9212
9213 static void i845_update_cursor(struct intel_plane *plane,
9214 const struct intel_crtc_state *crtc_state,
9215 const struct intel_plane_state *plane_state)
9216 {
9217 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9218 u32 cntl = 0, base = 0, pos = 0, size = 0;
9219 unsigned long irqflags;
9220
9221 if (plane_state && plane_state->base.visible) {
9222 unsigned int width = plane_state->base.crtc_w;
9223 unsigned int height = plane_state->base.crtc_h;
9224
9225 cntl = plane_state->ctl;
9226 size = (height << 12) | width;
9227
9228 base = intel_cursor_base(plane_state);
9229 pos = intel_cursor_position(plane_state);
9230 }
9231
9232 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9233
9234 /* On these chipsets we can only modify the base/size/stride
9235 * whilst the cursor is disabled.
9236 */
9237 if (plane->cursor.base != base ||
9238 plane->cursor.size != size ||
9239 plane->cursor.cntl != cntl) {
9240 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9241 I915_WRITE_FW(CURBASE(PIPE_A), base);
9242 I915_WRITE_FW(CURSIZE, size);
9243 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9244 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9245
9246 plane->cursor.base = base;
9247 plane->cursor.size = size;
9248 plane->cursor.cntl = cntl;
9249 } else {
9250 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9251 }
9252
9253 POSTING_READ_FW(CURCNTR(PIPE_A));
9254
9255 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9256 }
9257
9258 static void i845_disable_cursor(struct intel_plane *plane,
9259 struct intel_crtc *crtc)
9260 {
9261 i845_update_cursor(plane, NULL, NULL);
9262 }
9263
9264 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9265 const struct intel_plane_state *plane_state)
9266 {
9267 struct drm_i915_private *dev_priv =
9268 to_i915(plane_state->base.plane->dev);
9269 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9270 u32 cntl;
9271
9272 cntl = MCURSOR_GAMMA_ENABLE;
9273
9274 if (HAS_DDI(dev_priv))
9275 cntl |= CURSOR_PIPE_CSC_ENABLE;
9276
9277 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9278
9279 switch (plane_state->base.crtc_w) {
9280 case 64:
9281 cntl |= CURSOR_MODE_64_ARGB_AX;
9282 break;
9283 case 128:
9284 cntl |= CURSOR_MODE_128_ARGB_AX;
9285 break;
9286 case 256:
9287 cntl |= CURSOR_MODE_256_ARGB_AX;
9288 break;
9289 default:
9290 MISSING_CASE(plane_state->base.crtc_w);
9291 return 0;
9292 }
9293
9294 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9295 cntl |= CURSOR_ROTATE_180;
9296
9297 return cntl;
9298 }
9299
9300 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9301 {
9302 struct drm_i915_private *dev_priv =
9303 to_i915(plane_state->base.plane->dev);
9304 int width = plane_state->base.crtc_w;
9305 int height = plane_state->base.crtc_h;
9306
9307 if (!intel_cursor_size_ok(plane_state))
9308 return false;
9309
9310 /* Cursor width is limited to a few power-of-two sizes */
9311 switch (width) {
9312 case 256:
9313 case 128:
9314 case 64:
9315 break;
9316 default:
9317 return false;
9318 }
9319
9320 /*
9321 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9322 * height from 8 lines up to the cursor width, when the
9323 * cursor is not rotated. Everything else requires square
9324 * cursors.
9325 */
9326 if (HAS_CUR_FBC(dev_priv) &&
9327 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9328 if (height < 8 || height > width)
9329 return false;
9330 } else {
9331 if (height != width)
9332 return false;
9333 }
9334
9335 return true;
9336 }
9337
9338 static int i9xx_check_cursor(struct intel_plane *plane,
9339 struct intel_crtc_state *crtc_state,
9340 struct intel_plane_state *plane_state)
9341 {
9342 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9343 const struct drm_framebuffer *fb = plane_state->base.fb;
9344 enum pipe pipe = plane->pipe;
9345 int ret;
9346
9347 ret = intel_check_cursor(crtc_state, plane_state);
9348 if (ret)
9349 return ret;
9350
9351 /* if we want to turn off the cursor ignore width and height */
9352 if (!fb)
9353 return 0;
9354
9355 /* Check for which cursor types we support */
9356 if (!i9xx_cursor_size_ok(plane_state)) {
9357 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9358 plane_state->base.crtc_w,
9359 plane_state->base.crtc_h);
9360 return -EINVAL;
9361 }
9362
9363 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9364 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9365 fb->pitches[0], plane_state->base.crtc_w);
9366 return -EINVAL;
9367 }
9368
9369 /*
9370 * There's something wrong with the cursor on CHV pipe C.
9371 * If it straddles the left edge of the screen then
9372 * moving it away from the edge or disabling it often
9373 * results in a pipe underrun, and often that can lead to
9374 * dead pipe (constant underrun reported, and it scans
9375 * out just a solid color). To recover from that, the
9376 * display power well must be turned off and on again.
9377 * Refuse the put the cursor into that compromised position.
9378 */
9379 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9380 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9381 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9382 return -EINVAL;
9383 }
9384
9385 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9386
9387 return 0;
9388 }
9389
9390 static void i9xx_update_cursor(struct intel_plane *plane,
9391 const struct intel_crtc_state *crtc_state,
9392 const struct intel_plane_state *plane_state)
9393 {
9394 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9395 enum pipe pipe = plane->pipe;
9396 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9397 unsigned long irqflags;
9398
9399 if (plane_state && plane_state->base.visible) {
9400 cntl = plane_state->ctl;
9401
9402 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9403 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9404
9405 base = intel_cursor_base(plane_state);
9406 pos = intel_cursor_position(plane_state);
9407 }
9408
9409 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9410
9411 /*
9412 * On some platforms writing CURCNTR first will also
9413 * cause CURPOS to be armed by the CURBASE write.
9414 * Without the CURCNTR write the CURPOS write would
9415 * arm itself. Thus we always start the full update
9416 * with a CURCNTR write.
9417 *
9418 * On other platforms CURPOS always requires the
9419 * CURBASE write to arm the update. Additonally
9420 * a write to any of the cursor register will cancel
9421 * an already armed cursor update. Thus leaving out
9422 * the CURBASE write after CURPOS could lead to a
9423 * cursor that doesn't appear to move, or even change
9424 * shape. Thus we always write CURBASE.
9425 *
9426 * CURCNTR and CUR_FBC_CTL are always
9427 * armed by the CURBASE write only.
9428 */
9429 if (plane->cursor.base != base ||
9430 plane->cursor.size != fbc_ctl ||
9431 plane->cursor.cntl != cntl) {
9432 I915_WRITE_FW(CURCNTR(pipe), cntl);
9433 if (HAS_CUR_FBC(dev_priv))
9434 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9435 I915_WRITE_FW(CURPOS(pipe), pos);
9436 I915_WRITE_FW(CURBASE(pipe), base);
9437
9438 plane->cursor.base = base;
9439 plane->cursor.size = fbc_ctl;
9440 plane->cursor.cntl = cntl;
9441 } else {
9442 I915_WRITE_FW(CURPOS(pipe), pos);
9443 I915_WRITE_FW(CURBASE(pipe), base);
9444 }
9445
9446 POSTING_READ_FW(CURBASE(pipe));
9447
9448 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9449 }
9450
9451 static void i9xx_disable_cursor(struct intel_plane *plane,
9452 struct intel_crtc *crtc)
9453 {
9454 i9xx_update_cursor(plane, NULL, NULL);
9455 }
9456
9457
9458 /* VESA 640x480x72Hz mode to set on the pipe */
9459 static struct drm_display_mode load_detect_mode = {
9460 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9461 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9462 };
9463
9464 struct drm_framebuffer *
9465 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9466 struct drm_mode_fb_cmd2 *mode_cmd)
9467 {
9468 struct intel_framebuffer *intel_fb;
9469 int ret;
9470
9471 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9472 if (!intel_fb)
9473 return ERR_PTR(-ENOMEM);
9474
9475 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9476 if (ret)
9477 goto err;
9478
9479 return &intel_fb->base;
9480
9481 err:
9482 kfree(intel_fb);
9483 return ERR_PTR(ret);
9484 }
9485
9486 static u32
9487 intel_framebuffer_pitch_for_width(int width, int bpp)
9488 {
9489 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9490 return ALIGN(pitch, 64);
9491 }
9492
9493 static u32
9494 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9495 {
9496 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9497 return PAGE_ALIGN(pitch * mode->vdisplay);
9498 }
9499
9500 static struct drm_framebuffer *
9501 intel_framebuffer_create_for_mode(struct drm_device *dev,
9502 struct drm_display_mode *mode,
9503 int depth, int bpp)
9504 {
9505 struct drm_framebuffer *fb;
9506 struct drm_i915_gem_object *obj;
9507 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9508
9509 obj = i915_gem_object_create(to_i915(dev),
9510 intel_framebuffer_size_for_mode(mode, bpp));
9511 if (IS_ERR(obj))
9512 return ERR_CAST(obj);
9513
9514 mode_cmd.width = mode->hdisplay;
9515 mode_cmd.height = mode->vdisplay;
9516 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9517 bpp);
9518 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9519
9520 fb = intel_framebuffer_create(obj, &mode_cmd);
9521 if (IS_ERR(fb))
9522 i915_gem_object_put(obj);
9523
9524 return fb;
9525 }
9526
9527 static struct drm_framebuffer *
9528 mode_fits_in_fbdev(struct drm_device *dev,
9529 struct drm_display_mode *mode)
9530 {
9531 #ifdef CONFIG_DRM_FBDEV_EMULATION
9532 struct drm_i915_private *dev_priv = to_i915(dev);
9533 struct drm_i915_gem_object *obj;
9534 struct drm_framebuffer *fb;
9535
9536 if (!dev_priv->fbdev)
9537 return NULL;
9538
9539 if (!dev_priv->fbdev->fb)
9540 return NULL;
9541
9542 obj = dev_priv->fbdev->fb->obj;
9543 BUG_ON(!obj);
9544
9545 fb = &dev_priv->fbdev->fb->base;
9546 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9547 fb->format->cpp[0] * 8))
9548 return NULL;
9549
9550 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9551 return NULL;
9552
9553 drm_framebuffer_reference(fb);
9554 return fb;
9555 #else
9556 return NULL;
9557 #endif
9558 }
9559
9560 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9561 struct drm_crtc *crtc,
9562 struct drm_display_mode *mode,
9563 struct drm_framebuffer *fb,
9564 int x, int y)
9565 {
9566 struct drm_plane_state *plane_state;
9567 int hdisplay, vdisplay;
9568 int ret;
9569
9570 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9571 if (IS_ERR(plane_state))
9572 return PTR_ERR(plane_state);
9573
9574 if (mode)
9575 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9576 else
9577 hdisplay = vdisplay = 0;
9578
9579 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9580 if (ret)
9581 return ret;
9582 drm_atomic_set_fb_for_plane(plane_state, fb);
9583 plane_state->crtc_x = 0;
9584 plane_state->crtc_y = 0;
9585 plane_state->crtc_w = hdisplay;
9586 plane_state->crtc_h = vdisplay;
9587 plane_state->src_x = x << 16;
9588 plane_state->src_y = y << 16;
9589 plane_state->src_w = hdisplay << 16;
9590 plane_state->src_h = vdisplay << 16;
9591
9592 return 0;
9593 }
9594
9595 int intel_get_load_detect_pipe(struct drm_connector *connector,
9596 struct drm_display_mode *mode,
9597 struct intel_load_detect_pipe *old,
9598 struct drm_modeset_acquire_ctx *ctx)
9599 {
9600 struct intel_crtc *intel_crtc;
9601 struct intel_encoder *intel_encoder =
9602 intel_attached_encoder(connector);
9603 struct drm_crtc *possible_crtc;
9604 struct drm_encoder *encoder = &intel_encoder->base;
9605 struct drm_crtc *crtc = NULL;
9606 struct drm_device *dev = encoder->dev;
9607 struct drm_i915_private *dev_priv = to_i915(dev);
9608 struct drm_framebuffer *fb;
9609 struct drm_mode_config *config = &dev->mode_config;
9610 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9611 struct drm_connector_state *connector_state;
9612 struct intel_crtc_state *crtc_state;
9613 int ret, i = -1;
9614
9615 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9616 connector->base.id, connector->name,
9617 encoder->base.id, encoder->name);
9618
9619 old->restore_state = NULL;
9620
9621 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9622
9623 /*
9624 * Algorithm gets a little messy:
9625 *
9626 * - if the connector already has an assigned crtc, use it (but make
9627 * sure it's on first)
9628 *
9629 * - try to find the first unused crtc that can drive this connector,
9630 * and use that if we find one
9631 */
9632
9633 /* See if we already have a CRTC for this connector */
9634 if (connector->state->crtc) {
9635 crtc = connector->state->crtc;
9636
9637 ret = drm_modeset_lock(&crtc->mutex, ctx);
9638 if (ret)
9639 goto fail;
9640
9641 /* Make sure the crtc and connector are running */
9642 goto found;
9643 }
9644
9645 /* Find an unused one (if possible) */
9646 for_each_crtc(dev, possible_crtc) {
9647 i++;
9648 if (!(encoder->possible_crtcs & (1 << i)))
9649 continue;
9650
9651 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9652 if (ret)
9653 goto fail;
9654
9655 if (possible_crtc->state->enable) {
9656 drm_modeset_unlock(&possible_crtc->mutex);
9657 continue;
9658 }
9659
9660 crtc = possible_crtc;
9661 break;
9662 }
9663
9664 /*
9665 * If we didn't find an unused CRTC, don't use any.
9666 */
9667 if (!crtc) {
9668 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9669 ret = -ENODEV;
9670 goto fail;
9671 }
9672
9673 found:
9674 intel_crtc = to_intel_crtc(crtc);
9675
9676 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9677 if (ret)
9678 goto fail;
9679
9680 state = drm_atomic_state_alloc(dev);
9681 restore_state = drm_atomic_state_alloc(dev);
9682 if (!state || !restore_state) {
9683 ret = -ENOMEM;
9684 goto fail;
9685 }
9686
9687 state->acquire_ctx = ctx;
9688 restore_state->acquire_ctx = ctx;
9689
9690 connector_state = drm_atomic_get_connector_state(state, connector);
9691 if (IS_ERR(connector_state)) {
9692 ret = PTR_ERR(connector_state);
9693 goto fail;
9694 }
9695
9696 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9697 if (ret)
9698 goto fail;
9699
9700 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9701 if (IS_ERR(crtc_state)) {
9702 ret = PTR_ERR(crtc_state);
9703 goto fail;
9704 }
9705
9706 crtc_state->base.active = crtc_state->base.enable = true;
9707
9708 if (!mode)
9709 mode = &load_detect_mode;
9710
9711 /* We need a framebuffer large enough to accommodate all accesses
9712 * that the plane may generate whilst we perform load detection.
9713 * We can not rely on the fbcon either being present (we get called
9714 * during its initialisation to detect all boot displays, or it may
9715 * not even exist) or that it is large enough to satisfy the
9716 * requested mode.
9717 */
9718 fb = mode_fits_in_fbdev(dev, mode);
9719 if (fb == NULL) {
9720 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9721 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9722 } else
9723 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9724 if (IS_ERR(fb)) {
9725 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9726 ret = PTR_ERR(fb);
9727 goto fail;
9728 }
9729
9730 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9731 if (ret)
9732 goto fail;
9733
9734 drm_framebuffer_unreference(fb);
9735
9736 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9737 if (ret)
9738 goto fail;
9739
9740 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9741 if (!ret)
9742 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9743 if (!ret)
9744 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9745 if (ret) {
9746 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9747 goto fail;
9748 }
9749
9750 ret = drm_atomic_commit(state);
9751 if (ret) {
9752 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9753 goto fail;
9754 }
9755
9756 old->restore_state = restore_state;
9757 drm_atomic_state_put(state);
9758
9759 /* let the connector get through one full cycle before testing */
9760 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9761 return true;
9762
9763 fail:
9764 if (state) {
9765 drm_atomic_state_put(state);
9766 state = NULL;
9767 }
9768 if (restore_state) {
9769 drm_atomic_state_put(restore_state);
9770 restore_state = NULL;
9771 }
9772
9773 if (ret == -EDEADLK)
9774 return ret;
9775
9776 return false;
9777 }
9778
9779 void intel_release_load_detect_pipe(struct drm_connector *connector,
9780 struct intel_load_detect_pipe *old,
9781 struct drm_modeset_acquire_ctx *ctx)
9782 {
9783 struct intel_encoder *intel_encoder =
9784 intel_attached_encoder(connector);
9785 struct drm_encoder *encoder = &intel_encoder->base;
9786 struct drm_atomic_state *state = old->restore_state;
9787 int ret;
9788
9789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9790 connector->base.id, connector->name,
9791 encoder->base.id, encoder->name);
9792
9793 if (!state)
9794 return;
9795
9796 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9797 if (ret)
9798 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9799 drm_atomic_state_put(state);
9800 }
9801
9802 static int i9xx_pll_refclk(struct drm_device *dev,
9803 const struct intel_crtc_state *pipe_config)
9804 {
9805 struct drm_i915_private *dev_priv = to_i915(dev);
9806 u32 dpll = pipe_config->dpll_hw_state.dpll;
9807
9808 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9809 return dev_priv->vbt.lvds_ssc_freq;
9810 else if (HAS_PCH_SPLIT(dev_priv))
9811 return 120000;
9812 else if (!IS_GEN2(dev_priv))
9813 return 96000;
9814 else
9815 return 48000;
9816 }
9817
9818 /* Returns the clock of the currently programmed mode of the given pipe. */
9819 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9820 struct intel_crtc_state *pipe_config)
9821 {
9822 struct drm_device *dev = crtc->base.dev;
9823 struct drm_i915_private *dev_priv = to_i915(dev);
9824 int pipe = pipe_config->cpu_transcoder;
9825 u32 dpll = pipe_config->dpll_hw_state.dpll;
9826 u32 fp;
9827 struct dpll clock;
9828 int port_clock;
9829 int refclk = i9xx_pll_refclk(dev, pipe_config);
9830
9831 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9832 fp = pipe_config->dpll_hw_state.fp0;
9833 else
9834 fp = pipe_config->dpll_hw_state.fp1;
9835
9836 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9837 if (IS_PINEVIEW(dev_priv)) {
9838 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9839 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9840 } else {
9841 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9842 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9843 }
9844
9845 if (!IS_GEN2(dev_priv)) {
9846 if (IS_PINEVIEW(dev_priv))
9847 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9848 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9849 else
9850 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9851 DPLL_FPA01_P1_POST_DIV_SHIFT);
9852
9853 switch (dpll & DPLL_MODE_MASK) {
9854 case DPLLB_MODE_DAC_SERIAL:
9855 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9856 5 : 10;
9857 break;
9858 case DPLLB_MODE_LVDS:
9859 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9860 7 : 14;
9861 break;
9862 default:
9863 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9864 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9865 return;
9866 }
9867
9868 if (IS_PINEVIEW(dev_priv))
9869 port_clock = pnv_calc_dpll_params(refclk, &clock);
9870 else
9871 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9872 } else {
9873 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9874 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9875
9876 if (is_lvds) {
9877 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9878 DPLL_FPA01_P1_POST_DIV_SHIFT);
9879
9880 if (lvds & LVDS_CLKB_POWER_UP)
9881 clock.p2 = 7;
9882 else
9883 clock.p2 = 14;
9884 } else {
9885 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9886 clock.p1 = 2;
9887 else {
9888 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9889 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9890 }
9891 if (dpll & PLL_P2_DIVIDE_BY_4)
9892 clock.p2 = 4;
9893 else
9894 clock.p2 = 2;
9895 }
9896
9897 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9898 }
9899
9900 /*
9901 * This value includes pixel_multiplier. We will use
9902 * port_clock to compute adjusted_mode.crtc_clock in the
9903 * encoder's get_config() function.
9904 */
9905 pipe_config->port_clock = port_clock;
9906 }
9907
9908 int intel_dotclock_calculate(int link_freq,
9909 const struct intel_link_m_n *m_n)
9910 {
9911 /*
9912 * The calculation for the data clock is:
9913 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9914 * But we want to avoid losing precison if possible, so:
9915 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9916 *
9917 * and the link clock is simpler:
9918 * link_clock = (m * link_clock) / n
9919 */
9920
9921 if (!m_n->link_n)
9922 return 0;
9923
9924 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9925 }
9926
9927 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9928 struct intel_crtc_state *pipe_config)
9929 {
9930 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9931
9932 /* read out port_clock from the DPLL */
9933 i9xx_crtc_clock_get(crtc, pipe_config);
9934
9935 /*
9936 * In case there is an active pipe without active ports,
9937 * we may need some idea for the dotclock anyway.
9938 * Calculate one based on the FDI configuration.
9939 */
9940 pipe_config->base.adjusted_mode.crtc_clock =
9941 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9942 &pipe_config->fdi_m_n);
9943 }
9944
9945 /** Returns the currently programmed mode of the given pipe. */
9946 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9947 struct drm_crtc *crtc)
9948 {
9949 struct drm_i915_private *dev_priv = to_i915(dev);
9950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9951 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9952 struct drm_display_mode *mode;
9953 struct intel_crtc_state *pipe_config;
9954 int htot = I915_READ(HTOTAL(cpu_transcoder));
9955 int hsync = I915_READ(HSYNC(cpu_transcoder));
9956 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9957 int vsync = I915_READ(VSYNC(cpu_transcoder));
9958 enum pipe pipe = intel_crtc->pipe;
9959
9960 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9961 if (!mode)
9962 return NULL;
9963
9964 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9965 if (!pipe_config) {
9966 kfree(mode);
9967 return NULL;
9968 }
9969
9970 /*
9971 * Construct a pipe_config sufficient for getting the clock info
9972 * back out of crtc_clock_get.
9973 *
9974 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9975 * to use a real value here instead.
9976 */
9977 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9978 pipe_config->pixel_multiplier = 1;
9979 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9980 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9981 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9982 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9983
9984 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9985 mode->hdisplay = (htot & 0xffff) + 1;
9986 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9987 mode->hsync_start = (hsync & 0xffff) + 1;
9988 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9989 mode->vdisplay = (vtot & 0xffff) + 1;
9990 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9991 mode->vsync_start = (vsync & 0xffff) + 1;
9992 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9993
9994 drm_mode_set_name(mode);
9995
9996 kfree(pipe_config);
9997
9998 return mode;
9999 }
10000
10001 static void intel_crtc_destroy(struct drm_crtc *crtc)
10002 {
10003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10004
10005 drm_crtc_cleanup(crtc);
10006 kfree(intel_crtc);
10007 }
10008
10009 /**
10010 * intel_wm_need_update - Check whether watermarks need updating
10011 * @plane: drm plane
10012 * @state: new plane state
10013 *
10014 * Check current plane state versus the new one to determine whether
10015 * watermarks need to be recalculated.
10016 *
10017 * Returns true or false.
10018 */
10019 static bool intel_wm_need_update(struct drm_plane *plane,
10020 struct drm_plane_state *state)
10021 {
10022 struct intel_plane_state *new = to_intel_plane_state(state);
10023 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10024
10025 /* Update watermarks on tiling or size changes. */
10026 if (new->base.visible != cur->base.visible)
10027 return true;
10028
10029 if (!cur->base.fb || !new->base.fb)
10030 return false;
10031
10032 if (cur->base.fb->modifier != new->base.fb->modifier ||
10033 cur->base.rotation != new->base.rotation ||
10034 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10035 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10036 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10037 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10038 return true;
10039
10040 return false;
10041 }
10042
10043 static bool needs_scaling(struct intel_plane_state *state)
10044 {
10045 int src_w = drm_rect_width(&state->base.src) >> 16;
10046 int src_h = drm_rect_height(&state->base.src) >> 16;
10047 int dst_w = drm_rect_width(&state->base.dst);
10048 int dst_h = drm_rect_height(&state->base.dst);
10049
10050 return (src_w != dst_w || src_h != dst_h);
10051 }
10052
10053 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10054 struct drm_plane_state *plane_state)
10055 {
10056 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10057 struct drm_crtc *crtc = crtc_state->crtc;
10058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10059 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10060 struct drm_device *dev = crtc->dev;
10061 struct drm_i915_private *dev_priv = to_i915(dev);
10062 struct intel_plane_state *old_plane_state =
10063 to_intel_plane_state(plane->base.state);
10064 bool mode_changed = needs_modeset(crtc_state);
10065 bool was_crtc_enabled = crtc->state->active;
10066 bool is_crtc_enabled = crtc_state->active;
10067 bool turn_off, turn_on, visible, was_visible;
10068 struct drm_framebuffer *fb = plane_state->fb;
10069 int ret;
10070
10071 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10072 ret = skl_update_scaler_plane(
10073 to_intel_crtc_state(crtc_state),
10074 to_intel_plane_state(plane_state));
10075 if (ret)
10076 return ret;
10077 }
10078
10079 was_visible = old_plane_state->base.visible;
10080 visible = plane_state->visible;
10081
10082 if (!was_crtc_enabled && WARN_ON(was_visible))
10083 was_visible = false;
10084
10085 /*
10086 * Visibility is calculated as if the crtc was on, but
10087 * after scaler setup everything depends on it being off
10088 * when the crtc isn't active.
10089 *
10090 * FIXME this is wrong for watermarks. Watermarks should also
10091 * be computed as if the pipe would be active. Perhaps move
10092 * per-plane wm computation to the .check_plane() hook, and
10093 * only combine the results from all planes in the current place?
10094 */
10095 if (!is_crtc_enabled) {
10096 plane_state->visible = visible = false;
10097 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10098 }
10099
10100 if (!was_visible && !visible)
10101 return 0;
10102
10103 if (fb != old_plane_state->base.fb)
10104 pipe_config->fb_changed = true;
10105
10106 turn_off = was_visible && (!visible || mode_changed);
10107 turn_on = visible && (!was_visible || mode_changed);
10108
10109 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10110 intel_crtc->base.base.id, intel_crtc->base.name,
10111 plane->base.base.id, plane->base.name,
10112 fb ? fb->base.id : -1);
10113
10114 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10115 plane->base.base.id, plane->base.name,
10116 was_visible, visible,
10117 turn_off, turn_on, mode_changed);
10118
10119 if (turn_on) {
10120 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10121 pipe_config->update_wm_pre = true;
10122
10123 /* must disable cxsr around plane enable/disable */
10124 if (plane->id != PLANE_CURSOR)
10125 pipe_config->disable_cxsr = true;
10126 } else if (turn_off) {
10127 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10128 pipe_config->update_wm_post = true;
10129
10130 /* must disable cxsr around plane enable/disable */
10131 if (plane->id != PLANE_CURSOR)
10132 pipe_config->disable_cxsr = true;
10133 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10134 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10135 /* FIXME bollocks */
10136 pipe_config->update_wm_pre = true;
10137 pipe_config->update_wm_post = true;
10138 }
10139 }
10140
10141 if (visible || was_visible)
10142 pipe_config->fb_bits |= plane->frontbuffer_bit;
10143
10144 /*
10145 * WaCxSRDisabledForSpriteScaling:ivb
10146 *
10147 * cstate->update_wm was already set above, so this flag will
10148 * take effect when we commit and program watermarks.
10149 */
10150 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10151 needs_scaling(to_intel_plane_state(plane_state)) &&
10152 !needs_scaling(old_plane_state))
10153 pipe_config->disable_lp_wm = true;
10154
10155 return 0;
10156 }
10157
10158 static bool encoders_cloneable(const struct intel_encoder *a,
10159 const struct intel_encoder *b)
10160 {
10161 /* masks could be asymmetric, so check both ways */
10162 return a == b || (a->cloneable & (1 << b->type) &&
10163 b->cloneable & (1 << a->type));
10164 }
10165
10166 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10167 struct intel_crtc *crtc,
10168 struct intel_encoder *encoder)
10169 {
10170 struct intel_encoder *source_encoder;
10171 struct drm_connector *connector;
10172 struct drm_connector_state *connector_state;
10173 int i;
10174
10175 for_each_new_connector_in_state(state, connector, connector_state, i) {
10176 if (connector_state->crtc != &crtc->base)
10177 continue;
10178
10179 source_encoder =
10180 to_intel_encoder(connector_state->best_encoder);
10181 if (!encoders_cloneable(encoder, source_encoder))
10182 return false;
10183 }
10184
10185 return true;
10186 }
10187
10188 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10189 struct drm_crtc_state *crtc_state)
10190 {
10191 struct drm_device *dev = crtc->dev;
10192 struct drm_i915_private *dev_priv = to_i915(dev);
10193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10194 struct intel_crtc_state *pipe_config =
10195 to_intel_crtc_state(crtc_state);
10196 struct drm_atomic_state *state = crtc_state->state;
10197 int ret;
10198 bool mode_changed = needs_modeset(crtc_state);
10199
10200 if (mode_changed && !crtc_state->active)
10201 pipe_config->update_wm_post = true;
10202
10203 if (mode_changed && crtc_state->enable &&
10204 dev_priv->display.crtc_compute_clock &&
10205 !WARN_ON(pipe_config->shared_dpll)) {
10206 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10207 pipe_config);
10208 if (ret)
10209 return ret;
10210 }
10211
10212 if (crtc_state->color_mgmt_changed) {
10213 ret = intel_color_check(crtc, crtc_state);
10214 if (ret)
10215 return ret;
10216
10217 /*
10218 * Changing color management on Intel hardware is
10219 * handled as part of planes update.
10220 */
10221 crtc_state->planes_changed = true;
10222 }
10223
10224 ret = 0;
10225 if (dev_priv->display.compute_pipe_wm) {
10226 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10227 if (ret) {
10228 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10229 return ret;
10230 }
10231 }
10232
10233 if (dev_priv->display.compute_intermediate_wm &&
10234 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10235 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10236 return 0;
10237
10238 /*
10239 * Calculate 'intermediate' watermarks that satisfy both the
10240 * old state and the new state. We can program these
10241 * immediately.
10242 */
10243 ret = dev_priv->display.compute_intermediate_wm(dev,
10244 intel_crtc,
10245 pipe_config);
10246 if (ret) {
10247 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10248 return ret;
10249 }
10250 } else if (dev_priv->display.compute_intermediate_wm) {
10251 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10252 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10253 }
10254
10255 if (INTEL_GEN(dev_priv) >= 9) {
10256 if (mode_changed)
10257 ret = skl_update_scaler_crtc(pipe_config);
10258
10259 if (!ret)
10260 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10261 pipe_config);
10262 if (!ret)
10263 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10264 pipe_config);
10265 }
10266
10267 return ret;
10268 }
10269
10270 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10271 .atomic_begin = intel_begin_crtc_commit,
10272 .atomic_flush = intel_finish_crtc_commit,
10273 .atomic_check = intel_crtc_atomic_check,
10274 };
10275
10276 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10277 {
10278 struct intel_connector *connector;
10279 struct drm_connector_list_iter conn_iter;
10280
10281 drm_connector_list_iter_begin(dev, &conn_iter);
10282 for_each_intel_connector_iter(connector, &conn_iter) {
10283 if (connector->base.state->crtc)
10284 drm_connector_unreference(&connector->base);
10285
10286 if (connector->base.encoder) {
10287 connector->base.state->best_encoder =
10288 connector->base.encoder;
10289 connector->base.state->crtc =
10290 connector->base.encoder->crtc;
10291
10292 drm_connector_reference(&connector->base);
10293 } else {
10294 connector->base.state->best_encoder = NULL;
10295 connector->base.state->crtc = NULL;
10296 }
10297 }
10298 drm_connector_list_iter_end(&conn_iter);
10299 }
10300
10301 static void
10302 connected_sink_compute_bpp(struct intel_connector *connector,
10303 struct intel_crtc_state *pipe_config)
10304 {
10305 const struct drm_display_info *info = &connector->base.display_info;
10306 int bpp = pipe_config->pipe_bpp;
10307
10308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10309 connector->base.base.id,
10310 connector->base.name);
10311
10312 /* Don't use an invalid EDID bpc value */
10313 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10314 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10315 bpp, info->bpc * 3);
10316 pipe_config->pipe_bpp = info->bpc * 3;
10317 }
10318
10319 /* Clamp bpp to 8 on screens without EDID 1.4 */
10320 if (info->bpc == 0 && bpp > 24) {
10321 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10322 bpp);
10323 pipe_config->pipe_bpp = 24;
10324 }
10325 }
10326
10327 static int
10328 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10329 struct intel_crtc_state *pipe_config)
10330 {
10331 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10332 struct drm_atomic_state *state;
10333 struct drm_connector *connector;
10334 struct drm_connector_state *connector_state;
10335 int bpp, i;
10336
10337 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10338 IS_CHERRYVIEW(dev_priv)))
10339 bpp = 10*3;
10340 else if (INTEL_GEN(dev_priv) >= 5)
10341 bpp = 12*3;
10342 else
10343 bpp = 8*3;
10344
10345
10346 pipe_config->pipe_bpp = bpp;
10347
10348 state = pipe_config->base.state;
10349
10350 /* Clamp display bpp to EDID value */
10351 for_each_new_connector_in_state(state, connector, connector_state, i) {
10352 if (connector_state->crtc != &crtc->base)
10353 continue;
10354
10355 connected_sink_compute_bpp(to_intel_connector(connector),
10356 pipe_config);
10357 }
10358
10359 return bpp;
10360 }
10361
10362 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10363 {
10364 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10365 "type: 0x%x flags: 0x%x\n",
10366 mode->crtc_clock,
10367 mode->crtc_hdisplay, mode->crtc_hsync_start,
10368 mode->crtc_hsync_end, mode->crtc_htotal,
10369 mode->crtc_vdisplay, mode->crtc_vsync_start,
10370 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10371 }
10372
10373 static inline void
10374 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10375 unsigned int lane_count, struct intel_link_m_n *m_n)
10376 {
10377 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10378 id, lane_count,
10379 m_n->gmch_m, m_n->gmch_n,
10380 m_n->link_m, m_n->link_n, m_n->tu);
10381 }
10382
10383 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10384 struct intel_crtc_state *pipe_config,
10385 const char *context)
10386 {
10387 struct drm_device *dev = crtc->base.dev;
10388 struct drm_i915_private *dev_priv = to_i915(dev);
10389 struct drm_plane *plane;
10390 struct intel_plane *intel_plane;
10391 struct intel_plane_state *state;
10392 struct drm_framebuffer *fb;
10393
10394 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10395 crtc->base.base.id, crtc->base.name, context);
10396
10397 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10398 transcoder_name(pipe_config->cpu_transcoder),
10399 pipe_config->pipe_bpp, pipe_config->dither);
10400
10401 if (pipe_config->has_pch_encoder)
10402 intel_dump_m_n_config(pipe_config, "fdi",
10403 pipe_config->fdi_lanes,
10404 &pipe_config->fdi_m_n);
10405
10406 if (intel_crtc_has_dp_encoder(pipe_config)) {
10407 intel_dump_m_n_config(pipe_config, "dp m_n",
10408 pipe_config->lane_count, &pipe_config->dp_m_n);
10409 if (pipe_config->has_drrs)
10410 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10411 pipe_config->lane_count,
10412 &pipe_config->dp_m2_n2);
10413 }
10414
10415 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10416 pipe_config->has_audio, pipe_config->has_infoframe);
10417
10418 DRM_DEBUG_KMS("requested mode:\n");
10419 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10420 DRM_DEBUG_KMS("adjusted mode:\n");
10421 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10422 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10423 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10424 pipe_config->port_clock,
10425 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10426 pipe_config->pixel_rate);
10427
10428 if (INTEL_GEN(dev_priv) >= 9)
10429 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10430 crtc->num_scalers,
10431 pipe_config->scaler_state.scaler_users,
10432 pipe_config->scaler_state.scaler_id);
10433
10434 if (HAS_GMCH_DISPLAY(dev_priv))
10435 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10436 pipe_config->gmch_pfit.control,
10437 pipe_config->gmch_pfit.pgm_ratios,
10438 pipe_config->gmch_pfit.lvds_border_bits);
10439 else
10440 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10441 pipe_config->pch_pfit.pos,
10442 pipe_config->pch_pfit.size,
10443 enableddisabled(pipe_config->pch_pfit.enabled));
10444
10445 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10446 pipe_config->ips_enabled, pipe_config->double_wide);
10447
10448 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10449
10450 DRM_DEBUG_KMS("planes on this crtc\n");
10451 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10452 struct drm_format_name_buf format_name;
10453 intel_plane = to_intel_plane(plane);
10454 if (intel_plane->pipe != crtc->pipe)
10455 continue;
10456
10457 state = to_intel_plane_state(plane->state);
10458 fb = state->base.fb;
10459 if (!fb) {
10460 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10461 plane->base.id, plane->name, state->scaler_id);
10462 continue;
10463 }
10464
10465 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10466 plane->base.id, plane->name,
10467 fb->base.id, fb->width, fb->height,
10468 drm_get_format_name(fb->format->format, &format_name));
10469 if (INTEL_GEN(dev_priv) >= 9)
10470 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10471 state->scaler_id,
10472 state->base.src.x1 >> 16,
10473 state->base.src.y1 >> 16,
10474 drm_rect_width(&state->base.src) >> 16,
10475 drm_rect_height(&state->base.src) >> 16,
10476 state->base.dst.x1, state->base.dst.y1,
10477 drm_rect_width(&state->base.dst),
10478 drm_rect_height(&state->base.dst));
10479 }
10480 }
10481
10482 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10483 {
10484 struct drm_device *dev = state->dev;
10485 struct drm_connector *connector;
10486 struct drm_connector_list_iter conn_iter;
10487 unsigned int used_ports = 0;
10488 unsigned int used_mst_ports = 0;
10489
10490 /*
10491 * Walk the connector list instead of the encoder
10492 * list to detect the problem on ddi platforms
10493 * where there's just one encoder per digital port.
10494 */
10495 drm_connector_list_iter_begin(dev, &conn_iter);
10496 drm_for_each_connector_iter(connector, &conn_iter) {
10497 struct drm_connector_state *connector_state;
10498 struct intel_encoder *encoder;
10499
10500 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10501 if (!connector_state)
10502 connector_state = connector->state;
10503
10504 if (!connector_state->best_encoder)
10505 continue;
10506
10507 encoder = to_intel_encoder(connector_state->best_encoder);
10508
10509 WARN_ON(!connector_state->crtc);
10510
10511 switch (encoder->type) {
10512 unsigned int port_mask;
10513 case INTEL_OUTPUT_UNKNOWN:
10514 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10515 break;
10516 case INTEL_OUTPUT_DP:
10517 case INTEL_OUTPUT_HDMI:
10518 case INTEL_OUTPUT_EDP:
10519 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10520
10521 /* the same port mustn't appear more than once */
10522 if (used_ports & port_mask)
10523 return false;
10524
10525 used_ports |= port_mask;
10526 break;
10527 case INTEL_OUTPUT_DP_MST:
10528 used_mst_ports |=
10529 1 << enc_to_mst(&encoder->base)->primary->port;
10530 break;
10531 default:
10532 break;
10533 }
10534 }
10535 drm_connector_list_iter_end(&conn_iter);
10536
10537 /* can't mix MST and SST/HDMI on the same port */
10538 if (used_ports & used_mst_ports)
10539 return false;
10540
10541 return true;
10542 }
10543
10544 static void
10545 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10546 {
10547 struct drm_i915_private *dev_priv =
10548 to_i915(crtc_state->base.crtc->dev);
10549 struct intel_crtc_scaler_state scaler_state;
10550 struct intel_dpll_hw_state dpll_hw_state;
10551 struct intel_shared_dpll *shared_dpll;
10552 struct intel_crtc_wm_state wm_state;
10553 bool force_thru;
10554
10555 /* FIXME: before the switch to atomic started, a new pipe_config was
10556 * kzalloc'd. Code that depends on any field being zero should be
10557 * fixed, so that the crtc_state can be safely duplicated. For now,
10558 * only fields that are know to not cause problems are preserved. */
10559
10560 scaler_state = crtc_state->scaler_state;
10561 shared_dpll = crtc_state->shared_dpll;
10562 dpll_hw_state = crtc_state->dpll_hw_state;
10563 force_thru = crtc_state->pch_pfit.force_thru;
10564 if (IS_G4X(dev_priv) ||
10565 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10566 wm_state = crtc_state->wm;
10567
10568 /* Keep base drm_crtc_state intact, only clear our extended struct */
10569 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10570 memset(&crtc_state->base + 1, 0,
10571 sizeof(*crtc_state) - sizeof(crtc_state->base));
10572
10573 crtc_state->scaler_state = scaler_state;
10574 crtc_state->shared_dpll = shared_dpll;
10575 crtc_state->dpll_hw_state = dpll_hw_state;
10576 crtc_state->pch_pfit.force_thru = force_thru;
10577 if (IS_G4X(dev_priv) ||
10578 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10579 crtc_state->wm = wm_state;
10580 }
10581
10582 static int
10583 intel_modeset_pipe_config(struct drm_crtc *crtc,
10584 struct intel_crtc_state *pipe_config)
10585 {
10586 struct drm_atomic_state *state = pipe_config->base.state;
10587 struct intel_encoder *encoder;
10588 struct drm_connector *connector;
10589 struct drm_connector_state *connector_state;
10590 int base_bpp, ret = -EINVAL;
10591 int i;
10592 bool retry = true;
10593
10594 clear_intel_crtc_state(pipe_config);
10595
10596 pipe_config->cpu_transcoder =
10597 (enum transcoder) to_intel_crtc(crtc)->pipe;
10598
10599 /*
10600 * Sanitize sync polarity flags based on requested ones. If neither
10601 * positive or negative polarity is requested, treat this as meaning
10602 * negative polarity.
10603 */
10604 if (!(pipe_config->base.adjusted_mode.flags &
10605 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10606 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10607
10608 if (!(pipe_config->base.adjusted_mode.flags &
10609 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10610 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10611
10612 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10613 pipe_config);
10614 if (base_bpp < 0)
10615 goto fail;
10616
10617 /*
10618 * Determine the real pipe dimensions. Note that stereo modes can
10619 * increase the actual pipe size due to the frame doubling and
10620 * insertion of additional space for blanks between the frame. This
10621 * is stored in the crtc timings. We use the requested mode to do this
10622 * computation to clearly distinguish it from the adjusted mode, which
10623 * can be changed by the connectors in the below retry loop.
10624 */
10625 drm_mode_get_hv_timing(&pipe_config->base.mode,
10626 &pipe_config->pipe_src_w,
10627 &pipe_config->pipe_src_h);
10628
10629 for_each_new_connector_in_state(state, connector, connector_state, i) {
10630 if (connector_state->crtc != crtc)
10631 continue;
10632
10633 encoder = to_intel_encoder(connector_state->best_encoder);
10634
10635 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10636 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10637 goto fail;
10638 }
10639
10640 /*
10641 * Determine output_types before calling the .compute_config()
10642 * hooks so that the hooks can use this information safely.
10643 */
10644 pipe_config->output_types |= 1 << encoder->type;
10645 }
10646
10647 encoder_retry:
10648 /* Ensure the port clock defaults are reset when retrying. */
10649 pipe_config->port_clock = 0;
10650 pipe_config->pixel_multiplier = 1;
10651
10652 /* Fill in default crtc timings, allow encoders to overwrite them. */
10653 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10654 CRTC_STEREO_DOUBLE);
10655
10656 /* Pass our mode to the connectors and the CRTC to give them a chance to
10657 * adjust it according to limitations or connector properties, and also
10658 * a chance to reject the mode entirely.
10659 */
10660 for_each_new_connector_in_state(state, connector, connector_state, i) {
10661 if (connector_state->crtc != crtc)
10662 continue;
10663
10664 encoder = to_intel_encoder(connector_state->best_encoder);
10665
10666 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10667 DRM_DEBUG_KMS("Encoder config failure\n");
10668 goto fail;
10669 }
10670 }
10671
10672 /* Set default port clock if not overwritten by the encoder. Needs to be
10673 * done afterwards in case the encoder adjusts the mode. */
10674 if (!pipe_config->port_clock)
10675 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10676 * pipe_config->pixel_multiplier;
10677
10678 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10679 if (ret < 0) {
10680 DRM_DEBUG_KMS("CRTC fixup failed\n");
10681 goto fail;
10682 }
10683
10684 if (ret == RETRY) {
10685 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10686 ret = -EINVAL;
10687 goto fail;
10688 }
10689
10690 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10691 retry = false;
10692 goto encoder_retry;
10693 }
10694
10695 /* Dithering seems to not pass-through bits correctly when it should, so
10696 * only enable it on 6bpc panels and when its not a compliance
10697 * test requesting 6bpc video pattern.
10698 */
10699 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10700 !pipe_config->dither_force_disable;
10701 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10702 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10703
10704 fail:
10705 return ret;
10706 }
10707
10708 static void
10709 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10710 {
10711 struct drm_crtc *crtc;
10712 struct drm_crtc_state *new_crtc_state;
10713 int i;
10714
10715 /* Double check state. */
10716 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10717 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10718
10719 /*
10720 * Update legacy state to satisfy fbc code. This can
10721 * be removed when fbc uses the atomic state.
10722 */
10723 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10724 struct drm_plane_state *plane_state = crtc->primary->state;
10725
10726 crtc->primary->fb = plane_state->fb;
10727 crtc->x = plane_state->src_x >> 16;
10728 crtc->y = plane_state->src_y >> 16;
10729 }
10730 }
10731 }
10732
10733 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10734 {
10735 int diff;
10736
10737 if (clock1 == clock2)
10738 return true;
10739
10740 if (!clock1 || !clock2)
10741 return false;
10742
10743 diff = abs(clock1 - clock2);
10744
10745 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10746 return true;
10747
10748 return false;
10749 }
10750
10751 static bool
10752 intel_compare_m_n(unsigned int m, unsigned int n,
10753 unsigned int m2, unsigned int n2,
10754 bool exact)
10755 {
10756 if (m == m2 && n == n2)
10757 return true;
10758
10759 if (exact || !m || !n || !m2 || !n2)
10760 return false;
10761
10762 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
10763
10764 if (n > n2) {
10765 while (n > n2) {
10766 m2 <<= 1;
10767 n2 <<= 1;
10768 }
10769 } else if (n < n2) {
10770 while (n < n2) {
10771 m <<= 1;
10772 n <<= 1;
10773 }
10774 }
10775
10776 if (n != n2)
10777 return false;
10778
10779 return intel_fuzzy_clock_check(m, m2);
10780 }
10781
10782 static bool
10783 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
10784 struct intel_link_m_n *m2_n2,
10785 bool adjust)
10786 {
10787 if (m_n->tu == m2_n2->tu &&
10788 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
10789 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
10790 intel_compare_m_n(m_n->link_m, m_n->link_n,
10791 m2_n2->link_m, m2_n2->link_n, !adjust)) {
10792 if (adjust)
10793 *m2_n2 = *m_n;
10794
10795 return true;
10796 }
10797
10798 return false;
10799 }
10800
10801 static void __printf(3, 4)
10802 pipe_config_err(bool adjust, const char *name, const char *format, ...)
10803 {
10804 char *level;
10805 unsigned int category;
10806 struct va_format vaf;
10807 va_list args;
10808
10809 if (adjust) {
10810 level = KERN_DEBUG;
10811 category = DRM_UT_KMS;
10812 } else {
10813 level = KERN_ERR;
10814 category = DRM_UT_NONE;
10815 }
10816
10817 va_start(args, format);
10818 vaf.fmt = format;
10819 vaf.va = &args;
10820
10821 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
10822
10823 va_end(args);
10824 }
10825
10826 static bool
10827 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
10828 struct intel_crtc_state *current_config,
10829 struct intel_crtc_state *pipe_config,
10830 bool adjust)
10831 {
10832 bool ret = true;
10833
10834 #define PIPE_CONF_CHECK_X(name) \
10835 if (current_config->name != pipe_config->name) { \
10836 pipe_config_err(adjust, __stringify(name), \
10837 "(expected 0x%08x, found 0x%08x)\n", \
10838 current_config->name, \
10839 pipe_config->name); \
10840 ret = false; \
10841 }
10842
10843 #define PIPE_CONF_CHECK_I(name) \
10844 if (current_config->name != pipe_config->name) { \
10845 pipe_config_err(adjust, __stringify(name), \
10846 "(expected %i, found %i)\n", \
10847 current_config->name, \
10848 pipe_config->name); \
10849 ret = false; \
10850 }
10851
10852 #define PIPE_CONF_CHECK_P(name) \
10853 if (current_config->name != pipe_config->name) { \
10854 pipe_config_err(adjust, __stringify(name), \
10855 "(expected %p, found %p)\n", \
10856 current_config->name, \
10857 pipe_config->name); \
10858 ret = false; \
10859 }
10860
10861 #define PIPE_CONF_CHECK_M_N(name) \
10862 if (!intel_compare_link_m_n(&current_config->name, \
10863 &pipe_config->name,\
10864 adjust)) { \
10865 pipe_config_err(adjust, __stringify(name), \
10866 "(expected tu %i gmch %i/%i link %i/%i, " \
10867 "found tu %i, gmch %i/%i link %i/%i)\n", \
10868 current_config->name.tu, \
10869 current_config->name.gmch_m, \
10870 current_config->name.gmch_n, \
10871 current_config->name.link_m, \
10872 current_config->name.link_n, \
10873 pipe_config->name.tu, \
10874 pipe_config->name.gmch_m, \
10875 pipe_config->name.gmch_n, \
10876 pipe_config->name.link_m, \
10877 pipe_config->name.link_n); \
10878 ret = false; \
10879 }
10880
10881 /* This is required for BDW+ where there is only one set of registers for
10882 * switching between high and low RR.
10883 * This macro can be used whenever a comparison has to be made between one
10884 * hw state and multiple sw state variables.
10885 */
10886 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
10887 if (!intel_compare_link_m_n(&current_config->name, \
10888 &pipe_config->name, adjust) && \
10889 !intel_compare_link_m_n(&current_config->alt_name, \
10890 &pipe_config->name, adjust)) { \
10891 pipe_config_err(adjust, __stringify(name), \
10892 "(expected tu %i gmch %i/%i link %i/%i, " \
10893 "or tu %i gmch %i/%i link %i/%i, " \
10894 "found tu %i, gmch %i/%i link %i/%i)\n", \
10895 current_config->name.tu, \
10896 current_config->name.gmch_m, \
10897 current_config->name.gmch_n, \
10898 current_config->name.link_m, \
10899 current_config->name.link_n, \
10900 current_config->alt_name.tu, \
10901 current_config->alt_name.gmch_m, \
10902 current_config->alt_name.gmch_n, \
10903 current_config->alt_name.link_m, \
10904 current_config->alt_name.link_n, \
10905 pipe_config->name.tu, \
10906 pipe_config->name.gmch_m, \
10907 pipe_config->name.gmch_n, \
10908 pipe_config->name.link_m, \
10909 pipe_config->name.link_n); \
10910 ret = false; \
10911 }
10912
10913 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10914 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10915 pipe_config_err(adjust, __stringify(name), \
10916 "(%x) (expected %i, found %i)\n", \
10917 (mask), \
10918 current_config->name & (mask), \
10919 pipe_config->name & (mask)); \
10920 ret = false; \
10921 }
10922
10923 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10924 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10925 pipe_config_err(adjust, __stringify(name), \
10926 "(expected %i, found %i)\n", \
10927 current_config->name, \
10928 pipe_config->name); \
10929 ret = false; \
10930 }
10931
10932 #define PIPE_CONF_QUIRK(quirk) \
10933 ((current_config->quirks | pipe_config->quirks) & (quirk))
10934
10935 PIPE_CONF_CHECK_I(cpu_transcoder);
10936
10937 PIPE_CONF_CHECK_I(has_pch_encoder);
10938 PIPE_CONF_CHECK_I(fdi_lanes);
10939 PIPE_CONF_CHECK_M_N(fdi_m_n);
10940
10941 PIPE_CONF_CHECK_I(lane_count);
10942 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
10943
10944 if (INTEL_GEN(dev_priv) < 8) {
10945 PIPE_CONF_CHECK_M_N(dp_m_n);
10946
10947 if (current_config->has_drrs)
10948 PIPE_CONF_CHECK_M_N(dp_m2_n2);
10949 } else
10950 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
10951
10952 PIPE_CONF_CHECK_X(output_types);
10953
10954 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10955 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10956 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10957 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10958 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10959 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10960
10961 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10962 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10963 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10964 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10965 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10966 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10967
10968 PIPE_CONF_CHECK_I(pixel_multiplier);
10969 PIPE_CONF_CHECK_I(has_hdmi_sink);
10970 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
10971 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10972 PIPE_CONF_CHECK_I(limited_color_range);
10973
10974 PIPE_CONF_CHECK_I(hdmi_scrambling);
10975 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
10976 PIPE_CONF_CHECK_I(has_infoframe);
10977
10978 PIPE_CONF_CHECK_I(has_audio);
10979
10980 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10981 DRM_MODE_FLAG_INTERLACE);
10982
10983 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10984 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10985 DRM_MODE_FLAG_PHSYNC);
10986 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10987 DRM_MODE_FLAG_NHSYNC);
10988 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10989 DRM_MODE_FLAG_PVSYNC);
10990 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10991 DRM_MODE_FLAG_NVSYNC);
10992 }
10993
10994 PIPE_CONF_CHECK_X(gmch_pfit.control);
10995 /* pfit ratios are autocomputed by the hw on gen4+ */
10996 if (INTEL_GEN(dev_priv) < 4)
10997 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
10998 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
10999
11000 if (!adjust) {
11001 PIPE_CONF_CHECK_I(pipe_src_w);
11002 PIPE_CONF_CHECK_I(pipe_src_h);
11003
11004 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11005 if (current_config->pch_pfit.enabled) {
11006 PIPE_CONF_CHECK_X(pch_pfit.pos);
11007 PIPE_CONF_CHECK_X(pch_pfit.size);
11008 }
11009
11010 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11011 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11012 }
11013
11014 /* BDW+ don't expose a synchronous way to read the state */
11015 if (IS_HASWELL(dev_priv))
11016 PIPE_CONF_CHECK_I(ips_enabled);
11017
11018 PIPE_CONF_CHECK_I(double_wide);
11019
11020 PIPE_CONF_CHECK_P(shared_dpll);
11021 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11022 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11023 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11024 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11025 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11026 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11027 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11028 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11029 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11030
11031 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11032 PIPE_CONF_CHECK_X(dsi_pll.div);
11033
11034 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11035 PIPE_CONF_CHECK_I(pipe_bpp);
11036
11037 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11038 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11039
11040 #undef PIPE_CONF_CHECK_X
11041 #undef PIPE_CONF_CHECK_I
11042 #undef PIPE_CONF_CHECK_P
11043 #undef PIPE_CONF_CHECK_FLAGS
11044 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11045 #undef PIPE_CONF_QUIRK
11046
11047 return ret;
11048 }
11049
11050 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11051 const struct intel_crtc_state *pipe_config)
11052 {
11053 if (pipe_config->has_pch_encoder) {
11054 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11055 &pipe_config->fdi_m_n);
11056 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11057
11058 /*
11059 * FDI already provided one idea for the dotclock.
11060 * Yell if the encoder disagrees.
11061 */
11062 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11063 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11064 fdi_dotclock, dotclock);
11065 }
11066 }
11067
11068 static void verify_wm_state(struct drm_crtc *crtc,
11069 struct drm_crtc_state *new_state)
11070 {
11071 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11072 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11073 struct skl_pipe_wm hw_wm, *sw_wm;
11074 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11075 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11077 const enum pipe pipe = intel_crtc->pipe;
11078 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11079
11080 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11081 return;
11082
11083 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11084 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11085
11086 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11087 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11088
11089 /* planes */
11090 for_each_universal_plane(dev_priv, pipe, plane) {
11091 hw_plane_wm = &hw_wm.planes[plane];
11092 sw_plane_wm = &sw_wm->planes[plane];
11093
11094 /* Watermarks */
11095 for (level = 0; level <= max_level; level++) {
11096 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11097 &sw_plane_wm->wm[level]))
11098 continue;
11099
11100 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11101 pipe_name(pipe), plane + 1, level,
11102 sw_plane_wm->wm[level].plane_en,
11103 sw_plane_wm->wm[level].plane_res_b,
11104 sw_plane_wm->wm[level].plane_res_l,
11105 hw_plane_wm->wm[level].plane_en,
11106 hw_plane_wm->wm[level].plane_res_b,
11107 hw_plane_wm->wm[level].plane_res_l);
11108 }
11109
11110 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11111 &sw_plane_wm->trans_wm)) {
11112 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11113 pipe_name(pipe), plane + 1,
11114 sw_plane_wm->trans_wm.plane_en,
11115 sw_plane_wm->trans_wm.plane_res_b,
11116 sw_plane_wm->trans_wm.plane_res_l,
11117 hw_plane_wm->trans_wm.plane_en,
11118 hw_plane_wm->trans_wm.plane_res_b,
11119 hw_plane_wm->trans_wm.plane_res_l);
11120 }
11121
11122 /* DDB */
11123 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11124 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11125
11126 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11127 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11128 pipe_name(pipe), plane + 1,
11129 sw_ddb_entry->start, sw_ddb_entry->end,
11130 hw_ddb_entry->start, hw_ddb_entry->end);
11131 }
11132 }
11133
11134 /*
11135 * cursor
11136 * If the cursor plane isn't active, we may not have updated it's ddb
11137 * allocation. In that case since the ddb allocation will be updated
11138 * once the plane becomes visible, we can skip this check
11139 */
11140 if (1) {
11141 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11142 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11143
11144 /* Watermarks */
11145 for (level = 0; level <= max_level; level++) {
11146 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11147 &sw_plane_wm->wm[level]))
11148 continue;
11149
11150 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11151 pipe_name(pipe), level,
11152 sw_plane_wm->wm[level].plane_en,
11153 sw_plane_wm->wm[level].plane_res_b,
11154 sw_plane_wm->wm[level].plane_res_l,
11155 hw_plane_wm->wm[level].plane_en,
11156 hw_plane_wm->wm[level].plane_res_b,
11157 hw_plane_wm->wm[level].plane_res_l);
11158 }
11159
11160 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11161 &sw_plane_wm->trans_wm)) {
11162 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11163 pipe_name(pipe),
11164 sw_plane_wm->trans_wm.plane_en,
11165 sw_plane_wm->trans_wm.plane_res_b,
11166 sw_plane_wm->trans_wm.plane_res_l,
11167 hw_plane_wm->trans_wm.plane_en,
11168 hw_plane_wm->trans_wm.plane_res_b,
11169 hw_plane_wm->trans_wm.plane_res_l);
11170 }
11171
11172 /* DDB */
11173 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11174 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11175
11176 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11177 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11178 pipe_name(pipe),
11179 sw_ddb_entry->start, sw_ddb_entry->end,
11180 hw_ddb_entry->start, hw_ddb_entry->end);
11181 }
11182 }
11183 }
11184
11185 static void
11186 verify_connector_state(struct drm_device *dev,
11187 struct drm_atomic_state *state,
11188 struct drm_crtc *crtc)
11189 {
11190 struct drm_connector *connector;
11191 struct drm_connector_state *new_conn_state;
11192 int i;
11193
11194 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11195 struct drm_encoder *encoder = connector->encoder;
11196 struct drm_crtc_state *crtc_state = NULL;
11197
11198 if (new_conn_state->crtc != crtc)
11199 continue;
11200
11201 if (crtc)
11202 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11203
11204 intel_connector_verify_state(crtc_state, new_conn_state);
11205
11206 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11207 "connector's atomic encoder doesn't match legacy encoder\n");
11208 }
11209 }
11210
11211 static void
11212 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11213 {
11214 struct intel_encoder *encoder;
11215 struct drm_connector *connector;
11216 struct drm_connector_state *old_conn_state, *new_conn_state;
11217 int i;
11218
11219 for_each_intel_encoder(dev, encoder) {
11220 bool enabled = false, found = false;
11221 enum pipe pipe;
11222
11223 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11224 encoder->base.base.id,
11225 encoder->base.name);
11226
11227 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11228 new_conn_state, i) {
11229 if (old_conn_state->best_encoder == &encoder->base)
11230 found = true;
11231
11232 if (new_conn_state->best_encoder != &encoder->base)
11233 continue;
11234 found = enabled = true;
11235
11236 I915_STATE_WARN(new_conn_state->crtc !=
11237 encoder->base.crtc,
11238 "connector's crtc doesn't match encoder crtc\n");
11239 }
11240
11241 if (!found)
11242 continue;
11243
11244 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11245 "encoder's enabled state mismatch "
11246 "(expected %i, found %i)\n",
11247 !!encoder->base.crtc, enabled);
11248
11249 if (!encoder->base.crtc) {
11250 bool active;
11251
11252 active = encoder->get_hw_state(encoder, &pipe);
11253 I915_STATE_WARN(active,
11254 "encoder detached but still enabled on pipe %c.\n",
11255 pipe_name(pipe));
11256 }
11257 }
11258 }
11259
11260 static void
11261 verify_crtc_state(struct drm_crtc *crtc,
11262 struct drm_crtc_state *old_crtc_state,
11263 struct drm_crtc_state *new_crtc_state)
11264 {
11265 struct drm_device *dev = crtc->dev;
11266 struct drm_i915_private *dev_priv = to_i915(dev);
11267 struct intel_encoder *encoder;
11268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11269 struct intel_crtc_state *pipe_config, *sw_config;
11270 struct drm_atomic_state *old_state;
11271 bool active;
11272
11273 old_state = old_crtc_state->state;
11274 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11275 pipe_config = to_intel_crtc_state(old_crtc_state);
11276 memset(pipe_config, 0, sizeof(*pipe_config));
11277 pipe_config->base.crtc = crtc;
11278 pipe_config->base.state = old_state;
11279
11280 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11281
11282 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11283
11284 /* we keep both pipes enabled on 830 */
11285 if (IS_I830(dev_priv))
11286 active = new_crtc_state->active;
11287
11288 I915_STATE_WARN(new_crtc_state->active != active,
11289 "crtc active state doesn't match with hw state "
11290 "(expected %i, found %i)\n", new_crtc_state->active, active);
11291
11292 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11293 "transitional active state does not match atomic hw state "
11294 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11295
11296 for_each_encoder_on_crtc(dev, crtc, encoder) {
11297 enum pipe pipe;
11298
11299 active = encoder->get_hw_state(encoder, &pipe);
11300 I915_STATE_WARN(active != new_crtc_state->active,
11301 "[ENCODER:%i] active %i with crtc active %i\n",
11302 encoder->base.base.id, active, new_crtc_state->active);
11303
11304 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11305 "Encoder connected to wrong pipe %c\n",
11306 pipe_name(pipe));
11307
11308 if (active) {
11309 pipe_config->output_types |= 1 << encoder->type;
11310 encoder->get_config(encoder, pipe_config);
11311 }
11312 }
11313
11314 intel_crtc_compute_pixel_rate(pipe_config);
11315
11316 if (!new_crtc_state->active)
11317 return;
11318
11319 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11320
11321 sw_config = to_intel_crtc_state(new_crtc_state);
11322 if (!intel_pipe_config_compare(dev_priv, sw_config,
11323 pipe_config, false)) {
11324 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11325 intel_dump_pipe_config(intel_crtc, pipe_config,
11326 "[hw state]");
11327 intel_dump_pipe_config(intel_crtc, sw_config,
11328 "[sw state]");
11329 }
11330 }
11331
11332 static void
11333 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11334 struct intel_shared_dpll *pll,
11335 struct drm_crtc *crtc,
11336 struct drm_crtc_state *new_state)
11337 {
11338 struct intel_dpll_hw_state dpll_hw_state;
11339 unsigned crtc_mask;
11340 bool active;
11341
11342 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11343
11344 DRM_DEBUG_KMS("%s\n", pll->name);
11345
11346 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11347
11348 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11349 I915_STATE_WARN(!pll->on && pll->active_mask,
11350 "pll in active use but not on in sw tracking\n");
11351 I915_STATE_WARN(pll->on && !pll->active_mask,
11352 "pll is on but not used by any active crtc\n");
11353 I915_STATE_WARN(pll->on != active,
11354 "pll on state mismatch (expected %i, found %i)\n",
11355 pll->on, active);
11356 }
11357
11358 if (!crtc) {
11359 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11360 "more active pll users than references: %x vs %x\n",
11361 pll->active_mask, pll->state.crtc_mask);
11362
11363 return;
11364 }
11365
11366 crtc_mask = 1 << drm_crtc_index(crtc);
11367
11368 if (new_state->active)
11369 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11370 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11371 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11372 else
11373 I915_STATE_WARN(pll->active_mask & crtc_mask,
11374 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11375 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11376
11377 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11378 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11379 crtc_mask, pll->state.crtc_mask);
11380
11381 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11382 &dpll_hw_state,
11383 sizeof(dpll_hw_state)),
11384 "pll hw state mismatch\n");
11385 }
11386
11387 static void
11388 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11389 struct drm_crtc_state *old_crtc_state,
11390 struct drm_crtc_state *new_crtc_state)
11391 {
11392 struct drm_i915_private *dev_priv = to_i915(dev);
11393 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11394 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11395
11396 if (new_state->shared_dpll)
11397 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11398
11399 if (old_state->shared_dpll &&
11400 old_state->shared_dpll != new_state->shared_dpll) {
11401 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11402 struct intel_shared_dpll *pll = old_state->shared_dpll;
11403
11404 I915_STATE_WARN(pll->active_mask & crtc_mask,
11405 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11406 pipe_name(drm_crtc_index(crtc)));
11407 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11408 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11409 pipe_name(drm_crtc_index(crtc)));
11410 }
11411 }
11412
11413 static void
11414 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11415 struct drm_atomic_state *state,
11416 struct drm_crtc_state *old_state,
11417 struct drm_crtc_state *new_state)
11418 {
11419 if (!needs_modeset(new_state) &&
11420 !to_intel_crtc_state(new_state)->update_pipe)
11421 return;
11422
11423 verify_wm_state(crtc, new_state);
11424 verify_connector_state(crtc->dev, state, crtc);
11425 verify_crtc_state(crtc, old_state, new_state);
11426 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11427 }
11428
11429 static void
11430 verify_disabled_dpll_state(struct drm_device *dev)
11431 {
11432 struct drm_i915_private *dev_priv = to_i915(dev);
11433 int i;
11434
11435 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11436 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11437 }
11438
11439 static void
11440 intel_modeset_verify_disabled(struct drm_device *dev,
11441 struct drm_atomic_state *state)
11442 {
11443 verify_encoder_state(dev, state);
11444 verify_connector_state(dev, state, NULL);
11445 verify_disabled_dpll_state(dev);
11446 }
11447
11448 static void update_scanline_offset(struct intel_crtc *crtc)
11449 {
11450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11451
11452 /*
11453 * The scanline counter increments at the leading edge of hsync.
11454 *
11455 * On most platforms it starts counting from vtotal-1 on the
11456 * first active line. That means the scanline counter value is
11457 * always one less than what we would expect. Ie. just after
11458 * start of vblank, which also occurs at start of hsync (on the
11459 * last active line), the scanline counter will read vblank_start-1.
11460 *
11461 * On gen2 the scanline counter starts counting from 1 instead
11462 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11463 * to keep the value positive), instead of adding one.
11464 *
11465 * On HSW+ the behaviour of the scanline counter depends on the output
11466 * type. For DP ports it behaves like most other platforms, but on HDMI
11467 * there's an extra 1 line difference. So we need to add two instead of
11468 * one to the value.
11469 *
11470 * On VLV/CHV DSI the scanline counter would appear to increment
11471 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11472 * that means we can't tell whether we're in vblank or not while
11473 * we're on that particular line. We must still set scanline_offset
11474 * to 1 so that the vblank timestamps come out correct when we query
11475 * the scanline counter from within the vblank interrupt handler.
11476 * However if queried just before the start of vblank we'll get an
11477 * answer that's slightly in the future.
11478 */
11479 if (IS_GEN2(dev_priv)) {
11480 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11481 int vtotal;
11482
11483 vtotal = adjusted_mode->crtc_vtotal;
11484 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11485 vtotal /= 2;
11486
11487 crtc->scanline_offset = vtotal - 1;
11488 } else if (HAS_DDI(dev_priv) &&
11489 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11490 crtc->scanline_offset = 2;
11491 } else
11492 crtc->scanline_offset = 1;
11493 }
11494
11495 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11496 {
11497 struct drm_device *dev = state->dev;
11498 struct drm_i915_private *dev_priv = to_i915(dev);
11499 struct drm_crtc *crtc;
11500 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11501 int i;
11502
11503 if (!dev_priv->display.crtc_compute_clock)
11504 return;
11505
11506 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11508 struct intel_shared_dpll *old_dpll =
11509 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11510
11511 if (!needs_modeset(new_crtc_state))
11512 continue;
11513
11514 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11515
11516 if (!old_dpll)
11517 continue;
11518
11519 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11520 }
11521 }
11522
11523 /*
11524 * This implements the workaround described in the "notes" section of the mode
11525 * set sequence documentation. When going from no pipes or single pipe to
11526 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11527 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11528 */
11529 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11530 {
11531 struct drm_crtc_state *crtc_state;
11532 struct intel_crtc *intel_crtc;
11533 struct drm_crtc *crtc;
11534 struct intel_crtc_state *first_crtc_state = NULL;
11535 struct intel_crtc_state *other_crtc_state = NULL;
11536 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11537 int i;
11538
11539 /* look at all crtc's that are going to be enabled in during modeset */
11540 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11541 intel_crtc = to_intel_crtc(crtc);
11542
11543 if (!crtc_state->active || !needs_modeset(crtc_state))
11544 continue;
11545
11546 if (first_crtc_state) {
11547 other_crtc_state = to_intel_crtc_state(crtc_state);
11548 break;
11549 } else {
11550 first_crtc_state = to_intel_crtc_state(crtc_state);
11551 first_pipe = intel_crtc->pipe;
11552 }
11553 }
11554
11555 /* No workaround needed? */
11556 if (!first_crtc_state)
11557 return 0;
11558
11559 /* w/a possibly needed, check how many crtc's are already enabled. */
11560 for_each_intel_crtc(state->dev, intel_crtc) {
11561 struct intel_crtc_state *pipe_config;
11562
11563 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11564 if (IS_ERR(pipe_config))
11565 return PTR_ERR(pipe_config);
11566
11567 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11568
11569 if (!pipe_config->base.active ||
11570 needs_modeset(&pipe_config->base))
11571 continue;
11572
11573 /* 2 or more enabled crtcs means no need for w/a */
11574 if (enabled_pipe != INVALID_PIPE)
11575 return 0;
11576
11577 enabled_pipe = intel_crtc->pipe;
11578 }
11579
11580 if (enabled_pipe != INVALID_PIPE)
11581 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11582 else if (other_crtc_state)
11583 other_crtc_state->hsw_workaround_pipe = first_pipe;
11584
11585 return 0;
11586 }
11587
11588 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11589 {
11590 struct drm_crtc *crtc;
11591
11592 /* Add all pipes to the state */
11593 for_each_crtc(state->dev, crtc) {
11594 struct drm_crtc_state *crtc_state;
11595
11596 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11597 if (IS_ERR(crtc_state))
11598 return PTR_ERR(crtc_state);
11599 }
11600
11601 return 0;
11602 }
11603
11604 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11605 {
11606 struct drm_crtc *crtc;
11607
11608 /*
11609 * Add all pipes to the state, and force
11610 * a modeset on all the active ones.
11611 */
11612 for_each_crtc(state->dev, crtc) {
11613 struct drm_crtc_state *crtc_state;
11614 int ret;
11615
11616 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11617 if (IS_ERR(crtc_state))
11618 return PTR_ERR(crtc_state);
11619
11620 if (!crtc_state->active || needs_modeset(crtc_state))
11621 continue;
11622
11623 crtc_state->mode_changed = true;
11624
11625 ret = drm_atomic_add_affected_connectors(state, crtc);
11626 if (ret)
11627 return ret;
11628
11629 ret = drm_atomic_add_affected_planes(state, crtc);
11630 if (ret)
11631 return ret;
11632 }
11633
11634 return 0;
11635 }
11636
11637 static int intel_modeset_checks(struct drm_atomic_state *state)
11638 {
11639 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11640 struct drm_i915_private *dev_priv = to_i915(state->dev);
11641 struct drm_crtc *crtc;
11642 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11643 int ret = 0, i;
11644
11645 if (!check_digital_port_conflicts(state)) {
11646 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11647 return -EINVAL;
11648 }
11649
11650 intel_state->modeset = true;
11651 intel_state->active_crtcs = dev_priv->active_crtcs;
11652 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11653 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11654
11655 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11656 if (new_crtc_state->active)
11657 intel_state->active_crtcs |= 1 << i;
11658 else
11659 intel_state->active_crtcs &= ~(1 << i);
11660
11661 if (old_crtc_state->active != new_crtc_state->active)
11662 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11663 }
11664
11665 /*
11666 * See if the config requires any additional preparation, e.g.
11667 * to adjust global state with pipes off. We need to do this
11668 * here so we can get the modeset_pipe updated config for the new
11669 * mode set on this crtc. For other crtcs we need to use the
11670 * adjusted_mode bits in the crtc directly.
11671 */
11672 if (dev_priv->display.modeset_calc_cdclk) {
11673 ret = dev_priv->display.modeset_calc_cdclk(state);
11674 if (ret < 0)
11675 return ret;
11676
11677 /*
11678 * Writes to dev_priv->cdclk.logical must protected by
11679 * holding all the crtc locks, even if we don't end up
11680 * touching the hardware
11681 */
11682 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11683 &intel_state->cdclk.logical)) {
11684 ret = intel_lock_all_pipes(state);
11685 if (ret < 0)
11686 return ret;
11687 }
11688
11689 /* All pipes must be switched off while we change the cdclk. */
11690 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11691 &intel_state->cdclk.actual)) {
11692 ret = intel_modeset_all_pipes(state);
11693 if (ret < 0)
11694 return ret;
11695 }
11696
11697 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11698 intel_state->cdclk.logical.cdclk,
11699 intel_state->cdclk.actual.cdclk);
11700 } else {
11701 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11702 }
11703
11704 intel_modeset_clear_plls(state);
11705
11706 if (IS_HASWELL(dev_priv))
11707 return haswell_mode_set_planes_workaround(state);
11708
11709 return 0;
11710 }
11711
11712 /*
11713 * Handle calculation of various watermark data at the end of the atomic check
11714 * phase. The code here should be run after the per-crtc and per-plane 'check'
11715 * handlers to ensure that all derived state has been updated.
11716 */
11717 static int calc_watermark_data(struct drm_atomic_state *state)
11718 {
11719 struct drm_device *dev = state->dev;
11720 struct drm_i915_private *dev_priv = to_i915(dev);
11721
11722 /* Is there platform-specific watermark information to calculate? */
11723 if (dev_priv->display.compute_global_watermarks)
11724 return dev_priv->display.compute_global_watermarks(state);
11725
11726 return 0;
11727 }
11728
11729 /**
11730 * intel_atomic_check - validate state object
11731 * @dev: drm device
11732 * @state: state to validate
11733 */
11734 static int intel_atomic_check(struct drm_device *dev,
11735 struct drm_atomic_state *state)
11736 {
11737 struct drm_i915_private *dev_priv = to_i915(dev);
11738 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11739 struct drm_crtc *crtc;
11740 struct drm_crtc_state *old_crtc_state, *crtc_state;
11741 int ret, i;
11742 bool any_ms = false;
11743
11744 ret = drm_atomic_helper_check_modeset(dev, state);
11745 if (ret)
11746 return ret;
11747
11748 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
11749 struct intel_crtc_state *pipe_config =
11750 to_intel_crtc_state(crtc_state);
11751
11752 /* Catch I915_MODE_FLAG_INHERITED */
11753 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
11754 crtc_state->mode_changed = true;
11755
11756 if (!needs_modeset(crtc_state))
11757 continue;
11758
11759 if (!crtc_state->enable) {
11760 any_ms = true;
11761 continue;
11762 }
11763
11764 /* FIXME: For only active_changed we shouldn't need to do any
11765 * state recomputation at all. */
11766
11767 ret = drm_atomic_add_affected_connectors(state, crtc);
11768 if (ret)
11769 return ret;
11770
11771 ret = intel_modeset_pipe_config(crtc, pipe_config);
11772 if (ret) {
11773 intel_dump_pipe_config(to_intel_crtc(crtc),
11774 pipe_config, "[failed]");
11775 return ret;
11776 }
11777
11778 if (i915.fastboot &&
11779 intel_pipe_config_compare(dev_priv,
11780 to_intel_crtc_state(old_crtc_state),
11781 pipe_config, true)) {
11782 crtc_state->mode_changed = false;
11783 pipe_config->update_pipe = true;
11784 }
11785
11786 if (needs_modeset(crtc_state))
11787 any_ms = true;
11788
11789 ret = drm_atomic_add_affected_planes(state, crtc);
11790 if (ret)
11791 return ret;
11792
11793 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11794 needs_modeset(crtc_state) ?
11795 "[modeset]" : "[fastset]");
11796 }
11797
11798 if (any_ms) {
11799 ret = intel_modeset_checks(state);
11800
11801 if (ret)
11802 return ret;
11803 } else {
11804 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11805 }
11806
11807 ret = drm_atomic_helper_check_planes(dev, state);
11808 if (ret)
11809 return ret;
11810
11811 intel_fbc_choose_crtc(dev_priv, state);
11812 return calc_watermark_data(state);
11813 }
11814
11815 static int intel_atomic_prepare_commit(struct drm_device *dev,
11816 struct drm_atomic_state *state)
11817 {
11818 struct drm_i915_private *dev_priv = to_i915(dev);
11819 struct drm_crtc_state *crtc_state;
11820 struct drm_crtc *crtc;
11821 int i, ret;
11822
11823 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11824 if (state->legacy_cursor_update)
11825 continue;
11826
11827 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
11828 flush_workqueue(dev_priv->wq);
11829 }
11830
11831 ret = mutex_lock_interruptible(&dev->struct_mutex);
11832 if (ret)
11833 return ret;
11834
11835 ret = drm_atomic_helper_prepare_planes(dev, state);
11836 mutex_unlock(&dev->struct_mutex);
11837
11838 return ret;
11839 }
11840
11841 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
11842 {
11843 struct drm_device *dev = crtc->base.dev;
11844
11845 if (!dev->max_vblank_count)
11846 return drm_accurate_vblank_count(&crtc->base);
11847
11848 return dev->driver->get_vblank_counter(dev, crtc->pipe);
11849 }
11850
11851 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
11852 struct drm_i915_private *dev_priv,
11853 unsigned crtc_mask)
11854 {
11855 unsigned last_vblank_count[I915_MAX_PIPES];
11856 enum pipe pipe;
11857 int ret;
11858
11859 if (!crtc_mask)
11860 return;
11861
11862 for_each_pipe(dev_priv, pipe) {
11863 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11864 pipe);
11865
11866 if (!((1 << pipe) & crtc_mask))
11867 continue;
11868
11869 ret = drm_crtc_vblank_get(&crtc->base);
11870 if (WARN_ON(ret != 0)) {
11871 crtc_mask &= ~(1 << pipe);
11872 continue;
11873 }
11874
11875 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
11876 }
11877
11878 for_each_pipe(dev_priv, pipe) {
11879 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11880 pipe);
11881 long lret;
11882
11883 if (!((1 << pipe) & crtc_mask))
11884 continue;
11885
11886 lret = wait_event_timeout(dev->vblank[pipe].queue,
11887 last_vblank_count[pipe] !=
11888 drm_crtc_vblank_count(&crtc->base),
11889 msecs_to_jiffies(50));
11890
11891 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
11892
11893 drm_crtc_vblank_put(&crtc->base);
11894 }
11895 }
11896
11897 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
11898 {
11899 /* fb updated, need to unpin old fb */
11900 if (crtc_state->fb_changed)
11901 return true;
11902
11903 /* wm changes, need vblank before final wm's */
11904 if (crtc_state->update_wm_post)
11905 return true;
11906
11907 if (crtc_state->wm.need_postvbl_update)
11908 return true;
11909
11910 return false;
11911 }
11912
11913 static void intel_update_crtc(struct drm_crtc *crtc,
11914 struct drm_atomic_state *state,
11915 struct drm_crtc_state *old_crtc_state,
11916 struct drm_crtc_state *new_crtc_state,
11917 unsigned int *crtc_vblank_mask)
11918 {
11919 struct drm_device *dev = crtc->dev;
11920 struct drm_i915_private *dev_priv = to_i915(dev);
11921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11922 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
11923 bool modeset = needs_modeset(new_crtc_state);
11924
11925 if (modeset) {
11926 update_scanline_offset(intel_crtc);
11927 dev_priv->display.crtc_enable(pipe_config, state);
11928 } else {
11929 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
11930 pipe_config);
11931 }
11932
11933 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11934 intel_fbc_enable(
11935 intel_crtc, pipe_config,
11936 to_intel_plane_state(crtc->primary->state));
11937 }
11938
11939 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
11940
11941 if (needs_vblank_wait(pipe_config))
11942 *crtc_vblank_mask |= drm_crtc_mask(crtc);
11943 }
11944
11945 static void intel_update_crtcs(struct drm_atomic_state *state,
11946 unsigned int *crtc_vblank_mask)
11947 {
11948 struct drm_crtc *crtc;
11949 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11950 int i;
11951
11952 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11953 if (!new_crtc_state->active)
11954 continue;
11955
11956 intel_update_crtc(crtc, state, old_crtc_state,
11957 new_crtc_state, crtc_vblank_mask);
11958 }
11959 }
11960
11961 static void skl_update_crtcs(struct drm_atomic_state *state,
11962 unsigned int *crtc_vblank_mask)
11963 {
11964 struct drm_i915_private *dev_priv = to_i915(state->dev);
11965 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11966 struct drm_crtc *crtc;
11967 struct intel_crtc *intel_crtc;
11968 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11969 struct intel_crtc_state *cstate;
11970 unsigned int updated = 0;
11971 bool progress;
11972 enum pipe pipe;
11973 int i;
11974
11975 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
11976
11977 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
11978 /* ignore allocations for crtc's that have been turned off. */
11979 if (new_crtc_state->active)
11980 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
11981
11982 /*
11983 * Whenever the number of active pipes changes, we need to make sure we
11984 * update the pipes in the right order so that their ddb allocations
11985 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
11986 * cause pipe underruns and other bad stuff.
11987 */
11988 do {
11989 progress = false;
11990
11991 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11992 bool vbl_wait = false;
11993 unsigned int cmask = drm_crtc_mask(crtc);
11994
11995 intel_crtc = to_intel_crtc(crtc);
11996 cstate = to_intel_crtc_state(crtc->state);
11997 pipe = intel_crtc->pipe;
11998
11999 if (updated & cmask || !cstate->base.active)
12000 continue;
12001
12002 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12003 continue;
12004
12005 updated |= cmask;
12006 entries[i] = &cstate->wm.skl.ddb;
12007
12008 /*
12009 * If this is an already active pipe, it's DDB changed,
12010 * and this isn't the last pipe that needs updating
12011 * then we need to wait for a vblank to pass for the
12012 * new ddb allocation to take effect.
12013 */
12014 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12015 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12016 !new_crtc_state->active_changed &&
12017 intel_state->wm_results.dirty_pipes != updated)
12018 vbl_wait = true;
12019
12020 intel_update_crtc(crtc, state, old_crtc_state,
12021 new_crtc_state, crtc_vblank_mask);
12022
12023 if (vbl_wait)
12024 intel_wait_for_vblank(dev_priv, pipe);
12025
12026 progress = true;
12027 }
12028 } while (progress);
12029 }
12030
12031 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12032 {
12033 struct intel_atomic_state *state, *next;
12034 struct llist_node *freed;
12035
12036 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12037 llist_for_each_entry_safe(state, next, freed, freed)
12038 drm_atomic_state_put(&state->base);
12039 }
12040
12041 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12042 {
12043 struct drm_i915_private *dev_priv =
12044 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12045
12046 intel_atomic_helper_free_state(dev_priv);
12047 }
12048
12049 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12050 {
12051 struct drm_device *dev = state->dev;
12052 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12053 struct drm_i915_private *dev_priv = to_i915(dev);
12054 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12055 struct drm_crtc *crtc;
12056 struct intel_crtc_state *intel_cstate;
12057 bool hw_check = intel_state->modeset;
12058 u64 put_domains[I915_MAX_PIPES] = {};
12059 unsigned crtc_vblank_mask = 0;
12060 int i;
12061
12062 drm_atomic_helper_wait_for_dependencies(state);
12063
12064 if (intel_state->modeset)
12065 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12066
12067 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12069
12070 if (needs_modeset(new_crtc_state) ||
12071 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12072 hw_check = true;
12073
12074 put_domains[to_intel_crtc(crtc)->pipe] =
12075 modeset_get_crtc_power_domains(crtc,
12076 to_intel_crtc_state(new_crtc_state));
12077 }
12078
12079 if (!needs_modeset(new_crtc_state))
12080 continue;
12081
12082 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12083 to_intel_crtc_state(new_crtc_state));
12084
12085 if (old_crtc_state->active) {
12086 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12087 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12088 intel_crtc->active = false;
12089 intel_fbc_disable(intel_crtc);
12090 intel_disable_shared_dpll(intel_crtc);
12091
12092 /*
12093 * Underruns don't always raise
12094 * interrupts, so check manually.
12095 */
12096 intel_check_cpu_fifo_underruns(dev_priv);
12097 intel_check_pch_fifo_underruns(dev_priv);
12098
12099 if (!crtc->state->active) {
12100 /*
12101 * Make sure we don't call initial_watermarks
12102 * for ILK-style watermark updates.
12103 *
12104 * No clue what this is supposed to achieve.
12105 */
12106 if (INTEL_GEN(dev_priv) >= 9)
12107 dev_priv->display.initial_watermarks(intel_state,
12108 to_intel_crtc_state(crtc->state));
12109 }
12110 }
12111 }
12112
12113 /* Only after disabling all output pipelines that will be changed can we
12114 * update the the output configuration. */
12115 intel_modeset_update_crtc_state(state);
12116
12117 if (intel_state->modeset) {
12118 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12119
12120 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12121
12122 /*
12123 * SKL workaround: bspec recommends we disable the SAGV when we
12124 * have more then one pipe enabled
12125 */
12126 if (!intel_can_enable_sagv(state))
12127 intel_disable_sagv(dev_priv);
12128
12129 intel_modeset_verify_disabled(dev, state);
12130 }
12131
12132 /* Complete the events for pipes that have now been disabled */
12133 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12134 bool modeset = needs_modeset(new_crtc_state);
12135
12136 /* Complete events for now disable pipes here. */
12137 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12138 spin_lock_irq(&dev->event_lock);
12139 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12140 spin_unlock_irq(&dev->event_lock);
12141
12142 new_crtc_state->event = NULL;
12143 }
12144 }
12145
12146 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12147 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12148
12149 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12150 * already, but still need the state for the delayed optimization. To
12151 * fix this:
12152 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12153 * - schedule that vblank worker _before_ calling hw_done
12154 * - at the start of commit_tail, cancel it _synchrously
12155 * - switch over to the vblank wait helper in the core after that since
12156 * we don't need out special handling any more.
12157 */
12158 if (!state->legacy_cursor_update)
12159 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12160
12161 /*
12162 * Now that the vblank has passed, we can go ahead and program the
12163 * optimal watermarks on platforms that need two-step watermark
12164 * programming.
12165 *
12166 * TODO: Move this (and other cleanup) to an async worker eventually.
12167 */
12168 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12169 intel_cstate = to_intel_crtc_state(new_crtc_state);
12170
12171 if (dev_priv->display.optimize_watermarks)
12172 dev_priv->display.optimize_watermarks(intel_state,
12173 intel_cstate);
12174 }
12175
12176 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12177 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12178
12179 if (put_domains[i])
12180 modeset_put_power_domains(dev_priv, put_domains[i]);
12181
12182 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12183 }
12184
12185 if (intel_state->modeset && intel_can_enable_sagv(state))
12186 intel_enable_sagv(dev_priv);
12187
12188 drm_atomic_helper_commit_hw_done(state);
12189
12190 if (intel_state->modeset) {
12191 /* As one of the primary mmio accessors, KMS has a high
12192 * likelihood of triggering bugs in unclaimed access. After we
12193 * finish modesetting, see if an error has been flagged, and if
12194 * so enable debugging for the next modeset - and hope we catch
12195 * the culprit.
12196 */
12197 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12198 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12199 }
12200
12201 mutex_lock(&dev->struct_mutex);
12202 drm_atomic_helper_cleanup_planes(dev, state);
12203 mutex_unlock(&dev->struct_mutex);
12204
12205 drm_atomic_helper_commit_cleanup_done(state);
12206
12207 drm_atomic_state_put(state);
12208
12209 intel_atomic_helper_free_state(dev_priv);
12210 }
12211
12212 static void intel_atomic_commit_work(struct work_struct *work)
12213 {
12214 struct drm_atomic_state *state =
12215 container_of(work, struct drm_atomic_state, commit_work);
12216
12217 intel_atomic_commit_tail(state);
12218 }
12219
12220 static int __i915_sw_fence_call
12221 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12222 enum i915_sw_fence_notify notify)
12223 {
12224 struct intel_atomic_state *state =
12225 container_of(fence, struct intel_atomic_state, commit_ready);
12226
12227 switch (notify) {
12228 case FENCE_COMPLETE:
12229 if (state->base.commit_work.func)
12230 queue_work(system_unbound_wq, &state->base.commit_work);
12231 break;
12232
12233 case FENCE_FREE:
12234 {
12235 struct intel_atomic_helper *helper =
12236 &to_i915(state->base.dev)->atomic_helper;
12237
12238 if (llist_add(&state->freed, &helper->free_list))
12239 schedule_work(&helper->free_work);
12240 break;
12241 }
12242 }
12243
12244 return NOTIFY_DONE;
12245 }
12246
12247 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12248 {
12249 struct drm_plane_state *old_plane_state, *new_plane_state;
12250 struct drm_plane *plane;
12251 int i;
12252
12253 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12254 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12255 intel_fb_obj(new_plane_state->fb),
12256 to_intel_plane(plane)->frontbuffer_bit);
12257 }
12258
12259 /**
12260 * intel_atomic_commit - commit validated state object
12261 * @dev: DRM device
12262 * @state: the top-level driver state object
12263 * @nonblock: nonblocking commit
12264 *
12265 * This function commits a top-level state object that has been validated
12266 * with drm_atomic_helper_check().
12267 *
12268 * RETURNS
12269 * Zero for success or -errno.
12270 */
12271 static int intel_atomic_commit(struct drm_device *dev,
12272 struct drm_atomic_state *state,
12273 bool nonblock)
12274 {
12275 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12276 struct drm_i915_private *dev_priv = to_i915(dev);
12277 int ret = 0;
12278
12279 ret = drm_atomic_helper_setup_commit(state, nonblock);
12280 if (ret)
12281 return ret;
12282
12283 drm_atomic_state_get(state);
12284 i915_sw_fence_init(&intel_state->commit_ready,
12285 intel_atomic_commit_ready);
12286
12287 ret = intel_atomic_prepare_commit(dev, state);
12288 if (ret) {
12289 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12290 i915_sw_fence_commit(&intel_state->commit_ready);
12291 return ret;
12292 }
12293
12294 /*
12295 * The intel_legacy_cursor_update() fast path takes care
12296 * of avoiding the vblank waits for simple cursor
12297 * movement and flips. For cursor on/off and size changes,
12298 * we want to perform the vblank waits so that watermark
12299 * updates happen during the correct frames. Gen9+ have
12300 * double buffered watermarks and so shouldn't need this.
12301 *
12302 * Do this after drm_atomic_helper_setup_commit() and
12303 * intel_atomic_prepare_commit() because we still want
12304 * to skip the flip and fb cleanup waits. Although that
12305 * does risk yanking the mapping from under the display
12306 * engine.
12307 *
12308 * FIXME doing watermarks and fb cleanup from a vblank worker
12309 * (assuming we had any) would solve these problems.
12310 */
12311 if (INTEL_GEN(dev_priv) < 9)
12312 state->legacy_cursor_update = false;
12313
12314 drm_atomic_helper_swap_state(state, true);
12315 dev_priv->wm.distrust_bios_wm = false;
12316 intel_shared_dpll_swap_state(state);
12317 intel_atomic_track_fbs(state);
12318
12319 if (intel_state->modeset) {
12320 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
12321 sizeof(intel_state->min_pixclk));
12322 dev_priv->active_crtcs = intel_state->active_crtcs;
12323 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12324 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12325 }
12326
12327 drm_atomic_state_get(state);
12328 INIT_WORK(&state->commit_work,
12329 nonblock ? intel_atomic_commit_work : NULL);
12330
12331 i915_sw_fence_commit(&intel_state->commit_ready);
12332 if (!nonblock) {
12333 i915_sw_fence_wait(&intel_state->commit_ready);
12334 intel_atomic_commit_tail(state);
12335 }
12336
12337 return 0;
12338 }
12339
12340 static const struct drm_crtc_funcs intel_crtc_funcs = {
12341 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12342 .set_config = drm_atomic_helper_set_config,
12343 .set_property = drm_atomic_helper_crtc_set_property,
12344 .destroy = intel_crtc_destroy,
12345 .page_flip = drm_atomic_helper_page_flip,
12346 .atomic_duplicate_state = intel_crtc_duplicate_state,
12347 .atomic_destroy_state = intel_crtc_destroy_state,
12348 .set_crc_source = intel_crtc_set_crc_source,
12349 };
12350
12351 /**
12352 * intel_prepare_plane_fb - Prepare fb for usage on plane
12353 * @plane: drm plane to prepare for
12354 * @fb: framebuffer to prepare for presentation
12355 *
12356 * Prepares a framebuffer for usage on a display plane. Generally this
12357 * involves pinning the underlying object and updating the frontbuffer tracking
12358 * bits. Some older platforms need special physical address handling for
12359 * cursor planes.
12360 *
12361 * Must be called with struct_mutex held.
12362 *
12363 * Returns 0 on success, negative error code on failure.
12364 */
12365 int
12366 intel_prepare_plane_fb(struct drm_plane *plane,
12367 struct drm_plane_state *new_state)
12368 {
12369 struct intel_atomic_state *intel_state =
12370 to_intel_atomic_state(new_state->state);
12371 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12372 struct drm_framebuffer *fb = new_state->fb;
12373 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12374 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12375 int ret;
12376
12377 if (obj) {
12378 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12379 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12380 const int align = intel_cursor_alignment(dev_priv);
12381
12382 ret = i915_gem_object_attach_phys(obj, align);
12383 if (ret) {
12384 DRM_DEBUG_KMS("failed to attach phys object\n");
12385 return ret;
12386 }
12387 } else {
12388 struct i915_vma *vma;
12389
12390 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12391 if (IS_ERR(vma)) {
12392 DRM_DEBUG_KMS("failed to pin object\n");
12393 return PTR_ERR(vma);
12394 }
12395
12396 to_intel_plane_state(new_state)->vma = vma;
12397 }
12398 }
12399
12400 if (!obj && !old_obj)
12401 return 0;
12402
12403 if (old_obj) {
12404 struct drm_crtc_state *crtc_state =
12405 drm_atomic_get_existing_crtc_state(new_state->state,
12406 plane->state->crtc);
12407
12408 /* Big Hammer, we also need to ensure that any pending
12409 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12410 * current scanout is retired before unpinning the old
12411 * framebuffer. Note that we rely on userspace rendering
12412 * into the buffer attached to the pipe they are waiting
12413 * on. If not, userspace generates a GPU hang with IPEHR
12414 * point to the MI_WAIT_FOR_EVENT.
12415 *
12416 * This should only fail upon a hung GPU, in which case we
12417 * can safely continue.
12418 */
12419 if (needs_modeset(crtc_state)) {
12420 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12421 old_obj->resv, NULL,
12422 false, 0,
12423 GFP_KERNEL);
12424 if (ret < 0)
12425 return ret;
12426 }
12427 }
12428
12429 if (new_state->fence) { /* explicit fencing */
12430 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12431 new_state->fence,
12432 I915_FENCE_TIMEOUT,
12433 GFP_KERNEL);
12434 if (ret < 0)
12435 return ret;
12436 }
12437
12438 if (!obj)
12439 return 0;
12440
12441 if (!new_state->fence) { /* implicit fencing */
12442 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12443 obj->resv, NULL,
12444 false, I915_FENCE_TIMEOUT,
12445 GFP_KERNEL);
12446 if (ret < 0)
12447 return ret;
12448
12449 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12450 }
12451
12452 return 0;
12453 }
12454
12455 /**
12456 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12457 * @plane: drm plane to clean up for
12458 * @fb: old framebuffer that was on plane
12459 *
12460 * Cleans up a framebuffer that has just been removed from a plane.
12461 *
12462 * Must be called with struct_mutex held.
12463 */
12464 void
12465 intel_cleanup_plane_fb(struct drm_plane *plane,
12466 struct drm_plane_state *old_state)
12467 {
12468 struct i915_vma *vma;
12469
12470 /* Should only be called after a successful intel_prepare_plane_fb()! */
12471 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12472 if (vma)
12473 intel_unpin_fb_vma(vma);
12474 }
12475
12476 int
12477 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12478 {
12479 struct drm_i915_private *dev_priv;
12480 int max_scale;
12481 int crtc_clock, max_dotclk;
12482
12483 if (!intel_crtc || !crtc_state->base.enable)
12484 return DRM_PLANE_HELPER_NO_SCALING;
12485
12486 dev_priv = to_i915(intel_crtc->base.dev);
12487
12488 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12489 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12490
12491 if (IS_GEMINILAKE(dev_priv))
12492 max_dotclk *= 2;
12493
12494 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12495 return DRM_PLANE_HELPER_NO_SCALING;
12496
12497 /*
12498 * skl max scale is lower of:
12499 * close to 3 but not 3, -1 is for that purpose
12500 * or
12501 * cdclk/crtc_clock
12502 */
12503 max_scale = min((1 << 16) * 3 - 1,
12504 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12505
12506 return max_scale;
12507 }
12508
12509 static int
12510 intel_check_primary_plane(struct intel_plane *plane,
12511 struct intel_crtc_state *crtc_state,
12512 struct intel_plane_state *state)
12513 {
12514 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12515 struct drm_crtc *crtc = state->base.crtc;
12516 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12517 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12518 bool can_position = false;
12519 int ret;
12520
12521 if (INTEL_GEN(dev_priv) >= 9) {
12522 /* use scaler when colorkey is not required */
12523 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12524 min_scale = 1;
12525 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12526 }
12527 can_position = true;
12528 }
12529
12530 ret = drm_plane_helper_check_state(&state->base,
12531 &state->clip,
12532 min_scale, max_scale,
12533 can_position, true);
12534 if (ret)
12535 return ret;
12536
12537 if (!state->base.fb)
12538 return 0;
12539
12540 if (INTEL_GEN(dev_priv) >= 9) {
12541 ret = skl_check_plane_surface(state);
12542 if (ret)
12543 return ret;
12544
12545 state->ctl = skl_plane_ctl(crtc_state, state);
12546 } else {
12547 ret = i9xx_check_plane_surface(state);
12548 if (ret)
12549 return ret;
12550
12551 state->ctl = i9xx_plane_ctl(crtc_state, state);
12552 }
12553
12554 return 0;
12555 }
12556
12557 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12558 struct drm_crtc_state *old_crtc_state)
12559 {
12560 struct drm_device *dev = crtc->dev;
12561 struct drm_i915_private *dev_priv = to_i915(dev);
12562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12563 struct intel_crtc_state *intel_cstate =
12564 to_intel_crtc_state(crtc->state);
12565 struct intel_crtc_state *old_intel_cstate =
12566 to_intel_crtc_state(old_crtc_state);
12567 struct intel_atomic_state *old_intel_state =
12568 to_intel_atomic_state(old_crtc_state->state);
12569 bool modeset = needs_modeset(crtc->state);
12570
12571 if (!modeset &&
12572 (intel_cstate->base.color_mgmt_changed ||
12573 intel_cstate->update_pipe)) {
12574 intel_color_set_csc(crtc->state);
12575 intel_color_load_luts(crtc->state);
12576 }
12577
12578 /* Perform vblank evasion around commit operation */
12579 intel_pipe_update_start(intel_crtc);
12580
12581 if (modeset)
12582 goto out;
12583
12584 if (intel_cstate->update_pipe)
12585 intel_update_pipe_config(intel_crtc, old_intel_cstate);
12586 else if (INTEL_GEN(dev_priv) >= 9)
12587 skl_detach_scalers(intel_crtc);
12588
12589 out:
12590 if (dev_priv->display.atomic_update_watermarks)
12591 dev_priv->display.atomic_update_watermarks(old_intel_state,
12592 intel_cstate);
12593 }
12594
12595 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12596 struct drm_crtc_state *old_crtc_state)
12597 {
12598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12599
12600 intel_pipe_update_end(intel_crtc);
12601 }
12602
12603 /**
12604 * intel_plane_destroy - destroy a plane
12605 * @plane: plane to destroy
12606 *
12607 * Common destruction function for all types of planes (primary, cursor,
12608 * sprite).
12609 */
12610 void intel_plane_destroy(struct drm_plane *plane)
12611 {
12612 drm_plane_cleanup(plane);
12613 kfree(to_intel_plane(plane));
12614 }
12615
12616 const struct drm_plane_funcs intel_plane_funcs = {
12617 .update_plane = drm_atomic_helper_update_plane,
12618 .disable_plane = drm_atomic_helper_disable_plane,
12619 .destroy = intel_plane_destroy,
12620 .set_property = drm_atomic_helper_plane_set_property,
12621 .atomic_get_property = intel_plane_atomic_get_property,
12622 .atomic_set_property = intel_plane_atomic_set_property,
12623 .atomic_duplicate_state = intel_plane_duplicate_state,
12624 .atomic_destroy_state = intel_plane_destroy_state,
12625 };
12626
12627 static int
12628 intel_legacy_cursor_update(struct drm_plane *plane,
12629 struct drm_crtc *crtc,
12630 struct drm_framebuffer *fb,
12631 int crtc_x, int crtc_y,
12632 unsigned int crtc_w, unsigned int crtc_h,
12633 uint32_t src_x, uint32_t src_y,
12634 uint32_t src_w, uint32_t src_h,
12635 struct drm_modeset_acquire_ctx *ctx)
12636 {
12637 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12638 int ret;
12639 struct drm_plane_state *old_plane_state, *new_plane_state;
12640 struct intel_plane *intel_plane = to_intel_plane(plane);
12641 struct drm_framebuffer *old_fb;
12642 struct drm_crtc_state *crtc_state = crtc->state;
12643 struct i915_vma *old_vma;
12644
12645 /*
12646 * When crtc is inactive or there is a modeset pending,
12647 * wait for it to complete in the slowpath
12648 */
12649 if (!crtc_state->active || needs_modeset(crtc_state) ||
12650 to_intel_crtc_state(crtc_state)->update_pipe)
12651 goto slow;
12652
12653 old_plane_state = plane->state;
12654
12655 /*
12656 * If any parameters change that may affect watermarks,
12657 * take the slowpath. Only changing fb or position should be
12658 * in the fastpath.
12659 */
12660 if (old_plane_state->crtc != crtc ||
12661 old_plane_state->src_w != src_w ||
12662 old_plane_state->src_h != src_h ||
12663 old_plane_state->crtc_w != crtc_w ||
12664 old_plane_state->crtc_h != crtc_h ||
12665 !old_plane_state->fb != !fb)
12666 goto slow;
12667
12668 new_plane_state = intel_plane_duplicate_state(plane);
12669 if (!new_plane_state)
12670 return -ENOMEM;
12671
12672 drm_atomic_set_fb_for_plane(new_plane_state, fb);
12673
12674 new_plane_state->src_x = src_x;
12675 new_plane_state->src_y = src_y;
12676 new_plane_state->src_w = src_w;
12677 new_plane_state->src_h = src_h;
12678 new_plane_state->crtc_x = crtc_x;
12679 new_plane_state->crtc_y = crtc_y;
12680 new_plane_state->crtc_w = crtc_w;
12681 new_plane_state->crtc_h = crtc_h;
12682
12683 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
12684 to_intel_plane_state(new_plane_state));
12685 if (ret)
12686 goto out_free;
12687
12688 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12689 if (ret)
12690 goto out_free;
12691
12692 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
12693 int align = intel_cursor_alignment(dev_priv);
12694
12695 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
12696 if (ret) {
12697 DRM_DEBUG_KMS("failed to attach phys object\n");
12698 goto out_unlock;
12699 }
12700 } else {
12701 struct i915_vma *vma;
12702
12703 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
12704 if (IS_ERR(vma)) {
12705 DRM_DEBUG_KMS("failed to pin object\n");
12706
12707 ret = PTR_ERR(vma);
12708 goto out_unlock;
12709 }
12710
12711 to_intel_plane_state(new_plane_state)->vma = vma;
12712 }
12713
12714 old_fb = old_plane_state->fb;
12715 old_vma = to_intel_plane_state(old_plane_state)->vma;
12716
12717 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
12718 intel_plane->frontbuffer_bit);
12719
12720 /* Swap plane state */
12721 new_plane_state->fence = old_plane_state->fence;
12722 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
12723 new_plane_state->fence = NULL;
12724 new_plane_state->fb = old_fb;
12725 to_intel_plane_state(new_plane_state)->vma = old_vma;
12726
12727 if (plane->state->visible) {
12728 trace_intel_update_plane(plane, to_intel_crtc(crtc));
12729 intel_plane->update_plane(intel_plane,
12730 to_intel_crtc_state(crtc->state),
12731 to_intel_plane_state(plane->state));
12732 } else {
12733 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
12734 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
12735 }
12736
12737 intel_cleanup_plane_fb(plane, new_plane_state);
12738
12739 out_unlock:
12740 mutex_unlock(&dev_priv->drm.struct_mutex);
12741 out_free:
12742 intel_plane_destroy_state(plane, new_plane_state);
12743 return ret;
12744
12745 slow:
12746 return drm_atomic_helper_update_plane(plane, crtc, fb,
12747 crtc_x, crtc_y, crtc_w, crtc_h,
12748 src_x, src_y, src_w, src_h, ctx);
12749 }
12750
12751 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12752 .update_plane = intel_legacy_cursor_update,
12753 .disable_plane = drm_atomic_helper_disable_plane,
12754 .destroy = intel_plane_destroy,
12755 .set_property = drm_atomic_helper_plane_set_property,
12756 .atomic_get_property = intel_plane_atomic_get_property,
12757 .atomic_set_property = intel_plane_atomic_set_property,
12758 .atomic_duplicate_state = intel_plane_duplicate_state,
12759 .atomic_destroy_state = intel_plane_destroy_state,
12760 };
12761
12762 static struct intel_plane *
12763 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
12764 {
12765 struct intel_plane *primary = NULL;
12766 struct intel_plane_state *state = NULL;
12767 const uint32_t *intel_primary_formats;
12768 unsigned int supported_rotations;
12769 unsigned int num_formats;
12770 int ret;
12771
12772 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12773 if (!primary) {
12774 ret = -ENOMEM;
12775 goto fail;
12776 }
12777
12778 state = intel_create_plane_state(&primary->base);
12779 if (!state) {
12780 ret = -ENOMEM;
12781 goto fail;
12782 }
12783
12784 primary->base.state = &state->base;
12785
12786 primary->can_scale = false;
12787 primary->max_downscale = 1;
12788 if (INTEL_GEN(dev_priv) >= 9) {
12789 primary->can_scale = true;
12790 state->scaler_id = -1;
12791 }
12792 primary->pipe = pipe;
12793 /*
12794 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
12795 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
12796 */
12797 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
12798 primary->plane = (enum plane) !pipe;
12799 else
12800 primary->plane = (enum plane) pipe;
12801 primary->id = PLANE_PRIMARY;
12802 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
12803 primary->check_plane = intel_check_primary_plane;
12804
12805 if (INTEL_GEN(dev_priv) >= 9) {
12806 intel_primary_formats = skl_primary_formats;
12807 num_formats = ARRAY_SIZE(skl_primary_formats);
12808
12809 primary->update_plane = skylake_update_primary_plane;
12810 primary->disable_plane = skylake_disable_primary_plane;
12811 } else if (INTEL_GEN(dev_priv) >= 4) {
12812 intel_primary_formats = i965_primary_formats;
12813 num_formats = ARRAY_SIZE(i965_primary_formats);
12814
12815 primary->update_plane = i9xx_update_primary_plane;
12816 primary->disable_plane = i9xx_disable_primary_plane;
12817 } else {
12818 intel_primary_formats = i8xx_primary_formats;
12819 num_formats = ARRAY_SIZE(i8xx_primary_formats);
12820
12821 primary->update_plane = i9xx_update_primary_plane;
12822 primary->disable_plane = i9xx_disable_primary_plane;
12823 }
12824
12825 if (INTEL_GEN(dev_priv) >= 9)
12826 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12827 0, &intel_plane_funcs,
12828 intel_primary_formats, num_formats,
12829 DRM_PLANE_TYPE_PRIMARY,
12830 "plane 1%c", pipe_name(pipe));
12831 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12832 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12833 0, &intel_plane_funcs,
12834 intel_primary_formats, num_formats,
12835 DRM_PLANE_TYPE_PRIMARY,
12836 "primary %c", pipe_name(pipe));
12837 else
12838 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12839 0, &intel_plane_funcs,
12840 intel_primary_formats, num_formats,
12841 DRM_PLANE_TYPE_PRIMARY,
12842 "plane %c", plane_name(primary->plane));
12843 if (ret)
12844 goto fail;
12845
12846 if (INTEL_GEN(dev_priv) >= 9) {
12847 supported_rotations =
12848 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
12849 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
12850 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
12851 supported_rotations =
12852 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
12853 DRM_MODE_REFLECT_X;
12854 } else if (INTEL_GEN(dev_priv) >= 4) {
12855 supported_rotations =
12856 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
12857 } else {
12858 supported_rotations = DRM_MODE_ROTATE_0;
12859 }
12860
12861 if (INTEL_GEN(dev_priv) >= 4)
12862 drm_plane_create_rotation_property(&primary->base,
12863 DRM_MODE_ROTATE_0,
12864 supported_rotations);
12865
12866 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12867
12868 return primary;
12869
12870 fail:
12871 kfree(state);
12872 kfree(primary);
12873
12874 return ERR_PTR(ret);
12875 }
12876
12877 static struct intel_plane *
12878 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
12879 enum pipe pipe)
12880 {
12881 struct intel_plane *cursor = NULL;
12882 struct intel_plane_state *state = NULL;
12883 int ret;
12884
12885 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12886 if (!cursor) {
12887 ret = -ENOMEM;
12888 goto fail;
12889 }
12890
12891 state = intel_create_plane_state(&cursor->base);
12892 if (!state) {
12893 ret = -ENOMEM;
12894 goto fail;
12895 }
12896
12897 cursor->base.state = &state->base;
12898
12899 cursor->can_scale = false;
12900 cursor->max_downscale = 1;
12901 cursor->pipe = pipe;
12902 cursor->plane = pipe;
12903 cursor->id = PLANE_CURSOR;
12904 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
12905
12906 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
12907 cursor->update_plane = i845_update_cursor;
12908 cursor->disable_plane = i845_disable_cursor;
12909 cursor->check_plane = i845_check_cursor;
12910 } else {
12911 cursor->update_plane = i9xx_update_cursor;
12912 cursor->disable_plane = i9xx_disable_cursor;
12913 cursor->check_plane = i9xx_check_cursor;
12914 }
12915
12916 cursor->cursor.base = ~0;
12917 cursor->cursor.cntl = ~0;
12918
12919 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
12920 cursor->cursor.size = ~0;
12921
12922 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
12923 0, &intel_cursor_plane_funcs,
12924 intel_cursor_formats,
12925 ARRAY_SIZE(intel_cursor_formats),
12926 DRM_PLANE_TYPE_CURSOR,
12927 "cursor %c", pipe_name(pipe));
12928 if (ret)
12929 goto fail;
12930
12931 if (INTEL_GEN(dev_priv) >= 4)
12932 drm_plane_create_rotation_property(&cursor->base,
12933 DRM_MODE_ROTATE_0,
12934 DRM_MODE_ROTATE_0 |
12935 DRM_MODE_ROTATE_180);
12936
12937 if (INTEL_GEN(dev_priv) >= 9)
12938 state->scaler_id = -1;
12939
12940 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12941
12942 return cursor;
12943
12944 fail:
12945 kfree(state);
12946 kfree(cursor);
12947
12948 return ERR_PTR(ret);
12949 }
12950
12951 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
12952 struct intel_crtc_state *crtc_state)
12953 {
12954 struct intel_crtc_scaler_state *scaler_state =
12955 &crtc_state->scaler_state;
12956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12957 int i;
12958
12959 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
12960 if (!crtc->num_scalers)
12961 return;
12962
12963 for (i = 0; i < crtc->num_scalers; i++) {
12964 struct intel_scaler *scaler = &scaler_state->scalers[i];
12965
12966 scaler->in_use = 0;
12967 scaler->mode = PS_SCALER_MODE_DYN;
12968 }
12969
12970 scaler_state->scaler_id = -1;
12971 }
12972
12973 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
12974 {
12975 struct intel_crtc *intel_crtc;
12976 struct intel_crtc_state *crtc_state = NULL;
12977 struct intel_plane *primary = NULL;
12978 struct intel_plane *cursor = NULL;
12979 int sprite, ret;
12980
12981 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12982 if (!intel_crtc)
12983 return -ENOMEM;
12984
12985 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12986 if (!crtc_state) {
12987 ret = -ENOMEM;
12988 goto fail;
12989 }
12990 intel_crtc->config = crtc_state;
12991 intel_crtc->base.state = &crtc_state->base;
12992 crtc_state->base.crtc = &intel_crtc->base;
12993
12994 primary = intel_primary_plane_create(dev_priv, pipe);
12995 if (IS_ERR(primary)) {
12996 ret = PTR_ERR(primary);
12997 goto fail;
12998 }
12999 intel_crtc->plane_ids_mask |= BIT(primary->id);
13000
13001 for_each_sprite(dev_priv, pipe, sprite) {
13002 struct intel_plane *plane;
13003
13004 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13005 if (IS_ERR(plane)) {
13006 ret = PTR_ERR(plane);
13007 goto fail;
13008 }
13009 intel_crtc->plane_ids_mask |= BIT(plane->id);
13010 }
13011
13012 cursor = intel_cursor_plane_create(dev_priv, pipe);
13013 if (IS_ERR(cursor)) {
13014 ret = PTR_ERR(cursor);
13015 goto fail;
13016 }
13017 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13018
13019 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13020 &primary->base, &cursor->base,
13021 &intel_crtc_funcs,
13022 "pipe %c", pipe_name(pipe));
13023 if (ret)
13024 goto fail;
13025
13026 intel_crtc->pipe = pipe;
13027 intel_crtc->plane = primary->plane;
13028
13029 /* initialize shared scalers */
13030 intel_crtc_init_scalers(intel_crtc, crtc_state);
13031
13032 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13033 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13034 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13035 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13036
13037 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13038
13039 intel_color_init(&intel_crtc->base);
13040
13041 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13042
13043 return 0;
13044
13045 fail:
13046 /*
13047 * drm_mode_config_cleanup() will free up any
13048 * crtcs/planes already initialized.
13049 */
13050 kfree(crtc_state);
13051 kfree(intel_crtc);
13052
13053 return ret;
13054 }
13055
13056 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13057 {
13058 struct drm_device *dev = connector->base.dev;
13059
13060 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13061
13062 if (!connector->base.state->crtc)
13063 return INVALID_PIPE;
13064
13065 return to_intel_crtc(connector->base.state->crtc)->pipe;
13066 }
13067
13068 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13069 struct drm_file *file)
13070 {
13071 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13072 struct drm_crtc *drmmode_crtc;
13073 struct intel_crtc *crtc;
13074
13075 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13076 if (!drmmode_crtc)
13077 return -ENOENT;
13078
13079 crtc = to_intel_crtc(drmmode_crtc);
13080 pipe_from_crtc_id->pipe = crtc->pipe;
13081
13082 return 0;
13083 }
13084
13085 static int intel_encoder_clones(struct intel_encoder *encoder)
13086 {
13087 struct drm_device *dev = encoder->base.dev;
13088 struct intel_encoder *source_encoder;
13089 int index_mask = 0;
13090 int entry = 0;
13091
13092 for_each_intel_encoder(dev, source_encoder) {
13093 if (encoders_cloneable(encoder, source_encoder))
13094 index_mask |= (1 << entry);
13095
13096 entry++;
13097 }
13098
13099 return index_mask;
13100 }
13101
13102 static bool has_edp_a(struct drm_i915_private *dev_priv)
13103 {
13104 if (!IS_MOBILE(dev_priv))
13105 return false;
13106
13107 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13108 return false;
13109
13110 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13111 return false;
13112
13113 return true;
13114 }
13115
13116 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13117 {
13118 if (INTEL_GEN(dev_priv) >= 9)
13119 return false;
13120
13121 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13122 return false;
13123
13124 if (IS_CHERRYVIEW(dev_priv))
13125 return false;
13126
13127 if (HAS_PCH_LPT_H(dev_priv) &&
13128 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13129 return false;
13130
13131 /* DDI E can't be used if DDI A requires 4 lanes */
13132 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13133 return false;
13134
13135 if (!dev_priv->vbt.int_crt_support)
13136 return false;
13137
13138 return true;
13139 }
13140
13141 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13142 {
13143 int pps_num;
13144 int pps_idx;
13145
13146 if (HAS_DDI(dev_priv))
13147 return;
13148 /*
13149 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13150 * everywhere where registers can be write protected.
13151 */
13152 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13153 pps_num = 2;
13154 else
13155 pps_num = 1;
13156
13157 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13158 u32 val = I915_READ(PP_CONTROL(pps_idx));
13159
13160 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13161 I915_WRITE(PP_CONTROL(pps_idx), val);
13162 }
13163 }
13164
13165 static void intel_pps_init(struct drm_i915_private *dev_priv)
13166 {
13167 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13168 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13169 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13170 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13171 else
13172 dev_priv->pps_mmio_base = PPS_BASE;
13173
13174 intel_pps_unlock_regs_wa(dev_priv);
13175 }
13176
13177 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13178 {
13179 struct intel_encoder *encoder;
13180 bool dpd_is_edp = false;
13181
13182 intel_pps_init(dev_priv);
13183
13184 /*
13185 * intel_edp_init_connector() depends on this completing first, to
13186 * prevent the registeration of both eDP and LVDS and the incorrect
13187 * sharing of the PPS.
13188 */
13189 intel_lvds_init(dev_priv);
13190
13191 if (intel_crt_present(dev_priv))
13192 intel_crt_init(dev_priv);
13193
13194 if (IS_GEN9_LP(dev_priv)) {
13195 /*
13196 * FIXME: Broxton doesn't support port detection via the
13197 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13198 * detect the ports.
13199 */
13200 intel_ddi_init(dev_priv, PORT_A);
13201 intel_ddi_init(dev_priv, PORT_B);
13202 intel_ddi_init(dev_priv, PORT_C);
13203
13204 intel_dsi_init(dev_priv);
13205 } else if (HAS_DDI(dev_priv)) {
13206 int found;
13207
13208 /*
13209 * Haswell uses DDI functions to detect digital outputs.
13210 * On SKL pre-D0 the strap isn't connected, so we assume
13211 * it's there.
13212 */
13213 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13214 /* WaIgnoreDDIAStrap: skl */
13215 if (found || IS_GEN9_BC(dev_priv))
13216 intel_ddi_init(dev_priv, PORT_A);
13217
13218 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13219 * register */
13220 found = I915_READ(SFUSE_STRAP);
13221
13222 if (found & SFUSE_STRAP_DDIB_DETECTED)
13223 intel_ddi_init(dev_priv, PORT_B);
13224 if (found & SFUSE_STRAP_DDIC_DETECTED)
13225 intel_ddi_init(dev_priv, PORT_C);
13226 if (found & SFUSE_STRAP_DDID_DETECTED)
13227 intel_ddi_init(dev_priv, PORT_D);
13228 /*
13229 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13230 */
13231 if (IS_GEN9_BC(dev_priv) &&
13232 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13233 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13234 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13235 intel_ddi_init(dev_priv, PORT_E);
13236
13237 } else if (HAS_PCH_SPLIT(dev_priv)) {
13238 int found;
13239 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
13240
13241 if (has_edp_a(dev_priv))
13242 intel_dp_init(dev_priv, DP_A, PORT_A);
13243
13244 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13245 /* PCH SDVOB multiplex with HDMIB */
13246 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13247 if (!found)
13248 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13249 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13250 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13251 }
13252
13253 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13254 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13255
13256 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13257 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13258
13259 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13260 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13261
13262 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13263 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13264 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13265 bool has_edp, has_port;
13266
13267 /*
13268 * The DP_DETECTED bit is the latched state of the DDC
13269 * SDA pin at boot. However since eDP doesn't require DDC
13270 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13271 * eDP ports may have been muxed to an alternate function.
13272 * Thus we can't rely on the DP_DETECTED bit alone to detect
13273 * eDP ports. Consult the VBT as well as DP_DETECTED to
13274 * detect eDP ports.
13275 *
13276 * Sadly the straps seem to be missing sometimes even for HDMI
13277 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13278 * and VBT for the presence of the port. Additionally we can't
13279 * trust the port type the VBT declares as we've seen at least
13280 * HDMI ports that the VBT claim are DP or eDP.
13281 */
13282 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
13283 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13284 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13285 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13286 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13287 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13288
13289 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
13290 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13291 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13292 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13293 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13294 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13295
13296 if (IS_CHERRYVIEW(dev_priv)) {
13297 /*
13298 * eDP not supported on port D,
13299 * so no need to worry about it
13300 */
13301 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13302 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13303 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13304 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13305 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13306 }
13307
13308 intel_dsi_init(dev_priv);
13309 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13310 bool found = false;
13311
13312 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13313 DRM_DEBUG_KMS("probing SDVOB\n");
13314 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13315 if (!found && IS_G4X(dev_priv)) {
13316 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13317 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13318 }
13319
13320 if (!found && IS_G4X(dev_priv))
13321 intel_dp_init(dev_priv, DP_B, PORT_B);
13322 }
13323
13324 /* Before G4X SDVOC doesn't have its own detect register */
13325
13326 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13327 DRM_DEBUG_KMS("probing SDVOC\n");
13328 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13329 }
13330
13331 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13332
13333 if (IS_G4X(dev_priv)) {
13334 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13335 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13336 }
13337 if (IS_G4X(dev_priv))
13338 intel_dp_init(dev_priv, DP_C, PORT_C);
13339 }
13340
13341 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13342 intel_dp_init(dev_priv, DP_D, PORT_D);
13343 } else if (IS_GEN2(dev_priv))
13344 intel_dvo_init(dev_priv);
13345
13346 if (SUPPORTS_TV(dev_priv))
13347 intel_tv_init(dev_priv);
13348
13349 intel_psr_init(dev_priv);
13350
13351 for_each_intel_encoder(&dev_priv->drm, encoder) {
13352 encoder->base.possible_crtcs = encoder->crtc_mask;
13353 encoder->base.possible_clones =
13354 intel_encoder_clones(encoder);
13355 }
13356
13357 intel_init_pch_refclk(dev_priv);
13358
13359 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13360 }
13361
13362 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13363 {
13364 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13365
13366 drm_framebuffer_cleanup(fb);
13367
13368 i915_gem_object_lock(intel_fb->obj);
13369 WARN_ON(!intel_fb->obj->framebuffer_references--);
13370 i915_gem_object_unlock(intel_fb->obj);
13371
13372 i915_gem_object_put(intel_fb->obj);
13373
13374 kfree(intel_fb);
13375 }
13376
13377 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13378 struct drm_file *file,
13379 unsigned int *handle)
13380 {
13381 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13382 struct drm_i915_gem_object *obj = intel_fb->obj;
13383
13384 if (obj->userptr.mm) {
13385 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13386 return -EINVAL;
13387 }
13388
13389 return drm_gem_handle_create(file, &obj->base, handle);
13390 }
13391
13392 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13393 struct drm_file *file,
13394 unsigned flags, unsigned color,
13395 struct drm_clip_rect *clips,
13396 unsigned num_clips)
13397 {
13398 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13399
13400 i915_gem_object_flush_if_display(obj);
13401 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13402
13403 return 0;
13404 }
13405
13406 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13407 .destroy = intel_user_framebuffer_destroy,
13408 .create_handle = intel_user_framebuffer_create_handle,
13409 .dirty = intel_user_framebuffer_dirty,
13410 };
13411
13412 static
13413 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13414 uint64_t fb_modifier, uint32_t pixel_format)
13415 {
13416 u32 gen = INTEL_GEN(dev_priv);
13417
13418 if (gen >= 9) {
13419 int cpp = drm_format_plane_cpp(pixel_format, 0);
13420
13421 /* "The stride in bytes must not exceed the of the size of 8K
13422 * pixels and 32K bytes."
13423 */
13424 return min(8192 * cpp, 32768);
13425 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13426 return 32*1024;
13427 } else if (gen >= 4) {
13428 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13429 return 16*1024;
13430 else
13431 return 32*1024;
13432 } else if (gen >= 3) {
13433 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13434 return 8*1024;
13435 else
13436 return 16*1024;
13437 } else {
13438 /* XXX DSPC is limited to 4k tiled */
13439 return 8*1024;
13440 }
13441 }
13442
13443 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13444 struct drm_i915_gem_object *obj,
13445 struct drm_mode_fb_cmd2 *mode_cmd)
13446 {
13447 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13448 struct drm_format_name_buf format_name;
13449 u32 pitch_limit, stride_alignment;
13450 unsigned int tiling, stride;
13451 int ret = -EINVAL;
13452
13453 i915_gem_object_lock(obj);
13454 obj->framebuffer_references++;
13455 tiling = i915_gem_object_get_tiling(obj);
13456 stride = i915_gem_object_get_stride(obj);
13457 i915_gem_object_unlock(obj);
13458
13459 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13460 /*
13461 * If there's a fence, enforce that
13462 * the fb modifier and tiling mode match.
13463 */
13464 if (tiling != I915_TILING_NONE &&
13465 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13466 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13467 goto err;
13468 }
13469 } else {
13470 if (tiling == I915_TILING_X) {
13471 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13472 } else if (tiling == I915_TILING_Y) {
13473 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13474 goto err;
13475 }
13476 }
13477
13478 /* Passed in modifier sanity checking. */
13479 switch (mode_cmd->modifier[0]) {
13480 case I915_FORMAT_MOD_Y_TILED:
13481 case I915_FORMAT_MOD_Yf_TILED:
13482 if (INTEL_GEN(dev_priv) < 9) {
13483 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13484 mode_cmd->modifier[0]);
13485 goto err;
13486 }
13487 case DRM_FORMAT_MOD_LINEAR:
13488 case I915_FORMAT_MOD_X_TILED:
13489 break;
13490 default:
13491 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13492 mode_cmd->modifier[0]);
13493 goto err;
13494 }
13495
13496 /*
13497 * gen2/3 display engine uses the fence if present,
13498 * so the tiling mode must match the fb modifier exactly.
13499 */
13500 if (INTEL_INFO(dev_priv)->gen < 4 &&
13501 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13502 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13503 goto err;
13504 }
13505
13506 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13507 mode_cmd->pixel_format);
13508 if (mode_cmd->pitches[0] > pitch_limit) {
13509 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13510 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13511 "tiled" : "linear",
13512 mode_cmd->pitches[0], pitch_limit);
13513 goto err;
13514 }
13515
13516 /*
13517 * If there's a fence, enforce that
13518 * the fb pitch and fence stride match.
13519 */
13520 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13521 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13522 mode_cmd->pitches[0], stride);
13523 goto err;
13524 }
13525
13526 /* Reject formats not supported by any plane early. */
13527 switch (mode_cmd->pixel_format) {
13528 case DRM_FORMAT_C8:
13529 case DRM_FORMAT_RGB565:
13530 case DRM_FORMAT_XRGB8888:
13531 case DRM_FORMAT_ARGB8888:
13532 break;
13533 case DRM_FORMAT_XRGB1555:
13534 if (INTEL_GEN(dev_priv) > 3) {
13535 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13536 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13537 goto err;
13538 }
13539 break;
13540 case DRM_FORMAT_ABGR8888:
13541 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13542 INTEL_GEN(dev_priv) < 9) {
13543 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13544 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13545 goto err;
13546 }
13547 break;
13548 case DRM_FORMAT_XBGR8888:
13549 case DRM_FORMAT_XRGB2101010:
13550 case DRM_FORMAT_XBGR2101010:
13551 if (INTEL_GEN(dev_priv) < 4) {
13552 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13553 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13554 goto err;
13555 }
13556 break;
13557 case DRM_FORMAT_ABGR2101010:
13558 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13559 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13560 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13561 goto err;
13562 }
13563 break;
13564 case DRM_FORMAT_YUYV:
13565 case DRM_FORMAT_UYVY:
13566 case DRM_FORMAT_YVYU:
13567 case DRM_FORMAT_VYUY:
13568 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13569 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13570 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13571 goto err;
13572 }
13573 break;
13574 default:
13575 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13576 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13577 goto err;
13578 }
13579
13580 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13581 if (mode_cmd->offsets[0] != 0)
13582 goto err;
13583
13584 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
13585 &intel_fb->base, mode_cmd);
13586
13587 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
13588 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13589 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
13590 mode_cmd->pitches[0], stride_alignment);
13591 goto err;
13592 }
13593
13594 intel_fb->obj = obj;
13595
13596 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
13597 if (ret)
13598 goto err;
13599
13600 ret = drm_framebuffer_init(obj->base.dev,
13601 &intel_fb->base,
13602 &intel_fb_funcs);
13603 if (ret) {
13604 DRM_ERROR("framebuffer init failed %d\n", ret);
13605 goto err;
13606 }
13607
13608 return 0;
13609
13610 err:
13611 i915_gem_object_lock(obj);
13612 obj->framebuffer_references--;
13613 i915_gem_object_unlock(obj);
13614 return ret;
13615 }
13616
13617 static struct drm_framebuffer *
13618 intel_user_framebuffer_create(struct drm_device *dev,
13619 struct drm_file *filp,
13620 const struct drm_mode_fb_cmd2 *user_mode_cmd)
13621 {
13622 struct drm_framebuffer *fb;
13623 struct drm_i915_gem_object *obj;
13624 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
13625
13626 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
13627 if (!obj)
13628 return ERR_PTR(-ENOENT);
13629
13630 fb = intel_framebuffer_create(obj, &mode_cmd);
13631 if (IS_ERR(fb))
13632 i915_gem_object_put(obj);
13633
13634 return fb;
13635 }
13636
13637 static void intel_atomic_state_free(struct drm_atomic_state *state)
13638 {
13639 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13640
13641 drm_atomic_state_default_release(state);
13642
13643 i915_sw_fence_fini(&intel_state->commit_ready);
13644
13645 kfree(state);
13646 }
13647
13648 static const struct drm_mode_config_funcs intel_mode_funcs = {
13649 .fb_create = intel_user_framebuffer_create,
13650 .output_poll_changed = intel_fbdev_output_poll_changed,
13651 .atomic_check = intel_atomic_check,
13652 .atomic_commit = intel_atomic_commit,
13653 .atomic_state_alloc = intel_atomic_state_alloc,
13654 .atomic_state_clear = intel_atomic_state_clear,
13655 .atomic_state_free = intel_atomic_state_free,
13656 };
13657
13658 /**
13659 * intel_init_display_hooks - initialize the display modesetting hooks
13660 * @dev_priv: device private
13661 */
13662 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
13663 {
13664 intel_init_cdclk_hooks(dev_priv);
13665
13666 if (INTEL_INFO(dev_priv)->gen >= 9) {
13667 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13668 dev_priv->display.get_initial_plane_config =
13669 skylake_get_initial_plane_config;
13670 dev_priv->display.crtc_compute_clock =
13671 haswell_crtc_compute_clock;
13672 dev_priv->display.crtc_enable = haswell_crtc_enable;
13673 dev_priv->display.crtc_disable = haswell_crtc_disable;
13674 } else if (HAS_DDI(dev_priv)) {
13675 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13676 dev_priv->display.get_initial_plane_config =
13677 ironlake_get_initial_plane_config;
13678 dev_priv->display.crtc_compute_clock =
13679 haswell_crtc_compute_clock;
13680 dev_priv->display.crtc_enable = haswell_crtc_enable;
13681 dev_priv->display.crtc_disable = haswell_crtc_disable;
13682 } else if (HAS_PCH_SPLIT(dev_priv)) {
13683 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13684 dev_priv->display.get_initial_plane_config =
13685 ironlake_get_initial_plane_config;
13686 dev_priv->display.crtc_compute_clock =
13687 ironlake_crtc_compute_clock;
13688 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13689 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13690 } else if (IS_CHERRYVIEW(dev_priv)) {
13691 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13692 dev_priv->display.get_initial_plane_config =
13693 i9xx_get_initial_plane_config;
13694 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
13695 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13696 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13697 } else if (IS_VALLEYVIEW(dev_priv)) {
13698 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13699 dev_priv->display.get_initial_plane_config =
13700 i9xx_get_initial_plane_config;
13701 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
13702 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13703 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13704 } else if (IS_G4X(dev_priv)) {
13705 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13706 dev_priv->display.get_initial_plane_config =
13707 i9xx_get_initial_plane_config;
13708 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
13709 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13710 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13711 } else if (IS_PINEVIEW(dev_priv)) {
13712 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13713 dev_priv->display.get_initial_plane_config =
13714 i9xx_get_initial_plane_config;
13715 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
13716 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13717 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13718 } else if (!IS_GEN2(dev_priv)) {
13719 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13720 dev_priv->display.get_initial_plane_config =
13721 i9xx_get_initial_plane_config;
13722 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13723 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13724 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13725 } else {
13726 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13727 dev_priv->display.get_initial_plane_config =
13728 i9xx_get_initial_plane_config;
13729 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
13730 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13731 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13732 }
13733
13734 if (IS_GEN5(dev_priv)) {
13735 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13736 } else if (IS_GEN6(dev_priv)) {
13737 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13738 } else if (IS_IVYBRIDGE(dev_priv)) {
13739 /* FIXME: detect B0+ stepping and use auto training */
13740 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13741 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
13742 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13743 }
13744
13745 if (dev_priv->info.gen >= 9)
13746 dev_priv->display.update_crtcs = skl_update_crtcs;
13747 else
13748 dev_priv->display.update_crtcs = intel_update_crtcs;
13749 }
13750
13751 /*
13752 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13753 */
13754 static void quirk_ssc_force_disable(struct drm_device *dev)
13755 {
13756 struct drm_i915_private *dev_priv = to_i915(dev);
13757 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13758 DRM_INFO("applying lvds SSC disable quirk\n");
13759 }
13760
13761 /*
13762 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13763 * brightness value
13764 */
13765 static void quirk_invert_brightness(struct drm_device *dev)
13766 {
13767 struct drm_i915_private *dev_priv = to_i915(dev);
13768 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13769 DRM_INFO("applying inverted panel brightness quirk\n");
13770 }
13771
13772 /* Some VBT's incorrectly indicate no backlight is present */
13773 static void quirk_backlight_present(struct drm_device *dev)
13774 {
13775 struct drm_i915_private *dev_priv = to_i915(dev);
13776 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13777 DRM_INFO("applying backlight present quirk\n");
13778 }
13779
13780 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
13781 * which is 300 ms greater than eDP spec T12 min.
13782 */
13783 static void quirk_increase_t12_delay(struct drm_device *dev)
13784 {
13785 struct drm_i915_private *dev_priv = to_i915(dev);
13786
13787 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
13788 DRM_INFO("Applying T12 delay quirk\n");
13789 }
13790
13791 struct intel_quirk {
13792 int device;
13793 int subsystem_vendor;
13794 int subsystem_device;
13795 void (*hook)(struct drm_device *dev);
13796 };
13797
13798 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13799 struct intel_dmi_quirk {
13800 void (*hook)(struct drm_device *dev);
13801 const struct dmi_system_id (*dmi_id_list)[];
13802 };
13803
13804 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13805 {
13806 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13807 return 1;
13808 }
13809
13810 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13811 {
13812 .dmi_id_list = &(const struct dmi_system_id[]) {
13813 {
13814 .callback = intel_dmi_reverse_brightness,
13815 .ident = "NCR Corporation",
13816 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13817 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13818 },
13819 },
13820 { } /* terminating entry */
13821 },
13822 .hook = quirk_invert_brightness,
13823 },
13824 };
13825
13826 static struct intel_quirk intel_quirks[] = {
13827 /* Lenovo U160 cannot use SSC on LVDS */
13828 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13829
13830 /* Sony Vaio Y cannot use SSC on LVDS */
13831 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13832
13833 /* Acer Aspire 5734Z must invert backlight brightness */
13834 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13835
13836 /* Acer/eMachines G725 */
13837 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13838
13839 /* Acer/eMachines e725 */
13840 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13841
13842 /* Acer/Packard Bell NCL20 */
13843 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13844
13845 /* Acer Aspire 4736Z */
13846 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13847
13848 /* Acer Aspire 5336 */
13849 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13850
13851 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13852 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13853
13854 /* Acer C720 Chromebook (Core i3 4005U) */
13855 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13856
13857 /* Apple Macbook 2,1 (Core 2 T7400) */
13858 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13859
13860 /* Apple Macbook 4,1 */
13861 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
13862
13863 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13864 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13865
13866 /* HP Chromebook 14 (Celeron 2955U) */
13867 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13868
13869 /* Dell Chromebook 11 */
13870 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13871
13872 /* Dell Chromebook 11 (2015 version) */
13873 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
13874
13875 /* Toshiba Satellite P50-C-18C */
13876 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
13877 };
13878
13879 static void intel_init_quirks(struct drm_device *dev)
13880 {
13881 struct pci_dev *d = dev->pdev;
13882 int i;
13883
13884 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13885 struct intel_quirk *q = &intel_quirks[i];
13886
13887 if (d->device == q->device &&
13888 (d->subsystem_vendor == q->subsystem_vendor ||
13889 q->subsystem_vendor == PCI_ANY_ID) &&
13890 (d->subsystem_device == q->subsystem_device ||
13891 q->subsystem_device == PCI_ANY_ID))
13892 q->hook(dev);
13893 }
13894 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13895 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13896 intel_dmi_quirks[i].hook(dev);
13897 }
13898 }
13899
13900 /* Disable the VGA plane that we never use */
13901 static void i915_disable_vga(struct drm_i915_private *dev_priv)
13902 {
13903 struct pci_dev *pdev = dev_priv->drm.pdev;
13904 u8 sr1;
13905 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
13906
13907 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13908 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
13909 outb(SR01, VGA_SR_INDEX);
13910 sr1 = inb(VGA_SR_DATA);
13911 outb(sr1 | 1<<5, VGA_SR_DATA);
13912 vga_put(pdev, VGA_RSRC_LEGACY_IO);
13913 udelay(300);
13914
13915 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13916 POSTING_READ(vga_reg);
13917 }
13918
13919 void intel_modeset_init_hw(struct drm_device *dev)
13920 {
13921 struct drm_i915_private *dev_priv = to_i915(dev);
13922
13923 intel_update_cdclk(dev_priv);
13924 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
13925
13926 intel_init_clock_gating(dev_priv);
13927 }
13928
13929 /*
13930 * Calculate what we think the watermarks should be for the state we've read
13931 * out of the hardware and then immediately program those watermarks so that
13932 * we ensure the hardware settings match our internal state.
13933 *
13934 * We can calculate what we think WM's should be by creating a duplicate of the
13935 * current state (which was constructed during hardware readout) and running it
13936 * through the atomic check code to calculate new watermark values in the
13937 * state object.
13938 */
13939 static void sanitize_watermarks(struct drm_device *dev)
13940 {
13941 struct drm_i915_private *dev_priv = to_i915(dev);
13942 struct drm_atomic_state *state;
13943 struct intel_atomic_state *intel_state;
13944 struct drm_crtc *crtc;
13945 struct drm_crtc_state *cstate;
13946 struct drm_modeset_acquire_ctx ctx;
13947 int ret;
13948 int i;
13949
13950 /* Only supported on platforms that use atomic watermark design */
13951 if (!dev_priv->display.optimize_watermarks)
13952 return;
13953
13954 /*
13955 * We need to hold connection_mutex before calling duplicate_state so
13956 * that the connector loop is protected.
13957 */
13958 drm_modeset_acquire_init(&ctx, 0);
13959 retry:
13960 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13961 if (ret == -EDEADLK) {
13962 drm_modeset_backoff(&ctx);
13963 goto retry;
13964 } else if (WARN_ON(ret)) {
13965 goto fail;
13966 }
13967
13968 state = drm_atomic_helper_duplicate_state(dev, &ctx);
13969 if (WARN_ON(IS_ERR(state)))
13970 goto fail;
13971
13972 intel_state = to_intel_atomic_state(state);
13973
13974 /*
13975 * Hardware readout is the only time we don't want to calculate
13976 * intermediate watermarks (since we don't trust the current
13977 * watermarks).
13978 */
13979 if (!HAS_GMCH_DISPLAY(dev_priv))
13980 intel_state->skip_intermediate_wm = true;
13981
13982 ret = intel_atomic_check(dev, state);
13983 if (ret) {
13984 /*
13985 * If we fail here, it means that the hardware appears to be
13986 * programmed in a way that shouldn't be possible, given our
13987 * understanding of watermark requirements. This might mean a
13988 * mistake in the hardware readout code or a mistake in the
13989 * watermark calculations for a given platform. Raise a WARN
13990 * so that this is noticeable.
13991 *
13992 * If this actually happens, we'll have to just leave the
13993 * BIOS-programmed watermarks untouched and hope for the best.
13994 */
13995 WARN(true, "Could not determine valid watermarks for inherited state\n");
13996 goto put_state;
13997 }
13998
13999 /* Write calculated watermark values back */
14000 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14001 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14002
14003 cs->wm.need_postvbl_update = true;
14004 dev_priv->display.optimize_watermarks(intel_state, cs);
14005 }
14006
14007 put_state:
14008 drm_atomic_state_put(state);
14009 fail:
14010 drm_modeset_drop_locks(&ctx);
14011 drm_modeset_acquire_fini(&ctx);
14012 }
14013
14014 int intel_modeset_init(struct drm_device *dev)
14015 {
14016 struct drm_i915_private *dev_priv = to_i915(dev);
14017 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14018 enum pipe pipe;
14019 struct intel_crtc *crtc;
14020
14021 drm_mode_config_init(dev);
14022
14023 dev->mode_config.min_width = 0;
14024 dev->mode_config.min_height = 0;
14025
14026 dev->mode_config.preferred_depth = 24;
14027 dev->mode_config.prefer_shadow = 1;
14028
14029 dev->mode_config.allow_fb_modifiers = true;
14030
14031 dev->mode_config.funcs = &intel_mode_funcs;
14032
14033 init_llist_head(&dev_priv->atomic_helper.free_list);
14034 INIT_WORK(&dev_priv->atomic_helper.free_work,
14035 intel_atomic_helper_free_state_worker);
14036
14037 intel_init_quirks(dev);
14038
14039 intel_init_pm(dev_priv);
14040
14041 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14042 return 0;
14043
14044 /*
14045 * There may be no VBT; and if the BIOS enabled SSC we can
14046 * just keep using it to avoid unnecessary flicker. Whereas if the
14047 * BIOS isn't using it, don't assume it will work even if the VBT
14048 * indicates as much.
14049 */
14050 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14051 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14052 DREF_SSC1_ENABLE);
14053
14054 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14055 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14056 bios_lvds_use_ssc ? "en" : "dis",
14057 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14058 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14059 }
14060 }
14061
14062 if (IS_GEN2(dev_priv)) {
14063 dev->mode_config.max_width = 2048;
14064 dev->mode_config.max_height = 2048;
14065 } else if (IS_GEN3(dev_priv)) {
14066 dev->mode_config.max_width = 4096;
14067 dev->mode_config.max_height = 4096;
14068 } else {
14069 dev->mode_config.max_width = 8192;
14070 dev->mode_config.max_height = 8192;
14071 }
14072
14073 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14074 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14075 dev->mode_config.cursor_height = 1023;
14076 } else if (IS_GEN2(dev_priv)) {
14077 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14078 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14079 } else {
14080 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14081 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14082 }
14083
14084 dev->mode_config.fb_base = ggtt->mappable_base;
14085
14086 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14087 INTEL_INFO(dev_priv)->num_pipes,
14088 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14089
14090 for_each_pipe(dev_priv, pipe) {
14091 int ret;
14092
14093 ret = intel_crtc_init(dev_priv, pipe);
14094 if (ret) {
14095 drm_mode_config_cleanup(dev);
14096 return ret;
14097 }
14098 }
14099
14100 intel_shared_dpll_init(dev);
14101
14102 intel_update_czclk(dev_priv);
14103 intel_modeset_init_hw(dev);
14104
14105 if (dev_priv->max_cdclk_freq == 0)
14106 intel_update_max_cdclk(dev_priv);
14107
14108 /* Just disable it once at startup */
14109 i915_disable_vga(dev_priv);
14110 intel_setup_outputs(dev_priv);
14111
14112 drm_modeset_lock_all(dev);
14113 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14114 drm_modeset_unlock_all(dev);
14115
14116 for_each_intel_crtc(dev, crtc) {
14117 struct intel_initial_plane_config plane_config = {};
14118
14119 if (!crtc->active)
14120 continue;
14121
14122 /*
14123 * Note that reserving the BIOS fb up front prevents us
14124 * from stuffing other stolen allocations like the ring
14125 * on top. This prevents some ugliness at boot time, and
14126 * can even allow for smooth boot transitions if the BIOS
14127 * fb is large enough for the active pipe configuration.
14128 */
14129 dev_priv->display.get_initial_plane_config(crtc,
14130 &plane_config);
14131
14132 /*
14133 * If the fb is shared between multiple heads, we'll
14134 * just get the first one.
14135 */
14136 intel_find_initial_plane_obj(crtc, &plane_config);
14137 }
14138
14139 /*
14140 * Make sure hardware watermarks really match the state we read out.
14141 * Note that we need to do this after reconstructing the BIOS fb's
14142 * since the watermark calculation done here will use pstate->fb.
14143 */
14144 if (!HAS_GMCH_DISPLAY(dev_priv))
14145 sanitize_watermarks(dev);
14146
14147 return 0;
14148 }
14149
14150 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14151 {
14152 /* 640x480@60Hz, ~25175 kHz */
14153 struct dpll clock = {
14154 .m1 = 18,
14155 .m2 = 7,
14156 .p1 = 13,
14157 .p2 = 4,
14158 .n = 2,
14159 };
14160 u32 dpll, fp;
14161 int i;
14162
14163 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14164
14165 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14166 pipe_name(pipe), clock.vco, clock.dot);
14167
14168 fp = i9xx_dpll_compute_fp(&clock);
14169 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14170 DPLL_VGA_MODE_DIS |
14171 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14172 PLL_P2_DIVIDE_BY_4 |
14173 PLL_REF_INPUT_DREFCLK |
14174 DPLL_VCO_ENABLE;
14175
14176 I915_WRITE(FP0(pipe), fp);
14177 I915_WRITE(FP1(pipe), fp);
14178
14179 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14180 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14181 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14182 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14183 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14184 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14185 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14186
14187 /*
14188 * Apparently we need to have VGA mode enabled prior to changing
14189 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14190 * dividers, even though the register value does change.
14191 */
14192 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14193 I915_WRITE(DPLL(pipe), dpll);
14194
14195 /* Wait for the clocks to stabilize. */
14196 POSTING_READ(DPLL(pipe));
14197 udelay(150);
14198
14199 /* The pixel multiplier can only be updated once the
14200 * DPLL is enabled and the clocks are stable.
14201 *
14202 * So write it again.
14203 */
14204 I915_WRITE(DPLL(pipe), dpll);
14205
14206 /* We do this three times for luck */
14207 for (i = 0; i < 3 ; i++) {
14208 I915_WRITE(DPLL(pipe), dpll);
14209 POSTING_READ(DPLL(pipe));
14210 udelay(150); /* wait for warmup */
14211 }
14212
14213 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14214 POSTING_READ(PIPECONF(pipe));
14215 }
14216
14217 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14218 {
14219 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14220 pipe_name(pipe));
14221
14222 assert_plane_disabled(dev_priv, PLANE_A);
14223 assert_plane_disabled(dev_priv, PLANE_B);
14224
14225 I915_WRITE(PIPECONF(pipe), 0);
14226 POSTING_READ(PIPECONF(pipe));
14227
14228 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14229 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14230
14231 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14232 POSTING_READ(DPLL(pipe));
14233 }
14234
14235 static bool
14236 intel_check_plane_mapping(struct intel_crtc *crtc)
14237 {
14238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14239 u32 val;
14240
14241 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14242 return true;
14243
14244 val = I915_READ(DSPCNTR(!crtc->plane));
14245
14246 if ((val & DISPLAY_PLANE_ENABLE) &&
14247 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14248 return false;
14249
14250 return true;
14251 }
14252
14253 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14254 {
14255 struct drm_device *dev = crtc->base.dev;
14256 struct intel_encoder *encoder;
14257
14258 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14259 return true;
14260
14261 return false;
14262 }
14263
14264 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14265 {
14266 struct drm_device *dev = encoder->base.dev;
14267 struct intel_connector *connector;
14268
14269 for_each_connector_on_encoder(dev, &encoder->base, connector)
14270 return connector;
14271
14272 return NULL;
14273 }
14274
14275 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14276 enum transcoder pch_transcoder)
14277 {
14278 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14279 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14280 }
14281
14282 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14283 struct drm_modeset_acquire_ctx *ctx)
14284 {
14285 struct drm_device *dev = crtc->base.dev;
14286 struct drm_i915_private *dev_priv = to_i915(dev);
14287 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14288
14289 /* Clear any frame start delays used for debugging left by the BIOS */
14290 if (!transcoder_is_dsi(cpu_transcoder)) {
14291 i915_reg_t reg = PIPECONF(cpu_transcoder);
14292
14293 I915_WRITE(reg,
14294 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14295 }
14296
14297 /* restore vblank interrupts to correct state */
14298 drm_crtc_vblank_reset(&crtc->base);
14299 if (crtc->active) {
14300 struct intel_plane *plane;
14301
14302 drm_crtc_vblank_on(&crtc->base);
14303
14304 /* Disable everything but the primary plane */
14305 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14306 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14307 continue;
14308
14309 trace_intel_disable_plane(&plane->base, crtc);
14310 plane->disable_plane(plane, crtc);
14311 }
14312 }
14313
14314 /* We need to sanitize the plane -> pipe mapping first because this will
14315 * disable the crtc (and hence change the state) if it is wrong. Note
14316 * that gen4+ has a fixed plane -> pipe mapping. */
14317 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14318 bool plane;
14319
14320 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14321 crtc->base.base.id, crtc->base.name);
14322
14323 /* Pipe has the wrong plane attached and the plane is active.
14324 * Temporarily change the plane mapping and disable everything
14325 * ... */
14326 plane = crtc->plane;
14327 crtc->base.primary->state->visible = true;
14328 crtc->plane = !plane;
14329 intel_crtc_disable_noatomic(&crtc->base, ctx);
14330 crtc->plane = plane;
14331 }
14332
14333 /* Adjust the state of the output pipe according to whether we
14334 * have active connectors/encoders. */
14335 if (crtc->active && !intel_crtc_has_encoders(crtc))
14336 intel_crtc_disable_noatomic(&crtc->base, ctx);
14337
14338 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14339 /*
14340 * We start out with underrun reporting disabled to avoid races.
14341 * For correct bookkeeping mark this on active crtcs.
14342 *
14343 * Also on gmch platforms we dont have any hardware bits to
14344 * disable the underrun reporting. Which means we need to start
14345 * out with underrun reporting disabled also on inactive pipes,
14346 * since otherwise we'll complain about the garbage we read when
14347 * e.g. coming up after runtime pm.
14348 *
14349 * No protection against concurrent access is required - at
14350 * worst a fifo underrun happens which also sets this to false.
14351 */
14352 crtc->cpu_fifo_underrun_disabled = true;
14353 /*
14354 * We track the PCH trancoder underrun reporting state
14355 * within the crtc. With crtc for pipe A housing the underrun
14356 * reporting state for PCH transcoder A, crtc for pipe B housing
14357 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14358 * and marking underrun reporting as disabled for the non-existing
14359 * PCH transcoders B and C would prevent enabling the south
14360 * error interrupt (see cpt_can_enable_serr_int()).
14361 */
14362 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14363 crtc->pch_fifo_underrun_disabled = true;
14364 }
14365 }
14366
14367 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14368 {
14369 struct intel_connector *connector;
14370
14371 /* We need to check both for a crtc link (meaning that the
14372 * encoder is active and trying to read from a pipe) and the
14373 * pipe itself being active. */
14374 bool has_active_crtc = encoder->base.crtc &&
14375 to_intel_crtc(encoder->base.crtc)->active;
14376
14377 connector = intel_encoder_find_connector(encoder);
14378 if (connector && !has_active_crtc) {
14379 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14380 encoder->base.base.id,
14381 encoder->base.name);
14382
14383 /* Connector is active, but has no active pipe. This is
14384 * fallout from our resume register restoring. Disable
14385 * the encoder manually again. */
14386 if (encoder->base.crtc) {
14387 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14388
14389 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14390 encoder->base.base.id,
14391 encoder->base.name);
14392 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14393 if (encoder->post_disable)
14394 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14395 }
14396 encoder->base.crtc = NULL;
14397
14398 /* Inconsistent output/port/pipe state happens presumably due to
14399 * a bug in one of the get_hw_state functions. Or someplace else
14400 * in our code, like the register restore mess on resume. Clamp
14401 * things to off as a safer default. */
14402
14403 connector->base.dpms = DRM_MODE_DPMS_OFF;
14404 connector->base.encoder = NULL;
14405 }
14406 /* Enabled encoders without active connectors will be fixed in
14407 * the crtc fixup. */
14408 }
14409
14410 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14411 {
14412 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14413
14414 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14415 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14416 i915_disable_vga(dev_priv);
14417 }
14418 }
14419
14420 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14421 {
14422 /* This function can be called both from intel_modeset_setup_hw_state or
14423 * at a very early point in our resume sequence, where the power well
14424 * structures are not yet restored. Since this function is at a very
14425 * paranoid "someone might have enabled VGA while we were not looking"
14426 * level, just check if the power well is enabled instead of trying to
14427 * follow the "don't touch the power well if we don't need it" policy
14428 * the rest of the driver uses. */
14429 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14430 return;
14431
14432 i915_redisable_vga_power_on(dev_priv);
14433
14434 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14435 }
14436
14437 static bool primary_get_hw_state(struct intel_plane *plane)
14438 {
14439 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14440
14441 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14442 }
14443
14444 /* FIXME read out full plane state for all planes */
14445 static void readout_plane_state(struct intel_crtc *crtc)
14446 {
14447 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14448 bool visible;
14449
14450 visible = crtc->active && primary_get_hw_state(primary);
14451
14452 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14453 to_intel_plane_state(primary->base.state),
14454 visible);
14455 }
14456
14457 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14458 {
14459 struct drm_i915_private *dev_priv = to_i915(dev);
14460 enum pipe pipe;
14461 struct intel_crtc *crtc;
14462 struct intel_encoder *encoder;
14463 struct intel_connector *connector;
14464 struct drm_connector_list_iter conn_iter;
14465 int i;
14466
14467 dev_priv->active_crtcs = 0;
14468
14469 for_each_intel_crtc(dev, crtc) {
14470 struct intel_crtc_state *crtc_state =
14471 to_intel_crtc_state(crtc->base.state);
14472
14473 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14474 memset(crtc_state, 0, sizeof(*crtc_state));
14475 crtc_state->base.crtc = &crtc->base;
14476
14477 crtc_state->base.active = crtc_state->base.enable =
14478 dev_priv->display.get_pipe_config(crtc, crtc_state);
14479
14480 crtc->base.enabled = crtc_state->base.enable;
14481 crtc->active = crtc_state->base.active;
14482
14483 if (crtc_state->base.active)
14484 dev_priv->active_crtcs |= 1 << crtc->pipe;
14485
14486 readout_plane_state(crtc);
14487
14488 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14489 crtc->base.base.id, crtc->base.name,
14490 enableddisabled(crtc_state->base.active));
14491 }
14492
14493 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14494 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14495
14496 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14497 &pll->state.hw_state);
14498 pll->state.crtc_mask = 0;
14499 for_each_intel_crtc(dev, crtc) {
14500 struct intel_crtc_state *crtc_state =
14501 to_intel_crtc_state(crtc->base.state);
14502
14503 if (crtc_state->base.active &&
14504 crtc_state->shared_dpll == pll)
14505 pll->state.crtc_mask |= 1 << crtc->pipe;
14506 }
14507 pll->active_mask = pll->state.crtc_mask;
14508
14509 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14510 pll->name, pll->state.crtc_mask, pll->on);
14511 }
14512
14513 for_each_intel_encoder(dev, encoder) {
14514 pipe = 0;
14515
14516 if (encoder->get_hw_state(encoder, &pipe)) {
14517 struct intel_crtc_state *crtc_state;
14518
14519 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14520 crtc_state = to_intel_crtc_state(crtc->base.state);
14521
14522 encoder->base.crtc = &crtc->base;
14523 crtc_state->output_types |= 1 << encoder->type;
14524 encoder->get_config(encoder, crtc_state);
14525 } else {
14526 encoder->base.crtc = NULL;
14527 }
14528
14529 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14530 encoder->base.base.id, encoder->base.name,
14531 enableddisabled(encoder->base.crtc),
14532 pipe_name(pipe));
14533 }
14534
14535 drm_connector_list_iter_begin(dev, &conn_iter);
14536 for_each_intel_connector_iter(connector, &conn_iter) {
14537 if (connector->get_hw_state(connector)) {
14538 connector->base.dpms = DRM_MODE_DPMS_ON;
14539
14540 encoder = connector->encoder;
14541 connector->base.encoder = &encoder->base;
14542
14543 if (encoder->base.crtc &&
14544 encoder->base.crtc->state->active) {
14545 /*
14546 * This has to be done during hardware readout
14547 * because anything calling .crtc_disable may
14548 * rely on the connector_mask being accurate.
14549 */
14550 encoder->base.crtc->state->connector_mask |=
14551 1 << drm_connector_index(&connector->base);
14552 encoder->base.crtc->state->encoder_mask |=
14553 1 << drm_encoder_index(&encoder->base);
14554 }
14555
14556 } else {
14557 connector->base.dpms = DRM_MODE_DPMS_OFF;
14558 connector->base.encoder = NULL;
14559 }
14560 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14561 connector->base.base.id, connector->base.name,
14562 enableddisabled(connector->base.encoder));
14563 }
14564 drm_connector_list_iter_end(&conn_iter);
14565
14566 for_each_intel_crtc(dev, crtc) {
14567 struct intel_crtc_state *crtc_state =
14568 to_intel_crtc_state(crtc->base.state);
14569 int pixclk = 0;
14570
14571 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
14572 if (crtc_state->base.active) {
14573 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
14574 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
14575 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
14576
14577 /*
14578 * The initial mode needs to be set in order to keep
14579 * the atomic core happy. It wants a valid mode if the
14580 * crtc's enabled, so we do the above call.
14581 *
14582 * But we don't set all the derived state fully, hence
14583 * set a flag to indicate that a full recalculation is
14584 * needed on the next commit.
14585 */
14586 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
14587
14588 intel_crtc_compute_pixel_rate(crtc_state);
14589
14590 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
14591 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14592 pixclk = crtc_state->pixel_rate;
14593 else
14594 WARN_ON(dev_priv->display.modeset_calc_cdclk);
14595
14596 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
14597 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
14598 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
14599
14600 drm_calc_timestamping_constants(&crtc->base,
14601 &crtc_state->base.adjusted_mode);
14602 update_scanline_offset(crtc);
14603 }
14604
14605 dev_priv->min_pixclk[crtc->pipe] = pixclk;
14606
14607 intel_pipe_config_sanity_check(dev_priv, crtc_state);
14608 }
14609 }
14610
14611 static void
14612 get_encoder_power_domains(struct drm_i915_private *dev_priv)
14613 {
14614 struct intel_encoder *encoder;
14615
14616 for_each_intel_encoder(&dev_priv->drm, encoder) {
14617 u64 get_domains;
14618 enum intel_display_power_domain domain;
14619
14620 if (!encoder->get_power_domains)
14621 continue;
14622
14623 get_domains = encoder->get_power_domains(encoder);
14624 for_each_power_domain(domain, get_domains)
14625 intel_display_power_get(dev_priv, domain);
14626 }
14627 }
14628
14629 /* Scan out the current hw modeset state,
14630 * and sanitizes it to the current state
14631 */
14632 static void
14633 intel_modeset_setup_hw_state(struct drm_device *dev,
14634 struct drm_modeset_acquire_ctx *ctx)
14635 {
14636 struct drm_i915_private *dev_priv = to_i915(dev);
14637 enum pipe pipe;
14638 struct intel_crtc *crtc;
14639 struct intel_encoder *encoder;
14640 int i;
14641
14642 intel_modeset_readout_hw_state(dev);
14643
14644 /* HW state is read out, now we need to sanitize this mess. */
14645 get_encoder_power_domains(dev_priv);
14646
14647 for_each_intel_encoder(dev, encoder) {
14648 intel_sanitize_encoder(encoder);
14649 }
14650
14651 for_each_pipe(dev_priv, pipe) {
14652 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14653
14654 intel_sanitize_crtc(crtc, ctx);
14655 intel_dump_pipe_config(crtc, crtc->config,
14656 "[setup_hw_state]");
14657 }
14658
14659 intel_modeset_update_connector_atomic_state(dev);
14660
14661 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14662 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14663
14664 if (!pll->on || pll->active_mask)
14665 continue;
14666
14667 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14668
14669 pll->funcs.disable(dev_priv, pll);
14670 pll->on = false;
14671 }
14672
14673 if (IS_G4X(dev_priv)) {
14674 g4x_wm_get_hw_state(dev);
14675 g4x_wm_sanitize(dev_priv);
14676 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14677 vlv_wm_get_hw_state(dev);
14678 vlv_wm_sanitize(dev_priv);
14679 } else if (IS_GEN9(dev_priv)) {
14680 skl_wm_get_hw_state(dev);
14681 } else if (HAS_PCH_SPLIT(dev_priv)) {
14682 ilk_wm_get_hw_state(dev);
14683 }
14684
14685 for_each_intel_crtc(dev, crtc) {
14686 u64 put_domains;
14687
14688 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
14689 if (WARN_ON(put_domains))
14690 modeset_put_power_domains(dev_priv, put_domains);
14691 }
14692 intel_display_set_init_power(dev_priv, false);
14693
14694 intel_power_domains_verify_state(dev_priv);
14695
14696 intel_fbc_init_pipe_state(dev_priv);
14697 }
14698
14699 void intel_display_resume(struct drm_device *dev)
14700 {
14701 struct drm_i915_private *dev_priv = to_i915(dev);
14702 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
14703 struct drm_modeset_acquire_ctx ctx;
14704 int ret;
14705
14706 dev_priv->modeset_restore_state = NULL;
14707 if (state)
14708 state->acquire_ctx = &ctx;
14709
14710 drm_modeset_acquire_init(&ctx, 0);
14711
14712 while (1) {
14713 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14714 if (ret != -EDEADLK)
14715 break;
14716
14717 drm_modeset_backoff(&ctx);
14718 }
14719
14720 if (!ret)
14721 ret = __intel_display_resume(dev, state, &ctx);
14722
14723 drm_modeset_drop_locks(&ctx);
14724 drm_modeset_acquire_fini(&ctx);
14725
14726 if (ret)
14727 DRM_ERROR("Restoring old state failed with %i\n", ret);
14728 if (state)
14729 drm_atomic_state_put(state);
14730 }
14731
14732 void intel_modeset_gem_init(struct drm_device *dev)
14733 {
14734 struct drm_i915_private *dev_priv = to_i915(dev);
14735
14736 intel_init_gt_powersave(dev_priv);
14737
14738 intel_setup_overlay(dev_priv);
14739 }
14740
14741 int intel_connector_register(struct drm_connector *connector)
14742 {
14743 struct intel_connector *intel_connector = to_intel_connector(connector);
14744 int ret;
14745
14746 ret = intel_backlight_device_register(intel_connector);
14747 if (ret)
14748 goto err;
14749
14750 return 0;
14751
14752 err:
14753 return ret;
14754 }
14755
14756 void intel_connector_unregister(struct drm_connector *connector)
14757 {
14758 struct intel_connector *intel_connector = to_intel_connector(connector);
14759
14760 intel_backlight_device_unregister(intel_connector);
14761 intel_panel_destroy_backlight(connector);
14762 }
14763
14764 void intel_modeset_cleanup(struct drm_device *dev)
14765 {
14766 struct drm_i915_private *dev_priv = to_i915(dev);
14767
14768 flush_work(&dev_priv->atomic_helper.free_work);
14769 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
14770
14771 intel_disable_gt_powersave(dev_priv);
14772
14773 /*
14774 * Interrupts and polling as the first thing to avoid creating havoc.
14775 * Too much stuff here (turning of connectors, ...) would
14776 * experience fancy races otherwise.
14777 */
14778 intel_irq_uninstall(dev_priv);
14779
14780 /*
14781 * Due to the hpd irq storm handling the hotplug work can re-arm the
14782 * poll handlers. Hence disable polling after hpd handling is shut down.
14783 */
14784 drm_kms_helper_poll_fini(dev);
14785
14786 /* poll work can call into fbdev, hence clean that up afterwards */
14787 intel_fbdev_fini(dev_priv);
14788
14789 intel_unregister_dsm_handler();
14790
14791 intel_fbc_global_disable(dev_priv);
14792
14793 /* flush any delayed tasks or pending work */
14794 flush_scheduled_work();
14795
14796 drm_mode_config_cleanup(dev);
14797
14798 intel_cleanup_overlay(dev_priv);
14799
14800 intel_cleanup_gt_powersave(dev_priv);
14801
14802 intel_teardown_gmbus(dev_priv);
14803 }
14804
14805 void intel_connector_attach_encoder(struct intel_connector *connector,
14806 struct intel_encoder *encoder)
14807 {
14808 connector->encoder = encoder;
14809 drm_mode_connector_attach_encoder(&connector->base,
14810 &encoder->base);
14811 }
14812
14813 /*
14814 * set vga decode state - true == enable VGA decode
14815 */
14816 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
14817 {
14818 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14819 u16 gmch_ctrl;
14820
14821 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14822 DRM_ERROR("failed to read control word\n");
14823 return -EIO;
14824 }
14825
14826 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14827 return 0;
14828
14829 if (state)
14830 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14831 else
14832 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14833
14834 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14835 DRM_ERROR("failed to write control word\n");
14836 return -EIO;
14837 }
14838
14839 return 0;
14840 }
14841
14842 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
14843
14844 struct intel_display_error_state {
14845
14846 u32 power_well_driver;
14847
14848 int num_transcoders;
14849
14850 struct intel_cursor_error_state {
14851 u32 control;
14852 u32 position;
14853 u32 base;
14854 u32 size;
14855 } cursor[I915_MAX_PIPES];
14856
14857 struct intel_pipe_error_state {
14858 bool power_domain_on;
14859 u32 source;
14860 u32 stat;
14861 } pipe[I915_MAX_PIPES];
14862
14863 struct intel_plane_error_state {
14864 u32 control;
14865 u32 stride;
14866 u32 size;
14867 u32 pos;
14868 u32 addr;
14869 u32 surface;
14870 u32 tile_offset;
14871 } plane[I915_MAX_PIPES];
14872
14873 struct intel_transcoder_error_state {
14874 bool power_domain_on;
14875 enum transcoder cpu_transcoder;
14876
14877 u32 conf;
14878
14879 u32 htotal;
14880 u32 hblank;
14881 u32 hsync;
14882 u32 vtotal;
14883 u32 vblank;
14884 u32 vsync;
14885 } transcoder[4];
14886 };
14887
14888 struct intel_display_error_state *
14889 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
14890 {
14891 struct intel_display_error_state *error;
14892 int transcoders[] = {
14893 TRANSCODER_A,
14894 TRANSCODER_B,
14895 TRANSCODER_C,
14896 TRANSCODER_EDP,
14897 };
14898 int i;
14899
14900 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14901 return NULL;
14902
14903 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14904 if (error == NULL)
14905 return NULL;
14906
14907 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
14908 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14909
14910 for_each_pipe(dev_priv, i) {
14911 error->pipe[i].power_domain_on =
14912 __intel_display_power_is_enabled(dev_priv,
14913 POWER_DOMAIN_PIPE(i));
14914 if (!error->pipe[i].power_domain_on)
14915 continue;
14916
14917 error->cursor[i].control = I915_READ(CURCNTR(i));
14918 error->cursor[i].position = I915_READ(CURPOS(i));
14919 error->cursor[i].base = I915_READ(CURBASE(i));
14920
14921 error->plane[i].control = I915_READ(DSPCNTR(i));
14922 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14923 if (INTEL_GEN(dev_priv) <= 3) {
14924 error->plane[i].size = I915_READ(DSPSIZE(i));
14925 error->plane[i].pos = I915_READ(DSPPOS(i));
14926 }
14927 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
14928 error->plane[i].addr = I915_READ(DSPADDR(i));
14929 if (INTEL_GEN(dev_priv) >= 4) {
14930 error->plane[i].surface = I915_READ(DSPSURF(i));
14931 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14932 }
14933
14934 error->pipe[i].source = I915_READ(PIPESRC(i));
14935
14936 if (HAS_GMCH_DISPLAY(dev_priv))
14937 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14938 }
14939
14940 /* Note: this does not include DSI transcoders. */
14941 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
14942 if (HAS_DDI(dev_priv))
14943 error->num_transcoders++; /* Account for eDP. */
14944
14945 for (i = 0; i < error->num_transcoders; i++) {
14946 enum transcoder cpu_transcoder = transcoders[i];
14947
14948 error->transcoder[i].power_domain_on =
14949 __intel_display_power_is_enabled(dev_priv,
14950 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14951 if (!error->transcoder[i].power_domain_on)
14952 continue;
14953
14954 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14955
14956 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14957 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14958 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14959 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14960 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14961 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14962 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14963 }
14964
14965 return error;
14966 }
14967
14968 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14969
14970 void
14971 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14972 struct intel_display_error_state *error)
14973 {
14974 struct drm_i915_private *dev_priv = m->i915;
14975 int i;
14976
14977 if (!error)
14978 return;
14979
14980 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
14981 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
14982 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14983 error->power_well_driver);
14984 for_each_pipe(dev_priv, i) {
14985 err_printf(m, "Pipe [%d]:\n", i);
14986 err_printf(m, " Power: %s\n",
14987 onoff(error->pipe[i].power_domain_on));
14988 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14989 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14990
14991 err_printf(m, "Plane [%d]:\n", i);
14992 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14993 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14994 if (INTEL_GEN(dev_priv) <= 3) {
14995 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14996 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14997 }
14998 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
14999 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15000 if (INTEL_GEN(dev_priv) >= 4) {
15001 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15002 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15003 }
15004
15005 err_printf(m, "Cursor [%d]:\n", i);
15006 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15007 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15008 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15009 }
15010
15011 for (i = 0; i < error->num_transcoders; i++) {
15012 err_printf(m, "CPU transcoder: %s\n",
15013 transcoder_name(error->transcoder[i].cpu_transcoder));
15014 err_printf(m, " Power: %s\n",
15015 onoff(error->transcoder[i].power_domain_on));
15016 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15017 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15018 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15019 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15020 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15021 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15022 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15023 }
15024 }
15025
15026 #endif
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