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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev,
124 struct drm_modeset_acquire_ctx *ctx);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126
127 struct intel_limit {
128 struct {
129 int min, max;
130 } dot, vco, n, m, m1, m2, p, p1;
131
132 struct {
133 int dot_limit;
134 int p2_slow, p2_fast;
135 } p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154 {
155 u32 val;
156 int divider;
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 }
170
171 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
172 const char *name, u32 reg)
173 {
174 if (dev_priv->hpll_freq == 0)
175 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
176
177 return vlv_get_cck_clock(dev_priv, name, reg,
178 dev_priv->hpll_freq);
179 }
180
181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 {
183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
184 return;
185
186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
187 CCK_CZ_CLOCK_CONTROL);
188
189 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
190 }
191
192 static inline u32 /* units of 100MHz */
193 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
194 const struct intel_crtc_state *pipe_config)
195 {
196 if (HAS_DDI(dev_priv))
197 return pipe_config->port_clock; /* SPLL */
198 else if (IS_GEN5(dev_priv))
199 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
200 else
201 return 270000;
202 }
203
204 static const struct intel_limit intel_limits_i8xx_dac = {
205 .dot = { .min = 25000, .max = 350000 },
206 .vco = { .min = 908000, .max = 1512000 },
207 .n = { .min = 2, .max = 16 },
208 .m = { .min = 96, .max = 140 },
209 .m1 = { .min = 18, .max = 26 },
210 .m2 = { .min = 6, .max = 16 },
211 .p = { .min = 4, .max = 128 },
212 .p1 = { .min = 2, .max = 33 },
213 .p2 = { .dot_limit = 165000,
214 .p2_slow = 4, .p2_fast = 2 },
215 };
216
217 static const struct intel_limit intel_limits_i8xx_dvo = {
218 .dot = { .min = 25000, .max = 350000 },
219 .vco = { .min = 908000, .max = 1512000 },
220 .n = { .min = 2, .max = 16 },
221 .m = { .min = 96, .max = 140 },
222 .m1 = { .min = 18, .max = 26 },
223 .m2 = { .min = 6, .max = 16 },
224 .p = { .min = 4, .max = 128 },
225 .p1 = { .min = 2, .max = 33 },
226 .p2 = { .dot_limit = 165000,
227 .p2_slow = 4, .p2_fast = 4 },
228 };
229
230 static const struct intel_limit intel_limits_i8xx_lvds = {
231 .dot = { .min = 25000, .max = 350000 },
232 .vco = { .min = 908000, .max = 1512000 },
233 .n = { .min = 2, .max = 16 },
234 .m = { .min = 96, .max = 140 },
235 .m1 = { .min = 18, .max = 26 },
236 .m2 = { .min = 6, .max = 16 },
237 .p = { .min = 4, .max = 128 },
238 .p1 = { .min = 1, .max = 6 },
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 14, .p2_fast = 7 },
241 };
242
243 static const struct intel_limit intel_limits_i9xx_sdvo = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1400000, .max = 2800000 },
246 .n = { .min = 1, .max = 6 },
247 .m = { .min = 70, .max = 120 },
248 .m1 = { .min = 8, .max = 18 },
249 .m2 = { .min = 3, .max = 7 },
250 .p = { .min = 5, .max = 80 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 200000,
253 .p2_slow = 10, .p2_fast = 5 },
254 };
255
256 static const struct intel_limit intel_limits_i9xx_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1400000, .max = 2800000 },
259 .n = { .min = 1, .max = 6 },
260 .m = { .min = 70, .max = 120 },
261 .m1 = { .min = 8, .max = 18 },
262 .m2 = { .min = 3, .max = 7 },
263 .p = { .min = 7, .max = 98 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 7 },
267 };
268
269
270 static const struct intel_limit intel_limits_g4x_sdvo = {
271 .dot = { .min = 25000, .max = 270000 },
272 .vco = { .min = 1750000, .max = 3500000},
273 .n = { .min = 1, .max = 4 },
274 .m = { .min = 104, .max = 138 },
275 .m1 = { .min = 17, .max = 23 },
276 .m2 = { .min = 5, .max = 11 },
277 .p = { .min = 10, .max = 30 },
278 .p1 = { .min = 1, .max = 3},
279 .p2 = { .dot_limit = 270000,
280 .p2_slow = 10,
281 .p2_fast = 10
282 },
283 };
284
285 static const struct intel_limit intel_limits_g4x_hdmi = {
286 .dot = { .min = 22000, .max = 400000 },
287 .vco = { .min = 1750000, .max = 3500000},
288 .n = { .min = 1, .max = 4 },
289 .m = { .min = 104, .max = 138 },
290 .m1 = { .min = 16, .max = 23 },
291 .m2 = { .min = 5, .max = 11 },
292 .p = { .min = 5, .max = 80 },
293 .p1 = { .min = 1, .max = 8},
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 10, .p2_fast = 5 },
296 };
297
298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
299 .dot = { .min = 20000, .max = 115000 },
300 .vco = { .min = 1750000, .max = 3500000 },
301 .n = { .min = 1, .max = 3 },
302 .m = { .min = 104, .max = 138 },
303 .m1 = { .min = 17, .max = 23 },
304 .m2 = { .min = 5, .max = 11 },
305 .p = { .min = 28, .max = 112 },
306 .p1 = { .min = 2, .max = 8 },
307 .p2 = { .dot_limit = 0,
308 .p2_slow = 14, .p2_fast = 14
309 },
310 };
311
312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
313 .dot = { .min = 80000, .max = 224000 },
314 .vco = { .min = 1750000, .max = 3500000 },
315 .n = { .min = 1, .max = 3 },
316 .m = { .min = 104, .max = 138 },
317 .m1 = { .min = 17, .max = 23 },
318 .m2 = { .min = 5, .max = 11 },
319 .p = { .min = 14, .max = 42 },
320 .p1 = { .min = 2, .max = 6 },
321 .p2 = { .dot_limit = 0,
322 .p2_slow = 7, .p2_fast = 7
323 },
324 };
325
326 static const struct intel_limit intel_limits_pineview_sdvo = {
327 .dot = { .min = 20000, .max = 400000},
328 .vco = { .min = 1700000, .max = 3500000 },
329 /* Pineview's Ncounter is a ring counter */
330 .n = { .min = 3, .max = 6 },
331 .m = { .min = 2, .max = 256 },
332 /* Pineview only has one combined m divider, which we treat as m2. */
333 .m1 = { .min = 0, .max = 0 },
334 .m2 = { .min = 0, .max = 254 },
335 .p = { .min = 5, .max = 80 },
336 .p1 = { .min = 1, .max = 8 },
337 .p2 = { .dot_limit = 200000,
338 .p2_slow = 10, .p2_fast = 5 },
339 };
340
341 static const struct intel_limit intel_limits_pineview_lvds = {
342 .dot = { .min = 20000, .max = 400000 },
343 .vco = { .min = 1700000, .max = 3500000 },
344 .n = { .min = 3, .max = 6 },
345 .m = { .min = 2, .max = 256 },
346 .m1 = { .min = 0, .max = 0 },
347 .m2 = { .min = 0, .max = 254 },
348 .p = { .min = 7, .max = 112 },
349 .p1 = { .min = 1, .max = 8 },
350 .p2 = { .dot_limit = 112000,
351 .p2_slow = 14, .p2_fast = 14 },
352 };
353
354 /* Ironlake / Sandybridge
355 *
356 * We calculate clock using (register_value + 2) for N/M1/M2, so here
357 * the range value for them is (actual_value - 2).
358 */
359 static const struct intel_limit intel_limits_ironlake_dac = {
360 .dot = { .min = 25000, .max = 350000 },
361 .vco = { .min = 1760000, .max = 3510000 },
362 .n = { .min = 1, .max = 5 },
363 .m = { .min = 79, .max = 127 },
364 .m1 = { .min = 12, .max = 22 },
365 .m2 = { .min = 5, .max = 9 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 225000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
373 .dot = { .min = 25000, .max = 350000 },
374 .vco = { .min = 1760000, .max = 3510000 },
375 .n = { .min = 1, .max = 3 },
376 .m = { .min = 79, .max = 118 },
377 .m1 = { .min = 12, .max = 22 },
378 .m2 = { .min = 5, .max = 9 },
379 .p = { .min = 28, .max = 112 },
380 .p1 = { .min = 2, .max = 8 },
381 .p2 = { .dot_limit = 225000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
386 .dot = { .min = 25000, .max = 350000 },
387 .vco = { .min = 1760000, .max = 3510000 },
388 .n = { .min = 1, .max = 3 },
389 .m = { .min = 79, .max = 127 },
390 .m1 = { .min = 12, .max = 22 },
391 .m2 = { .min = 5, .max = 9 },
392 .p = { .min = 14, .max = 56 },
393 .p1 = { .min = 2, .max = 8 },
394 .p2 = { .dot_limit = 225000,
395 .p2_slow = 7, .p2_fast = 7 },
396 };
397
398 /* LVDS 100mhz refclk limits. */
399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
400 .dot = { .min = 25000, .max = 350000 },
401 .vco = { .min = 1760000, .max = 3510000 },
402 .n = { .min = 1, .max = 2 },
403 .m = { .min = 79, .max = 126 },
404 .m1 = { .min = 12, .max = 22 },
405 .m2 = { .min = 5, .max = 9 },
406 .p = { .min = 28, .max = 112 },
407 .p1 = { .min = 2, .max = 8 },
408 .p2 = { .dot_limit = 225000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 3 },
416 .m = { .min = 79, .max = 126 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 14, .max = 42 },
420 .p1 = { .min = 2, .max = 6 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 7, .p2_fast = 7 },
423 };
424
425 static const struct intel_limit intel_limits_vlv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
433 .vco = { .min = 4000000, .max = 6000000 },
434 .n = { .min = 1, .max = 7 },
435 .m1 = { .min = 2, .max = 3 },
436 .m2 = { .min = 11, .max = 156 },
437 .p1 = { .min = 2, .max = 3 },
438 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
439 };
440
441 static const struct intel_limit intel_limits_chv = {
442 /*
443 * These are the data rate limits (measured in fast clocks)
444 * since those are the strictest limits we have. The fast
445 * clock and actual rate limits are more relaxed, so checking
446 * them would make no difference.
447 */
448 .dot = { .min = 25000 * 5, .max = 540000 * 5},
449 .vco = { .min = 4800000, .max = 6480000 },
450 .n = { .min = 1, .max = 1 },
451 .m1 = { .min = 2, .max = 2 },
452 .m2 = { .min = 24 << 22, .max = 175 << 22 },
453 .p1 = { .min = 2, .max = 4 },
454 .p2 = { .p2_slow = 1, .p2_fast = 14 },
455 };
456
457 static const struct intel_limit intel_limits_bxt = {
458 /* FIXME: find real dot limits */
459 .dot = { .min = 0, .max = INT_MAX },
460 .vco = { .min = 4800000, .max = 6700000 },
461 .n = { .min = 1, .max = 1 },
462 .m1 = { .min = 2, .max = 2 },
463 /* FIXME: find real m2 limits */
464 .m2 = { .min = 2 << 22, .max = 255 << 22 },
465 .p1 = { .min = 2, .max = 4 },
466 .p2 = { .p2_slow = 1, .p2_fast = 20 },
467 };
468
469 static bool
470 needs_modeset(struct drm_crtc_state *state)
471 {
472 return drm_atomic_crtc_needs_modeset(state);
473 }
474
475 /*
476 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
477 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
478 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
479 * The helpers' return value is the rate of the clock that is fed to the
480 * display engine's pipe which can be the above fast dot clock rate or a
481 * divided-down version of it.
482 */
483 /* m1 is reserved as 0 in Pineview, n is a ring counter */
484 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
485 {
486 clock->m = clock->m2 + 2;
487 clock->p = clock->p1 * clock->p2;
488 if (WARN_ON(clock->n == 0 || clock->p == 0))
489 return 0;
490 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
491 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
492
493 return clock->dot;
494 }
495
496 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
497 {
498 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
499 }
500
501 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
502 {
503 clock->m = i9xx_dpll_compute_m(clock);
504 clock->p = clock->p1 * clock->p2;
505 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
506 return 0;
507 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
508 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
509
510 return clock->dot;
511 }
512
513 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
514 {
515 clock->m = clock->m1 * clock->m2;
516 clock->p = clock->p1 * clock->p2;
517 if (WARN_ON(clock->n == 0 || clock->p == 0))
518 return 0;
519 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
520 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
521
522 return clock->dot / 5;
523 }
524
525 int chv_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = clock->m1 * clock->m2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
532 clock->n << 22);
533 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534
535 return clock->dot / 5;
536 }
537
538 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 /**
540 * Returns whether the given set of divisors are valid for a given refclk with
541 * the given connectors.
542 */
543
544 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
545 const struct intel_limit *limit,
546 const struct dpll *clock)
547 {
548 if (clock->n < limit->n.min || limit->n.max < clock->n)
549 INTELPllInvalid("n out of range\n");
550 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
551 INTELPllInvalid("p1 out of range\n");
552 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
553 INTELPllInvalid("m2 out of range\n");
554 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
555 INTELPllInvalid("m1 out of range\n");
556
557 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
558 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
561
562 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
563 !IS_GEN9_LP(dev_priv)) {
564 if (clock->p < limit->p.min || limit->p.max < clock->p)
565 INTELPllInvalid("p out of range\n");
566 if (clock->m < limit->m.min || limit->m.max < clock->m)
567 INTELPllInvalid("m out of range\n");
568 }
569
570 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
571 INTELPllInvalid("vco out of range\n");
572 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
573 * connector, etc., rather than just a single range.
574 */
575 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
576 INTELPllInvalid("dot out of range\n");
577
578 return true;
579 }
580
581 static int
582 i9xx_select_p2_div(const struct intel_limit *limit,
583 const struct intel_crtc_state *crtc_state,
584 int target)
585 {
586 struct drm_device *dev = crtc_state->base.crtc->dev;
587
588 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 /*
590 * For LVDS just rely on its current settings for dual-channel.
591 * We haven't figured out how to reliably set up different
592 * single/dual channel state, if we even can.
593 */
594 if (intel_is_dual_link_lvds(dev))
595 return limit->p2.p2_fast;
596 else
597 return limit->p2.p2_slow;
598 } else {
599 if (target < limit->p2.dot_limit)
600 return limit->p2.p2_slow;
601 else
602 return limit->p2.p2_fast;
603 }
604 }
605
606 /*
607 * Returns a set of divisors for the desired target clock with the given
608 * refclk, or FALSE. The returned values represent the clock equation:
609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
610 *
611 * Target and reference clocks are specified in kHz.
612 *
613 * If match_clock is provided, then best_clock P divider must match the P
614 * divider from @match_clock used for LVDS downclocking.
615 */
616 static bool
617 i9xx_find_best_dpll(const struct intel_limit *limit,
618 struct intel_crtc_state *crtc_state,
619 int target, int refclk, struct dpll *match_clock,
620 struct dpll *best_clock)
621 {
622 struct drm_device *dev = crtc_state->base.crtc->dev;
623 struct dpll clock;
624 int err = target;
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_calc_dpll_params(refclk, &clock);
643 if (!intel_PLL_is_valid(to_i915(dev),
644 limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 pnv_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 for (clock.n = limit->n.min;
693 clock.n <= limit->n.max; clock.n++) {
694 for (clock.p1 = limit->p1.min;
695 clock.p1 <= limit->p1.max; clock.p1++) {
696 int this_err;
697
698 pnv_calc_dpll_params(refclk, &clock);
699 if (!intel_PLL_is_valid(to_i915(dev),
700 limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 /*
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724 *
725 * Target and reference clocks are specified in kHz.
726 *
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
729 */
730 static bool
731 g4x_find_best_dpll(const struct intel_limit *limit,
732 struct intel_crtc_state *crtc_state,
733 int target, int refclk, struct dpll *match_clock,
734 struct dpll *best_clock)
735 {
736 struct drm_device *dev = crtc_state->base.crtc->dev;
737 struct dpll clock;
738 int max_n;
739 bool found = false;
740 /* approximately equals target * 0.00585 */
741 int err_most = (target >> 8) + (target >> 9);
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_calc_dpll_params(refclk, &clock);
760 if (!intel_PLL_is_valid(to_i915(dev),
761 limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const struct dpll *calculated_clock,
785 const struct dpll *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(to_i915(dev))) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 /*
820 * Returns a set of divisors for the desired target clock with the given
821 * refclk, or FALSE. The returned values represent the clock equation:
822 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 */
824 static bool
825 vlv_find_best_dpll(const struct intel_limit *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, struct dpll *match_clock,
828 struct dpll *best_clock)
829 {
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct dpll clock;
833 unsigned int bestppm = 1000000;
834 /* min update 19.2 MHz */
835 int max_n = min(limit->n.max, refclk / 19200);
836 bool found = false;
837
838 target *= 5; /* fast clock */
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
844 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
845 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
846 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
847 clock.p = clock.p1 * clock.p2;
848 /* based on hardware requirement, prefer bigger m1,m2 values */
849 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
850 unsigned int ppm;
851
852 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
853 refclk * clock.m1);
854
855 vlv_calc_dpll_params(refclk, &clock);
856
857 if (!intel_PLL_is_valid(to_i915(dev),
858 limit,
859 &clock))
860 continue;
861
862 if (!vlv_PLL_is_optimal(dev, target,
863 &clock,
864 best_clock,
865 bestppm, &ppm))
866 continue;
867
868 *best_clock = clock;
869 bestppm = ppm;
870 found = true;
871 }
872 }
873 }
874 }
875
876 return found;
877 }
878
879 /*
880 * Returns a set of divisors for the desired target clock with the given
881 * refclk, or FALSE. The returned values represent the clock equation:
882 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
883 */
884 static bool
885 chv_find_best_dpll(const struct intel_limit *limit,
886 struct intel_crtc_state *crtc_state,
887 int target, int refclk, struct dpll *match_clock,
888 struct dpll *best_clock)
889 {
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
891 struct drm_device *dev = crtc->base.dev;
892 unsigned int best_error_ppm;
893 struct dpll clock;
894 uint64_t m2;
895 int found = false;
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 best_error_ppm = 1000000;
899
900 /*
901 * Based on hardware doc, the n always set to 1, and m1 always
902 * set to 2. If requires to support 200Mhz refclk, we need to
903 * revisit this because n may not 1 anymore.
904 */
905 clock.n = 1, clock.m1 = 2;
906 target *= 5; /* fast clock */
907
908 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
909 for (clock.p2 = limit->p2.p2_fast;
910 clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 unsigned int error_ppm;
913
914 clock.p = clock.p1 * clock.p2;
915
916 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
917 clock.n) << 22, refclk * clock.m1);
918
919 if (m2 > INT_MAX/clock.m1)
920 continue;
921
922 clock.m2 = m2;
923
924 chv_calc_dpll_params(refclk, &clock);
925
926 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
927 continue;
928
929 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
930 best_error_ppm, &error_ppm))
931 continue;
932
933 *best_clock = clock;
934 best_error_ppm = error_ppm;
935 found = true;
936 }
937 }
938
939 return found;
940 }
941
942 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
943 struct dpll *best_clock)
944 {
945 int refclk = 100000;
946 const struct intel_limit *limit = &intel_limits_bxt;
947
948 return chv_find_best_dpll(limit, crtc_state,
949 target_clock, refclk, NULL, best_clock);
950 }
951
952 bool intel_crtc_active(struct intel_crtc *crtc)
953 {
954 /* Be paranoid as we can arrive here with only partial
955 * state retrieved from the hardware during setup.
956 *
957 * We can ditch the adjusted_mode.crtc_clock check as soon
958 * as Haswell has gained clock readout/fastboot support.
959 *
960 * We can ditch the crtc->primary->fb check as soon as we can
961 * properly reconstruct framebuffers.
962 *
963 * FIXME: The intel_crtc->active here should be switched to
964 * crtc->state->active once we have proper CRTC states wired up
965 * for atomic.
966 */
967 return crtc->active && crtc->base.primary->state->fb &&
968 crtc->config->base.adjusted_mode.crtc_clock;
969 }
970
971 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
972 enum pipe pipe)
973 {
974 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
975
976 return crtc->config->cpu_transcoder;
977 }
978
979 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
980 {
981 i915_reg_t reg = PIPEDSL(pipe);
982 u32 line1, line2;
983 u32 line_mask;
984
985 if (IS_GEN2(dev_priv))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 line1 = I915_READ(reg) & line_mask;
991 msleep(5);
992 line2 = I915_READ(reg) & line_mask;
993
994 return line1 == line2;
995 }
996
997 /*
998 * intel_wait_for_pipe_off - wait for pipe to turn off
999 * @crtc: crtc whose pipe to wait for
1000 *
1001 * After disabling a pipe, we can't wait for vblank in the usual way,
1002 * spinning on the vblank interrupt status bit, since we won't actually
1003 * see an interrupt when the pipe is disabled.
1004 *
1005 * On Gen4 and above:
1006 * wait for the pipe register state bit to turn off
1007 *
1008 * Otherwise:
1009 * wait for the display line value to settle (it usually
1010 * ends up stopping at the start of the next frame).
1011 *
1012 */
1013 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 {
1015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1016 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1017 enum pipe pipe = crtc->pipe;
1018
1019 if (INTEL_GEN(dev_priv) >= 4) {
1020 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021
1022 /* Wait for the Pipe State to go off */
1023 if (intel_wait_for_register(dev_priv,
1024 reg, I965_PIPECONF_ACTIVE, 0,
1025 100))
1026 WARN(1, "pipe_off wait timed out\n");
1027 } else {
1028 /* Wait for the display line to settle */
1029 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 }
1032 }
1033
1034 /* Only for pre-ILK configs */
1035 void assert_pll(struct drm_i915_private *dev_priv,
1036 enum pipe pipe, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 val = I915_READ(DPLL(pipe));
1042 cur_state = !!(val & DPLL_VCO_ENABLE);
1043 I915_STATE_WARN(cur_state != state,
1044 "PLL state assertion failure (expected %s, current %s)\n",
1045 onoff(state), onoff(cur_state));
1046 }
1047
1048 /* XXX: the dsi pll is shared between MIPI DSI ports */
1049 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1050 {
1051 u32 val;
1052 bool cur_state;
1053
1054 mutex_lock(&dev_priv->sb_lock);
1055 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1056 mutex_unlock(&dev_priv->sb_lock);
1057
1058 cur_state = val & DSI_PLL_VCO_EN;
1059 I915_STATE_WARN(cur_state != state,
1060 "DSI PLL state assertion failure (expected %s, current %s)\n",
1061 onoff(state), onoff(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 bool cur_state;
1068 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1069 pipe);
1070
1071 if (HAS_DDI(dev_priv)) {
1072 /* DDI does not have a specific FDI_TX register */
1073 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1074 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075 } else {
1076 u32 val = I915_READ(FDI_TX_CTL(pipe));
1077 cur_state = !!(val & FDI_TX_ENABLE);
1078 }
1079 I915_STATE_WARN(cur_state != state,
1080 "FDI TX state assertion failure (expected %s, current %s)\n",
1081 onoff(state), onoff(cur_state));
1082 }
1083 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1084 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085
1086 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 u32 val;
1090 bool cur_state;
1091
1092 val = I915_READ(FDI_RX_CTL(pipe));
1093 cur_state = !!(val & FDI_RX_ENABLE);
1094 I915_STATE_WARN(cur_state != state,
1095 "FDI RX state assertion failure (expected %s, current %s)\n",
1096 onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1099 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100
1101 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1102 enum pipe pipe)
1103 {
1104 u32 val;
1105
1106 /* ILK FDI PLL is always enabled */
1107 if (IS_GEN5(dev_priv))
1108 return;
1109
1110 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1111 if (HAS_DDI(dev_priv))
1112 return;
1113
1114 val = I915_READ(FDI_TX_CTL(pipe));
1115 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1116 }
1117
1118 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1123
1124 val = I915_READ(FDI_RX_CTL(pipe));
1125 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1126 I915_STATE_WARN(cur_state != state,
1127 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1128 onoff(state), onoff(cur_state));
1129 }
1130
1131 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133 i915_reg_t pp_reg;
1134 u32 val;
1135 enum pipe panel_pipe = PIPE_A;
1136 bool locked = true;
1137
1138 if (WARN_ON(HAS_DDI(dev_priv)))
1139 return;
1140
1141 if (HAS_PCH_SPLIT(dev_priv)) {
1142 u32 port_sel;
1143
1144 pp_reg = PP_CONTROL(0);
1145 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146
1147 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1148 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1149 panel_pipe = PIPE_B;
1150 /* XXX: else fix for eDP */
1151 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152 /* presumably write lock depends on pipe, not port select */
1153 pp_reg = PP_CONTROL(pipe);
1154 panel_pipe = pipe;
1155 } else {
1156 pp_reg = PP_CONTROL(0);
1157 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1158 panel_pipe = PIPE_B;
1159 }
1160
1161 val = I915_READ(pp_reg);
1162 if (!(val & PANEL_POWER_ON) ||
1163 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1164 locked = false;
1165
1166 I915_STATE_WARN(panel_pipe == pipe && locked,
1167 "panel assertion failure, pipe %c regs locked\n",
1168 pipe_name(pipe));
1169 }
1170
1171 static void assert_cursor(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1173 {
1174 bool cur_state;
1175
1176 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1177 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178 else
1179 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180
1181 I915_STATE_WARN(cur_state != state,
1182 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1183 pipe_name(pipe), onoff(state), onoff(cur_state));
1184 }
1185 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1186 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187
1188 void assert_pipe(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 bool cur_state;
1192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 pipe);
1194 enum intel_display_power_domain power_domain;
1195
1196 /* we keep both pipes enabled on 830 */
1197 if (IS_I830(dev_priv))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552 int i;
1553
1554 assert_pipe_disabled(dev_priv, crtc->pipe);
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 /* Enable DVO 2x clock on both PLLs if necessary */
1561 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562 /*
1563 * It appears to be important that we don't enable this
1564 * for the current pipe before otherwise configuring the
1565 * PLL. No idea how this should be handled if multiple
1566 * DVO outputs are enabled simultaneosly.
1567 */
1568 dpll |= DPLL_DVO_2X_MODE;
1569 I915_WRITE(DPLL(!crtc->pipe),
1570 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1571 }
1572
1573 /*
1574 * Apparently we need to have VGA mode enabled prior to changing
1575 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1576 * dividers, even though the register value does change.
1577 */
1578 I915_WRITE(reg, 0);
1579
1580 I915_WRITE(reg, dpll);
1581
1582 /* Wait for the clocks to stabilize. */
1583 POSTING_READ(reg);
1584 udelay(150);
1585
1586 if (INTEL_GEN(dev_priv) >= 4) {
1587 I915_WRITE(DPLL_MD(crtc->pipe),
1588 crtc->config->dpll_hw_state.dpll_md);
1589 } else {
1590 /* The pixel multiplier can only be updated once the
1591 * DPLL is enabled and the clocks are stable.
1592 *
1593 * So write it again.
1594 */
1595 I915_WRITE(reg, dpll);
1596 }
1597
1598 /* We do this three times for luck */
1599 for (i = 0; i < 3; i++) {
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150); /* wait for warmup */
1603 }
1604 }
1605
1606 /**
1607 * i9xx_disable_pll - disable a PLL
1608 * @dev_priv: i915 private structure
1609 * @pipe: pipe PLL to disable
1610 *
1611 * Disable the PLL for @pipe, making sure the pipe is off first.
1612 *
1613 * Note! This is for pre-ILK only.
1614 */
1615 static void i9xx_disable_pll(struct intel_crtc *crtc)
1616 {
1617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618 enum pipe pipe = crtc->pipe;
1619
1620 /* Disable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev_priv) &&
1622 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1623 !intel_num_dvo_pipes(dev_priv)) {
1624 I915_WRITE(DPLL(PIPE_B),
1625 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1626 I915_WRITE(DPLL(PIPE_A),
1627 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1628 }
1629
1630 /* Don't disable pipe or pipe PLLs if needed */
1631 if (IS_I830(dev_priv))
1632 return;
1633
1634 /* Make sure the pipe isn't still relying on us */
1635 assert_pipe_disabled(dev_priv, pipe);
1636
1637 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1638 POSTING_READ(DPLL(pipe));
1639 }
1640
1641 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1642 {
1643 u32 val;
1644
1645 /* Make sure the pipe isn't still relying on us */
1646 assert_pipe_disabled(dev_priv, pipe);
1647
1648 val = DPLL_INTEGRATED_REF_CLK_VLV |
1649 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1650 if (pipe != PIPE_A)
1651 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1652
1653 I915_WRITE(DPLL(pipe), val);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660 u32 val;
1661
1662 /* Make sure the pipe isn't still relying on us */
1663 assert_pipe_disabled(dev_priv, pipe);
1664
1665 val = DPLL_SSC_REF_CLK_CHV |
1666 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1667 if (pipe != PIPE_A)
1668 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1669
1670 I915_WRITE(DPLL(pipe), val);
1671 POSTING_READ(DPLL(pipe));
1672
1673 mutex_lock(&dev_priv->sb_lock);
1674
1675 /* Disable 10bit clock to display controller */
1676 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1677 val &= ~DPIO_DCLKP_EN;
1678 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1679
1680 mutex_unlock(&dev_priv->sb_lock);
1681 }
1682
1683 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1684 struct intel_digital_port *dport,
1685 unsigned int expected_mask)
1686 {
1687 u32 port_mask;
1688 i915_reg_t dpll_reg;
1689
1690 switch (dport->port) {
1691 case PORT_B:
1692 port_mask = DPLL_PORTB_READY_MASK;
1693 dpll_reg = DPLL(0);
1694 break;
1695 case PORT_C:
1696 port_mask = DPLL_PORTC_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 expected_mask <<= 4;
1699 break;
1700 case PORT_D:
1701 port_mask = DPLL_PORTD_READY_MASK;
1702 dpll_reg = DPIO_PHY_STATUS;
1703 break;
1704 default:
1705 BUG();
1706 }
1707
1708 if (intel_wait_for_register(dev_priv,
1709 dpll_reg, port_mask, expected_mask,
1710 1000))
1711 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1712 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1713 }
1714
1715 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1716 enum pipe pipe)
1717 {
1718 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1719 pipe);
1720 i915_reg_t reg;
1721 uint32_t val, pipeconf_val;
1722
1723 /* Make sure PCH DPLL is enabled */
1724 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, pipe);
1728 assert_fdi_rx_enabled(dev_priv, pipe);
1729
1730 if (HAS_PCH_CPT(dev_priv)) {
1731 /* Workaround: Set the timing override bit before enabling the
1732 * pch transcoder. */
1733 reg = TRANS_CHICKEN2(pipe);
1734 val = I915_READ(reg);
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(reg, val);
1737 }
1738
1739 reg = PCH_TRANSCONF(pipe);
1740 val = I915_READ(reg);
1741 pipeconf_val = I915_READ(PIPECONF(pipe));
1742
1743 if (HAS_PCH_IBX(dev_priv)) {
1744 /*
1745 * Make the BPC in transcoder be consistent with
1746 * that in pipeconf reg. For HDMI we must use 8bpc
1747 * here for both 8bpc and 12bpc.
1748 */
1749 val &= ~PIPECONF_BPC_MASK;
1750 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1751 val |= PIPECONF_8BPC;
1752 else
1753 val |= pipeconf_val & PIPECONF_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv) &&
1759 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else
1764 val |= TRANS_PROGRESSIVE;
1765
1766 I915_WRITE(reg, val | TRANS_ENABLE);
1767 if (intel_wait_for_register(dev_priv,
1768 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1769 100))
1770 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1771 }
1772
1773 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 enum transcoder cpu_transcoder)
1775 {
1776 u32 val, pipeconf_val;
1777
1778 /* FDI must be feeding us bits for PCH ports */
1779 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1780 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1781
1782 /* Workaround: set timing override bit. */
1783 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1785 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786
1787 val = TRANS_ENABLE;
1788 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1789
1790 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1791 PIPECONF_INTERLACED_ILK)
1792 val |= TRANS_INTERLACED;
1793 else
1794 val |= TRANS_PROGRESSIVE;
1795
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 if (intel_wait_for_register(dev_priv,
1798 LPT_TRANSCONF,
1799 TRANS_STATE_ENABLE,
1800 TRANS_STATE_ENABLE,
1801 100))
1802 DRM_ERROR("Failed to enable PCH transcoder\n");
1803 }
1804
1805 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 i915_reg_t reg;
1809 uint32_t val;
1810
1811 /* FDI relies on the transcoder */
1812 assert_fdi_tx_disabled(dev_priv, pipe);
1813 assert_fdi_rx_disabled(dev_priv, pipe);
1814
1815 /* Ports must be off as well */
1816 assert_pch_ports_disabled(dev_priv, pipe);
1817
1818 reg = PCH_TRANSCONF(pipe);
1819 val = I915_READ(reg);
1820 val &= ~TRANS_ENABLE;
1821 I915_WRITE(reg, val);
1822 /* wait for PCH transcoder off, transcoder state */
1823 if (intel_wait_for_register(dev_priv,
1824 reg, TRANS_STATE_ENABLE, 0,
1825 50))
1826 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1827
1828 if (HAS_PCH_CPT(dev_priv)) {
1829 /* Workaround: Clear the timing override chicken bit again. */
1830 reg = TRANS_CHICKEN2(pipe);
1831 val = I915_READ(reg);
1832 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1833 I915_WRITE(reg, val);
1834 }
1835 }
1836
1837 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1838 {
1839 u32 val;
1840
1841 val = I915_READ(LPT_TRANSCONF);
1842 val &= ~TRANS_ENABLE;
1843 I915_WRITE(LPT_TRANSCONF, val);
1844 /* wait for PCH transcoder off, transcoder state */
1845 if (intel_wait_for_register(dev_priv,
1846 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1847 50))
1848 DRM_ERROR("Failed to disable PCH transcoder\n");
1849
1850 /* Workaround: clear timing override bit. */
1851 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1852 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1853 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1854 }
1855
1856 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1857 {
1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859
1860 WARN_ON(!crtc->config->has_pch_encoder);
1861
1862 if (HAS_PCH_LPT(dev_priv))
1863 return PIPE_A;
1864 else
1865 return crtc->pipe;
1866 }
1867
1868 /**
1869 * intel_enable_pipe - enable a pipe, asserting requirements
1870 * @crtc: crtc responsible for the pipe
1871 *
1872 * Enable @crtc's pipe, making sure that various hardware specific requirements
1873 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1874 */
1875 static void intel_enable_pipe(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = to_i915(dev);
1879 enum pipe pipe = crtc->pipe;
1880 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1881 i915_reg_t reg;
1882 u32 val;
1883
1884 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1885
1886 assert_planes_disabled(dev_priv, pipe);
1887 assert_cursor_disabled(dev_priv, pipe);
1888 assert_sprites_disabled(dev_priv, pipe);
1889
1890 /*
1891 * A pipe without a PLL won't actually be able to drive bits from
1892 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1893 * need the check.
1894 */
1895 if (HAS_GMCH_DISPLAY(dev_priv)) {
1896 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1897 assert_dsi_pll_enabled(dev_priv);
1898 else
1899 assert_pll_enabled(dev_priv, pipe);
1900 } else {
1901 if (crtc->config->has_pch_encoder) {
1902 /* if driving the PCH, we need FDI enabled */
1903 assert_fdi_rx_pll_enabled(dev_priv,
1904 intel_crtc_pch_transcoder(crtc));
1905 assert_fdi_tx_pll_enabled(dev_priv,
1906 (enum pipe) cpu_transcoder);
1907 }
1908 /* FIXME: assert CPU port conditions for SNB+ */
1909 }
1910
1911 reg = PIPECONF(cpu_transcoder);
1912 val = I915_READ(reg);
1913 if (val & PIPECONF_ENABLE) {
1914 /* we keep both pipes enabled on 830 */
1915 WARN_ON(!IS_I830(dev_priv));
1916 return;
1917 }
1918
1919 I915_WRITE(reg, val | PIPECONF_ENABLE);
1920 POSTING_READ(reg);
1921
1922 /*
1923 * Until the pipe starts DSL will read as 0, which would cause
1924 * an apparent vblank timestamp jump, which messes up also the
1925 * frame count when it's derived from the timestamps. So let's
1926 * wait for the pipe to start properly before we call
1927 * drm_crtc_vblank_on()
1928 */
1929 if (dev->max_vblank_count == 0 &&
1930 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1931 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1932 }
1933
1934 /**
1935 * intel_disable_pipe - disable a pipe, asserting requirements
1936 * @crtc: crtc whose pipes is to be disabled
1937 *
1938 * Disable the pipe of @crtc, making sure that various hardware
1939 * specific requirements are met, if applicable, e.g. plane
1940 * disabled, panel fitter off, etc.
1941 *
1942 * Will wait until the pipe has shut down before returning.
1943 */
1944 static void intel_disable_pipe(struct intel_crtc *crtc)
1945 {
1946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1948 enum pipe pipe = crtc->pipe;
1949 i915_reg_t reg;
1950 u32 val;
1951
1952 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1953
1954 /*
1955 * Make sure planes won't keep trying to pump pixels to us,
1956 * or we might hang the display.
1957 */
1958 assert_planes_disabled(dev_priv, pipe);
1959 assert_cursor_disabled(dev_priv, pipe);
1960 assert_sprites_disabled(dev_priv, pipe);
1961
1962 reg = PIPECONF(cpu_transcoder);
1963 val = I915_READ(reg);
1964 if ((val & PIPECONF_ENABLE) == 0)
1965 return;
1966
1967 /*
1968 * Double wide has implications for planes
1969 * so best keep it disabled when not needed.
1970 */
1971 if (crtc->config->double_wide)
1972 val &= ~PIPECONF_DOUBLE_WIDE;
1973
1974 /* Don't disable pipe or pipe PLLs if needed */
1975 if (!IS_I830(dev_priv))
1976 val &= ~PIPECONF_ENABLE;
1977
1978 I915_WRITE(reg, val);
1979 if ((val & PIPECONF_ENABLE) == 0)
1980 intel_wait_for_pipe_off(crtc);
1981 }
1982
1983 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1984 {
1985 return IS_GEN2(dev_priv) ? 2048 : 4096;
1986 }
1987
1988 static unsigned int
1989 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1990 {
1991 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1992 unsigned int cpp = fb->format->cpp[plane];
1993
1994 switch (fb->modifier) {
1995 case DRM_FORMAT_MOD_LINEAR:
1996 return cpp;
1997 case I915_FORMAT_MOD_X_TILED:
1998 if (IS_GEN2(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Y_TILED:
2003 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Yf_TILED:
2008 switch (cpp) {
2009 case 1:
2010 return 64;
2011 case 2:
2012 case 4:
2013 return 128;
2014 case 8:
2015 case 16:
2016 return 256;
2017 default:
2018 MISSING_CASE(cpp);
2019 return cpp;
2020 }
2021 break;
2022 default:
2023 MISSING_CASE(fb->modifier);
2024 return cpp;
2025 }
2026 }
2027
2028 static unsigned int
2029 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2030 {
2031 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2032 return 1;
2033 else
2034 return intel_tile_size(to_i915(fb->dev)) /
2035 intel_tile_width_bytes(fb, plane);
2036 }
2037
2038 /* Return the tile dimensions in pixel units */
2039 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2040 unsigned int *tile_width,
2041 unsigned int *tile_height)
2042 {
2043 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2044 unsigned int cpp = fb->format->cpp[plane];
2045
2046 *tile_width = tile_width_bytes / cpp;
2047 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2048 }
2049
2050 unsigned int
2051 intel_fb_align_height(const struct drm_framebuffer *fb,
2052 int plane, unsigned int height)
2053 {
2054 unsigned int tile_height = intel_tile_height(fb, plane);
2055
2056 return ALIGN(height, tile_height);
2057 }
2058
2059 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2060 {
2061 unsigned int size = 0;
2062 int i;
2063
2064 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2065 size += rot_info->plane[i].width * rot_info->plane[i].height;
2066
2067 return size;
2068 }
2069
2070 static void
2071 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2072 const struct drm_framebuffer *fb,
2073 unsigned int rotation)
2074 {
2075 view->type = I915_GGTT_VIEW_NORMAL;
2076 if (drm_rotation_90_or_270(rotation)) {
2077 view->type = I915_GGTT_VIEW_ROTATED;
2078 view->rotated = to_intel_framebuffer(fb)->rot_info;
2079 }
2080 }
2081
2082 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2083 {
2084 if (IS_I830(dev_priv))
2085 return 16 * 1024;
2086 else if (IS_I85X(dev_priv))
2087 return 256;
2088 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2089 return 32;
2090 else
2091 return 4 * 1024;
2092 }
2093
2094 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2095 {
2096 if (INTEL_INFO(dev_priv)->gen >= 9)
2097 return 256 * 1024;
2098 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2099 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2100 return 128 * 1024;
2101 else if (INTEL_INFO(dev_priv)->gen >= 4)
2102 return 4 * 1024;
2103 else
2104 return 0;
2105 }
2106
2107 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2108 int plane)
2109 {
2110 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2111
2112 /* AUX_DIST needs only 4K alignment */
2113 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2114 return 4096;
2115
2116 switch (fb->modifier) {
2117 case DRM_FORMAT_MOD_LINEAR:
2118 return intel_linear_alignment(dev_priv);
2119 case I915_FORMAT_MOD_X_TILED:
2120 if (INTEL_GEN(dev_priv) >= 9)
2121 return 256 * 1024;
2122 return 0;
2123 case I915_FORMAT_MOD_Y_TILED:
2124 case I915_FORMAT_MOD_Yf_TILED:
2125 return 1 * 1024 * 1024;
2126 default:
2127 MISSING_CASE(fb->modifier);
2128 return 0;
2129 }
2130 }
2131
2132 struct i915_vma *
2133 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2134 {
2135 struct drm_device *dev = fb->dev;
2136 struct drm_i915_private *dev_priv = to_i915(dev);
2137 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2138 struct i915_ggtt_view view;
2139 struct i915_vma *vma;
2140 u32 alignment;
2141
2142 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2143
2144 alignment = intel_surf_alignment(fb, 0);
2145
2146 intel_fill_fb_ggtt_view(&view, fb, rotation);
2147
2148 /* Note that the w/a also requires 64 PTE of padding following the
2149 * bo. We currently fill all unused PTE with the shadow page and so
2150 * we should always have valid PTE following the scanout preventing
2151 * the VT-d warning.
2152 */
2153 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2154 alignment = 256 * 1024;
2155
2156 /*
2157 * Global gtt pte registers are special registers which actually forward
2158 * writes to a chunk of system memory. Which means that there is no risk
2159 * that the register values disappear as soon as we call
2160 * intel_runtime_pm_put(), so it is correct to wrap only the
2161 * pin/unpin/fence and not more.
2162 */
2163 intel_runtime_pm_get(dev_priv);
2164
2165 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2166 if (IS_ERR(vma))
2167 goto err;
2168
2169 if (i915_vma_is_map_and_fenceable(vma)) {
2170 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2171 * fence, whereas 965+ only requires a fence if using
2172 * framebuffer compression. For simplicity, we always, when
2173 * possible, install a fence as the cost is not that onerous.
2174 *
2175 * If we fail to fence the tiled scanout, then either the
2176 * modeset will reject the change (which is highly unlikely as
2177 * the affected systems, all but one, do not have unmappable
2178 * space) or we will not be able to enable full powersaving
2179 * techniques (also likely not to apply due to various limits
2180 * FBC and the like impose on the size of the buffer, which
2181 * presumably we violated anyway with this unmappable buffer).
2182 * Anyway, it is presumably better to stumble onwards with
2183 * something and try to run the system in a "less than optimal"
2184 * mode that matches the user configuration.
2185 */
2186 if (i915_vma_get_fence(vma) == 0)
2187 i915_vma_pin_fence(vma);
2188 }
2189
2190 i915_vma_get(vma);
2191 err:
2192 intel_runtime_pm_put(dev_priv);
2193 return vma;
2194 }
2195
2196 void intel_unpin_fb_vma(struct i915_vma *vma)
2197 {
2198 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2199
2200 i915_vma_unpin_fence(vma);
2201 i915_gem_object_unpin_from_display_plane(vma);
2202 i915_vma_put(vma);
2203 }
2204
2205 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2206 unsigned int rotation)
2207 {
2208 if (drm_rotation_90_or_270(rotation))
2209 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2210 else
2211 return fb->pitches[plane];
2212 }
2213
2214 /*
2215 * Convert the x/y offsets into a linear offset.
2216 * Only valid with 0/180 degree rotation, which is fine since linear
2217 * offset is only used with linear buffers on pre-hsw and tiled buffers
2218 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2219 */
2220 u32 intel_fb_xy_to_linear(int x, int y,
2221 const struct intel_plane_state *state,
2222 int plane)
2223 {
2224 const struct drm_framebuffer *fb = state->base.fb;
2225 unsigned int cpp = fb->format->cpp[plane];
2226 unsigned int pitch = fb->pitches[plane];
2227
2228 return y * pitch + x * cpp;
2229 }
2230
2231 /*
2232 * Add the x/y offsets derived from fb->offsets[] to the user
2233 * specified plane src x/y offsets. The resulting x/y offsets
2234 * specify the start of scanout from the beginning of the gtt mapping.
2235 */
2236 void intel_add_fb_offsets(int *x, int *y,
2237 const struct intel_plane_state *state,
2238 int plane)
2239
2240 {
2241 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2242 unsigned int rotation = state->base.rotation;
2243
2244 if (drm_rotation_90_or_270(rotation)) {
2245 *x += intel_fb->rotated[plane].x;
2246 *y += intel_fb->rotated[plane].y;
2247 } else {
2248 *x += intel_fb->normal[plane].x;
2249 *y += intel_fb->normal[plane].y;
2250 }
2251 }
2252
2253 /*
2254 * Input tile dimensions and pitch must already be
2255 * rotated to match x and y, and in pixel units.
2256 */
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258 unsigned int tile_width,
2259 unsigned int tile_height,
2260 unsigned int tile_size,
2261 unsigned int pitch_tiles,
2262 u32 old_offset,
2263 u32 new_offset)
2264 {
2265 unsigned int pitch_pixels = pitch_tiles * tile_width;
2266 unsigned int tiles;
2267
2268 WARN_ON(old_offset & (tile_size - 1));
2269 WARN_ON(new_offset & (tile_size - 1));
2270 WARN_ON(new_offset > old_offset);
2271
2272 tiles = (old_offset - new_offset) / tile_size;
2273
2274 *y += tiles / pitch_tiles * tile_height;
2275 *x += tiles % pitch_tiles * tile_width;
2276
2277 /* minimize x in case it got needlessly big */
2278 *y += *x / pitch_pixels * tile_height;
2279 *x %= pitch_pixels;
2280
2281 return new_offset;
2282 }
2283
2284 /*
2285 * Adjust the tile offset by moving the difference into
2286 * the x/y offsets.
2287 */
2288 static u32 intel_adjust_tile_offset(int *x, int *y,
2289 const struct intel_plane_state *state, int plane,
2290 u32 old_offset, u32 new_offset)
2291 {
2292 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2293 const struct drm_framebuffer *fb = state->base.fb;
2294 unsigned int cpp = fb->format->cpp[plane];
2295 unsigned int rotation = state->base.rotation;
2296 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2297
2298 WARN_ON(new_offset > old_offset);
2299
2300 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2301 unsigned int tile_size, tile_width, tile_height;
2302 unsigned int pitch_tiles;
2303
2304 tile_size = intel_tile_size(dev_priv);
2305 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2306
2307 if (drm_rotation_90_or_270(rotation)) {
2308 pitch_tiles = pitch / tile_height;
2309 swap(tile_width, tile_height);
2310 } else {
2311 pitch_tiles = pitch / (tile_width * cpp);
2312 }
2313
2314 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2315 tile_size, pitch_tiles,
2316 old_offset, new_offset);
2317 } else {
2318 old_offset += *y * pitch + *x * cpp;
2319
2320 *y = (old_offset - new_offset) / pitch;
2321 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2322 }
2323
2324 return new_offset;
2325 }
2326
2327 /*
2328 * Computes the linear offset to the base tile and adjusts
2329 * x, y. bytes per pixel is assumed to be a power-of-two.
2330 *
2331 * In the 90/270 rotated case, x and y are assumed
2332 * to be already rotated to match the rotated GTT view, and
2333 * pitch is the tile_height aligned framebuffer height.
2334 *
2335 * This function is used when computing the derived information
2336 * under intel_framebuffer, so using any of that information
2337 * here is not allowed. Anything under drm_framebuffer can be
2338 * used. This is why the user has to pass in the pitch since it
2339 * is specified in the rotated orientation.
2340 */
2341 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2342 int *x, int *y,
2343 const struct drm_framebuffer *fb, int plane,
2344 unsigned int pitch,
2345 unsigned int rotation,
2346 u32 alignment)
2347 {
2348 uint64_t fb_modifier = fb->modifier;
2349 unsigned int cpp = fb->format->cpp[plane];
2350 u32 offset, offset_aligned;
2351
2352 if (alignment)
2353 alignment--;
2354
2355 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int tile_rows, tiles, pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2361
2362 if (drm_rotation_90_or_270(rotation)) {
2363 pitch_tiles = pitch / tile_height;
2364 swap(tile_width, tile_height);
2365 } else {
2366 pitch_tiles = pitch / (tile_width * cpp);
2367 }
2368
2369 tile_rows = *y / tile_height;
2370 *y %= tile_height;
2371
2372 tiles = *x / tile_width;
2373 *x %= tile_width;
2374
2375 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2376 offset_aligned = offset & ~alignment;
2377
2378 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2379 tile_size, pitch_tiles,
2380 offset, offset_aligned);
2381 } else {
2382 offset = *y * pitch + *x * cpp;
2383 offset_aligned = offset & ~alignment;
2384
2385 *y = (offset & alignment) / pitch;
2386 *x = ((offset & alignment) - *y * pitch) / cpp;
2387 }
2388
2389 return offset_aligned;
2390 }
2391
2392 u32 intel_compute_tile_offset(int *x, int *y,
2393 const struct intel_plane_state *state,
2394 int plane)
2395 {
2396 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2397 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2398 const struct drm_framebuffer *fb = state->base.fb;
2399 unsigned int rotation = state->base.rotation;
2400 int pitch = intel_fb_pitch(fb, plane, rotation);
2401 u32 alignment;
2402
2403 if (intel_plane->id == PLANE_CURSOR)
2404 alignment = intel_cursor_alignment(dev_priv);
2405 else
2406 alignment = intel_surf_alignment(fb, plane);
2407
2408 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2409 rotation, alignment);
2410 }
2411
2412 /* Convert the fb->offset[] linear offset into x/y offsets */
2413 static void intel_fb_offset_to_xy(int *x, int *y,
2414 const struct drm_framebuffer *fb, int plane)
2415 {
2416 unsigned int cpp = fb->format->cpp[plane];
2417 unsigned int pitch = fb->pitches[plane];
2418 u32 linear_offset = fb->offsets[plane];
2419
2420 *y = linear_offset / pitch;
2421 *x = linear_offset % pitch / cpp;
2422 }
2423
2424 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2425 {
2426 switch (fb_modifier) {
2427 case I915_FORMAT_MOD_X_TILED:
2428 return I915_TILING_X;
2429 case I915_FORMAT_MOD_Y_TILED:
2430 return I915_TILING_Y;
2431 default:
2432 return I915_TILING_NONE;
2433 }
2434 }
2435
2436 static int
2437 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2438 struct drm_framebuffer *fb)
2439 {
2440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2441 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2442 u32 gtt_offset_rotated = 0;
2443 unsigned int max_size = 0;
2444 int i, num_planes = fb->format->num_planes;
2445 unsigned int tile_size = intel_tile_size(dev_priv);
2446
2447 for (i = 0; i < num_planes; i++) {
2448 unsigned int width, height;
2449 unsigned int cpp, size;
2450 u32 offset;
2451 int x, y;
2452
2453 cpp = fb->format->cpp[i];
2454 width = drm_framebuffer_plane_width(fb->width, fb, i);
2455 height = drm_framebuffer_plane_height(fb->height, fb, i);
2456
2457 intel_fb_offset_to_xy(&x, &y, fb, i);
2458
2459 /*
2460 * The fence (if used) is aligned to the start of the object
2461 * so having the framebuffer wrap around across the edge of the
2462 * fenced region doesn't really work. We have no API to configure
2463 * the fence start offset within the object (nor could we probably
2464 * on gen2/3). So it's just easier if we just require that the
2465 * fb layout agrees with the fence layout. We already check that the
2466 * fb stride matches the fence stride elsewhere.
2467 */
2468 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2469 (x + width) * cpp > fb->pitches[i]) {
2470 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2471 i, fb->offsets[i]);
2472 return -EINVAL;
2473 }
2474
2475 /*
2476 * First pixel of the framebuffer from
2477 * the start of the normal gtt mapping.
2478 */
2479 intel_fb->normal[i].x = x;
2480 intel_fb->normal[i].y = y;
2481
2482 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2483 fb, i, fb->pitches[i],
2484 DRM_MODE_ROTATE_0, tile_size);
2485 offset /= tile_size;
2486
2487 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2488 unsigned int tile_width, tile_height;
2489 unsigned int pitch_tiles;
2490 struct drm_rect r;
2491
2492 intel_tile_dims(fb, i, &tile_width, &tile_height);
2493
2494 rot_info->plane[i].offset = offset;
2495 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2496 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2497 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2498
2499 intel_fb->rotated[i].pitch =
2500 rot_info->plane[i].height * tile_height;
2501
2502 /* how many tiles does this plane need */
2503 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2504 /*
2505 * If the plane isn't horizontally tile aligned,
2506 * we need one more tile.
2507 */
2508 if (x != 0)
2509 size++;
2510
2511 /* rotate the x/y offsets to match the GTT view */
2512 r.x1 = x;
2513 r.y1 = y;
2514 r.x2 = x + width;
2515 r.y2 = y + height;
2516 drm_rect_rotate(&r,
2517 rot_info->plane[i].width * tile_width,
2518 rot_info->plane[i].height * tile_height,
2519 DRM_MODE_ROTATE_270);
2520 x = r.x1;
2521 y = r.y1;
2522
2523 /* rotate the tile dimensions to match the GTT view */
2524 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2525 swap(tile_width, tile_height);
2526
2527 /*
2528 * We only keep the x/y offsets, so push all of the
2529 * gtt offset into the x/y offsets.
2530 */
2531 _intel_adjust_tile_offset(&x, &y,
2532 tile_width, tile_height,
2533 tile_size, pitch_tiles,
2534 gtt_offset_rotated * tile_size, 0);
2535
2536 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2537
2538 /*
2539 * First pixel of the framebuffer from
2540 * the start of the rotated gtt mapping.
2541 */
2542 intel_fb->rotated[i].x = x;
2543 intel_fb->rotated[i].y = y;
2544 } else {
2545 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2546 x * cpp, tile_size);
2547 }
2548
2549 /* how many tiles in total needed in the bo */
2550 max_size = max(max_size, offset + size);
2551 }
2552
2553 if (max_size * tile_size > intel_fb->obj->base.size) {
2554 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2555 max_size * tile_size, intel_fb->obj->base.size);
2556 return -EINVAL;
2557 }
2558
2559 return 0;
2560 }
2561
2562 static int i9xx_format_to_fourcc(int format)
2563 {
2564 switch (format) {
2565 case DISPPLANE_8BPP:
2566 return DRM_FORMAT_C8;
2567 case DISPPLANE_BGRX555:
2568 return DRM_FORMAT_XRGB1555;
2569 case DISPPLANE_BGRX565:
2570 return DRM_FORMAT_RGB565;
2571 default:
2572 case DISPPLANE_BGRX888:
2573 return DRM_FORMAT_XRGB8888;
2574 case DISPPLANE_RGBX888:
2575 return DRM_FORMAT_XBGR8888;
2576 case DISPPLANE_BGRX101010:
2577 return DRM_FORMAT_XRGB2101010;
2578 case DISPPLANE_RGBX101010:
2579 return DRM_FORMAT_XBGR2101010;
2580 }
2581 }
2582
2583 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2584 {
2585 switch (format) {
2586 case PLANE_CTL_FORMAT_RGB_565:
2587 return DRM_FORMAT_RGB565;
2588 default:
2589 case PLANE_CTL_FORMAT_XRGB_8888:
2590 if (rgb_order) {
2591 if (alpha)
2592 return DRM_FORMAT_ABGR8888;
2593 else
2594 return DRM_FORMAT_XBGR8888;
2595 } else {
2596 if (alpha)
2597 return DRM_FORMAT_ARGB8888;
2598 else
2599 return DRM_FORMAT_XRGB8888;
2600 }
2601 case PLANE_CTL_FORMAT_XRGB_2101010:
2602 if (rgb_order)
2603 return DRM_FORMAT_XBGR2101010;
2604 else
2605 return DRM_FORMAT_XRGB2101010;
2606 }
2607 }
2608
2609 static bool
2610 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2611 struct intel_initial_plane_config *plane_config)
2612 {
2613 struct drm_device *dev = crtc->base.dev;
2614 struct drm_i915_private *dev_priv = to_i915(dev);
2615 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2616 struct drm_i915_gem_object *obj = NULL;
2617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2618 struct drm_framebuffer *fb = &plane_config->fb->base;
2619 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2620 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2621 PAGE_SIZE);
2622
2623 size_aligned -= base_aligned;
2624
2625 if (plane_config->size == 0)
2626 return false;
2627
2628 /* If the FB is too big, just don't use it since fbdev is not very
2629 * important and we should probably use that space with FBC or other
2630 * features. */
2631 if (size_aligned * 2 > ggtt->stolen_usable_size)
2632 return false;
2633
2634 mutex_lock(&dev->struct_mutex);
2635 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2636 base_aligned,
2637 base_aligned,
2638 size_aligned);
2639 mutex_unlock(&dev->struct_mutex);
2640 if (!obj)
2641 return false;
2642
2643 if (plane_config->tiling == I915_TILING_X)
2644 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2645
2646 mode_cmd.pixel_format = fb->format->format;
2647 mode_cmd.width = fb->width;
2648 mode_cmd.height = fb->height;
2649 mode_cmd.pitches[0] = fb->pitches[0];
2650 mode_cmd.modifier[0] = fb->modifier;
2651 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2652
2653 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2654 DRM_DEBUG_KMS("intel fb init failed\n");
2655 goto out_unref_obj;
2656 }
2657
2658
2659 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2660 return true;
2661
2662 out_unref_obj:
2663 i915_gem_object_put(obj);
2664 return false;
2665 }
2666
2667 static void
2668 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2669 struct intel_plane_state *plane_state,
2670 bool visible)
2671 {
2672 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2673
2674 plane_state->base.visible = visible;
2675
2676 /* FIXME pre-g4x don't work like this */
2677 if (visible) {
2678 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2679 crtc_state->active_planes |= BIT(plane->id);
2680 } else {
2681 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2682 crtc_state->active_planes &= ~BIT(plane->id);
2683 }
2684
2685 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2686 crtc_state->base.crtc->name,
2687 crtc_state->active_planes);
2688 }
2689
2690 static void
2691 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2692 struct intel_initial_plane_config *plane_config)
2693 {
2694 struct drm_device *dev = intel_crtc->base.dev;
2695 struct drm_i915_private *dev_priv = to_i915(dev);
2696 struct drm_crtc *c;
2697 struct drm_i915_gem_object *obj;
2698 struct drm_plane *primary = intel_crtc->base.primary;
2699 struct drm_plane_state *plane_state = primary->state;
2700 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2701 struct intel_plane *intel_plane = to_intel_plane(primary);
2702 struct intel_plane_state *intel_state =
2703 to_intel_plane_state(plane_state);
2704 struct drm_framebuffer *fb;
2705
2706 if (!plane_config->fb)
2707 return;
2708
2709 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2710 fb = &plane_config->fb->base;
2711 goto valid_fb;
2712 }
2713
2714 kfree(plane_config->fb);
2715
2716 /*
2717 * Failed to alloc the obj, check to see if we should share
2718 * an fb with another CRTC instead
2719 */
2720 for_each_crtc(dev, c) {
2721 struct intel_plane_state *state;
2722
2723 if (c == &intel_crtc->base)
2724 continue;
2725
2726 if (!to_intel_crtc(c)->active)
2727 continue;
2728
2729 state = to_intel_plane_state(c->primary->state);
2730 if (!state->vma)
2731 continue;
2732
2733 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2734 fb = c->primary->fb;
2735 drm_framebuffer_reference(fb);
2736 goto valid_fb;
2737 }
2738 }
2739
2740 /*
2741 * We've failed to reconstruct the BIOS FB. Current display state
2742 * indicates that the primary plane is visible, but has a NULL FB,
2743 * which will lead to problems later if we don't fix it up. The
2744 * simplest solution is to just disable the primary plane now and
2745 * pretend the BIOS never had it enabled.
2746 */
2747 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2748 to_intel_plane_state(plane_state),
2749 false);
2750 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2751 trace_intel_disable_plane(primary, intel_crtc);
2752 intel_plane->disable_plane(intel_plane, intel_crtc);
2753
2754 return;
2755
2756 valid_fb:
2757 mutex_lock(&dev->struct_mutex);
2758 intel_state->vma =
2759 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2760 mutex_unlock(&dev->struct_mutex);
2761 if (IS_ERR(intel_state->vma)) {
2762 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2763 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2764
2765 intel_state->vma = NULL;
2766 drm_framebuffer_unreference(fb);
2767 return;
2768 }
2769
2770 plane_state->src_x = 0;
2771 plane_state->src_y = 0;
2772 plane_state->src_w = fb->width << 16;
2773 plane_state->src_h = fb->height << 16;
2774
2775 plane_state->crtc_x = 0;
2776 plane_state->crtc_y = 0;
2777 plane_state->crtc_w = fb->width;
2778 plane_state->crtc_h = fb->height;
2779
2780 intel_state->base.src = drm_plane_state_src(plane_state);
2781 intel_state->base.dst = drm_plane_state_dest(plane_state);
2782
2783 obj = intel_fb_obj(fb);
2784 if (i915_gem_object_is_tiled(obj))
2785 dev_priv->preserve_bios_swizzle = true;
2786
2787 drm_framebuffer_reference(fb);
2788 primary->fb = primary->state->fb = fb;
2789 primary->crtc = primary->state->crtc = &intel_crtc->base;
2790
2791 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2792 to_intel_plane_state(plane_state),
2793 true);
2794
2795 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2796 &obj->frontbuffer_bits);
2797 }
2798
2799 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2800 unsigned int rotation)
2801 {
2802 int cpp = fb->format->cpp[plane];
2803
2804 switch (fb->modifier) {
2805 case DRM_FORMAT_MOD_LINEAR:
2806 case I915_FORMAT_MOD_X_TILED:
2807 switch (cpp) {
2808 case 8:
2809 return 4096;
2810 case 4:
2811 case 2:
2812 case 1:
2813 return 8192;
2814 default:
2815 MISSING_CASE(cpp);
2816 break;
2817 }
2818 break;
2819 case I915_FORMAT_MOD_Y_TILED:
2820 case I915_FORMAT_MOD_Yf_TILED:
2821 switch (cpp) {
2822 case 8:
2823 return 2048;
2824 case 4:
2825 return 4096;
2826 case 2:
2827 case 1:
2828 return 8192;
2829 default:
2830 MISSING_CASE(cpp);
2831 break;
2832 }
2833 break;
2834 default:
2835 MISSING_CASE(fb->modifier);
2836 }
2837
2838 return 2048;
2839 }
2840
2841 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2842 {
2843 const struct drm_framebuffer *fb = plane_state->base.fb;
2844 unsigned int rotation = plane_state->base.rotation;
2845 int x = plane_state->base.src.x1 >> 16;
2846 int y = plane_state->base.src.y1 >> 16;
2847 int w = drm_rect_width(&plane_state->base.src) >> 16;
2848 int h = drm_rect_height(&plane_state->base.src) >> 16;
2849 int max_width = skl_max_plane_width(fb, 0, rotation);
2850 int max_height = 4096;
2851 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2852
2853 if (w > max_width || h > max_height) {
2854 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2855 w, h, max_width, max_height);
2856 return -EINVAL;
2857 }
2858
2859 intel_add_fb_offsets(&x, &y, plane_state, 0);
2860 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2861 alignment = intel_surf_alignment(fb, 0);
2862
2863 /*
2864 * AUX surface offset is specified as the distance from the
2865 * main surface offset, and it must be non-negative. Make
2866 * sure that is what we will get.
2867 */
2868 if (offset > aux_offset)
2869 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2870 offset, aux_offset & ~(alignment - 1));
2871
2872 /*
2873 * When using an X-tiled surface, the plane blows up
2874 * if the x offset + width exceed the stride.
2875 *
2876 * TODO: linear and Y-tiled seem fine, Yf untested,
2877 */
2878 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2879 int cpp = fb->format->cpp[0];
2880
2881 while ((x + w) * cpp > fb->pitches[0]) {
2882 if (offset == 0) {
2883 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2884 return -EINVAL;
2885 }
2886
2887 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2888 offset, offset - alignment);
2889 }
2890 }
2891
2892 plane_state->main.offset = offset;
2893 plane_state->main.x = x;
2894 plane_state->main.y = y;
2895
2896 return 0;
2897 }
2898
2899 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2900 {
2901 const struct drm_framebuffer *fb = plane_state->base.fb;
2902 unsigned int rotation = plane_state->base.rotation;
2903 int max_width = skl_max_plane_width(fb, 1, rotation);
2904 int max_height = 4096;
2905 int x = plane_state->base.src.x1 >> 17;
2906 int y = plane_state->base.src.y1 >> 17;
2907 int w = drm_rect_width(&plane_state->base.src) >> 17;
2908 int h = drm_rect_height(&plane_state->base.src) >> 17;
2909 u32 offset;
2910
2911 intel_add_fb_offsets(&x, &y, plane_state, 1);
2912 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2913
2914 /* FIXME not quite sure how/if these apply to the chroma plane */
2915 if (w > max_width || h > max_height) {
2916 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2917 w, h, max_width, max_height);
2918 return -EINVAL;
2919 }
2920
2921 plane_state->aux.offset = offset;
2922 plane_state->aux.x = x;
2923 plane_state->aux.y = y;
2924
2925 return 0;
2926 }
2927
2928 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2929 {
2930 const struct drm_framebuffer *fb = plane_state->base.fb;
2931 unsigned int rotation = plane_state->base.rotation;
2932 int ret;
2933
2934 if (!plane_state->base.visible)
2935 return 0;
2936
2937 /* Rotate src coordinates to match rotated GTT view */
2938 if (drm_rotation_90_or_270(rotation))
2939 drm_rect_rotate(&plane_state->base.src,
2940 fb->width << 16, fb->height << 16,
2941 DRM_MODE_ROTATE_270);
2942
2943 /*
2944 * Handle the AUX surface first since
2945 * the main surface setup depends on it.
2946 */
2947 if (fb->format->format == DRM_FORMAT_NV12) {
2948 ret = skl_check_nv12_aux_surface(plane_state);
2949 if (ret)
2950 return ret;
2951 } else {
2952 plane_state->aux.offset = ~0xfff;
2953 plane_state->aux.x = 0;
2954 plane_state->aux.y = 0;
2955 }
2956
2957 ret = skl_check_main_surface(plane_state);
2958 if (ret)
2959 return ret;
2960
2961 return 0;
2962 }
2963
2964 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2965 const struct intel_plane_state *plane_state)
2966 {
2967 struct drm_i915_private *dev_priv =
2968 to_i915(plane_state->base.plane->dev);
2969 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2970 const struct drm_framebuffer *fb = plane_state->base.fb;
2971 unsigned int rotation = plane_state->base.rotation;
2972 u32 dspcntr;
2973
2974 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2975
2976 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2977 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2978 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2979
2980 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2981 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2982
2983 if (INTEL_GEN(dev_priv) < 4)
2984 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2985
2986 switch (fb->format->format) {
2987 case DRM_FORMAT_C8:
2988 dspcntr |= DISPPLANE_8BPP;
2989 break;
2990 case DRM_FORMAT_XRGB1555:
2991 dspcntr |= DISPPLANE_BGRX555;
2992 break;
2993 case DRM_FORMAT_RGB565:
2994 dspcntr |= DISPPLANE_BGRX565;
2995 break;
2996 case DRM_FORMAT_XRGB8888:
2997 dspcntr |= DISPPLANE_BGRX888;
2998 break;
2999 case DRM_FORMAT_XBGR8888:
3000 dspcntr |= DISPPLANE_RGBX888;
3001 break;
3002 case DRM_FORMAT_XRGB2101010:
3003 dspcntr |= DISPPLANE_BGRX101010;
3004 break;
3005 case DRM_FORMAT_XBGR2101010:
3006 dspcntr |= DISPPLANE_RGBX101010;
3007 break;
3008 default:
3009 MISSING_CASE(fb->format->format);
3010 return 0;
3011 }
3012
3013 if (INTEL_GEN(dev_priv) >= 4 &&
3014 fb->modifier == I915_FORMAT_MOD_X_TILED)
3015 dspcntr |= DISPPLANE_TILED;
3016
3017 if (rotation & DRM_MODE_ROTATE_180)
3018 dspcntr |= DISPPLANE_ROTATE_180;
3019
3020 if (rotation & DRM_MODE_REFLECT_X)
3021 dspcntr |= DISPPLANE_MIRROR;
3022
3023 return dspcntr;
3024 }
3025
3026 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3027 {
3028 struct drm_i915_private *dev_priv =
3029 to_i915(plane_state->base.plane->dev);
3030 int src_x = plane_state->base.src.x1 >> 16;
3031 int src_y = plane_state->base.src.y1 >> 16;
3032 u32 offset;
3033
3034 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3035
3036 if (INTEL_GEN(dev_priv) >= 4)
3037 offset = intel_compute_tile_offset(&src_x, &src_y,
3038 plane_state, 0);
3039 else
3040 offset = 0;
3041
3042 /* HSW/BDW do this automagically in hardware */
3043 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3044 unsigned int rotation = plane_state->base.rotation;
3045 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3046 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3047
3048 if (rotation & DRM_MODE_ROTATE_180) {
3049 src_x += src_w - 1;
3050 src_y += src_h - 1;
3051 } else if (rotation & DRM_MODE_REFLECT_X) {
3052 src_x += src_w - 1;
3053 }
3054 }
3055
3056 plane_state->main.offset = offset;
3057 plane_state->main.x = src_x;
3058 plane_state->main.y = src_y;
3059
3060 return 0;
3061 }
3062
3063 static void i9xx_update_primary_plane(struct intel_plane *primary,
3064 const struct intel_crtc_state *crtc_state,
3065 const struct intel_plane_state *plane_state)
3066 {
3067 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3069 const struct drm_framebuffer *fb = plane_state->base.fb;
3070 enum plane plane = primary->plane;
3071 u32 linear_offset;
3072 u32 dspcntr = plane_state->ctl;
3073 i915_reg_t reg = DSPCNTR(plane);
3074 int x = plane_state->main.x;
3075 int y = plane_state->main.y;
3076 unsigned long irqflags;
3077
3078 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3079
3080 if (INTEL_GEN(dev_priv) >= 4)
3081 crtc->dspaddr_offset = plane_state->main.offset;
3082 else
3083 crtc->dspaddr_offset = linear_offset;
3084
3085 crtc->adjusted_x = x;
3086 crtc->adjusted_y = y;
3087
3088 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3089
3090 if (INTEL_GEN(dev_priv) < 4) {
3091 /* pipesrc and dspsize control the size that is scaled from,
3092 * which should always be the user's requested size.
3093 */
3094 I915_WRITE_FW(DSPSIZE(plane),
3095 ((crtc_state->pipe_src_h - 1) << 16) |
3096 (crtc_state->pipe_src_w - 1));
3097 I915_WRITE_FW(DSPPOS(plane), 0);
3098 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3099 I915_WRITE_FW(PRIMSIZE(plane),
3100 ((crtc_state->pipe_src_h - 1) << 16) |
3101 (crtc_state->pipe_src_w - 1));
3102 I915_WRITE_FW(PRIMPOS(plane), 0);
3103 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3104 }
3105
3106 I915_WRITE_FW(reg, dspcntr);
3107
3108 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3109 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3110 I915_WRITE_FW(DSPSURF(plane),
3111 intel_plane_ggtt_offset(plane_state) +
3112 crtc->dspaddr_offset);
3113 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3114 } else if (INTEL_GEN(dev_priv) >= 4) {
3115 I915_WRITE_FW(DSPSURF(plane),
3116 intel_plane_ggtt_offset(plane_state) +
3117 crtc->dspaddr_offset);
3118 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3119 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3120 } else {
3121 I915_WRITE_FW(DSPADDR(plane),
3122 intel_plane_ggtt_offset(plane_state) +
3123 crtc->dspaddr_offset);
3124 }
3125 POSTING_READ_FW(reg);
3126
3127 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3128 }
3129
3130 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3131 struct intel_crtc *crtc)
3132 {
3133 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3134 enum plane plane = primary->plane;
3135 unsigned long irqflags;
3136
3137 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3138
3139 I915_WRITE_FW(DSPCNTR(plane), 0);
3140 if (INTEL_INFO(dev_priv)->gen >= 4)
3141 I915_WRITE_FW(DSPSURF(plane), 0);
3142 else
3143 I915_WRITE_FW(DSPADDR(plane), 0);
3144 POSTING_READ_FW(DSPCNTR(plane));
3145
3146 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3147 }
3148
3149 static u32
3150 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3151 {
3152 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3153 return 64;
3154 else
3155 return intel_tile_width_bytes(fb, plane);
3156 }
3157
3158 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3159 {
3160 struct drm_device *dev = intel_crtc->base.dev;
3161 struct drm_i915_private *dev_priv = to_i915(dev);
3162
3163 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3164 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3165 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3166 }
3167
3168 /*
3169 * This function detaches (aka. unbinds) unused scalers in hardware
3170 */
3171 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3172 {
3173 struct intel_crtc_scaler_state *scaler_state;
3174 int i;
3175
3176 scaler_state = &intel_crtc->config->scaler_state;
3177
3178 /* loop through and disable scalers that aren't in use */
3179 for (i = 0; i < intel_crtc->num_scalers; i++) {
3180 if (!scaler_state->scalers[i].in_use)
3181 skl_detach_scaler(intel_crtc, i);
3182 }
3183 }
3184
3185 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3186 unsigned int rotation)
3187 {
3188 u32 stride;
3189
3190 if (plane >= fb->format->num_planes)
3191 return 0;
3192
3193 stride = intel_fb_pitch(fb, plane, rotation);
3194
3195 /*
3196 * The stride is either expressed as a multiple of 64 bytes chunks for
3197 * linear buffers or in number of tiles for tiled buffers.
3198 */
3199 if (drm_rotation_90_or_270(rotation))
3200 stride /= intel_tile_height(fb, plane);
3201 else
3202 stride /= intel_fb_stride_alignment(fb, plane);
3203
3204 return stride;
3205 }
3206
3207 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3208 {
3209 switch (pixel_format) {
3210 case DRM_FORMAT_C8:
3211 return PLANE_CTL_FORMAT_INDEXED;
3212 case DRM_FORMAT_RGB565:
3213 return PLANE_CTL_FORMAT_RGB_565;
3214 case DRM_FORMAT_XBGR8888:
3215 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3216 case DRM_FORMAT_XRGB8888:
3217 return PLANE_CTL_FORMAT_XRGB_8888;
3218 /*
3219 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3220 * to be already pre-multiplied. We need to add a knob (or a different
3221 * DRM_FORMAT) for user-space to configure that.
3222 */
3223 case DRM_FORMAT_ABGR8888:
3224 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3225 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3226 case DRM_FORMAT_ARGB8888:
3227 return PLANE_CTL_FORMAT_XRGB_8888 |
3228 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3229 case DRM_FORMAT_XRGB2101010:
3230 return PLANE_CTL_FORMAT_XRGB_2101010;
3231 case DRM_FORMAT_XBGR2101010:
3232 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3233 case DRM_FORMAT_YUYV:
3234 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3235 case DRM_FORMAT_YVYU:
3236 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3237 case DRM_FORMAT_UYVY:
3238 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3239 case DRM_FORMAT_VYUY:
3240 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3241 default:
3242 MISSING_CASE(pixel_format);
3243 }
3244
3245 return 0;
3246 }
3247
3248 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3249 {
3250 switch (fb_modifier) {
3251 case DRM_FORMAT_MOD_LINEAR:
3252 break;
3253 case I915_FORMAT_MOD_X_TILED:
3254 return PLANE_CTL_TILED_X;
3255 case I915_FORMAT_MOD_Y_TILED:
3256 return PLANE_CTL_TILED_Y;
3257 case I915_FORMAT_MOD_Yf_TILED:
3258 return PLANE_CTL_TILED_YF;
3259 default:
3260 MISSING_CASE(fb_modifier);
3261 }
3262
3263 return 0;
3264 }
3265
3266 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3267 {
3268 switch (rotation) {
3269 case DRM_MODE_ROTATE_0:
3270 break;
3271 /*
3272 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3273 * while i915 HW rotation is clockwise, thats why this swapping.
3274 */
3275 case DRM_MODE_ROTATE_90:
3276 return PLANE_CTL_ROTATE_270;
3277 case DRM_MODE_ROTATE_180:
3278 return PLANE_CTL_ROTATE_180;
3279 case DRM_MODE_ROTATE_270:
3280 return PLANE_CTL_ROTATE_90;
3281 default:
3282 MISSING_CASE(rotation);
3283 }
3284
3285 return 0;
3286 }
3287
3288 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3289 const struct intel_plane_state *plane_state)
3290 {
3291 struct drm_i915_private *dev_priv =
3292 to_i915(plane_state->base.plane->dev);
3293 const struct drm_framebuffer *fb = plane_state->base.fb;
3294 unsigned int rotation = plane_state->base.rotation;
3295 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3296 u32 plane_ctl;
3297
3298 plane_ctl = PLANE_CTL_ENABLE;
3299
3300 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3301 plane_ctl |=
3302 PLANE_CTL_PIPE_GAMMA_ENABLE |
3303 PLANE_CTL_PIPE_CSC_ENABLE |
3304 PLANE_CTL_PLANE_GAMMA_DISABLE;
3305 }
3306
3307 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3308 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3309 plane_ctl |= skl_plane_ctl_rotation(rotation);
3310
3311 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3312 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3313 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3314 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3315
3316 return plane_ctl;
3317 }
3318
3319 static void skylake_update_primary_plane(struct intel_plane *plane,
3320 const struct intel_crtc_state *crtc_state,
3321 const struct intel_plane_state *plane_state)
3322 {
3323 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3325 const struct drm_framebuffer *fb = plane_state->base.fb;
3326 enum plane_id plane_id = plane->id;
3327 enum pipe pipe = plane->pipe;
3328 u32 plane_ctl = plane_state->ctl;
3329 unsigned int rotation = plane_state->base.rotation;
3330 u32 stride = skl_plane_stride(fb, 0, rotation);
3331 u32 surf_addr = plane_state->main.offset;
3332 int scaler_id = plane_state->scaler_id;
3333 int src_x = plane_state->main.x;
3334 int src_y = plane_state->main.y;
3335 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3336 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3337 int dst_x = plane_state->base.dst.x1;
3338 int dst_y = plane_state->base.dst.y1;
3339 int dst_w = drm_rect_width(&plane_state->base.dst);
3340 int dst_h = drm_rect_height(&plane_state->base.dst);
3341 unsigned long irqflags;
3342
3343 /* Sizes are 0 based */
3344 src_w--;
3345 src_h--;
3346 dst_w--;
3347 dst_h--;
3348
3349 crtc->dspaddr_offset = surf_addr;
3350
3351 crtc->adjusted_x = src_x;
3352 crtc->adjusted_y = src_y;
3353
3354 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3355
3356 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3357 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3358 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3359 PLANE_COLOR_PIPE_CSC_ENABLE |
3360 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3361 }
3362
3363 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3364 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3365 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3366 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3367
3368 if (scaler_id >= 0) {
3369 uint32_t ps_ctrl = 0;
3370
3371 WARN_ON(!dst_w || !dst_h);
3372 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3373 crtc_state->scaler_state.scalers[scaler_id].mode;
3374 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3375 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3376 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3377 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3378 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3379 } else {
3380 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3381 }
3382
3383 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3384 intel_plane_ggtt_offset(plane_state) + surf_addr);
3385
3386 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3387
3388 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3389 }
3390
3391 static void skylake_disable_primary_plane(struct intel_plane *primary,
3392 struct intel_crtc *crtc)
3393 {
3394 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3395 enum plane_id plane_id = primary->id;
3396 enum pipe pipe = primary->pipe;
3397 unsigned long irqflags;
3398
3399 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3400
3401 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3402 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3403 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3404
3405 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3406 }
3407
3408 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3409 {
3410 struct intel_crtc *crtc;
3411
3412 for_each_intel_crtc(&dev_priv->drm, crtc)
3413 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3414 }
3415
3416 static int
3417 __intel_display_resume(struct drm_device *dev,
3418 struct drm_atomic_state *state,
3419 struct drm_modeset_acquire_ctx *ctx)
3420 {
3421 struct drm_crtc_state *crtc_state;
3422 struct drm_crtc *crtc;
3423 int i, ret;
3424
3425 intel_modeset_setup_hw_state(dev, ctx);
3426 i915_redisable_vga(to_i915(dev));
3427
3428 if (!state)
3429 return 0;
3430
3431 /*
3432 * We've duplicated the state, pointers to the old state are invalid.
3433 *
3434 * Don't attempt to use the old state until we commit the duplicated state.
3435 */
3436 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3437 /*
3438 * Force recalculation even if we restore
3439 * current state. With fast modeset this may not result
3440 * in a modeset when the state is compatible.
3441 */
3442 crtc_state->mode_changed = true;
3443 }
3444
3445 /* ignore any reset values/BIOS leftovers in the WM registers */
3446 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3447 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3448
3449 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3450
3451 WARN_ON(ret == -EDEADLK);
3452 return ret;
3453 }
3454
3455 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3456 {
3457 return intel_has_gpu_reset(dev_priv) &&
3458 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3459 }
3460
3461 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3462 {
3463 struct drm_device *dev = &dev_priv->drm;
3464 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3465 struct drm_atomic_state *state;
3466 int ret;
3467
3468
3469 /* reset doesn't touch the display */
3470 if (!i915.force_reset_modeset_test &&
3471 !gpu_reset_clobbers_display(dev_priv))
3472 return;
3473
3474 /*
3475 * Need mode_config.mutex so that we don't
3476 * trample ongoing ->detect() and whatnot.
3477 */
3478 mutex_lock(&dev->mode_config.mutex);
3479 drm_modeset_acquire_init(ctx, 0);
3480 while (1) {
3481 ret = drm_modeset_lock_all_ctx(dev, ctx);
3482 if (ret != -EDEADLK)
3483 break;
3484
3485 drm_modeset_backoff(ctx);
3486 }
3487 /*
3488 * Disabling the crtcs gracefully seems nicer. Also the
3489 * g33 docs say we should at least disable all the planes.
3490 */
3491 state = drm_atomic_helper_duplicate_state(dev, ctx);
3492 if (IS_ERR(state)) {
3493 ret = PTR_ERR(state);
3494 DRM_ERROR("Duplicating state failed with %i\n", ret);
3495 return;
3496 }
3497
3498 ret = drm_atomic_helper_disable_all(dev, ctx);
3499 if (ret) {
3500 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3501 drm_atomic_state_put(state);
3502 return;
3503 }
3504
3505 dev_priv->modeset_restore_state = state;
3506 state->acquire_ctx = ctx;
3507 }
3508
3509 void intel_finish_reset(struct drm_i915_private *dev_priv)
3510 {
3511 struct drm_device *dev = &dev_priv->drm;
3512 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3513 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3514 int ret;
3515
3516 /* reset doesn't touch the display */
3517 if (!i915.force_reset_modeset_test &&
3518 !gpu_reset_clobbers_display(dev_priv))
3519 return;
3520
3521 if (!state)
3522 goto unlock;
3523
3524 /*
3525 * Flips in the rings will be nuked by the reset,
3526 * so complete all pending flips so that user space
3527 * will get its events and not get stuck.
3528 */
3529 intel_complete_page_flips(dev_priv);
3530
3531 dev_priv->modeset_restore_state = NULL;
3532
3533 /* reset doesn't touch the display */
3534 if (!gpu_reset_clobbers_display(dev_priv)) {
3535 /* for testing only restore the display */
3536 ret = __intel_display_resume(dev, state, ctx);
3537 if (ret)
3538 DRM_ERROR("Restoring old state failed with %i\n", ret);
3539 } else {
3540 /*
3541 * The display has been reset as well,
3542 * so need a full re-initialization.
3543 */
3544 intel_runtime_pm_disable_interrupts(dev_priv);
3545 intel_runtime_pm_enable_interrupts(dev_priv);
3546
3547 intel_pps_unlock_regs_wa(dev_priv);
3548 intel_modeset_init_hw(dev);
3549
3550 spin_lock_irq(&dev_priv->irq_lock);
3551 if (dev_priv->display.hpd_irq_setup)
3552 dev_priv->display.hpd_irq_setup(dev_priv);
3553 spin_unlock_irq(&dev_priv->irq_lock);
3554
3555 ret = __intel_display_resume(dev, state, ctx);
3556 if (ret)
3557 DRM_ERROR("Restoring old state failed with %i\n", ret);
3558
3559 intel_hpd_init(dev_priv);
3560 }
3561
3562 drm_atomic_state_put(state);
3563 unlock:
3564 drm_modeset_drop_locks(ctx);
3565 drm_modeset_acquire_fini(ctx);
3566 mutex_unlock(&dev->mode_config.mutex);
3567 }
3568
3569 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3570 {
3571 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3572
3573 if (i915_reset_backoff(error))
3574 return true;
3575
3576 if (crtc->reset_count != i915_reset_count(error))
3577 return true;
3578
3579 return false;
3580 }
3581
3582 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3583 {
3584 struct drm_device *dev = crtc->dev;
3585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586 bool pending;
3587
3588 if (abort_flip_on_reset(intel_crtc))
3589 return false;
3590
3591 spin_lock_irq(&dev->event_lock);
3592 pending = to_intel_crtc(crtc)->flip_work != NULL;
3593 spin_unlock_irq(&dev->event_lock);
3594
3595 return pending;
3596 }
3597
3598 static void intel_update_pipe_config(struct intel_crtc *crtc,
3599 struct intel_crtc_state *old_crtc_state)
3600 {
3601 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3602 struct intel_crtc_state *pipe_config =
3603 to_intel_crtc_state(crtc->base.state);
3604
3605 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3606 crtc->base.mode = crtc->base.state->mode;
3607
3608 /*
3609 * Update pipe size and adjust fitter if needed: the reason for this is
3610 * that in compute_mode_changes we check the native mode (not the pfit
3611 * mode) to see if we can flip rather than do a full mode set. In the
3612 * fastboot case, we'll flip, but if we don't update the pipesrc and
3613 * pfit state, we'll end up with a big fb scanned out into the wrong
3614 * sized surface.
3615 */
3616
3617 I915_WRITE(PIPESRC(crtc->pipe),
3618 ((pipe_config->pipe_src_w - 1) << 16) |
3619 (pipe_config->pipe_src_h - 1));
3620
3621 /* on skylake this is done by detaching scalers */
3622 if (INTEL_GEN(dev_priv) >= 9) {
3623 skl_detach_scalers(crtc);
3624
3625 if (pipe_config->pch_pfit.enabled)
3626 skylake_pfit_enable(crtc);
3627 } else if (HAS_PCH_SPLIT(dev_priv)) {
3628 if (pipe_config->pch_pfit.enabled)
3629 ironlake_pfit_enable(crtc);
3630 else if (old_crtc_state->pch_pfit.enabled)
3631 ironlake_pfit_disable(crtc, true);
3632 }
3633 }
3634
3635 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3636 {
3637 struct drm_device *dev = crtc->base.dev;
3638 struct drm_i915_private *dev_priv = to_i915(dev);
3639 int pipe = crtc->pipe;
3640 i915_reg_t reg;
3641 u32 temp;
3642
3643 /* enable normal train */
3644 reg = FDI_TX_CTL(pipe);
3645 temp = I915_READ(reg);
3646 if (IS_IVYBRIDGE(dev_priv)) {
3647 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3648 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3649 } else {
3650 temp &= ~FDI_LINK_TRAIN_NONE;
3651 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3652 }
3653 I915_WRITE(reg, temp);
3654
3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 if (HAS_PCH_CPT(dev_priv)) {
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3660 } else {
3661 temp &= ~FDI_LINK_TRAIN_NONE;
3662 temp |= FDI_LINK_TRAIN_NONE;
3663 }
3664 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3665
3666 /* wait one idle pattern time */
3667 POSTING_READ(reg);
3668 udelay(1000);
3669
3670 /* IVB wants error correction enabled */
3671 if (IS_IVYBRIDGE(dev_priv))
3672 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3673 FDI_FE_ERRC_ENABLE);
3674 }
3675
3676 /* The FDI link training functions for ILK/Ibexpeak. */
3677 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3678 const struct intel_crtc_state *crtc_state)
3679 {
3680 struct drm_device *dev = crtc->base.dev;
3681 struct drm_i915_private *dev_priv = to_i915(dev);
3682 int pipe = crtc->pipe;
3683 i915_reg_t reg;
3684 u32 temp, tries;
3685
3686 /* FDI needs bits from pipe first */
3687 assert_pipe_enabled(dev_priv, pipe);
3688
3689 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3690 for train result */
3691 reg = FDI_RX_IMR(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_RX_SYMBOL_LOCK;
3694 temp &= ~FDI_RX_BIT_LOCK;
3695 I915_WRITE(reg, temp);
3696 I915_READ(reg);
3697 udelay(150);
3698
3699 /* enable CPU FDI TX and PCH FDI RX */
3700 reg = FDI_TX_CTL(pipe);
3701 temp = I915_READ(reg);
3702 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3703 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3704 temp &= ~FDI_LINK_TRAIN_NONE;
3705 temp |= FDI_LINK_TRAIN_PATTERN_1;
3706 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3707
3708 reg = FDI_RX_CTL(pipe);
3709 temp = I915_READ(reg);
3710 temp &= ~FDI_LINK_TRAIN_NONE;
3711 temp |= FDI_LINK_TRAIN_PATTERN_1;
3712 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3713
3714 POSTING_READ(reg);
3715 udelay(150);
3716
3717 /* Ironlake workaround, enable clock pointer after FDI enable*/
3718 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3719 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3720 FDI_RX_PHASE_SYNC_POINTER_EN);
3721
3722 reg = FDI_RX_IIR(pipe);
3723 for (tries = 0; tries < 5; tries++) {
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727 if ((temp & FDI_RX_BIT_LOCK)) {
3728 DRM_DEBUG_KMS("FDI train 1 done.\n");
3729 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3730 break;
3731 }
3732 }
3733 if (tries == 5)
3734 DRM_ERROR("FDI train 1 fail!\n");
3735
3736 /* Train 2 */
3737 reg = FDI_TX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 temp &= ~FDI_LINK_TRAIN_NONE;
3740 temp |= FDI_LINK_TRAIN_PATTERN_2;
3741 I915_WRITE(reg, temp);
3742
3743 reg = FDI_RX_CTL(pipe);
3744 temp = I915_READ(reg);
3745 temp &= ~FDI_LINK_TRAIN_NONE;
3746 temp |= FDI_LINK_TRAIN_PATTERN_2;
3747 I915_WRITE(reg, temp);
3748
3749 POSTING_READ(reg);
3750 udelay(150);
3751
3752 reg = FDI_RX_IIR(pipe);
3753 for (tries = 0; tries < 5; tries++) {
3754 temp = I915_READ(reg);
3755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3756
3757 if (temp & FDI_RX_SYMBOL_LOCK) {
3758 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3759 DRM_DEBUG_KMS("FDI train 2 done.\n");
3760 break;
3761 }
3762 }
3763 if (tries == 5)
3764 DRM_ERROR("FDI train 2 fail!\n");
3765
3766 DRM_DEBUG_KMS("FDI train done\n");
3767
3768 }
3769
3770 static const int snb_b_fdi_train_param[] = {
3771 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3772 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3773 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3774 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3775 };
3776
3777 /* The FDI link training functions for SNB/Cougarpoint. */
3778 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3779 const struct intel_crtc_state *crtc_state)
3780 {
3781 struct drm_device *dev = crtc->base.dev;
3782 struct drm_i915_private *dev_priv = to_i915(dev);
3783 int pipe = crtc->pipe;
3784 i915_reg_t reg;
3785 u32 temp, i, retry;
3786
3787 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3788 for train result */
3789 reg = FDI_RX_IMR(pipe);
3790 temp = I915_READ(reg);
3791 temp &= ~FDI_RX_SYMBOL_LOCK;
3792 temp &= ~FDI_RX_BIT_LOCK;
3793 I915_WRITE(reg, temp);
3794
3795 POSTING_READ(reg);
3796 udelay(150);
3797
3798 /* enable CPU FDI TX and PCH FDI RX */
3799 reg = FDI_TX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3802 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3803 temp &= ~FDI_LINK_TRAIN_NONE;
3804 temp |= FDI_LINK_TRAIN_PATTERN_1;
3805 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3806 /* SNB-B */
3807 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3808 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3809
3810 I915_WRITE(FDI_RX_MISC(pipe),
3811 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 if (HAS_PCH_CPT(dev_priv)) {
3816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3817 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3818 } else {
3819 temp &= ~FDI_LINK_TRAIN_NONE;
3820 temp |= FDI_LINK_TRAIN_PATTERN_1;
3821 }
3822 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3823
3824 POSTING_READ(reg);
3825 udelay(150);
3826
3827 for (i = 0; i < 4; i++) {
3828 reg = FDI_TX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3831 temp |= snb_b_fdi_train_param[i];
3832 I915_WRITE(reg, temp);
3833
3834 POSTING_READ(reg);
3835 udelay(500);
3836
3837 for (retry = 0; retry < 5; retry++) {
3838 reg = FDI_RX_IIR(pipe);
3839 temp = I915_READ(reg);
3840 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3841 if (temp & FDI_RX_BIT_LOCK) {
3842 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3843 DRM_DEBUG_KMS("FDI train 1 done.\n");
3844 break;
3845 }
3846 udelay(50);
3847 }
3848 if (retry < 5)
3849 break;
3850 }
3851 if (i == 4)
3852 DRM_ERROR("FDI train 1 fail!\n");
3853
3854 /* Train 2 */
3855 reg = FDI_TX_CTL(pipe);
3856 temp = I915_READ(reg);
3857 temp &= ~FDI_LINK_TRAIN_NONE;
3858 temp |= FDI_LINK_TRAIN_PATTERN_2;
3859 if (IS_GEN6(dev_priv)) {
3860 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3861 /* SNB-B */
3862 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3863 }
3864 I915_WRITE(reg, temp);
3865
3866 reg = FDI_RX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 if (HAS_PCH_CPT(dev_priv)) {
3869 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3870 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3871 } else {
3872 temp &= ~FDI_LINK_TRAIN_NONE;
3873 temp |= FDI_LINK_TRAIN_PATTERN_2;
3874 }
3875 I915_WRITE(reg, temp);
3876
3877 POSTING_READ(reg);
3878 udelay(150);
3879
3880 for (i = 0; i < 4; i++) {
3881 reg = FDI_TX_CTL(pipe);
3882 temp = I915_READ(reg);
3883 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3884 temp |= snb_b_fdi_train_param[i];
3885 I915_WRITE(reg, temp);
3886
3887 POSTING_READ(reg);
3888 udelay(500);
3889
3890 for (retry = 0; retry < 5; retry++) {
3891 reg = FDI_RX_IIR(pipe);
3892 temp = I915_READ(reg);
3893 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3894 if (temp & FDI_RX_SYMBOL_LOCK) {
3895 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3896 DRM_DEBUG_KMS("FDI train 2 done.\n");
3897 break;
3898 }
3899 udelay(50);
3900 }
3901 if (retry < 5)
3902 break;
3903 }
3904 if (i == 4)
3905 DRM_ERROR("FDI train 2 fail!\n");
3906
3907 DRM_DEBUG_KMS("FDI train done.\n");
3908 }
3909
3910 /* Manual link training for Ivy Bridge A0 parts */
3911 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3912 const struct intel_crtc_state *crtc_state)
3913 {
3914 struct drm_device *dev = crtc->base.dev;
3915 struct drm_i915_private *dev_priv = to_i915(dev);
3916 int pipe = crtc->pipe;
3917 i915_reg_t reg;
3918 u32 temp, i, j;
3919
3920 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3921 for train result */
3922 reg = FDI_RX_IMR(pipe);
3923 temp = I915_READ(reg);
3924 temp &= ~FDI_RX_SYMBOL_LOCK;
3925 temp &= ~FDI_RX_BIT_LOCK;
3926 I915_WRITE(reg, temp);
3927
3928 POSTING_READ(reg);
3929 udelay(150);
3930
3931 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3932 I915_READ(FDI_RX_IIR(pipe)));
3933
3934 /* Try each vswing and preemphasis setting twice before moving on */
3935 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3936 /* disable first in case we need to retry */
3937 reg = FDI_TX_CTL(pipe);
3938 temp = I915_READ(reg);
3939 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3940 temp &= ~FDI_TX_ENABLE;
3941 I915_WRITE(reg, temp);
3942
3943 reg = FDI_RX_CTL(pipe);
3944 temp = I915_READ(reg);
3945 temp &= ~FDI_LINK_TRAIN_AUTO;
3946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3947 temp &= ~FDI_RX_ENABLE;
3948 I915_WRITE(reg, temp);
3949
3950 /* enable CPU FDI TX and PCH FDI RX */
3951 reg = FDI_TX_CTL(pipe);
3952 temp = I915_READ(reg);
3953 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3954 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3955 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3956 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3957 temp |= snb_b_fdi_train_param[j/2];
3958 temp |= FDI_COMPOSITE_SYNC;
3959 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3960
3961 I915_WRITE(FDI_RX_MISC(pipe),
3962 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3963
3964 reg = FDI_RX_CTL(pipe);
3965 temp = I915_READ(reg);
3966 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3967 temp |= FDI_COMPOSITE_SYNC;
3968 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3969
3970 POSTING_READ(reg);
3971 udelay(1); /* should be 0.5us */
3972
3973 for (i = 0; i < 4; i++) {
3974 reg = FDI_RX_IIR(pipe);
3975 temp = I915_READ(reg);
3976 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3977
3978 if (temp & FDI_RX_BIT_LOCK ||
3979 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3980 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3981 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3982 i);
3983 break;
3984 }
3985 udelay(1); /* should be 0.5us */
3986 }
3987 if (i == 4) {
3988 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3989 continue;
3990 }
3991
3992 /* Train 2 */
3993 reg = FDI_TX_CTL(pipe);
3994 temp = I915_READ(reg);
3995 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3996 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3997 I915_WRITE(reg, temp);
3998
3999 reg = FDI_RX_CTL(pipe);
4000 temp = I915_READ(reg);
4001 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4002 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4003 I915_WRITE(reg, temp);
4004
4005 POSTING_READ(reg);
4006 udelay(2); /* should be 1.5us */
4007
4008 for (i = 0; i < 4; i++) {
4009 reg = FDI_RX_IIR(pipe);
4010 temp = I915_READ(reg);
4011 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4012
4013 if (temp & FDI_RX_SYMBOL_LOCK ||
4014 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4015 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4016 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4017 i);
4018 goto train_done;
4019 }
4020 udelay(2); /* should be 1.5us */
4021 }
4022 if (i == 4)
4023 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4024 }
4025
4026 train_done:
4027 DRM_DEBUG_KMS("FDI train done.\n");
4028 }
4029
4030 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4031 {
4032 struct drm_device *dev = intel_crtc->base.dev;
4033 struct drm_i915_private *dev_priv = to_i915(dev);
4034 int pipe = intel_crtc->pipe;
4035 i915_reg_t reg;
4036 u32 temp;
4037
4038 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4039 reg = FDI_RX_CTL(pipe);
4040 temp = I915_READ(reg);
4041 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4042 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4043 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4044 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4045
4046 POSTING_READ(reg);
4047 udelay(200);
4048
4049 /* Switch from Rawclk to PCDclk */
4050 temp = I915_READ(reg);
4051 I915_WRITE(reg, temp | FDI_PCDCLK);
4052
4053 POSTING_READ(reg);
4054 udelay(200);
4055
4056 /* Enable CPU FDI TX PLL, always on for Ironlake */
4057 reg = FDI_TX_CTL(pipe);
4058 temp = I915_READ(reg);
4059 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4060 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4061
4062 POSTING_READ(reg);
4063 udelay(100);
4064 }
4065 }
4066
4067 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4068 {
4069 struct drm_device *dev = intel_crtc->base.dev;
4070 struct drm_i915_private *dev_priv = to_i915(dev);
4071 int pipe = intel_crtc->pipe;
4072 i915_reg_t reg;
4073 u32 temp;
4074
4075 /* Switch from PCDclk to Rawclk */
4076 reg = FDI_RX_CTL(pipe);
4077 temp = I915_READ(reg);
4078 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4079
4080 /* Disable CPU FDI TX PLL */
4081 reg = FDI_TX_CTL(pipe);
4082 temp = I915_READ(reg);
4083 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4084
4085 POSTING_READ(reg);
4086 udelay(100);
4087
4088 reg = FDI_RX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4091
4092 /* Wait for the clocks to turn off. */
4093 POSTING_READ(reg);
4094 udelay(100);
4095 }
4096
4097 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4098 {
4099 struct drm_device *dev = crtc->dev;
4100 struct drm_i915_private *dev_priv = to_i915(dev);
4101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102 int pipe = intel_crtc->pipe;
4103 i915_reg_t reg;
4104 u32 temp;
4105
4106 /* disable CPU FDI tx and PCH FDI rx */
4107 reg = FDI_TX_CTL(pipe);
4108 temp = I915_READ(reg);
4109 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4110 POSTING_READ(reg);
4111
4112 reg = FDI_RX_CTL(pipe);
4113 temp = I915_READ(reg);
4114 temp &= ~(0x7 << 16);
4115 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4116 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4117
4118 POSTING_READ(reg);
4119 udelay(100);
4120
4121 /* Ironlake workaround, disable clock pointer after downing FDI */
4122 if (HAS_PCH_IBX(dev_priv))
4123 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4124
4125 /* still set train pattern 1 */
4126 reg = FDI_TX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 temp &= ~FDI_LINK_TRAIN_NONE;
4129 temp |= FDI_LINK_TRAIN_PATTERN_1;
4130 I915_WRITE(reg, temp);
4131
4132 reg = FDI_RX_CTL(pipe);
4133 temp = I915_READ(reg);
4134 if (HAS_PCH_CPT(dev_priv)) {
4135 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4136 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4137 } else {
4138 temp &= ~FDI_LINK_TRAIN_NONE;
4139 temp |= FDI_LINK_TRAIN_PATTERN_1;
4140 }
4141 /* BPC in FDI rx is consistent with that in PIPECONF */
4142 temp &= ~(0x07 << 16);
4143 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4144 I915_WRITE(reg, temp);
4145
4146 POSTING_READ(reg);
4147 udelay(100);
4148 }
4149
4150 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4151 {
4152 struct intel_crtc *crtc;
4153
4154 /* Note that we don't need to be called with mode_config.lock here
4155 * as our list of CRTC objects is static for the lifetime of the
4156 * device and so cannot disappear as we iterate. Similarly, we can
4157 * happily treat the predicates as racy, atomic checks as userspace
4158 * cannot claim and pin a new fb without at least acquring the
4159 * struct_mutex and so serialising with us.
4160 */
4161 for_each_intel_crtc(&dev_priv->drm, crtc) {
4162 if (atomic_read(&crtc->unpin_work_count) == 0)
4163 continue;
4164
4165 if (crtc->flip_work)
4166 intel_wait_for_vblank(dev_priv, crtc->pipe);
4167
4168 return true;
4169 }
4170
4171 return false;
4172 }
4173
4174 static void page_flip_completed(struct intel_crtc *intel_crtc)
4175 {
4176 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4177 struct intel_flip_work *work = intel_crtc->flip_work;
4178
4179 intel_crtc->flip_work = NULL;
4180
4181 if (work->event)
4182 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4183
4184 drm_crtc_vblank_put(&intel_crtc->base);
4185
4186 wake_up_all(&dev_priv->pending_flip_queue);
4187 trace_i915_flip_complete(intel_crtc->plane,
4188 work->pending_flip_obj);
4189
4190 queue_work(dev_priv->wq, &work->unpin_work);
4191 }
4192
4193 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4194 {
4195 struct drm_device *dev = crtc->dev;
4196 struct drm_i915_private *dev_priv = to_i915(dev);
4197 long ret;
4198
4199 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4200
4201 ret = wait_event_interruptible_timeout(
4202 dev_priv->pending_flip_queue,
4203 !intel_crtc_has_pending_flip(crtc),
4204 60*HZ);
4205
4206 if (ret < 0)
4207 return ret;
4208
4209 if (ret == 0) {
4210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211 struct intel_flip_work *work;
4212
4213 spin_lock_irq(&dev->event_lock);
4214 work = intel_crtc->flip_work;
4215 if (work && !is_mmio_work(work)) {
4216 WARN_ONCE(1, "Removing stuck page flip\n");
4217 page_flip_completed(intel_crtc);
4218 }
4219 spin_unlock_irq(&dev->event_lock);
4220 }
4221
4222 return 0;
4223 }
4224
4225 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4226 {
4227 u32 temp;
4228
4229 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4230
4231 mutex_lock(&dev_priv->sb_lock);
4232
4233 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4234 temp |= SBI_SSCCTL_DISABLE;
4235 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4236
4237 mutex_unlock(&dev_priv->sb_lock);
4238 }
4239
4240 /* Program iCLKIP clock to the desired frequency */
4241 static void lpt_program_iclkip(struct intel_crtc *crtc)
4242 {
4243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4244 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4245 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4246 u32 temp;
4247
4248 lpt_disable_iclkip(dev_priv);
4249
4250 /* The iCLK virtual clock root frequency is in MHz,
4251 * but the adjusted_mode->crtc_clock in in KHz. To get the
4252 * divisors, it is necessary to divide one by another, so we
4253 * convert the virtual clock precision to KHz here for higher
4254 * precision.
4255 */
4256 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4257 u32 iclk_virtual_root_freq = 172800 * 1000;
4258 u32 iclk_pi_range = 64;
4259 u32 desired_divisor;
4260
4261 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4262 clock << auxdiv);
4263 divsel = (desired_divisor / iclk_pi_range) - 2;
4264 phaseinc = desired_divisor % iclk_pi_range;
4265
4266 /*
4267 * Near 20MHz is a corner case which is
4268 * out of range for the 7-bit divisor
4269 */
4270 if (divsel <= 0x7f)
4271 break;
4272 }
4273
4274 /* This should not happen with any sane values */
4275 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4276 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4277 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4278 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4279
4280 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4281 clock,
4282 auxdiv,
4283 divsel,
4284 phasedir,
4285 phaseinc);
4286
4287 mutex_lock(&dev_priv->sb_lock);
4288
4289 /* Program SSCDIVINTPHASE6 */
4290 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4291 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4292 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4293 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4294 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4295 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4296 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4297 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4298
4299 /* Program SSCAUXDIV */
4300 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4301 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4302 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4303 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4304
4305 /* Enable modulator and associated divider */
4306 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4307 temp &= ~SBI_SSCCTL_DISABLE;
4308 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4309
4310 mutex_unlock(&dev_priv->sb_lock);
4311
4312 /* Wait for initialization time */
4313 udelay(24);
4314
4315 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4316 }
4317
4318 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4319 {
4320 u32 divsel, phaseinc, auxdiv;
4321 u32 iclk_virtual_root_freq = 172800 * 1000;
4322 u32 iclk_pi_range = 64;
4323 u32 desired_divisor;
4324 u32 temp;
4325
4326 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4327 return 0;
4328
4329 mutex_lock(&dev_priv->sb_lock);
4330
4331 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4332 if (temp & SBI_SSCCTL_DISABLE) {
4333 mutex_unlock(&dev_priv->sb_lock);
4334 return 0;
4335 }
4336
4337 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4338 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4339 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4340 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4341 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4342
4343 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4344 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4345 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4346
4347 mutex_unlock(&dev_priv->sb_lock);
4348
4349 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4350
4351 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4352 desired_divisor << auxdiv);
4353 }
4354
4355 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4356 enum pipe pch_transcoder)
4357 {
4358 struct drm_device *dev = crtc->base.dev;
4359 struct drm_i915_private *dev_priv = to_i915(dev);
4360 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4361
4362 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4363 I915_READ(HTOTAL(cpu_transcoder)));
4364 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4365 I915_READ(HBLANK(cpu_transcoder)));
4366 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4367 I915_READ(HSYNC(cpu_transcoder)));
4368
4369 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4370 I915_READ(VTOTAL(cpu_transcoder)));
4371 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4372 I915_READ(VBLANK(cpu_transcoder)));
4373 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4374 I915_READ(VSYNC(cpu_transcoder)));
4375 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4376 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4377 }
4378
4379 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4380 {
4381 struct drm_i915_private *dev_priv = to_i915(dev);
4382 uint32_t temp;
4383
4384 temp = I915_READ(SOUTH_CHICKEN1);
4385 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4386 return;
4387
4388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4389 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4390
4391 temp &= ~FDI_BC_BIFURCATION_SELECT;
4392 if (enable)
4393 temp |= FDI_BC_BIFURCATION_SELECT;
4394
4395 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4396 I915_WRITE(SOUTH_CHICKEN1, temp);
4397 POSTING_READ(SOUTH_CHICKEN1);
4398 }
4399
4400 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4401 {
4402 struct drm_device *dev = intel_crtc->base.dev;
4403
4404 switch (intel_crtc->pipe) {
4405 case PIPE_A:
4406 break;
4407 case PIPE_B:
4408 if (intel_crtc->config->fdi_lanes > 2)
4409 cpt_set_fdi_bc_bifurcation(dev, false);
4410 else
4411 cpt_set_fdi_bc_bifurcation(dev, true);
4412
4413 break;
4414 case PIPE_C:
4415 cpt_set_fdi_bc_bifurcation(dev, true);
4416
4417 break;
4418 default:
4419 BUG();
4420 }
4421 }
4422
4423 /* Return which DP Port should be selected for Transcoder DP control */
4424 static enum port
4425 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4426 {
4427 struct drm_device *dev = crtc->base.dev;
4428 struct intel_encoder *encoder;
4429
4430 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4431 if (encoder->type == INTEL_OUTPUT_DP ||
4432 encoder->type == INTEL_OUTPUT_EDP)
4433 return enc_to_dig_port(&encoder->base)->port;
4434 }
4435
4436 return -1;
4437 }
4438
4439 /*
4440 * Enable PCH resources required for PCH ports:
4441 * - PCH PLLs
4442 * - FDI training & RX/TX
4443 * - update transcoder timings
4444 * - DP transcoding bits
4445 * - transcoder
4446 */
4447 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4448 {
4449 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4450 struct drm_device *dev = crtc->base.dev;
4451 struct drm_i915_private *dev_priv = to_i915(dev);
4452 int pipe = crtc->pipe;
4453 u32 temp;
4454
4455 assert_pch_transcoder_disabled(dev_priv, pipe);
4456
4457 if (IS_IVYBRIDGE(dev_priv))
4458 ivybridge_update_fdi_bc_bifurcation(crtc);
4459
4460 /* Write the TU size bits before fdi link training, so that error
4461 * detection works. */
4462 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4463 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4464
4465 /* For PCH output, training FDI link */
4466 dev_priv->display.fdi_link_train(crtc, crtc_state);
4467
4468 /* We need to program the right clock selection before writing the pixel
4469 * mutliplier into the DPLL. */
4470 if (HAS_PCH_CPT(dev_priv)) {
4471 u32 sel;
4472
4473 temp = I915_READ(PCH_DPLL_SEL);
4474 temp |= TRANS_DPLL_ENABLE(pipe);
4475 sel = TRANS_DPLLB_SEL(pipe);
4476 if (crtc_state->shared_dpll ==
4477 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4478 temp |= sel;
4479 else
4480 temp &= ~sel;
4481 I915_WRITE(PCH_DPLL_SEL, temp);
4482 }
4483
4484 /* XXX: pch pll's can be enabled any time before we enable the PCH
4485 * transcoder, and we actually should do this to not upset any PCH
4486 * transcoder that already use the clock when we share it.
4487 *
4488 * Note that enable_shared_dpll tries to do the right thing, but
4489 * get_shared_dpll unconditionally resets the pll - we need that to have
4490 * the right LVDS enable sequence. */
4491 intel_enable_shared_dpll(crtc);
4492
4493 /* set transcoder timing, panel must allow it */
4494 assert_panel_unlocked(dev_priv, pipe);
4495 ironlake_pch_transcoder_set_timings(crtc, pipe);
4496
4497 intel_fdi_normal_train(crtc);
4498
4499 /* For PCH DP, enable TRANS_DP_CTL */
4500 if (HAS_PCH_CPT(dev_priv) &&
4501 intel_crtc_has_dp_encoder(crtc_state)) {
4502 const struct drm_display_mode *adjusted_mode =
4503 &crtc_state->base.adjusted_mode;
4504 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4505 i915_reg_t reg = TRANS_DP_CTL(pipe);
4506 temp = I915_READ(reg);
4507 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4508 TRANS_DP_SYNC_MASK |
4509 TRANS_DP_BPC_MASK);
4510 temp |= TRANS_DP_OUTPUT_ENABLE;
4511 temp |= bpc << 9; /* same format but at 11:9 */
4512
4513 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4514 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4515 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4516 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4517
4518 switch (intel_trans_dp_port_sel(crtc)) {
4519 case PORT_B:
4520 temp |= TRANS_DP_PORT_SEL_B;
4521 break;
4522 case PORT_C:
4523 temp |= TRANS_DP_PORT_SEL_C;
4524 break;
4525 case PORT_D:
4526 temp |= TRANS_DP_PORT_SEL_D;
4527 break;
4528 default:
4529 BUG();
4530 }
4531
4532 I915_WRITE(reg, temp);
4533 }
4534
4535 ironlake_enable_pch_transcoder(dev_priv, pipe);
4536 }
4537
4538 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4539 {
4540 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4542 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4543
4544 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4545
4546 lpt_program_iclkip(crtc);
4547
4548 /* Set transcoder timing. */
4549 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4550
4551 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4552 }
4553
4554 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4555 {
4556 struct drm_i915_private *dev_priv = to_i915(dev);
4557 i915_reg_t dslreg = PIPEDSL(pipe);
4558 u32 temp;
4559
4560 temp = I915_READ(dslreg);
4561 udelay(500);
4562 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4563 if (wait_for(I915_READ(dslreg) != temp, 5))
4564 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4565 }
4566 }
4567
4568 static int
4569 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4570 unsigned int scaler_user, int *scaler_id,
4571 int src_w, int src_h, int dst_w, int dst_h)
4572 {
4573 struct intel_crtc_scaler_state *scaler_state =
4574 &crtc_state->scaler_state;
4575 struct intel_crtc *intel_crtc =
4576 to_intel_crtc(crtc_state->base.crtc);
4577 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4578 const struct drm_display_mode *adjusted_mode =
4579 &crtc_state->base.adjusted_mode;
4580 int need_scaling;
4581
4582 /*
4583 * Src coordinates are already rotated by 270 degrees for
4584 * the 90/270 degree plane rotation cases (to match the
4585 * GTT mapping), hence no need to account for rotation here.
4586 */
4587 need_scaling = src_w != dst_w || src_h != dst_h;
4588
4589 /*
4590 * Scaling/fitting not supported in IF-ID mode in GEN9+
4591 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4592 * Once NV12 is enabled, handle it here while allocating scaler
4593 * for NV12.
4594 */
4595 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4596 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4597 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4598 return -EINVAL;
4599 }
4600
4601 /*
4602 * if plane is being disabled or scaler is no more required or force detach
4603 * - free scaler binded to this plane/crtc
4604 * - in order to do this, update crtc->scaler_usage
4605 *
4606 * Here scaler state in crtc_state is set free so that
4607 * scaler can be assigned to other user. Actual register
4608 * update to free the scaler is done in plane/panel-fit programming.
4609 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4610 */
4611 if (force_detach || !need_scaling) {
4612 if (*scaler_id >= 0) {
4613 scaler_state->scaler_users &= ~(1 << scaler_user);
4614 scaler_state->scalers[*scaler_id].in_use = 0;
4615
4616 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4617 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4618 intel_crtc->pipe, scaler_user, *scaler_id,
4619 scaler_state->scaler_users);
4620 *scaler_id = -1;
4621 }
4622 return 0;
4623 }
4624
4625 /* range checks */
4626 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4627 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4628
4629 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4630 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4631 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4632 "size is out of scaler range\n",
4633 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4634 return -EINVAL;
4635 }
4636
4637 /* mark this plane as a scaler user in crtc_state */
4638 scaler_state->scaler_users |= (1 << scaler_user);
4639 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4640 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4641 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4642 scaler_state->scaler_users);
4643
4644 return 0;
4645 }
4646
4647 /**
4648 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4649 *
4650 * @state: crtc's scaler state
4651 *
4652 * Return
4653 * 0 - scaler_usage updated successfully
4654 * error - requested scaling cannot be supported or other error condition
4655 */
4656 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4657 {
4658 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4659
4660 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4661 &state->scaler_state.scaler_id,
4662 state->pipe_src_w, state->pipe_src_h,
4663 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4664 }
4665
4666 /**
4667 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4668 *
4669 * @state: crtc's scaler state
4670 * @plane_state: atomic plane state to update
4671 *
4672 * Return
4673 * 0 - scaler_usage updated successfully
4674 * error - requested scaling cannot be supported or other error condition
4675 */
4676 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4677 struct intel_plane_state *plane_state)
4678 {
4679
4680 struct intel_plane *intel_plane =
4681 to_intel_plane(plane_state->base.plane);
4682 struct drm_framebuffer *fb = plane_state->base.fb;
4683 int ret;
4684
4685 bool force_detach = !fb || !plane_state->base.visible;
4686
4687 ret = skl_update_scaler(crtc_state, force_detach,
4688 drm_plane_index(&intel_plane->base),
4689 &plane_state->scaler_id,
4690 drm_rect_width(&plane_state->base.src) >> 16,
4691 drm_rect_height(&plane_state->base.src) >> 16,
4692 drm_rect_width(&plane_state->base.dst),
4693 drm_rect_height(&plane_state->base.dst));
4694
4695 if (ret || plane_state->scaler_id < 0)
4696 return ret;
4697
4698 /* check colorkey */
4699 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4700 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4701 intel_plane->base.base.id,
4702 intel_plane->base.name);
4703 return -EINVAL;
4704 }
4705
4706 /* Check src format */
4707 switch (fb->format->format) {
4708 case DRM_FORMAT_RGB565:
4709 case DRM_FORMAT_XBGR8888:
4710 case DRM_FORMAT_XRGB8888:
4711 case DRM_FORMAT_ABGR8888:
4712 case DRM_FORMAT_ARGB8888:
4713 case DRM_FORMAT_XRGB2101010:
4714 case DRM_FORMAT_XBGR2101010:
4715 case DRM_FORMAT_YUYV:
4716 case DRM_FORMAT_YVYU:
4717 case DRM_FORMAT_UYVY:
4718 case DRM_FORMAT_VYUY:
4719 break;
4720 default:
4721 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4722 intel_plane->base.base.id, intel_plane->base.name,
4723 fb->base.id, fb->format->format);
4724 return -EINVAL;
4725 }
4726
4727 return 0;
4728 }
4729
4730 static void skylake_scaler_disable(struct intel_crtc *crtc)
4731 {
4732 int i;
4733
4734 for (i = 0; i < crtc->num_scalers; i++)
4735 skl_detach_scaler(crtc, i);
4736 }
4737
4738 static void skylake_pfit_enable(struct intel_crtc *crtc)
4739 {
4740 struct drm_device *dev = crtc->base.dev;
4741 struct drm_i915_private *dev_priv = to_i915(dev);
4742 int pipe = crtc->pipe;
4743 struct intel_crtc_scaler_state *scaler_state =
4744 &crtc->config->scaler_state;
4745
4746 if (crtc->config->pch_pfit.enabled) {
4747 int id;
4748
4749 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4750 return;
4751
4752 id = scaler_state->scaler_id;
4753 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4754 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4755 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4756 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4757 }
4758 }
4759
4760 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4761 {
4762 struct drm_device *dev = crtc->base.dev;
4763 struct drm_i915_private *dev_priv = to_i915(dev);
4764 int pipe = crtc->pipe;
4765
4766 if (crtc->config->pch_pfit.enabled) {
4767 /* Force use of hard-coded filter coefficients
4768 * as some pre-programmed values are broken,
4769 * e.g. x201.
4770 */
4771 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4772 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4773 PF_PIPE_SEL_IVB(pipe));
4774 else
4775 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4776 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4777 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4778 }
4779 }
4780
4781 void hsw_enable_ips(struct intel_crtc *crtc)
4782 {
4783 struct drm_device *dev = crtc->base.dev;
4784 struct drm_i915_private *dev_priv = to_i915(dev);
4785
4786 if (!crtc->config->ips_enabled)
4787 return;
4788
4789 /*
4790 * We can only enable IPS after we enable a plane and wait for a vblank
4791 * This function is called from post_plane_update, which is run after
4792 * a vblank wait.
4793 */
4794
4795 assert_plane_enabled(dev_priv, crtc->plane);
4796 if (IS_BROADWELL(dev_priv)) {
4797 mutex_lock(&dev_priv->rps.hw_lock);
4798 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4799 mutex_unlock(&dev_priv->rps.hw_lock);
4800 /* Quoting Art Runyan: "its not safe to expect any particular
4801 * value in IPS_CTL bit 31 after enabling IPS through the
4802 * mailbox." Moreover, the mailbox may return a bogus state,
4803 * so we need to just enable it and continue on.
4804 */
4805 } else {
4806 I915_WRITE(IPS_CTL, IPS_ENABLE);
4807 /* The bit only becomes 1 in the next vblank, so this wait here
4808 * is essentially intel_wait_for_vblank. If we don't have this
4809 * and don't wait for vblanks until the end of crtc_enable, then
4810 * the HW state readout code will complain that the expected
4811 * IPS_CTL value is not the one we read. */
4812 if (intel_wait_for_register(dev_priv,
4813 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4814 50))
4815 DRM_ERROR("Timed out waiting for IPS enable\n");
4816 }
4817 }
4818
4819 void hsw_disable_ips(struct intel_crtc *crtc)
4820 {
4821 struct drm_device *dev = crtc->base.dev;
4822 struct drm_i915_private *dev_priv = to_i915(dev);
4823
4824 if (!crtc->config->ips_enabled)
4825 return;
4826
4827 assert_plane_enabled(dev_priv, crtc->plane);
4828 if (IS_BROADWELL(dev_priv)) {
4829 mutex_lock(&dev_priv->rps.hw_lock);
4830 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4831 mutex_unlock(&dev_priv->rps.hw_lock);
4832 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4833 if (intel_wait_for_register(dev_priv,
4834 IPS_CTL, IPS_ENABLE, 0,
4835 42))
4836 DRM_ERROR("Timed out waiting for IPS disable\n");
4837 } else {
4838 I915_WRITE(IPS_CTL, 0);
4839 POSTING_READ(IPS_CTL);
4840 }
4841
4842 /* We need to wait for a vblank before we can disable the plane. */
4843 intel_wait_for_vblank(dev_priv, crtc->pipe);
4844 }
4845
4846 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4847 {
4848 if (intel_crtc->overlay) {
4849 struct drm_device *dev = intel_crtc->base.dev;
4850
4851 mutex_lock(&dev->struct_mutex);
4852 (void) intel_overlay_switch_off(intel_crtc->overlay);
4853 mutex_unlock(&dev->struct_mutex);
4854 }
4855
4856 /* Let userspace switch the overlay on again. In most cases userspace
4857 * has to recompute where to put it anyway.
4858 */
4859 }
4860
4861 /**
4862 * intel_post_enable_primary - Perform operations after enabling primary plane
4863 * @crtc: the CRTC whose primary plane was just enabled
4864 *
4865 * Performs potentially sleeping operations that must be done after the primary
4866 * plane is enabled, such as updating FBC and IPS. Note that this may be
4867 * called due to an explicit primary plane update, or due to an implicit
4868 * re-enable that is caused when a sprite plane is updated to no longer
4869 * completely hide the primary plane.
4870 */
4871 static void
4872 intel_post_enable_primary(struct drm_crtc *crtc)
4873 {
4874 struct drm_device *dev = crtc->dev;
4875 struct drm_i915_private *dev_priv = to_i915(dev);
4876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4877 int pipe = intel_crtc->pipe;
4878
4879 /*
4880 * FIXME IPS should be fine as long as one plane is
4881 * enabled, but in practice it seems to have problems
4882 * when going from primary only to sprite only and vice
4883 * versa.
4884 */
4885 hsw_enable_ips(intel_crtc);
4886
4887 /*
4888 * Gen2 reports pipe underruns whenever all planes are disabled.
4889 * So don't enable underrun reporting before at least some planes
4890 * are enabled.
4891 * FIXME: Need to fix the logic to work when we turn off all planes
4892 * but leave the pipe running.
4893 */
4894 if (IS_GEN2(dev_priv))
4895 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4896
4897 /* Underruns don't always raise interrupts, so check manually. */
4898 intel_check_cpu_fifo_underruns(dev_priv);
4899 intel_check_pch_fifo_underruns(dev_priv);
4900 }
4901
4902 /* FIXME move all this to pre_plane_update() with proper state tracking */
4903 static void
4904 intel_pre_disable_primary(struct drm_crtc *crtc)
4905 {
4906 struct drm_device *dev = crtc->dev;
4907 struct drm_i915_private *dev_priv = to_i915(dev);
4908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4909 int pipe = intel_crtc->pipe;
4910
4911 /*
4912 * Gen2 reports pipe underruns whenever all planes are disabled.
4913 * So diasble underrun reporting before all the planes get disabled.
4914 * FIXME: Need to fix the logic to work when we turn off all planes
4915 * but leave the pipe running.
4916 */
4917 if (IS_GEN2(dev_priv))
4918 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4919
4920 /*
4921 * FIXME IPS should be fine as long as one plane is
4922 * enabled, but in practice it seems to have problems
4923 * when going from primary only to sprite only and vice
4924 * versa.
4925 */
4926 hsw_disable_ips(intel_crtc);
4927 }
4928
4929 /* FIXME get rid of this and use pre_plane_update */
4930 static void
4931 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4932 {
4933 struct drm_device *dev = crtc->dev;
4934 struct drm_i915_private *dev_priv = to_i915(dev);
4935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4936 int pipe = intel_crtc->pipe;
4937
4938 intel_pre_disable_primary(crtc);
4939
4940 /*
4941 * Vblank time updates from the shadow to live plane control register
4942 * are blocked if the memory self-refresh mode is active at that
4943 * moment. So to make sure the plane gets truly disabled, disable
4944 * first the self-refresh mode. The self-refresh enable bit in turn
4945 * will be checked/applied by the HW only at the next frame start
4946 * event which is after the vblank start event, so we need to have a
4947 * wait-for-vblank between disabling the plane and the pipe.
4948 */
4949 if (HAS_GMCH_DISPLAY(dev_priv) &&
4950 intel_set_memory_cxsr(dev_priv, false))
4951 intel_wait_for_vblank(dev_priv, pipe);
4952 }
4953
4954 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4955 {
4956 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4957 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4958 struct intel_crtc_state *pipe_config =
4959 to_intel_crtc_state(crtc->base.state);
4960 struct drm_plane *primary = crtc->base.primary;
4961 struct drm_plane_state *old_pri_state =
4962 drm_atomic_get_existing_plane_state(old_state, primary);
4963
4964 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4965
4966 if (pipe_config->update_wm_post && pipe_config->base.active)
4967 intel_update_watermarks(crtc);
4968
4969 if (old_pri_state) {
4970 struct intel_plane_state *primary_state =
4971 to_intel_plane_state(primary->state);
4972 struct intel_plane_state *old_primary_state =
4973 to_intel_plane_state(old_pri_state);
4974
4975 intel_fbc_post_update(crtc);
4976
4977 if (primary_state->base.visible &&
4978 (needs_modeset(&pipe_config->base) ||
4979 !old_primary_state->base.visible))
4980 intel_post_enable_primary(&crtc->base);
4981 }
4982 }
4983
4984 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
4985 struct intel_crtc_state *pipe_config)
4986 {
4987 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4988 struct drm_device *dev = crtc->base.dev;
4989 struct drm_i915_private *dev_priv = to_i915(dev);
4990 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4991 struct drm_plane *primary = crtc->base.primary;
4992 struct drm_plane_state *old_pri_state =
4993 drm_atomic_get_existing_plane_state(old_state, primary);
4994 bool modeset = needs_modeset(&pipe_config->base);
4995 struct intel_atomic_state *old_intel_state =
4996 to_intel_atomic_state(old_state);
4997
4998 if (old_pri_state) {
4999 struct intel_plane_state *primary_state =
5000 to_intel_plane_state(primary->state);
5001 struct intel_plane_state *old_primary_state =
5002 to_intel_plane_state(old_pri_state);
5003
5004 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5005
5006 if (old_primary_state->base.visible &&
5007 (modeset || !primary_state->base.visible))
5008 intel_pre_disable_primary(&crtc->base);
5009 }
5010
5011 /*
5012 * Vblank time updates from the shadow to live plane control register
5013 * are blocked if the memory self-refresh mode is active at that
5014 * moment. So to make sure the plane gets truly disabled, disable
5015 * first the self-refresh mode. The self-refresh enable bit in turn
5016 * will be checked/applied by the HW only at the next frame start
5017 * event which is after the vblank start event, so we need to have a
5018 * wait-for-vblank between disabling the plane and the pipe.
5019 */
5020 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5021 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5022 intel_wait_for_vblank(dev_priv, crtc->pipe);
5023
5024 /*
5025 * IVB workaround: must disable low power watermarks for at least
5026 * one frame before enabling scaling. LP watermarks can be re-enabled
5027 * when scaling is disabled.
5028 *
5029 * WaCxSRDisabledForSpriteScaling:ivb
5030 */
5031 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5032 intel_wait_for_vblank(dev_priv, crtc->pipe);
5033
5034 /*
5035 * If we're doing a modeset, we're done. No need to do any pre-vblank
5036 * watermark programming here.
5037 */
5038 if (needs_modeset(&pipe_config->base))
5039 return;
5040
5041 /*
5042 * For platforms that support atomic watermarks, program the
5043 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5044 * will be the intermediate values that are safe for both pre- and
5045 * post- vblank; when vblank happens, the 'active' values will be set
5046 * to the final 'target' values and we'll do this again to get the
5047 * optimal watermarks. For gen9+ platforms, the values we program here
5048 * will be the final target values which will get automatically latched
5049 * at vblank time; no further programming will be necessary.
5050 *
5051 * If a platform hasn't been transitioned to atomic watermarks yet,
5052 * we'll continue to update watermarks the old way, if flags tell
5053 * us to.
5054 */
5055 if (dev_priv->display.initial_watermarks != NULL)
5056 dev_priv->display.initial_watermarks(old_intel_state,
5057 pipe_config);
5058 else if (pipe_config->update_wm_pre)
5059 intel_update_watermarks(crtc);
5060 }
5061
5062 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5063 {
5064 struct drm_device *dev = crtc->dev;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 struct drm_plane *p;
5067 int pipe = intel_crtc->pipe;
5068
5069 intel_crtc_dpms_overlay_disable(intel_crtc);
5070
5071 drm_for_each_plane_mask(p, dev, plane_mask)
5072 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5073
5074 /*
5075 * FIXME: Once we grow proper nuclear flip support out of this we need
5076 * to compute the mask of flip planes precisely. For the time being
5077 * consider this a flip to a NULL plane.
5078 */
5079 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5080 }
5081
5082 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5083 struct intel_crtc_state *crtc_state,
5084 struct drm_atomic_state *old_state)
5085 {
5086 struct drm_connector_state *conn_state;
5087 struct drm_connector *conn;
5088 int i;
5089
5090 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5091 struct intel_encoder *encoder =
5092 to_intel_encoder(conn_state->best_encoder);
5093
5094 if (conn_state->crtc != crtc)
5095 continue;
5096
5097 if (encoder->pre_pll_enable)
5098 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5099 }
5100 }
5101
5102 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5103 struct intel_crtc_state *crtc_state,
5104 struct drm_atomic_state *old_state)
5105 {
5106 struct drm_connector_state *conn_state;
5107 struct drm_connector *conn;
5108 int i;
5109
5110 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5111 struct intel_encoder *encoder =
5112 to_intel_encoder(conn_state->best_encoder);
5113
5114 if (conn_state->crtc != crtc)
5115 continue;
5116
5117 if (encoder->pre_enable)
5118 encoder->pre_enable(encoder, crtc_state, conn_state);
5119 }
5120 }
5121
5122 static void intel_encoders_enable(struct drm_crtc *crtc,
5123 struct intel_crtc_state *crtc_state,
5124 struct drm_atomic_state *old_state)
5125 {
5126 struct drm_connector_state *conn_state;
5127 struct drm_connector *conn;
5128 int i;
5129
5130 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5131 struct intel_encoder *encoder =
5132 to_intel_encoder(conn_state->best_encoder);
5133
5134 if (conn_state->crtc != crtc)
5135 continue;
5136
5137 encoder->enable(encoder, crtc_state, conn_state);
5138 intel_opregion_notify_encoder(encoder, true);
5139 }
5140 }
5141
5142 static void intel_encoders_disable(struct drm_crtc *crtc,
5143 struct intel_crtc_state *old_crtc_state,
5144 struct drm_atomic_state *old_state)
5145 {
5146 struct drm_connector_state *old_conn_state;
5147 struct drm_connector *conn;
5148 int i;
5149
5150 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5151 struct intel_encoder *encoder =
5152 to_intel_encoder(old_conn_state->best_encoder);
5153
5154 if (old_conn_state->crtc != crtc)
5155 continue;
5156
5157 intel_opregion_notify_encoder(encoder, false);
5158 encoder->disable(encoder, old_crtc_state, old_conn_state);
5159 }
5160 }
5161
5162 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5163 struct intel_crtc_state *old_crtc_state,
5164 struct drm_atomic_state *old_state)
5165 {
5166 struct drm_connector_state *old_conn_state;
5167 struct drm_connector *conn;
5168 int i;
5169
5170 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5171 struct intel_encoder *encoder =
5172 to_intel_encoder(old_conn_state->best_encoder);
5173
5174 if (old_conn_state->crtc != crtc)
5175 continue;
5176
5177 if (encoder->post_disable)
5178 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5179 }
5180 }
5181
5182 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5183 struct intel_crtc_state *old_crtc_state,
5184 struct drm_atomic_state *old_state)
5185 {
5186 struct drm_connector_state *old_conn_state;
5187 struct drm_connector *conn;
5188 int i;
5189
5190 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5191 struct intel_encoder *encoder =
5192 to_intel_encoder(old_conn_state->best_encoder);
5193
5194 if (old_conn_state->crtc != crtc)
5195 continue;
5196
5197 if (encoder->post_pll_disable)
5198 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5199 }
5200 }
5201
5202 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5203 struct drm_atomic_state *old_state)
5204 {
5205 struct drm_crtc *crtc = pipe_config->base.crtc;
5206 struct drm_device *dev = crtc->dev;
5207 struct drm_i915_private *dev_priv = to_i915(dev);
5208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5209 int pipe = intel_crtc->pipe;
5210 struct intel_atomic_state *old_intel_state =
5211 to_intel_atomic_state(old_state);
5212
5213 if (WARN_ON(intel_crtc->active))
5214 return;
5215
5216 /*
5217 * Sometimes spurious CPU pipe underruns happen during FDI
5218 * training, at least with VGA+HDMI cloning. Suppress them.
5219 *
5220 * On ILK we get an occasional spurious CPU pipe underruns
5221 * between eDP port A enable and vdd enable. Also PCH port
5222 * enable seems to result in the occasional CPU pipe underrun.
5223 *
5224 * Spurious PCH underruns also occur during PCH enabling.
5225 */
5226 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5227 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5228 if (intel_crtc->config->has_pch_encoder)
5229 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5230
5231 if (intel_crtc->config->has_pch_encoder)
5232 intel_prepare_shared_dpll(intel_crtc);
5233
5234 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5235 intel_dp_set_m_n(intel_crtc, M1_N1);
5236
5237 intel_set_pipe_timings(intel_crtc);
5238 intel_set_pipe_src_size(intel_crtc);
5239
5240 if (intel_crtc->config->has_pch_encoder) {
5241 intel_cpu_transcoder_set_m_n(intel_crtc,
5242 &intel_crtc->config->fdi_m_n, NULL);
5243 }
5244
5245 ironlake_set_pipeconf(crtc);
5246
5247 intel_crtc->active = true;
5248
5249 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5250
5251 if (intel_crtc->config->has_pch_encoder) {
5252 /* Note: FDI PLL enabling _must_ be done before we enable the
5253 * cpu pipes, hence this is separate from all the other fdi/pch
5254 * enabling. */
5255 ironlake_fdi_pll_enable(intel_crtc);
5256 } else {
5257 assert_fdi_tx_disabled(dev_priv, pipe);
5258 assert_fdi_rx_disabled(dev_priv, pipe);
5259 }
5260
5261 ironlake_pfit_enable(intel_crtc);
5262
5263 /*
5264 * On ILK+ LUT must be loaded before the pipe is running but with
5265 * clocks enabled
5266 */
5267 intel_color_load_luts(&pipe_config->base);
5268
5269 if (dev_priv->display.initial_watermarks != NULL)
5270 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5271 intel_enable_pipe(intel_crtc);
5272
5273 if (intel_crtc->config->has_pch_encoder)
5274 ironlake_pch_enable(pipe_config);
5275
5276 assert_vblank_disabled(crtc);
5277 drm_crtc_vblank_on(crtc);
5278
5279 intel_encoders_enable(crtc, pipe_config, old_state);
5280
5281 if (HAS_PCH_CPT(dev_priv))
5282 cpt_verify_modeset(dev, intel_crtc->pipe);
5283
5284 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5285 if (intel_crtc->config->has_pch_encoder)
5286 intel_wait_for_vblank(dev_priv, pipe);
5287 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5288 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5289 }
5290
5291 /* IPS only exists on ULT machines and is tied to pipe A. */
5292 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5293 {
5294 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5295 }
5296
5297 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5298 struct drm_atomic_state *old_state)
5299 {
5300 struct drm_crtc *crtc = pipe_config->base.crtc;
5301 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5303 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5304 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5305 struct intel_atomic_state *old_intel_state =
5306 to_intel_atomic_state(old_state);
5307
5308 if (WARN_ON(intel_crtc->active))
5309 return;
5310
5311 if (intel_crtc->config->has_pch_encoder)
5312 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5313
5314 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5315
5316 if (intel_crtc->config->shared_dpll)
5317 intel_enable_shared_dpll(intel_crtc);
5318
5319 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5320 intel_dp_set_m_n(intel_crtc, M1_N1);
5321
5322 if (!transcoder_is_dsi(cpu_transcoder))
5323 intel_set_pipe_timings(intel_crtc);
5324
5325 intel_set_pipe_src_size(intel_crtc);
5326
5327 if (cpu_transcoder != TRANSCODER_EDP &&
5328 !transcoder_is_dsi(cpu_transcoder)) {
5329 I915_WRITE(PIPE_MULT(cpu_transcoder),
5330 intel_crtc->config->pixel_multiplier - 1);
5331 }
5332
5333 if (intel_crtc->config->has_pch_encoder) {
5334 intel_cpu_transcoder_set_m_n(intel_crtc,
5335 &intel_crtc->config->fdi_m_n, NULL);
5336 }
5337
5338 if (!transcoder_is_dsi(cpu_transcoder))
5339 haswell_set_pipeconf(crtc);
5340
5341 haswell_set_pipemisc(crtc);
5342
5343 intel_color_set_csc(&pipe_config->base);
5344
5345 intel_crtc->active = true;
5346
5347 if (intel_crtc->config->has_pch_encoder)
5348 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5349 else
5350 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5351
5352 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5353
5354 if (intel_crtc->config->has_pch_encoder)
5355 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5356
5357 if (!transcoder_is_dsi(cpu_transcoder))
5358 intel_ddi_enable_pipe_clock(pipe_config);
5359
5360 if (INTEL_GEN(dev_priv) >= 9)
5361 skylake_pfit_enable(intel_crtc);
5362 else
5363 ironlake_pfit_enable(intel_crtc);
5364
5365 /*
5366 * On ILK+ LUT must be loaded before the pipe is running but with
5367 * clocks enabled
5368 */
5369 intel_color_load_luts(&pipe_config->base);
5370
5371 intel_ddi_set_pipe_settings(pipe_config);
5372 if (!transcoder_is_dsi(cpu_transcoder))
5373 intel_ddi_enable_transcoder_func(pipe_config);
5374
5375 if (dev_priv->display.initial_watermarks != NULL)
5376 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5377
5378 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5379 if (!transcoder_is_dsi(cpu_transcoder))
5380 intel_enable_pipe(intel_crtc);
5381
5382 if (intel_crtc->config->has_pch_encoder)
5383 lpt_pch_enable(pipe_config);
5384
5385 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5386 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5387
5388 assert_vblank_disabled(crtc);
5389 drm_crtc_vblank_on(crtc);
5390
5391 intel_encoders_enable(crtc, pipe_config, old_state);
5392
5393 if (intel_crtc->config->has_pch_encoder) {
5394 intel_wait_for_vblank(dev_priv, pipe);
5395 intel_wait_for_vblank(dev_priv, pipe);
5396 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5397 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5398 }
5399
5400 /* If we change the relative order between pipe/planes enabling, we need
5401 * to change the workaround. */
5402 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5403 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5404 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5405 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5406 }
5407 }
5408
5409 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5410 {
5411 struct drm_device *dev = crtc->base.dev;
5412 struct drm_i915_private *dev_priv = to_i915(dev);
5413 int pipe = crtc->pipe;
5414
5415 /* To avoid upsetting the power well on haswell only disable the pfit if
5416 * it's in use. The hw state code will make sure we get this right. */
5417 if (force || crtc->config->pch_pfit.enabled) {
5418 I915_WRITE(PF_CTL(pipe), 0);
5419 I915_WRITE(PF_WIN_POS(pipe), 0);
5420 I915_WRITE(PF_WIN_SZ(pipe), 0);
5421 }
5422 }
5423
5424 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5425 struct drm_atomic_state *old_state)
5426 {
5427 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5428 struct drm_device *dev = crtc->dev;
5429 struct drm_i915_private *dev_priv = to_i915(dev);
5430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431 int pipe = intel_crtc->pipe;
5432
5433 /*
5434 * Sometimes spurious CPU pipe underruns happen when the
5435 * pipe is already disabled, but FDI RX/TX is still enabled.
5436 * Happens at least with VGA+HDMI cloning. Suppress them.
5437 */
5438 if (intel_crtc->config->has_pch_encoder) {
5439 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5440 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5441 }
5442
5443 intel_encoders_disable(crtc, old_crtc_state, old_state);
5444
5445 drm_crtc_vblank_off(crtc);
5446 assert_vblank_disabled(crtc);
5447
5448 intel_disable_pipe(intel_crtc);
5449
5450 ironlake_pfit_disable(intel_crtc, false);
5451
5452 if (intel_crtc->config->has_pch_encoder)
5453 ironlake_fdi_disable(crtc);
5454
5455 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5456
5457 if (intel_crtc->config->has_pch_encoder) {
5458 ironlake_disable_pch_transcoder(dev_priv, pipe);
5459
5460 if (HAS_PCH_CPT(dev_priv)) {
5461 i915_reg_t reg;
5462 u32 temp;
5463
5464 /* disable TRANS_DP_CTL */
5465 reg = TRANS_DP_CTL(pipe);
5466 temp = I915_READ(reg);
5467 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5468 TRANS_DP_PORT_SEL_MASK);
5469 temp |= TRANS_DP_PORT_SEL_NONE;
5470 I915_WRITE(reg, temp);
5471
5472 /* disable DPLL_SEL */
5473 temp = I915_READ(PCH_DPLL_SEL);
5474 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5475 I915_WRITE(PCH_DPLL_SEL, temp);
5476 }
5477
5478 ironlake_fdi_pll_disable(intel_crtc);
5479 }
5480
5481 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5482 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5483 }
5484
5485 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5486 struct drm_atomic_state *old_state)
5487 {
5488 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5489 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5491 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5492
5493 if (intel_crtc->config->has_pch_encoder)
5494 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5495
5496 intel_encoders_disable(crtc, old_crtc_state, old_state);
5497
5498 drm_crtc_vblank_off(crtc);
5499 assert_vblank_disabled(crtc);
5500
5501 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5502 if (!transcoder_is_dsi(cpu_transcoder))
5503 intel_disable_pipe(intel_crtc);
5504
5505 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5506 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5507
5508 if (!transcoder_is_dsi(cpu_transcoder))
5509 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5510
5511 if (INTEL_GEN(dev_priv) >= 9)
5512 skylake_scaler_disable(intel_crtc);
5513 else
5514 ironlake_pfit_disable(intel_crtc, false);
5515
5516 if (!transcoder_is_dsi(cpu_transcoder))
5517 intel_ddi_disable_pipe_clock(intel_crtc->config);
5518
5519 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5520
5521 if (old_crtc_state->has_pch_encoder)
5522 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5523 }
5524
5525 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5526 {
5527 struct drm_device *dev = crtc->base.dev;
5528 struct drm_i915_private *dev_priv = to_i915(dev);
5529 struct intel_crtc_state *pipe_config = crtc->config;
5530
5531 if (!pipe_config->gmch_pfit.control)
5532 return;
5533
5534 /*
5535 * The panel fitter should only be adjusted whilst the pipe is disabled,
5536 * according to register description and PRM.
5537 */
5538 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5539 assert_pipe_disabled(dev_priv, crtc->pipe);
5540
5541 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5542 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5543
5544 /* Border color in case we don't scale up to the full screen. Black by
5545 * default, change to something else for debugging. */
5546 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5547 }
5548
5549 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5550 {
5551 switch (port) {
5552 case PORT_A:
5553 return POWER_DOMAIN_PORT_DDI_A_LANES;
5554 case PORT_B:
5555 return POWER_DOMAIN_PORT_DDI_B_LANES;
5556 case PORT_C:
5557 return POWER_DOMAIN_PORT_DDI_C_LANES;
5558 case PORT_D:
5559 return POWER_DOMAIN_PORT_DDI_D_LANES;
5560 case PORT_E:
5561 return POWER_DOMAIN_PORT_DDI_E_LANES;
5562 default:
5563 MISSING_CASE(port);
5564 return POWER_DOMAIN_PORT_OTHER;
5565 }
5566 }
5567
5568 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5569 struct intel_crtc_state *crtc_state)
5570 {
5571 struct drm_device *dev = crtc->dev;
5572 struct drm_i915_private *dev_priv = to_i915(dev);
5573 struct drm_encoder *encoder;
5574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575 enum pipe pipe = intel_crtc->pipe;
5576 u64 mask;
5577 enum transcoder transcoder = crtc_state->cpu_transcoder;
5578
5579 if (!crtc_state->base.active)
5580 return 0;
5581
5582 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5583 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5584 if (crtc_state->pch_pfit.enabled ||
5585 crtc_state->pch_pfit.force_thru)
5586 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5587
5588 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5589 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5590
5591 mask |= BIT_ULL(intel_encoder->power_domain);
5592 }
5593
5594 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5595 mask |= BIT(POWER_DOMAIN_AUDIO);
5596
5597 if (crtc_state->shared_dpll)
5598 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5599
5600 return mask;
5601 }
5602
5603 static u64
5604 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5605 struct intel_crtc_state *crtc_state)
5606 {
5607 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5609 enum intel_display_power_domain domain;
5610 u64 domains, new_domains, old_domains;
5611
5612 old_domains = intel_crtc->enabled_power_domains;
5613 intel_crtc->enabled_power_domains = new_domains =
5614 get_crtc_power_domains(crtc, crtc_state);
5615
5616 domains = new_domains & ~old_domains;
5617
5618 for_each_power_domain(domain, domains)
5619 intel_display_power_get(dev_priv, domain);
5620
5621 return old_domains & ~new_domains;
5622 }
5623
5624 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5625 u64 domains)
5626 {
5627 enum intel_display_power_domain domain;
5628
5629 for_each_power_domain(domain, domains)
5630 intel_display_power_put(dev_priv, domain);
5631 }
5632
5633 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5634 struct drm_atomic_state *old_state)
5635 {
5636 struct intel_atomic_state *old_intel_state =
5637 to_intel_atomic_state(old_state);
5638 struct drm_crtc *crtc = pipe_config->base.crtc;
5639 struct drm_device *dev = crtc->dev;
5640 struct drm_i915_private *dev_priv = to_i915(dev);
5641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5642 int pipe = intel_crtc->pipe;
5643
5644 if (WARN_ON(intel_crtc->active))
5645 return;
5646
5647 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5648 intel_dp_set_m_n(intel_crtc, M1_N1);
5649
5650 intel_set_pipe_timings(intel_crtc);
5651 intel_set_pipe_src_size(intel_crtc);
5652
5653 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5654 struct drm_i915_private *dev_priv = to_i915(dev);
5655
5656 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5657 I915_WRITE(CHV_CANVAS(pipe), 0);
5658 }
5659
5660 i9xx_set_pipeconf(intel_crtc);
5661
5662 intel_crtc->active = true;
5663
5664 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5665
5666 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5667
5668 if (IS_CHERRYVIEW(dev_priv)) {
5669 chv_prepare_pll(intel_crtc, intel_crtc->config);
5670 chv_enable_pll(intel_crtc, intel_crtc->config);
5671 } else {
5672 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5673 vlv_enable_pll(intel_crtc, intel_crtc->config);
5674 }
5675
5676 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5677
5678 i9xx_pfit_enable(intel_crtc);
5679
5680 intel_color_load_luts(&pipe_config->base);
5681
5682 dev_priv->display.initial_watermarks(old_intel_state,
5683 pipe_config);
5684 intel_enable_pipe(intel_crtc);
5685
5686 assert_vblank_disabled(crtc);
5687 drm_crtc_vblank_on(crtc);
5688
5689 intel_encoders_enable(crtc, pipe_config, old_state);
5690 }
5691
5692 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5693 {
5694 struct drm_device *dev = crtc->base.dev;
5695 struct drm_i915_private *dev_priv = to_i915(dev);
5696
5697 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5698 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5699 }
5700
5701 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5702 struct drm_atomic_state *old_state)
5703 {
5704 struct intel_atomic_state *old_intel_state =
5705 to_intel_atomic_state(old_state);
5706 struct drm_crtc *crtc = pipe_config->base.crtc;
5707 struct drm_device *dev = crtc->dev;
5708 struct drm_i915_private *dev_priv = to_i915(dev);
5709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710 enum pipe pipe = intel_crtc->pipe;
5711
5712 if (WARN_ON(intel_crtc->active))
5713 return;
5714
5715 i9xx_set_pll_dividers(intel_crtc);
5716
5717 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5718 intel_dp_set_m_n(intel_crtc, M1_N1);
5719
5720 intel_set_pipe_timings(intel_crtc);
5721 intel_set_pipe_src_size(intel_crtc);
5722
5723 i9xx_set_pipeconf(intel_crtc);
5724
5725 intel_crtc->active = true;
5726
5727 if (!IS_GEN2(dev_priv))
5728 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5729
5730 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5731
5732 i9xx_enable_pll(intel_crtc);
5733
5734 i9xx_pfit_enable(intel_crtc);
5735
5736 intel_color_load_luts(&pipe_config->base);
5737
5738 if (dev_priv->display.initial_watermarks != NULL)
5739 dev_priv->display.initial_watermarks(old_intel_state,
5740 intel_crtc->config);
5741 else
5742 intel_update_watermarks(intel_crtc);
5743 intel_enable_pipe(intel_crtc);
5744
5745 assert_vblank_disabled(crtc);
5746 drm_crtc_vblank_on(crtc);
5747
5748 intel_encoders_enable(crtc, pipe_config, old_state);
5749 }
5750
5751 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5752 {
5753 struct drm_device *dev = crtc->base.dev;
5754 struct drm_i915_private *dev_priv = to_i915(dev);
5755
5756 if (!crtc->config->gmch_pfit.control)
5757 return;
5758
5759 assert_pipe_disabled(dev_priv, crtc->pipe);
5760
5761 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5762 I915_READ(PFIT_CONTROL));
5763 I915_WRITE(PFIT_CONTROL, 0);
5764 }
5765
5766 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5767 struct drm_atomic_state *old_state)
5768 {
5769 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5770 struct drm_device *dev = crtc->dev;
5771 struct drm_i915_private *dev_priv = to_i915(dev);
5772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5773 int pipe = intel_crtc->pipe;
5774
5775 /*
5776 * On gen2 planes are double buffered but the pipe isn't, so we must
5777 * wait for planes to fully turn off before disabling the pipe.
5778 */
5779 if (IS_GEN2(dev_priv))
5780 intel_wait_for_vblank(dev_priv, pipe);
5781
5782 intel_encoders_disable(crtc, old_crtc_state, old_state);
5783
5784 drm_crtc_vblank_off(crtc);
5785 assert_vblank_disabled(crtc);
5786
5787 intel_disable_pipe(intel_crtc);
5788
5789 i9xx_pfit_disable(intel_crtc);
5790
5791 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5792
5793 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5794 if (IS_CHERRYVIEW(dev_priv))
5795 chv_disable_pll(dev_priv, pipe);
5796 else if (IS_VALLEYVIEW(dev_priv))
5797 vlv_disable_pll(dev_priv, pipe);
5798 else
5799 i9xx_disable_pll(intel_crtc);
5800 }
5801
5802 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5803
5804 if (!IS_GEN2(dev_priv))
5805 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5806
5807 if (!dev_priv->display.initial_watermarks)
5808 intel_update_watermarks(intel_crtc);
5809
5810 /* clock the pipe down to 640x480@60 to potentially save power */
5811 if (IS_I830(dev_priv))
5812 i830_enable_pipe(dev_priv, pipe);
5813 }
5814
5815 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5816 struct drm_modeset_acquire_ctx *ctx)
5817 {
5818 struct intel_encoder *encoder;
5819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5820 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5821 enum intel_display_power_domain domain;
5822 u64 domains;
5823 struct drm_atomic_state *state;
5824 struct intel_crtc_state *crtc_state;
5825 int ret;
5826
5827 if (!intel_crtc->active)
5828 return;
5829
5830 if (crtc->primary->state->visible) {
5831 WARN_ON(intel_crtc->flip_work);
5832
5833 intel_pre_disable_primary_noatomic(crtc);
5834
5835 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5836 crtc->primary->state->visible = false;
5837 }
5838
5839 state = drm_atomic_state_alloc(crtc->dev);
5840 if (!state) {
5841 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5842 crtc->base.id, crtc->name);
5843 return;
5844 }
5845
5846 state->acquire_ctx = ctx;
5847
5848 /* Everything's already locked, -EDEADLK can't happen. */
5849 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5850 ret = drm_atomic_add_affected_connectors(state, crtc);
5851
5852 WARN_ON(IS_ERR(crtc_state) || ret);
5853
5854 dev_priv->display.crtc_disable(crtc_state, state);
5855
5856 drm_atomic_state_put(state);
5857
5858 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5859 crtc->base.id, crtc->name);
5860
5861 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5862 crtc->state->active = false;
5863 intel_crtc->active = false;
5864 crtc->enabled = false;
5865 crtc->state->connector_mask = 0;
5866 crtc->state->encoder_mask = 0;
5867
5868 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5869 encoder->base.crtc = NULL;
5870
5871 intel_fbc_disable(intel_crtc);
5872 intel_update_watermarks(intel_crtc);
5873 intel_disable_shared_dpll(intel_crtc);
5874
5875 domains = intel_crtc->enabled_power_domains;
5876 for_each_power_domain(domain, domains)
5877 intel_display_power_put(dev_priv, domain);
5878 intel_crtc->enabled_power_domains = 0;
5879
5880 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5881 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5882 }
5883
5884 /*
5885 * turn all crtc's off, but do not adjust state
5886 * This has to be paired with a call to intel_modeset_setup_hw_state.
5887 */
5888 int intel_display_suspend(struct drm_device *dev)
5889 {
5890 struct drm_i915_private *dev_priv = to_i915(dev);
5891 struct drm_atomic_state *state;
5892 int ret;
5893
5894 state = drm_atomic_helper_suspend(dev);
5895 ret = PTR_ERR_OR_ZERO(state);
5896 if (ret)
5897 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5898 else
5899 dev_priv->modeset_restore_state = state;
5900 return ret;
5901 }
5902
5903 void intel_encoder_destroy(struct drm_encoder *encoder)
5904 {
5905 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5906
5907 drm_encoder_cleanup(encoder);
5908 kfree(intel_encoder);
5909 }
5910
5911 /* Cross check the actual hw state with our own modeset state tracking (and it's
5912 * internal consistency). */
5913 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5914 struct drm_connector_state *conn_state)
5915 {
5916 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5917
5918 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5919 connector->base.base.id,
5920 connector->base.name);
5921
5922 if (connector->get_hw_state(connector)) {
5923 struct intel_encoder *encoder = connector->encoder;
5924
5925 I915_STATE_WARN(!crtc_state,
5926 "connector enabled without attached crtc\n");
5927
5928 if (!crtc_state)
5929 return;
5930
5931 I915_STATE_WARN(!crtc_state->active,
5932 "connector is active, but attached crtc isn't\n");
5933
5934 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5935 return;
5936
5937 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5938 "atomic encoder doesn't match attached encoder\n");
5939
5940 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5941 "attached encoder crtc differs from connector crtc\n");
5942 } else {
5943 I915_STATE_WARN(crtc_state && crtc_state->active,
5944 "attached crtc is active, but connector isn't\n");
5945 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5946 "best encoder set without crtc!\n");
5947 }
5948 }
5949
5950 int intel_connector_init(struct intel_connector *connector)
5951 {
5952 struct intel_digital_connector_state *conn_state;
5953
5954 /*
5955 * Allocate enough memory to hold intel_digital_connector_state,
5956 * This might be a few bytes too many, but for connectors that don't
5957 * need it we'll free the state and allocate a smaller one on the first
5958 * succesful commit anyway.
5959 */
5960 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
5961 if (!conn_state)
5962 return -ENOMEM;
5963
5964 __drm_atomic_helper_connector_reset(&connector->base,
5965 &conn_state->base);
5966
5967 return 0;
5968 }
5969
5970 struct intel_connector *intel_connector_alloc(void)
5971 {
5972 struct intel_connector *connector;
5973
5974 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5975 if (!connector)
5976 return NULL;
5977
5978 if (intel_connector_init(connector) < 0) {
5979 kfree(connector);
5980 return NULL;
5981 }
5982
5983 return connector;
5984 }
5985
5986 /* Simple connector->get_hw_state implementation for encoders that support only
5987 * one connector and no cloning and hence the encoder state determines the state
5988 * of the connector. */
5989 bool intel_connector_get_hw_state(struct intel_connector *connector)
5990 {
5991 enum pipe pipe = 0;
5992 struct intel_encoder *encoder = connector->encoder;
5993
5994 return encoder->get_hw_state(encoder, &pipe);
5995 }
5996
5997 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5998 {
5999 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6000 return crtc_state->fdi_lanes;
6001
6002 return 0;
6003 }
6004
6005 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6006 struct intel_crtc_state *pipe_config)
6007 {
6008 struct drm_i915_private *dev_priv = to_i915(dev);
6009 struct drm_atomic_state *state = pipe_config->base.state;
6010 struct intel_crtc *other_crtc;
6011 struct intel_crtc_state *other_crtc_state;
6012
6013 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6014 pipe_name(pipe), pipe_config->fdi_lanes);
6015 if (pipe_config->fdi_lanes > 4) {
6016 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6017 pipe_name(pipe), pipe_config->fdi_lanes);
6018 return -EINVAL;
6019 }
6020
6021 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6022 if (pipe_config->fdi_lanes > 2) {
6023 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6024 pipe_config->fdi_lanes);
6025 return -EINVAL;
6026 } else {
6027 return 0;
6028 }
6029 }
6030
6031 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6032 return 0;
6033
6034 /* Ivybridge 3 pipe is really complicated */
6035 switch (pipe) {
6036 case PIPE_A:
6037 return 0;
6038 case PIPE_B:
6039 if (pipe_config->fdi_lanes <= 2)
6040 return 0;
6041
6042 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6043 other_crtc_state =
6044 intel_atomic_get_crtc_state(state, other_crtc);
6045 if (IS_ERR(other_crtc_state))
6046 return PTR_ERR(other_crtc_state);
6047
6048 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6049 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6050 pipe_name(pipe), pipe_config->fdi_lanes);
6051 return -EINVAL;
6052 }
6053 return 0;
6054 case PIPE_C:
6055 if (pipe_config->fdi_lanes > 2) {
6056 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6057 pipe_name(pipe), pipe_config->fdi_lanes);
6058 return -EINVAL;
6059 }
6060
6061 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6062 other_crtc_state =
6063 intel_atomic_get_crtc_state(state, other_crtc);
6064 if (IS_ERR(other_crtc_state))
6065 return PTR_ERR(other_crtc_state);
6066
6067 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6068 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6069 return -EINVAL;
6070 }
6071 return 0;
6072 default:
6073 BUG();
6074 }
6075 }
6076
6077 #define RETRY 1
6078 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6079 struct intel_crtc_state *pipe_config)
6080 {
6081 struct drm_device *dev = intel_crtc->base.dev;
6082 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6083 int lane, link_bw, fdi_dotclock, ret;
6084 bool needs_recompute = false;
6085
6086 retry:
6087 /* FDI is a binary signal running at ~2.7GHz, encoding
6088 * each output octet as 10 bits. The actual frequency
6089 * is stored as a divider into a 100MHz clock, and the
6090 * mode pixel clock is stored in units of 1KHz.
6091 * Hence the bw of each lane in terms of the mode signal
6092 * is:
6093 */
6094 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6095
6096 fdi_dotclock = adjusted_mode->crtc_clock;
6097
6098 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6099 pipe_config->pipe_bpp);
6100
6101 pipe_config->fdi_lanes = lane;
6102
6103 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6104 link_bw, &pipe_config->fdi_m_n, false);
6105
6106 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6107 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6108 pipe_config->pipe_bpp -= 2*3;
6109 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6110 pipe_config->pipe_bpp);
6111 needs_recompute = true;
6112 pipe_config->bw_constrained = true;
6113
6114 goto retry;
6115 }
6116
6117 if (needs_recompute)
6118 return RETRY;
6119
6120 return ret;
6121 }
6122
6123 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6124 struct intel_crtc_state *pipe_config)
6125 {
6126 if (pipe_config->pipe_bpp > 24)
6127 return false;
6128
6129 /* HSW can handle pixel rate up to cdclk? */
6130 if (IS_HASWELL(dev_priv))
6131 return true;
6132
6133 /*
6134 * We compare against max which means we must take
6135 * the increased cdclk requirement into account when
6136 * calculating the new cdclk.
6137 *
6138 * Should measure whether using a lower cdclk w/o IPS
6139 */
6140 return pipe_config->pixel_rate <=
6141 dev_priv->max_cdclk_freq * 95 / 100;
6142 }
6143
6144 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6145 struct intel_crtc_state *pipe_config)
6146 {
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = to_i915(dev);
6149
6150 pipe_config->ips_enabled = i915.enable_ips &&
6151 hsw_crtc_supports_ips(crtc) &&
6152 pipe_config_supports_ips(dev_priv, pipe_config);
6153 }
6154
6155 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6156 {
6157 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6158
6159 /* GDG double wide on either pipe, otherwise pipe A only */
6160 return INTEL_INFO(dev_priv)->gen < 4 &&
6161 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6162 }
6163
6164 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6165 {
6166 uint32_t pixel_rate;
6167
6168 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6169
6170 /*
6171 * We only use IF-ID interlacing. If we ever use
6172 * PF-ID we'll need to adjust the pixel_rate here.
6173 */
6174
6175 if (pipe_config->pch_pfit.enabled) {
6176 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6177 uint32_t pfit_size = pipe_config->pch_pfit.size;
6178
6179 pipe_w = pipe_config->pipe_src_w;
6180 pipe_h = pipe_config->pipe_src_h;
6181
6182 pfit_w = (pfit_size >> 16) & 0xFFFF;
6183 pfit_h = pfit_size & 0xFFFF;
6184 if (pipe_w < pfit_w)
6185 pipe_w = pfit_w;
6186 if (pipe_h < pfit_h)
6187 pipe_h = pfit_h;
6188
6189 if (WARN_ON(!pfit_w || !pfit_h))
6190 return pixel_rate;
6191
6192 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6193 pfit_w * pfit_h);
6194 }
6195
6196 return pixel_rate;
6197 }
6198
6199 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6200 {
6201 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6202
6203 if (HAS_GMCH_DISPLAY(dev_priv))
6204 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6205 crtc_state->pixel_rate =
6206 crtc_state->base.adjusted_mode.crtc_clock;
6207 else
6208 crtc_state->pixel_rate =
6209 ilk_pipe_pixel_rate(crtc_state);
6210 }
6211
6212 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6213 struct intel_crtc_state *pipe_config)
6214 {
6215 struct drm_device *dev = crtc->base.dev;
6216 struct drm_i915_private *dev_priv = to_i915(dev);
6217 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6218 int clock_limit = dev_priv->max_dotclk_freq;
6219
6220 if (INTEL_GEN(dev_priv) < 4) {
6221 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6222
6223 /*
6224 * Enable double wide mode when the dot clock
6225 * is > 90% of the (display) core speed.
6226 */
6227 if (intel_crtc_supports_double_wide(crtc) &&
6228 adjusted_mode->crtc_clock > clock_limit) {
6229 clock_limit = dev_priv->max_dotclk_freq;
6230 pipe_config->double_wide = true;
6231 }
6232 }
6233
6234 if (adjusted_mode->crtc_clock > clock_limit) {
6235 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6236 adjusted_mode->crtc_clock, clock_limit,
6237 yesno(pipe_config->double_wide));
6238 return -EINVAL;
6239 }
6240
6241 /*
6242 * Pipe horizontal size must be even in:
6243 * - DVO ganged mode
6244 * - LVDS dual channel mode
6245 * - Double wide pipe
6246 */
6247 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6248 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6249 pipe_config->pipe_src_w &= ~1;
6250
6251 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6252 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6253 */
6254 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6255 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6256 return -EINVAL;
6257
6258 intel_crtc_compute_pixel_rate(pipe_config);
6259
6260 if (HAS_IPS(dev_priv))
6261 hsw_compute_ips_config(crtc, pipe_config);
6262
6263 if (pipe_config->has_pch_encoder)
6264 return ironlake_fdi_compute_config(crtc, pipe_config);
6265
6266 return 0;
6267 }
6268
6269 static void
6270 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6271 {
6272 while (*num > DATA_LINK_M_N_MASK ||
6273 *den > DATA_LINK_M_N_MASK) {
6274 *num >>= 1;
6275 *den >>= 1;
6276 }
6277 }
6278
6279 static void compute_m_n(unsigned int m, unsigned int n,
6280 uint32_t *ret_m, uint32_t *ret_n,
6281 bool reduce_m_n)
6282 {
6283 /*
6284 * Reduce M/N as much as possible without loss in precision. Several DP
6285 * dongles in particular seem to be fussy about too large *link* M/N
6286 * values. The passed in values are more likely to have the least
6287 * significant bits zero than M after rounding below, so do this first.
6288 */
6289 if (reduce_m_n) {
6290 while ((m & 1) == 0 && (n & 1) == 0) {
6291 m >>= 1;
6292 n >>= 1;
6293 }
6294 }
6295
6296 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6297 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6298 intel_reduce_m_n_ratio(ret_m, ret_n);
6299 }
6300
6301 void
6302 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6303 int pixel_clock, int link_clock,
6304 struct intel_link_m_n *m_n,
6305 bool reduce_m_n)
6306 {
6307 m_n->tu = 64;
6308
6309 compute_m_n(bits_per_pixel * pixel_clock,
6310 link_clock * nlanes * 8,
6311 &m_n->gmch_m, &m_n->gmch_n,
6312 reduce_m_n);
6313
6314 compute_m_n(pixel_clock, link_clock,
6315 &m_n->link_m, &m_n->link_n,
6316 reduce_m_n);
6317 }
6318
6319 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6320 {
6321 if (i915.panel_use_ssc >= 0)
6322 return i915.panel_use_ssc != 0;
6323 return dev_priv->vbt.lvds_use_ssc
6324 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6325 }
6326
6327 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6328 {
6329 return (1 << dpll->n) << 16 | dpll->m2;
6330 }
6331
6332 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6333 {
6334 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6335 }
6336
6337 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6338 struct intel_crtc_state *crtc_state,
6339 struct dpll *reduced_clock)
6340 {
6341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6342 u32 fp, fp2 = 0;
6343
6344 if (IS_PINEVIEW(dev_priv)) {
6345 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6346 if (reduced_clock)
6347 fp2 = pnv_dpll_compute_fp(reduced_clock);
6348 } else {
6349 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6350 if (reduced_clock)
6351 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6352 }
6353
6354 crtc_state->dpll_hw_state.fp0 = fp;
6355
6356 crtc->lowfreq_avail = false;
6357 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6358 reduced_clock) {
6359 crtc_state->dpll_hw_state.fp1 = fp2;
6360 crtc->lowfreq_avail = true;
6361 } else {
6362 crtc_state->dpll_hw_state.fp1 = fp;
6363 }
6364 }
6365
6366 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6367 pipe)
6368 {
6369 u32 reg_val;
6370
6371 /*
6372 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6373 * and set it to a reasonable value instead.
6374 */
6375 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6376 reg_val &= 0xffffff00;
6377 reg_val |= 0x00000030;
6378 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6379
6380 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6381 reg_val &= 0x00ffffff;
6382 reg_val |= 0x8c000000;
6383 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6384
6385 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6386 reg_val &= 0xffffff00;
6387 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6388
6389 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6390 reg_val &= 0x00ffffff;
6391 reg_val |= 0xb0000000;
6392 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6393 }
6394
6395 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6396 struct intel_link_m_n *m_n)
6397 {
6398 struct drm_device *dev = crtc->base.dev;
6399 struct drm_i915_private *dev_priv = to_i915(dev);
6400 int pipe = crtc->pipe;
6401
6402 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6403 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6404 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6405 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6406 }
6407
6408 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6409 struct intel_link_m_n *m_n,
6410 struct intel_link_m_n *m2_n2)
6411 {
6412 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6413 int pipe = crtc->pipe;
6414 enum transcoder transcoder = crtc->config->cpu_transcoder;
6415
6416 if (INTEL_GEN(dev_priv) >= 5) {
6417 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6418 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6419 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6420 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6421 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6422 * for gen < 8) and if DRRS is supported (to make sure the
6423 * registers are not unnecessarily accessed).
6424 */
6425 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6426 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6427 I915_WRITE(PIPE_DATA_M2(transcoder),
6428 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6429 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6430 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6431 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6432 }
6433 } else {
6434 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6435 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6436 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6437 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6438 }
6439 }
6440
6441 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6442 {
6443 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6444
6445 if (m_n == M1_N1) {
6446 dp_m_n = &crtc->config->dp_m_n;
6447 dp_m2_n2 = &crtc->config->dp_m2_n2;
6448 } else if (m_n == M2_N2) {
6449
6450 /*
6451 * M2_N2 registers are not supported. Hence m2_n2 divider value
6452 * needs to be programmed into M1_N1.
6453 */
6454 dp_m_n = &crtc->config->dp_m2_n2;
6455 } else {
6456 DRM_ERROR("Unsupported divider value\n");
6457 return;
6458 }
6459
6460 if (crtc->config->has_pch_encoder)
6461 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6462 else
6463 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6464 }
6465
6466 static void vlv_compute_dpll(struct intel_crtc *crtc,
6467 struct intel_crtc_state *pipe_config)
6468 {
6469 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6470 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6471 if (crtc->pipe != PIPE_A)
6472 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6473
6474 /* DPLL not used with DSI, but still need the rest set up */
6475 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6476 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6477 DPLL_EXT_BUFFER_ENABLE_VLV;
6478
6479 pipe_config->dpll_hw_state.dpll_md =
6480 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6481 }
6482
6483 static void chv_compute_dpll(struct intel_crtc *crtc,
6484 struct intel_crtc_state *pipe_config)
6485 {
6486 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6487 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6488 if (crtc->pipe != PIPE_A)
6489 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6490
6491 /* DPLL not used with DSI, but still need the rest set up */
6492 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6493 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6494
6495 pipe_config->dpll_hw_state.dpll_md =
6496 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6497 }
6498
6499 static void vlv_prepare_pll(struct intel_crtc *crtc,
6500 const struct intel_crtc_state *pipe_config)
6501 {
6502 struct drm_device *dev = crtc->base.dev;
6503 struct drm_i915_private *dev_priv = to_i915(dev);
6504 enum pipe pipe = crtc->pipe;
6505 u32 mdiv;
6506 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6507 u32 coreclk, reg_val;
6508
6509 /* Enable Refclk */
6510 I915_WRITE(DPLL(pipe),
6511 pipe_config->dpll_hw_state.dpll &
6512 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6513
6514 /* No need to actually set up the DPLL with DSI */
6515 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6516 return;
6517
6518 mutex_lock(&dev_priv->sb_lock);
6519
6520 bestn = pipe_config->dpll.n;
6521 bestm1 = pipe_config->dpll.m1;
6522 bestm2 = pipe_config->dpll.m2;
6523 bestp1 = pipe_config->dpll.p1;
6524 bestp2 = pipe_config->dpll.p2;
6525
6526 /* See eDP HDMI DPIO driver vbios notes doc */
6527
6528 /* PLL B needs special handling */
6529 if (pipe == PIPE_B)
6530 vlv_pllb_recal_opamp(dev_priv, pipe);
6531
6532 /* Set up Tx target for periodic Rcomp update */
6533 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6534
6535 /* Disable target IRef on PLL */
6536 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6537 reg_val &= 0x00ffffff;
6538 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6539
6540 /* Disable fast lock */
6541 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6542
6543 /* Set idtafcrecal before PLL is enabled */
6544 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6545 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6546 mdiv |= ((bestn << DPIO_N_SHIFT));
6547 mdiv |= (1 << DPIO_K_SHIFT);
6548
6549 /*
6550 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6551 * but we don't support that).
6552 * Note: don't use the DAC post divider as it seems unstable.
6553 */
6554 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6555 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6556
6557 mdiv |= DPIO_ENABLE_CALIBRATION;
6558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6559
6560 /* Set HBR and RBR LPF coefficients */
6561 if (pipe_config->port_clock == 162000 ||
6562 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6563 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6564 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6565 0x009f0003);
6566 else
6567 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6568 0x00d0000f);
6569
6570 if (intel_crtc_has_dp_encoder(pipe_config)) {
6571 /* Use SSC source */
6572 if (pipe == PIPE_A)
6573 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6574 0x0df40000);
6575 else
6576 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6577 0x0df70000);
6578 } else { /* HDMI or VGA */
6579 /* Use bend source */
6580 if (pipe == PIPE_A)
6581 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6582 0x0df70000);
6583 else
6584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6585 0x0df40000);
6586 }
6587
6588 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6589 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6590 if (intel_crtc_has_dp_encoder(crtc->config))
6591 coreclk |= 0x01000000;
6592 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6593
6594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6595 mutex_unlock(&dev_priv->sb_lock);
6596 }
6597
6598 static void chv_prepare_pll(struct intel_crtc *crtc,
6599 const struct intel_crtc_state *pipe_config)
6600 {
6601 struct drm_device *dev = crtc->base.dev;
6602 struct drm_i915_private *dev_priv = to_i915(dev);
6603 enum pipe pipe = crtc->pipe;
6604 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6605 u32 loopfilter, tribuf_calcntr;
6606 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6607 u32 dpio_val;
6608 int vco;
6609
6610 /* Enable Refclk and SSC */
6611 I915_WRITE(DPLL(pipe),
6612 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6613
6614 /* No need to actually set up the DPLL with DSI */
6615 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6616 return;
6617
6618 bestn = pipe_config->dpll.n;
6619 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6620 bestm1 = pipe_config->dpll.m1;
6621 bestm2 = pipe_config->dpll.m2 >> 22;
6622 bestp1 = pipe_config->dpll.p1;
6623 bestp2 = pipe_config->dpll.p2;
6624 vco = pipe_config->dpll.vco;
6625 dpio_val = 0;
6626 loopfilter = 0;
6627
6628 mutex_lock(&dev_priv->sb_lock);
6629
6630 /* p1 and p2 divider */
6631 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6632 5 << DPIO_CHV_S1_DIV_SHIFT |
6633 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6634 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6635 1 << DPIO_CHV_K_DIV_SHIFT);
6636
6637 /* Feedback post-divider - m2 */
6638 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6639
6640 /* Feedback refclk divider - n and m1 */
6641 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6642 DPIO_CHV_M1_DIV_BY_2 |
6643 1 << DPIO_CHV_N_DIV_SHIFT);
6644
6645 /* M2 fraction division */
6646 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6647
6648 /* M2 fraction division enable */
6649 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6650 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6651 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6652 if (bestm2_frac)
6653 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6654 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6655
6656 /* Program digital lock detect threshold */
6657 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6658 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6659 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6660 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6661 if (!bestm2_frac)
6662 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6663 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6664
6665 /* Loop filter */
6666 if (vco == 5400000) {
6667 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6668 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6669 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6670 tribuf_calcntr = 0x9;
6671 } else if (vco <= 6200000) {
6672 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6673 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6674 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6675 tribuf_calcntr = 0x9;
6676 } else if (vco <= 6480000) {
6677 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6678 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6679 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6680 tribuf_calcntr = 0x8;
6681 } else {
6682 /* Not supported. Apply the same limits as in the max case */
6683 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6684 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6685 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6686 tribuf_calcntr = 0;
6687 }
6688 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6689
6690 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6691 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6692 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6693 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6694
6695 /* AFC Recal */
6696 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6697 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6698 DPIO_AFC_RECAL);
6699
6700 mutex_unlock(&dev_priv->sb_lock);
6701 }
6702
6703 /**
6704 * vlv_force_pll_on - forcibly enable just the PLL
6705 * @dev_priv: i915 private structure
6706 * @pipe: pipe PLL to enable
6707 * @dpll: PLL configuration
6708 *
6709 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6710 * in cases where we need the PLL enabled even when @pipe is not going to
6711 * be enabled.
6712 */
6713 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6714 const struct dpll *dpll)
6715 {
6716 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6717 struct intel_crtc_state *pipe_config;
6718
6719 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6720 if (!pipe_config)
6721 return -ENOMEM;
6722
6723 pipe_config->base.crtc = &crtc->base;
6724 pipe_config->pixel_multiplier = 1;
6725 pipe_config->dpll = *dpll;
6726
6727 if (IS_CHERRYVIEW(dev_priv)) {
6728 chv_compute_dpll(crtc, pipe_config);
6729 chv_prepare_pll(crtc, pipe_config);
6730 chv_enable_pll(crtc, pipe_config);
6731 } else {
6732 vlv_compute_dpll(crtc, pipe_config);
6733 vlv_prepare_pll(crtc, pipe_config);
6734 vlv_enable_pll(crtc, pipe_config);
6735 }
6736
6737 kfree(pipe_config);
6738
6739 return 0;
6740 }
6741
6742 /**
6743 * vlv_force_pll_off - forcibly disable just the PLL
6744 * @dev_priv: i915 private structure
6745 * @pipe: pipe PLL to disable
6746 *
6747 * Disable the PLL for @pipe. To be used in cases where we need
6748 * the PLL enabled even when @pipe is not going to be enabled.
6749 */
6750 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6751 {
6752 if (IS_CHERRYVIEW(dev_priv))
6753 chv_disable_pll(dev_priv, pipe);
6754 else
6755 vlv_disable_pll(dev_priv, pipe);
6756 }
6757
6758 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6759 struct intel_crtc_state *crtc_state,
6760 struct dpll *reduced_clock)
6761 {
6762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6763 u32 dpll;
6764 struct dpll *clock = &crtc_state->dpll;
6765
6766 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6767
6768 dpll = DPLL_VGA_MODE_DIS;
6769
6770 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6771 dpll |= DPLLB_MODE_LVDS;
6772 else
6773 dpll |= DPLLB_MODE_DAC_SERIAL;
6774
6775 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6776 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6777 dpll |= (crtc_state->pixel_multiplier - 1)
6778 << SDVO_MULTIPLIER_SHIFT_HIRES;
6779 }
6780
6781 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6782 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6783 dpll |= DPLL_SDVO_HIGH_SPEED;
6784
6785 if (intel_crtc_has_dp_encoder(crtc_state))
6786 dpll |= DPLL_SDVO_HIGH_SPEED;
6787
6788 /* compute bitmask from p1 value */
6789 if (IS_PINEVIEW(dev_priv))
6790 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6791 else {
6792 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6793 if (IS_G4X(dev_priv) && reduced_clock)
6794 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6795 }
6796 switch (clock->p2) {
6797 case 5:
6798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6799 break;
6800 case 7:
6801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6802 break;
6803 case 10:
6804 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6805 break;
6806 case 14:
6807 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6808 break;
6809 }
6810 if (INTEL_GEN(dev_priv) >= 4)
6811 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6812
6813 if (crtc_state->sdvo_tv_clock)
6814 dpll |= PLL_REF_INPUT_TVCLKINBC;
6815 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6816 intel_panel_use_ssc(dev_priv))
6817 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6818 else
6819 dpll |= PLL_REF_INPUT_DREFCLK;
6820
6821 dpll |= DPLL_VCO_ENABLE;
6822 crtc_state->dpll_hw_state.dpll = dpll;
6823
6824 if (INTEL_GEN(dev_priv) >= 4) {
6825 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6826 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6827 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6828 }
6829 }
6830
6831 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6832 struct intel_crtc_state *crtc_state,
6833 struct dpll *reduced_clock)
6834 {
6835 struct drm_device *dev = crtc->base.dev;
6836 struct drm_i915_private *dev_priv = to_i915(dev);
6837 u32 dpll;
6838 struct dpll *clock = &crtc_state->dpll;
6839
6840 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6841
6842 dpll = DPLL_VGA_MODE_DIS;
6843
6844 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6845 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6846 } else {
6847 if (clock->p1 == 2)
6848 dpll |= PLL_P1_DIVIDE_BY_TWO;
6849 else
6850 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6851 if (clock->p2 == 4)
6852 dpll |= PLL_P2_DIVIDE_BY_4;
6853 }
6854
6855 if (!IS_I830(dev_priv) &&
6856 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6857 dpll |= DPLL_DVO_2X_MODE;
6858
6859 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6860 intel_panel_use_ssc(dev_priv))
6861 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6862 else
6863 dpll |= PLL_REF_INPUT_DREFCLK;
6864
6865 dpll |= DPLL_VCO_ENABLE;
6866 crtc_state->dpll_hw_state.dpll = dpll;
6867 }
6868
6869 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6870 {
6871 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6872 enum pipe pipe = intel_crtc->pipe;
6873 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6874 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6875 uint32_t crtc_vtotal, crtc_vblank_end;
6876 int vsyncshift = 0;
6877
6878 /* We need to be careful not to changed the adjusted mode, for otherwise
6879 * the hw state checker will get angry at the mismatch. */
6880 crtc_vtotal = adjusted_mode->crtc_vtotal;
6881 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6882
6883 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6884 /* the chip adds 2 halflines automatically */
6885 crtc_vtotal -= 1;
6886 crtc_vblank_end -= 1;
6887
6888 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6889 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6890 else
6891 vsyncshift = adjusted_mode->crtc_hsync_start -
6892 adjusted_mode->crtc_htotal / 2;
6893 if (vsyncshift < 0)
6894 vsyncshift += adjusted_mode->crtc_htotal;
6895 }
6896
6897 if (INTEL_GEN(dev_priv) > 3)
6898 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6899
6900 I915_WRITE(HTOTAL(cpu_transcoder),
6901 (adjusted_mode->crtc_hdisplay - 1) |
6902 ((adjusted_mode->crtc_htotal - 1) << 16));
6903 I915_WRITE(HBLANK(cpu_transcoder),
6904 (adjusted_mode->crtc_hblank_start - 1) |
6905 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6906 I915_WRITE(HSYNC(cpu_transcoder),
6907 (adjusted_mode->crtc_hsync_start - 1) |
6908 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6909
6910 I915_WRITE(VTOTAL(cpu_transcoder),
6911 (adjusted_mode->crtc_vdisplay - 1) |
6912 ((crtc_vtotal - 1) << 16));
6913 I915_WRITE(VBLANK(cpu_transcoder),
6914 (adjusted_mode->crtc_vblank_start - 1) |
6915 ((crtc_vblank_end - 1) << 16));
6916 I915_WRITE(VSYNC(cpu_transcoder),
6917 (adjusted_mode->crtc_vsync_start - 1) |
6918 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6919
6920 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6921 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6922 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6923 * bits. */
6924 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6925 (pipe == PIPE_B || pipe == PIPE_C))
6926 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6927
6928 }
6929
6930 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6931 {
6932 struct drm_device *dev = intel_crtc->base.dev;
6933 struct drm_i915_private *dev_priv = to_i915(dev);
6934 enum pipe pipe = intel_crtc->pipe;
6935
6936 /* pipesrc controls the size that is scaled from, which should
6937 * always be the user's requested size.
6938 */
6939 I915_WRITE(PIPESRC(pipe),
6940 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6941 (intel_crtc->config->pipe_src_h - 1));
6942 }
6943
6944 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6945 struct intel_crtc_state *pipe_config)
6946 {
6947 struct drm_device *dev = crtc->base.dev;
6948 struct drm_i915_private *dev_priv = to_i915(dev);
6949 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6950 uint32_t tmp;
6951
6952 tmp = I915_READ(HTOTAL(cpu_transcoder));
6953 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6954 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6955 tmp = I915_READ(HBLANK(cpu_transcoder));
6956 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6957 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6958 tmp = I915_READ(HSYNC(cpu_transcoder));
6959 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6960 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6961
6962 tmp = I915_READ(VTOTAL(cpu_transcoder));
6963 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6964 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6965 tmp = I915_READ(VBLANK(cpu_transcoder));
6966 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6967 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6968 tmp = I915_READ(VSYNC(cpu_transcoder));
6969 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6970 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6971
6972 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6973 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6974 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6975 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6976 }
6977 }
6978
6979 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6980 struct intel_crtc_state *pipe_config)
6981 {
6982 struct drm_device *dev = crtc->base.dev;
6983 struct drm_i915_private *dev_priv = to_i915(dev);
6984 u32 tmp;
6985
6986 tmp = I915_READ(PIPESRC(crtc->pipe));
6987 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6988 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6989
6990 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6991 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6992 }
6993
6994 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6995 struct intel_crtc_state *pipe_config)
6996 {
6997 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6998 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6999 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7000 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7001
7002 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7003 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7004 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7005 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7006
7007 mode->flags = pipe_config->base.adjusted_mode.flags;
7008 mode->type = DRM_MODE_TYPE_DRIVER;
7009
7010 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7011
7012 mode->hsync = drm_mode_hsync(mode);
7013 mode->vrefresh = drm_mode_vrefresh(mode);
7014 drm_mode_set_name(mode);
7015 }
7016
7017 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7018 {
7019 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7020 uint32_t pipeconf;
7021
7022 pipeconf = 0;
7023
7024 /* we keep both pipes enabled on 830 */
7025 if (IS_I830(dev_priv))
7026 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7027
7028 if (intel_crtc->config->double_wide)
7029 pipeconf |= PIPECONF_DOUBLE_WIDE;
7030
7031 /* only g4x and later have fancy bpc/dither controls */
7032 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7033 IS_CHERRYVIEW(dev_priv)) {
7034 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7035 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7036 pipeconf |= PIPECONF_DITHER_EN |
7037 PIPECONF_DITHER_TYPE_SP;
7038
7039 switch (intel_crtc->config->pipe_bpp) {
7040 case 18:
7041 pipeconf |= PIPECONF_6BPC;
7042 break;
7043 case 24:
7044 pipeconf |= PIPECONF_8BPC;
7045 break;
7046 case 30:
7047 pipeconf |= PIPECONF_10BPC;
7048 break;
7049 default:
7050 /* Case prevented by intel_choose_pipe_bpp_dither. */
7051 BUG();
7052 }
7053 }
7054
7055 if (HAS_PIPE_CXSR(dev_priv)) {
7056 if (intel_crtc->lowfreq_avail) {
7057 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7058 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7059 } else {
7060 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7061 }
7062 }
7063
7064 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7065 if (INTEL_GEN(dev_priv) < 4 ||
7066 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7067 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7068 else
7069 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7070 } else
7071 pipeconf |= PIPECONF_PROGRESSIVE;
7072
7073 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7074 intel_crtc->config->limited_color_range)
7075 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7076
7077 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7078 POSTING_READ(PIPECONF(intel_crtc->pipe));
7079 }
7080
7081 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7082 struct intel_crtc_state *crtc_state)
7083 {
7084 struct drm_device *dev = crtc->base.dev;
7085 struct drm_i915_private *dev_priv = to_i915(dev);
7086 const struct intel_limit *limit;
7087 int refclk = 48000;
7088
7089 memset(&crtc_state->dpll_hw_state, 0,
7090 sizeof(crtc_state->dpll_hw_state));
7091
7092 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7093 if (intel_panel_use_ssc(dev_priv)) {
7094 refclk = dev_priv->vbt.lvds_ssc_freq;
7095 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7096 }
7097
7098 limit = &intel_limits_i8xx_lvds;
7099 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7100 limit = &intel_limits_i8xx_dvo;
7101 } else {
7102 limit = &intel_limits_i8xx_dac;
7103 }
7104
7105 if (!crtc_state->clock_set &&
7106 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7107 refclk, NULL, &crtc_state->dpll)) {
7108 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7109 return -EINVAL;
7110 }
7111
7112 i8xx_compute_dpll(crtc, crtc_state, NULL);
7113
7114 return 0;
7115 }
7116
7117 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7118 struct intel_crtc_state *crtc_state)
7119 {
7120 struct drm_device *dev = crtc->base.dev;
7121 struct drm_i915_private *dev_priv = to_i915(dev);
7122 const struct intel_limit *limit;
7123 int refclk = 96000;
7124
7125 memset(&crtc_state->dpll_hw_state, 0,
7126 sizeof(crtc_state->dpll_hw_state));
7127
7128 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7129 if (intel_panel_use_ssc(dev_priv)) {
7130 refclk = dev_priv->vbt.lvds_ssc_freq;
7131 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7132 }
7133
7134 if (intel_is_dual_link_lvds(dev))
7135 limit = &intel_limits_g4x_dual_channel_lvds;
7136 else
7137 limit = &intel_limits_g4x_single_channel_lvds;
7138 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7139 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7140 limit = &intel_limits_g4x_hdmi;
7141 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7142 limit = &intel_limits_g4x_sdvo;
7143 } else {
7144 /* The option is for other outputs */
7145 limit = &intel_limits_i9xx_sdvo;
7146 }
7147
7148 if (!crtc_state->clock_set &&
7149 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7150 refclk, NULL, &crtc_state->dpll)) {
7151 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7152 return -EINVAL;
7153 }
7154
7155 i9xx_compute_dpll(crtc, crtc_state, NULL);
7156
7157 return 0;
7158 }
7159
7160 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7161 struct intel_crtc_state *crtc_state)
7162 {
7163 struct drm_device *dev = crtc->base.dev;
7164 struct drm_i915_private *dev_priv = to_i915(dev);
7165 const struct intel_limit *limit;
7166 int refclk = 96000;
7167
7168 memset(&crtc_state->dpll_hw_state, 0,
7169 sizeof(crtc_state->dpll_hw_state));
7170
7171 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7172 if (intel_panel_use_ssc(dev_priv)) {
7173 refclk = dev_priv->vbt.lvds_ssc_freq;
7174 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7175 }
7176
7177 limit = &intel_limits_pineview_lvds;
7178 } else {
7179 limit = &intel_limits_pineview_sdvo;
7180 }
7181
7182 if (!crtc_state->clock_set &&
7183 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7184 refclk, NULL, &crtc_state->dpll)) {
7185 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7186 return -EINVAL;
7187 }
7188
7189 i9xx_compute_dpll(crtc, crtc_state, NULL);
7190
7191 return 0;
7192 }
7193
7194 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7195 struct intel_crtc_state *crtc_state)
7196 {
7197 struct drm_device *dev = crtc->base.dev;
7198 struct drm_i915_private *dev_priv = to_i915(dev);
7199 const struct intel_limit *limit;
7200 int refclk = 96000;
7201
7202 memset(&crtc_state->dpll_hw_state, 0,
7203 sizeof(crtc_state->dpll_hw_state));
7204
7205 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7206 if (intel_panel_use_ssc(dev_priv)) {
7207 refclk = dev_priv->vbt.lvds_ssc_freq;
7208 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7209 }
7210
7211 limit = &intel_limits_i9xx_lvds;
7212 } else {
7213 limit = &intel_limits_i9xx_sdvo;
7214 }
7215
7216 if (!crtc_state->clock_set &&
7217 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7218 refclk, NULL, &crtc_state->dpll)) {
7219 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7220 return -EINVAL;
7221 }
7222
7223 i9xx_compute_dpll(crtc, crtc_state, NULL);
7224
7225 return 0;
7226 }
7227
7228 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7229 struct intel_crtc_state *crtc_state)
7230 {
7231 int refclk = 100000;
7232 const struct intel_limit *limit = &intel_limits_chv;
7233
7234 memset(&crtc_state->dpll_hw_state, 0,
7235 sizeof(crtc_state->dpll_hw_state));
7236
7237 if (!crtc_state->clock_set &&
7238 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7239 refclk, NULL, &crtc_state->dpll)) {
7240 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7241 return -EINVAL;
7242 }
7243
7244 chv_compute_dpll(crtc, crtc_state);
7245
7246 return 0;
7247 }
7248
7249 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7250 struct intel_crtc_state *crtc_state)
7251 {
7252 int refclk = 100000;
7253 const struct intel_limit *limit = &intel_limits_vlv;
7254
7255 memset(&crtc_state->dpll_hw_state, 0,
7256 sizeof(crtc_state->dpll_hw_state));
7257
7258 if (!crtc_state->clock_set &&
7259 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7260 refclk, NULL, &crtc_state->dpll)) {
7261 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7262 return -EINVAL;
7263 }
7264
7265 vlv_compute_dpll(crtc, crtc_state);
7266
7267 return 0;
7268 }
7269
7270 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7271 struct intel_crtc_state *pipe_config)
7272 {
7273 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7274 uint32_t tmp;
7275
7276 if (INTEL_GEN(dev_priv) <= 3 &&
7277 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7278 return;
7279
7280 tmp = I915_READ(PFIT_CONTROL);
7281 if (!(tmp & PFIT_ENABLE))
7282 return;
7283
7284 /* Check whether the pfit is attached to our pipe. */
7285 if (INTEL_GEN(dev_priv) < 4) {
7286 if (crtc->pipe != PIPE_B)
7287 return;
7288 } else {
7289 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7290 return;
7291 }
7292
7293 pipe_config->gmch_pfit.control = tmp;
7294 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7295 }
7296
7297 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7298 struct intel_crtc_state *pipe_config)
7299 {
7300 struct drm_device *dev = crtc->base.dev;
7301 struct drm_i915_private *dev_priv = to_i915(dev);
7302 int pipe = pipe_config->cpu_transcoder;
7303 struct dpll clock;
7304 u32 mdiv;
7305 int refclk = 100000;
7306
7307 /* In case of DSI, DPLL will not be used */
7308 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7309 return;
7310
7311 mutex_lock(&dev_priv->sb_lock);
7312 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7313 mutex_unlock(&dev_priv->sb_lock);
7314
7315 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7316 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7317 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7318 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7319 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7320
7321 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7322 }
7323
7324 static void
7325 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7326 struct intel_initial_plane_config *plane_config)
7327 {
7328 struct drm_device *dev = crtc->base.dev;
7329 struct drm_i915_private *dev_priv = to_i915(dev);
7330 u32 val, base, offset;
7331 int pipe = crtc->pipe, plane = crtc->plane;
7332 int fourcc, pixel_format;
7333 unsigned int aligned_height;
7334 struct drm_framebuffer *fb;
7335 struct intel_framebuffer *intel_fb;
7336
7337 val = I915_READ(DSPCNTR(plane));
7338 if (!(val & DISPLAY_PLANE_ENABLE))
7339 return;
7340
7341 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7342 if (!intel_fb) {
7343 DRM_DEBUG_KMS("failed to alloc fb\n");
7344 return;
7345 }
7346
7347 fb = &intel_fb->base;
7348
7349 fb->dev = dev;
7350
7351 if (INTEL_GEN(dev_priv) >= 4) {
7352 if (val & DISPPLANE_TILED) {
7353 plane_config->tiling = I915_TILING_X;
7354 fb->modifier = I915_FORMAT_MOD_X_TILED;
7355 }
7356 }
7357
7358 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7359 fourcc = i9xx_format_to_fourcc(pixel_format);
7360 fb->format = drm_format_info(fourcc);
7361
7362 if (INTEL_GEN(dev_priv) >= 4) {
7363 if (plane_config->tiling)
7364 offset = I915_READ(DSPTILEOFF(plane));
7365 else
7366 offset = I915_READ(DSPLINOFF(plane));
7367 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7368 } else {
7369 base = I915_READ(DSPADDR(plane));
7370 }
7371 plane_config->base = base;
7372
7373 val = I915_READ(PIPESRC(pipe));
7374 fb->width = ((val >> 16) & 0xfff) + 1;
7375 fb->height = ((val >> 0) & 0xfff) + 1;
7376
7377 val = I915_READ(DSPSTRIDE(pipe));
7378 fb->pitches[0] = val & 0xffffffc0;
7379
7380 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7381
7382 plane_config->size = fb->pitches[0] * aligned_height;
7383
7384 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7385 pipe_name(pipe), plane, fb->width, fb->height,
7386 fb->format->cpp[0] * 8, base, fb->pitches[0],
7387 plane_config->size);
7388
7389 plane_config->fb = intel_fb;
7390 }
7391
7392 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7393 struct intel_crtc_state *pipe_config)
7394 {
7395 struct drm_device *dev = crtc->base.dev;
7396 struct drm_i915_private *dev_priv = to_i915(dev);
7397 int pipe = pipe_config->cpu_transcoder;
7398 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7399 struct dpll clock;
7400 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7401 int refclk = 100000;
7402
7403 /* In case of DSI, DPLL will not be used */
7404 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7405 return;
7406
7407 mutex_lock(&dev_priv->sb_lock);
7408 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7409 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7410 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7411 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7412 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7413 mutex_unlock(&dev_priv->sb_lock);
7414
7415 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7416 clock.m2 = (pll_dw0 & 0xff) << 22;
7417 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7418 clock.m2 |= pll_dw2 & 0x3fffff;
7419 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7420 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7421 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7422
7423 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7424 }
7425
7426 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7427 struct intel_crtc_state *pipe_config)
7428 {
7429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7430 enum intel_display_power_domain power_domain;
7431 uint32_t tmp;
7432 bool ret;
7433
7434 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7435 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7436 return false;
7437
7438 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7439 pipe_config->shared_dpll = NULL;
7440
7441 ret = false;
7442
7443 tmp = I915_READ(PIPECONF(crtc->pipe));
7444 if (!(tmp & PIPECONF_ENABLE))
7445 goto out;
7446
7447 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7448 IS_CHERRYVIEW(dev_priv)) {
7449 switch (tmp & PIPECONF_BPC_MASK) {
7450 case PIPECONF_6BPC:
7451 pipe_config->pipe_bpp = 18;
7452 break;
7453 case PIPECONF_8BPC:
7454 pipe_config->pipe_bpp = 24;
7455 break;
7456 case PIPECONF_10BPC:
7457 pipe_config->pipe_bpp = 30;
7458 break;
7459 default:
7460 break;
7461 }
7462 }
7463
7464 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7465 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7466 pipe_config->limited_color_range = true;
7467
7468 if (INTEL_GEN(dev_priv) < 4)
7469 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7470
7471 intel_get_pipe_timings(crtc, pipe_config);
7472 intel_get_pipe_src_size(crtc, pipe_config);
7473
7474 i9xx_get_pfit_config(crtc, pipe_config);
7475
7476 if (INTEL_GEN(dev_priv) >= 4) {
7477 /* No way to read it out on pipes B and C */
7478 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7479 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7480 else
7481 tmp = I915_READ(DPLL_MD(crtc->pipe));
7482 pipe_config->pixel_multiplier =
7483 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7484 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7485 pipe_config->dpll_hw_state.dpll_md = tmp;
7486 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7487 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7488 tmp = I915_READ(DPLL(crtc->pipe));
7489 pipe_config->pixel_multiplier =
7490 ((tmp & SDVO_MULTIPLIER_MASK)
7491 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7492 } else {
7493 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7494 * port and will be fixed up in the encoder->get_config
7495 * function. */
7496 pipe_config->pixel_multiplier = 1;
7497 }
7498 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7499 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7500 /*
7501 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7502 * on 830. Filter it out here so that we don't
7503 * report errors due to that.
7504 */
7505 if (IS_I830(dev_priv))
7506 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7507
7508 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7509 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7510 } else {
7511 /* Mask out read-only status bits. */
7512 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7513 DPLL_PORTC_READY_MASK |
7514 DPLL_PORTB_READY_MASK);
7515 }
7516
7517 if (IS_CHERRYVIEW(dev_priv))
7518 chv_crtc_clock_get(crtc, pipe_config);
7519 else if (IS_VALLEYVIEW(dev_priv))
7520 vlv_crtc_clock_get(crtc, pipe_config);
7521 else
7522 i9xx_crtc_clock_get(crtc, pipe_config);
7523
7524 /*
7525 * Normally the dotclock is filled in by the encoder .get_config()
7526 * but in case the pipe is enabled w/o any ports we need a sane
7527 * default.
7528 */
7529 pipe_config->base.adjusted_mode.crtc_clock =
7530 pipe_config->port_clock / pipe_config->pixel_multiplier;
7531
7532 ret = true;
7533
7534 out:
7535 intel_display_power_put(dev_priv, power_domain);
7536
7537 return ret;
7538 }
7539
7540 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7541 {
7542 struct intel_encoder *encoder;
7543 int i;
7544 u32 val, final;
7545 bool has_lvds = false;
7546 bool has_cpu_edp = false;
7547 bool has_panel = false;
7548 bool has_ck505 = false;
7549 bool can_ssc = false;
7550 bool using_ssc_source = false;
7551
7552 /* We need to take the global config into account */
7553 for_each_intel_encoder(&dev_priv->drm, encoder) {
7554 switch (encoder->type) {
7555 case INTEL_OUTPUT_LVDS:
7556 has_panel = true;
7557 has_lvds = true;
7558 break;
7559 case INTEL_OUTPUT_EDP:
7560 has_panel = true;
7561 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7562 has_cpu_edp = true;
7563 break;
7564 default:
7565 break;
7566 }
7567 }
7568
7569 if (HAS_PCH_IBX(dev_priv)) {
7570 has_ck505 = dev_priv->vbt.display_clock_mode;
7571 can_ssc = has_ck505;
7572 } else {
7573 has_ck505 = false;
7574 can_ssc = true;
7575 }
7576
7577 /* Check if any DPLLs are using the SSC source */
7578 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7579 u32 temp = I915_READ(PCH_DPLL(i));
7580
7581 if (!(temp & DPLL_VCO_ENABLE))
7582 continue;
7583
7584 if ((temp & PLL_REF_INPUT_MASK) ==
7585 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7586 using_ssc_source = true;
7587 break;
7588 }
7589 }
7590
7591 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7592 has_panel, has_lvds, has_ck505, using_ssc_source);
7593
7594 /* Ironlake: try to setup display ref clock before DPLL
7595 * enabling. This is only under driver's control after
7596 * PCH B stepping, previous chipset stepping should be
7597 * ignoring this setting.
7598 */
7599 val = I915_READ(PCH_DREF_CONTROL);
7600
7601 /* As we must carefully and slowly disable/enable each source in turn,
7602 * compute the final state we want first and check if we need to
7603 * make any changes at all.
7604 */
7605 final = val;
7606 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7607 if (has_ck505)
7608 final |= DREF_NONSPREAD_CK505_ENABLE;
7609 else
7610 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7611
7612 final &= ~DREF_SSC_SOURCE_MASK;
7613 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7614 final &= ~DREF_SSC1_ENABLE;
7615
7616 if (has_panel) {
7617 final |= DREF_SSC_SOURCE_ENABLE;
7618
7619 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7620 final |= DREF_SSC1_ENABLE;
7621
7622 if (has_cpu_edp) {
7623 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7624 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7625 else
7626 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7627 } else
7628 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7629 } else if (using_ssc_source) {
7630 final |= DREF_SSC_SOURCE_ENABLE;
7631 final |= DREF_SSC1_ENABLE;
7632 }
7633
7634 if (final == val)
7635 return;
7636
7637 /* Always enable nonspread source */
7638 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7639
7640 if (has_ck505)
7641 val |= DREF_NONSPREAD_CK505_ENABLE;
7642 else
7643 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7644
7645 if (has_panel) {
7646 val &= ~DREF_SSC_SOURCE_MASK;
7647 val |= DREF_SSC_SOURCE_ENABLE;
7648
7649 /* SSC must be turned on before enabling the CPU output */
7650 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7651 DRM_DEBUG_KMS("Using SSC on panel\n");
7652 val |= DREF_SSC1_ENABLE;
7653 } else
7654 val &= ~DREF_SSC1_ENABLE;
7655
7656 /* Get SSC going before enabling the outputs */
7657 I915_WRITE(PCH_DREF_CONTROL, val);
7658 POSTING_READ(PCH_DREF_CONTROL);
7659 udelay(200);
7660
7661 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7662
7663 /* Enable CPU source on CPU attached eDP */
7664 if (has_cpu_edp) {
7665 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7666 DRM_DEBUG_KMS("Using SSC on eDP\n");
7667 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7668 } else
7669 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7670 } else
7671 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7672
7673 I915_WRITE(PCH_DREF_CONTROL, val);
7674 POSTING_READ(PCH_DREF_CONTROL);
7675 udelay(200);
7676 } else {
7677 DRM_DEBUG_KMS("Disabling CPU source output\n");
7678
7679 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7680
7681 /* Turn off CPU output */
7682 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7683
7684 I915_WRITE(PCH_DREF_CONTROL, val);
7685 POSTING_READ(PCH_DREF_CONTROL);
7686 udelay(200);
7687
7688 if (!using_ssc_source) {
7689 DRM_DEBUG_KMS("Disabling SSC source\n");
7690
7691 /* Turn off the SSC source */
7692 val &= ~DREF_SSC_SOURCE_MASK;
7693 val |= DREF_SSC_SOURCE_DISABLE;
7694
7695 /* Turn off SSC1 */
7696 val &= ~DREF_SSC1_ENABLE;
7697
7698 I915_WRITE(PCH_DREF_CONTROL, val);
7699 POSTING_READ(PCH_DREF_CONTROL);
7700 udelay(200);
7701 }
7702 }
7703
7704 BUG_ON(val != final);
7705 }
7706
7707 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7708 {
7709 uint32_t tmp;
7710
7711 tmp = I915_READ(SOUTH_CHICKEN2);
7712 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7713 I915_WRITE(SOUTH_CHICKEN2, tmp);
7714
7715 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7716 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7717 DRM_ERROR("FDI mPHY reset assert timeout\n");
7718
7719 tmp = I915_READ(SOUTH_CHICKEN2);
7720 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7721 I915_WRITE(SOUTH_CHICKEN2, tmp);
7722
7723 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7724 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7725 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7726 }
7727
7728 /* WaMPhyProgramming:hsw */
7729 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7730 {
7731 uint32_t tmp;
7732
7733 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7734 tmp &= ~(0xFF << 24);
7735 tmp |= (0x12 << 24);
7736 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7737
7738 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7739 tmp |= (1 << 11);
7740 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7741
7742 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7743 tmp |= (1 << 11);
7744 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7745
7746 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7747 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7748 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7749
7750 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7751 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7752 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7753
7754 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7755 tmp &= ~(7 << 13);
7756 tmp |= (5 << 13);
7757 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7758
7759 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7760 tmp &= ~(7 << 13);
7761 tmp |= (5 << 13);
7762 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7763
7764 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7765 tmp &= ~0xFF;
7766 tmp |= 0x1C;
7767 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7768
7769 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7770 tmp &= ~0xFF;
7771 tmp |= 0x1C;
7772 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7773
7774 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7775 tmp &= ~(0xFF << 16);
7776 tmp |= (0x1C << 16);
7777 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7778
7779 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7780 tmp &= ~(0xFF << 16);
7781 tmp |= (0x1C << 16);
7782 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7783
7784 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7785 tmp |= (1 << 27);
7786 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7787
7788 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7789 tmp |= (1 << 27);
7790 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7791
7792 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7793 tmp &= ~(0xF << 28);
7794 tmp |= (4 << 28);
7795 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7796
7797 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7798 tmp &= ~(0xF << 28);
7799 tmp |= (4 << 28);
7800 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7801 }
7802
7803 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7804 * Programming" based on the parameters passed:
7805 * - Sequence to enable CLKOUT_DP
7806 * - Sequence to enable CLKOUT_DP without spread
7807 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7808 */
7809 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7810 bool with_spread, bool with_fdi)
7811 {
7812 uint32_t reg, tmp;
7813
7814 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7815 with_spread = true;
7816 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7817 with_fdi, "LP PCH doesn't have FDI\n"))
7818 with_fdi = false;
7819
7820 mutex_lock(&dev_priv->sb_lock);
7821
7822 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7823 tmp &= ~SBI_SSCCTL_DISABLE;
7824 tmp |= SBI_SSCCTL_PATHALT;
7825 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7826
7827 udelay(24);
7828
7829 if (with_spread) {
7830 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7831 tmp &= ~SBI_SSCCTL_PATHALT;
7832 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7833
7834 if (with_fdi) {
7835 lpt_reset_fdi_mphy(dev_priv);
7836 lpt_program_fdi_mphy(dev_priv);
7837 }
7838 }
7839
7840 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7841 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7842 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7843 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7844
7845 mutex_unlock(&dev_priv->sb_lock);
7846 }
7847
7848 /* Sequence to disable CLKOUT_DP */
7849 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7850 {
7851 uint32_t reg, tmp;
7852
7853 mutex_lock(&dev_priv->sb_lock);
7854
7855 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7856 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7857 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7858 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7859
7860 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7861 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7862 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7863 tmp |= SBI_SSCCTL_PATHALT;
7864 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7865 udelay(32);
7866 }
7867 tmp |= SBI_SSCCTL_DISABLE;
7868 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7869 }
7870
7871 mutex_unlock(&dev_priv->sb_lock);
7872 }
7873
7874 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7875
7876 static const uint16_t sscdivintphase[] = {
7877 [BEND_IDX( 50)] = 0x3B23,
7878 [BEND_IDX( 45)] = 0x3B23,
7879 [BEND_IDX( 40)] = 0x3C23,
7880 [BEND_IDX( 35)] = 0x3C23,
7881 [BEND_IDX( 30)] = 0x3D23,
7882 [BEND_IDX( 25)] = 0x3D23,
7883 [BEND_IDX( 20)] = 0x3E23,
7884 [BEND_IDX( 15)] = 0x3E23,
7885 [BEND_IDX( 10)] = 0x3F23,
7886 [BEND_IDX( 5)] = 0x3F23,
7887 [BEND_IDX( 0)] = 0x0025,
7888 [BEND_IDX( -5)] = 0x0025,
7889 [BEND_IDX(-10)] = 0x0125,
7890 [BEND_IDX(-15)] = 0x0125,
7891 [BEND_IDX(-20)] = 0x0225,
7892 [BEND_IDX(-25)] = 0x0225,
7893 [BEND_IDX(-30)] = 0x0325,
7894 [BEND_IDX(-35)] = 0x0325,
7895 [BEND_IDX(-40)] = 0x0425,
7896 [BEND_IDX(-45)] = 0x0425,
7897 [BEND_IDX(-50)] = 0x0525,
7898 };
7899
7900 /*
7901 * Bend CLKOUT_DP
7902 * steps -50 to 50 inclusive, in steps of 5
7903 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7904 * change in clock period = -(steps / 10) * 5.787 ps
7905 */
7906 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7907 {
7908 uint32_t tmp;
7909 int idx = BEND_IDX(steps);
7910
7911 if (WARN_ON(steps % 5 != 0))
7912 return;
7913
7914 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7915 return;
7916
7917 mutex_lock(&dev_priv->sb_lock);
7918
7919 if (steps % 10 != 0)
7920 tmp = 0xAAAAAAAB;
7921 else
7922 tmp = 0x00000000;
7923 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7924
7925 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7926 tmp &= 0xffff0000;
7927 tmp |= sscdivintphase[idx];
7928 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7929
7930 mutex_unlock(&dev_priv->sb_lock);
7931 }
7932
7933 #undef BEND_IDX
7934
7935 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7936 {
7937 struct intel_encoder *encoder;
7938 bool has_vga = false;
7939
7940 for_each_intel_encoder(&dev_priv->drm, encoder) {
7941 switch (encoder->type) {
7942 case INTEL_OUTPUT_ANALOG:
7943 has_vga = true;
7944 break;
7945 default:
7946 break;
7947 }
7948 }
7949
7950 if (has_vga) {
7951 lpt_bend_clkout_dp(dev_priv, 0);
7952 lpt_enable_clkout_dp(dev_priv, true, true);
7953 } else {
7954 lpt_disable_clkout_dp(dev_priv);
7955 }
7956 }
7957
7958 /*
7959 * Initialize reference clocks when the driver loads
7960 */
7961 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7962 {
7963 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7964 ironlake_init_pch_refclk(dev_priv);
7965 else if (HAS_PCH_LPT(dev_priv))
7966 lpt_init_pch_refclk(dev_priv);
7967 }
7968
7969 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7970 {
7971 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7973 int pipe = intel_crtc->pipe;
7974 uint32_t val;
7975
7976 val = 0;
7977
7978 switch (intel_crtc->config->pipe_bpp) {
7979 case 18:
7980 val |= PIPECONF_6BPC;
7981 break;
7982 case 24:
7983 val |= PIPECONF_8BPC;
7984 break;
7985 case 30:
7986 val |= PIPECONF_10BPC;
7987 break;
7988 case 36:
7989 val |= PIPECONF_12BPC;
7990 break;
7991 default:
7992 /* Case prevented by intel_choose_pipe_bpp_dither. */
7993 BUG();
7994 }
7995
7996 if (intel_crtc->config->dither)
7997 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7998
7999 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8000 val |= PIPECONF_INTERLACED_ILK;
8001 else
8002 val |= PIPECONF_PROGRESSIVE;
8003
8004 if (intel_crtc->config->limited_color_range)
8005 val |= PIPECONF_COLOR_RANGE_SELECT;
8006
8007 I915_WRITE(PIPECONF(pipe), val);
8008 POSTING_READ(PIPECONF(pipe));
8009 }
8010
8011 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8012 {
8013 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8016 u32 val = 0;
8017
8018 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8019 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8020
8021 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8022 val |= PIPECONF_INTERLACED_ILK;
8023 else
8024 val |= PIPECONF_PROGRESSIVE;
8025
8026 I915_WRITE(PIPECONF(cpu_transcoder), val);
8027 POSTING_READ(PIPECONF(cpu_transcoder));
8028 }
8029
8030 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8031 {
8032 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8034
8035 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8036 u32 val = 0;
8037
8038 switch (intel_crtc->config->pipe_bpp) {
8039 case 18:
8040 val |= PIPEMISC_DITHER_6_BPC;
8041 break;
8042 case 24:
8043 val |= PIPEMISC_DITHER_8_BPC;
8044 break;
8045 case 30:
8046 val |= PIPEMISC_DITHER_10_BPC;
8047 break;
8048 case 36:
8049 val |= PIPEMISC_DITHER_12_BPC;
8050 break;
8051 default:
8052 /* Case prevented by pipe_config_set_bpp. */
8053 BUG();
8054 }
8055
8056 if (intel_crtc->config->dither)
8057 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8058
8059 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8060 }
8061 }
8062
8063 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8064 {
8065 /*
8066 * Account for spread spectrum to avoid
8067 * oversubscribing the link. Max center spread
8068 * is 2.5%; use 5% for safety's sake.
8069 */
8070 u32 bps = target_clock * bpp * 21 / 20;
8071 return DIV_ROUND_UP(bps, link_bw * 8);
8072 }
8073
8074 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8075 {
8076 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8077 }
8078
8079 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8080 struct intel_crtc_state *crtc_state,
8081 struct dpll *reduced_clock)
8082 {
8083 struct drm_crtc *crtc = &intel_crtc->base;
8084 struct drm_device *dev = crtc->dev;
8085 struct drm_i915_private *dev_priv = to_i915(dev);
8086 u32 dpll, fp, fp2;
8087 int factor;
8088
8089 /* Enable autotuning of the PLL clock (if permissible) */
8090 factor = 21;
8091 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8092 if ((intel_panel_use_ssc(dev_priv) &&
8093 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8094 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8095 factor = 25;
8096 } else if (crtc_state->sdvo_tv_clock)
8097 factor = 20;
8098
8099 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8100
8101 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8102 fp |= FP_CB_TUNE;
8103
8104 if (reduced_clock) {
8105 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8106
8107 if (reduced_clock->m < factor * reduced_clock->n)
8108 fp2 |= FP_CB_TUNE;
8109 } else {
8110 fp2 = fp;
8111 }
8112
8113 dpll = 0;
8114
8115 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8116 dpll |= DPLLB_MODE_LVDS;
8117 else
8118 dpll |= DPLLB_MODE_DAC_SERIAL;
8119
8120 dpll |= (crtc_state->pixel_multiplier - 1)
8121 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8122
8123 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8124 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8125 dpll |= DPLL_SDVO_HIGH_SPEED;
8126
8127 if (intel_crtc_has_dp_encoder(crtc_state))
8128 dpll |= DPLL_SDVO_HIGH_SPEED;
8129
8130 /*
8131 * The high speed IO clock is only really required for
8132 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8133 * possible to share the DPLL between CRT and HDMI. Enabling
8134 * the clock needlessly does no real harm, except use up a
8135 * bit of power potentially.
8136 *
8137 * We'll limit this to IVB with 3 pipes, since it has only two
8138 * DPLLs and so DPLL sharing is the only way to get three pipes
8139 * driving PCH ports at the same time. On SNB we could do this,
8140 * and potentially avoid enabling the second DPLL, but it's not
8141 * clear if it''s a win or loss power wise. No point in doing
8142 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8143 */
8144 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8145 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8146 dpll |= DPLL_SDVO_HIGH_SPEED;
8147
8148 /* compute bitmask from p1 value */
8149 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8150 /* also FPA1 */
8151 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8152
8153 switch (crtc_state->dpll.p2) {
8154 case 5:
8155 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8156 break;
8157 case 7:
8158 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8159 break;
8160 case 10:
8161 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8162 break;
8163 case 14:
8164 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8165 break;
8166 }
8167
8168 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8169 intel_panel_use_ssc(dev_priv))
8170 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8171 else
8172 dpll |= PLL_REF_INPUT_DREFCLK;
8173
8174 dpll |= DPLL_VCO_ENABLE;
8175
8176 crtc_state->dpll_hw_state.dpll = dpll;
8177 crtc_state->dpll_hw_state.fp0 = fp;
8178 crtc_state->dpll_hw_state.fp1 = fp2;
8179 }
8180
8181 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8182 struct intel_crtc_state *crtc_state)
8183 {
8184 struct drm_device *dev = crtc->base.dev;
8185 struct drm_i915_private *dev_priv = to_i915(dev);
8186 const struct intel_limit *limit;
8187 int refclk = 120000;
8188
8189 memset(&crtc_state->dpll_hw_state, 0,
8190 sizeof(crtc_state->dpll_hw_state));
8191
8192 crtc->lowfreq_avail = false;
8193
8194 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8195 if (!crtc_state->has_pch_encoder)
8196 return 0;
8197
8198 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8199 if (intel_panel_use_ssc(dev_priv)) {
8200 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8201 dev_priv->vbt.lvds_ssc_freq);
8202 refclk = dev_priv->vbt.lvds_ssc_freq;
8203 }
8204
8205 if (intel_is_dual_link_lvds(dev)) {
8206 if (refclk == 100000)
8207 limit = &intel_limits_ironlake_dual_lvds_100m;
8208 else
8209 limit = &intel_limits_ironlake_dual_lvds;
8210 } else {
8211 if (refclk == 100000)
8212 limit = &intel_limits_ironlake_single_lvds_100m;
8213 else
8214 limit = &intel_limits_ironlake_single_lvds;
8215 }
8216 } else {
8217 limit = &intel_limits_ironlake_dac;
8218 }
8219
8220 if (!crtc_state->clock_set &&
8221 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8222 refclk, NULL, &crtc_state->dpll)) {
8223 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8224 return -EINVAL;
8225 }
8226
8227 ironlake_compute_dpll(crtc, crtc_state, NULL);
8228
8229 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8230 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8231 pipe_name(crtc->pipe));
8232 return -EINVAL;
8233 }
8234
8235 return 0;
8236 }
8237
8238 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8239 struct intel_link_m_n *m_n)
8240 {
8241 struct drm_device *dev = crtc->base.dev;
8242 struct drm_i915_private *dev_priv = to_i915(dev);
8243 enum pipe pipe = crtc->pipe;
8244
8245 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8246 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8247 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8248 & ~TU_SIZE_MASK;
8249 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8250 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8251 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8252 }
8253
8254 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8255 enum transcoder transcoder,
8256 struct intel_link_m_n *m_n,
8257 struct intel_link_m_n *m2_n2)
8258 {
8259 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8260 enum pipe pipe = crtc->pipe;
8261
8262 if (INTEL_GEN(dev_priv) >= 5) {
8263 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8264 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8265 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8266 & ~TU_SIZE_MASK;
8267 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8268 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8269 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8270 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8271 * gen < 8) and if DRRS is supported (to make sure the
8272 * registers are not unnecessarily read).
8273 */
8274 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8275 crtc->config->has_drrs) {
8276 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8277 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8278 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8279 & ~TU_SIZE_MASK;
8280 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8281 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8282 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8283 }
8284 } else {
8285 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8286 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8287 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8288 & ~TU_SIZE_MASK;
8289 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8290 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8291 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8292 }
8293 }
8294
8295 void intel_dp_get_m_n(struct intel_crtc *crtc,
8296 struct intel_crtc_state *pipe_config)
8297 {
8298 if (pipe_config->has_pch_encoder)
8299 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8300 else
8301 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8302 &pipe_config->dp_m_n,
8303 &pipe_config->dp_m2_n2);
8304 }
8305
8306 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8307 struct intel_crtc_state *pipe_config)
8308 {
8309 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8310 &pipe_config->fdi_m_n, NULL);
8311 }
8312
8313 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8314 struct intel_crtc_state *pipe_config)
8315 {
8316 struct drm_device *dev = crtc->base.dev;
8317 struct drm_i915_private *dev_priv = to_i915(dev);
8318 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8319 uint32_t ps_ctrl = 0;
8320 int id = -1;
8321 int i;
8322
8323 /* find scaler attached to this pipe */
8324 for (i = 0; i < crtc->num_scalers; i++) {
8325 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8326 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8327 id = i;
8328 pipe_config->pch_pfit.enabled = true;
8329 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8330 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8331 break;
8332 }
8333 }
8334
8335 scaler_state->scaler_id = id;
8336 if (id >= 0) {
8337 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8338 } else {
8339 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8340 }
8341 }
8342
8343 static void
8344 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8345 struct intel_initial_plane_config *plane_config)
8346 {
8347 struct drm_device *dev = crtc->base.dev;
8348 struct drm_i915_private *dev_priv = to_i915(dev);
8349 u32 val, base, offset, stride_mult, tiling;
8350 int pipe = crtc->pipe;
8351 int fourcc, pixel_format;
8352 unsigned int aligned_height;
8353 struct drm_framebuffer *fb;
8354 struct intel_framebuffer *intel_fb;
8355
8356 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8357 if (!intel_fb) {
8358 DRM_DEBUG_KMS("failed to alloc fb\n");
8359 return;
8360 }
8361
8362 fb = &intel_fb->base;
8363
8364 fb->dev = dev;
8365
8366 val = I915_READ(PLANE_CTL(pipe, 0));
8367 if (!(val & PLANE_CTL_ENABLE))
8368 goto error;
8369
8370 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8371 fourcc = skl_format_to_fourcc(pixel_format,
8372 val & PLANE_CTL_ORDER_RGBX,
8373 val & PLANE_CTL_ALPHA_MASK);
8374 fb->format = drm_format_info(fourcc);
8375
8376 tiling = val & PLANE_CTL_TILED_MASK;
8377 switch (tiling) {
8378 case PLANE_CTL_TILED_LINEAR:
8379 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8380 break;
8381 case PLANE_CTL_TILED_X:
8382 plane_config->tiling = I915_TILING_X;
8383 fb->modifier = I915_FORMAT_MOD_X_TILED;
8384 break;
8385 case PLANE_CTL_TILED_Y:
8386 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8387 break;
8388 case PLANE_CTL_TILED_YF:
8389 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8390 break;
8391 default:
8392 MISSING_CASE(tiling);
8393 goto error;
8394 }
8395
8396 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8397 plane_config->base = base;
8398
8399 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8400
8401 val = I915_READ(PLANE_SIZE(pipe, 0));
8402 fb->height = ((val >> 16) & 0xfff) + 1;
8403 fb->width = ((val >> 0) & 0x1fff) + 1;
8404
8405 val = I915_READ(PLANE_STRIDE(pipe, 0));
8406 stride_mult = intel_fb_stride_alignment(fb, 0);
8407 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8408
8409 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8410
8411 plane_config->size = fb->pitches[0] * aligned_height;
8412
8413 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8414 pipe_name(pipe), fb->width, fb->height,
8415 fb->format->cpp[0] * 8, base, fb->pitches[0],
8416 plane_config->size);
8417
8418 plane_config->fb = intel_fb;
8419 return;
8420
8421 error:
8422 kfree(intel_fb);
8423 }
8424
8425 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8426 struct intel_crtc_state *pipe_config)
8427 {
8428 struct drm_device *dev = crtc->base.dev;
8429 struct drm_i915_private *dev_priv = to_i915(dev);
8430 uint32_t tmp;
8431
8432 tmp = I915_READ(PF_CTL(crtc->pipe));
8433
8434 if (tmp & PF_ENABLE) {
8435 pipe_config->pch_pfit.enabled = true;
8436 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8437 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8438
8439 /* We currently do not free assignements of panel fitters on
8440 * ivb/hsw (since we don't use the higher upscaling modes which
8441 * differentiates them) so just WARN about this case for now. */
8442 if (IS_GEN7(dev_priv)) {
8443 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8444 PF_PIPE_SEL_IVB(crtc->pipe));
8445 }
8446 }
8447 }
8448
8449 static void
8450 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8451 struct intel_initial_plane_config *plane_config)
8452 {
8453 struct drm_device *dev = crtc->base.dev;
8454 struct drm_i915_private *dev_priv = to_i915(dev);
8455 u32 val, base, offset;
8456 int pipe = crtc->pipe;
8457 int fourcc, pixel_format;
8458 unsigned int aligned_height;
8459 struct drm_framebuffer *fb;
8460 struct intel_framebuffer *intel_fb;
8461
8462 val = I915_READ(DSPCNTR(pipe));
8463 if (!(val & DISPLAY_PLANE_ENABLE))
8464 return;
8465
8466 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8467 if (!intel_fb) {
8468 DRM_DEBUG_KMS("failed to alloc fb\n");
8469 return;
8470 }
8471
8472 fb = &intel_fb->base;
8473
8474 fb->dev = dev;
8475
8476 if (INTEL_GEN(dev_priv) >= 4) {
8477 if (val & DISPPLANE_TILED) {
8478 plane_config->tiling = I915_TILING_X;
8479 fb->modifier = I915_FORMAT_MOD_X_TILED;
8480 }
8481 }
8482
8483 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8484 fourcc = i9xx_format_to_fourcc(pixel_format);
8485 fb->format = drm_format_info(fourcc);
8486
8487 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8488 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8489 offset = I915_READ(DSPOFFSET(pipe));
8490 } else {
8491 if (plane_config->tiling)
8492 offset = I915_READ(DSPTILEOFF(pipe));
8493 else
8494 offset = I915_READ(DSPLINOFF(pipe));
8495 }
8496 plane_config->base = base;
8497
8498 val = I915_READ(PIPESRC(pipe));
8499 fb->width = ((val >> 16) & 0xfff) + 1;
8500 fb->height = ((val >> 0) & 0xfff) + 1;
8501
8502 val = I915_READ(DSPSTRIDE(pipe));
8503 fb->pitches[0] = val & 0xffffffc0;
8504
8505 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8506
8507 plane_config->size = fb->pitches[0] * aligned_height;
8508
8509 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8510 pipe_name(pipe), fb->width, fb->height,
8511 fb->format->cpp[0] * 8, base, fb->pitches[0],
8512 plane_config->size);
8513
8514 plane_config->fb = intel_fb;
8515 }
8516
8517 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8518 struct intel_crtc_state *pipe_config)
8519 {
8520 struct drm_device *dev = crtc->base.dev;
8521 struct drm_i915_private *dev_priv = to_i915(dev);
8522 enum intel_display_power_domain power_domain;
8523 uint32_t tmp;
8524 bool ret;
8525
8526 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8527 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8528 return false;
8529
8530 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8531 pipe_config->shared_dpll = NULL;
8532
8533 ret = false;
8534 tmp = I915_READ(PIPECONF(crtc->pipe));
8535 if (!(tmp & PIPECONF_ENABLE))
8536 goto out;
8537
8538 switch (tmp & PIPECONF_BPC_MASK) {
8539 case PIPECONF_6BPC:
8540 pipe_config->pipe_bpp = 18;
8541 break;
8542 case PIPECONF_8BPC:
8543 pipe_config->pipe_bpp = 24;
8544 break;
8545 case PIPECONF_10BPC:
8546 pipe_config->pipe_bpp = 30;
8547 break;
8548 case PIPECONF_12BPC:
8549 pipe_config->pipe_bpp = 36;
8550 break;
8551 default:
8552 break;
8553 }
8554
8555 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8556 pipe_config->limited_color_range = true;
8557
8558 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8559 struct intel_shared_dpll *pll;
8560 enum intel_dpll_id pll_id;
8561
8562 pipe_config->has_pch_encoder = true;
8563
8564 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8565 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8566 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8567
8568 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8569
8570 if (HAS_PCH_IBX(dev_priv)) {
8571 /*
8572 * The pipe->pch transcoder and pch transcoder->pll
8573 * mapping is fixed.
8574 */
8575 pll_id = (enum intel_dpll_id) crtc->pipe;
8576 } else {
8577 tmp = I915_READ(PCH_DPLL_SEL);
8578 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8579 pll_id = DPLL_ID_PCH_PLL_B;
8580 else
8581 pll_id= DPLL_ID_PCH_PLL_A;
8582 }
8583
8584 pipe_config->shared_dpll =
8585 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8586 pll = pipe_config->shared_dpll;
8587
8588 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8589 &pipe_config->dpll_hw_state));
8590
8591 tmp = pipe_config->dpll_hw_state.dpll;
8592 pipe_config->pixel_multiplier =
8593 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8594 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8595
8596 ironlake_pch_clock_get(crtc, pipe_config);
8597 } else {
8598 pipe_config->pixel_multiplier = 1;
8599 }
8600
8601 intel_get_pipe_timings(crtc, pipe_config);
8602 intel_get_pipe_src_size(crtc, pipe_config);
8603
8604 ironlake_get_pfit_config(crtc, pipe_config);
8605
8606 ret = true;
8607
8608 out:
8609 intel_display_power_put(dev_priv, power_domain);
8610
8611 return ret;
8612 }
8613
8614 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8615 {
8616 struct drm_device *dev = &dev_priv->drm;
8617 struct intel_crtc *crtc;
8618
8619 for_each_intel_crtc(dev, crtc)
8620 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8621 pipe_name(crtc->pipe));
8622
8623 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8624 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8625 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8626 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8627 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8628 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8629 "CPU PWM1 enabled\n");
8630 if (IS_HASWELL(dev_priv))
8631 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8632 "CPU PWM2 enabled\n");
8633 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8634 "PCH PWM1 enabled\n");
8635 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8636 "Utility pin enabled\n");
8637 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8638
8639 /*
8640 * In theory we can still leave IRQs enabled, as long as only the HPD
8641 * interrupts remain enabled. We used to check for that, but since it's
8642 * gen-specific and since we only disable LCPLL after we fully disable
8643 * the interrupts, the check below should be enough.
8644 */
8645 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8646 }
8647
8648 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8649 {
8650 if (IS_HASWELL(dev_priv))
8651 return I915_READ(D_COMP_HSW);
8652 else
8653 return I915_READ(D_COMP_BDW);
8654 }
8655
8656 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8657 {
8658 if (IS_HASWELL(dev_priv)) {
8659 mutex_lock(&dev_priv->rps.hw_lock);
8660 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8661 val))
8662 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8663 mutex_unlock(&dev_priv->rps.hw_lock);
8664 } else {
8665 I915_WRITE(D_COMP_BDW, val);
8666 POSTING_READ(D_COMP_BDW);
8667 }
8668 }
8669
8670 /*
8671 * This function implements pieces of two sequences from BSpec:
8672 * - Sequence for display software to disable LCPLL
8673 * - Sequence for display software to allow package C8+
8674 * The steps implemented here are just the steps that actually touch the LCPLL
8675 * register. Callers should take care of disabling all the display engine
8676 * functions, doing the mode unset, fixing interrupts, etc.
8677 */
8678 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8679 bool switch_to_fclk, bool allow_power_down)
8680 {
8681 uint32_t val;
8682
8683 assert_can_disable_lcpll(dev_priv);
8684
8685 val = I915_READ(LCPLL_CTL);
8686
8687 if (switch_to_fclk) {
8688 val |= LCPLL_CD_SOURCE_FCLK;
8689 I915_WRITE(LCPLL_CTL, val);
8690
8691 if (wait_for_us(I915_READ(LCPLL_CTL) &
8692 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8693 DRM_ERROR("Switching to FCLK failed\n");
8694
8695 val = I915_READ(LCPLL_CTL);
8696 }
8697
8698 val |= LCPLL_PLL_DISABLE;
8699 I915_WRITE(LCPLL_CTL, val);
8700 POSTING_READ(LCPLL_CTL);
8701
8702 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8703 DRM_ERROR("LCPLL still locked\n");
8704
8705 val = hsw_read_dcomp(dev_priv);
8706 val |= D_COMP_COMP_DISABLE;
8707 hsw_write_dcomp(dev_priv, val);
8708 ndelay(100);
8709
8710 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8711 1))
8712 DRM_ERROR("D_COMP RCOMP still in progress\n");
8713
8714 if (allow_power_down) {
8715 val = I915_READ(LCPLL_CTL);
8716 val |= LCPLL_POWER_DOWN_ALLOW;
8717 I915_WRITE(LCPLL_CTL, val);
8718 POSTING_READ(LCPLL_CTL);
8719 }
8720 }
8721
8722 /*
8723 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8724 * source.
8725 */
8726 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8727 {
8728 uint32_t val;
8729
8730 val = I915_READ(LCPLL_CTL);
8731
8732 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8733 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8734 return;
8735
8736 /*
8737 * Make sure we're not on PC8 state before disabling PC8, otherwise
8738 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8739 */
8740 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8741
8742 if (val & LCPLL_POWER_DOWN_ALLOW) {
8743 val &= ~LCPLL_POWER_DOWN_ALLOW;
8744 I915_WRITE(LCPLL_CTL, val);
8745 POSTING_READ(LCPLL_CTL);
8746 }
8747
8748 val = hsw_read_dcomp(dev_priv);
8749 val |= D_COMP_COMP_FORCE;
8750 val &= ~D_COMP_COMP_DISABLE;
8751 hsw_write_dcomp(dev_priv, val);
8752
8753 val = I915_READ(LCPLL_CTL);
8754 val &= ~LCPLL_PLL_DISABLE;
8755 I915_WRITE(LCPLL_CTL, val);
8756
8757 if (intel_wait_for_register(dev_priv,
8758 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8759 5))
8760 DRM_ERROR("LCPLL not locked yet\n");
8761
8762 if (val & LCPLL_CD_SOURCE_FCLK) {
8763 val = I915_READ(LCPLL_CTL);
8764 val &= ~LCPLL_CD_SOURCE_FCLK;
8765 I915_WRITE(LCPLL_CTL, val);
8766
8767 if (wait_for_us((I915_READ(LCPLL_CTL) &
8768 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8769 DRM_ERROR("Switching back to LCPLL failed\n");
8770 }
8771
8772 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8773 intel_update_cdclk(dev_priv);
8774 }
8775
8776 /*
8777 * Package states C8 and deeper are really deep PC states that can only be
8778 * reached when all the devices on the system allow it, so even if the graphics
8779 * device allows PC8+, it doesn't mean the system will actually get to these
8780 * states. Our driver only allows PC8+ when going into runtime PM.
8781 *
8782 * The requirements for PC8+ are that all the outputs are disabled, the power
8783 * well is disabled and most interrupts are disabled, and these are also
8784 * requirements for runtime PM. When these conditions are met, we manually do
8785 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8786 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8787 * hang the machine.
8788 *
8789 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8790 * the state of some registers, so when we come back from PC8+ we need to
8791 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8792 * need to take care of the registers kept by RC6. Notice that this happens even
8793 * if we don't put the device in PCI D3 state (which is what currently happens
8794 * because of the runtime PM support).
8795 *
8796 * For more, read "Display Sequences for Package C8" on the hardware
8797 * documentation.
8798 */
8799 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8800 {
8801 uint32_t val;
8802
8803 DRM_DEBUG_KMS("Enabling package C8+\n");
8804
8805 if (HAS_PCH_LPT_LP(dev_priv)) {
8806 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8807 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8808 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8809 }
8810
8811 lpt_disable_clkout_dp(dev_priv);
8812 hsw_disable_lcpll(dev_priv, true, true);
8813 }
8814
8815 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8816 {
8817 uint32_t val;
8818
8819 DRM_DEBUG_KMS("Disabling package C8+\n");
8820
8821 hsw_restore_lcpll(dev_priv);
8822 lpt_init_pch_refclk(dev_priv);
8823
8824 if (HAS_PCH_LPT_LP(dev_priv)) {
8825 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8826 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8827 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8828 }
8829 }
8830
8831 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8832 struct intel_crtc_state *crtc_state)
8833 {
8834 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8835 struct intel_encoder *encoder =
8836 intel_ddi_get_crtc_new_encoder(crtc_state);
8837
8838 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8839 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8840 pipe_name(crtc->pipe));
8841 return -EINVAL;
8842 }
8843 }
8844
8845 crtc->lowfreq_avail = false;
8846
8847 return 0;
8848 }
8849
8850 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8851 enum port port,
8852 struct intel_crtc_state *pipe_config)
8853 {
8854 enum intel_dpll_id id;
8855 u32 temp;
8856
8857 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8858 id = temp >> (port * 2);
8859
8860 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8861 return;
8862
8863 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8864 }
8865
8866 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8867 enum port port,
8868 struct intel_crtc_state *pipe_config)
8869 {
8870 enum intel_dpll_id id;
8871
8872 switch (port) {
8873 case PORT_A:
8874 id = DPLL_ID_SKL_DPLL0;
8875 break;
8876 case PORT_B:
8877 id = DPLL_ID_SKL_DPLL1;
8878 break;
8879 case PORT_C:
8880 id = DPLL_ID_SKL_DPLL2;
8881 break;
8882 default:
8883 DRM_ERROR("Incorrect port type\n");
8884 return;
8885 }
8886
8887 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8888 }
8889
8890 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8891 enum port port,
8892 struct intel_crtc_state *pipe_config)
8893 {
8894 enum intel_dpll_id id;
8895 u32 temp;
8896
8897 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8898 id = temp >> (port * 3 + 1);
8899
8900 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8901 return;
8902
8903 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8904 }
8905
8906 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8907 enum port port,
8908 struct intel_crtc_state *pipe_config)
8909 {
8910 enum intel_dpll_id id;
8911 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8912
8913 switch (ddi_pll_sel) {
8914 case PORT_CLK_SEL_WRPLL1:
8915 id = DPLL_ID_WRPLL1;
8916 break;
8917 case PORT_CLK_SEL_WRPLL2:
8918 id = DPLL_ID_WRPLL2;
8919 break;
8920 case PORT_CLK_SEL_SPLL:
8921 id = DPLL_ID_SPLL;
8922 break;
8923 case PORT_CLK_SEL_LCPLL_810:
8924 id = DPLL_ID_LCPLL_810;
8925 break;
8926 case PORT_CLK_SEL_LCPLL_1350:
8927 id = DPLL_ID_LCPLL_1350;
8928 break;
8929 case PORT_CLK_SEL_LCPLL_2700:
8930 id = DPLL_ID_LCPLL_2700;
8931 break;
8932 default:
8933 MISSING_CASE(ddi_pll_sel);
8934 /* fall through */
8935 case PORT_CLK_SEL_NONE:
8936 return;
8937 }
8938
8939 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8940 }
8941
8942 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8943 struct intel_crtc_state *pipe_config,
8944 u64 *power_domain_mask)
8945 {
8946 struct drm_device *dev = crtc->base.dev;
8947 struct drm_i915_private *dev_priv = to_i915(dev);
8948 enum intel_display_power_domain power_domain;
8949 u32 tmp;
8950
8951 /*
8952 * The pipe->transcoder mapping is fixed with the exception of the eDP
8953 * transcoder handled below.
8954 */
8955 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8956
8957 /*
8958 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8959 * consistency and less surprising code; it's in always on power).
8960 */
8961 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8962 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8963 enum pipe trans_edp_pipe;
8964 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8965 default:
8966 WARN(1, "unknown pipe linked to edp transcoder\n");
8967 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8968 case TRANS_DDI_EDP_INPUT_A_ON:
8969 trans_edp_pipe = PIPE_A;
8970 break;
8971 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8972 trans_edp_pipe = PIPE_B;
8973 break;
8974 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8975 trans_edp_pipe = PIPE_C;
8976 break;
8977 }
8978
8979 if (trans_edp_pipe == crtc->pipe)
8980 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8981 }
8982
8983 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8984 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8985 return false;
8986 *power_domain_mask |= BIT_ULL(power_domain);
8987
8988 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8989
8990 return tmp & PIPECONF_ENABLE;
8991 }
8992
8993 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8994 struct intel_crtc_state *pipe_config,
8995 u64 *power_domain_mask)
8996 {
8997 struct drm_device *dev = crtc->base.dev;
8998 struct drm_i915_private *dev_priv = to_i915(dev);
8999 enum intel_display_power_domain power_domain;
9000 enum port port;
9001 enum transcoder cpu_transcoder;
9002 u32 tmp;
9003
9004 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9005 if (port == PORT_A)
9006 cpu_transcoder = TRANSCODER_DSI_A;
9007 else
9008 cpu_transcoder = TRANSCODER_DSI_C;
9009
9010 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9011 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9012 continue;
9013 *power_domain_mask |= BIT_ULL(power_domain);
9014
9015 /*
9016 * The PLL needs to be enabled with a valid divider
9017 * configuration, otherwise accessing DSI registers will hang
9018 * the machine. See BSpec North Display Engine
9019 * registers/MIPI[BXT]. We can break out here early, since we
9020 * need the same DSI PLL to be enabled for both DSI ports.
9021 */
9022 if (!intel_dsi_pll_is_enabled(dev_priv))
9023 break;
9024
9025 /* XXX: this works for video mode only */
9026 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9027 if (!(tmp & DPI_ENABLE))
9028 continue;
9029
9030 tmp = I915_READ(MIPI_CTRL(port));
9031 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9032 continue;
9033
9034 pipe_config->cpu_transcoder = cpu_transcoder;
9035 break;
9036 }
9037
9038 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9039 }
9040
9041 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9042 struct intel_crtc_state *pipe_config)
9043 {
9044 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9045 struct intel_shared_dpll *pll;
9046 enum port port;
9047 uint32_t tmp;
9048
9049 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9050
9051 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9052
9053 if (IS_CANNONLAKE(dev_priv))
9054 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9055 else if (IS_GEN9_BC(dev_priv))
9056 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9057 else if (IS_GEN9_LP(dev_priv))
9058 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9059 else
9060 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9061
9062 pll = pipe_config->shared_dpll;
9063 if (pll) {
9064 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9065 &pipe_config->dpll_hw_state));
9066 }
9067
9068 /*
9069 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9070 * DDI E. So just check whether this pipe is wired to DDI E and whether
9071 * the PCH transcoder is on.
9072 */
9073 if (INTEL_GEN(dev_priv) < 9 &&
9074 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9075 pipe_config->has_pch_encoder = true;
9076
9077 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9078 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9079 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9080
9081 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9082 }
9083 }
9084
9085 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9086 struct intel_crtc_state *pipe_config)
9087 {
9088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9089 enum intel_display_power_domain power_domain;
9090 u64 power_domain_mask;
9091 bool active;
9092
9093 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9094 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9095 return false;
9096 power_domain_mask = BIT_ULL(power_domain);
9097
9098 pipe_config->shared_dpll = NULL;
9099
9100 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9101
9102 if (IS_GEN9_LP(dev_priv) &&
9103 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9104 WARN_ON(active);
9105 active = true;
9106 }
9107
9108 if (!active)
9109 goto out;
9110
9111 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9112 haswell_get_ddi_port_state(crtc, pipe_config);
9113 intel_get_pipe_timings(crtc, pipe_config);
9114 }
9115
9116 intel_get_pipe_src_size(crtc, pipe_config);
9117
9118 pipe_config->gamma_mode =
9119 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9120
9121 if (INTEL_GEN(dev_priv) >= 9) {
9122 intel_crtc_init_scalers(crtc, pipe_config);
9123
9124 pipe_config->scaler_state.scaler_id = -1;
9125 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9126 }
9127
9128 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9129 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9130 power_domain_mask |= BIT_ULL(power_domain);
9131 if (INTEL_GEN(dev_priv) >= 9)
9132 skylake_get_pfit_config(crtc, pipe_config);
9133 else
9134 ironlake_get_pfit_config(crtc, pipe_config);
9135 }
9136
9137 if (IS_HASWELL(dev_priv))
9138 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9139 (I915_READ(IPS_CTL) & IPS_ENABLE);
9140
9141 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9142 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9143 pipe_config->pixel_multiplier =
9144 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9145 } else {
9146 pipe_config->pixel_multiplier = 1;
9147 }
9148
9149 out:
9150 for_each_power_domain(power_domain, power_domain_mask)
9151 intel_display_power_put(dev_priv, power_domain);
9152
9153 return active;
9154 }
9155
9156 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9157 {
9158 struct drm_i915_private *dev_priv =
9159 to_i915(plane_state->base.plane->dev);
9160 const struct drm_framebuffer *fb = plane_state->base.fb;
9161 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9162 u32 base;
9163
9164 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9165 base = obj->phys_handle->busaddr;
9166 else
9167 base = intel_plane_ggtt_offset(plane_state);
9168
9169 base += plane_state->main.offset;
9170
9171 /* ILK+ do this automagically */
9172 if (HAS_GMCH_DISPLAY(dev_priv) &&
9173 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9174 base += (plane_state->base.crtc_h *
9175 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9176
9177 return base;
9178 }
9179
9180 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9181 {
9182 int x = plane_state->base.crtc_x;
9183 int y = plane_state->base.crtc_y;
9184 u32 pos = 0;
9185
9186 if (x < 0) {
9187 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9188 x = -x;
9189 }
9190 pos |= x << CURSOR_X_SHIFT;
9191
9192 if (y < 0) {
9193 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9194 y = -y;
9195 }
9196 pos |= y << CURSOR_Y_SHIFT;
9197
9198 return pos;
9199 }
9200
9201 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9202 {
9203 const struct drm_mode_config *config =
9204 &plane_state->base.plane->dev->mode_config;
9205 int width = plane_state->base.crtc_w;
9206 int height = plane_state->base.crtc_h;
9207
9208 return width > 0 && width <= config->cursor_width &&
9209 height > 0 && height <= config->cursor_height;
9210 }
9211
9212 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9213 struct intel_plane_state *plane_state)
9214 {
9215 const struct drm_framebuffer *fb = plane_state->base.fb;
9216 int src_x, src_y;
9217 u32 offset;
9218 int ret;
9219
9220 ret = drm_plane_helper_check_state(&plane_state->base,
9221 &plane_state->clip,
9222 DRM_PLANE_HELPER_NO_SCALING,
9223 DRM_PLANE_HELPER_NO_SCALING,
9224 true, true);
9225 if (ret)
9226 return ret;
9227
9228 if (!fb)
9229 return 0;
9230
9231 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9232 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9233 return -EINVAL;
9234 }
9235
9236 src_x = plane_state->base.src_x >> 16;
9237 src_y = plane_state->base.src_y >> 16;
9238
9239 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9240 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9241
9242 if (src_x != 0 || src_y != 0) {
9243 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9244 return -EINVAL;
9245 }
9246
9247 plane_state->main.offset = offset;
9248
9249 return 0;
9250 }
9251
9252 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9253 const struct intel_plane_state *plane_state)
9254 {
9255 const struct drm_framebuffer *fb = plane_state->base.fb;
9256
9257 return CURSOR_ENABLE |
9258 CURSOR_GAMMA_ENABLE |
9259 CURSOR_FORMAT_ARGB |
9260 CURSOR_STRIDE(fb->pitches[0]);
9261 }
9262
9263 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9264 {
9265 int width = plane_state->base.crtc_w;
9266
9267 /*
9268 * 845g/865g are only limited by the width of their cursors,
9269 * the height is arbitrary up to the precision of the register.
9270 */
9271 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9272 }
9273
9274 static int i845_check_cursor(struct intel_plane *plane,
9275 struct intel_crtc_state *crtc_state,
9276 struct intel_plane_state *plane_state)
9277 {
9278 const struct drm_framebuffer *fb = plane_state->base.fb;
9279 int ret;
9280
9281 ret = intel_check_cursor(crtc_state, plane_state);
9282 if (ret)
9283 return ret;
9284
9285 /* if we want to turn off the cursor ignore width and height */
9286 if (!fb)
9287 return 0;
9288
9289 /* Check for which cursor types we support */
9290 if (!i845_cursor_size_ok(plane_state)) {
9291 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9292 plane_state->base.crtc_w,
9293 plane_state->base.crtc_h);
9294 return -EINVAL;
9295 }
9296
9297 switch (fb->pitches[0]) {
9298 case 256:
9299 case 512:
9300 case 1024:
9301 case 2048:
9302 break;
9303 default:
9304 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9305 fb->pitches[0]);
9306 return -EINVAL;
9307 }
9308
9309 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9310
9311 return 0;
9312 }
9313
9314 static void i845_update_cursor(struct intel_plane *plane,
9315 const struct intel_crtc_state *crtc_state,
9316 const struct intel_plane_state *plane_state)
9317 {
9318 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9319 u32 cntl = 0, base = 0, pos = 0, size = 0;
9320 unsigned long irqflags;
9321
9322 if (plane_state && plane_state->base.visible) {
9323 unsigned int width = plane_state->base.crtc_w;
9324 unsigned int height = plane_state->base.crtc_h;
9325
9326 cntl = plane_state->ctl;
9327 size = (height << 12) | width;
9328
9329 base = intel_cursor_base(plane_state);
9330 pos = intel_cursor_position(plane_state);
9331 }
9332
9333 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9334
9335 /* On these chipsets we can only modify the base/size/stride
9336 * whilst the cursor is disabled.
9337 */
9338 if (plane->cursor.base != base ||
9339 plane->cursor.size != size ||
9340 plane->cursor.cntl != cntl) {
9341 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9342 I915_WRITE_FW(CURBASE(PIPE_A), base);
9343 I915_WRITE_FW(CURSIZE, size);
9344 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9345 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9346
9347 plane->cursor.base = base;
9348 plane->cursor.size = size;
9349 plane->cursor.cntl = cntl;
9350 } else {
9351 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9352 }
9353
9354 POSTING_READ_FW(CURCNTR(PIPE_A));
9355
9356 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9357 }
9358
9359 static void i845_disable_cursor(struct intel_plane *plane,
9360 struct intel_crtc *crtc)
9361 {
9362 i845_update_cursor(plane, NULL, NULL);
9363 }
9364
9365 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9366 const struct intel_plane_state *plane_state)
9367 {
9368 struct drm_i915_private *dev_priv =
9369 to_i915(plane_state->base.plane->dev);
9370 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9371 u32 cntl;
9372
9373 cntl = MCURSOR_GAMMA_ENABLE;
9374
9375 if (HAS_DDI(dev_priv))
9376 cntl |= CURSOR_PIPE_CSC_ENABLE;
9377
9378 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9379
9380 switch (plane_state->base.crtc_w) {
9381 case 64:
9382 cntl |= CURSOR_MODE_64_ARGB_AX;
9383 break;
9384 case 128:
9385 cntl |= CURSOR_MODE_128_ARGB_AX;
9386 break;
9387 case 256:
9388 cntl |= CURSOR_MODE_256_ARGB_AX;
9389 break;
9390 default:
9391 MISSING_CASE(plane_state->base.crtc_w);
9392 return 0;
9393 }
9394
9395 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9396 cntl |= CURSOR_ROTATE_180;
9397
9398 return cntl;
9399 }
9400
9401 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9402 {
9403 struct drm_i915_private *dev_priv =
9404 to_i915(plane_state->base.plane->dev);
9405 int width = plane_state->base.crtc_w;
9406 int height = plane_state->base.crtc_h;
9407
9408 if (!intel_cursor_size_ok(plane_state))
9409 return false;
9410
9411 /* Cursor width is limited to a few power-of-two sizes */
9412 switch (width) {
9413 case 256:
9414 case 128:
9415 case 64:
9416 break;
9417 default:
9418 return false;
9419 }
9420
9421 /*
9422 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9423 * height from 8 lines up to the cursor width, when the
9424 * cursor is not rotated. Everything else requires square
9425 * cursors.
9426 */
9427 if (HAS_CUR_FBC(dev_priv) &&
9428 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9429 if (height < 8 || height > width)
9430 return false;
9431 } else {
9432 if (height != width)
9433 return false;
9434 }
9435
9436 return true;
9437 }
9438
9439 static int i9xx_check_cursor(struct intel_plane *plane,
9440 struct intel_crtc_state *crtc_state,
9441 struct intel_plane_state *plane_state)
9442 {
9443 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9444 const struct drm_framebuffer *fb = plane_state->base.fb;
9445 enum pipe pipe = plane->pipe;
9446 int ret;
9447
9448 ret = intel_check_cursor(crtc_state, plane_state);
9449 if (ret)
9450 return ret;
9451
9452 /* if we want to turn off the cursor ignore width and height */
9453 if (!fb)
9454 return 0;
9455
9456 /* Check for which cursor types we support */
9457 if (!i9xx_cursor_size_ok(plane_state)) {
9458 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9459 plane_state->base.crtc_w,
9460 plane_state->base.crtc_h);
9461 return -EINVAL;
9462 }
9463
9464 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9465 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9466 fb->pitches[0], plane_state->base.crtc_w);
9467 return -EINVAL;
9468 }
9469
9470 /*
9471 * There's something wrong with the cursor on CHV pipe C.
9472 * If it straddles the left edge of the screen then
9473 * moving it away from the edge or disabling it often
9474 * results in a pipe underrun, and often that can lead to
9475 * dead pipe (constant underrun reported, and it scans
9476 * out just a solid color). To recover from that, the
9477 * display power well must be turned off and on again.
9478 * Refuse the put the cursor into that compromised position.
9479 */
9480 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9481 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9482 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9483 return -EINVAL;
9484 }
9485
9486 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9487
9488 return 0;
9489 }
9490
9491 static void i9xx_update_cursor(struct intel_plane *plane,
9492 const struct intel_crtc_state *crtc_state,
9493 const struct intel_plane_state *plane_state)
9494 {
9495 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9496 enum pipe pipe = plane->pipe;
9497 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9498 unsigned long irqflags;
9499
9500 if (plane_state && plane_state->base.visible) {
9501 cntl = plane_state->ctl;
9502
9503 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9504 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9505
9506 base = intel_cursor_base(plane_state);
9507 pos = intel_cursor_position(plane_state);
9508 }
9509
9510 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9511
9512 /*
9513 * On some platforms writing CURCNTR first will also
9514 * cause CURPOS to be armed by the CURBASE write.
9515 * Without the CURCNTR write the CURPOS write would
9516 * arm itself. Thus we always start the full update
9517 * with a CURCNTR write.
9518 *
9519 * On other platforms CURPOS always requires the
9520 * CURBASE write to arm the update. Additonally
9521 * a write to any of the cursor register will cancel
9522 * an already armed cursor update. Thus leaving out
9523 * the CURBASE write after CURPOS could lead to a
9524 * cursor that doesn't appear to move, or even change
9525 * shape. Thus we always write CURBASE.
9526 *
9527 * CURCNTR and CUR_FBC_CTL are always
9528 * armed by the CURBASE write only.
9529 */
9530 if (plane->cursor.base != base ||
9531 plane->cursor.size != fbc_ctl ||
9532 plane->cursor.cntl != cntl) {
9533 I915_WRITE_FW(CURCNTR(pipe), cntl);
9534 if (HAS_CUR_FBC(dev_priv))
9535 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9536 I915_WRITE_FW(CURPOS(pipe), pos);
9537 I915_WRITE_FW(CURBASE(pipe), base);
9538
9539 plane->cursor.base = base;
9540 plane->cursor.size = fbc_ctl;
9541 plane->cursor.cntl = cntl;
9542 } else {
9543 I915_WRITE_FW(CURPOS(pipe), pos);
9544 I915_WRITE_FW(CURBASE(pipe), base);
9545 }
9546
9547 POSTING_READ_FW(CURBASE(pipe));
9548
9549 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9550 }
9551
9552 static void i9xx_disable_cursor(struct intel_plane *plane,
9553 struct intel_crtc *crtc)
9554 {
9555 i9xx_update_cursor(plane, NULL, NULL);
9556 }
9557
9558
9559 /* VESA 640x480x72Hz mode to set on the pipe */
9560 static struct drm_display_mode load_detect_mode = {
9561 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9562 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9563 };
9564
9565 struct drm_framebuffer *
9566 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9567 struct drm_mode_fb_cmd2 *mode_cmd)
9568 {
9569 struct intel_framebuffer *intel_fb;
9570 int ret;
9571
9572 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9573 if (!intel_fb)
9574 return ERR_PTR(-ENOMEM);
9575
9576 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9577 if (ret)
9578 goto err;
9579
9580 return &intel_fb->base;
9581
9582 err:
9583 kfree(intel_fb);
9584 return ERR_PTR(ret);
9585 }
9586
9587 static u32
9588 intel_framebuffer_pitch_for_width(int width, int bpp)
9589 {
9590 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9591 return ALIGN(pitch, 64);
9592 }
9593
9594 static u32
9595 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9596 {
9597 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9598 return PAGE_ALIGN(pitch * mode->vdisplay);
9599 }
9600
9601 static struct drm_framebuffer *
9602 intel_framebuffer_create_for_mode(struct drm_device *dev,
9603 struct drm_display_mode *mode,
9604 int depth, int bpp)
9605 {
9606 struct drm_framebuffer *fb;
9607 struct drm_i915_gem_object *obj;
9608 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9609
9610 obj = i915_gem_object_create(to_i915(dev),
9611 intel_framebuffer_size_for_mode(mode, bpp));
9612 if (IS_ERR(obj))
9613 return ERR_CAST(obj);
9614
9615 mode_cmd.width = mode->hdisplay;
9616 mode_cmd.height = mode->vdisplay;
9617 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9618 bpp);
9619 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9620
9621 fb = intel_framebuffer_create(obj, &mode_cmd);
9622 if (IS_ERR(fb))
9623 i915_gem_object_put(obj);
9624
9625 return fb;
9626 }
9627
9628 static struct drm_framebuffer *
9629 mode_fits_in_fbdev(struct drm_device *dev,
9630 struct drm_display_mode *mode)
9631 {
9632 #ifdef CONFIG_DRM_FBDEV_EMULATION
9633 struct drm_i915_private *dev_priv = to_i915(dev);
9634 struct drm_i915_gem_object *obj;
9635 struct drm_framebuffer *fb;
9636
9637 if (!dev_priv->fbdev)
9638 return NULL;
9639
9640 if (!dev_priv->fbdev->fb)
9641 return NULL;
9642
9643 obj = dev_priv->fbdev->fb->obj;
9644 BUG_ON(!obj);
9645
9646 fb = &dev_priv->fbdev->fb->base;
9647 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9648 fb->format->cpp[0] * 8))
9649 return NULL;
9650
9651 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9652 return NULL;
9653
9654 drm_framebuffer_reference(fb);
9655 return fb;
9656 #else
9657 return NULL;
9658 #endif
9659 }
9660
9661 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9662 struct drm_crtc *crtc,
9663 struct drm_display_mode *mode,
9664 struct drm_framebuffer *fb,
9665 int x, int y)
9666 {
9667 struct drm_plane_state *plane_state;
9668 int hdisplay, vdisplay;
9669 int ret;
9670
9671 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9672 if (IS_ERR(plane_state))
9673 return PTR_ERR(plane_state);
9674
9675 if (mode)
9676 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9677 else
9678 hdisplay = vdisplay = 0;
9679
9680 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9681 if (ret)
9682 return ret;
9683 drm_atomic_set_fb_for_plane(plane_state, fb);
9684 plane_state->crtc_x = 0;
9685 plane_state->crtc_y = 0;
9686 plane_state->crtc_w = hdisplay;
9687 plane_state->crtc_h = vdisplay;
9688 plane_state->src_x = x << 16;
9689 plane_state->src_y = y << 16;
9690 plane_state->src_w = hdisplay << 16;
9691 plane_state->src_h = vdisplay << 16;
9692
9693 return 0;
9694 }
9695
9696 int intel_get_load_detect_pipe(struct drm_connector *connector,
9697 struct drm_display_mode *mode,
9698 struct intel_load_detect_pipe *old,
9699 struct drm_modeset_acquire_ctx *ctx)
9700 {
9701 struct intel_crtc *intel_crtc;
9702 struct intel_encoder *intel_encoder =
9703 intel_attached_encoder(connector);
9704 struct drm_crtc *possible_crtc;
9705 struct drm_encoder *encoder = &intel_encoder->base;
9706 struct drm_crtc *crtc = NULL;
9707 struct drm_device *dev = encoder->dev;
9708 struct drm_i915_private *dev_priv = to_i915(dev);
9709 struct drm_framebuffer *fb;
9710 struct drm_mode_config *config = &dev->mode_config;
9711 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9712 struct drm_connector_state *connector_state;
9713 struct intel_crtc_state *crtc_state;
9714 int ret, i = -1;
9715
9716 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9717 connector->base.id, connector->name,
9718 encoder->base.id, encoder->name);
9719
9720 old->restore_state = NULL;
9721
9722 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9723
9724 /*
9725 * Algorithm gets a little messy:
9726 *
9727 * - if the connector already has an assigned crtc, use it (but make
9728 * sure it's on first)
9729 *
9730 * - try to find the first unused crtc that can drive this connector,
9731 * and use that if we find one
9732 */
9733
9734 /* See if we already have a CRTC for this connector */
9735 if (connector->state->crtc) {
9736 crtc = connector->state->crtc;
9737
9738 ret = drm_modeset_lock(&crtc->mutex, ctx);
9739 if (ret)
9740 goto fail;
9741
9742 /* Make sure the crtc and connector are running */
9743 goto found;
9744 }
9745
9746 /* Find an unused one (if possible) */
9747 for_each_crtc(dev, possible_crtc) {
9748 i++;
9749 if (!(encoder->possible_crtcs & (1 << i)))
9750 continue;
9751
9752 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9753 if (ret)
9754 goto fail;
9755
9756 if (possible_crtc->state->enable) {
9757 drm_modeset_unlock(&possible_crtc->mutex);
9758 continue;
9759 }
9760
9761 crtc = possible_crtc;
9762 break;
9763 }
9764
9765 /*
9766 * If we didn't find an unused CRTC, don't use any.
9767 */
9768 if (!crtc) {
9769 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9770 ret = -ENODEV;
9771 goto fail;
9772 }
9773
9774 found:
9775 intel_crtc = to_intel_crtc(crtc);
9776
9777 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9778 if (ret)
9779 goto fail;
9780
9781 state = drm_atomic_state_alloc(dev);
9782 restore_state = drm_atomic_state_alloc(dev);
9783 if (!state || !restore_state) {
9784 ret = -ENOMEM;
9785 goto fail;
9786 }
9787
9788 state->acquire_ctx = ctx;
9789 restore_state->acquire_ctx = ctx;
9790
9791 connector_state = drm_atomic_get_connector_state(state, connector);
9792 if (IS_ERR(connector_state)) {
9793 ret = PTR_ERR(connector_state);
9794 goto fail;
9795 }
9796
9797 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9798 if (ret)
9799 goto fail;
9800
9801 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9802 if (IS_ERR(crtc_state)) {
9803 ret = PTR_ERR(crtc_state);
9804 goto fail;
9805 }
9806
9807 crtc_state->base.active = crtc_state->base.enable = true;
9808
9809 if (!mode)
9810 mode = &load_detect_mode;
9811
9812 /* We need a framebuffer large enough to accommodate all accesses
9813 * that the plane may generate whilst we perform load detection.
9814 * We can not rely on the fbcon either being present (we get called
9815 * during its initialisation to detect all boot displays, or it may
9816 * not even exist) or that it is large enough to satisfy the
9817 * requested mode.
9818 */
9819 fb = mode_fits_in_fbdev(dev, mode);
9820 if (fb == NULL) {
9821 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9822 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9823 } else
9824 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9825 if (IS_ERR(fb)) {
9826 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9827 ret = PTR_ERR(fb);
9828 goto fail;
9829 }
9830
9831 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9832 if (ret)
9833 goto fail;
9834
9835 drm_framebuffer_unreference(fb);
9836
9837 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9838 if (ret)
9839 goto fail;
9840
9841 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9842 if (!ret)
9843 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9844 if (!ret)
9845 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9846 if (ret) {
9847 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9848 goto fail;
9849 }
9850
9851 ret = drm_atomic_commit(state);
9852 if (ret) {
9853 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9854 goto fail;
9855 }
9856
9857 old->restore_state = restore_state;
9858 drm_atomic_state_put(state);
9859
9860 /* let the connector get through one full cycle before testing */
9861 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9862 return true;
9863
9864 fail:
9865 if (state) {
9866 drm_atomic_state_put(state);
9867 state = NULL;
9868 }
9869 if (restore_state) {
9870 drm_atomic_state_put(restore_state);
9871 restore_state = NULL;
9872 }
9873
9874 if (ret == -EDEADLK)
9875 return ret;
9876
9877 return false;
9878 }
9879
9880 void intel_release_load_detect_pipe(struct drm_connector *connector,
9881 struct intel_load_detect_pipe *old,
9882 struct drm_modeset_acquire_ctx *ctx)
9883 {
9884 struct intel_encoder *intel_encoder =
9885 intel_attached_encoder(connector);
9886 struct drm_encoder *encoder = &intel_encoder->base;
9887 struct drm_atomic_state *state = old->restore_state;
9888 int ret;
9889
9890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9891 connector->base.id, connector->name,
9892 encoder->base.id, encoder->name);
9893
9894 if (!state)
9895 return;
9896
9897 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9898 if (ret)
9899 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9900 drm_atomic_state_put(state);
9901 }
9902
9903 static int i9xx_pll_refclk(struct drm_device *dev,
9904 const struct intel_crtc_state *pipe_config)
9905 {
9906 struct drm_i915_private *dev_priv = to_i915(dev);
9907 u32 dpll = pipe_config->dpll_hw_state.dpll;
9908
9909 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9910 return dev_priv->vbt.lvds_ssc_freq;
9911 else if (HAS_PCH_SPLIT(dev_priv))
9912 return 120000;
9913 else if (!IS_GEN2(dev_priv))
9914 return 96000;
9915 else
9916 return 48000;
9917 }
9918
9919 /* Returns the clock of the currently programmed mode of the given pipe. */
9920 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9921 struct intel_crtc_state *pipe_config)
9922 {
9923 struct drm_device *dev = crtc->base.dev;
9924 struct drm_i915_private *dev_priv = to_i915(dev);
9925 int pipe = pipe_config->cpu_transcoder;
9926 u32 dpll = pipe_config->dpll_hw_state.dpll;
9927 u32 fp;
9928 struct dpll clock;
9929 int port_clock;
9930 int refclk = i9xx_pll_refclk(dev, pipe_config);
9931
9932 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9933 fp = pipe_config->dpll_hw_state.fp0;
9934 else
9935 fp = pipe_config->dpll_hw_state.fp1;
9936
9937 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9938 if (IS_PINEVIEW(dev_priv)) {
9939 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9940 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9941 } else {
9942 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9943 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9944 }
9945
9946 if (!IS_GEN2(dev_priv)) {
9947 if (IS_PINEVIEW(dev_priv))
9948 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9949 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9950 else
9951 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9952 DPLL_FPA01_P1_POST_DIV_SHIFT);
9953
9954 switch (dpll & DPLL_MODE_MASK) {
9955 case DPLLB_MODE_DAC_SERIAL:
9956 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9957 5 : 10;
9958 break;
9959 case DPLLB_MODE_LVDS:
9960 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9961 7 : 14;
9962 break;
9963 default:
9964 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9965 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9966 return;
9967 }
9968
9969 if (IS_PINEVIEW(dev_priv))
9970 port_clock = pnv_calc_dpll_params(refclk, &clock);
9971 else
9972 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9973 } else {
9974 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9975 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9976
9977 if (is_lvds) {
9978 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9979 DPLL_FPA01_P1_POST_DIV_SHIFT);
9980
9981 if (lvds & LVDS_CLKB_POWER_UP)
9982 clock.p2 = 7;
9983 else
9984 clock.p2 = 14;
9985 } else {
9986 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9987 clock.p1 = 2;
9988 else {
9989 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9990 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9991 }
9992 if (dpll & PLL_P2_DIVIDE_BY_4)
9993 clock.p2 = 4;
9994 else
9995 clock.p2 = 2;
9996 }
9997
9998 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9999 }
10000
10001 /*
10002 * This value includes pixel_multiplier. We will use
10003 * port_clock to compute adjusted_mode.crtc_clock in the
10004 * encoder's get_config() function.
10005 */
10006 pipe_config->port_clock = port_clock;
10007 }
10008
10009 int intel_dotclock_calculate(int link_freq,
10010 const struct intel_link_m_n *m_n)
10011 {
10012 /*
10013 * The calculation for the data clock is:
10014 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10015 * But we want to avoid losing precison if possible, so:
10016 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10017 *
10018 * and the link clock is simpler:
10019 * link_clock = (m * link_clock) / n
10020 */
10021
10022 if (!m_n->link_n)
10023 return 0;
10024
10025 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10026 }
10027
10028 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10029 struct intel_crtc_state *pipe_config)
10030 {
10031 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10032
10033 /* read out port_clock from the DPLL */
10034 i9xx_crtc_clock_get(crtc, pipe_config);
10035
10036 /*
10037 * In case there is an active pipe without active ports,
10038 * we may need some idea for the dotclock anyway.
10039 * Calculate one based on the FDI configuration.
10040 */
10041 pipe_config->base.adjusted_mode.crtc_clock =
10042 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10043 &pipe_config->fdi_m_n);
10044 }
10045
10046 /** Returns the currently programmed mode of the given pipe. */
10047 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10048 struct drm_crtc *crtc)
10049 {
10050 struct drm_i915_private *dev_priv = to_i915(dev);
10051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10052 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10053 struct drm_display_mode *mode;
10054 struct intel_crtc_state *pipe_config;
10055 int htot = I915_READ(HTOTAL(cpu_transcoder));
10056 int hsync = I915_READ(HSYNC(cpu_transcoder));
10057 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10058 int vsync = I915_READ(VSYNC(cpu_transcoder));
10059 enum pipe pipe = intel_crtc->pipe;
10060
10061 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10062 if (!mode)
10063 return NULL;
10064
10065 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10066 if (!pipe_config) {
10067 kfree(mode);
10068 return NULL;
10069 }
10070
10071 /*
10072 * Construct a pipe_config sufficient for getting the clock info
10073 * back out of crtc_clock_get.
10074 *
10075 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10076 * to use a real value here instead.
10077 */
10078 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10079 pipe_config->pixel_multiplier = 1;
10080 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10081 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10082 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10083 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10084
10085 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10086 mode->hdisplay = (htot & 0xffff) + 1;
10087 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10088 mode->hsync_start = (hsync & 0xffff) + 1;
10089 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10090 mode->vdisplay = (vtot & 0xffff) + 1;
10091 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10092 mode->vsync_start = (vsync & 0xffff) + 1;
10093 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10094
10095 drm_mode_set_name(mode);
10096
10097 kfree(pipe_config);
10098
10099 return mode;
10100 }
10101
10102 static void intel_crtc_destroy(struct drm_crtc *crtc)
10103 {
10104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10105 struct drm_device *dev = crtc->dev;
10106 struct intel_flip_work *work;
10107
10108 spin_lock_irq(&dev->event_lock);
10109 work = intel_crtc->flip_work;
10110 intel_crtc->flip_work = NULL;
10111 spin_unlock_irq(&dev->event_lock);
10112
10113 if (work) {
10114 cancel_work_sync(&work->mmio_work);
10115 cancel_work_sync(&work->unpin_work);
10116 kfree(work);
10117 }
10118
10119 drm_crtc_cleanup(crtc);
10120
10121 kfree(intel_crtc);
10122 }
10123
10124 /* Is 'a' after or equal to 'b'? */
10125 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10126 {
10127 return !((a - b) & 0x80000000);
10128 }
10129
10130 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10131 struct intel_flip_work *work)
10132 {
10133 struct drm_device *dev = crtc->base.dev;
10134 struct drm_i915_private *dev_priv = to_i915(dev);
10135
10136 if (abort_flip_on_reset(crtc))
10137 return true;
10138
10139 /*
10140 * The relevant registers doen't exist on pre-ctg.
10141 * As the flip done interrupt doesn't trigger for mmio
10142 * flips on gmch platforms, a flip count check isn't
10143 * really needed there. But since ctg has the registers,
10144 * include it in the check anyway.
10145 */
10146 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10147 return true;
10148
10149 /*
10150 * BDW signals flip done immediately if the plane
10151 * is disabled, even if the plane enable is already
10152 * armed to occur at the next vblank :(
10153 */
10154
10155 /*
10156 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10157 * used the same base address. In that case the mmio flip might
10158 * have completed, but the CS hasn't even executed the flip yet.
10159 *
10160 * A flip count check isn't enough as the CS might have updated
10161 * the base address just after start of vblank, but before we
10162 * managed to process the interrupt. This means we'd complete the
10163 * CS flip too soon.
10164 *
10165 * Combining both checks should get us a good enough result. It may
10166 * still happen that the CS flip has been executed, but has not
10167 * yet actually completed. But in case the base address is the same
10168 * anyway, we don't really care.
10169 */
10170 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10171 crtc->flip_work->gtt_offset &&
10172 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10173 crtc->flip_work->flip_count);
10174 }
10175
10176 static bool
10177 __pageflip_finished_mmio(struct intel_crtc *crtc,
10178 struct intel_flip_work *work)
10179 {
10180 /*
10181 * MMIO work completes when vblank is different from
10182 * flip_queued_vblank.
10183 *
10184 * Reset counter value doesn't matter, this is handled by
10185 * i915_wait_request finishing early, so no need to handle
10186 * reset here.
10187 */
10188 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10189 }
10190
10191
10192 static bool pageflip_finished(struct intel_crtc *crtc,
10193 struct intel_flip_work *work)
10194 {
10195 if (!atomic_read(&work->pending))
10196 return false;
10197
10198 smp_rmb();
10199
10200 if (is_mmio_work(work))
10201 return __pageflip_finished_mmio(crtc, work);
10202 else
10203 return __pageflip_finished_cs(crtc, work);
10204 }
10205
10206 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10207 {
10208 struct drm_device *dev = &dev_priv->drm;
10209 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10210 struct intel_flip_work *work;
10211 unsigned long flags;
10212
10213 /* Ignore early vblank irqs */
10214 if (!crtc)
10215 return;
10216
10217 /*
10218 * This is called both by irq handlers and the reset code (to complete
10219 * lost pageflips) so needs the full irqsave spinlocks.
10220 */
10221 spin_lock_irqsave(&dev->event_lock, flags);
10222 work = crtc->flip_work;
10223
10224 if (work != NULL &&
10225 !is_mmio_work(work) &&
10226 pageflip_finished(crtc, work))
10227 page_flip_completed(crtc);
10228
10229 spin_unlock_irqrestore(&dev->event_lock, flags);
10230 }
10231
10232 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10233 {
10234 struct drm_device *dev = &dev_priv->drm;
10235 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10236 struct intel_flip_work *work;
10237 unsigned long flags;
10238
10239 /* Ignore early vblank irqs */
10240 if (!crtc)
10241 return;
10242
10243 /*
10244 * This is called both by irq handlers and the reset code (to complete
10245 * lost pageflips) so needs the full irqsave spinlocks.
10246 */
10247 spin_lock_irqsave(&dev->event_lock, flags);
10248 work = crtc->flip_work;
10249
10250 if (work != NULL &&
10251 is_mmio_work(work) &&
10252 pageflip_finished(crtc, work))
10253 page_flip_completed(crtc);
10254
10255 spin_unlock_irqrestore(&dev->event_lock, flags);
10256 }
10257
10258 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10259 struct intel_flip_work *work)
10260 {
10261 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10262
10263 /* Ensure that the work item is consistent when activating it ... */
10264 smp_mb__before_atomic();
10265 atomic_set(&work->pending, 1);
10266 }
10267
10268 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10269 struct intel_crtc *intel_crtc,
10270 struct intel_flip_work *work)
10271 {
10272 u32 addr, vblank;
10273
10274 if (!atomic_read(&work->pending))
10275 return false;
10276
10277 smp_rmb();
10278
10279 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10280 if (work->flip_ready_vblank == 0) {
10281 if (work->flip_queued_req &&
10282 !i915_gem_request_completed(work->flip_queued_req))
10283 return false;
10284
10285 work->flip_ready_vblank = vblank;
10286 }
10287
10288 if (vblank - work->flip_ready_vblank < 3)
10289 return false;
10290
10291 /* Potential stall - if we see that the flip has happened,
10292 * assume a missed interrupt. */
10293 if (INTEL_GEN(dev_priv) >= 4)
10294 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10295 else
10296 addr = I915_READ(DSPADDR(intel_crtc->plane));
10297
10298 /* There is a potential issue here with a false positive after a flip
10299 * to the same address. We could address this by checking for a
10300 * non-incrementing frame counter.
10301 */
10302 return addr == work->gtt_offset;
10303 }
10304
10305 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10306 {
10307 struct drm_device *dev = &dev_priv->drm;
10308 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10309 struct intel_flip_work *work;
10310
10311 WARN_ON(!in_interrupt());
10312
10313 if (crtc == NULL)
10314 return;
10315
10316 spin_lock(&dev->event_lock);
10317 work = crtc->flip_work;
10318
10319 if (work != NULL && !is_mmio_work(work) &&
10320 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10321 WARN_ONCE(1,
10322 "Kicking stuck page flip: queued at %d, now %d\n",
10323 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10324 page_flip_completed(crtc);
10325 work = NULL;
10326 }
10327
10328 if (work != NULL && !is_mmio_work(work) &&
10329 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10330 intel_queue_rps_boost_for_request(work->flip_queued_req);
10331 spin_unlock(&dev->event_lock);
10332 }
10333
10334 /**
10335 * intel_wm_need_update - Check whether watermarks need updating
10336 * @plane: drm plane
10337 * @state: new plane state
10338 *
10339 * Check current plane state versus the new one to determine whether
10340 * watermarks need to be recalculated.
10341 *
10342 * Returns true or false.
10343 */
10344 static bool intel_wm_need_update(struct drm_plane *plane,
10345 struct drm_plane_state *state)
10346 {
10347 struct intel_plane_state *new = to_intel_plane_state(state);
10348 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10349
10350 /* Update watermarks on tiling or size changes. */
10351 if (new->base.visible != cur->base.visible)
10352 return true;
10353
10354 if (!cur->base.fb || !new->base.fb)
10355 return false;
10356
10357 if (cur->base.fb->modifier != new->base.fb->modifier ||
10358 cur->base.rotation != new->base.rotation ||
10359 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10360 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10361 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10362 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10363 return true;
10364
10365 return false;
10366 }
10367
10368 static bool needs_scaling(struct intel_plane_state *state)
10369 {
10370 int src_w = drm_rect_width(&state->base.src) >> 16;
10371 int src_h = drm_rect_height(&state->base.src) >> 16;
10372 int dst_w = drm_rect_width(&state->base.dst);
10373 int dst_h = drm_rect_height(&state->base.dst);
10374
10375 return (src_w != dst_w || src_h != dst_h);
10376 }
10377
10378 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10379 struct drm_plane_state *plane_state)
10380 {
10381 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10382 struct drm_crtc *crtc = crtc_state->crtc;
10383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10384 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10385 struct drm_device *dev = crtc->dev;
10386 struct drm_i915_private *dev_priv = to_i915(dev);
10387 struct intel_plane_state *old_plane_state =
10388 to_intel_plane_state(plane->base.state);
10389 bool mode_changed = needs_modeset(crtc_state);
10390 bool was_crtc_enabled = crtc->state->active;
10391 bool is_crtc_enabled = crtc_state->active;
10392 bool turn_off, turn_on, visible, was_visible;
10393 struct drm_framebuffer *fb = plane_state->fb;
10394 int ret;
10395
10396 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10397 ret = skl_update_scaler_plane(
10398 to_intel_crtc_state(crtc_state),
10399 to_intel_plane_state(plane_state));
10400 if (ret)
10401 return ret;
10402 }
10403
10404 was_visible = old_plane_state->base.visible;
10405 visible = plane_state->visible;
10406
10407 if (!was_crtc_enabled && WARN_ON(was_visible))
10408 was_visible = false;
10409
10410 /*
10411 * Visibility is calculated as if the crtc was on, but
10412 * after scaler setup everything depends on it being off
10413 * when the crtc isn't active.
10414 *
10415 * FIXME this is wrong for watermarks. Watermarks should also
10416 * be computed as if the pipe would be active. Perhaps move
10417 * per-plane wm computation to the .check_plane() hook, and
10418 * only combine the results from all planes in the current place?
10419 */
10420 if (!is_crtc_enabled) {
10421 plane_state->visible = visible = false;
10422 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10423 }
10424
10425 if (!was_visible && !visible)
10426 return 0;
10427
10428 if (fb != old_plane_state->base.fb)
10429 pipe_config->fb_changed = true;
10430
10431 turn_off = was_visible && (!visible || mode_changed);
10432 turn_on = visible && (!was_visible || mode_changed);
10433
10434 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10435 intel_crtc->base.base.id, intel_crtc->base.name,
10436 plane->base.base.id, plane->base.name,
10437 fb ? fb->base.id : -1);
10438
10439 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10440 plane->base.base.id, plane->base.name,
10441 was_visible, visible,
10442 turn_off, turn_on, mode_changed);
10443
10444 if (turn_on) {
10445 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10446 pipe_config->update_wm_pre = true;
10447
10448 /* must disable cxsr around plane enable/disable */
10449 if (plane->id != PLANE_CURSOR)
10450 pipe_config->disable_cxsr = true;
10451 } else if (turn_off) {
10452 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10453 pipe_config->update_wm_post = true;
10454
10455 /* must disable cxsr around plane enable/disable */
10456 if (plane->id != PLANE_CURSOR)
10457 pipe_config->disable_cxsr = true;
10458 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10459 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10460 /* FIXME bollocks */
10461 pipe_config->update_wm_pre = true;
10462 pipe_config->update_wm_post = true;
10463 }
10464 }
10465
10466 if (visible || was_visible)
10467 pipe_config->fb_bits |= plane->frontbuffer_bit;
10468
10469 /*
10470 * WaCxSRDisabledForSpriteScaling:ivb
10471 *
10472 * cstate->update_wm was already set above, so this flag will
10473 * take effect when we commit and program watermarks.
10474 */
10475 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10476 needs_scaling(to_intel_plane_state(plane_state)) &&
10477 !needs_scaling(old_plane_state))
10478 pipe_config->disable_lp_wm = true;
10479
10480 return 0;
10481 }
10482
10483 static bool encoders_cloneable(const struct intel_encoder *a,
10484 const struct intel_encoder *b)
10485 {
10486 /* masks could be asymmetric, so check both ways */
10487 return a == b || (a->cloneable & (1 << b->type) &&
10488 b->cloneable & (1 << a->type));
10489 }
10490
10491 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10492 struct intel_crtc *crtc,
10493 struct intel_encoder *encoder)
10494 {
10495 struct intel_encoder *source_encoder;
10496 struct drm_connector *connector;
10497 struct drm_connector_state *connector_state;
10498 int i;
10499
10500 for_each_new_connector_in_state(state, connector, connector_state, i) {
10501 if (connector_state->crtc != &crtc->base)
10502 continue;
10503
10504 source_encoder =
10505 to_intel_encoder(connector_state->best_encoder);
10506 if (!encoders_cloneable(encoder, source_encoder))
10507 return false;
10508 }
10509
10510 return true;
10511 }
10512
10513 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10514 struct drm_crtc_state *crtc_state)
10515 {
10516 struct drm_device *dev = crtc->dev;
10517 struct drm_i915_private *dev_priv = to_i915(dev);
10518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10519 struct intel_crtc_state *pipe_config =
10520 to_intel_crtc_state(crtc_state);
10521 struct drm_atomic_state *state = crtc_state->state;
10522 int ret;
10523 bool mode_changed = needs_modeset(crtc_state);
10524
10525 if (mode_changed && !crtc_state->active)
10526 pipe_config->update_wm_post = true;
10527
10528 if (mode_changed && crtc_state->enable &&
10529 dev_priv->display.crtc_compute_clock &&
10530 !WARN_ON(pipe_config->shared_dpll)) {
10531 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10532 pipe_config);
10533 if (ret)
10534 return ret;
10535 }
10536
10537 if (crtc_state->color_mgmt_changed) {
10538 ret = intel_color_check(crtc, crtc_state);
10539 if (ret)
10540 return ret;
10541
10542 /*
10543 * Changing color management on Intel hardware is
10544 * handled as part of planes update.
10545 */
10546 crtc_state->planes_changed = true;
10547 }
10548
10549 ret = 0;
10550 if (dev_priv->display.compute_pipe_wm) {
10551 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10552 if (ret) {
10553 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10554 return ret;
10555 }
10556 }
10557
10558 if (dev_priv->display.compute_intermediate_wm &&
10559 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10560 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10561 return 0;
10562
10563 /*
10564 * Calculate 'intermediate' watermarks that satisfy both the
10565 * old state and the new state. We can program these
10566 * immediately.
10567 */
10568 ret = dev_priv->display.compute_intermediate_wm(dev,
10569 intel_crtc,
10570 pipe_config);
10571 if (ret) {
10572 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10573 return ret;
10574 }
10575 } else if (dev_priv->display.compute_intermediate_wm) {
10576 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10577 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10578 }
10579
10580 if (INTEL_GEN(dev_priv) >= 9) {
10581 if (mode_changed)
10582 ret = skl_update_scaler_crtc(pipe_config);
10583
10584 if (!ret)
10585 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10586 pipe_config);
10587 if (!ret)
10588 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10589 pipe_config);
10590 }
10591
10592 return ret;
10593 }
10594
10595 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10596 .atomic_begin = intel_begin_crtc_commit,
10597 .atomic_flush = intel_finish_crtc_commit,
10598 .atomic_check = intel_crtc_atomic_check,
10599 };
10600
10601 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10602 {
10603 struct intel_connector *connector;
10604 struct drm_connector_list_iter conn_iter;
10605
10606 drm_connector_list_iter_begin(dev, &conn_iter);
10607 for_each_intel_connector_iter(connector, &conn_iter) {
10608 if (connector->base.state->crtc)
10609 drm_connector_unreference(&connector->base);
10610
10611 if (connector->base.encoder) {
10612 connector->base.state->best_encoder =
10613 connector->base.encoder;
10614 connector->base.state->crtc =
10615 connector->base.encoder->crtc;
10616
10617 drm_connector_reference(&connector->base);
10618 } else {
10619 connector->base.state->best_encoder = NULL;
10620 connector->base.state->crtc = NULL;
10621 }
10622 }
10623 drm_connector_list_iter_end(&conn_iter);
10624 }
10625
10626 static void
10627 connected_sink_compute_bpp(struct intel_connector *connector,
10628 struct intel_crtc_state *pipe_config)
10629 {
10630 const struct drm_display_info *info = &connector->base.display_info;
10631 int bpp = pipe_config->pipe_bpp;
10632
10633 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10634 connector->base.base.id,
10635 connector->base.name);
10636
10637 /* Don't use an invalid EDID bpc value */
10638 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10639 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10640 bpp, info->bpc * 3);
10641 pipe_config->pipe_bpp = info->bpc * 3;
10642 }
10643
10644 /* Clamp bpp to 8 on screens without EDID 1.4 */
10645 if (info->bpc == 0 && bpp > 24) {
10646 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10647 bpp);
10648 pipe_config->pipe_bpp = 24;
10649 }
10650 }
10651
10652 static int
10653 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10654 struct intel_crtc_state *pipe_config)
10655 {
10656 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10657 struct drm_atomic_state *state;
10658 struct drm_connector *connector;
10659 struct drm_connector_state *connector_state;
10660 int bpp, i;
10661
10662 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10663 IS_CHERRYVIEW(dev_priv)))
10664 bpp = 10*3;
10665 else if (INTEL_GEN(dev_priv) >= 5)
10666 bpp = 12*3;
10667 else
10668 bpp = 8*3;
10669
10670
10671 pipe_config->pipe_bpp = bpp;
10672
10673 state = pipe_config->base.state;
10674
10675 /* Clamp display bpp to EDID value */
10676 for_each_new_connector_in_state(state, connector, connector_state, i) {
10677 if (connector_state->crtc != &crtc->base)
10678 continue;
10679
10680 connected_sink_compute_bpp(to_intel_connector(connector),
10681 pipe_config);
10682 }
10683
10684 return bpp;
10685 }
10686
10687 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10688 {
10689 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10690 "type: 0x%x flags: 0x%x\n",
10691 mode->crtc_clock,
10692 mode->crtc_hdisplay, mode->crtc_hsync_start,
10693 mode->crtc_hsync_end, mode->crtc_htotal,
10694 mode->crtc_vdisplay, mode->crtc_vsync_start,
10695 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10696 }
10697
10698 static inline void
10699 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10700 unsigned int lane_count, struct intel_link_m_n *m_n)
10701 {
10702 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10703 id, lane_count,
10704 m_n->gmch_m, m_n->gmch_n,
10705 m_n->link_m, m_n->link_n, m_n->tu);
10706 }
10707
10708 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10709 struct intel_crtc_state *pipe_config,
10710 const char *context)
10711 {
10712 struct drm_device *dev = crtc->base.dev;
10713 struct drm_i915_private *dev_priv = to_i915(dev);
10714 struct drm_plane *plane;
10715 struct intel_plane *intel_plane;
10716 struct intel_plane_state *state;
10717 struct drm_framebuffer *fb;
10718
10719 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10720 crtc->base.base.id, crtc->base.name, context);
10721
10722 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10723 transcoder_name(pipe_config->cpu_transcoder),
10724 pipe_config->pipe_bpp, pipe_config->dither);
10725
10726 if (pipe_config->has_pch_encoder)
10727 intel_dump_m_n_config(pipe_config, "fdi",
10728 pipe_config->fdi_lanes,
10729 &pipe_config->fdi_m_n);
10730
10731 if (intel_crtc_has_dp_encoder(pipe_config)) {
10732 intel_dump_m_n_config(pipe_config, "dp m_n",
10733 pipe_config->lane_count, &pipe_config->dp_m_n);
10734 if (pipe_config->has_drrs)
10735 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10736 pipe_config->lane_count,
10737 &pipe_config->dp_m2_n2);
10738 }
10739
10740 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10741 pipe_config->has_audio, pipe_config->has_infoframe);
10742
10743 DRM_DEBUG_KMS("requested mode:\n");
10744 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10745 DRM_DEBUG_KMS("adjusted mode:\n");
10746 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10747 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10748 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10749 pipe_config->port_clock,
10750 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10751 pipe_config->pixel_rate);
10752
10753 if (INTEL_GEN(dev_priv) >= 9)
10754 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10755 crtc->num_scalers,
10756 pipe_config->scaler_state.scaler_users,
10757 pipe_config->scaler_state.scaler_id);
10758
10759 if (HAS_GMCH_DISPLAY(dev_priv))
10760 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10761 pipe_config->gmch_pfit.control,
10762 pipe_config->gmch_pfit.pgm_ratios,
10763 pipe_config->gmch_pfit.lvds_border_bits);
10764 else
10765 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10766 pipe_config->pch_pfit.pos,
10767 pipe_config->pch_pfit.size,
10768 enableddisabled(pipe_config->pch_pfit.enabled));
10769
10770 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10771 pipe_config->ips_enabled, pipe_config->double_wide);
10772
10773 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10774
10775 DRM_DEBUG_KMS("planes on this crtc\n");
10776 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10777 struct drm_format_name_buf format_name;
10778 intel_plane = to_intel_plane(plane);
10779 if (intel_plane->pipe != crtc->pipe)
10780 continue;
10781
10782 state = to_intel_plane_state(plane->state);
10783 fb = state->base.fb;
10784 if (!fb) {
10785 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10786 plane->base.id, plane->name, state->scaler_id);
10787 continue;
10788 }
10789
10790 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10791 plane->base.id, plane->name,
10792 fb->base.id, fb->width, fb->height,
10793 drm_get_format_name(fb->format->format, &format_name));
10794 if (INTEL_GEN(dev_priv) >= 9)
10795 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10796 state->scaler_id,
10797 state->base.src.x1 >> 16,
10798 state->base.src.y1 >> 16,
10799 drm_rect_width(&state->base.src) >> 16,
10800 drm_rect_height(&state->base.src) >> 16,
10801 state->base.dst.x1, state->base.dst.y1,
10802 drm_rect_width(&state->base.dst),
10803 drm_rect_height(&state->base.dst));
10804 }
10805 }
10806
10807 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10808 {
10809 struct drm_device *dev = state->dev;
10810 struct drm_connector *connector;
10811 struct drm_connector_list_iter conn_iter;
10812 unsigned int used_ports = 0;
10813 unsigned int used_mst_ports = 0;
10814
10815 /*
10816 * Walk the connector list instead of the encoder
10817 * list to detect the problem on ddi platforms
10818 * where there's just one encoder per digital port.
10819 */
10820 drm_connector_list_iter_begin(dev, &conn_iter);
10821 drm_for_each_connector_iter(connector, &conn_iter) {
10822 struct drm_connector_state *connector_state;
10823 struct intel_encoder *encoder;
10824
10825 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10826 if (!connector_state)
10827 connector_state = connector->state;
10828
10829 if (!connector_state->best_encoder)
10830 continue;
10831
10832 encoder = to_intel_encoder(connector_state->best_encoder);
10833
10834 WARN_ON(!connector_state->crtc);
10835
10836 switch (encoder->type) {
10837 unsigned int port_mask;
10838 case INTEL_OUTPUT_UNKNOWN:
10839 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10840 break;
10841 case INTEL_OUTPUT_DP:
10842 case INTEL_OUTPUT_HDMI:
10843 case INTEL_OUTPUT_EDP:
10844 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10845
10846 /* the same port mustn't appear more than once */
10847 if (used_ports & port_mask)
10848 return false;
10849
10850 used_ports |= port_mask;
10851 break;
10852 case INTEL_OUTPUT_DP_MST:
10853 used_mst_ports |=
10854 1 << enc_to_mst(&encoder->base)->primary->port;
10855 break;
10856 default:
10857 break;
10858 }
10859 }
10860 drm_connector_list_iter_end(&conn_iter);
10861
10862 /* can't mix MST and SST/HDMI on the same port */
10863 if (used_ports & used_mst_ports)
10864 return false;
10865
10866 return true;
10867 }
10868
10869 static void
10870 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10871 {
10872 struct drm_i915_private *dev_priv =
10873 to_i915(crtc_state->base.crtc->dev);
10874 struct intel_crtc_scaler_state scaler_state;
10875 struct intel_dpll_hw_state dpll_hw_state;
10876 struct intel_shared_dpll *shared_dpll;
10877 struct intel_crtc_wm_state wm_state;
10878 bool force_thru;
10879
10880 /* FIXME: before the switch to atomic started, a new pipe_config was
10881 * kzalloc'd. Code that depends on any field being zero should be
10882 * fixed, so that the crtc_state can be safely duplicated. For now,
10883 * only fields that are know to not cause problems are preserved. */
10884
10885 scaler_state = crtc_state->scaler_state;
10886 shared_dpll = crtc_state->shared_dpll;
10887 dpll_hw_state = crtc_state->dpll_hw_state;
10888 force_thru = crtc_state->pch_pfit.force_thru;
10889 if (IS_G4X(dev_priv) ||
10890 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10891 wm_state = crtc_state->wm;
10892
10893 /* Keep base drm_crtc_state intact, only clear our extended struct */
10894 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10895 memset(&crtc_state->base + 1, 0,
10896 sizeof(*crtc_state) - sizeof(crtc_state->base));
10897
10898 crtc_state->scaler_state = scaler_state;
10899 crtc_state->shared_dpll = shared_dpll;
10900 crtc_state->dpll_hw_state = dpll_hw_state;
10901 crtc_state->pch_pfit.force_thru = force_thru;
10902 if (IS_G4X(dev_priv) ||
10903 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10904 crtc_state->wm = wm_state;
10905 }
10906
10907 static int
10908 intel_modeset_pipe_config(struct drm_crtc *crtc,
10909 struct intel_crtc_state *pipe_config)
10910 {
10911 struct drm_atomic_state *state = pipe_config->base.state;
10912 struct intel_encoder *encoder;
10913 struct drm_connector *connector;
10914 struct drm_connector_state *connector_state;
10915 int base_bpp, ret = -EINVAL;
10916 int i;
10917 bool retry = true;
10918
10919 clear_intel_crtc_state(pipe_config);
10920
10921 pipe_config->cpu_transcoder =
10922 (enum transcoder) to_intel_crtc(crtc)->pipe;
10923
10924 /*
10925 * Sanitize sync polarity flags based on requested ones. If neither
10926 * positive or negative polarity is requested, treat this as meaning
10927 * negative polarity.
10928 */
10929 if (!(pipe_config->base.adjusted_mode.flags &
10930 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10931 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10932
10933 if (!(pipe_config->base.adjusted_mode.flags &
10934 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10935 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10936
10937 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10938 pipe_config);
10939 if (base_bpp < 0)
10940 goto fail;
10941
10942 /*
10943 * Determine the real pipe dimensions. Note that stereo modes can
10944 * increase the actual pipe size due to the frame doubling and
10945 * insertion of additional space for blanks between the frame. This
10946 * is stored in the crtc timings. We use the requested mode to do this
10947 * computation to clearly distinguish it from the adjusted mode, which
10948 * can be changed by the connectors in the below retry loop.
10949 */
10950 drm_mode_get_hv_timing(&pipe_config->base.mode,
10951 &pipe_config->pipe_src_w,
10952 &pipe_config->pipe_src_h);
10953
10954 for_each_new_connector_in_state(state, connector, connector_state, i) {
10955 if (connector_state->crtc != crtc)
10956 continue;
10957
10958 encoder = to_intel_encoder(connector_state->best_encoder);
10959
10960 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10961 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10962 goto fail;
10963 }
10964
10965 /*
10966 * Determine output_types before calling the .compute_config()
10967 * hooks so that the hooks can use this information safely.
10968 */
10969 pipe_config->output_types |= 1 << encoder->type;
10970 }
10971
10972 encoder_retry:
10973 /* Ensure the port clock defaults are reset when retrying. */
10974 pipe_config->port_clock = 0;
10975 pipe_config->pixel_multiplier = 1;
10976
10977 /* Fill in default crtc timings, allow encoders to overwrite them. */
10978 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10979 CRTC_STEREO_DOUBLE);
10980
10981 /* Pass our mode to the connectors and the CRTC to give them a chance to
10982 * adjust it according to limitations or connector properties, and also
10983 * a chance to reject the mode entirely.
10984 */
10985 for_each_new_connector_in_state(state, connector, connector_state, i) {
10986 if (connector_state->crtc != crtc)
10987 continue;
10988
10989 encoder = to_intel_encoder(connector_state->best_encoder);
10990
10991 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10992 DRM_DEBUG_KMS("Encoder config failure\n");
10993 goto fail;
10994 }
10995 }
10996
10997 /* Set default port clock if not overwritten by the encoder. Needs to be
10998 * done afterwards in case the encoder adjusts the mode. */
10999 if (!pipe_config->port_clock)
11000 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11001 * pipe_config->pixel_multiplier;
11002
11003 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11004 if (ret < 0) {
11005 DRM_DEBUG_KMS("CRTC fixup failed\n");
11006 goto fail;
11007 }
11008
11009 if (ret == RETRY) {
11010 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11011 ret = -EINVAL;
11012 goto fail;
11013 }
11014
11015 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11016 retry = false;
11017 goto encoder_retry;
11018 }
11019
11020 /* Dithering seems to not pass-through bits correctly when it should, so
11021 * only enable it on 6bpc panels and when its not a compliance
11022 * test requesting 6bpc video pattern.
11023 */
11024 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11025 !pipe_config->dither_force_disable;
11026 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11027 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11028
11029 fail:
11030 return ret;
11031 }
11032
11033 static void
11034 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11035 {
11036 struct drm_crtc *crtc;
11037 struct drm_crtc_state *new_crtc_state;
11038 int i;
11039
11040 /* Double check state. */
11041 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11042 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11043
11044 /*
11045 * Update legacy state to satisfy fbc code. This can
11046 * be removed when fbc uses the atomic state.
11047 */
11048 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11049 struct drm_plane_state *plane_state = crtc->primary->state;
11050
11051 crtc->primary->fb = plane_state->fb;
11052 crtc->x = plane_state->src_x >> 16;
11053 crtc->y = plane_state->src_y >> 16;
11054 }
11055 }
11056 }
11057
11058 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11059 {
11060 int diff;
11061
11062 if (clock1 == clock2)
11063 return true;
11064
11065 if (!clock1 || !clock2)
11066 return false;
11067
11068 diff = abs(clock1 - clock2);
11069
11070 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11071 return true;
11072
11073 return false;
11074 }
11075
11076 static bool
11077 intel_compare_m_n(unsigned int m, unsigned int n,
11078 unsigned int m2, unsigned int n2,
11079 bool exact)
11080 {
11081 if (m == m2 && n == n2)
11082 return true;
11083
11084 if (exact || !m || !n || !m2 || !n2)
11085 return false;
11086
11087 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11088
11089 if (n > n2) {
11090 while (n > n2) {
11091 m2 <<= 1;
11092 n2 <<= 1;
11093 }
11094 } else if (n < n2) {
11095 while (n < n2) {
11096 m <<= 1;
11097 n <<= 1;
11098 }
11099 }
11100
11101 if (n != n2)
11102 return false;
11103
11104 return intel_fuzzy_clock_check(m, m2);
11105 }
11106
11107 static bool
11108 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11109 struct intel_link_m_n *m2_n2,
11110 bool adjust)
11111 {
11112 if (m_n->tu == m2_n2->tu &&
11113 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11114 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11115 intel_compare_m_n(m_n->link_m, m_n->link_n,
11116 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11117 if (adjust)
11118 *m2_n2 = *m_n;
11119
11120 return true;
11121 }
11122
11123 return false;
11124 }
11125
11126 static void __printf(3, 4)
11127 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11128 {
11129 char *level;
11130 unsigned int category;
11131 struct va_format vaf;
11132 va_list args;
11133
11134 if (adjust) {
11135 level = KERN_DEBUG;
11136 category = DRM_UT_KMS;
11137 } else {
11138 level = KERN_ERR;
11139 category = DRM_UT_NONE;
11140 }
11141
11142 va_start(args, format);
11143 vaf.fmt = format;
11144 vaf.va = &args;
11145
11146 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11147
11148 va_end(args);
11149 }
11150
11151 static bool
11152 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11153 struct intel_crtc_state *current_config,
11154 struct intel_crtc_state *pipe_config,
11155 bool adjust)
11156 {
11157 bool ret = true;
11158
11159 #define PIPE_CONF_CHECK_X(name) \
11160 if (current_config->name != pipe_config->name) { \
11161 pipe_config_err(adjust, __stringify(name), \
11162 "(expected 0x%08x, found 0x%08x)\n", \
11163 current_config->name, \
11164 pipe_config->name); \
11165 ret = false; \
11166 }
11167
11168 #define PIPE_CONF_CHECK_I(name) \
11169 if (current_config->name != pipe_config->name) { \
11170 pipe_config_err(adjust, __stringify(name), \
11171 "(expected %i, found %i)\n", \
11172 current_config->name, \
11173 pipe_config->name); \
11174 ret = false; \
11175 }
11176
11177 #define PIPE_CONF_CHECK_P(name) \
11178 if (current_config->name != pipe_config->name) { \
11179 pipe_config_err(adjust, __stringify(name), \
11180 "(expected %p, found %p)\n", \
11181 current_config->name, \
11182 pipe_config->name); \
11183 ret = false; \
11184 }
11185
11186 #define PIPE_CONF_CHECK_M_N(name) \
11187 if (!intel_compare_link_m_n(&current_config->name, \
11188 &pipe_config->name,\
11189 adjust)) { \
11190 pipe_config_err(adjust, __stringify(name), \
11191 "(expected tu %i gmch %i/%i link %i/%i, " \
11192 "found tu %i, gmch %i/%i link %i/%i)\n", \
11193 current_config->name.tu, \
11194 current_config->name.gmch_m, \
11195 current_config->name.gmch_n, \
11196 current_config->name.link_m, \
11197 current_config->name.link_n, \
11198 pipe_config->name.tu, \
11199 pipe_config->name.gmch_m, \
11200 pipe_config->name.gmch_n, \
11201 pipe_config->name.link_m, \
11202 pipe_config->name.link_n); \
11203 ret = false; \
11204 }
11205
11206 /* This is required for BDW+ where there is only one set of registers for
11207 * switching between high and low RR.
11208 * This macro can be used whenever a comparison has to be made between one
11209 * hw state and multiple sw state variables.
11210 */
11211 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11212 if (!intel_compare_link_m_n(&current_config->name, \
11213 &pipe_config->name, adjust) && \
11214 !intel_compare_link_m_n(&current_config->alt_name, \
11215 &pipe_config->name, adjust)) { \
11216 pipe_config_err(adjust, __stringify(name), \
11217 "(expected tu %i gmch %i/%i link %i/%i, " \
11218 "or tu %i gmch %i/%i link %i/%i, " \
11219 "found tu %i, gmch %i/%i link %i/%i)\n", \
11220 current_config->name.tu, \
11221 current_config->name.gmch_m, \
11222 current_config->name.gmch_n, \
11223 current_config->name.link_m, \
11224 current_config->name.link_n, \
11225 current_config->alt_name.tu, \
11226 current_config->alt_name.gmch_m, \
11227 current_config->alt_name.gmch_n, \
11228 current_config->alt_name.link_m, \
11229 current_config->alt_name.link_n, \
11230 pipe_config->name.tu, \
11231 pipe_config->name.gmch_m, \
11232 pipe_config->name.gmch_n, \
11233 pipe_config->name.link_m, \
11234 pipe_config->name.link_n); \
11235 ret = false; \
11236 }
11237
11238 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11239 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11240 pipe_config_err(adjust, __stringify(name), \
11241 "(%x) (expected %i, found %i)\n", \
11242 (mask), \
11243 current_config->name & (mask), \
11244 pipe_config->name & (mask)); \
11245 ret = false; \
11246 }
11247
11248 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11249 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11250 pipe_config_err(adjust, __stringify(name), \
11251 "(expected %i, found %i)\n", \
11252 current_config->name, \
11253 pipe_config->name); \
11254 ret = false; \
11255 }
11256
11257 #define PIPE_CONF_QUIRK(quirk) \
11258 ((current_config->quirks | pipe_config->quirks) & (quirk))
11259
11260 PIPE_CONF_CHECK_I(cpu_transcoder);
11261
11262 PIPE_CONF_CHECK_I(has_pch_encoder);
11263 PIPE_CONF_CHECK_I(fdi_lanes);
11264 PIPE_CONF_CHECK_M_N(fdi_m_n);
11265
11266 PIPE_CONF_CHECK_I(lane_count);
11267 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11268
11269 if (INTEL_GEN(dev_priv) < 8) {
11270 PIPE_CONF_CHECK_M_N(dp_m_n);
11271
11272 if (current_config->has_drrs)
11273 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11274 } else
11275 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11276
11277 PIPE_CONF_CHECK_X(output_types);
11278
11279 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11280 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11281 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11282 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11283 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11284 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11285
11286 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11287 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11288 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11289 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11290 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11291 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11292
11293 PIPE_CONF_CHECK_I(pixel_multiplier);
11294 PIPE_CONF_CHECK_I(has_hdmi_sink);
11295 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11296 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11297 PIPE_CONF_CHECK_I(limited_color_range);
11298
11299 PIPE_CONF_CHECK_I(hdmi_scrambling);
11300 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11301 PIPE_CONF_CHECK_I(has_infoframe);
11302
11303 PIPE_CONF_CHECK_I(has_audio);
11304
11305 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11306 DRM_MODE_FLAG_INTERLACE);
11307
11308 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11309 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11310 DRM_MODE_FLAG_PHSYNC);
11311 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11312 DRM_MODE_FLAG_NHSYNC);
11313 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11314 DRM_MODE_FLAG_PVSYNC);
11315 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11316 DRM_MODE_FLAG_NVSYNC);
11317 }
11318
11319 PIPE_CONF_CHECK_X(gmch_pfit.control);
11320 /* pfit ratios are autocomputed by the hw on gen4+ */
11321 if (INTEL_GEN(dev_priv) < 4)
11322 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11323 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11324
11325 if (!adjust) {
11326 PIPE_CONF_CHECK_I(pipe_src_w);
11327 PIPE_CONF_CHECK_I(pipe_src_h);
11328
11329 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11330 if (current_config->pch_pfit.enabled) {
11331 PIPE_CONF_CHECK_X(pch_pfit.pos);
11332 PIPE_CONF_CHECK_X(pch_pfit.size);
11333 }
11334
11335 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11336 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11337 }
11338
11339 /* BDW+ don't expose a synchronous way to read the state */
11340 if (IS_HASWELL(dev_priv))
11341 PIPE_CONF_CHECK_I(ips_enabled);
11342
11343 PIPE_CONF_CHECK_I(double_wide);
11344
11345 PIPE_CONF_CHECK_P(shared_dpll);
11346 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11347 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11348 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11349 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11350 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11351 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11352 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11353 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11354 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11355
11356 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11357 PIPE_CONF_CHECK_X(dsi_pll.div);
11358
11359 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11360 PIPE_CONF_CHECK_I(pipe_bpp);
11361
11362 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11363 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11364
11365 #undef PIPE_CONF_CHECK_X
11366 #undef PIPE_CONF_CHECK_I
11367 #undef PIPE_CONF_CHECK_P
11368 #undef PIPE_CONF_CHECK_FLAGS
11369 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11370 #undef PIPE_CONF_QUIRK
11371
11372 return ret;
11373 }
11374
11375 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11376 const struct intel_crtc_state *pipe_config)
11377 {
11378 if (pipe_config->has_pch_encoder) {
11379 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11380 &pipe_config->fdi_m_n);
11381 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11382
11383 /*
11384 * FDI already provided one idea for the dotclock.
11385 * Yell if the encoder disagrees.
11386 */
11387 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11388 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11389 fdi_dotclock, dotclock);
11390 }
11391 }
11392
11393 static void verify_wm_state(struct drm_crtc *crtc,
11394 struct drm_crtc_state *new_state)
11395 {
11396 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11397 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11398 struct skl_pipe_wm hw_wm, *sw_wm;
11399 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11400 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11402 const enum pipe pipe = intel_crtc->pipe;
11403 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11404
11405 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11406 return;
11407
11408 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11409 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11410
11411 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11412 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11413
11414 /* planes */
11415 for_each_universal_plane(dev_priv, pipe, plane) {
11416 hw_plane_wm = &hw_wm.planes[plane];
11417 sw_plane_wm = &sw_wm->planes[plane];
11418
11419 /* Watermarks */
11420 for (level = 0; level <= max_level; level++) {
11421 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11422 &sw_plane_wm->wm[level]))
11423 continue;
11424
11425 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11426 pipe_name(pipe), plane + 1, level,
11427 sw_plane_wm->wm[level].plane_en,
11428 sw_plane_wm->wm[level].plane_res_b,
11429 sw_plane_wm->wm[level].plane_res_l,
11430 hw_plane_wm->wm[level].plane_en,
11431 hw_plane_wm->wm[level].plane_res_b,
11432 hw_plane_wm->wm[level].plane_res_l);
11433 }
11434
11435 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11436 &sw_plane_wm->trans_wm)) {
11437 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11438 pipe_name(pipe), plane + 1,
11439 sw_plane_wm->trans_wm.plane_en,
11440 sw_plane_wm->trans_wm.plane_res_b,
11441 sw_plane_wm->trans_wm.plane_res_l,
11442 hw_plane_wm->trans_wm.plane_en,
11443 hw_plane_wm->trans_wm.plane_res_b,
11444 hw_plane_wm->trans_wm.plane_res_l);
11445 }
11446
11447 /* DDB */
11448 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11449 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11450
11451 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11452 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11453 pipe_name(pipe), plane + 1,
11454 sw_ddb_entry->start, sw_ddb_entry->end,
11455 hw_ddb_entry->start, hw_ddb_entry->end);
11456 }
11457 }
11458
11459 /*
11460 * cursor
11461 * If the cursor plane isn't active, we may not have updated it's ddb
11462 * allocation. In that case since the ddb allocation will be updated
11463 * once the plane becomes visible, we can skip this check
11464 */
11465 if (1) {
11466 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11467 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11468
11469 /* Watermarks */
11470 for (level = 0; level <= max_level; level++) {
11471 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11472 &sw_plane_wm->wm[level]))
11473 continue;
11474
11475 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11476 pipe_name(pipe), level,
11477 sw_plane_wm->wm[level].plane_en,
11478 sw_plane_wm->wm[level].plane_res_b,
11479 sw_plane_wm->wm[level].plane_res_l,
11480 hw_plane_wm->wm[level].plane_en,
11481 hw_plane_wm->wm[level].plane_res_b,
11482 hw_plane_wm->wm[level].plane_res_l);
11483 }
11484
11485 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11486 &sw_plane_wm->trans_wm)) {
11487 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11488 pipe_name(pipe),
11489 sw_plane_wm->trans_wm.plane_en,
11490 sw_plane_wm->trans_wm.plane_res_b,
11491 sw_plane_wm->trans_wm.plane_res_l,
11492 hw_plane_wm->trans_wm.plane_en,
11493 hw_plane_wm->trans_wm.plane_res_b,
11494 hw_plane_wm->trans_wm.plane_res_l);
11495 }
11496
11497 /* DDB */
11498 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11499 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11500
11501 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11502 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11503 pipe_name(pipe),
11504 sw_ddb_entry->start, sw_ddb_entry->end,
11505 hw_ddb_entry->start, hw_ddb_entry->end);
11506 }
11507 }
11508 }
11509
11510 static void
11511 verify_connector_state(struct drm_device *dev,
11512 struct drm_atomic_state *state,
11513 struct drm_crtc *crtc)
11514 {
11515 struct drm_connector *connector;
11516 struct drm_connector_state *new_conn_state;
11517 int i;
11518
11519 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11520 struct drm_encoder *encoder = connector->encoder;
11521 struct drm_crtc_state *crtc_state = NULL;
11522
11523 if (new_conn_state->crtc != crtc)
11524 continue;
11525
11526 if (crtc)
11527 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11528
11529 intel_connector_verify_state(crtc_state, new_conn_state);
11530
11531 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11532 "connector's atomic encoder doesn't match legacy encoder\n");
11533 }
11534 }
11535
11536 static void
11537 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11538 {
11539 struct intel_encoder *encoder;
11540 struct drm_connector *connector;
11541 struct drm_connector_state *old_conn_state, *new_conn_state;
11542 int i;
11543
11544 for_each_intel_encoder(dev, encoder) {
11545 bool enabled = false, found = false;
11546 enum pipe pipe;
11547
11548 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11549 encoder->base.base.id,
11550 encoder->base.name);
11551
11552 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11553 new_conn_state, i) {
11554 if (old_conn_state->best_encoder == &encoder->base)
11555 found = true;
11556
11557 if (new_conn_state->best_encoder != &encoder->base)
11558 continue;
11559 found = enabled = true;
11560
11561 I915_STATE_WARN(new_conn_state->crtc !=
11562 encoder->base.crtc,
11563 "connector's crtc doesn't match encoder crtc\n");
11564 }
11565
11566 if (!found)
11567 continue;
11568
11569 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11570 "encoder's enabled state mismatch "
11571 "(expected %i, found %i)\n",
11572 !!encoder->base.crtc, enabled);
11573
11574 if (!encoder->base.crtc) {
11575 bool active;
11576
11577 active = encoder->get_hw_state(encoder, &pipe);
11578 I915_STATE_WARN(active,
11579 "encoder detached but still enabled on pipe %c.\n",
11580 pipe_name(pipe));
11581 }
11582 }
11583 }
11584
11585 static void
11586 verify_crtc_state(struct drm_crtc *crtc,
11587 struct drm_crtc_state *old_crtc_state,
11588 struct drm_crtc_state *new_crtc_state)
11589 {
11590 struct drm_device *dev = crtc->dev;
11591 struct drm_i915_private *dev_priv = to_i915(dev);
11592 struct intel_encoder *encoder;
11593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11594 struct intel_crtc_state *pipe_config, *sw_config;
11595 struct drm_atomic_state *old_state;
11596 bool active;
11597
11598 old_state = old_crtc_state->state;
11599 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11600 pipe_config = to_intel_crtc_state(old_crtc_state);
11601 memset(pipe_config, 0, sizeof(*pipe_config));
11602 pipe_config->base.crtc = crtc;
11603 pipe_config->base.state = old_state;
11604
11605 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11606
11607 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11608
11609 /* we keep both pipes enabled on 830 */
11610 if (IS_I830(dev_priv))
11611 active = new_crtc_state->active;
11612
11613 I915_STATE_WARN(new_crtc_state->active != active,
11614 "crtc active state doesn't match with hw state "
11615 "(expected %i, found %i)\n", new_crtc_state->active, active);
11616
11617 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11618 "transitional active state does not match atomic hw state "
11619 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11620
11621 for_each_encoder_on_crtc(dev, crtc, encoder) {
11622 enum pipe pipe;
11623
11624 active = encoder->get_hw_state(encoder, &pipe);
11625 I915_STATE_WARN(active != new_crtc_state->active,
11626 "[ENCODER:%i] active %i with crtc active %i\n",
11627 encoder->base.base.id, active, new_crtc_state->active);
11628
11629 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11630 "Encoder connected to wrong pipe %c\n",
11631 pipe_name(pipe));
11632
11633 if (active) {
11634 pipe_config->output_types |= 1 << encoder->type;
11635 encoder->get_config(encoder, pipe_config);
11636 }
11637 }
11638
11639 intel_crtc_compute_pixel_rate(pipe_config);
11640
11641 if (!new_crtc_state->active)
11642 return;
11643
11644 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11645
11646 sw_config = to_intel_crtc_state(new_crtc_state);
11647 if (!intel_pipe_config_compare(dev_priv, sw_config,
11648 pipe_config, false)) {
11649 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11650 intel_dump_pipe_config(intel_crtc, pipe_config,
11651 "[hw state]");
11652 intel_dump_pipe_config(intel_crtc, sw_config,
11653 "[sw state]");
11654 }
11655 }
11656
11657 static void
11658 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11659 struct intel_shared_dpll *pll,
11660 struct drm_crtc *crtc,
11661 struct drm_crtc_state *new_state)
11662 {
11663 struct intel_dpll_hw_state dpll_hw_state;
11664 unsigned crtc_mask;
11665 bool active;
11666
11667 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11668
11669 DRM_DEBUG_KMS("%s\n", pll->name);
11670
11671 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11672
11673 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11674 I915_STATE_WARN(!pll->on && pll->active_mask,
11675 "pll in active use but not on in sw tracking\n");
11676 I915_STATE_WARN(pll->on && !pll->active_mask,
11677 "pll is on but not used by any active crtc\n");
11678 I915_STATE_WARN(pll->on != active,
11679 "pll on state mismatch (expected %i, found %i)\n",
11680 pll->on, active);
11681 }
11682
11683 if (!crtc) {
11684 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11685 "more active pll users than references: %x vs %x\n",
11686 pll->active_mask, pll->state.crtc_mask);
11687
11688 return;
11689 }
11690
11691 crtc_mask = 1 << drm_crtc_index(crtc);
11692
11693 if (new_state->active)
11694 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11695 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11696 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11697 else
11698 I915_STATE_WARN(pll->active_mask & crtc_mask,
11699 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11700 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11701
11702 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11703 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11704 crtc_mask, pll->state.crtc_mask);
11705
11706 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11707 &dpll_hw_state,
11708 sizeof(dpll_hw_state)),
11709 "pll hw state mismatch\n");
11710 }
11711
11712 static void
11713 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11714 struct drm_crtc_state *old_crtc_state,
11715 struct drm_crtc_state *new_crtc_state)
11716 {
11717 struct drm_i915_private *dev_priv = to_i915(dev);
11718 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11719 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11720
11721 if (new_state->shared_dpll)
11722 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11723
11724 if (old_state->shared_dpll &&
11725 old_state->shared_dpll != new_state->shared_dpll) {
11726 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11727 struct intel_shared_dpll *pll = old_state->shared_dpll;
11728
11729 I915_STATE_WARN(pll->active_mask & crtc_mask,
11730 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11731 pipe_name(drm_crtc_index(crtc)));
11732 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11733 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11734 pipe_name(drm_crtc_index(crtc)));
11735 }
11736 }
11737
11738 static void
11739 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11740 struct drm_atomic_state *state,
11741 struct drm_crtc_state *old_state,
11742 struct drm_crtc_state *new_state)
11743 {
11744 if (!needs_modeset(new_state) &&
11745 !to_intel_crtc_state(new_state)->update_pipe)
11746 return;
11747
11748 verify_wm_state(crtc, new_state);
11749 verify_connector_state(crtc->dev, state, crtc);
11750 verify_crtc_state(crtc, old_state, new_state);
11751 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11752 }
11753
11754 static void
11755 verify_disabled_dpll_state(struct drm_device *dev)
11756 {
11757 struct drm_i915_private *dev_priv = to_i915(dev);
11758 int i;
11759
11760 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11761 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11762 }
11763
11764 static void
11765 intel_modeset_verify_disabled(struct drm_device *dev,
11766 struct drm_atomic_state *state)
11767 {
11768 verify_encoder_state(dev, state);
11769 verify_connector_state(dev, state, NULL);
11770 verify_disabled_dpll_state(dev);
11771 }
11772
11773 static void update_scanline_offset(struct intel_crtc *crtc)
11774 {
11775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11776
11777 /*
11778 * The scanline counter increments at the leading edge of hsync.
11779 *
11780 * On most platforms it starts counting from vtotal-1 on the
11781 * first active line. That means the scanline counter value is
11782 * always one less than what we would expect. Ie. just after
11783 * start of vblank, which also occurs at start of hsync (on the
11784 * last active line), the scanline counter will read vblank_start-1.
11785 *
11786 * On gen2 the scanline counter starts counting from 1 instead
11787 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11788 * to keep the value positive), instead of adding one.
11789 *
11790 * On HSW+ the behaviour of the scanline counter depends on the output
11791 * type. For DP ports it behaves like most other platforms, but on HDMI
11792 * there's an extra 1 line difference. So we need to add two instead of
11793 * one to the value.
11794 *
11795 * On VLV/CHV DSI the scanline counter would appear to increment
11796 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11797 * that means we can't tell whether we're in vblank or not while
11798 * we're on that particular line. We must still set scanline_offset
11799 * to 1 so that the vblank timestamps come out correct when we query
11800 * the scanline counter from within the vblank interrupt handler.
11801 * However if queried just before the start of vblank we'll get an
11802 * answer that's slightly in the future.
11803 */
11804 if (IS_GEN2(dev_priv)) {
11805 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11806 int vtotal;
11807
11808 vtotal = adjusted_mode->crtc_vtotal;
11809 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11810 vtotal /= 2;
11811
11812 crtc->scanline_offset = vtotal - 1;
11813 } else if (HAS_DDI(dev_priv) &&
11814 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11815 crtc->scanline_offset = 2;
11816 } else
11817 crtc->scanline_offset = 1;
11818 }
11819
11820 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11821 {
11822 struct drm_device *dev = state->dev;
11823 struct drm_i915_private *dev_priv = to_i915(dev);
11824 struct drm_crtc *crtc;
11825 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11826 int i;
11827
11828 if (!dev_priv->display.crtc_compute_clock)
11829 return;
11830
11831 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11833 struct intel_shared_dpll *old_dpll =
11834 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11835
11836 if (!needs_modeset(new_crtc_state))
11837 continue;
11838
11839 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11840
11841 if (!old_dpll)
11842 continue;
11843
11844 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11845 }
11846 }
11847
11848 /*
11849 * This implements the workaround described in the "notes" section of the mode
11850 * set sequence documentation. When going from no pipes or single pipe to
11851 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11852 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11853 */
11854 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11855 {
11856 struct drm_crtc_state *crtc_state;
11857 struct intel_crtc *intel_crtc;
11858 struct drm_crtc *crtc;
11859 struct intel_crtc_state *first_crtc_state = NULL;
11860 struct intel_crtc_state *other_crtc_state = NULL;
11861 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11862 int i;
11863
11864 /* look at all crtc's that are going to be enabled in during modeset */
11865 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11866 intel_crtc = to_intel_crtc(crtc);
11867
11868 if (!crtc_state->active || !needs_modeset(crtc_state))
11869 continue;
11870
11871 if (first_crtc_state) {
11872 other_crtc_state = to_intel_crtc_state(crtc_state);
11873 break;
11874 } else {
11875 first_crtc_state = to_intel_crtc_state(crtc_state);
11876 first_pipe = intel_crtc->pipe;
11877 }
11878 }
11879
11880 /* No workaround needed? */
11881 if (!first_crtc_state)
11882 return 0;
11883
11884 /* w/a possibly needed, check how many crtc's are already enabled. */
11885 for_each_intel_crtc(state->dev, intel_crtc) {
11886 struct intel_crtc_state *pipe_config;
11887
11888 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11889 if (IS_ERR(pipe_config))
11890 return PTR_ERR(pipe_config);
11891
11892 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11893
11894 if (!pipe_config->base.active ||
11895 needs_modeset(&pipe_config->base))
11896 continue;
11897
11898 /* 2 or more enabled crtcs means no need for w/a */
11899 if (enabled_pipe != INVALID_PIPE)
11900 return 0;
11901
11902 enabled_pipe = intel_crtc->pipe;
11903 }
11904
11905 if (enabled_pipe != INVALID_PIPE)
11906 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11907 else if (other_crtc_state)
11908 other_crtc_state->hsw_workaround_pipe = first_pipe;
11909
11910 return 0;
11911 }
11912
11913 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11914 {
11915 struct drm_crtc *crtc;
11916
11917 /* Add all pipes to the state */
11918 for_each_crtc(state->dev, crtc) {
11919 struct drm_crtc_state *crtc_state;
11920
11921 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11922 if (IS_ERR(crtc_state))
11923 return PTR_ERR(crtc_state);
11924 }
11925
11926 return 0;
11927 }
11928
11929 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11930 {
11931 struct drm_crtc *crtc;
11932
11933 /*
11934 * Add all pipes to the state, and force
11935 * a modeset on all the active ones.
11936 */
11937 for_each_crtc(state->dev, crtc) {
11938 struct drm_crtc_state *crtc_state;
11939 int ret;
11940
11941 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11942 if (IS_ERR(crtc_state))
11943 return PTR_ERR(crtc_state);
11944
11945 if (!crtc_state->active || needs_modeset(crtc_state))
11946 continue;
11947
11948 crtc_state->mode_changed = true;
11949
11950 ret = drm_atomic_add_affected_connectors(state, crtc);
11951 if (ret)
11952 return ret;
11953
11954 ret = drm_atomic_add_affected_planes(state, crtc);
11955 if (ret)
11956 return ret;
11957 }
11958
11959 return 0;
11960 }
11961
11962 static int intel_modeset_checks(struct drm_atomic_state *state)
11963 {
11964 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11965 struct drm_i915_private *dev_priv = to_i915(state->dev);
11966 struct drm_crtc *crtc;
11967 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11968 int ret = 0, i;
11969
11970 if (!check_digital_port_conflicts(state)) {
11971 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11972 return -EINVAL;
11973 }
11974
11975 intel_state->modeset = true;
11976 intel_state->active_crtcs = dev_priv->active_crtcs;
11977 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11978 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11979
11980 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11981 if (new_crtc_state->active)
11982 intel_state->active_crtcs |= 1 << i;
11983 else
11984 intel_state->active_crtcs &= ~(1 << i);
11985
11986 if (old_crtc_state->active != new_crtc_state->active)
11987 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11988 }
11989
11990 /*
11991 * See if the config requires any additional preparation, e.g.
11992 * to adjust global state with pipes off. We need to do this
11993 * here so we can get the modeset_pipe updated config for the new
11994 * mode set on this crtc. For other crtcs we need to use the
11995 * adjusted_mode bits in the crtc directly.
11996 */
11997 if (dev_priv->display.modeset_calc_cdclk) {
11998 ret = dev_priv->display.modeset_calc_cdclk(state);
11999 if (ret < 0)
12000 return ret;
12001
12002 /*
12003 * Writes to dev_priv->cdclk.logical must protected by
12004 * holding all the crtc locks, even if we don't end up
12005 * touching the hardware
12006 */
12007 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12008 &intel_state->cdclk.logical)) {
12009 ret = intel_lock_all_pipes(state);
12010 if (ret < 0)
12011 return ret;
12012 }
12013
12014 /* All pipes must be switched off while we change the cdclk. */
12015 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12016 &intel_state->cdclk.actual)) {
12017 ret = intel_modeset_all_pipes(state);
12018 if (ret < 0)
12019 return ret;
12020 }
12021
12022 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12023 intel_state->cdclk.logical.cdclk,
12024 intel_state->cdclk.actual.cdclk);
12025 } else {
12026 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12027 }
12028
12029 intel_modeset_clear_plls(state);
12030
12031 if (IS_HASWELL(dev_priv))
12032 return haswell_mode_set_planes_workaround(state);
12033
12034 return 0;
12035 }
12036
12037 /*
12038 * Handle calculation of various watermark data at the end of the atomic check
12039 * phase. The code here should be run after the per-crtc and per-plane 'check'
12040 * handlers to ensure that all derived state has been updated.
12041 */
12042 static int calc_watermark_data(struct drm_atomic_state *state)
12043 {
12044 struct drm_device *dev = state->dev;
12045 struct drm_i915_private *dev_priv = to_i915(dev);
12046
12047 /* Is there platform-specific watermark information to calculate? */
12048 if (dev_priv->display.compute_global_watermarks)
12049 return dev_priv->display.compute_global_watermarks(state);
12050
12051 return 0;
12052 }
12053
12054 /**
12055 * intel_atomic_check - validate state object
12056 * @dev: drm device
12057 * @state: state to validate
12058 */
12059 static int intel_atomic_check(struct drm_device *dev,
12060 struct drm_atomic_state *state)
12061 {
12062 struct drm_i915_private *dev_priv = to_i915(dev);
12063 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12064 struct drm_crtc *crtc;
12065 struct drm_crtc_state *old_crtc_state, *crtc_state;
12066 int ret, i;
12067 bool any_ms = false;
12068
12069 ret = drm_atomic_helper_check_modeset(dev, state);
12070 if (ret)
12071 return ret;
12072
12073 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12074 struct intel_crtc_state *pipe_config =
12075 to_intel_crtc_state(crtc_state);
12076
12077 /* Catch I915_MODE_FLAG_INHERITED */
12078 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12079 crtc_state->mode_changed = true;
12080
12081 if (!needs_modeset(crtc_state))
12082 continue;
12083
12084 if (!crtc_state->enable) {
12085 any_ms = true;
12086 continue;
12087 }
12088
12089 /* FIXME: For only active_changed we shouldn't need to do any
12090 * state recomputation at all. */
12091
12092 ret = drm_atomic_add_affected_connectors(state, crtc);
12093 if (ret)
12094 return ret;
12095
12096 ret = intel_modeset_pipe_config(crtc, pipe_config);
12097 if (ret) {
12098 intel_dump_pipe_config(to_intel_crtc(crtc),
12099 pipe_config, "[failed]");
12100 return ret;
12101 }
12102
12103 if (i915.fastboot &&
12104 intel_pipe_config_compare(dev_priv,
12105 to_intel_crtc_state(old_crtc_state),
12106 pipe_config, true)) {
12107 crtc_state->mode_changed = false;
12108 pipe_config->update_pipe = true;
12109 }
12110
12111 if (needs_modeset(crtc_state))
12112 any_ms = true;
12113
12114 ret = drm_atomic_add_affected_planes(state, crtc);
12115 if (ret)
12116 return ret;
12117
12118 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12119 needs_modeset(crtc_state) ?
12120 "[modeset]" : "[fastset]");
12121 }
12122
12123 if (any_ms) {
12124 ret = intel_modeset_checks(state);
12125
12126 if (ret)
12127 return ret;
12128 } else {
12129 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12130 }
12131
12132 ret = drm_atomic_helper_check_planes(dev, state);
12133 if (ret)
12134 return ret;
12135
12136 intel_fbc_choose_crtc(dev_priv, state);
12137 return calc_watermark_data(state);
12138 }
12139
12140 static int intel_atomic_prepare_commit(struct drm_device *dev,
12141 struct drm_atomic_state *state)
12142 {
12143 struct drm_i915_private *dev_priv = to_i915(dev);
12144 struct drm_crtc_state *crtc_state;
12145 struct drm_crtc *crtc;
12146 int i, ret;
12147
12148 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12149 if (state->legacy_cursor_update)
12150 continue;
12151
12152 ret = intel_crtc_wait_for_pending_flips(crtc);
12153 if (ret)
12154 return ret;
12155
12156 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12157 flush_workqueue(dev_priv->wq);
12158 }
12159
12160 ret = mutex_lock_interruptible(&dev->struct_mutex);
12161 if (ret)
12162 return ret;
12163
12164 ret = drm_atomic_helper_prepare_planes(dev, state);
12165 mutex_unlock(&dev->struct_mutex);
12166
12167 return ret;
12168 }
12169
12170 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12171 {
12172 struct drm_device *dev = crtc->base.dev;
12173
12174 if (!dev->max_vblank_count)
12175 return drm_accurate_vblank_count(&crtc->base);
12176
12177 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12178 }
12179
12180 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12181 struct drm_i915_private *dev_priv,
12182 unsigned crtc_mask)
12183 {
12184 unsigned last_vblank_count[I915_MAX_PIPES];
12185 enum pipe pipe;
12186 int ret;
12187
12188 if (!crtc_mask)
12189 return;
12190
12191 for_each_pipe(dev_priv, pipe) {
12192 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12193 pipe);
12194
12195 if (!((1 << pipe) & crtc_mask))
12196 continue;
12197
12198 ret = drm_crtc_vblank_get(&crtc->base);
12199 if (WARN_ON(ret != 0)) {
12200 crtc_mask &= ~(1 << pipe);
12201 continue;
12202 }
12203
12204 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12205 }
12206
12207 for_each_pipe(dev_priv, pipe) {
12208 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12209 pipe);
12210 long lret;
12211
12212 if (!((1 << pipe) & crtc_mask))
12213 continue;
12214
12215 lret = wait_event_timeout(dev->vblank[pipe].queue,
12216 last_vblank_count[pipe] !=
12217 drm_crtc_vblank_count(&crtc->base),
12218 msecs_to_jiffies(50));
12219
12220 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12221
12222 drm_crtc_vblank_put(&crtc->base);
12223 }
12224 }
12225
12226 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12227 {
12228 /* fb updated, need to unpin old fb */
12229 if (crtc_state->fb_changed)
12230 return true;
12231
12232 /* wm changes, need vblank before final wm's */
12233 if (crtc_state->update_wm_post)
12234 return true;
12235
12236 if (crtc_state->wm.need_postvbl_update)
12237 return true;
12238
12239 return false;
12240 }
12241
12242 static void intel_update_crtc(struct drm_crtc *crtc,
12243 struct drm_atomic_state *state,
12244 struct drm_crtc_state *old_crtc_state,
12245 struct drm_crtc_state *new_crtc_state,
12246 unsigned int *crtc_vblank_mask)
12247 {
12248 struct drm_device *dev = crtc->dev;
12249 struct drm_i915_private *dev_priv = to_i915(dev);
12250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12251 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12252 bool modeset = needs_modeset(new_crtc_state);
12253
12254 if (modeset) {
12255 update_scanline_offset(intel_crtc);
12256 dev_priv->display.crtc_enable(pipe_config, state);
12257 } else {
12258 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12259 pipe_config);
12260 }
12261
12262 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12263 intel_fbc_enable(
12264 intel_crtc, pipe_config,
12265 to_intel_plane_state(crtc->primary->state));
12266 }
12267
12268 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12269
12270 if (needs_vblank_wait(pipe_config))
12271 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12272 }
12273
12274 static void intel_update_crtcs(struct drm_atomic_state *state,
12275 unsigned int *crtc_vblank_mask)
12276 {
12277 struct drm_crtc *crtc;
12278 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12279 int i;
12280
12281 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12282 if (!new_crtc_state->active)
12283 continue;
12284
12285 intel_update_crtc(crtc, state, old_crtc_state,
12286 new_crtc_state, crtc_vblank_mask);
12287 }
12288 }
12289
12290 static void skl_update_crtcs(struct drm_atomic_state *state,
12291 unsigned int *crtc_vblank_mask)
12292 {
12293 struct drm_i915_private *dev_priv = to_i915(state->dev);
12294 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12295 struct drm_crtc *crtc;
12296 struct intel_crtc *intel_crtc;
12297 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12298 struct intel_crtc_state *cstate;
12299 unsigned int updated = 0;
12300 bool progress;
12301 enum pipe pipe;
12302 int i;
12303
12304 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12305
12306 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12307 /* ignore allocations for crtc's that have been turned off. */
12308 if (new_crtc_state->active)
12309 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12310
12311 /*
12312 * Whenever the number of active pipes changes, we need to make sure we
12313 * update the pipes in the right order so that their ddb allocations
12314 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12315 * cause pipe underruns and other bad stuff.
12316 */
12317 do {
12318 progress = false;
12319
12320 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12321 bool vbl_wait = false;
12322 unsigned int cmask = drm_crtc_mask(crtc);
12323
12324 intel_crtc = to_intel_crtc(crtc);
12325 cstate = to_intel_crtc_state(crtc->state);
12326 pipe = intel_crtc->pipe;
12327
12328 if (updated & cmask || !cstate->base.active)
12329 continue;
12330
12331 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12332 continue;
12333
12334 updated |= cmask;
12335 entries[i] = &cstate->wm.skl.ddb;
12336
12337 /*
12338 * If this is an already active pipe, it's DDB changed,
12339 * and this isn't the last pipe that needs updating
12340 * then we need to wait for a vblank to pass for the
12341 * new ddb allocation to take effect.
12342 */
12343 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12344 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12345 !new_crtc_state->active_changed &&
12346 intel_state->wm_results.dirty_pipes != updated)
12347 vbl_wait = true;
12348
12349 intel_update_crtc(crtc, state, old_crtc_state,
12350 new_crtc_state, crtc_vblank_mask);
12351
12352 if (vbl_wait)
12353 intel_wait_for_vblank(dev_priv, pipe);
12354
12355 progress = true;
12356 }
12357 } while (progress);
12358 }
12359
12360 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12361 {
12362 struct intel_atomic_state *state, *next;
12363 struct llist_node *freed;
12364
12365 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12366 llist_for_each_entry_safe(state, next, freed, freed)
12367 drm_atomic_state_put(&state->base);
12368 }
12369
12370 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12371 {
12372 struct drm_i915_private *dev_priv =
12373 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12374
12375 intel_atomic_helper_free_state(dev_priv);
12376 }
12377
12378 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12379 {
12380 struct drm_device *dev = state->dev;
12381 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12382 struct drm_i915_private *dev_priv = to_i915(dev);
12383 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12384 struct drm_crtc *crtc;
12385 struct intel_crtc_state *intel_cstate;
12386 bool hw_check = intel_state->modeset;
12387 u64 put_domains[I915_MAX_PIPES] = {};
12388 unsigned crtc_vblank_mask = 0;
12389 int i;
12390
12391 drm_atomic_helper_wait_for_dependencies(state);
12392
12393 if (intel_state->modeset)
12394 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12395
12396 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12398
12399 if (needs_modeset(new_crtc_state) ||
12400 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12401 hw_check = true;
12402
12403 put_domains[to_intel_crtc(crtc)->pipe] =
12404 modeset_get_crtc_power_domains(crtc,
12405 to_intel_crtc_state(new_crtc_state));
12406 }
12407
12408 if (!needs_modeset(new_crtc_state))
12409 continue;
12410
12411 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12412 to_intel_crtc_state(new_crtc_state));
12413
12414 if (old_crtc_state->active) {
12415 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12416 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12417 intel_crtc->active = false;
12418 intel_fbc_disable(intel_crtc);
12419 intel_disable_shared_dpll(intel_crtc);
12420
12421 /*
12422 * Underruns don't always raise
12423 * interrupts, so check manually.
12424 */
12425 intel_check_cpu_fifo_underruns(dev_priv);
12426 intel_check_pch_fifo_underruns(dev_priv);
12427
12428 if (!crtc->state->active) {
12429 /*
12430 * Make sure we don't call initial_watermarks
12431 * for ILK-style watermark updates.
12432 *
12433 * No clue what this is supposed to achieve.
12434 */
12435 if (INTEL_GEN(dev_priv) >= 9)
12436 dev_priv->display.initial_watermarks(intel_state,
12437 to_intel_crtc_state(crtc->state));
12438 }
12439 }
12440 }
12441
12442 /* Only after disabling all output pipelines that will be changed can we
12443 * update the the output configuration. */
12444 intel_modeset_update_crtc_state(state);
12445
12446 if (intel_state->modeset) {
12447 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12448
12449 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12450
12451 /*
12452 * SKL workaround: bspec recommends we disable the SAGV when we
12453 * have more then one pipe enabled
12454 */
12455 if (!intel_can_enable_sagv(state))
12456 intel_disable_sagv(dev_priv);
12457
12458 intel_modeset_verify_disabled(dev, state);
12459 }
12460
12461 /* Complete the events for pipes that have now been disabled */
12462 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12463 bool modeset = needs_modeset(new_crtc_state);
12464
12465 /* Complete events for now disable pipes here. */
12466 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12467 spin_lock_irq(&dev->event_lock);
12468 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12469 spin_unlock_irq(&dev->event_lock);
12470
12471 new_crtc_state->event = NULL;
12472 }
12473 }
12474
12475 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12476 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12477
12478 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12479 * already, but still need the state for the delayed optimization. To
12480 * fix this:
12481 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12482 * - schedule that vblank worker _before_ calling hw_done
12483 * - at the start of commit_tail, cancel it _synchrously
12484 * - switch over to the vblank wait helper in the core after that since
12485 * we don't need out special handling any more.
12486 */
12487 if (!state->legacy_cursor_update)
12488 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12489
12490 /*
12491 * Now that the vblank has passed, we can go ahead and program the
12492 * optimal watermarks on platforms that need two-step watermark
12493 * programming.
12494 *
12495 * TODO: Move this (and other cleanup) to an async worker eventually.
12496 */
12497 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12498 intel_cstate = to_intel_crtc_state(new_crtc_state);
12499
12500 if (dev_priv->display.optimize_watermarks)
12501 dev_priv->display.optimize_watermarks(intel_state,
12502 intel_cstate);
12503 }
12504
12505 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12506 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12507
12508 if (put_domains[i])
12509 modeset_put_power_domains(dev_priv, put_domains[i]);
12510
12511 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12512 }
12513
12514 if (intel_state->modeset && intel_can_enable_sagv(state))
12515 intel_enable_sagv(dev_priv);
12516
12517 drm_atomic_helper_commit_hw_done(state);
12518
12519 if (intel_state->modeset) {
12520 /* As one of the primary mmio accessors, KMS has a high
12521 * likelihood of triggering bugs in unclaimed access. After we
12522 * finish modesetting, see if an error has been flagged, and if
12523 * so enable debugging for the next modeset - and hope we catch
12524 * the culprit.
12525 */
12526 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12527 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12528 }
12529
12530 mutex_lock(&dev->struct_mutex);
12531 drm_atomic_helper_cleanup_planes(dev, state);
12532 mutex_unlock(&dev->struct_mutex);
12533
12534 drm_atomic_helper_commit_cleanup_done(state);
12535
12536 drm_atomic_state_put(state);
12537
12538 intel_atomic_helper_free_state(dev_priv);
12539 }
12540
12541 static void intel_atomic_commit_work(struct work_struct *work)
12542 {
12543 struct drm_atomic_state *state =
12544 container_of(work, struct drm_atomic_state, commit_work);
12545
12546 intel_atomic_commit_tail(state);
12547 }
12548
12549 static int __i915_sw_fence_call
12550 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12551 enum i915_sw_fence_notify notify)
12552 {
12553 struct intel_atomic_state *state =
12554 container_of(fence, struct intel_atomic_state, commit_ready);
12555
12556 switch (notify) {
12557 case FENCE_COMPLETE:
12558 if (state->base.commit_work.func)
12559 queue_work(system_unbound_wq, &state->base.commit_work);
12560 break;
12561
12562 case FENCE_FREE:
12563 {
12564 struct intel_atomic_helper *helper =
12565 &to_i915(state->base.dev)->atomic_helper;
12566
12567 if (llist_add(&state->freed, &helper->free_list))
12568 schedule_work(&helper->free_work);
12569 break;
12570 }
12571 }
12572
12573 return NOTIFY_DONE;
12574 }
12575
12576 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12577 {
12578 struct drm_plane_state *old_plane_state, *new_plane_state;
12579 struct drm_plane *plane;
12580 int i;
12581
12582 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12583 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12584 intel_fb_obj(new_plane_state->fb),
12585 to_intel_plane(plane)->frontbuffer_bit);
12586 }
12587
12588 /**
12589 * intel_atomic_commit - commit validated state object
12590 * @dev: DRM device
12591 * @state: the top-level driver state object
12592 * @nonblock: nonblocking commit
12593 *
12594 * This function commits a top-level state object that has been validated
12595 * with drm_atomic_helper_check().
12596 *
12597 * RETURNS
12598 * Zero for success or -errno.
12599 */
12600 static int intel_atomic_commit(struct drm_device *dev,
12601 struct drm_atomic_state *state,
12602 bool nonblock)
12603 {
12604 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12605 struct drm_i915_private *dev_priv = to_i915(dev);
12606 int ret = 0;
12607
12608 ret = drm_atomic_helper_setup_commit(state, nonblock);
12609 if (ret)
12610 return ret;
12611
12612 drm_atomic_state_get(state);
12613 i915_sw_fence_init(&intel_state->commit_ready,
12614 intel_atomic_commit_ready);
12615
12616 ret = intel_atomic_prepare_commit(dev, state);
12617 if (ret) {
12618 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12619 i915_sw_fence_commit(&intel_state->commit_ready);
12620 return ret;
12621 }
12622
12623 /*
12624 * The intel_legacy_cursor_update() fast path takes care
12625 * of avoiding the vblank waits for simple cursor
12626 * movement and flips. For cursor on/off and size changes,
12627 * we want to perform the vblank waits so that watermark
12628 * updates happen during the correct frames. Gen9+ have
12629 * double buffered watermarks and so shouldn't need this.
12630 *
12631 * Do this after drm_atomic_helper_setup_commit() and
12632 * intel_atomic_prepare_commit() because we still want
12633 * to skip the flip and fb cleanup waits. Although that
12634 * does risk yanking the mapping from under the display
12635 * engine.
12636 *
12637 * FIXME doing watermarks and fb cleanup from a vblank worker
12638 * (assuming we had any) would solve these problems.
12639 */
12640 if (INTEL_GEN(dev_priv) < 9)
12641 state->legacy_cursor_update = false;
12642
12643 drm_atomic_helper_swap_state(state, true);
12644 dev_priv->wm.distrust_bios_wm = false;
12645 intel_shared_dpll_swap_state(state);
12646 intel_atomic_track_fbs(state);
12647
12648 if (intel_state->modeset) {
12649 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
12650 sizeof(intel_state->min_pixclk));
12651 dev_priv->active_crtcs = intel_state->active_crtcs;
12652 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12653 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12654 }
12655
12656 drm_atomic_state_get(state);
12657 INIT_WORK(&state->commit_work,
12658 nonblock ? intel_atomic_commit_work : NULL);
12659
12660 i915_sw_fence_commit(&intel_state->commit_ready);
12661 if (!nonblock) {
12662 i915_sw_fence_wait(&intel_state->commit_ready);
12663 intel_atomic_commit_tail(state);
12664 }
12665
12666 return 0;
12667 }
12668
12669 static const struct drm_crtc_funcs intel_crtc_funcs = {
12670 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12671 .set_config = drm_atomic_helper_set_config,
12672 .set_property = drm_atomic_helper_crtc_set_property,
12673 .destroy = intel_crtc_destroy,
12674 .page_flip = drm_atomic_helper_page_flip,
12675 .atomic_duplicate_state = intel_crtc_duplicate_state,
12676 .atomic_destroy_state = intel_crtc_destroy_state,
12677 .set_crc_source = intel_crtc_set_crc_source,
12678 };
12679
12680 /**
12681 * intel_prepare_plane_fb - Prepare fb for usage on plane
12682 * @plane: drm plane to prepare for
12683 * @fb: framebuffer to prepare for presentation
12684 *
12685 * Prepares a framebuffer for usage on a display plane. Generally this
12686 * involves pinning the underlying object and updating the frontbuffer tracking
12687 * bits. Some older platforms need special physical address handling for
12688 * cursor planes.
12689 *
12690 * Must be called with struct_mutex held.
12691 *
12692 * Returns 0 on success, negative error code on failure.
12693 */
12694 int
12695 intel_prepare_plane_fb(struct drm_plane *plane,
12696 struct drm_plane_state *new_state)
12697 {
12698 struct intel_atomic_state *intel_state =
12699 to_intel_atomic_state(new_state->state);
12700 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12701 struct drm_framebuffer *fb = new_state->fb;
12702 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12703 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12704 int ret;
12705
12706 if (obj) {
12707 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12708 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12709 const int align = intel_cursor_alignment(dev_priv);
12710
12711 ret = i915_gem_object_attach_phys(obj, align);
12712 if (ret) {
12713 DRM_DEBUG_KMS("failed to attach phys object\n");
12714 return ret;
12715 }
12716 } else {
12717 struct i915_vma *vma;
12718
12719 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12720 if (IS_ERR(vma)) {
12721 DRM_DEBUG_KMS("failed to pin object\n");
12722 return PTR_ERR(vma);
12723 }
12724
12725 to_intel_plane_state(new_state)->vma = vma;
12726 }
12727 }
12728
12729 if (!obj && !old_obj)
12730 return 0;
12731
12732 if (old_obj) {
12733 struct drm_crtc_state *crtc_state =
12734 drm_atomic_get_existing_crtc_state(new_state->state,
12735 plane->state->crtc);
12736
12737 /* Big Hammer, we also need to ensure that any pending
12738 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12739 * current scanout is retired before unpinning the old
12740 * framebuffer. Note that we rely on userspace rendering
12741 * into the buffer attached to the pipe they are waiting
12742 * on. If not, userspace generates a GPU hang with IPEHR
12743 * point to the MI_WAIT_FOR_EVENT.
12744 *
12745 * This should only fail upon a hung GPU, in which case we
12746 * can safely continue.
12747 */
12748 if (needs_modeset(crtc_state)) {
12749 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12750 old_obj->resv, NULL,
12751 false, 0,
12752 GFP_KERNEL);
12753 if (ret < 0)
12754 return ret;
12755 }
12756 }
12757
12758 if (new_state->fence) { /* explicit fencing */
12759 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12760 new_state->fence,
12761 I915_FENCE_TIMEOUT,
12762 GFP_KERNEL);
12763 if (ret < 0)
12764 return ret;
12765 }
12766
12767 if (!obj)
12768 return 0;
12769
12770 if (!new_state->fence) { /* implicit fencing */
12771 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12772 obj->resv, NULL,
12773 false, I915_FENCE_TIMEOUT,
12774 GFP_KERNEL);
12775 if (ret < 0)
12776 return ret;
12777
12778 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12779 }
12780
12781 return 0;
12782 }
12783
12784 /**
12785 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12786 * @plane: drm plane to clean up for
12787 * @fb: old framebuffer that was on plane
12788 *
12789 * Cleans up a framebuffer that has just been removed from a plane.
12790 *
12791 * Must be called with struct_mutex held.
12792 */
12793 void
12794 intel_cleanup_plane_fb(struct drm_plane *plane,
12795 struct drm_plane_state *old_state)
12796 {
12797 struct i915_vma *vma;
12798
12799 /* Should only be called after a successful intel_prepare_plane_fb()! */
12800 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12801 if (vma)
12802 intel_unpin_fb_vma(vma);
12803 }
12804
12805 int
12806 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12807 {
12808 struct drm_i915_private *dev_priv;
12809 int max_scale;
12810 int crtc_clock, max_dotclk;
12811
12812 if (!intel_crtc || !crtc_state->base.enable)
12813 return DRM_PLANE_HELPER_NO_SCALING;
12814
12815 dev_priv = to_i915(intel_crtc->base.dev);
12816
12817 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12818 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12819
12820 if (IS_GEMINILAKE(dev_priv))
12821 max_dotclk *= 2;
12822
12823 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12824 return DRM_PLANE_HELPER_NO_SCALING;
12825
12826 /*
12827 * skl max scale is lower of:
12828 * close to 3 but not 3, -1 is for that purpose
12829 * or
12830 * cdclk/crtc_clock
12831 */
12832 max_scale = min((1 << 16) * 3 - 1,
12833 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12834
12835 return max_scale;
12836 }
12837
12838 static int
12839 intel_check_primary_plane(struct intel_plane *plane,
12840 struct intel_crtc_state *crtc_state,
12841 struct intel_plane_state *state)
12842 {
12843 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12844 struct drm_crtc *crtc = state->base.crtc;
12845 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12846 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12847 bool can_position = false;
12848 int ret;
12849
12850 if (INTEL_GEN(dev_priv) >= 9) {
12851 /* use scaler when colorkey is not required */
12852 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12853 min_scale = 1;
12854 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12855 }
12856 can_position = true;
12857 }
12858
12859 ret = drm_plane_helper_check_state(&state->base,
12860 &state->clip,
12861 min_scale, max_scale,
12862 can_position, true);
12863 if (ret)
12864 return ret;
12865
12866 if (!state->base.fb)
12867 return 0;
12868
12869 if (INTEL_GEN(dev_priv) >= 9) {
12870 ret = skl_check_plane_surface(state);
12871 if (ret)
12872 return ret;
12873
12874 state->ctl = skl_plane_ctl(crtc_state, state);
12875 } else {
12876 ret = i9xx_check_plane_surface(state);
12877 if (ret)
12878 return ret;
12879
12880 state->ctl = i9xx_plane_ctl(crtc_state, state);
12881 }
12882
12883 return 0;
12884 }
12885
12886 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12887 struct drm_crtc_state *old_crtc_state)
12888 {
12889 struct drm_device *dev = crtc->dev;
12890 struct drm_i915_private *dev_priv = to_i915(dev);
12891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12892 struct intel_crtc_state *intel_cstate =
12893 to_intel_crtc_state(crtc->state);
12894 struct intel_crtc_state *old_intel_cstate =
12895 to_intel_crtc_state(old_crtc_state);
12896 struct intel_atomic_state *old_intel_state =
12897 to_intel_atomic_state(old_crtc_state->state);
12898 bool modeset = needs_modeset(crtc->state);
12899
12900 if (!modeset &&
12901 (intel_cstate->base.color_mgmt_changed ||
12902 intel_cstate->update_pipe)) {
12903 intel_color_set_csc(crtc->state);
12904 intel_color_load_luts(crtc->state);
12905 }
12906
12907 /* Perform vblank evasion around commit operation */
12908 intel_pipe_update_start(intel_crtc);
12909
12910 if (modeset)
12911 goto out;
12912
12913 if (intel_cstate->update_pipe)
12914 intel_update_pipe_config(intel_crtc, old_intel_cstate);
12915 else if (INTEL_GEN(dev_priv) >= 9)
12916 skl_detach_scalers(intel_crtc);
12917
12918 out:
12919 if (dev_priv->display.atomic_update_watermarks)
12920 dev_priv->display.atomic_update_watermarks(old_intel_state,
12921 intel_cstate);
12922 }
12923
12924 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12925 struct drm_crtc_state *old_crtc_state)
12926 {
12927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12928
12929 intel_pipe_update_end(intel_crtc, NULL);
12930 }
12931
12932 /**
12933 * intel_plane_destroy - destroy a plane
12934 * @plane: plane to destroy
12935 *
12936 * Common destruction function for all types of planes (primary, cursor,
12937 * sprite).
12938 */
12939 void intel_plane_destroy(struct drm_plane *plane)
12940 {
12941 drm_plane_cleanup(plane);
12942 kfree(to_intel_plane(plane));
12943 }
12944
12945 const struct drm_plane_funcs intel_plane_funcs = {
12946 .update_plane = drm_atomic_helper_update_plane,
12947 .disable_plane = drm_atomic_helper_disable_plane,
12948 .destroy = intel_plane_destroy,
12949 .set_property = drm_atomic_helper_plane_set_property,
12950 .atomic_get_property = intel_plane_atomic_get_property,
12951 .atomic_set_property = intel_plane_atomic_set_property,
12952 .atomic_duplicate_state = intel_plane_duplicate_state,
12953 .atomic_destroy_state = intel_plane_destroy_state,
12954 };
12955
12956 static int
12957 intel_legacy_cursor_update(struct drm_plane *plane,
12958 struct drm_crtc *crtc,
12959 struct drm_framebuffer *fb,
12960 int crtc_x, int crtc_y,
12961 unsigned int crtc_w, unsigned int crtc_h,
12962 uint32_t src_x, uint32_t src_y,
12963 uint32_t src_w, uint32_t src_h,
12964 struct drm_modeset_acquire_ctx *ctx)
12965 {
12966 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12967 int ret;
12968 struct drm_plane_state *old_plane_state, *new_plane_state;
12969 struct intel_plane *intel_plane = to_intel_plane(plane);
12970 struct drm_framebuffer *old_fb;
12971 struct drm_crtc_state *crtc_state = crtc->state;
12972 struct i915_vma *old_vma;
12973
12974 /*
12975 * When crtc is inactive or there is a modeset pending,
12976 * wait for it to complete in the slowpath
12977 */
12978 if (!crtc_state->active || needs_modeset(crtc_state) ||
12979 to_intel_crtc_state(crtc_state)->update_pipe)
12980 goto slow;
12981
12982 old_plane_state = plane->state;
12983
12984 /*
12985 * If any parameters change that may affect watermarks,
12986 * take the slowpath. Only changing fb or position should be
12987 * in the fastpath.
12988 */
12989 if (old_plane_state->crtc != crtc ||
12990 old_plane_state->src_w != src_w ||
12991 old_plane_state->src_h != src_h ||
12992 old_plane_state->crtc_w != crtc_w ||
12993 old_plane_state->crtc_h != crtc_h ||
12994 !old_plane_state->fb != !fb)
12995 goto slow;
12996
12997 new_plane_state = intel_plane_duplicate_state(plane);
12998 if (!new_plane_state)
12999 return -ENOMEM;
13000
13001 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13002
13003 new_plane_state->src_x = src_x;
13004 new_plane_state->src_y = src_y;
13005 new_plane_state->src_w = src_w;
13006 new_plane_state->src_h = src_h;
13007 new_plane_state->crtc_x = crtc_x;
13008 new_plane_state->crtc_y = crtc_y;
13009 new_plane_state->crtc_w = crtc_w;
13010 new_plane_state->crtc_h = crtc_h;
13011
13012 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13013 to_intel_plane_state(new_plane_state));
13014 if (ret)
13015 goto out_free;
13016
13017 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13018 if (ret)
13019 goto out_free;
13020
13021 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13022 int align = intel_cursor_alignment(dev_priv);
13023
13024 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13025 if (ret) {
13026 DRM_DEBUG_KMS("failed to attach phys object\n");
13027 goto out_unlock;
13028 }
13029 } else {
13030 struct i915_vma *vma;
13031
13032 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13033 if (IS_ERR(vma)) {
13034 DRM_DEBUG_KMS("failed to pin object\n");
13035
13036 ret = PTR_ERR(vma);
13037 goto out_unlock;
13038 }
13039
13040 to_intel_plane_state(new_plane_state)->vma = vma;
13041 }
13042
13043 old_fb = old_plane_state->fb;
13044 old_vma = to_intel_plane_state(old_plane_state)->vma;
13045
13046 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13047 intel_plane->frontbuffer_bit);
13048
13049 /* Swap plane state */
13050 new_plane_state->fence = old_plane_state->fence;
13051 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13052 new_plane_state->fence = NULL;
13053 new_plane_state->fb = old_fb;
13054 to_intel_plane_state(new_plane_state)->vma = old_vma;
13055
13056 if (plane->state->visible) {
13057 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13058 intel_plane->update_plane(intel_plane,
13059 to_intel_crtc_state(crtc->state),
13060 to_intel_plane_state(plane->state));
13061 } else {
13062 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13063 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13064 }
13065
13066 intel_cleanup_plane_fb(plane, new_plane_state);
13067
13068 out_unlock:
13069 mutex_unlock(&dev_priv->drm.struct_mutex);
13070 out_free:
13071 intel_plane_destroy_state(plane, new_plane_state);
13072 return ret;
13073
13074 slow:
13075 return drm_atomic_helper_update_plane(plane, crtc, fb,
13076 crtc_x, crtc_y, crtc_w, crtc_h,
13077 src_x, src_y, src_w, src_h, ctx);
13078 }
13079
13080 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13081 .update_plane = intel_legacy_cursor_update,
13082 .disable_plane = drm_atomic_helper_disable_plane,
13083 .destroy = intel_plane_destroy,
13084 .set_property = drm_atomic_helper_plane_set_property,
13085 .atomic_get_property = intel_plane_atomic_get_property,
13086 .atomic_set_property = intel_plane_atomic_set_property,
13087 .atomic_duplicate_state = intel_plane_duplicate_state,
13088 .atomic_destroy_state = intel_plane_destroy_state,
13089 };
13090
13091 static struct intel_plane *
13092 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13093 {
13094 struct intel_plane *primary = NULL;
13095 struct intel_plane_state *state = NULL;
13096 const uint32_t *intel_primary_formats;
13097 unsigned int supported_rotations;
13098 unsigned int num_formats;
13099 int ret;
13100
13101 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13102 if (!primary) {
13103 ret = -ENOMEM;
13104 goto fail;
13105 }
13106
13107 state = intel_create_plane_state(&primary->base);
13108 if (!state) {
13109 ret = -ENOMEM;
13110 goto fail;
13111 }
13112
13113 primary->base.state = &state->base;
13114
13115 primary->can_scale = false;
13116 primary->max_downscale = 1;
13117 if (INTEL_GEN(dev_priv) >= 9) {
13118 primary->can_scale = true;
13119 state->scaler_id = -1;
13120 }
13121 primary->pipe = pipe;
13122 /*
13123 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13124 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13125 */
13126 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13127 primary->plane = (enum plane) !pipe;
13128 else
13129 primary->plane = (enum plane) pipe;
13130 primary->id = PLANE_PRIMARY;
13131 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13132 primary->check_plane = intel_check_primary_plane;
13133
13134 if (INTEL_GEN(dev_priv) >= 9) {
13135 intel_primary_formats = skl_primary_formats;
13136 num_formats = ARRAY_SIZE(skl_primary_formats);
13137
13138 primary->update_plane = skylake_update_primary_plane;
13139 primary->disable_plane = skylake_disable_primary_plane;
13140 } else if (INTEL_GEN(dev_priv) >= 4) {
13141 intel_primary_formats = i965_primary_formats;
13142 num_formats = ARRAY_SIZE(i965_primary_formats);
13143
13144 primary->update_plane = i9xx_update_primary_plane;
13145 primary->disable_plane = i9xx_disable_primary_plane;
13146 } else {
13147 intel_primary_formats = i8xx_primary_formats;
13148 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13149
13150 primary->update_plane = i9xx_update_primary_plane;
13151 primary->disable_plane = i9xx_disable_primary_plane;
13152 }
13153
13154 if (INTEL_GEN(dev_priv) >= 9)
13155 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13156 0, &intel_plane_funcs,
13157 intel_primary_formats, num_formats,
13158 DRM_PLANE_TYPE_PRIMARY,
13159 "plane 1%c", pipe_name(pipe));
13160 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13161 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13162 0, &intel_plane_funcs,
13163 intel_primary_formats, num_formats,
13164 DRM_PLANE_TYPE_PRIMARY,
13165 "primary %c", pipe_name(pipe));
13166 else
13167 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13168 0, &intel_plane_funcs,
13169 intel_primary_formats, num_formats,
13170 DRM_PLANE_TYPE_PRIMARY,
13171 "plane %c", plane_name(primary->plane));
13172 if (ret)
13173 goto fail;
13174
13175 if (INTEL_GEN(dev_priv) >= 9) {
13176 supported_rotations =
13177 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13178 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13179 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13180 supported_rotations =
13181 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13182 DRM_MODE_REFLECT_X;
13183 } else if (INTEL_GEN(dev_priv) >= 4) {
13184 supported_rotations =
13185 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13186 } else {
13187 supported_rotations = DRM_MODE_ROTATE_0;
13188 }
13189
13190 if (INTEL_GEN(dev_priv) >= 4)
13191 drm_plane_create_rotation_property(&primary->base,
13192 DRM_MODE_ROTATE_0,
13193 supported_rotations);
13194
13195 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13196
13197 return primary;
13198
13199 fail:
13200 kfree(state);
13201 kfree(primary);
13202
13203 return ERR_PTR(ret);
13204 }
13205
13206 static struct intel_plane *
13207 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13208 enum pipe pipe)
13209 {
13210 struct intel_plane *cursor = NULL;
13211 struct intel_plane_state *state = NULL;
13212 int ret;
13213
13214 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13215 if (!cursor) {
13216 ret = -ENOMEM;
13217 goto fail;
13218 }
13219
13220 state = intel_create_plane_state(&cursor->base);
13221 if (!state) {
13222 ret = -ENOMEM;
13223 goto fail;
13224 }
13225
13226 cursor->base.state = &state->base;
13227
13228 cursor->can_scale = false;
13229 cursor->max_downscale = 1;
13230 cursor->pipe = pipe;
13231 cursor->plane = pipe;
13232 cursor->id = PLANE_CURSOR;
13233 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13234
13235 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13236 cursor->update_plane = i845_update_cursor;
13237 cursor->disable_plane = i845_disable_cursor;
13238 cursor->check_plane = i845_check_cursor;
13239 } else {
13240 cursor->update_plane = i9xx_update_cursor;
13241 cursor->disable_plane = i9xx_disable_cursor;
13242 cursor->check_plane = i9xx_check_cursor;
13243 }
13244
13245 cursor->cursor.base = ~0;
13246 cursor->cursor.cntl = ~0;
13247
13248 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13249 cursor->cursor.size = ~0;
13250
13251 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13252 0, &intel_cursor_plane_funcs,
13253 intel_cursor_formats,
13254 ARRAY_SIZE(intel_cursor_formats),
13255 DRM_PLANE_TYPE_CURSOR,
13256 "cursor %c", pipe_name(pipe));
13257 if (ret)
13258 goto fail;
13259
13260 if (INTEL_GEN(dev_priv) >= 4)
13261 drm_plane_create_rotation_property(&cursor->base,
13262 DRM_MODE_ROTATE_0,
13263 DRM_MODE_ROTATE_0 |
13264 DRM_MODE_ROTATE_180);
13265
13266 if (INTEL_GEN(dev_priv) >= 9)
13267 state->scaler_id = -1;
13268
13269 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13270
13271 return cursor;
13272
13273 fail:
13274 kfree(state);
13275 kfree(cursor);
13276
13277 return ERR_PTR(ret);
13278 }
13279
13280 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13281 struct intel_crtc_state *crtc_state)
13282 {
13283 struct intel_crtc_scaler_state *scaler_state =
13284 &crtc_state->scaler_state;
13285 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13286 int i;
13287
13288 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13289 if (!crtc->num_scalers)
13290 return;
13291
13292 for (i = 0; i < crtc->num_scalers; i++) {
13293 struct intel_scaler *scaler = &scaler_state->scalers[i];
13294
13295 scaler->in_use = 0;
13296 scaler->mode = PS_SCALER_MODE_DYN;
13297 }
13298
13299 scaler_state->scaler_id = -1;
13300 }
13301
13302 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13303 {
13304 struct intel_crtc *intel_crtc;
13305 struct intel_crtc_state *crtc_state = NULL;
13306 struct intel_plane *primary = NULL;
13307 struct intel_plane *cursor = NULL;
13308 int sprite, ret;
13309
13310 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13311 if (!intel_crtc)
13312 return -ENOMEM;
13313
13314 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13315 if (!crtc_state) {
13316 ret = -ENOMEM;
13317 goto fail;
13318 }
13319 intel_crtc->config = crtc_state;
13320 intel_crtc->base.state = &crtc_state->base;
13321 crtc_state->base.crtc = &intel_crtc->base;
13322
13323 primary = intel_primary_plane_create(dev_priv, pipe);
13324 if (IS_ERR(primary)) {
13325 ret = PTR_ERR(primary);
13326 goto fail;
13327 }
13328 intel_crtc->plane_ids_mask |= BIT(primary->id);
13329
13330 for_each_sprite(dev_priv, pipe, sprite) {
13331 struct intel_plane *plane;
13332
13333 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13334 if (IS_ERR(plane)) {
13335 ret = PTR_ERR(plane);
13336 goto fail;
13337 }
13338 intel_crtc->plane_ids_mask |= BIT(plane->id);
13339 }
13340
13341 cursor = intel_cursor_plane_create(dev_priv, pipe);
13342 if (IS_ERR(cursor)) {
13343 ret = PTR_ERR(cursor);
13344 goto fail;
13345 }
13346 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13347
13348 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13349 &primary->base, &cursor->base,
13350 &intel_crtc_funcs,
13351 "pipe %c", pipe_name(pipe));
13352 if (ret)
13353 goto fail;
13354
13355 intel_crtc->pipe = pipe;
13356 intel_crtc->plane = primary->plane;
13357
13358 /* initialize shared scalers */
13359 intel_crtc_init_scalers(intel_crtc, crtc_state);
13360
13361 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13362 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13363 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13364 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13365
13366 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13367
13368 intel_color_init(&intel_crtc->base);
13369
13370 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13371
13372 return 0;
13373
13374 fail:
13375 /*
13376 * drm_mode_config_cleanup() will free up any
13377 * crtcs/planes already initialized.
13378 */
13379 kfree(crtc_state);
13380 kfree(intel_crtc);
13381
13382 return ret;
13383 }
13384
13385 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13386 {
13387 struct drm_device *dev = connector->base.dev;
13388
13389 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13390
13391 if (!connector->base.state->crtc)
13392 return INVALID_PIPE;
13393
13394 return to_intel_crtc(connector->base.state->crtc)->pipe;
13395 }
13396
13397 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13398 struct drm_file *file)
13399 {
13400 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13401 struct drm_crtc *drmmode_crtc;
13402 struct intel_crtc *crtc;
13403
13404 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13405 if (!drmmode_crtc)
13406 return -ENOENT;
13407
13408 crtc = to_intel_crtc(drmmode_crtc);
13409 pipe_from_crtc_id->pipe = crtc->pipe;
13410
13411 return 0;
13412 }
13413
13414 static int intel_encoder_clones(struct intel_encoder *encoder)
13415 {
13416 struct drm_device *dev = encoder->base.dev;
13417 struct intel_encoder *source_encoder;
13418 int index_mask = 0;
13419 int entry = 0;
13420
13421 for_each_intel_encoder(dev, source_encoder) {
13422 if (encoders_cloneable(encoder, source_encoder))
13423 index_mask |= (1 << entry);
13424
13425 entry++;
13426 }
13427
13428 return index_mask;
13429 }
13430
13431 static bool has_edp_a(struct drm_i915_private *dev_priv)
13432 {
13433 if (!IS_MOBILE(dev_priv))
13434 return false;
13435
13436 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13437 return false;
13438
13439 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13440 return false;
13441
13442 return true;
13443 }
13444
13445 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13446 {
13447 if (INTEL_GEN(dev_priv) >= 9)
13448 return false;
13449
13450 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13451 return false;
13452
13453 if (IS_CHERRYVIEW(dev_priv))
13454 return false;
13455
13456 if (HAS_PCH_LPT_H(dev_priv) &&
13457 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13458 return false;
13459
13460 /* DDI E can't be used if DDI A requires 4 lanes */
13461 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13462 return false;
13463
13464 if (!dev_priv->vbt.int_crt_support)
13465 return false;
13466
13467 return true;
13468 }
13469
13470 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13471 {
13472 int pps_num;
13473 int pps_idx;
13474
13475 if (HAS_DDI(dev_priv))
13476 return;
13477 /*
13478 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13479 * everywhere where registers can be write protected.
13480 */
13481 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13482 pps_num = 2;
13483 else
13484 pps_num = 1;
13485
13486 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13487 u32 val = I915_READ(PP_CONTROL(pps_idx));
13488
13489 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13490 I915_WRITE(PP_CONTROL(pps_idx), val);
13491 }
13492 }
13493
13494 static void intel_pps_init(struct drm_i915_private *dev_priv)
13495 {
13496 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13497 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13498 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13499 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13500 else
13501 dev_priv->pps_mmio_base = PPS_BASE;
13502
13503 intel_pps_unlock_regs_wa(dev_priv);
13504 }
13505
13506 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13507 {
13508 struct intel_encoder *encoder;
13509 bool dpd_is_edp = false;
13510
13511 intel_pps_init(dev_priv);
13512
13513 /*
13514 * intel_edp_init_connector() depends on this completing first, to
13515 * prevent the registeration of both eDP and LVDS and the incorrect
13516 * sharing of the PPS.
13517 */
13518 intel_lvds_init(dev_priv);
13519
13520 if (intel_crt_present(dev_priv))
13521 intel_crt_init(dev_priv);
13522
13523 if (IS_GEN9_LP(dev_priv)) {
13524 /*
13525 * FIXME: Broxton doesn't support port detection via the
13526 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13527 * detect the ports.
13528 */
13529 intel_ddi_init(dev_priv, PORT_A);
13530 intel_ddi_init(dev_priv, PORT_B);
13531 intel_ddi_init(dev_priv, PORT_C);
13532
13533 intel_dsi_init(dev_priv);
13534 } else if (HAS_DDI(dev_priv)) {
13535 int found;
13536
13537 /*
13538 * Haswell uses DDI functions to detect digital outputs.
13539 * On SKL pre-D0 the strap isn't connected, so we assume
13540 * it's there.
13541 */
13542 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13543 /* WaIgnoreDDIAStrap: skl */
13544 if (found || IS_GEN9_BC(dev_priv))
13545 intel_ddi_init(dev_priv, PORT_A);
13546
13547 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13548 * register */
13549 found = I915_READ(SFUSE_STRAP);
13550
13551 if (found & SFUSE_STRAP_DDIB_DETECTED)
13552 intel_ddi_init(dev_priv, PORT_B);
13553 if (found & SFUSE_STRAP_DDIC_DETECTED)
13554 intel_ddi_init(dev_priv, PORT_C);
13555 if (found & SFUSE_STRAP_DDID_DETECTED)
13556 intel_ddi_init(dev_priv, PORT_D);
13557 /*
13558 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13559 */
13560 if (IS_GEN9_BC(dev_priv) &&
13561 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13562 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13563 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13564 intel_ddi_init(dev_priv, PORT_E);
13565
13566 } else if (HAS_PCH_SPLIT(dev_priv)) {
13567 int found;
13568 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
13569
13570 if (has_edp_a(dev_priv))
13571 intel_dp_init(dev_priv, DP_A, PORT_A);
13572
13573 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13574 /* PCH SDVOB multiplex with HDMIB */
13575 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13576 if (!found)
13577 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13578 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13579 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13580 }
13581
13582 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13583 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13584
13585 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13586 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13587
13588 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13589 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13590
13591 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13592 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13593 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13594 bool has_edp, has_port;
13595
13596 /*
13597 * The DP_DETECTED bit is the latched state of the DDC
13598 * SDA pin at boot. However since eDP doesn't require DDC
13599 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13600 * eDP ports may have been muxed to an alternate function.
13601 * Thus we can't rely on the DP_DETECTED bit alone to detect
13602 * eDP ports. Consult the VBT as well as DP_DETECTED to
13603 * detect eDP ports.
13604 *
13605 * Sadly the straps seem to be missing sometimes even for HDMI
13606 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13607 * and VBT for the presence of the port. Additionally we can't
13608 * trust the port type the VBT declares as we've seen at least
13609 * HDMI ports that the VBT claim are DP or eDP.
13610 */
13611 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
13612 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13613 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13614 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13615 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13616 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13617
13618 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
13619 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13620 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13621 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13622 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13623 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13624
13625 if (IS_CHERRYVIEW(dev_priv)) {
13626 /*
13627 * eDP not supported on port D,
13628 * so no need to worry about it
13629 */
13630 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13631 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13632 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13633 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13634 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13635 }
13636
13637 intel_dsi_init(dev_priv);
13638 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13639 bool found = false;
13640
13641 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13642 DRM_DEBUG_KMS("probing SDVOB\n");
13643 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13644 if (!found && IS_G4X(dev_priv)) {
13645 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13646 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13647 }
13648
13649 if (!found && IS_G4X(dev_priv))
13650 intel_dp_init(dev_priv, DP_B, PORT_B);
13651 }
13652
13653 /* Before G4X SDVOC doesn't have its own detect register */
13654
13655 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13656 DRM_DEBUG_KMS("probing SDVOC\n");
13657 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13658 }
13659
13660 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13661
13662 if (IS_G4X(dev_priv)) {
13663 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13664 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13665 }
13666 if (IS_G4X(dev_priv))
13667 intel_dp_init(dev_priv, DP_C, PORT_C);
13668 }
13669
13670 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13671 intel_dp_init(dev_priv, DP_D, PORT_D);
13672 } else if (IS_GEN2(dev_priv))
13673 intel_dvo_init(dev_priv);
13674
13675 if (SUPPORTS_TV(dev_priv))
13676 intel_tv_init(dev_priv);
13677
13678 intel_psr_init(dev_priv);
13679
13680 for_each_intel_encoder(&dev_priv->drm, encoder) {
13681 encoder->base.possible_crtcs = encoder->crtc_mask;
13682 encoder->base.possible_clones =
13683 intel_encoder_clones(encoder);
13684 }
13685
13686 intel_init_pch_refclk(dev_priv);
13687
13688 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13689 }
13690
13691 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13692 {
13693 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13694
13695 drm_framebuffer_cleanup(fb);
13696
13697 i915_gem_object_lock(intel_fb->obj);
13698 WARN_ON(!intel_fb->obj->framebuffer_references--);
13699 i915_gem_object_unlock(intel_fb->obj);
13700
13701 i915_gem_object_put(intel_fb->obj);
13702
13703 kfree(intel_fb);
13704 }
13705
13706 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13707 struct drm_file *file,
13708 unsigned int *handle)
13709 {
13710 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13711 struct drm_i915_gem_object *obj = intel_fb->obj;
13712
13713 if (obj->userptr.mm) {
13714 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13715 return -EINVAL;
13716 }
13717
13718 return drm_gem_handle_create(file, &obj->base, handle);
13719 }
13720
13721 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13722 struct drm_file *file,
13723 unsigned flags, unsigned color,
13724 struct drm_clip_rect *clips,
13725 unsigned num_clips)
13726 {
13727 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13728
13729 i915_gem_object_flush_if_display(obj);
13730 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13731
13732 return 0;
13733 }
13734
13735 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13736 .destroy = intel_user_framebuffer_destroy,
13737 .create_handle = intel_user_framebuffer_create_handle,
13738 .dirty = intel_user_framebuffer_dirty,
13739 };
13740
13741 static
13742 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13743 uint64_t fb_modifier, uint32_t pixel_format)
13744 {
13745 u32 gen = INTEL_GEN(dev_priv);
13746
13747 if (gen >= 9) {
13748 int cpp = drm_format_plane_cpp(pixel_format, 0);
13749
13750 /* "The stride in bytes must not exceed the of the size of 8K
13751 * pixels and 32K bytes."
13752 */
13753 return min(8192 * cpp, 32768);
13754 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13755 return 32*1024;
13756 } else if (gen >= 4) {
13757 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13758 return 16*1024;
13759 else
13760 return 32*1024;
13761 } else if (gen >= 3) {
13762 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13763 return 8*1024;
13764 else
13765 return 16*1024;
13766 } else {
13767 /* XXX DSPC is limited to 4k tiled */
13768 return 8*1024;
13769 }
13770 }
13771
13772 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13773 struct drm_i915_gem_object *obj,
13774 struct drm_mode_fb_cmd2 *mode_cmd)
13775 {
13776 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13777 struct drm_format_name_buf format_name;
13778 u32 pitch_limit, stride_alignment;
13779 unsigned int tiling, stride;
13780 int ret = -EINVAL;
13781
13782 i915_gem_object_lock(obj);
13783 obj->framebuffer_references++;
13784 tiling = i915_gem_object_get_tiling(obj);
13785 stride = i915_gem_object_get_stride(obj);
13786 i915_gem_object_unlock(obj);
13787
13788 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13789 /*
13790 * If there's a fence, enforce that
13791 * the fb modifier and tiling mode match.
13792 */
13793 if (tiling != I915_TILING_NONE &&
13794 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13795 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13796 goto err;
13797 }
13798 } else {
13799 if (tiling == I915_TILING_X) {
13800 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13801 } else if (tiling == I915_TILING_Y) {
13802 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13803 goto err;
13804 }
13805 }
13806
13807 /* Passed in modifier sanity checking. */
13808 switch (mode_cmd->modifier[0]) {
13809 case I915_FORMAT_MOD_Y_TILED:
13810 case I915_FORMAT_MOD_Yf_TILED:
13811 if (INTEL_GEN(dev_priv) < 9) {
13812 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13813 mode_cmd->modifier[0]);
13814 goto err;
13815 }
13816 case DRM_FORMAT_MOD_LINEAR:
13817 case I915_FORMAT_MOD_X_TILED:
13818 break;
13819 default:
13820 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13821 mode_cmd->modifier[0]);
13822 goto err;
13823 }
13824
13825 /*
13826 * gen2/3 display engine uses the fence if present,
13827 * so the tiling mode must match the fb modifier exactly.
13828 */
13829 if (INTEL_INFO(dev_priv)->gen < 4 &&
13830 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13831 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13832 goto err;
13833 }
13834
13835 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13836 mode_cmd->pixel_format);
13837 if (mode_cmd->pitches[0] > pitch_limit) {
13838 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13839 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13840 "tiled" : "linear",
13841 mode_cmd->pitches[0], pitch_limit);
13842 goto err;
13843 }
13844
13845 /*
13846 * If there's a fence, enforce that
13847 * the fb pitch and fence stride match.
13848 */
13849 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13850 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13851 mode_cmd->pitches[0], stride);
13852 goto err;
13853 }
13854
13855 /* Reject formats not supported by any plane early. */
13856 switch (mode_cmd->pixel_format) {
13857 case DRM_FORMAT_C8:
13858 case DRM_FORMAT_RGB565:
13859 case DRM_FORMAT_XRGB8888:
13860 case DRM_FORMAT_ARGB8888:
13861 break;
13862 case DRM_FORMAT_XRGB1555:
13863 if (INTEL_GEN(dev_priv) > 3) {
13864 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13865 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13866 goto err;
13867 }
13868 break;
13869 case DRM_FORMAT_ABGR8888:
13870 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13871 INTEL_GEN(dev_priv) < 9) {
13872 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13873 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13874 goto err;
13875 }
13876 break;
13877 case DRM_FORMAT_XBGR8888:
13878 case DRM_FORMAT_XRGB2101010:
13879 case DRM_FORMAT_XBGR2101010:
13880 if (INTEL_GEN(dev_priv) < 4) {
13881 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13882 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13883 goto err;
13884 }
13885 break;
13886 case DRM_FORMAT_ABGR2101010:
13887 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13888 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13889 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13890 goto err;
13891 }
13892 break;
13893 case DRM_FORMAT_YUYV:
13894 case DRM_FORMAT_UYVY:
13895 case DRM_FORMAT_YVYU:
13896 case DRM_FORMAT_VYUY:
13897 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13898 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13899 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13900 goto err;
13901 }
13902 break;
13903 default:
13904 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13905 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13906 goto err;
13907 }
13908
13909 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13910 if (mode_cmd->offsets[0] != 0)
13911 goto err;
13912
13913 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
13914 &intel_fb->base, mode_cmd);
13915
13916 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
13917 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13918 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
13919 mode_cmd->pitches[0], stride_alignment);
13920 goto err;
13921 }
13922
13923 intel_fb->obj = obj;
13924
13925 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
13926 if (ret)
13927 goto err;
13928
13929 ret = drm_framebuffer_init(obj->base.dev,
13930 &intel_fb->base,
13931 &intel_fb_funcs);
13932 if (ret) {
13933 DRM_ERROR("framebuffer init failed %d\n", ret);
13934 goto err;
13935 }
13936
13937 return 0;
13938
13939 err:
13940 i915_gem_object_lock(obj);
13941 obj->framebuffer_references--;
13942 i915_gem_object_unlock(obj);
13943 return ret;
13944 }
13945
13946 static struct drm_framebuffer *
13947 intel_user_framebuffer_create(struct drm_device *dev,
13948 struct drm_file *filp,
13949 const struct drm_mode_fb_cmd2 *user_mode_cmd)
13950 {
13951 struct drm_framebuffer *fb;
13952 struct drm_i915_gem_object *obj;
13953 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
13954
13955 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
13956 if (!obj)
13957 return ERR_PTR(-ENOENT);
13958
13959 fb = intel_framebuffer_create(obj, &mode_cmd);
13960 if (IS_ERR(fb))
13961 i915_gem_object_put(obj);
13962
13963 return fb;
13964 }
13965
13966 static void intel_atomic_state_free(struct drm_atomic_state *state)
13967 {
13968 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13969
13970 drm_atomic_state_default_release(state);
13971
13972 i915_sw_fence_fini(&intel_state->commit_ready);
13973
13974 kfree(state);
13975 }
13976
13977 static const struct drm_mode_config_funcs intel_mode_funcs = {
13978 .fb_create = intel_user_framebuffer_create,
13979 .output_poll_changed = intel_fbdev_output_poll_changed,
13980 .atomic_check = intel_atomic_check,
13981 .atomic_commit = intel_atomic_commit,
13982 .atomic_state_alloc = intel_atomic_state_alloc,
13983 .atomic_state_clear = intel_atomic_state_clear,
13984 .atomic_state_free = intel_atomic_state_free,
13985 };
13986
13987 /**
13988 * intel_init_display_hooks - initialize the display modesetting hooks
13989 * @dev_priv: device private
13990 */
13991 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
13992 {
13993 intel_init_cdclk_hooks(dev_priv);
13994
13995 if (INTEL_INFO(dev_priv)->gen >= 9) {
13996 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13997 dev_priv->display.get_initial_plane_config =
13998 skylake_get_initial_plane_config;
13999 dev_priv->display.crtc_compute_clock =
14000 haswell_crtc_compute_clock;
14001 dev_priv->display.crtc_enable = haswell_crtc_enable;
14002 dev_priv->display.crtc_disable = haswell_crtc_disable;
14003 } else if (HAS_DDI(dev_priv)) {
14004 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14005 dev_priv->display.get_initial_plane_config =
14006 ironlake_get_initial_plane_config;
14007 dev_priv->display.crtc_compute_clock =
14008 haswell_crtc_compute_clock;
14009 dev_priv->display.crtc_enable = haswell_crtc_enable;
14010 dev_priv->display.crtc_disable = haswell_crtc_disable;
14011 } else if (HAS_PCH_SPLIT(dev_priv)) {
14012 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14013 dev_priv->display.get_initial_plane_config =
14014 ironlake_get_initial_plane_config;
14015 dev_priv->display.crtc_compute_clock =
14016 ironlake_crtc_compute_clock;
14017 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14018 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14019 } else if (IS_CHERRYVIEW(dev_priv)) {
14020 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14021 dev_priv->display.get_initial_plane_config =
14022 i9xx_get_initial_plane_config;
14023 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14024 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14025 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14026 } else if (IS_VALLEYVIEW(dev_priv)) {
14027 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14028 dev_priv->display.get_initial_plane_config =
14029 i9xx_get_initial_plane_config;
14030 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14031 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14032 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14033 } else if (IS_G4X(dev_priv)) {
14034 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14035 dev_priv->display.get_initial_plane_config =
14036 i9xx_get_initial_plane_config;
14037 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14038 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14039 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14040 } else if (IS_PINEVIEW(dev_priv)) {
14041 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14042 dev_priv->display.get_initial_plane_config =
14043 i9xx_get_initial_plane_config;
14044 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14045 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14046 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14047 } else if (!IS_GEN2(dev_priv)) {
14048 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14049 dev_priv->display.get_initial_plane_config =
14050 i9xx_get_initial_plane_config;
14051 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14052 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14053 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14054 } else {
14055 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14056 dev_priv->display.get_initial_plane_config =
14057 i9xx_get_initial_plane_config;
14058 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14059 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14060 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14061 }
14062
14063 if (IS_GEN5(dev_priv)) {
14064 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14065 } else if (IS_GEN6(dev_priv)) {
14066 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14067 } else if (IS_IVYBRIDGE(dev_priv)) {
14068 /* FIXME: detect B0+ stepping and use auto training */
14069 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14070 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14071 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14072 }
14073
14074 if (dev_priv->info.gen >= 9)
14075 dev_priv->display.update_crtcs = skl_update_crtcs;
14076 else
14077 dev_priv->display.update_crtcs = intel_update_crtcs;
14078 }
14079
14080 /*
14081 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14082 */
14083 static void quirk_ssc_force_disable(struct drm_device *dev)
14084 {
14085 struct drm_i915_private *dev_priv = to_i915(dev);
14086 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14087 DRM_INFO("applying lvds SSC disable quirk\n");
14088 }
14089
14090 /*
14091 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14092 * brightness value
14093 */
14094 static void quirk_invert_brightness(struct drm_device *dev)
14095 {
14096 struct drm_i915_private *dev_priv = to_i915(dev);
14097 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14098 DRM_INFO("applying inverted panel brightness quirk\n");
14099 }
14100
14101 /* Some VBT's incorrectly indicate no backlight is present */
14102 static void quirk_backlight_present(struct drm_device *dev)
14103 {
14104 struct drm_i915_private *dev_priv = to_i915(dev);
14105 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14106 DRM_INFO("applying backlight present quirk\n");
14107 }
14108
14109 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14110 * which is 300 ms greater than eDP spec T12 min.
14111 */
14112 static void quirk_increase_t12_delay(struct drm_device *dev)
14113 {
14114 struct drm_i915_private *dev_priv = to_i915(dev);
14115
14116 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14117 DRM_INFO("Applying T12 delay quirk\n");
14118 }
14119
14120 struct intel_quirk {
14121 int device;
14122 int subsystem_vendor;
14123 int subsystem_device;
14124 void (*hook)(struct drm_device *dev);
14125 };
14126
14127 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14128 struct intel_dmi_quirk {
14129 void (*hook)(struct drm_device *dev);
14130 const struct dmi_system_id (*dmi_id_list)[];
14131 };
14132
14133 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14134 {
14135 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14136 return 1;
14137 }
14138
14139 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14140 {
14141 .dmi_id_list = &(const struct dmi_system_id[]) {
14142 {
14143 .callback = intel_dmi_reverse_brightness,
14144 .ident = "NCR Corporation",
14145 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14146 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14147 },
14148 },
14149 { } /* terminating entry */
14150 },
14151 .hook = quirk_invert_brightness,
14152 },
14153 };
14154
14155 static struct intel_quirk intel_quirks[] = {
14156 /* Lenovo U160 cannot use SSC on LVDS */
14157 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14158
14159 /* Sony Vaio Y cannot use SSC on LVDS */
14160 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14161
14162 /* Acer Aspire 5734Z must invert backlight brightness */
14163 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14164
14165 /* Acer/eMachines G725 */
14166 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14167
14168 /* Acer/eMachines e725 */
14169 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14170
14171 /* Acer/Packard Bell NCL20 */
14172 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14173
14174 /* Acer Aspire 4736Z */
14175 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14176
14177 /* Acer Aspire 5336 */
14178 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14179
14180 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14181 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14182
14183 /* Acer C720 Chromebook (Core i3 4005U) */
14184 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14185
14186 /* Apple Macbook 2,1 (Core 2 T7400) */
14187 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14188
14189 /* Apple Macbook 4,1 */
14190 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14191
14192 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14193 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14194
14195 /* HP Chromebook 14 (Celeron 2955U) */
14196 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14197
14198 /* Dell Chromebook 11 */
14199 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14200
14201 /* Dell Chromebook 11 (2015 version) */
14202 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14203
14204 /* Toshiba Satellite P50-C-18C */
14205 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14206 };
14207
14208 static void intel_init_quirks(struct drm_device *dev)
14209 {
14210 struct pci_dev *d = dev->pdev;
14211 int i;
14212
14213 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14214 struct intel_quirk *q = &intel_quirks[i];
14215
14216 if (d->device == q->device &&
14217 (d->subsystem_vendor == q->subsystem_vendor ||
14218 q->subsystem_vendor == PCI_ANY_ID) &&
14219 (d->subsystem_device == q->subsystem_device ||
14220 q->subsystem_device == PCI_ANY_ID))
14221 q->hook(dev);
14222 }
14223 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14224 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14225 intel_dmi_quirks[i].hook(dev);
14226 }
14227 }
14228
14229 /* Disable the VGA plane that we never use */
14230 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14231 {
14232 struct pci_dev *pdev = dev_priv->drm.pdev;
14233 u8 sr1;
14234 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14235
14236 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14237 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14238 outb(SR01, VGA_SR_INDEX);
14239 sr1 = inb(VGA_SR_DATA);
14240 outb(sr1 | 1<<5, VGA_SR_DATA);
14241 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14242 udelay(300);
14243
14244 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14245 POSTING_READ(vga_reg);
14246 }
14247
14248 void intel_modeset_init_hw(struct drm_device *dev)
14249 {
14250 struct drm_i915_private *dev_priv = to_i915(dev);
14251
14252 intel_update_cdclk(dev_priv);
14253 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14254
14255 intel_init_clock_gating(dev_priv);
14256 }
14257
14258 /*
14259 * Calculate what we think the watermarks should be for the state we've read
14260 * out of the hardware and then immediately program those watermarks so that
14261 * we ensure the hardware settings match our internal state.
14262 *
14263 * We can calculate what we think WM's should be by creating a duplicate of the
14264 * current state (which was constructed during hardware readout) and running it
14265 * through the atomic check code to calculate new watermark values in the
14266 * state object.
14267 */
14268 static void sanitize_watermarks(struct drm_device *dev)
14269 {
14270 struct drm_i915_private *dev_priv = to_i915(dev);
14271 struct drm_atomic_state *state;
14272 struct intel_atomic_state *intel_state;
14273 struct drm_crtc *crtc;
14274 struct drm_crtc_state *cstate;
14275 struct drm_modeset_acquire_ctx ctx;
14276 int ret;
14277 int i;
14278
14279 /* Only supported on platforms that use atomic watermark design */
14280 if (!dev_priv->display.optimize_watermarks)
14281 return;
14282
14283 /*
14284 * We need to hold connection_mutex before calling duplicate_state so
14285 * that the connector loop is protected.
14286 */
14287 drm_modeset_acquire_init(&ctx, 0);
14288 retry:
14289 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14290 if (ret == -EDEADLK) {
14291 drm_modeset_backoff(&ctx);
14292 goto retry;
14293 } else if (WARN_ON(ret)) {
14294 goto fail;
14295 }
14296
14297 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14298 if (WARN_ON(IS_ERR(state)))
14299 goto fail;
14300
14301 intel_state = to_intel_atomic_state(state);
14302
14303 /*
14304 * Hardware readout is the only time we don't want to calculate
14305 * intermediate watermarks (since we don't trust the current
14306 * watermarks).
14307 */
14308 if (!HAS_GMCH_DISPLAY(dev_priv))
14309 intel_state->skip_intermediate_wm = true;
14310
14311 ret = intel_atomic_check(dev, state);
14312 if (ret) {
14313 /*
14314 * If we fail here, it means that the hardware appears to be
14315 * programmed in a way that shouldn't be possible, given our
14316 * understanding of watermark requirements. This might mean a
14317 * mistake in the hardware readout code or a mistake in the
14318 * watermark calculations for a given platform. Raise a WARN
14319 * so that this is noticeable.
14320 *
14321 * If this actually happens, we'll have to just leave the
14322 * BIOS-programmed watermarks untouched and hope for the best.
14323 */
14324 WARN(true, "Could not determine valid watermarks for inherited state\n");
14325 goto put_state;
14326 }
14327
14328 /* Write calculated watermark values back */
14329 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14330 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14331
14332 cs->wm.need_postvbl_update = true;
14333 dev_priv->display.optimize_watermarks(intel_state, cs);
14334 }
14335
14336 put_state:
14337 drm_atomic_state_put(state);
14338 fail:
14339 drm_modeset_drop_locks(&ctx);
14340 drm_modeset_acquire_fini(&ctx);
14341 }
14342
14343 int intel_modeset_init(struct drm_device *dev)
14344 {
14345 struct drm_i915_private *dev_priv = to_i915(dev);
14346 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14347 enum pipe pipe;
14348 struct intel_crtc *crtc;
14349
14350 drm_mode_config_init(dev);
14351
14352 dev->mode_config.min_width = 0;
14353 dev->mode_config.min_height = 0;
14354
14355 dev->mode_config.preferred_depth = 24;
14356 dev->mode_config.prefer_shadow = 1;
14357
14358 dev->mode_config.allow_fb_modifiers = true;
14359
14360 dev->mode_config.funcs = &intel_mode_funcs;
14361
14362 init_llist_head(&dev_priv->atomic_helper.free_list);
14363 INIT_WORK(&dev_priv->atomic_helper.free_work,
14364 intel_atomic_helper_free_state_worker);
14365
14366 intel_init_quirks(dev);
14367
14368 intel_init_pm(dev_priv);
14369
14370 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14371 return 0;
14372
14373 /*
14374 * There may be no VBT; and if the BIOS enabled SSC we can
14375 * just keep using it to avoid unnecessary flicker. Whereas if the
14376 * BIOS isn't using it, don't assume it will work even if the VBT
14377 * indicates as much.
14378 */
14379 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14380 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14381 DREF_SSC1_ENABLE);
14382
14383 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14384 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14385 bios_lvds_use_ssc ? "en" : "dis",
14386 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14387 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14388 }
14389 }
14390
14391 if (IS_GEN2(dev_priv)) {
14392 dev->mode_config.max_width = 2048;
14393 dev->mode_config.max_height = 2048;
14394 } else if (IS_GEN3(dev_priv)) {
14395 dev->mode_config.max_width = 4096;
14396 dev->mode_config.max_height = 4096;
14397 } else {
14398 dev->mode_config.max_width = 8192;
14399 dev->mode_config.max_height = 8192;
14400 }
14401
14402 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14403 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14404 dev->mode_config.cursor_height = 1023;
14405 } else if (IS_GEN2(dev_priv)) {
14406 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14407 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14408 } else {
14409 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14410 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14411 }
14412
14413 dev->mode_config.fb_base = ggtt->mappable_base;
14414
14415 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14416 INTEL_INFO(dev_priv)->num_pipes,
14417 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14418
14419 for_each_pipe(dev_priv, pipe) {
14420 int ret;
14421
14422 ret = intel_crtc_init(dev_priv, pipe);
14423 if (ret) {
14424 drm_mode_config_cleanup(dev);
14425 return ret;
14426 }
14427 }
14428
14429 intel_shared_dpll_init(dev);
14430
14431 intel_update_czclk(dev_priv);
14432 intel_modeset_init_hw(dev);
14433
14434 if (dev_priv->max_cdclk_freq == 0)
14435 intel_update_max_cdclk(dev_priv);
14436
14437 /* Just disable it once at startup */
14438 i915_disable_vga(dev_priv);
14439 intel_setup_outputs(dev_priv);
14440
14441 drm_modeset_lock_all(dev);
14442 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14443 drm_modeset_unlock_all(dev);
14444
14445 for_each_intel_crtc(dev, crtc) {
14446 struct intel_initial_plane_config plane_config = {};
14447
14448 if (!crtc->active)
14449 continue;
14450
14451 /*
14452 * Note that reserving the BIOS fb up front prevents us
14453 * from stuffing other stolen allocations like the ring
14454 * on top. This prevents some ugliness at boot time, and
14455 * can even allow for smooth boot transitions if the BIOS
14456 * fb is large enough for the active pipe configuration.
14457 */
14458 dev_priv->display.get_initial_plane_config(crtc,
14459 &plane_config);
14460
14461 /*
14462 * If the fb is shared between multiple heads, we'll
14463 * just get the first one.
14464 */
14465 intel_find_initial_plane_obj(crtc, &plane_config);
14466 }
14467
14468 /*
14469 * Make sure hardware watermarks really match the state we read out.
14470 * Note that we need to do this after reconstructing the BIOS fb's
14471 * since the watermark calculation done here will use pstate->fb.
14472 */
14473 if (!HAS_GMCH_DISPLAY(dev_priv))
14474 sanitize_watermarks(dev);
14475
14476 return 0;
14477 }
14478
14479 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14480 {
14481 /* 640x480@60Hz, ~25175 kHz */
14482 struct dpll clock = {
14483 .m1 = 18,
14484 .m2 = 7,
14485 .p1 = 13,
14486 .p2 = 4,
14487 .n = 2,
14488 };
14489 u32 dpll, fp;
14490 int i;
14491
14492 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14493
14494 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14495 pipe_name(pipe), clock.vco, clock.dot);
14496
14497 fp = i9xx_dpll_compute_fp(&clock);
14498 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14499 DPLL_VGA_MODE_DIS |
14500 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14501 PLL_P2_DIVIDE_BY_4 |
14502 PLL_REF_INPUT_DREFCLK |
14503 DPLL_VCO_ENABLE;
14504
14505 I915_WRITE(FP0(pipe), fp);
14506 I915_WRITE(FP1(pipe), fp);
14507
14508 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14509 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14510 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14511 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14512 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14513 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14514 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14515
14516 /*
14517 * Apparently we need to have VGA mode enabled prior to changing
14518 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14519 * dividers, even though the register value does change.
14520 */
14521 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14522 I915_WRITE(DPLL(pipe), dpll);
14523
14524 /* Wait for the clocks to stabilize. */
14525 POSTING_READ(DPLL(pipe));
14526 udelay(150);
14527
14528 /* The pixel multiplier can only be updated once the
14529 * DPLL is enabled and the clocks are stable.
14530 *
14531 * So write it again.
14532 */
14533 I915_WRITE(DPLL(pipe), dpll);
14534
14535 /* We do this three times for luck */
14536 for (i = 0; i < 3 ; i++) {
14537 I915_WRITE(DPLL(pipe), dpll);
14538 POSTING_READ(DPLL(pipe));
14539 udelay(150); /* wait for warmup */
14540 }
14541
14542 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14543 POSTING_READ(PIPECONF(pipe));
14544 }
14545
14546 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14547 {
14548 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14549 pipe_name(pipe));
14550
14551 assert_plane_disabled(dev_priv, PLANE_A);
14552 assert_plane_disabled(dev_priv, PLANE_B);
14553
14554 I915_WRITE(PIPECONF(pipe), 0);
14555 POSTING_READ(PIPECONF(pipe));
14556
14557 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14558 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14559
14560 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14561 POSTING_READ(DPLL(pipe));
14562 }
14563
14564 static bool
14565 intel_check_plane_mapping(struct intel_crtc *crtc)
14566 {
14567 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14568 u32 val;
14569
14570 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14571 return true;
14572
14573 val = I915_READ(DSPCNTR(!crtc->plane));
14574
14575 if ((val & DISPLAY_PLANE_ENABLE) &&
14576 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14577 return false;
14578
14579 return true;
14580 }
14581
14582 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14583 {
14584 struct drm_device *dev = crtc->base.dev;
14585 struct intel_encoder *encoder;
14586
14587 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14588 return true;
14589
14590 return false;
14591 }
14592
14593 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14594 {
14595 struct drm_device *dev = encoder->base.dev;
14596 struct intel_connector *connector;
14597
14598 for_each_connector_on_encoder(dev, &encoder->base, connector)
14599 return connector;
14600
14601 return NULL;
14602 }
14603
14604 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14605 enum transcoder pch_transcoder)
14606 {
14607 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14608 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14609 }
14610
14611 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14612 struct drm_modeset_acquire_ctx *ctx)
14613 {
14614 struct drm_device *dev = crtc->base.dev;
14615 struct drm_i915_private *dev_priv = to_i915(dev);
14616 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14617
14618 /* Clear any frame start delays used for debugging left by the BIOS */
14619 if (!transcoder_is_dsi(cpu_transcoder)) {
14620 i915_reg_t reg = PIPECONF(cpu_transcoder);
14621
14622 I915_WRITE(reg,
14623 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14624 }
14625
14626 /* restore vblank interrupts to correct state */
14627 drm_crtc_vblank_reset(&crtc->base);
14628 if (crtc->active) {
14629 struct intel_plane *plane;
14630
14631 drm_crtc_vblank_on(&crtc->base);
14632
14633 /* Disable everything but the primary plane */
14634 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14635 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14636 continue;
14637
14638 trace_intel_disable_plane(&plane->base, crtc);
14639 plane->disable_plane(plane, crtc);
14640 }
14641 }
14642
14643 /* We need to sanitize the plane -> pipe mapping first because this will
14644 * disable the crtc (and hence change the state) if it is wrong. Note
14645 * that gen4+ has a fixed plane -> pipe mapping. */
14646 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14647 bool plane;
14648
14649 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14650 crtc->base.base.id, crtc->base.name);
14651
14652 /* Pipe has the wrong plane attached and the plane is active.
14653 * Temporarily change the plane mapping and disable everything
14654 * ... */
14655 plane = crtc->plane;
14656 crtc->base.primary->state->visible = true;
14657 crtc->plane = !plane;
14658 intel_crtc_disable_noatomic(&crtc->base, ctx);
14659 crtc->plane = plane;
14660 }
14661
14662 /* Adjust the state of the output pipe according to whether we
14663 * have active connectors/encoders. */
14664 if (crtc->active && !intel_crtc_has_encoders(crtc))
14665 intel_crtc_disable_noatomic(&crtc->base, ctx);
14666
14667 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14668 /*
14669 * We start out with underrun reporting disabled to avoid races.
14670 * For correct bookkeeping mark this on active crtcs.
14671 *
14672 * Also on gmch platforms we dont have any hardware bits to
14673 * disable the underrun reporting. Which means we need to start
14674 * out with underrun reporting disabled also on inactive pipes,
14675 * since otherwise we'll complain about the garbage we read when
14676 * e.g. coming up after runtime pm.
14677 *
14678 * No protection against concurrent access is required - at
14679 * worst a fifo underrun happens which also sets this to false.
14680 */
14681 crtc->cpu_fifo_underrun_disabled = true;
14682 /*
14683 * We track the PCH trancoder underrun reporting state
14684 * within the crtc. With crtc for pipe A housing the underrun
14685 * reporting state for PCH transcoder A, crtc for pipe B housing
14686 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14687 * and marking underrun reporting as disabled for the non-existing
14688 * PCH transcoders B and C would prevent enabling the south
14689 * error interrupt (see cpt_can_enable_serr_int()).
14690 */
14691 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14692 crtc->pch_fifo_underrun_disabled = true;
14693 }
14694 }
14695
14696 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14697 {
14698 struct intel_connector *connector;
14699
14700 /* We need to check both for a crtc link (meaning that the
14701 * encoder is active and trying to read from a pipe) and the
14702 * pipe itself being active. */
14703 bool has_active_crtc = encoder->base.crtc &&
14704 to_intel_crtc(encoder->base.crtc)->active;
14705
14706 connector = intel_encoder_find_connector(encoder);
14707 if (connector && !has_active_crtc) {
14708 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14709 encoder->base.base.id,
14710 encoder->base.name);
14711
14712 /* Connector is active, but has no active pipe. This is
14713 * fallout from our resume register restoring. Disable
14714 * the encoder manually again. */
14715 if (encoder->base.crtc) {
14716 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14717
14718 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14719 encoder->base.base.id,
14720 encoder->base.name);
14721 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14722 if (encoder->post_disable)
14723 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14724 }
14725 encoder->base.crtc = NULL;
14726
14727 /* Inconsistent output/port/pipe state happens presumably due to
14728 * a bug in one of the get_hw_state functions. Or someplace else
14729 * in our code, like the register restore mess on resume. Clamp
14730 * things to off as a safer default. */
14731
14732 connector->base.dpms = DRM_MODE_DPMS_OFF;
14733 connector->base.encoder = NULL;
14734 }
14735 /* Enabled encoders without active connectors will be fixed in
14736 * the crtc fixup. */
14737 }
14738
14739 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14740 {
14741 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14742
14743 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14744 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14745 i915_disable_vga(dev_priv);
14746 }
14747 }
14748
14749 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14750 {
14751 /* This function can be called both from intel_modeset_setup_hw_state or
14752 * at a very early point in our resume sequence, where the power well
14753 * structures are not yet restored. Since this function is at a very
14754 * paranoid "someone might have enabled VGA while we were not looking"
14755 * level, just check if the power well is enabled instead of trying to
14756 * follow the "don't touch the power well if we don't need it" policy
14757 * the rest of the driver uses. */
14758 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14759 return;
14760
14761 i915_redisable_vga_power_on(dev_priv);
14762
14763 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14764 }
14765
14766 static bool primary_get_hw_state(struct intel_plane *plane)
14767 {
14768 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14769
14770 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14771 }
14772
14773 /* FIXME read out full plane state for all planes */
14774 static void readout_plane_state(struct intel_crtc *crtc)
14775 {
14776 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14777 bool visible;
14778
14779 visible = crtc->active && primary_get_hw_state(primary);
14780
14781 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14782 to_intel_plane_state(primary->base.state),
14783 visible);
14784 }
14785
14786 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14787 {
14788 struct drm_i915_private *dev_priv = to_i915(dev);
14789 enum pipe pipe;
14790 struct intel_crtc *crtc;
14791 struct intel_encoder *encoder;
14792 struct intel_connector *connector;
14793 struct drm_connector_list_iter conn_iter;
14794 int i;
14795
14796 dev_priv->active_crtcs = 0;
14797
14798 for_each_intel_crtc(dev, crtc) {
14799 struct intel_crtc_state *crtc_state =
14800 to_intel_crtc_state(crtc->base.state);
14801
14802 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14803 memset(crtc_state, 0, sizeof(*crtc_state));
14804 crtc_state->base.crtc = &crtc->base;
14805
14806 crtc_state->base.active = crtc_state->base.enable =
14807 dev_priv->display.get_pipe_config(crtc, crtc_state);
14808
14809 crtc->base.enabled = crtc_state->base.enable;
14810 crtc->active = crtc_state->base.active;
14811
14812 if (crtc_state->base.active)
14813 dev_priv->active_crtcs |= 1 << crtc->pipe;
14814
14815 readout_plane_state(crtc);
14816
14817 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14818 crtc->base.base.id, crtc->base.name,
14819 enableddisabled(crtc_state->base.active));
14820 }
14821
14822 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14823 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14824
14825 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14826 &pll->state.hw_state);
14827 pll->state.crtc_mask = 0;
14828 for_each_intel_crtc(dev, crtc) {
14829 struct intel_crtc_state *crtc_state =
14830 to_intel_crtc_state(crtc->base.state);
14831
14832 if (crtc_state->base.active &&
14833 crtc_state->shared_dpll == pll)
14834 pll->state.crtc_mask |= 1 << crtc->pipe;
14835 }
14836 pll->active_mask = pll->state.crtc_mask;
14837
14838 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14839 pll->name, pll->state.crtc_mask, pll->on);
14840 }
14841
14842 for_each_intel_encoder(dev, encoder) {
14843 pipe = 0;
14844
14845 if (encoder->get_hw_state(encoder, &pipe)) {
14846 struct intel_crtc_state *crtc_state;
14847
14848 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14849 crtc_state = to_intel_crtc_state(crtc->base.state);
14850
14851 encoder->base.crtc = &crtc->base;
14852 crtc_state->output_types |= 1 << encoder->type;
14853 encoder->get_config(encoder, crtc_state);
14854 } else {
14855 encoder->base.crtc = NULL;
14856 }
14857
14858 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14859 encoder->base.base.id, encoder->base.name,
14860 enableddisabled(encoder->base.crtc),
14861 pipe_name(pipe));
14862 }
14863
14864 drm_connector_list_iter_begin(dev, &conn_iter);
14865 for_each_intel_connector_iter(connector, &conn_iter) {
14866 if (connector->get_hw_state(connector)) {
14867 connector->base.dpms = DRM_MODE_DPMS_ON;
14868
14869 encoder = connector->encoder;
14870 connector->base.encoder = &encoder->base;
14871
14872 if (encoder->base.crtc &&
14873 encoder->base.crtc->state->active) {
14874 /*
14875 * This has to be done during hardware readout
14876 * because anything calling .crtc_disable may
14877 * rely on the connector_mask being accurate.
14878 */
14879 encoder->base.crtc->state->connector_mask |=
14880 1 << drm_connector_index(&connector->base);
14881 encoder->base.crtc->state->encoder_mask |=
14882 1 << drm_encoder_index(&encoder->base);
14883 }
14884
14885 } else {
14886 connector->base.dpms = DRM_MODE_DPMS_OFF;
14887 connector->base.encoder = NULL;
14888 }
14889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14890 connector->base.base.id, connector->base.name,
14891 enableddisabled(connector->base.encoder));
14892 }
14893 drm_connector_list_iter_end(&conn_iter);
14894
14895 for_each_intel_crtc(dev, crtc) {
14896 struct intel_crtc_state *crtc_state =
14897 to_intel_crtc_state(crtc->base.state);
14898 int pixclk = 0;
14899
14900 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
14901 if (crtc_state->base.active) {
14902 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
14903 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
14904 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
14905
14906 /*
14907 * The initial mode needs to be set in order to keep
14908 * the atomic core happy. It wants a valid mode if the
14909 * crtc's enabled, so we do the above call.
14910 *
14911 * But we don't set all the derived state fully, hence
14912 * set a flag to indicate that a full recalculation is
14913 * needed on the next commit.
14914 */
14915 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
14916
14917 intel_crtc_compute_pixel_rate(crtc_state);
14918
14919 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
14920 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14921 pixclk = crtc_state->pixel_rate;
14922 else
14923 WARN_ON(dev_priv->display.modeset_calc_cdclk);
14924
14925 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
14926 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
14927 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
14928
14929 drm_calc_timestamping_constants(&crtc->base,
14930 &crtc_state->base.adjusted_mode);
14931 update_scanline_offset(crtc);
14932 }
14933
14934 dev_priv->min_pixclk[crtc->pipe] = pixclk;
14935
14936 intel_pipe_config_sanity_check(dev_priv, crtc_state);
14937 }
14938 }
14939
14940 static void
14941 get_encoder_power_domains(struct drm_i915_private *dev_priv)
14942 {
14943 struct intel_encoder *encoder;
14944
14945 for_each_intel_encoder(&dev_priv->drm, encoder) {
14946 u64 get_domains;
14947 enum intel_display_power_domain domain;
14948
14949 if (!encoder->get_power_domains)
14950 continue;
14951
14952 get_domains = encoder->get_power_domains(encoder);
14953 for_each_power_domain(domain, get_domains)
14954 intel_display_power_get(dev_priv, domain);
14955 }
14956 }
14957
14958 /* Scan out the current hw modeset state,
14959 * and sanitizes it to the current state
14960 */
14961 static void
14962 intel_modeset_setup_hw_state(struct drm_device *dev,
14963 struct drm_modeset_acquire_ctx *ctx)
14964 {
14965 struct drm_i915_private *dev_priv = to_i915(dev);
14966 enum pipe pipe;
14967 struct intel_crtc *crtc;
14968 struct intel_encoder *encoder;
14969 int i;
14970
14971 intel_modeset_readout_hw_state(dev);
14972
14973 /* HW state is read out, now we need to sanitize this mess. */
14974 get_encoder_power_domains(dev_priv);
14975
14976 for_each_intel_encoder(dev, encoder) {
14977 intel_sanitize_encoder(encoder);
14978 }
14979
14980 for_each_pipe(dev_priv, pipe) {
14981 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14982
14983 intel_sanitize_crtc(crtc, ctx);
14984 intel_dump_pipe_config(crtc, crtc->config,
14985 "[setup_hw_state]");
14986 }
14987
14988 intel_modeset_update_connector_atomic_state(dev);
14989
14990 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14991 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14992
14993 if (!pll->on || pll->active_mask)
14994 continue;
14995
14996 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14997
14998 pll->funcs.disable(dev_priv, pll);
14999 pll->on = false;
15000 }
15001
15002 if (IS_G4X(dev_priv)) {
15003 g4x_wm_get_hw_state(dev);
15004 g4x_wm_sanitize(dev_priv);
15005 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15006 vlv_wm_get_hw_state(dev);
15007 vlv_wm_sanitize(dev_priv);
15008 } else if (IS_GEN9(dev_priv)) {
15009 skl_wm_get_hw_state(dev);
15010 } else if (HAS_PCH_SPLIT(dev_priv)) {
15011 ilk_wm_get_hw_state(dev);
15012 }
15013
15014 for_each_intel_crtc(dev, crtc) {
15015 u64 put_domains;
15016
15017 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15018 if (WARN_ON(put_domains))
15019 modeset_put_power_domains(dev_priv, put_domains);
15020 }
15021 intel_display_set_init_power(dev_priv, false);
15022
15023 intel_power_domains_verify_state(dev_priv);
15024
15025 intel_fbc_init_pipe_state(dev_priv);
15026 }
15027
15028 void intel_display_resume(struct drm_device *dev)
15029 {
15030 struct drm_i915_private *dev_priv = to_i915(dev);
15031 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15032 struct drm_modeset_acquire_ctx ctx;
15033 int ret;
15034
15035 dev_priv->modeset_restore_state = NULL;
15036 if (state)
15037 state->acquire_ctx = &ctx;
15038
15039 drm_modeset_acquire_init(&ctx, 0);
15040
15041 while (1) {
15042 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15043 if (ret != -EDEADLK)
15044 break;
15045
15046 drm_modeset_backoff(&ctx);
15047 }
15048
15049 if (!ret)
15050 ret = __intel_display_resume(dev, state, &ctx);
15051
15052 drm_modeset_drop_locks(&ctx);
15053 drm_modeset_acquire_fini(&ctx);
15054
15055 if (ret)
15056 DRM_ERROR("Restoring old state failed with %i\n", ret);
15057 if (state)
15058 drm_atomic_state_put(state);
15059 }
15060
15061 void intel_modeset_gem_init(struct drm_device *dev)
15062 {
15063 struct drm_i915_private *dev_priv = to_i915(dev);
15064
15065 intel_init_gt_powersave(dev_priv);
15066
15067 intel_setup_overlay(dev_priv);
15068 }
15069
15070 int intel_connector_register(struct drm_connector *connector)
15071 {
15072 struct intel_connector *intel_connector = to_intel_connector(connector);
15073 int ret;
15074
15075 ret = intel_backlight_device_register(intel_connector);
15076 if (ret)
15077 goto err;
15078
15079 return 0;
15080
15081 err:
15082 return ret;
15083 }
15084
15085 void intel_connector_unregister(struct drm_connector *connector)
15086 {
15087 struct intel_connector *intel_connector = to_intel_connector(connector);
15088
15089 intel_backlight_device_unregister(intel_connector);
15090 intel_panel_destroy_backlight(connector);
15091 }
15092
15093 void intel_modeset_cleanup(struct drm_device *dev)
15094 {
15095 struct drm_i915_private *dev_priv = to_i915(dev);
15096
15097 flush_work(&dev_priv->atomic_helper.free_work);
15098 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15099
15100 intel_disable_gt_powersave(dev_priv);
15101
15102 /*
15103 * Interrupts and polling as the first thing to avoid creating havoc.
15104 * Too much stuff here (turning of connectors, ...) would
15105 * experience fancy races otherwise.
15106 */
15107 intel_irq_uninstall(dev_priv);
15108
15109 /*
15110 * Due to the hpd irq storm handling the hotplug work can re-arm the
15111 * poll handlers. Hence disable polling after hpd handling is shut down.
15112 */
15113 drm_kms_helper_poll_fini(dev);
15114
15115 /* poll work can call into fbdev, hence clean that up afterwards */
15116 intel_fbdev_fini(dev_priv);
15117
15118 intel_unregister_dsm_handler();
15119
15120 intel_fbc_global_disable(dev_priv);
15121
15122 /* flush any delayed tasks or pending work */
15123 flush_scheduled_work();
15124
15125 drm_mode_config_cleanup(dev);
15126
15127 intel_cleanup_overlay(dev_priv);
15128
15129 intel_cleanup_gt_powersave(dev_priv);
15130
15131 intel_teardown_gmbus(dev_priv);
15132 }
15133
15134 void intel_connector_attach_encoder(struct intel_connector *connector,
15135 struct intel_encoder *encoder)
15136 {
15137 connector->encoder = encoder;
15138 drm_mode_connector_attach_encoder(&connector->base,
15139 &encoder->base);
15140 }
15141
15142 /*
15143 * set vga decode state - true == enable VGA decode
15144 */
15145 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15146 {
15147 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15148 u16 gmch_ctrl;
15149
15150 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15151 DRM_ERROR("failed to read control word\n");
15152 return -EIO;
15153 }
15154
15155 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15156 return 0;
15157
15158 if (state)
15159 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15160 else
15161 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15162
15163 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15164 DRM_ERROR("failed to write control word\n");
15165 return -EIO;
15166 }
15167
15168 return 0;
15169 }
15170
15171 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15172
15173 struct intel_display_error_state {
15174
15175 u32 power_well_driver;
15176
15177 int num_transcoders;
15178
15179 struct intel_cursor_error_state {
15180 u32 control;
15181 u32 position;
15182 u32 base;
15183 u32 size;
15184 } cursor[I915_MAX_PIPES];
15185
15186 struct intel_pipe_error_state {
15187 bool power_domain_on;
15188 u32 source;
15189 u32 stat;
15190 } pipe[I915_MAX_PIPES];
15191
15192 struct intel_plane_error_state {
15193 u32 control;
15194 u32 stride;
15195 u32 size;
15196 u32 pos;
15197 u32 addr;
15198 u32 surface;
15199 u32 tile_offset;
15200 } plane[I915_MAX_PIPES];
15201
15202 struct intel_transcoder_error_state {
15203 bool power_domain_on;
15204 enum transcoder cpu_transcoder;
15205
15206 u32 conf;
15207
15208 u32 htotal;
15209 u32 hblank;
15210 u32 hsync;
15211 u32 vtotal;
15212 u32 vblank;
15213 u32 vsync;
15214 } transcoder[4];
15215 };
15216
15217 struct intel_display_error_state *
15218 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15219 {
15220 struct intel_display_error_state *error;
15221 int transcoders[] = {
15222 TRANSCODER_A,
15223 TRANSCODER_B,
15224 TRANSCODER_C,
15225 TRANSCODER_EDP,
15226 };
15227 int i;
15228
15229 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15230 return NULL;
15231
15232 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15233 if (error == NULL)
15234 return NULL;
15235
15236 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15237 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15238
15239 for_each_pipe(dev_priv, i) {
15240 error->pipe[i].power_domain_on =
15241 __intel_display_power_is_enabled(dev_priv,
15242 POWER_DOMAIN_PIPE(i));
15243 if (!error->pipe[i].power_domain_on)
15244 continue;
15245
15246 error->cursor[i].control = I915_READ(CURCNTR(i));
15247 error->cursor[i].position = I915_READ(CURPOS(i));
15248 error->cursor[i].base = I915_READ(CURBASE(i));
15249
15250 error->plane[i].control = I915_READ(DSPCNTR(i));
15251 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15252 if (INTEL_GEN(dev_priv) <= 3) {
15253 error->plane[i].size = I915_READ(DSPSIZE(i));
15254 error->plane[i].pos = I915_READ(DSPPOS(i));
15255 }
15256 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15257 error->plane[i].addr = I915_READ(DSPADDR(i));
15258 if (INTEL_GEN(dev_priv) >= 4) {
15259 error->plane[i].surface = I915_READ(DSPSURF(i));
15260 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15261 }
15262
15263 error->pipe[i].source = I915_READ(PIPESRC(i));
15264
15265 if (HAS_GMCH_DISPLAY(dev_priv))
15266 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15267 }
15268
15269 /* Note: this does not include DSI transcoders. */
15270 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15271 if (HAS_DDI(dev_priv))
15272 error->num_transcoders++; /* Account for eDP. */
15273
15274 for (i = 0; i < error->num_transcoders; i++) {
15275 enum transcoder cpu_transcoder = transcoders[i];
15276
15277 error->transcoder[i].power_domain_on =
15278 __intel_display_power_is_enabled(dev_priv,
15279 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15280 if (!error->transcoder[i].power_domain_on)
15281 continue;
15282
15283 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15284
15285 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15286 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15287 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15288 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15289 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15290 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15291 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15292 }
15293
15294 return error;
15295 }
15296
15297 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15298
15299 void
15300 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15301 struct intel_display_error_state *error)
15302 {
15303 struct drm_i915_private *dev_priv = m->i915;
15304 int i;
15305
15306 if (!error)
15307 return;
15308
15309 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15310 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15311 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15312 error->power_well_driver);
15313 for_each_pipe(dev_priv, i) {
15314 err_printf(m, "Pipe [%d]:\n", i);
15315 err_printf(m, " Power: %s\n",
15316 onoff(error->pipe[i].power_domain_on));
15317 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15318 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15319
15320 err_printf(m, "Plane [%d]:\n", i);
15321 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15322 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15323 if (INTEL_GEN(dev_priv) <= 3) {
15324 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15325 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15326 }
15327 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15328 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15329 if (INTEL_GEN(dev_priv) >= 4) {
15330 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15331 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15332 }
15333
15334 err_printf(m, "Cursor [%d]:\n", i);
15335 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15336 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15337 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15338 }
15339
15340 for (i = 0; i < error->num_transcoders; i++) {
15341 err_printf(m, "CPU transcoder: %s\n",
15342 transcoder_name(error->transcoder[i].cpu_transcoder));
15343 err_printf(m, " Power: %s\n",
15344 onoff(error->transcoder[i].power_domain_on));
15345 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15346 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15347 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15348 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15349 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15350 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15351 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15352 }
15353 }
15354
15355 #endif
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