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Merge tag 'drm-intel-next-2013-06-18' of git://people.freedesktop.org/~danvet/drm...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 };
63
64 /* FDI */
65 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
67 int
68 intel_pch_rawclk(struct drm_device *dev)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75 }
76
77 static inline u32 /* units of 100MHz */
78 intel_fdi_link_freq(struct drm_device *dev)
79 {
80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
85 }
86
87 static const intel_limit_t intel_limits_i8xx_dvo = {
88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
98 };
99
100 static const intel_limit_t intel_limits_i8xx_lvds = {
101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
111 };
112
113 static const intel_limit_t intel_limits_i9xx_sdvo = {
114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
124 };
125
126 static const intel_limit_t intel_limits_i9xx_lvds = {
127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
137 };
138
139
140 static const intel_limit_t intel_limits_g4x_sdvo = {
141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
152 },
153 };
154
155 static const intel_limit_t intel_limits_g4x_hdmi = {
156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
166 };
167
168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
179 },
180 };
181
182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
193 },
194 };
195
196 static const intel_limit_t intel_limits_pineview_sdvo = {
197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
199 /* Pineview's Ncounter is a ring counter */
200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
202 /* Pineview only has one combined m divider, which we treat as m2. */
203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_pineview_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
222 };
223
224 /* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
229 static const intel_limit_t intel_limits_ironlake_dac = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
253 };
254
255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
266 };
267
268 /* LVDS 100mhz refclk limits. */
269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
277 .p1 = { .min = 2, .max = 8 },
278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
280 };
281
282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
290 .p1 = { .min = 2, .max = 6 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
293 };
294
295 static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
303 .p1 = { .min = 1, .max = 3 },
304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
306 };
307
308 static const intel_limit_t intel_limits_vlv_hdmi = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
319 };
320
321 static const intel_limit_t intel_limits_vlv_dp = {
322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m = { .min = 22, .max = 450 },
326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
329 .p1 = { .min = 1, .max = 3 },
330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
332 };
333
334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
336 {
337 struct drm_device *dev = crtc->dev;
338 const intel_limit_t *limit;
339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
341 if (intel_is_dual_link_lvds(dev)) {
342 if (refclk == 100000)
343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
352 } else
353 limit = &intel_limits_ironlake_dac;
354
355 return limit;
356 }
357
358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359 {
360 struct drm_device *dev = crtc->dev;
361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
364 if (intel_is_dual_link_lvds(dev))
365 limit = &intel_limits_g4x_dual_channel_lvds;
366 else
367 limit = &intel_limits_g4x_single_channel_lvds;
368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
370 limit = &intel_limits_g4x_hdmi;
371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
372 limit = &intel_limits_g4x_sdvo;
373 } else /* The option is for other outputs */
374 limit = &intel_limits_i9xx_sdvo;
375
376 return limit;
377 }
378
379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
380 {
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
384 if (HAS_PCH_SPLIT(dev))
385 limit = intel_ironlake_limit(crtc, refclk);
386 else if (IS_G4X(dev)) {
387 limit = intel_g4x_limit(crtc);
388 } else if (IS_PINEVIEW(dev)) {
389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
390 limit = &intel_limits_pineview_lvds;
391 else
392 limit = &intel_limits_pineview_sdvo;
393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i8xx_lvds;
408 else
409 limit = &intel_limits_i8xx_dvo;
410 }
411 return limit;
412 }
413
414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
415 static void pineview_clock(int refclk, intel_clock_t *clock)
416 {
417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421 }
422
423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424 {
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426 }
427
428 static void i9xx_clock(int refclk, intel_clock_t *clock)
429 {
430 clock->m = i9xx_dpll_compute_m(clock);
431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434 }
435
436 /**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
440 {
441 struct drm_device *dev = crtc->dev;
442 struct intel_encoder *encoder;
443
444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
446 return true;
447
448 return false;
449 }
450
451 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 /**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
457 static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
460 {
461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
462 INTELPllInvalid("p1 out of range\n");
463 if (clock->p < limit->p.min || limit->p.max < clock->p)
464 INTELPllInvalid("p out of range\n");
465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
466 INTELPllInvalid("m2 out of range\n");
467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
468 INTELPllInvalid("m1 out of range\n");
469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
470 INTELPllInvalid("m1 <= m2\n");
471 if (clock->m < limit->m.min || limit->m.max < clock->m)
472 INTELPllInvalid("m out of range\n");
473 if (clock->n < limit->n.min || limit->n.max < clock->n)
474 INTELPllInvalid("n out of range\n");
475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
476 INTELPllInvalid("vco out of range\n");
477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
481 INTELPllInvalid("dot out of range\n");
482
483 return true;
484 }
485
486 static bool
487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
490 {
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
518 if (clock.m2 >= clock.m1)
519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
525
526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545 }
546
547 static bool
548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
551 {
552 struct drm_device *dev = crtc->dev;
553 intel_clock_t clock;
554 int err = target;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 /*
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
561 */
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
573 memset(best_clock, 0, sizeof(*best_clock));
574
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
583 int this_err;
584
585 pineview_clock(refclk, &clock);
586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
588 continue;
589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604 }
605
606 static bool
607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
610 {
611 struct drm_device *dev = crtc->dev;
612 intel_clock_t clock;
613 int max_n;
614 bool found;
615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
620 if (intel_is_dual_link_lvds(dev))
621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
633 /* based on hardware requirement, prefer smaller n to precision */
634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
635 /* based on hardware requirement, prefere larger m1,m2 */
636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
644 i9xx_clock(refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
660 return found;
661 }
662
663 static bool
664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
674 flag = 0;
675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730 }
731
732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734 {
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
738 return intel_crtc->config.cpu_transcoder;
739 }
740
741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742 {
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750 }
751
752 /**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 int pipestat_reg = PIPESTAT(pipe);
764
765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
786 /* Wait for vblank interrupt bit to set */
787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
790 DRM_DEBUG_KMS("vblank wait timed out\n");
791 }
792
793 /*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
808 *
809 */
810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
811 {
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
815
816 if (INTEL_INFO(dev)->gen >= 4) {
817 int reg = PIPECONF(cpu_transcoder);
818
819 /* Wait for the Pipe State to go off */
820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
822 WARN(1, "pipe_off wait timed out\n");
823 } else {
824 u32 last_line, line_mask;
825 int reg = PIPEDSL(pipe);
826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
833 /* Wait for the display line to settle */
834 do {
835 last_line = I915_READ(reg) & line_mask;
836 mdelay(5);
837 } while (((I915_READ(reg) & line_mask) != last_line) &&
838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
840 WARN(1, "pipe_off wait timed out\n");
841 }
842 }
843
844 /*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853 {
854 u32 bit;
855
856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
884 }
885
886 return I915_READ(SDEISR) & bit;
887 }
888
889 static const char *state_string(bool enabled)
890 {
891 return enabled ? "on" : "off";
892 }
893
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897 {
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908 }
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
912 static struct intel_shared_dpll *
913 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914 {
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
917 if (crtc->config.shared_dpll < 0)
918 return NULL;
919
920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
921 }
922
923 /* For ILK+ */
924 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
926 bool state)
927 {
928 bool cur_state;
929 struct intel_dpll_hw_state hw_state;
930
931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
936 if (WARN (!pll,
937 "asserting DPLL %s with no DPLL\n", state_string(state)))
938 return;
939
940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
941 WARN(cur_state != state,
942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
944 }
945 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
947
948 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
950 {
951 int reg;
952 u32 val;
953 bool cur_state;
954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
955 pipe);
956
957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
960 val = I915_READ(reg);
961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
962 } else {
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
966 }
967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
970 }
971 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
973
974 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976 {
977 int reg;
978 u32 val;
979 bool cur_state;
980
981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
987 }
988 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
990
991 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993 {
994 int reg;
995 u32 val;
996
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
999 return;
1000
1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1002 if (HAS_DDI(dev_priv->dev))
1003 return;
1004
1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008 }
1009
1010 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012 {
1013 int reg;
1014 u32 val;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023 {
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
1027 bool locked = true;
1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
1047 pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
1052 {
1053 int reg;
1054 u32 val;
1055 bool cur_state;
1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
1058
1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
1074 pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
1079 {
1080 int reg;
1081 u32 val;
1082 bool cur_state;
1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097 {
1098 struct drm_device *dev = dev_priv->dev;
1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
1110 return;
1111 }
1112
1113 /* Need to check both planes against the pipe */
1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
1122 }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 struct drm_device *dev = dev_priv->dev;
1129 int reg, i;
1130 u32 val;
1131
1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
1142 val = I915_READ(reg);
1143 WARN((val & SPRITE_ENABLE),
1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DVS_ENABLE),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe), pipe_name(pipe));
1152 }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157 u32 val;
1158 bool enabled;
1159
1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173 {
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
1178 reg = PCH_TRANSCONF(pipe);
1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206 {
1207 if ((val & SDVO_ENABLE) == 0)
1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212 return false;
1213 } else {
1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215 return false;
1216 }
1217 return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222 {
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238 {
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, int reg, u32 port_sel)
1253 {
1254 u32 val = I915_READ(reg);
1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257 reg, pipe_name(pipe));
1258
1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
1261 "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266 {
1267 u32 val = I915_READ(reg);
1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270 reg, pipe_name(pipe));
1271
1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273 && (val & SDVO_PIPE_B_SELECT),
1274 "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279 {
1280 int reg;
1281 u32 val;
1282
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
1291 pipe_name(pipe));
1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297 pipe_name(pipe));
1298
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 /**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1316 */
1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318 {
1319 int reg;
1320 u32 val;
1321
1322 assert_pipe_disabled(dev_priv, pipe);
1323
1324 /* No really, not for ILK+ */
1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345 }
1346
1347 /**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 }
1374
1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376 {
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387 }
1388
1389 /**
1390 * ironlake_enable_shared_dpll - enable PCH PLL
1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1398 {
1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1401
1402 /* PCH PLLs only available on ILK, SNB and IVB */
1403 BUG_ON(dev_priv->info->gen < 5);
1404 if (WARN_ON(pll == NULL))
1405 return;
1406
1407 if (WARN_ON(pll->refcount == 0))
1408 return;
1409
1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
1412 crtc->base.base.id);
1413
1414 if (pll->active++) {
1415 WARN_ON(!pll->on);
1416 assert_shared_dpll_enabled(dev_priv, pll);
1417 return;
1418 }
1419 WARN_ON(pll->on);
1420
1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1422 pll->enable(dev_priv, pll);
1423 pll->on = true;
1424 }
1425
1426 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1427 {
1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1430
1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
1433 if (WARN_ON(pll == NULL))
1434 return;
1435
1436 if (WARN_ON(pll->refcount == 0))
1437 return;
1438
1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
1441 crtc->base.base.id);
1442
1443 if (WARN_ON(pll->active == 0)) {
1444 assert_shared_dpll_disabled(dev_priv, pll);
1445 return;
1446 }
1447
1448 assert_shared_dpll_enabled(dev_priv, pll);
1449 WARN_ON(!pll->on);
1450 if (--pll->active)
1451 return;
1452
1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454 pll->disable(dev_priv, pll);
1455 pll->on = false;
1456 }
1457
1458 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460 {
1461 struct drm_device *dev = dev_priv->dev;
1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1464 uint32_t reg, val, pipeconf_val;
1465
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1468
1469 /* Make sure PCH DPLL is enabled */
1470 assert_shared_dpll_enabled(dev_priv,
1471 intel_crtc_to_shared_dpll(intel_crtc));
1472
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1476
1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
1484 }
1485
1486 reg = PCH_TRANSCONF(pipe);
1487 val = I915_READ(reg);
1488 pipeconf_val = I915_READ(PIPECONF(pipe));
1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
1497 }
1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1512 }
1513
1514 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1515 enum transcoder cpu_transcoder)
1516 {
1517 u32 val, pipeconf_val;
1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
1522 /* FDI must be feeding us bits for PCH ports */
1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1525
1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1530
1531 val = TRANS_ENABLE;
1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1533
1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
1536 val |= TRANS_INTERLACED;
1537 else
1538 val |= TRANS_PROGRESSIVE;
1539
1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1542 DRM_ERROR("Failed to enable PCH transcoder\n");
1543 }
1544
1545 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546 enum pipe pipe)
1547 {
1548 struct drm_device *dev = dev_priv->dev;
1549 uint32_t reg, val;
1550
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1554
1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1557
1558 reg = PCH_TRANSCONF(pipe);
1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1565
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1572 }
1573 }
1574
1575 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1576 {
1577 u32 val;
1578
1579 val = I915_READ(LPT_TRANSCONF);
1580 val &= ~TRANS_ENABLE;
1581 I915_WRITE(LPT_TRANSCONF, val);
1582 /* wait for PCH transcoder off, transcoder state */
1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1584 DRM_ERROR("Failed to disable PCH transcoder\n");
1585
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589 I915_WRITE(_TRANSA_CHICKEN2, val);
1590 }
1591
1592 /**
1593 * intel_enable_pipe - enable a pipe, asserting requirements
1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1597 *
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600 *
1601 * @pipe should be %PIPE_A or %PIPE_B.
1602 *
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1604 * returning.
1605 */
1606 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607 bool pch_port)
1608 {
1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610 pipe);
1611 enum pipe pch_transcoder;
1612 int reg;
1613 u32 val;
1614
1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
1618 if (HAS_PCH_LPT(dev_priv->dev))
1619 pch_transcoder = TRANSCODER_A;
1620 else
1621 pch_transcoder = pipe;
1622
1623 /*
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1626 * need the check.
1627 */
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
1630 else {
1631 if (pch_port) {
1632 /* if driving the PCH, we need FDI enabled */
1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
1636 }
1637 /* FIXME: assert CPU port conditions for SNB+ */
1638 }
1639
1640 reg = PIPECONF(cpu_transcoder);
1641 val = I915_READ(reg);
1642 if (val & PIPECONF_ENABLE)
1643 return;
1644
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1647 }
1648
1649 /**
1650 * intel_disable_pipe - disable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1653 *
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656 *
1657 * @pipe should be %PIPE_A or %PIPE_B.
1658 *
1659 * Will wait until the pipe has shut down before returning.
1660 */
1661 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663 {
1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
1666 int reg;
1667 u32 val;
1668
1669 /*
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1672 */
1673 assert_planes_disabled(dev_priv, pipe);
1674 assert_sprites_disabled(dev_priv, pipe);
1675
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678 return;
1679
1680 reg = PIPECONF(cpu_transcoder);
1681 val = I915_READ(reg);
1682 if ((val & PIPECONF_ENABLE) == 0)
1683 return;
1684
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687 }
1688
1689 /*
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1692 */
1693 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1694 enum plane plane)
1695 {
1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698 else
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1700 }
1701
1702 /**
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1707 *
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1709 */
1710 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1712 {
1713 int reg;
1714 u32 val;
1715
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1718
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
1721 if (val & DISPLAY_PLANE_ENABLE)
1722 return;
1723
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1725 intel_flush_display_plane(dev_priv, plane);
1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1727 }
1728
1729 /**
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1734 *
1735 * Disable @plane; should be an independent operation.
1736 */
1737 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1739 {
1740 int reg;
1741 u32 val;
1742
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746 return;
1747
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1751 }
1752
1753 static bool need_vtd_wa(struct drm_device *dev)
1754 {
1755 #ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757 return true;
1758 #endif
1759 return false;
1760 }
1761
1762 int
1763 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1764 struct drm_i915_gem_object *obj,
1765 struct intel_ring_buffer *pipelined)
1766 {
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 u32 alignment;
1769 int ret;
1770
1771 switch (obj->tiling_mode) {
1772 case I915_TILING_NONE:
1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
1775 else if (INTEL_INFO(dev)->gen >= 4)
1776 alignment = 4 * 1024;
1777 else
1778 alignment = 64 * 1024;
1779 break;
1780 case I915_TILING_X:
1781 /* pin() will align the object as required by fence */
1782 alignment = 0;
1783 break;
1784 case I915_TILING_Y:
1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1789 return -EINVAL;
1790 default:
1791 BUG();
1792 }
1793
1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1797 * the VT-d warning.
1798 */
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1801
1802 dev_priv->mm.interruptible = false;
1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1804 if (ret)
1805 goto err_interruptible;
1806
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1811 */
1812 ret = i915_gem_object_get_fence(obj);
1813 if (ret)
1814 goto err_unpin;
1815
1816 i915_gem_object_pin_fence(obj);
1817
1818 dev_priv->mm.interruptible = true;
1819 return 0;
1820
1821 err_unpin:
1822 i915_gem_object_unpin(obj);
1823 err_interruptible:
1824 dev_priv->mm.interruptible = true;
1825 return ret;
1826 }
1827
1828 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829 {
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1832 }
1833
1834 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
1836 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1838 unsigned int cpp,
1839 unsigned int pitch)
1840 {
1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
1843
1844 tile_rows = *y / 8;
1845 *y %= 8;
1846
1847 tiles = *x / (512/cpp);
1848 *x %= 512/cpp;
1849
1850 return tile_rows * pitch * 8 + tiles * 4096;
1851 } else {
1852 unsigned int offset;
1853
1854 offset = *y * pitch + *x * cpp;
1855 *y = 0;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1858 }
1859 }
1860
1861 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862 int x, int y)
1863 {
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
1868 struct drm_i915_gem_object *obj;
1869 int plane = intel_crtc->plane;
1870 unsigned long linear_offset;
1871 u32 dspcntr;
1872 u32 reg;
1873
1874 switch (plane) {
1875 case 0:
1876 case 1:
1877 break;
1878 default:
1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1880 return -EINVAL;
1881 }
1882
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
1885
1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1890 switch (fb->pixel_format) {
1891 case DRM_FORMAT_C8:
1892 dspcntr |= DISPPLANE_8BPP;
1893 break;
1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
1897 break;
1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1900 break;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1904 break;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1908 break;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1912 break;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
1916 break;
1917 default:
1918 BUG();
1919 }
1920
1921 if (INTEL_INFO(dev)->gen >= 4) {
1922 if (obj->tiling_mode != I915_TILING_NONE)
1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926 }
1927
1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
1931 I915_WRITE(reg, dspcntr);
1932
1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1934
1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1939 fb->pitches[0]);
1940 linear_offset -= intel_crtc->dspaddr_offset;
1941 } else {
1942 intel_crtc->dspaddr_offset = linear_offset;
1943 }
1944
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1948 if (INTEL_INFO(dev)->gen >= 4) {
1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
1953 } else
1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1955 POSTING_READ(reg);
1956
1957 return 0;
1958 }
1959
1960 static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1962 {
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
1969 unsigned long linear_offset;
1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 case 2:
1977 break;
1978 default:
1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1985
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
1996 break;
1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2000 break;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2004 break;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2008 break;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
2012 break;
2013 default:
2014 BUG();
2015 }
2016
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2019 else
2020 dspcntr &= ~DISPPLANE_TILED;
2021
2022 /* must disable */
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025 I915_WRITE(reg, dspcntr);
2026
2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2028 intel_crtc->dspaddr_offset =
2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2031 fb->pitches[0]);
2032 linear_offset -= intel_crtc->dspaddr_offset;
2033
2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041 } else {
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044 }
2045 POSTING_READ(reg);
2046
2047 return 0;
2048 }
2049
2050 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2051 static int
2052 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2054 {
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057
2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
2060 intel_increase_pllclock(crtc);
2061
2062 return dev_priv->display.update_plane(crtc, fb, x, y);
2063 }
2064
2065 void intel_display_handle_reset(struct drm_device *dev)
2066 {
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2069
2070 /*
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2074 *
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2078 *
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2082 */
2083
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2087
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2090 }
2091
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2098 crtc->x, crtc->y);
2099 mutex_unlock(&crtc->mutex);
2100 }
2101 }
2102
2103 static int
2104 intel_finish_fb(struct drm_framebuffer *old_fb)
2105 {
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2109 int ret;
2110
2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2114 * framebuffer.
2115 *
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2118 */
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2122
2123 return ret;
2124 }
2125
2126 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127 {
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132 if (!dev->primary->master)
2133 return;
2134
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2137 return;
2138
2139 switch (intel_crtc->pipe) {
2140 case 0:
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2143 break;
2144 case 1:
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2147 break;
2148 default:
2149 break;
2150 }
2151 }
2152
2153 static int
2154 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2155 struct drm_framebuffer *fb)
2156 {
2157 struct drm_device *dev = crtc->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160 struct drm_framebuffer *old_fb;
2161 int ret;
2162
2163 /* no fb bound */
2164 if (!fb) {
2165 DRM_ERROR("No FB bound\n");
2166 return 0;
2167 }
2168
2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
2173 return -EINVAL;
2174 }
2175
2176 mutex_lock(&dev->struct_mutex);
2177 ret = intel_pin_and_fence_fb_obj(dev,
2178 to_intel_framebuffer(fb)->obj,
2179 NULL);
2180 if (ret != 0) {
2181 mutex_unlock(&dev->struct_mutex);
2182 DRM_ERROR("pin & fence failed\n");
2183 return ret;
2184 }
2185
2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2187 if (ret) {
2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2189 mutex_unlock(&dev->struct_mutex);
2190 DRM_ERROR("failed to update base address\n");
2191 return ret;
2192 }
2193
2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
2196 crtc->x = x;
2197 crtc->y = y;
2198
2199 if (old_fb) {
2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2203 }
2204
2205 intel_update_fbc(dev);
2206 mutex_unlock(&dev->struct_mutex);
2207
2208 intel_crtc_update_sarea_pos(crtc, x, y);
2209
2210 return 0;
2211 }
2212
2213 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214 {
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2219 u32 reg, temp;
2220
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
2224 if (IS_IVYBRIDGE(dev)) {
2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2227 } else {
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2230 }
2231 I915_WRITE(reg, temp);
2232
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238 } else {
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2241 }
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244 /* wait one idle pattern time */
2245 POSTING_READ(reg);
2246 udelay(1000);
2247
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
2252 }
2253
2254 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255 {
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257 }
2258
2259 static void ivb_modeset_global_resources(struct drm_device *dev)
2260 {
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266 uint32_t temp;
2267
2268 /*
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2282 }
2283 }
2284
2285 /* The FDI link training functions for ILK/Ibexpeak. */
2286 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287 {
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
2292 int plane = intel_crtc->plane;
2293 u32 reg, temp, tries;
2294
2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2298
2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
2305 I915_WRITE(reg, temp);
2306 I915_READ(reg);
2307 udelay(150);
2308
2309 /* enable CPU FDI TX and PCH FDI RX */
2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2317
2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324 POSTING_READ(reg);
2325 udelay(150);
2326
2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
2331
2332 reg = FDI_RX_IIR(pipe);
2333 for (tries = 0; tries < 5; tries++) {
2334 temp = I915_READ(reg);
2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2340 break;
2341 }
2342 }
2343 if (tries == 5)
2344 DRM_ERROR("FDI train 1 fail!\n");
2345
2346 /* Train 2 */
2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
2351 I915_WRITE(reg, temp);
2352
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
2357 I915_WRITE(reg, temp);
2358
2359 POSTING_READ(reg);
2360 udelay(150);
2361
2362 reg = FDI_RX_IIR(pipe);
2363 for (tries = 0; tries < 5; tries++) {
2364 temp = I915_READ(reg);
2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 break;
2371 }
2372 }
2373 if (tries == 5)
2374 DRM_ERROR("FDI train 2 fail!\n");
2375
2376 DRM_DEBUG_KMS("FDI train done\n");
2377
2378 }
2379
2380 static const int snb_b_fdi_train_param[] = {
2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385 };
2386
2387 /* The FDI link training functions for SNB/Cougarpoint. */
2388 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389 {
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
2394 u32 reg, temp, i, retry;
2395
2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(150);
2406
2407 /* enable CPU FDI TX and PCH FDI RX */
2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415 /* SNB-B */
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2418
2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427 } else {
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430 }
2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
2434 udelay(150);
2435
2436 for (i = 0; i < 4; i++) {
2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
2441 I915_WRITE(reg, temp);
2442
2443 POSTING_READ(reg);
2444 udelay(500);
2445
2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453 break;
2454 }
2455 udelay(50);
2456 }
2457 if (retry < 5)
2458 break;
2459 }
2460 if (i == 4)
2461 DRM_ERROR("FDI train 1 fail!\n");
2462
2463 /* Train 2 */
2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2468 if (IS_GEN6(dev)) {
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 }
2473 I915_WRITE(reg, temp);
2474
2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 }
2484 I915_WRITE(reg, temp);
2485
2486 POSTING_READ(reg);
2487 udelay(150);
2488
2489 for (i = 0; i < 4; i++) {
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
2497 udelay(500);
2498
2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506 break;
2507 }
2508 udelay(50);
2509 }
2510 if (retry < 5)
2511 break;
2512 }
2513 if (i == 4)
2514 DRM_ERROR("FDI train 2 fail!\n");
2515
2516 DRM_DEBUG_KMS("FDI train done.\n");
2517 }
2518
2519 /* Manual link training for Ivy Bridge A0 parts */
2520 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521 {
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp, i;
2527
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
2537 udelay(150);
2538
2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2541
2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 temp |= FDI_COMPOSITE_SYNC;
2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2562 temp |= FDI_COMPOSITE_SYNC;
2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2600
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
2610 for (i = 0; i < 4; i++) {
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2627 break;
2628 }
2629 }
2630 if (i == 4)
2631 DRM_ERROR("FDI train 2 fail!\n");
2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634 }
2635
2636 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2637 {
2638 struct drm_device *dev = intel_crtc->base.dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 int pipe = intel_crtc->pipe;
2641 u32 reg, temp;
2642
2643
2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652 POSTING_READ(reg);
2653 udelay(200);
2654
2655 /* Switch from Rawclk to PCDclk */
2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659 POSTING_READ(reg);
2660 udelay(200);
2661
2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2667
2668 POSTING_READ(reg);
2669 udelay(100);
2670 }
2671 }
2672
2673 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674 {
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2678 u32 reg, temp;
2679
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
2691 udelay(100);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697 /* Wait for the clocks to turn off. */
2698 POSTING_READ(reg);
2699 udelay(100);
2700 }
2701
2702 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703 {
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714 POSTING_READ(reg);
2715
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2728 }
2729
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2736
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 }
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753 }
2754
2755 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2760 unsigned long flags;
2761 bool pending;
2762
2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2765 return false;
2766
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771 return pending;
2772 }
2773
2774 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775 {
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778
2779 if (crtc->fb == NULL)
2780 return;
2781
2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2786
2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
2790 }
2791
2792 /* Program iCLKIP clock to the desired frequency */
2793 static void lpt_program_iclkip(struct drm_crtc *crtc)
2794 {
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798 u32 temp;
2799
2800 mutex_lock(&dev_priv->dpio_lock);
2801
2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2804 */
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810 SBI_SSCCTL_DISABLE,
2811 SBI_ICLK);
2812
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2815 auxdiv = 1;
2816 divsel = 0x41;
2817 phaseinc = 0x20;
2818 } else {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2823 * precision.
2824 */
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2832
2833 auxdiv = 0;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2836 }
2837
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845 crtc->mode.clock,
2846 auxdiv,
2847 divsel,
2848 phasedir,
2849 phaseinc);
2850
2851 /* Program SSCDIVINTPHASE6 */
2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2860
2861 /* Program SSCAUXDIV */
2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2866
2867 /* Enable modulator and associated divider */
2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2869 temp &= ~SBI_SSCCTL_DISABLE;
2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2871
2872 /* Wait for initialization time */
2873 udelay(24);
2874
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2876
2877 mutex_unlock(&dev_priv->dpio_lock);
2878 }
2879
2880 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882 {
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902 }
2903
2904 /*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912 static void ironlake_pch_enable(struct drm_crtc *crtc)
2913 {
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
2918 u32 reg, temp;
2919
2920 assert_pch_transcoder_disabled(dev_priv, pipe);
2921
2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
2927 /* For PCH output, training FDI link */
2928 dev_priv->display.fdi_link_train(crtc);
2929
2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2933 *
2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
2938
2939 if (HAS_PCH_CPT(dev)) {
2940 u32 sel;
2941
2942 temp = I915_READ(PCH_DPLL_SEL);
2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2946 temp |= sel;
2947 else
2948 temp &= ~sel;
2949 I915_WRITE(PCH_DPLL_SEL, temp);
2950 }
2951
2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2955
2956 intel_fdi_normal_train(crtc);
2957
2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2966 TRANS_DP_SYNC_MASK |
2967 TRANS_DP_BPC_MASK);
2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
2970 temp |= bpc << 9; /* same format but at 11:9 */
2971
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2976
2977 switch (intel_trans_dp_port_sel(crtc)) {
2978 case PCH_DP_B:
2979 temp |= TRANS_DP_PORT_SEL_B;
2980 break;
2981 case PCH_DP_C:
2982 temp |= TRANS_DP_PORT_SEL_C;
2983 break;
2984 case PCH_DP_D:
2985 temp |= TRANS_DP_PORT_SEL_D;
2986 break;
2987 default:
2988 BUG();
2989 }
2990
2991 I915_WRITE(reg, temp);
2992 }
2993
2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
2995 }
2996
2997 static void lpt_pch_enable(struct drm_crtc *crtc)
2998 {
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3003
3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3005
3006 lpt_program_iclkip(crtc);
3007
3008 /* Set transcoder timing. */
3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3010
3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3012 }
3013
3014 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3015 {
3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3017
3018 if (pll == NULL)
3019 return;
3020
3021 if (pll->refcount == 0) {
3022 WARN(1, "bad %s refcount\n", pll->name);
3023 return;
3024 }
3025
3026 if (--pll->refcount == 0) {
3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3032 }
3033
3034 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3035 {
3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
3039
3040 if (pll) {
3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
3043 intel_put_shared_dpll(crtc);
3044 }
3045
3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3048 i = crtc->pipe;
3049 pll = &dev_priv->shared_dplls[i];
3050
3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
3053
3054 goto found;
3055 }
3056
3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
3059
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3062 continue;
3063
3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065 fp == I915_READ(PCH_FP0(pll->id))) {
3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3067 crtc->base.base.id,
3068 pll->name, pll->refcount, pll->active);
3069
3070 goto found;
3071 }
3072 }
3073
3074 /* Ok no matching timings, maybe there's a free one? */
3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
3077 if (pll->refcount == 0) {
3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
3080 goto found;
3081 }
3082 }
3083
3084 return NULL;
3085
3086 found:
3087 crtc->config.shared_dpll = i;
3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
3090
3091 if (pll->active == 0) {
3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093 sizeof(pll->hw_state));
3094
3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3096 WARN_ON(pll->on);
3097 assert_shared_dpll_disabled(dev_priv, pll);
3098
3099 /* Wait for the clocks to stabilize before rewriting the regs */
3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
3102 udelay(150);
3103
3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3106 }
3107 pll->refcount++;
3108
3109 return pll;
3110 }
3111
3112 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3113 {
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 int dslreg = PIPEDSL(pipe);
3116 u32 temp;
3117
3118 temp = I915_READ(dslreg);
3119 udelay(500);
3120 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3121 if (wait_for(I915_READ(dslreg) != temp, 5))
3122 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3123 }
3124 }
3125
3126 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127 {
3128 struct drm_device *dev = crtc->base.dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int pipe = crtc->pipe;
3131
3132 if (crtc->config.pch_pfit.size) {
3133 /* Force use of hard-coded filter coefficients
3134 * as some pre-programmed values are broken,
3135 * e.g. x201.
3136 */
3137 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139 PF_PIPE_SEL_IVB(pipe));
3140 else
3141 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3144 }
3145 }
3146
3147 static void intel_enable_planes(struct drm_crtc *crtc)
3148 {
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3152
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3156 }
3157
3158 static void intel_disable_planes(struct drm_crtc *crtc)
3159 {
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3167 }
3168
3169 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170 {
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174 struct intel_encoder *encoder;
3175 int pipe = intel_crtc->pipe;
3176 int plane = intel_crtc->plane;
3177 u32 temp;
3178
3179 WARN_ON(!crtc->enabled);
3180
3181 if (intel_crtc->active)
3182 return;
3183
3184 intel_crtc->active = true;
3185
3186 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
3189 intel_update_watermarks(dev);
3190
3191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192 temp = I915_READ(PCH_LVDS);
3193 if ((temp & LVDS_PORT_EN) == 0)
3194 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3195 }
3196
3197
3198 if (intel_crtc->config.has_pch_encoder) {
3199 /* Note: FDI PLL enabling _must_ be done before we enable the
3200 * cpu pipes, hence this is separate from all the other fdi/pch
3201 * enabling. */
3202 ironlake_fdi_pll_enable(intel_crtc);
3203 } else {
3204 assert_fdi_tx_disabled(dev_priv, pipe);
3205 assert_fdi_rx_disabled(dev_priv, pipe);
3206 }
3207
3208 for_each_encoder_on_crtc(dev, crtc, encoder)
3209 if (encoder->pre_enable)
3210 encoder->pre_enable(encoder);
3211
3212 ironlake_pfit_enable(intel_crtc);
3213
3214 /*
3215 * On ILK+ LUT must be loaded before the pipe is running but with
3216 * clocks enabled
3217 */
3218 intel_crtc_load_lut(crtc);
3219
3220 intel_enable_pipe(dev_priv, pipe,
3221 intel_crtc->config.has_pch_encoder);
3222 intel_enable_plane(dev_priv, plane, pipe);
3223 intel_enable_planes(crtc);
3224 intel_crtc_update_cursor(crtc, true);
3225
3226 if (intel_crtc->config.has_pch_encoder)
3227 ironlake_pch_enable(crtc);
3228
3229 mutex_lock(&dev->struct_mutex);
3230 intel_update_fbc(dev);
3231 mutex_unlock(&dev->struct_mutex);
3232
3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3234 encoder->enable(encoder);
3235
3236 if (HAS_PCH_CPT(dev))
3237 cpt_verify_modeset(dev, intel_crtc->pipe);
3238
3239 /*
3240 * There seems to be a race in PCH platform hw (at least on some
3241 * outputs) where an enabled pipe still completes any pageflip right
3242 * away (as if the pipe is off) instead of waiting for vblank. As soon
3243 * as the first vblank happend, everything works as expected. Hence just
3244 * wait for one vblank before returning to avoid strange things
3245 * happening.
3246 */
3247 intel_wait_for_vblank(dev, intel_crtc->pipe);
3248 }
3249
3250 /* IPS only exists on ULT machines and is tied to pipe A. */
3251 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3252 {
3253 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3254 }
3255
3256 static void hsw_enable_ips(struct intel_crtc *crtc)
3257 {
3258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3259
3260 if (!crtc->config.ips_enabled)
3261 return;
3262
3263 /* We can only enable IPS after we enable a plane and wait for a vblank.
3264 * We guarantee that the plane is enabled by calling intel_enable_ips
3265 * only after intel_enable_plane. And intel_enable_plane already waits
3266 * for a vblank, so all we need to do here is to enable the IPS bit. */
3267 assert_plane_enabled(dev_priv, crtc->plane);
3268 I915_WRITE(IPS_CTL, IPS_ENABLE);
3269 }
3270
3271 static void hsw_disable_ips(struct intel_crtc *crtc)
3272 {
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275
3276 if (!crtc->config.ips_enabled)
3277 return;
3278
3279 assert_plane_enabled(dev_priv, crtc->plane);
3280 I915_WRITE(IPS_CTL, 0);
3281
3282 /* We need to wait for a vblank before we can disable the plane. */
3283 intel_wait_for_vblank(dev, crtc->pipe);
3284 }
3285
3286 static void haswell_crtc_enable(struct drm_crtc *crtc)
3287 {
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 struct intel_encoder *encoder;
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
3294
3295 WARN_ON(!crtc->enabled);
3296
3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 if (intel_crtc->config.has_pch_encoder)
3304 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3305
3306 intel_update_watermarks(dev);
3307
3308 if (intel_crtc->config.has_pch_encoder)
3309 dev_priv->display.fdi_link_train(crtc);
3310
3311 for_each_encoder_on_crtc(dev, crtc, encoder)
3312 if (encoder->pre_enable)
3313 encoder->pre_enable(encoder);
3314
3315 intel_ddi_enable_pipe_clock(intel_crtc);
3316
3317 ironlake_pfit_enable(intel_crtc);
3318
3319 /*
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3321 * clocks enabled
3322 */
3323 intel_crtc_load_lut(crtc);
3324
3325 intel_ddi_set_pipe_settings(crtc);
3326 intel_ddi_enable_transcoder_func(crtc);
3327
3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3333
3334 hsw_enable_ips(intel_crtc);
3335
3336 if (intel_crtc->config.has_pch_encoder)
3337 lpt_pch_enable(crtc);
3338
3339 mutex_lock(&dev->struct_mutex);
3340 intel_update_fbc(dev);
3341 mutex_unlock(&dev->struct_mutex);
3342
3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3345
3346 /*
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3352 * happening.
3353 */
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3355 }
3356
3357 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358 {
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370 }
3371
3372 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373 {
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377 struct intel_encoder *encoder;
3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
3380 u32 reg, temp;
3381
3382
3383 if (!intel_crtc->active)
3384 return;
3385
3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
3389 intel_crtc_wait_for_pending_flips(crtc);
3390 drm_vblank_off(dev, pipe);
3391
3392 if (dev_priv->cfb_plane == plane)
3393 intel_disable_fbc(dev);
3394
3395 intel_crtc_update_cursor(crtc, false);
3396 intel_disable_planes(crtc);
3397 intel_disable_plane(dev_priv, plane, pipe);
3398
3399 if (intel_crtc->config.has_pch_encoder)
3400 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3401
3402 intel_disable_pipe(dev_priv, pipe);
3403
3404 ironlake_pfit_disable(intel_crtc);
3405
3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 if (encoder->post_disable)
3408 encoder->post_disable(encoder);
3409
3410 if (intel_crtc->config.has_pch_encoder) {
3411 ironlake_fdi_disable(crtc);
3412
3413 ironlake_disable_pch_transcoder(dev_priv, pipe);
3414 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3415
3416 if (HAS_PCH_CPT(dev)) {
3417 /* disable TRANS_DP_CTL */
3418 reg = TRANS_DP_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3421 TRANS_DP_PORT_SEL_MASK);
3422 temp |= TRANS_DP_PORT_SEL_NONE;
3423 I915_WRITE(reg, temp);
3424
3425 /* disable DPLL_SEL */
3426 temp = I915_READ(PCH_DPLL_SEL);
3427 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3428 I915_WRITE(PCH_DPLL_SEL, temp);
3429 }
3430
3431 /* disable PCH DPLL */
3432 intel_disable_shared_dpll(intel_crtc);
3433
3434 ironlake_fdi_pll_disable(intel_crtc);
3435 }
3436
3437 intel_crtc->active = false;
3438 intel_update_watermarks(dev);
3439
3440 mutex_lock(&dev->struct_mutex);
3441 intel_update_fbc(dev);
3442 mutex_unlock(&dev->struct_mutex);
3443 }
3444
3445 static void haswell_crtc_disable(struct drm_crtc *crtc)
3446 {
3447 struct drm_device *dev = crtc->dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450 struct intel_encoder *encoder;
3451 int pipe = intel_crtc->pipe;
3452 int plane = intel_crtc->plane;
3453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3454
3455 if (!intel_crtc->active)
3456 return;
3457
3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 encoder->disable(encoder);
3460
3461 intel_crtc_wait_for_pending_flips(crtc);
3462 drm_vblank_off(dev, pipe);
3463
3464 /* FBC must be disabled before disabling the plane on HSW. */
3465 if (dev_priv->cfb_plane == plane)
3466 intel_disable_fbc(dev);
3467
3468 hsw_disable_ips(intel_crtc);
3469
3470 intel_crtc_update_cursor(crtc, false);
3471 intel_disable_planes(crtc);
3472 intel_disable_plane(dev_priv, plane, pipe);
3473
3474 if (intel_crtc->config.has_pch_encoder)
3475 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3476 intel_disable_pipe(dev_priv, pipe);
3477
3478 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3479
3480 ironlake_pfit_disable(intel_crtc);
3481
3482 intel_ddi_disable_pipe_clock(intel_crtc);
3483
3484 for_each_encoder_on_crtc(dev, crtc, encoder)
3485 if (encoder->post_disable)
3486 encoder->post_disable(encoder);
3487
3488 if (intel_crtc->config.has_pch_encoder) {
3489 lpt_disable_pch_transcoder(dev_priv);
3490 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3491 intel_ddi_fdi_disable(crtc);
3492 }
3493
3494 intel_crtc->active = false;
3495 intel_update_watermarks(dev);
3496
3497 mutex_lock(&dev->struct_mutex);
3498 intel_update_fbc(dev);
3499 mutex_unlock(&dev->struct_mutex);
3500 }
3501
3502 static void ironlake_crtc_off(struct drm_crtc *crtc)
3503 {
3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505 intel_put_shared_dpll(intel_crtc);
3506 }
3507
3508 static void haswell_crtc_off(struct drm_crtc *crtc)
3509 {
3510 intel_ddi_put_crtc_pll(crtc);
3511 }
3512
3513 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3514 {
3515 if (!enable && intel_crtc->overlay) {
3516 struct drm_device *dev = intel_crtc->base.dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519 mutex_lock(&dev->struct_mutex);
3520 dev_priv->mm.interruptible = false;
3521 (void) intel_overlay_switch_off(intel_crtc->overlay);
3522 dev_priv->mm.interruptible = true;
3523 mutex_unlock(&dev->struct_mutex);
3524 }
3525
3526 /* Let userspace switch the overlay on again. In most cases userspace
3527 * has to recompute where to put it anyway.
3528 */
3529 }
3530
3531 /**
3532 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3533 * cursor plane briefly if not already running after enabling the display
3534 * plane.
3535 * This workaround avoids occasional blank screens when self refresh is
3536 * enabled.
3537 */
3538 static void
3539 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3540 {
3541 u32 cntl = I915_READ(CURCNTR(pipe));
3542
3543 if ((cntl & CURSOR_MODE) == 0) {
3544 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3545
3546 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3547 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3548 intel_wait_for_vblank(dev_priv->dev, pipe);
3549 I915_WRITE(CURCNTR(pipe), cntl);
3550 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3551 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3552 }
3553 }
3554
3555 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3556 {
3557 struct drm_device *dev = crtc->base.dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct intel_crtc_config *pipe_config = &crtc->config;
3560
3561 if (!crtc->config.gmch_pfit.control)
3562 return;
3563
3564 /*
3565 * The panel fitter should only be adjusted whilst the pipe is disabled,
3566 * according to register description and PRM.
3567 */
3568 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3569 assert_pipe_disabled(dev_priv, crtc->pipe);
3570
3571 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3572 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3573
3574 /* Border color in case we don't scale up to the full screen. Black by
3575 * default, change to something else for debugging. */
3576 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3577 }
3578
3579 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3580 {
3581 struct drm_device *dev = crtc->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3584 struct intel_encoder *encoder;
3585 int pipe = intel_crtc->pipe;
3586 int plane = intel_crtc->plane;
3587
3588 WARN_ON(!crtc->enabled);
3589
3590 if (intel_crtc->active)
3591 return;
3592
3593 intel_crtc->active = true;
3594 intel_update_watermarks(dev);
3595
3596 mutex_lock(&dev_priv->dpio_lock);
3597
3598 for_each_encoder_on_crtc(dev, crtc, encoder)
3599 if (encoder->pre_pll_enable)
3600 encoder->pre_pll_enable(encoder);
3601
3602 intel_enable_pll(dev_priv, pipe);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_enable)
3606 encoder->pre_enable(encoder);
3607
3608 /* VLV wants encoder enabling _before_ the pipe is up. */
3609 for_each_encoder_on_crtc(dev, crtc, encoder)
3610 encoder->enable(encoder);
3611
3612 i9xx_pfit_enable(intel_crtc);
3613
3614 intel_crtc_load_lut(crtc);
3615
3616 intel_enable_pipe(dev_priv, pipe, false);
3617 intel_enable_plane(dev_priv, plane, pipe);
3618 intel_enable_planes(crtc);
3619 intel_crtc_update_cursor(crtc, true);
3620
3621 intel_update_fbc(dev);
3622
3623 mutex_unlock(&dev_priv->dpio_lock);
3624 }
3625
3626 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3627 {
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 struct intel_encoder *encoder;
3632 int pipe = intel_crtc->pipe;
3633 int plane = intel_crtc->plane;
3634
3635 WARN_ON(!crtc->enabled);
3636
3637 if (intel_crtc->active)
3638 return;
3639
3640 intel_crtc->active = true;
3641 intel_update_watermarks(dev);
3642
3643 intel_enable_pll(dev_priv, pipe);
3644
3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 if (encoder->pre_enable)
3647 encoder->pre_enable(encoder);
3648
3649 i9xx_pfit_enable(intel_crtc);
3650
3651 intel_crtc_load_lut(crtc);
3652
3653 intel_enable_pipe(dev_priv, pipe, false);
3654 intel_enable_plane(dev_priv, plane, pipe);
3655 intel_enable_planes(crtc);
3656 /* The fixup needs to happen before cursor is enabled */
3657 if (IS_G4X(dev))
3658 g4x_fixup_plane(dev_priv, pipe);
3659 intel_crtc_update_cursor(crtc, true);
3660
3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3662 intel_crtc_dpms_overlay(intel_crtc, true);
3663
3664 intel_update_fbc(dev);
3665
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 encoder->enable(encoder);
3668 }
3669
3670 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3671 {
3672 struct drm_device *dev = crtc->base.dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674
3675 if (!crtc->config.gmch_pfit.control)
3676 return;
3677
3678 assert_pipe_disabled(dev_priv, crtc->pipe);
3679
3680 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3681 I915_READ(PFIT_CONTROL));
3682 I915_WRITE(PFIT_CONTROL, 0);
3683 }
3684
3685 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3686 {
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690 struct intel_encoder *encoder;
3691 int pipe = intel_crtc->pipe;
3692 int plane = intel_crtc->plane;
3693
3694 if (!intel_crtc->active)
3695 return;
3696
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 encoder->disable(encoder);
3699
3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
3701 intel_crtc_wait_for_pending_flips(crtc);
3702 drm_vblank_off(dev, pipe);
3703
3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
3706
3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
3709 intel_disable_planes(crtc);
3710 intel_disable_plane(dev_priv, plane, pipe);
3711
3712 intel_disable_pipe(dev_priv, pipe);
3713
3714 i9xx_pfit_disable(intel_crtc);
3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->post_disable)
3718 encoder->post_disable(encoder);
3719
3720 intel_disable_pll(dev_priv, pipe);
3721
3722 intel_crtc->active = false;
3723 intel_update_fbc(dev);
3724 intel_update_watermarks(dev);
3725 }
3726
3727 static void i9xx_crtc_off(struct drm_crtc *crtc)
3728 {
3729 }
3730
3731 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3732 bool enabled)
3733 {
3734 struct drm_device *dev = crtc->dev;
3735 struct drm_i915_master_private *master_priv;
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737 int pipe = intel_crtc->pipe;
3738
3739 if (!dev->primary->master)
3740 return;
3741
3742 master_priv = dev->primary->master->driver_priv;
3743 if (!master_priv->sarea_priv)
3744 return;
3745
3746 switch (pipe) {
3747 case 0:
3748 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3750 break;
3751 case 1:
3752 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 default:
3756 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3757 break;
3758 }
3759 }
3760
3761 /**
3762 * Sets the power management mode of the pipe and plane.
3763 */
3764 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3765 {
3766 struct drm_device *dev = crtc->dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 struct intel_encoder *intel_encoder;
3769 bool enable = false;
3770
3771 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3772 enable |= intel_encoder->connectors_active;
3773
3774 if (enable)
3775 dev_priv->display.crtc_enable(crtc);
3776 else
3777 dev_priv->display.crtc_disable(crtc);
3778
3779 intel_crtc_update_sarea(crtc, enable);
3780 }
3781
3782 static void intel_crtc_disable(struct drm_crtc *crtc)
3783 {
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_connector *connector;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3788
3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc->enabled);
3791
3792 dev_priv->display.crtc_disable(crtc);
3793 intel_crtc->eld_vld = false;
3794 intel_crtc_update_sarea(crtc, false);
3795 dev_priv->display.off(crtc);
3796
3797 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3799
3800 if (crtc->fb) {
3801 mutex_lock(&dev->struct_mutex);
3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3803 mutex_unlock(&dev->struct_mutex);
3804 crtc->fb = NULL;
3805 }
3806
3807 /* Update computed state. */
3808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809 if (!connector->encoder || !connector->encoder->crtc)
3810 continue;
3811
3812 if (connector->encoder->crtc != crtc)
3813 continue;
3814
3815 connector->dpms = DRM_MODE_DPMS_OFF;
3816 to_intel_encoder(connector->encoder)->connectors_active = false;
3817 }
3818 }
3819
3820 void intel_modeset_disable(struct drm_device *dev)
3821 {
3822 struct drm_crtc *crtc;
3823
3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3825 if (crtc->enabled)
3826 intel_crtc_disable(crtc);
3827 }
3828 }
3829
3830 void intel_encoder_destroy(struct drm_encoder *encoder)
3831 {
3832 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3833
3834 drm_encoder_cleanup(encoder);
3835 kfree(intel_encoder);
3836 }
3837
3838 /* Simple dpms helper for encodres with just one connector, no cloning and only
3839 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3840 * state of the entire output pipe. */
3841 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3842 {
3843 if (mode == DRM_MODE_DPMS_ON) {
3844 encoder->connectors_active = true;
3845
3846 intel_crtc_update_dpms(encoder->base.crtc);
3847 } else {
3848 encoder->connectors_active = false;
3849
3850 intel_crtc_update_dpms(encoder->base.crtc);
3851 }
3852 }
3853
3854 /* Cross check the actual hw state with our own modeset state tracking (and it's
3855 * internal consistency). */
3856 static void intel_connector_check_state(struct intel_connector *connector)
3857 {
3858 if (connector->get_hw_state(connector)) {
3859 struct intel_encoder *encoder = connector->encoder;
3860 struct drm_crtc *crtc;
3861 bool encoder_enabled;
3862 enum pipe pipe;
3863
3864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3865 connector->base.base.id,
3866 drm_get_connector_name(&connector->base));
3867
3868 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3869 "wrong connector dpms state\n");
3870 WARN(connector->base.encoder != &encoder->base,
3871 "active connector not linked to encoder\n");
3872 WARN(!encoder->connectors_active,
3873 "encoder->connectors_active not set\n");
3874
3875 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3876 WARN(!encoder_enabled, "encoder not enabled\n");
3877 if (WARN_ON(!encoder->base.crtc))
3878 return;
3879
3880 crtc = encoder->base.crtc;
3881
3882 WARN(!crtc->enabled, "crtc not enabled\n");
3883 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3884 WARN(pipe != to_intel_crtc(crtc)->pipe,
3885 "encoder active on the wrong pipe\n");
3886 }
3887 }
3888
3889 /* Even simpler default implementation, if there's really no special case to
3890 * consider. */
3891 void intel_connector_dpms(struct drm_connector *connector, int mode)
3892 {
3893 struct intel_encoder *encoder = intel_attached_encoder(connector);
3894
3895 /* All the simple cases only support two dpms states. */
3896 if (mode != DRM_MODE_DPMS_ON)
3897 mode = DRM_MODE_DPMS_OFF;
3898
3899 if (mode == connector->dpms)
3900 return;
3901
3902 connector->dpms = mode;
3903
3904 /* Only need to change hw state when actually enabled */
3905 if (encoder->base.crtc)
3906 intel_encoder_dpms(encoder, mode);
3907 else
3908 WARN_ON(encoder->connectors_active != false);
3909
3910 intel_modeset_check_state(connector->dev);
3911 }
3912
3913 /* Simple connector->get_hw_state implementation for encoders that support only
3914 * one connector and no cloning and hence the encoder state determines the state
3915 * of the connector. */
3916 bool intel_connector_get_hw_state(struct intel_connector *connector)
3917 {
3918 enum pipe pipe = 0;
3919 struct intel_encoder *encoder = connector->encoder;
3920
3921 return encoder->get_hw_state(encoder, &pipe);
3922 }
3923
3924 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3925 struct intel_crtc_config *pipe_config)
3926 {
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *pipe_B_crtc =
3929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3930
3931 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932 pipe_name(pipe), pipe_config->fdi_lanes);
3933 if (pipe_config->fdi_lanes > 4) {
3934 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3936 return false;
3937 }
3938
3939 if (IS_HASWELL(dev)) {
3940 if (pipe_config->fdi_lanes > 2) {
3941 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942 pipe_config->fdi_lanes);
3943 return false;
3944 } else {
3945 return true;
3946 }
3947 }
3948
3949 if (INTEL_INFO(dev)->num_pipes == 2)
3950 return true;
3951
3952 /* Ivybridge 3 pipe is really complicated */
3953 switch (pipe) {
3954 case PIPE_A:
3955 return true;
3956 case PIPE_B:
3957 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958 pipe_config->fdi_lanes > 2) {
3959 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960 pipe_name(pipe), pipe_config->fdi_lanes);
3961 return false;
3962 }
3963 return true;
3964 case PIPE_C:
3965 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3966 pipe_B_crtc->config.fdi_lanes <= 2) {
3967 if (pipe_config->fdi_lanes > 2) {
3968 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969 pipe_name(pipe), pipe_config->fdi_lanes);
3970 return false;
3971 }
3972 } else {
3973 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3974 return false;
3975 }
3976 return true;
3977 default:
3978 BUG();
3979 }
3980 }
3981
3982 #define RETRY 1
3983 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984 struct intel_crtc_config *pipe_config)
3985 {
3986 struct drm_device *dev = intel_crtc->base.dev;
3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3988 int lane, link_bw, fdi_dotclock;
3989 bool setup_ok, needs_recompute = false;
3990
3991 retry:
3992 /* FDI is a binary signal running at ~2.7GHz, encoding
3993 * each output octet as 10 bits. The actual frequency
3994 * is stored as a divider into a 100MHz clock, and the
3995 * mode pixel clock is stored in units of 1KHz.
3996 * Hence the bw of each lane in terms of the mode signal
3997 * is:
3998 */
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000
4001 fdi_dotclock = adjusted_mode->clock;
4002 fdi_dotclock /= pipe_config->pixel_multiplier;
4003
4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4005 pipe_config->pipe_bpp);
4006
4007 pipe_config->fdi_lanes = lane;
4008
4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4010 link_bw, &pipe_config->fdi_m_n);
4011
4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4013 intel_crtc->pipe, pipe_config);
4014 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4015 pipe_config->pipe_bpp -= 2*3;
4016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4017 pipe_config->pipe_bpp);
4018 needs_recompute = true;
4019 pipe_config->bw_constrained = true;
4020
4021 goto retry;
4022 }
4023
4024 if (needs_recompute)
4025 return RETRY;
4026
4027 return setup_ok ? 0 : -EINVAL;
4028 }
4029
4030 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4031 struct intel_crtc_config *pipe_config)
4032 {
4033 pipe_config->ips_enabled = i915_enable_ips &&
4034 hsw_crtc_supports_ips(crtc) &&
4035 pipe_config->pipe_bpp == 24;
4036 }
4037
4038 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4039 struct intel_crtc_config *pipe_config)
4040 {
4041 struct drm_device *dev = crtc->base.dev;
4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4043
4044 if (HAS_PCH_SPLIT(dev)) {
4045 /* FDI link clock is fixed at 2.7G */
4046 if (pipe_config->requested_mode.clock * 3
4047 > IRONLAKE_FDI_FREQ * 4)
4048 return -EINVAL;
4049 }
4050
4051 /* All interlaced capable intel hw wants timings in frames. Note though
4052 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4053 * timings, so we need to be careful not to clobber these.*/
4054 if (!pipe_config->timings_set)
4055 drm_mode_set_crtcinfo(adjusted_mode, 0);
4056
4057 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4058 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4059 */
4060 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4061 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4062 return -EINVAL;
4063
4064 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4065 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4066 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4067 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4068 * for lvds. */
4069 pipe_config->pipe_bpp = 8*3;
4070 }
4071
4072 if (IS_HASWELL(dev))
4073 hsw_compute_ips_config(crtc, pipe_config);
4074
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
4079
4080 if (pipe_config->has_pch_encoder)
4081 return ironlake_fdi_compute_config(crtc, pipe_config);
4082
4083 return 0;
4084 }
4085
4086 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4087 {
4088 return 400000; /* FIXME */
4089 }
4090
4091 static int i945_get_display_clock_speed(struct drm_device *dev)
4092 {
4093 return 400000;
4094 }
4095
4096 static int i915_get_display_clock_speed(struct drm_device *dev)
4097 {
4098 return 333000;
4099 }
4100
4101 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4102 {
4103 return 200000;
4104 }
4105
4106 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4107 {
4108 u16 gcfgc = 0;
4109
4110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4111
4112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4113 return 133000;
4114 else {
4115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116 case GC_DISPLAY_CLOCK_333_MHZ:
4117 return 333000;
4118 default:
4119 case GC_DISPLAY_CLOCK_190_200_MHZ:
4120 return 190000;
4121 }
4122 }
4123 }
4124
4125 static int i865_get_display_clock_speed(struct drm_device *dev)
4126 {
4127 return 266000;
4128 }
4129
4130 static int i855_get_display_clock_speed(struct drm_device *dev)
4131 {
4132 u16 hpllcc = 0;
4133 /* Assume that the hardware is in the high speed state. This
4134 * should be the default.
4135 */
4136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137 case GC_CLOCK_133_200:
4138 case GC_CLOCK_100_200:
4139 return 200000;
4140 case GC_CLOCK_166_250:
4141 return 250000;
4142 case GC_CLOCK_100_133:
4143 return 133000;
4144 }
4145
4146 /* Shouldn't happen */
4147 return 0;
4148 }
4149
4150 static int i830_get_display_clock_speed(struct drm_device *dev)
4151 {
4152 return 133000;
4153 }
4154
4155 static void
4156 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4157 {
4158 while (*num > DATA_LINK_M_N_MASK ||
4159 *den > DATA_LINK_M_N_MASK) {
4160 *num >>= 1;
4161 *den >>= 1;
4162 }
4163 }
4164
4165 static void compute_m_n(unsigned int m, unsigned int n,
4166 uint32_t *ret_m, uint32_t *ret_n)
4167 {
4168 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170 intel_reduce_m_n_ratio(ret_m, ret_n);
4171 }
4172
4173 void
4174 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175 int pixel_clock, int link_clock,
4176 struct intel_link_m_n *m_n)
4177 {
4178 m_n->tu = 64;
4179
4180 compute_m_n(bits_per_pixel * pixel_clock,
4181 link_clock * nlanes * 8,
4182 &m_n->gmch_m, &m_n->gmch_n);
4183
4184 compute_m_n(pixel_clock, link_clock,
4185 &m_n->link_m, &m_n->link_n);
4186 }
4187
4188 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4189 {
4190 if (i915_panel_use_ssc >= 0)
4191 return i915_panel_use_ssc != 0;
4192 return dev_priv->vbt.lvds_use_ssc
4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4194 }
4195
4196 static int vlv_get_refclk(struct drm_crtc *crtc)
4197 {
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk = 27000; /* for DP & HDMI */
4201
4202 return 100000; /* only one validated so far */
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205 refclk = 96000;
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 if (intel_panel_use_ssc(dev_priv))
4208 refclk = 100000;
4209 else
4210 refclk = 96000;
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4212 refclk = 100000;
4213 }
4214
4215 return refclk;
4216 }
4217
4218 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219 {
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 int refclk;
4223
4224 if (IS_VALLEYVIEW(dev)) {
4225 refclk = vlv_get_refclk(crtc);
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230 refclk / 1000);
4231 } else if (!IS_GEN2(dev)) {
4232 refclk = 96000;
4233 } else {
4234 refclk = 48000;
4235 }
4236
4237 return refclk;
4238 }
4239
4240 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4241 {
4242 return (1 << dpll->n) << 16 | dpll->m2;
4243 }
4244
4245 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246 {
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4248 }
4249
4250 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4251 intel_clock_t *reduced_clock)
4252 {
4253 struct drm_device *dev = crtc->base.dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 int pipe = crtc->pipe;
4256 u32 fp, fp2 = 0;
4257
4258 if (IS_PINEVIEW(dev)) {
4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4260 if (reduced_clock)
4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
4262 } else {
4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4264 if (reduced_clock)
4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4266 }
4267
4268 I915_WRITE(FP0(pipe), fp);
4269
4270 crtc->lowfreq_avail = false;
4271 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4272 reduced_clock && i915_powersave) {
4273 I915_WRITE(FP1(pipe), fp2);
4274 crtc->lowfreq_avail = true;
4275 } else {
4276 I915_WRITE(FP1(pipe), fp);
4277 }
4278 }
4279
4280 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281 {
4282 u32 reg_val;
4283
4284 /*
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4287 */
4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4292
4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4297
4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4299 reg_val &= 0xffffff00;
4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306 }
4307
4308 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4310 {
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4314
4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4319 }
4320
4321 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4323 {
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334 } else {
4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4339 }
4340 }
4341
4342 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4343 {
4344 if (crtc->config.has_pch_encoder)
4345 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4346 else
4347 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4348 }
4349
4350 static void vlv_update_pll(struct intel_crtc *crtc)
4351 {
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_encoder *encoder;
4355 int pipe = crtc->pipe;
4356 u32 dpll, mdiv;
4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4358 bool is_hdmi;
4359 u32 coreclk, reg_val, dpll_md;
4360
4361 mutex_lock(&dev_priv->dpio_lock);
4362
4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4364
4365 bestn = crtc->config.dpll.n;
4366 bestm1 = crtc->config.dpll.m1;
4367 bestm2 = crtc->config.dpll.m2;
4368 bestp1 = crtc->config.dpll.p1;
4369 bestp2 = crtc->config.dpll.p2;
4370
4371 /* See eDP HDMI DPIO driver vbios notes doc */
4372
4373 /* PLL B needs special handling */
4374 if (pipe)
4375 vlv_pllb_recal_opamp(dev_priv);
4376
4377 /* Set up Tx target for periodic Rcomp update */
4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4379
4380 /* Disable target IRef on PLL */
4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4382 reg_val &= 0x00ffffff;
4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4384
4385 /* Disable fast lock */
4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4387
4388 /* Set idtafcrecal before PLL is enabled */
4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391 mdiv |= ((bestn << DPIO_N_SHIFT));
4392 mdiv |= (1 << DPIO_K_SHIFT);
4393
4394 /*
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4398 */
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404
4405 /* Set HBR and RBR LPF coefficients */
4406 if (crtc->config.port_clock == 162000 ||
4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4408 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4409 0x005f0021);
4410 else
4411 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4412 0x00d0000f);
4413
4414 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4415 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4416 /* Use SSC source */
4417 if (!pipe)
4418 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4419 0x0df40000);
4420 else
4421 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4422 0x0df70000);
4423 } else { /* HDMI or VGA */
4424 /* Use bend source */
4425 if (!pipe)
4426 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4427 0x0df70000);
4428 else
4429 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4430 0x0df40000);
4431 }
4432
4433 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4434 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4435 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4436 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4437 coreclk |= 0x01000000;
4438 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4439
4440 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4441
4442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4443 if (encoder->pre_pll_enable)
4444 encoder->pre_pll_enable(encoder);
4445
4446 /* Enable DPIO clock input */
4447 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4448 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4449 if (pipe)
4450 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4451
4452 dpll |= DPLL_VCO_ENABLE;
4453 I915_WRITE(DPLL(pipe), dpll);
4454 POSTING_READ(DPLL(pipe));
4455 udelay(150);
4456
4457 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4458 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4459
4460 dpll_md = (crtc->config.pixel_multiplier - 1)
4461 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4462 I915_WRITE(DPLL_MD(pipe), dpll_md);
4463 POSTING_READ(DPLL_MD(pipe));
4464
4465 if (crtc->config.has_dp_encoder)
4466 intel_dp_set_m_n(crtc);
4467
4468 mutex_unlock(&dev_priv->dpio_lock);
4469 }
4470
4471 static void i9xx_update_pll(struct intel_crtc *crtc,
4472 intel_clock_t *reduced_clock,
4473 int num_connectors)
4474 {
4475 struct drm_device *dev = crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 struct intel_encoder *encoder;
4478 int pipe = crtc->pipe;
4479 u32 dpll;
4480 bool is_sdvo;
4481 struct dpll *clock = &crtc->config.dpll;
4482
4483 i9xx_update_pll_dividers(crtc, reduced_clock);
4484
4485 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4486 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4487
4488 dpll = DPLL_VGA_MODE_DIS;
4489
4490 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4491 dpll |= DPLLB_MODE_LVDS;
4492 else
4493 dpll |= DPLLB_MODE_DAC_SERIAL;
4494
4495 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4496 dpll |= (crtc->config.pixel_multiplier - 1)
4497 << SDVO_MULTIPLIER_SHIFT_HIRES;
4498 }
4499
4500 if (is_sdvo)
4501 dpll |= DPLL_DVO_HIGH_SPEED;
4502
4503 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4504 dpll |= DPLL_DVO_HIGH_SPEED;
4505
4506 /* compute bitmask from p1 value */
4507 if (IS_PINEVIEW(dev))
4508 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4509 else {
4510 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4511 if (IS_G4X(dev) && reduced_clock)
4512 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4513 }
4514 switch (clock->p2) {
4515 case 5:
4516 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4517 break;
4518 case 7:
4519 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4520 break;
4521 case 10:
4522 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4523 break;
4524 case 14:
4525 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4526 break;
4527 }
4528 if (INTEL_INFO(dev)->gen >= 4)
4529 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4530
4531 if (crtc->config.sdvo_tv_clock)
4532 dpll |= PLL_REF_INPUT_TVCLKINBC;
4533 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4534 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4535 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4536 else
4537 dpll |= PLL_REF_INPUT_DREFCLK;
4538
4539 dpll |= DPLL_VCO_ENABLE;
4540 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4541 POSTING_READ(DPLL(pipe));
4542 udelay(150);
4543
4544 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4545 if (encoder->pre_pll_enable)
4546 encoder->pre_pll_enable(encoder);
4547
4548 if (crtc->config.has_dp_encoder)
4549 intel_dp_set_m_n(crtc);
4550
4551 I915_WRITE(DPLL(pipe), dpll);
4552
4553 /* Wait for the clocks to stabilize. */
4554 POSTING_READ(DPLL(pipe));
4555 udelay(150);
4556
4557 if (INTEL_INFO(dev)->gen >= 4) {
4558 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4559 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4560 I915_WRITE(DPLL_MD(pipe), dpll_md);
4561 } else {
4562 /* The pixel multiplier can only be updated once the
4563 * DPLL is enabled and the clocks are stable.
4564 *
4565 * So write it again.
4566 */
4567 I915_WRITE(DPLL(pipe), dpll);
4568 }
4569 }
4570
4571 static void i8xx_update_pll(struct intel_crtc *crtc,
4572 intel_clock_t *reduced_clock,
4573 int num_connectors)
4574 {
4575 struct drm_device *dev = crtc->base.dev;
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct intel_encoder *encoder;
4578 int pipe = crtc->pipe;
4579 u32 dpll;
4580 struct dpll *clock = &crtc->config.dpll;
4581
4582 i9xx_update_pll_dividers(crtc, reduced_clock);
4583
4584 dpll = DPLL_VGA_MODE_DIS;
4585
4586 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4587 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588 } else {
4589 if (clock->p1 == 2)
4590 dpll |= PLL_P1_DIVIDE_BY_TWO;
4591 else
4592 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593 if (clock->p2 == 4)
4594 dpll |= PLL_P2_DIVIDE_BY_4;
4595 }
4596
4597 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4598 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4599 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4600 else
4601 dpll |= PLL_REF_INPUT_DREFCLK;
4602
4603 dpll |= DPLL_VCO_ENABLE;
4604 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4605 POSTING_READ(DPLL(pipe));
4606 udelay(150);
4607
4608 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4609 if (encoder->pre_pll_enable)
4610 encoder->pre_pll_enable(encoder);
4611
4612 I915_WRITE(DPLL(pipe), dpll);
4613
4614 /* Wait for the clocks to stabilize. */
4615 POSTING_READ(DPLL(pipe));
4616 udelay(150);
4617
4618 /* The pixel multiplier can only be updated once the
4619 * DPLL is enabled and the clocks are stable.
4620 *
4621 * So write it again.
4622 */
4623 I915_WRITE(DPLL(pipe), dpll);
4624 }
4625
4626 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4627 {
4628 struct drm_device *dev = intel_crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 enum pipe pipe = intel_crtc->pipe;
4631 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4632 struct drm_display_mode *adjusted_mode =
4633 &intel_crtc->config.adjusted_mode;
4634 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4635 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4636
4637 /* We need to be careful not to changed the adjusted mode, for otherwise
4638 * the hw state checker will get angry at the mismatch. */
4639 crtc_vtotal = adjusted_mode->crtc_vtotal;
4640 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4641
4642 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4643 /* the chip adds 2 halflines automatically */
4644 crtc_vtotal -= 1;
4645 crtc_vblank_end -= 1;
4646 vsyncshift = adjusted_mode->crtc_hsync_start
4647 - adjusted_mode->crtc_htotal / 2;
4648 } else {
4649 vsyncshift = 0;
4650 }
4651
4652 if (INTEL_INFO(dev)->gen > 3)
4653 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4654
4655 I915_WRITE(HTOTAL(cpu_transcoder),
4656 (adjusted_mode->crtc_hdisplay - 1) |
4657 ((adjusted_mode->crtc_htotal - 1) << 16));
4658 I915_WRITE(HBLANK(cpu_transcoder),
4659 (adjusted_mode->crtc_hblank_start - 1) |
4660 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4661 I915_WRITE(HSYNC(cpu_transcoder),
4662 (adjusted_mode->crtc_hsync_start - 1) |
4663 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4664
4665 I915_WRITE(VTOTAL(cpu_transcoder),
4666 (adjusted_mode->crtc_vdisplay - 1) |
4667 ((crtc_vtotal - 1) << 16));
4668 I915_WRITE(VBLANK(cpu_transcoder),
4669 (adjusted_mode->crtc_vblank_start - 1) |
4670 ((crtc_vblank_end - 1) << 16));
4671 I915_WRITE(VSYNC(cpu_transcoder),
4672 (adjusted_mode->crtc_vsync_start - 1) |
4673 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4674
4675 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4676 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4677 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4678 * bits. */
4679 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4680 (pipe == PIPE_B || pipe == PIPE_C))
4681 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4682
4683 /* pipesrc controls the size that is scaled from, which should
4684 * always be the user's requested size.
4685 */
4686 I915_WRITE(PIPESRC(pipe),
4687 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4688 }
4689
4690 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4691 struct intel_crtc_config *pipe_config)
4692 {
4693 struct drm_device *dev = crtc->base.dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4696 uint32_t tmp;
4697
4698 tmp = I915_READ(HTOTAL(cpu_transcoder));
4699 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4700 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4701 tmp = I915_READ(HBLANK(cpu_transcoder));
4702 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4703 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4704 tmp = I915_READ(HSYNC(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4707
4708 tmp = I915_READ(VTOTAL(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4711 tmp = I915_READ(VBLANK(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4714 tmp = I915_READ(VSYNC(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4717
4718 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4719 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4720 pipe_config->adjusted_mode.crtc_vtotal += 1;
4721 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4722 }
4723
4724 tmp = I915_READ(PIPESRC(crtc->pipe));
4725 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4726 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4727 }
4728
4729 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4730 {
4731 struct drm_device *dev = intel_crtc->base.dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 uint32_t pipeconf;
4734
4735 pipeconf = 0;
4736
4737 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4738 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4739 * core speed.
4740 *
4741 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4742 * pipe == 0 check?
4743 */
4744 if (intel_crtc->config.requested_mode.clock >
4745 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4746 pipeconf |= PIPECONF_DOUBLE_WIDE;
4747 }
4748
4749 /* only g4x and later have fancy bpc/dither controls */
4750 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4751 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4752 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4753 pipeconf |= PIPECONF_DITHER_EN |
4754 PIPECONF_DITHER_TYPE_SP;
4755
4756 switch (intel_crtc->config.pipe_bpp) {
4757 case 18:
4758 pipeconf |= PIPECONF_6BPC;
4759 break;
4760 case 24:
4761 pipeconf |= PIPECONF_8BPC;
4762 break;
4763 case 30:
4764 pipeconf |= PIPECONF_10BPC;
4765 break;
4766 default:
4767 /* Case prevented by intel_choose_pipe_bpp_dither. */
4768 BUG();
4769 }
4770 }
4771
4772 if (HAS_PIPE_CXSR(dev)) {
4773 if (intel_crtc->lowfreq_avail) {
4774 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4775 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4776 } else {
4777 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4778 }
4779 }
4780
4781 if (!IS_GEN2(dev) &&
4782 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4783 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4784 else
4785 pipeconf |= PIPECONF_PROGRESSIVE;
4786
4787 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4788 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4789
4790 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4791 POSTING_READ(PIPECONF(intel_crtc->pipe));
4792 }
4793
4794 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4795 int x, int y,
4796 struct drm_framebuffer *fb)
4797 {
4798 struct drm_device *dev = crtc->dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4801 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4802 int pipe = intel_crtc->pipe;
4803 int plane = intel_crtc->plane;
4804 int refclk, num_connectors = 0;
4805 intel_clock_t clock, reduced_clock;
4806 u32 dspcntr;
4807 bool ok, has_reduced_clock = false;
4808 bool is_lvds = false;
4809 struct intel_encoder *encoder;
4810 const intel_limit_t *limit;
4811 int ret;
4812
4813 for_each_encoder_on_crtc(dev, crtc, encoder) {
4814 switch (encoder->type) {
4815 case INTEL_OUTPUT_LVDS:
4816 is_lvds = true;
4817 break;
4818 }
4819
4820 num_connectors++;
4821 }
4822
4823 refclk = i9xx_get_refclk(crtc, num_connectors);
4824
4825 /*
4826 * Returns a set of divisors for the desired target clock with the given
4827 * refclk, or FALSE. The returned values represent the clock equation:
4828 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4829 */
4830 limit = intel_limit(crtc, refclk);
4831 ok = dev_priv->display.find_dpll(limit, crtc,
4832 intel_crtc->config.port_clock,
4833 refclk, NULL, &clock);
4834 if (!ok && !intel_crtc->config.clock_set) {
4835 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4836 return -EINVAL;
4837 }
4838
4839 /* Ensure that the cursor is valid for the new mode before changing... */
4840 intel_crtc_update_cursor(crtc, true);
4841
4842 if (is_lvds && dev_priv->lvds_downclock_avail) {
4843 /*
4844 * Ensure we match the reduced clock's P to the target clock.
4845 * If the clocks don't match, we can't switch the display clock
4846 * by using the FP0/FP1. In such case we will disable the LVDS
4847 * downclock feature.
4848 */
4849 has_reduced_clock =
4850 dev_priv->display.find_dpll(limit, crtc,
4851 dev_priv->lvds_downclock,
4852 refclk, &clock,
4853 &reduced_clock);
4854 }
4855 /* Compat-code for transition, will disappear. */
4856 if (!intel_crtc->config.clock_set) {
4857 intel_crtc->config.dpll.n = clock.n;
4858 intel_crtc->config.dpll.m1 = clock.m1;
4859 intel_crtc->config.dpll.m2 = clock.m2;
4860 intel_crtc->config.dpll.p1 = clock.p1;
4861 intel_crtc->config.dpll.p2 = clock.p2;
4862 }
4863
4864 if (IS_GEN2(dev))
4865 i8xx_update_pll(intel_crtc,
4866 has_reduced_clock ? &reduced_clock : NULL,
4867 num_connectors);
4868 else if (IS_VALLEYVIEW(dev))
4869 vlv_update_pll(intel_crtc);
4870 else
4871 i9xx_update_pll(intel_crtc,
4872 has_reduced_clock ? &reduced_clock : NULL,
4873 num_connectors);
4874
4875 /* Set up the display plane register */
4876 dspcntr = DISPPLANE_GAMMA_ENABLE;
4877
4878 if (!IS_VALLEYVIEW(dev)) {
4879 if (pipe == 0)
4880 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4881 else
4882 dspcntr |= DISPPLANE_SEL_PIPE_B;
4883 }
4884
4885 intel_set_pipe_timings(intel_crtc);
4886
4887 /* pipesrc and dspsize control the size that is scaled from,
4888 * which should always be the user's requested size.
4889 */
4890 I915_WRITE(DSPSIZE(plane),
4891 ((mode->vdisplay - 1) << 16) |
4892 (mode->hdisplay - 1));
4893 I915_WRITE(DSPPOS(plane), 0);
4894
4895 i9xx_set_pipeconf(intel_crtc);
4896
4897 I915_WRITE(DSPCNTR(plane), dspcntr);
4898 POSTING_READ(DSPCNTR(plane));
4899
4900 ret = intel_pipe_set_base(crtc, x, y, fb);
4901
4902 intel_update_watermarks(dev);
4903
4904 return ret;
4905 }
4906
4907 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4908 struct intel_crtc_config *pipe_config)
4909 {
4910 struct drm_device *dev = crtc->base.dev;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 uint32_t tmp;
4913
4914 tmp = I915_READ(PFIT_CONTROL);
4915
4916 if (INTEL_INFO(dev)->gen < 4) {
4917 if (crtc->pipe != PIPE_B)
4918 return;
4919
4920 /* gen2/3 store dither state in pfit control, needs to match */
4921 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4922 } else {
4923 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4924 return;
4925 }
4926
4927 if (!(tmp & PFIT_ENABLE))
4928 return;
4929
4930 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4931 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4932 if (INTEL_INFO(dev)->gen < 5)
4933 pipe_config->gmch_pfit.lvds_border_bits =
4934 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4935 }
4936
4937 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4938 struct intel_crtc_config *pipe_config)
4939 {
4940 struct drm_device *dev = crtc->base.dev;
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942 uint32_t tmp;
4943
4944 pipe_config->cpu_transcoder = crtc->pipe;
4945 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4946
4947 tmp = I915_READ(PIPECONF(crtc->pipe));
4948 if (!(tmp & PIPECONF_ENABLE))
4949 return false;
4950
4951 intel_get_pipe_timings(crtc, pipe_config);
4952
4953 i9xx_get_pfit_config(crtc, pipe_config);
4954
4955 if (INTEL_INFO(dev)->gen >= 4) {
4956 tmp = I915_READ(DPLL_MD(crtc->pipe));
4957 pipe_config->pixel_multiplier =
4958 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4959 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4960 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4961 tmp = I915_READ(DPLL(crtc->pipe));
4962 pipe_config->pixel_multiplier =
4963 ((tmp & SDVO_MULTIPLIER_MASK)
4964 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4965 } else {
4966 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4967 * port and will be fixed up in the encoder->get_config
4968 * function. */
4969 pipe_config->pixel_multiplier = 1;
4970 }
4971
4972 return true;
4973 }
4974
4975 static void ironlake_init_pch_refclk(struct drm_device *dev)
4976 {
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 struct drm_mode_config *mode_config = &dev->mode_config;
4979 struct intel_encoder *encoder;
4980 u32 val, final;
4981 bool has_lvds = false;
4982 bool has_cpu_edp = false;
4983 bool has_panel = false;
4984 bool has_ck505 = false;
4985 bool can_ssc = false;
4986
4987 /* We need to take the global config into account */
4988 list_for_each_entry(encoder, &mode_config->encoder_list,
4989 base.head) {
4990 switch (encoder->type) {
4991 case INTEL_OUTPUT_LVDS:
4992 has_panel = true;
4993 has_lvds = true;
4994 break;
4995 case INTEL_OUTPUT_EDP:
4996 has_panel = true;
4997 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4998 has_cpu_edp = true;
4999 break;
5000 }
5001 }
5002
5003 if (HAS_PCH_IBX(dev)) {
5004 has_ck505 = dev_priv->vbt.display_clock_mode;
5005 can_ssc = has_ck505;
5006 } else {
5007 has_ck505 = false;
5008 can_ssc = true;
5009 }
5010
5011 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5012 has_panel, has_lvds, has_ck505);
5013
5014 /* Ironlake: try to setup display ref clock before DPLL
5015 * enabling. This is only under driver's control after
5016 * PCH B stepping, previous chipset stepping should be
5017 * ignoring this setting.
5018 */
5019 val = I915_READ(PCH_DREF_CONTROL);
5020
5021 /* As we must carefully and slowly disable/enable each source in turn,
5022 * compute the final state we want first and check if we need to
5023 * make any changes at all.
5024 */
5025 final = val;
5026 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5027 if (has_ck505)
5028 final |= DREF_NONSPREAD_CK505_ENABLE;
5029 else
5030 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5031
5032 final &= ~DREF_SSC_SOURCE_MASK;
5033 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5034 final &= ~DREF_SSC1_ENABLE;
5035
5036 if (has_panel) {
5037 final |= DREF_SSC_SOURCE_ENABLE;
5038
5039 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5040 final |= DREF_SSC1_ENABLE;
5041
5042 if (has_cpu_edp) {
5043 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5044 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5045 else
5046 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5047 } else
5048 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5049 } else {
5050 final |= DREF_SSC_SOURCE_DISABLE;
5051 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5052 }
5053
5054 if (final == val)
5055 return;
5056
5057 /* Always enable nonspread source */
5058 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5059
5060 if (has_ck505)
5061 val |= DREF_NONSPREAD_CK505_ENABLE;
5062 else
5063 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5064
5065 if (has_panel) {
5066 val &= ~DREF_SSC_SOURCE_MASK;
5067 val |= DREF_SSC_SOURCE_ENABLE;
5068
5069 /* SSC must be turned on before enabling the CPU output */
5070 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5071 DRM_DEBUG_KMS("Using SSC on panel\n");
5072 val |= DREF_SSC1_ENABLE;
5073 } else
5074 val &= ~DREF_SSC1_ENABLE;
5075
5076 /* Get SSC going before enabling the outputs */
5077 I915_WRITE(PCH_DREF_CONTROL, val);
5078 POSTING_READ(PCH_DREF_CONTROL);
5079 udelay(200);
5080
5081 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5082
5083 /* Enable CPU source on CPU attached eDP */
5084 if (has_cpu_edp) {
5085 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5086 DRM_DEBUG_KMS("Using SSC on eDP\n");
5087 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5088 }
5089 else
5090 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5091 } else
5092 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5093
5094 I915_WRITE(PCH_DREF_CONTROL, val);
5095 POSTING_READ(PCH_DREF_CONTROL);
5096 udelay(200);
5097 } else {
5098 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5099
5100 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5101
5102 /* Turn off CPU output */
5103 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5104
5105 I915_WRITE(PCH_DREF_CONTROL, val);
5106 POSTING_READ(PCH_DREF_CONTROL);
5107 udelay(200);
5108
5109 /* Turn off the SSC source */
5110 val &= ~DREF_SSC_SOURCE_MASK;
5111 val |= DREF_SSC_SOURCE_DISABLE;
5112
5113 /* Turn off SSC1 */
5114 val &= ~DREF_SSC1_ENABLE;
5115
5116 I915_WRITE(PCH_DREF_CONTROL, val);
5117 POSTING_READ(PCH_DREF_CONTROL);
5118 udelay(200);
5119 }
5120
5121 BUG_ON(val != final);
5122 }
5123
5124 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5125 static void lpt_init_pch_refclk(struct drm_device *dev)
5126 {
5127 struct drm_i915_private *dev_priv = dev->dev_private;
5128 struct drm_mode_config *mode_config = &dev->mode_config;
5129 struct intel_encoder *encoder;
5130 bool has_vga = false;
5131 bool is_sdv = false;
5132 u32 tmp;
5133
5134 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5135 switch (encoder->type) {
5136 case INTEL_OUTPUT_ANALOG:
5137 has_vga = true;
5138 break;
5139 }
5140 }
5141
5142 if (!has_vga)
5143 return;
5144
5145 mutex_lock(&dev_priv->dpio_lock);
5146
5147 /* XXX: Rip out SDV support once Haswell ships for real. */
5148 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5149 is_sdv = true;
5150
5151 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5152 tmp &= ~SBI_SSCCTL_DISABLE;
5153 tmp |= SBI_SSCCTL_PATHALT;
5154 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5155
5156 udelay(24);
5157
5158 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5159 tmp &= ~SBI_SSCCTL_PATHALT;
5160 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5161
5162 if (!is_sdv) {
5163 tmp = I915_READ(SOUTH_CHICKEN2);
5164 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5165 I915_WRITE(SOUTH_CHICKEN2, tmp);
5166
5167 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5168 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5169 DRM_ERROR("FDI mPHY reset assert timeout\n");
5170
5171 tmp = I915_READ(SOUTH_CHICKEN2);
5172 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5173 I915_WRITE(SOUTH_CHICKEN2, tmp);
5174
5175 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5176 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5177 100))
5178 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5179 }
5180
5181 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5182 tmp &= ~(0xFF << 24);
5183 tmp |= (0x12 << 24);
5184 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5185
5186 if (is_sdv) {
5187 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5188 tmp |= 0x7FFF;
5189 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5190 }
5191
5192 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5193 tmp |= (1 << 11);
5194 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5195
5196 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5197 tmp |= (1 << 11);
5198 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5199
5200 if (is_sdv) {
5201 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5202 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5203 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5204
5205 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5206 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5207 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5208
5209 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5210 tmp |= (0x3F << 8);
5211 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5214 tmp |= (0x3F << 8);
5215 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5216 }
5217
5218 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5219 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5220 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5221
5222 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5223 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5224 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5225
5226 if (!is_sdv) {
5227 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5228 tmp &= ~(7 << 13);
5229 tmp |= (5 << 13);
5230 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5231
5232 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5233 tmp &= ~(7 << 13);
5234 tmp |= (5 << 13);
5235 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5236 }
5237
5238 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5239 tmp &= ~0xFF;
5240 tmp |= 0x1C;
5241 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5242
5243 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5244 tmp &= ~0xFF;
5245 tmp |= 0x1C;
5246 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5247
5248 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5249 tmp &= ~(0xFF << 16);
5250 tmp |= (0x1C << 16);
5251 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5252
5253 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5254 tmp &= ~(0xFF << 16);
5255 tmp |= (0x1C << 16);
5256 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5257
5258 if (!is_sdv) {
5259 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5260 tmp |= (1 << 27);
5261 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5264 tmp |= (1 << 27);
5265 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5266
5267 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5268 tmp &= ~(0xF << 28);
5269 tmp |= (4 << 28);
5270 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5271
5272 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5273 tmp &= ~(0xF << 28);
5274 tmp |= (4 << 28);
5275 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5276 }
5277
5278 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5279 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5280 tmp |= SBI_DBUFF0_ENABLE;
5281 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5282
5283 mutex_unlock(&dev_priv->dpio_lock);
5284 }
5285
5286 /*
5287 * Initialize reference clocks when the driver loads
5288 */
5289 void intel_init_pch_refclk(struct drm_device *dev)
5290 {
5291 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5292 ironlake_init_pch_refclk(dev);
5293 else if (HAS_PCH_LPT(dev))
5294 lpt_init_pch_refclk(dev);
5295 }
5296
5297 static int ironlake_get_refclk(struct drm_crtc *crtc)
5298 {
5299 struct drm_device *dev = crtc->dev;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 struct intel_encoder *encoder;
5302 int num_connectors = 0;
5303 bool is_lvds = false;
5304
5305 for_each_encoder_on_crtc(dev, crtc, encoder) {
5306 switch (encoder->type) {
5307 case INTEL_OUTPUT_LVDS:
5308 is_lvds = true;
5309 break;
5310 }
5311 num_connectors++;
5312 }
5313
5314 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5315 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5316 dev_priv->vbt.lvds_ssc_freq);
5317 return dev_priv->vbt.lvds_ssc_freq * 1000;
5318 }
5319
5320 return 120000;
5321 }
5322
5323 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5324 {
5325 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5327 int pipe = intel_crtc->pipe;
5328 uint32_t val;
5329
5330 val = 0;
5331
5332 switch (intel_crtc->config.pipe_bpp) {
5333 case 18:
5334 val |= PIPECONF_6BPC;
5335 break;
5336 case 24:
5337 val |= PIPECONF_8BPC;
5338 break;
5339 case 30:
5340 val |= PIPECONF_10BPC;
5341 break;
5342 case 36:
5343 val |= PIPECONF_12BPC;
5344 break;
5345 default:
5346 /* Case prevented by intel_choose_pipe_bpp_dither. */
5347 BUG();
5348 }
5349
5350 if (intel_crtc->config.dither)
5351 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5352
5353 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5354 val |= PIPECONF_INTERLACED_ILK;
5355 else
5356 val |= PIPECONF_PROGRESSIVE;
5357
5358 if (intel_crtc->config.limited_color_range)
5359 val |= PIPECONF_COLOR_RANGE_SELECT;
5360
5361 I915_WRITE(PIPECONF(pipe), val);
5362 POSTING_READ(PIPECONF(pipe));
5363 }
5364
5365 /*
5366 * Set up the pipe CSC unit.
5367 *
5368 * Currently only full range RGB to limited range RGB conversion
5369 * is supported, but eventually this should handle various
5370 * RGB<->YCbCr scenarios as well.
5371 */
5372 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5373 {
5374 struct drm_device *dev = crtc->dev;
5375 struct drm_i915_private *dev_priv = dev->dev_private;
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377 int pipe = intel_crtc->pipe;
5378 uint16_t coeff = 0x7800; /* 1.0 */
5379
5380 /*
5381 * TODO: Check what kind of values actually come out of the pipe
5382 * with these coeff/postoff values and adjust to get the best
5383 * accuracy. Perhaps we even need to take the bpc value into
5384 * consideration.
5385 */
5386
5387 if (intel_crtc->config.limited_color_range)
5388 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5389
5390 /*
5391 * GY/GU and RY/RU should be the other way around according
5392 * to BSpec, but reality doesn't agree. Just set them up in
5393 * a way that results in the correct picture.
5394 */
5395 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5396 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5397
5398 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5399 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5400
5401 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5402 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5403
5404 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5405 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5406 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5407
5408 if (INTEL_INFO(dev)->gen > 6) {
5409 uint16_t postoff = 0;
5410
5411 if (intel_crtc->config.limited_color_range)
5412 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5413
5414 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5415 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5416 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5417
5418 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5419 } else {
5420 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5421
5422 if (intel_crtc->config.limited_color_range)
5423 mode |= CSC_BLACK_SCREEN_OFFSET;
5424
5425 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5426 }
5427 }
5428
5429 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5430 {
5431 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5433 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5434 uint32_t val;
5435
5436 val = 0;
5437
5438 if (intel_crtc->config.dither)
5439 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5440
5441 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5442 val |= PIPECONF_INTERLACED_ILK;
5443 else
5444 val |= PIPECONF_PROGRESSIVE;
5445
5446 I915_WRITE(PIPECONF(cpu_transcoder), val);
5447 POSTING_READ(PIPECONF(cpu_transcoder));
5448
5449 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5450 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5451 }
5452
5453 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5454 intel_clock_t *clock,
5455 bool *has_reduced_clock,
5456 intel_clock_t *reduced_clock)
5457 {
5458 struct drm_device *dev = crtc->dev;
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 struct intel_encoder *intel_encoder;
5461 int refclk;
5462 const intel_limit_t *limit;
5463 bool ret, is_lvds = false;
5464
5465 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5466 switch (intel_encoder->type) {
5467 case INTEL_OUTPUT_LVDS:
5468 is_lvds = true;
5469 break;
5470 }
5471 }
5472
5473 refclk = ironlake_get_refclk(crtc);
5474
5475 /*
5476 * Returns a set of divisors for the desired target clock with the given
5477 * refclk, or FALSE. The returned values represent the clock equation:
5478 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5479 */
5480 limit = intel_limit(crtc, refclk);
5481 ret = dev_priv->display.find_dpll(limit, crtc,
5482 to_intel_crtc(crtc)->config.port_clock,
5483 refclk, NULL, clock);
5484 if (!ret)
5485 return false;
5486
5487 if (is_lvds && dev_priv->lvds_downclock_avail) {
5488 /*
5489 * Ensure we match the reduced clock's P to the target clock.
5490 * If the clocks don't match, we can't switch the display clock
5491 * by using the FP0/FP1. In such case we will disable the LVDS
5492 * downclock feature.
5493 */
5494 *has_reduced_clock =
5495 dev_priv->display.find_dpll(limit, crtc,
5496 dev_priv->lvds_downclock,
5497 refclk, clock,
5498 reduced_clock);
5499 }
5500
5501 return true;
5502 }
5503
5504 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5505 {
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 uint32_t temp;
5508
5509 temp = I915_READ(SOUTH_CHICKEN1);
5510 if (temp & FDI_BC_BIFURCATION_SELECT)
5511 return;
5512
5513 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5514 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5515
5516 temp |= FDI_BC_BIFURCATION_SELECT;
5517 DRM_DEBUG_KMS("enabling fdi C rx\n");
5518 I915_WRITE(SOUTH_CHICKEN1, temp);
5519 POSTING_READ(SOUTH_CHICKEN1);
5520 }
5521
5522 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5523 {
5524 struct drm_device *dev = intel_crtc->base.dev;
5525 struct drm_i915_private *dev_priv = dev->dev_private;
5526
5527 switch (intel_crtc->pipe) {
5528 case PIPE_A:
5529 break;
5530 case PIPE_B:
5531 if (intel_crtc->config.fdi_lanes > 2)
5532 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5533 else
5534 cpt_enable_fdi_bc_bifurcation(dev);
5535
5536 break;
5537 case PIPE_C:
5538 cpt_enable_fdi_bc_bifurcation(dev);
5539
5540 break;
5541 default:
5542 BUG();
5543 }
5544 }
5545
5546 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5547 {
5548 /*
5549 * Account for spread spectrum to avoid
5550 * oversubscribing the link. Max center spread
5551 * is 2.5%; use 5% for safety's sake.
5552 */
5553 u32 bps = target_clock * bpp * 21 / 20;
5554 return bps / (link_bw * 8) + 1;
5555 }
5556
5557 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5558 {
5559 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5560 }
5561
5562 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5563 u32 *fp,
5564 intel_clock_t *reduced_clock, u32 *fp2)
5565 {
5566 struct drm_crtc *crtc = &intel_crtc->base;
5567 struct drm_device *dev = crtc->dev;
5568 struct drm_i915_private *dev_priv = dev->dev_private;
5569 struct intel_encoder *intel_encoder;
5570 uint32_t dpll;
5571 int factor, num_connectors = 0;
5572 bool is_lvds = false, is_sdvo = false;
5573
5574 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5575 switch (intel_encoder->type) {
5576 case INTEL_OUTPUT_LVDS:
5577 is_lvds = true;
5578 break;
5579 case INTEL_OUTPUT_SDVO:
5580 case INTEL_OUTPUT_HDMI:
5581 is_sdvo = true;
5582 break;
5583 }
5584
5585 num_connectors++;
5586 }
5587
5588 /* Enable autotuning of the PLL clock (if permissible) */
5589 factor = 21;
5590 if (is_lvds) {
5591 if ((intel_panel_use_ssc(dev_priv) &&
5592 dev_priv->vbt.lvds_ssc_freq == 100) ||
5593 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5594 factor = 25;
5595 } else if (intel_crtc->config.sdvo_tv_clock)
5596 factor = 20;
5597
5598 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5599 *fp |= FP_CB_TUNE;
5600
5601 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5602 *fp2 |= FP_CB_TUNE;
5603
5604 dpll = 0;
5605
5606 if (is_lvds)
5607 dpll |= DPLLB_MODE_LVDS;
5608 else
5609 dpll |= DPLLB_MODE_DAC_SERIAL;
5610
5611 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5612 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5613
5614 if (is_sdvo)
5615 dpll |= DPLL_DVO_HIGH_SPEED;
5616 if (intel_crtc->config.has_dp_encoder)
5617 dpll |= DPLL_DVO_HIGH_SPEED;
5618
5619 /* compute bitmask from p1 value */
5620 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5621 /* also FPA1 */
5622 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5623
5624 switch (intel_crtc->config.dpll.p2) {
5625 case 5:
5626 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5627 break;
5628 case 7:
5629 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5630 break;
5631 case 10:
5632 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5633 break;
5634 case 14:
5635 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5636 break;
5637 }
5638
5639 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5640 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5641 else
5642 dpll |= PLL_REF_INPUT_DREFCLK;
5643
5644 return dpll | DPLL_VCO_ENABLE;
5645 }
5646
5647 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5648 int x, int y,
5649 struct drm_framebuffer *fb)
5650 {
5651 struct drm_device *dev = crtc->dev;
5652 struct drm_i915_private *dev_priv = dev->dev_private;
5653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5654 int pipe = intel_crtc->pipe;
5655 int plane = intel_crtc->plane;
5656 int num_connectors = 0;
5657 intel_clock_t clock, reduced_clock;
5658 u32 dpll = 0, fp = 0, fp2 = 0;
5659 bool ok, has_reduced_clock = false;
5660 bool is_lvds = false;
5661 struct intel_encoder *encoder;
5662 struct intel_shared_dpll *pll;
5663 int ret;
5664
5665 for_each_encoder_on_crtc(dev, crtc, encoder) {
5666 switch (encoder->type) {
5667 case INTEL_OUTPUT_LVDS:
5668 is_lvds = true;
5669 break;
5670 }
5671
5672 num_connectors++;
5673 }
5674
5675 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5676 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5677
5678 ok = ironlake_compute_clocks(crtc, &clock,
5679 &has_reduced_clock, &reduced_clock);
5680 if (!ok && !intel_crtc->config.clock_set) {
5681 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5682 return -EINVAL;
5683 }
5684 /* Compat-code for transition, will disappear. */
5685 if (!intel_crtc->config.clock_set) {
5686 intel_crtc->config.dpll.n = clock.n;
5687 intel_crtc->config.dpll.m1 = clock.m1;
5688 intel_crtc->config.dpll.m2 = clock.m2;
5689 intel_crtc->config.dpll.p1 = clock.p1;
5690 intel_crtc->config.dpll.p2 = clock.p2;
5691 }
5692
5693 /* Ensure that the cursor is valid for the new mode before changing... */
5694 intel_crtc_update_cursor(crtc, true);
5695
5696 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5697 if (intel_crtc->config.has_pch_encoder) {
5698 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5699 if (has_reduced_clock)
5700 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5701
5702 dpll = ironlake_compute_dpll(intel_crtc,
5703 &fp, &reduced_clock,
5704 has_reduced_clock ? &fp2 : NULL);
5705
5706 intel_crtc->config.dpll_hw_state.dpll = dpll;
5707 intel_crtc->config.dpll_hw_state.fp0 = fp;
5708 if (has_reduced_clock)
5709 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5710 else
5711 intel_crtc->config.dpll_hw_state.fp1 = fp;
5712
5713 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5714 if (pll == NULL) {
5715 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5716 pipe_name(pipe));
5717 return -EINVAL;
5718 }
5719 } else
5720 intel_put_shared_dpll(intel_crtc);
5721
5722 if (intel_crtc->config.has_dp_encoder)
5723 intel_dp_set_m_n(intel_crtc);
5724
5725 for_each_encoder_on_crtc(dev, crtc, encoder)
5726 if (encoder->pre_pll_enable)
5727 encoder->pre_pll_enable(encoder);
5728
5729 if (is_lvds && has_reduced_clock && i915_powersave)
5730 intel_crtc->lowfreq_avail = true;
5731 else
5732 intel_crtc->lowfreq_avail = false;
5733
5734 if (intel_crtc->config.has_pch_encoder) {
5735 pll = intel_crtc_to_shared_dpll(intel_crtc);
5736
5737 I915_WRITE(PCH_DPLL(pll->id), dpll);
5738
5739 /* Wait for the clocks to stabilize. */
5740 POSTING_READ(PCH_DPLL(pll->id));
5741 udelay(150);
5742
5743 /* The pixel multiplier can only be updated once the
5744 * DPLL is enabled and the clocks are stable.
5745 *
5746 * So write it again.
5747 */
5748 I915_WRITE(PCH_DPLL(pll->id), dpll);
5749
5750 if (has_reduced_clock)
5751 I915_WRITE(PCH_FP1(pll->id), fp2);
5752 else
5753 I915_WRITE(PCH_FP1(pll->id), fp);
5754 }
5755
5756 intel_set_pipe_timings(intel_crtc);
5757
5758 if (intel_crtc->config.has_pch_encoder) {
5759 intel_cpu_transcoder_set_m_n(intel_crtc,
5760 &intel_crtc->config.fdi_m_n);
5761 }
5762
5763 if (IS_IVYBRIDGE(dev))
5764 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5765
5766 ironlake_set_pipeconf(crtc);
5767
5768 /* Set up the display plane register */
5769 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5770 POSTING_READ(DSPCNTR(plane));
5771
5772 ret = intel_pipe_set_base(crtc, x, y, fb);
5773
5774 intel_update_watermarks(dev);
5775
5776 return ret;
5777 }
5778
5779 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5780 struct intel_crtc_config *pipe_config)
5781 {
5782 struct drm_device *dev = crtc->base.dev;
5783 struct drm_i915_private *dev_priv = dev->dev_private;
5784 enum transcoder transcoder = pipe_config->cpu_transcoder;
5785
5786 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5787 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5788 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5789 & ~TU_SIZE_MASK;
5790 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5791 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5792 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5793 }
5794
5795 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5796 struct intel_crtc_config *pipe_config)
5797 {
5798 struct drm_device *dev = crtc->base.dev;
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 uint32_t tmp;
5801
5802 tmp = I915_READ(PF_CTL(crtc->pipe));
5803
5804 if (tmp & PF_ENABLE) {
5805 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5806 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5807
5808 /* We currently do not free assignements of panel fitters on
5809 * ivb/hsw (since we don't use the higher upscaling modes which
5810 * differentiates them) so just WARN about this case for now. */
5811 if (IS_GEN7(dev)) {
5812 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5813 PF_PIPE_SEL_IVB(crtc->pipe));
5814 }
5815 }
5816 }
5817
5818 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5819 struct intel_crtc_config *pipe_config)
5820 {
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 uint32_t tmp;
5824
5825 pipe_config->cpu_transcoder = crtc->pipe;
5826 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5827
5828 tmp = I915_READ(PIPECONF(crtc->pipe));
5829 if (!(tmp & PIPECONF_ENABLE))
5830 return false;
5831
5832 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5833 struct intel_shared_dpll *pll;
5834
5835 pipe_config->has_pch_encoder = true;
5836
5837 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5838 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5839 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5840
5841 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5842
5843 /* XXX: Can't properly read out the pch dpll pixel multiplier
5844 * since we don't have state tracking for pch clocks yet. */
5845 pipe_config->pixel_multiplier = 1;
5846
5847 if (HAS_PCH_IBX(dev_priv->dev)) {
5848 pipe_config->shared_dpll = crtc->pipe;
5849 } else {
5850 tmp = I915_READ(PCH_DPLL_SEL);
5851 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5852 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5853 else
5854 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5855 }
5856
5857 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5858
5859 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5860 &pipe_config->dpll_hw_state));
5861 } else {
5862 pipe_config->pixel_multiplier = 1;
5863 }
5864
5865 intel_get_pipe_timings(crtc, pipe_config);
5866
5867 ironlake_get_pfit_config(crtc, pipe_config);
5868
5869 return true;
5870 }
5871
5872 static void haswell_modeset_global_resources(struct drm_device *dev)
5873 {
5874 bool enable = false;
5875 struct intel_crtc *crtc;
5876
5877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5878 if (!crtc->base.enabled)
5879 continue;
5880
5881 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5882 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5883 enable = true;
5884 }
5885
5886 intel_set_power_well(dev, enable);
5887 }
5888
5889 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5890 int x, int y,
5891 struct drm_framebuffer *fb)
5892 {
5893 struct drm_device *dev = crtc->dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5896 int plane = intel_crtc->plane;
5897 int ret;
5898
5899 if (!intel_ddi_pll_mode_set(crtc))
5900 return -EINVAL;
5901
5902 /* Ensure that the cursor is valid for the new mode before changing... */
5903 intel_crtc_update_cursor(crtc, true);
5904
5905 if (intel_crtc->config.has_dp_encoder)
5906 intel_dp_set_m_n(intel_crtc);
5907
5908 intel_crtc->lowfreq_avail = false;
5909
5910 intel_set_pipe_timings(intel_crtc);
5911
5912 if (intel_crtc->config.has_pch_encoder) {
5913 intel_cpu_transcoder_set_m_n(intel_crtc,
5914 &intel_crtc->config.fdi_m_n);
5915 }
5916
5917 haswell_set_pipeconf(crtc);
5918
5919 intel_set_pipe_csc(crtc);
5920
5921 /* Set up the display plane register */
5922 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5923 POSTING_READ(DSPCNTR(plane));
5924
5925 ret = intel_pipe_set_base(crtc, x, y, fb);
5926
5927 intel_update_watermarks(dev);
5928
5929 return ret;
5930 }
5931
5932 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5933 struct intel_crtc_config *pipe_config)
5934 {
5935 struct drm_device *dev = crtc->base.dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 enum intel_display_power_domain pfit_domain;
5938 uint32_t tmp;
5939
5940 pipe_config->cpu_transcoder = crtc->pipe;
5941 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5942
5943 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5944 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5945 enum pipe trans_edp_pipe;
5946 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5947 default:
5948 WARN(1, "unknown pipe linked to edp transcoder\n");
5949 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5950 case TRANS_DDI_EDP_INPUT_A_ON:
5951 trans_edp_pipe = PIPE_A;
5952 break;
5953 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5954 trans_edp_pipe = PIPE_B;
5955 break;
5956 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5957 trans_edp_pipe = PIPE_C;
5958 break;
5959 }
5960
5961 if (trans_edp_pipe == crtc->pipe)
5962 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5963 }
5964
5965 if (!intel_display_power_enabled(dev,
5966 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5967 return false;
5968
5969 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5970 if (!(tmp & PIPECONF_ENABLE))
5971 return false;
5972
5973 /*
5974 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5975 * DDI E. So just check whether this pipe is wired to DDI E and whether
5976 * the PCH transcoder is on.
5977 */
5978 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5979 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5980 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5981 pipe_config->has_pch_encoder = true;
5982
5983 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5984 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5985 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5986
5987 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5988 }
5989
5990 intel_get_pipe_timings(crtc, pipe_config);
5991
5992 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5993 if (intel_display_power_enabled(dev, pfit_domain))
5994 ironlake_get_pfit_config(crtc, pipe_config);
5995
5996 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5997 (I915_READ(IPS_CTL) & IPS_ENABLE);
5998
5999 pipe_config->pixel_multiplier = 1;
6000
6001 return true;
6002 }
6003
6004 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6005 int x, int y,
6006 struct drm_framebuffer *fb)
6007 {
6008 struct drm_device *dev = crtc->dev;
6009 struct drm_i915_private *dev_priv = dev->dev_private;
6010 struct drm_encoder_helper_funcs *encoder_funcs;
6011 struct intel_encoder *encoder;
6012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6013 struct drm_display_mode *adjusted_mode =
6014 &intel_crtc->config.adjusted_mode;
6015 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6016 int pipe = intel_crtc->pipe;
6017 int ret;
6018
6019 drm_vblank_pre_modeset(dev, pipe);
6020
6021 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6022
6023 drm_vblank_post_modeset(dev, pipe);
6024
6025 if (ret != 0)
6026 return ret;
6027
6028 for_each_encoder_on_crtc(dev, crtc, encoder) {
6029 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6030 encoder->base.base.id,
6031 drm_get_encoder_name(&encoder->base),
6032 mode->base.id, mode->name);
6033 if (encoder->mode_set) {
6034 encoder->mode_set(encoder);
6035 } else {
6036 encoder_funcs = encoder->base.helper_private;
6037 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6038 }
6039 }
6040
6041 return 0;
6042 }
6043
6044 static bool intel_eld_uptodate(struct drm_connector *connector,
6045 int reg_eldv, uint32_t bits_eldv,
6046 int reg_elda, uint32_t bits_elda,
6047 int reg_edid)
6048 {
6049 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6050 uint8_t *eld = connector->eld;
6051 uint32_t i;
6052
6053 i = I915_READ(reg_eldv);
6054 i &= bits_eldv;
6055
6056 if (!eld[0])
6057 return !i;
6058
6059 if (!i)
6060 return false;
6061
6062 i = I915_READ(reg_elda);
6063 i &= ~bits_elda;
6064 I915_WRITE(reg_elda, i);
6065
6066 for (i = 0; i < eld[2]; i++)
6067 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6068 return false;
6069
6070 return true;
6071 }
6072
6073 static void g4x_write_eld(struct drm_connector *connector,
6074 struct drm_crtc *crtc)
6075 {
6076 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6077 uint8_t *eld = connector->eld;
6078 uint32_t eldv;
6079 uint32_t len;
6080 uint32_t i;
6081
6082 i = I915_READ(G4X_AUD_VID_DID);
6083
6084 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6085 eldv = G4X_ELDV_DEVCL_DEVBLC;
6086 else
6087 eldv = G4X_ELDV_DEVCTG;
6088
6089 if (intel_eld_uptodate(connector,
6090 G4X_AUD_CNTL_ST, eldv,
6091 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6092 G4X_HDMIW_HDMIEDID))
6093 return;
6094
6095 i = I915_READ(G4X_AUD_CNTL_ST);
6096 i &= ~(eldv | G4X_ELD_ADDR);
6097 len = (i >> 9) & 0x1f; /* ELD buffer size */
6098 I915_WRITE(G4X_AUD_CNTL_ST, i);
6099
6100 if (!eld[0])
6101 return;
6102
6103 len = min_t(uint8_t, eld[2], len);
6104 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6105 for (i = 0; i < len; i++)
6106 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6107
6108 i = I915_READ(G4X_AUD_CNTL_ST);
6109 i |= eldv;
6110 I915_WRITE(G4X_AUD_CNTL_ST, i);
6111 }
6112
6113 static void haswell_write_eld(struct drm_connector *connector,
6114 struct drm_crtc *crtc)
6115 {
6116 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6117 uint8_t *eld = connector->eld;
6118 struct drm_device *dev = crtc->dev;
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 uint32_t eldv;
6121 uint32_t i;
6122 int len;
6123 int pipe = to_intel_crtc(crtc)->pipe;
6124 int tmp;
6125
6126 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6127 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6128 int aud_config = HSW_AUD_CFG(pipe);
6129 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6130
6131
6132 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6133
6134 /* Audio output enable */
6135 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6136 tmp = I915_READ(aud_cntrl_st2);
6137 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6138 I915_WRITE(aud_cntrl_st2, tmp);
6139
6140 /* Wait for 1 vertical blank */
6141 intel_wait_for_vblank(dev, pipe);
6142
6143 /* Set ELD valid state */
6144 tmp = I915_READ(aud_cntrl_st2);
6145 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6146 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6147 I915_WRITE(aud_cntrl_st2, tmp);
6148 tmp = I915_READ(aud_cntrl_st2);
6149 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6150
6151 /* Enable HDMI mode */
6152 tmp = I915_READ(aud_config);
6153 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6154 /* clear N_programing_enable and N_value_index */
6155 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6156 I915_WRITE(aud_config, tmp);
6157
6158 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6159
6160 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6161 intel_crtc->eld_vld = true;
6162
6163 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6164 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6165 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6166 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6167 } else
6168 I915_WRITE(aud_config, 0);
6169
6170 if (intel_eld_uptodate(connector,
6171 aud_cntrl_st2, eldv,
6172 aud_cntl_st, IBX_ELD_ADDRESS,
6173 hdmiw_hdmiedid))
6174 return;
6175
6176 i = I915_READ(aud_cntrl_st2);
6177 i &= ~eldv;
6178 I915_WRITE(aud_cntrl_st2, i);
6179
6180 if (!eld[0])
6181 return;
6182
6183 i = I915_READ(aud_cntl_st);
6184 i &= ~IBX_ELD_ADDRESS;
6185 I915_WRITE(aud_cntl_st, i);
6186 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6187 DRM_DEBUG_DRIVER("port num:%d\n", i);
6188
6189 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6190 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6191 for (i = 0; i < len; i++)
6192 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6193
6194 i = I915_READ(aud_cntrl_st2);
6195 i |= eldv;
6196 I915_WRITE(aud_cntrl_st2, i);
6197
6198 }
6199
6200 static void ironlake_write_eld(struct drm_connector *connector,
6201 struct drm_crtc *crtc)
6202 {
6203 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6204 uint8_t *eld = connector->eld;
6205 uint32_t eldv;
6206 uint32_t i;
6207 int len;
6208 int hdmiw_hdmiedid;
6209 int aud_config;
6210 int aud_cntl_st;
6211 int aud_cntrl_st2;
6212 int pipe = to_intel_crtc(crtc)->pipe;
6213
6214 if (HAS_PCH_IBX(connector->dev)) {
6215 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6216 aud_config = IBX_AUD_CFG(pipe);
6217 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6218 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6219 } else {
6220 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6221 aud_config = CPT_AUD_CFG(pipe);
6222 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6223 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6224 }
6225
6226 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6227
6228 i = I915_READ(aud_cntl_st);
6229 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6230 if (!i) {
6231 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6232 /* operate blindly on all ports */
6233 eldv = IBX_ELD_VALIDB;
6234 eldv |= IBX_ELD_VALIDB << 4;
6235 eldv |= IBX_ELD_VALIDB << 8;
6236 } else {
6237 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6238 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6239 }
6240
6241 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6242 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6243 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6244 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6245 } else
6246 I915_WRITE(aud_config, 0);
6247
6248 if (intel_eld_uptodate(connector,
6249 aud_cntrl_st2, eldv,
6250 aud_cntl_st, IBX_ELD_ADDRESS,
6251 hdmiw_hdmiedid))
6252 return;
6253
6254 i = I915_READ(aud_cntrl_st2);
6255 i &= ~eldv;
6256 I915_WRITE(aud_cntrl_st2, i);
6257
6258 if (!eld[0])
6259 return;
6260
6261 i = I915_READ(aud_cntl_st);
6262 i &= ~IBX_ELD_ADDRESS;
6263 I915_WRITE(aud_cntl_st, i);
6264
6265 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6266 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6267 for (i = 0; i < len; i++)
6268 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6269
6270 i = I915_READ(aud_cntrl_st2);
6271 i |= eldv;
6272 I915_WRITE(aud_cntrl_st2, i);
6273 }
6274
6275 void intel_write_eld(struct drm_encoder *encoder,
6276 struct drm_display_mode *mode)
6277 {
6278 struct drm_crtc *crtc = encoder->crtc;
6279 struct drm_connector *connector;
6280 struct drm_device *dev = encoder->dev;
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6282
6283 connector = drm_select_eld(encoder, mode);
6284 if (!connector)
6285 return;
6286
6287 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6288 connector->base.id,
6289 drm_get_connector_name(connector),
6290 connector->encoder->base.id,
6291 drm_get_encoder_name(connector->encoder));
6292
6293 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6294
6295 if (dev_priv->display.write_eld)
6296 dev_priv->display.write_eld(connector, crtc);
6297 }
6298
6299 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6300 void intel_crtc_load_lut(struct drm_crtc *crtc)
6301 {
6302 struct drm_device *dev = crtc->dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6305 enum pipe pipe = intel_crtc->pipe;
6306 int palreg = PALETTE(pipe);
6307 int i;
6308 bool reenable_ips = false;
6309
6310 /* The clocks have to be on to load the palette. */
6311 if (!crtc->enabled || !intel_crtc->active)
6312 return;
6313
6314 if (!HAS_PCH_SPLIT(dev_priv->dev))
6315 assert_pll_enabled(dev_priv, pipe);
6316
6317 /* use legacy palette for Ironlake */
6318 if (HAS_PCH_SPLIT(dev))
6319 palreg = LGC_PALETTE(pipe);
6320
6321 /* Workaround : Do not read or write the pipe palette/gamma data while
6322 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6323 */
6324 if (intel_crtc->config.ips_enabled &&
6325 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6326 GAMMA_MODE_MODE_SPLIT)) {
6327 hsw_disable_ips(intel_crtc);
6328 reenable_ips = true;
6329 }
6330
6331 for (i = 0; i < 256; i++) {
6332 I915_WRITE(palreg + 4 * i,
6333 (intel_crtc->lut_r[i] << 16) |
6334 (intel_crtc->lut_g[i] << 8) |
6335 intel_crtc->lut_b[i]);
6336 }
6337
6338 if (reenable_ips)
6339 hsw_enable_ips(intel_crtc);
6340 }
6341
6342 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6343 {
6344 struct drm_device *dev = crtc->dev;
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 bool visible = base != 0;
6348 u32 cntl;
6349
6350 if (intel_crtc->cursor_visible == visible)
6351 return;
6352
6353 cntl = I915_READ(_CURACNTR);
6354 if (visible) {
6355 /* On these chipsets we can only modify the base whilst
6356 * the cursor is disabled.
6357 */
6358 I915_WRITE(_CURABASE, base);
6359
6360 cntl &= ~(CURSOR_FORMAT_MASK);
6361 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6362 cntl |= CURSOR_ENABLE |
6363 CURSOR_GAMMA_ENABLE |
6364 CURSOR_FORMAT_ARGB;
6365 } else
6366 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6367 I915_WRITE(_CURACNTR, cntl);
6368
6369 intel_crtc->cursor_visible = visible;
6370 }
6371
6372 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6373 {
6374 struct drm_device *dev = crtc->dev;
6375 struct drm_i915_private *dev_priv = dev->dev_private;
6376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377 int pipe = intel_crtc->pipe;
6378 bool visible = base != 0;
6379
6380 if (intel_crtc->cursor_visible != visible) {
6381 uint32_t cntl = I915_READ(CURCNTR(pipe));
6382 if (base) {
6383 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6384 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6385 cntl |= pipe << 28; /* Connect to correct pipe */
6386 } else {
6387 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6388 cntl |= CURSOR_MODE_DISABLE;
6389 }
6390 I915_WRITE(CURCNTR(pipe), cntl);
6391
6392 intel_crtc->cursor_visible = visible;
6393 }
6394 /* and commit changes on next vblank */
6395 I915_WRITE(CURBASE(pipe), base);
6396 }
6397
6398 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6399 {
6400 struct drm_device *dev = crtc->dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6403 int pipe = intel_crtc->pipe;
6404 bool visible = base != 0;
6405
6406 if (intel_crtc->cursor_visible != visible) {
6407 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6408 if (base) {
6409 cntl &= ~CURSOR_MODE;
6410 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6411 } else {
6412 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6413 cntl |= CURSOR_MODE_DISABLE;
6414 }
6415 if (IS_HASWELL(dev))
6416 cntl |= CURSOR_PIPE_CSC_ENABLE;
6417 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6418
6419 intel_crtc->cursor_visible = visible;
6420 }
6421 /* and commit changes on next vblank */
6422 I915_WRITE(CURBASE_IVB(pipe), base);
6423 }
6424
6425 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6426 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6427 bool on)
6428 {
6429 struct drm_device *dev = crtc->dev;
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432 int pipe = intel_crtc->pipe;
6433 int x = intel_crtc->cursor_x;
6434 int y = intel_crtc->cursor_y;
6435 u32 base, pos;
6436 bool visible;
6437
6438 pos = 0;
6439
6440 if (on && crtc->enabled && crtc->fb) {
6441 base = intel_crtc->cursor_addr;
6442 if (x > (int) crtc->fb->width)
6443 base = 0;
6444
6445 if (y > (int) crtc->fb->height)
6446 base = 0;
6447 } else
6448 base = 0;
6449
6450 if (x < 0) {
6451 if (x + intel_crtc->cursor_width < 0)
6452 base = 0;
6453
6454 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6455 x = -x;
6456 }
6457 pos |= x << CURSOR_X_SHIFT;
6458
6459 if (y < 0) {
6460 if (y + intel_crtc->cursor_height < 0)
6461 base = 0;
6462
6463 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6464 y = -y;
6465 }
6466 pos |= y << CURSOR_Y_SHIFT;
6467
6468 visible = base != 0;
6469 if (!visible && !intel_crtc->cursor_visible)
6470 return;
6471
6472 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6473 I915_WRITE(CURPOS_IVB(pipe), pos);
6474 ivb_update_cursor(crtc, base);
6475 } else {
6476 I915_WRITE(CURPOS(pipe), pos);
6477 if (IS_845G(dev) || IS_I865G(dev))
6478 i845_update_cursor(crtc, base);
6479 else
6480 i9xx_update_cursor(crtc, base);
6481 }
6482 }
6483
6484 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6485 struct drm_file *file,
6486 uint32_t handle,
6487 uint32_t width, uint32_t height)
6488 {
6489 struct drm_device *dev = crtc->dev;
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492 struct drm_i915_gem_object *obj;
6493 uint32_t addr;
6494 int ret;
6495
6496 /* if we want to turn off the cursor ignore width and height */
6497 if (!handle) {
6498 DRM_DEBUG_KMS("cursor off\n");
6499 addr = 0;
6500 obj = NULL;
6501 mutex_lock(&dev->struct_mutex);
6502 goto finish;
6503 }
6504
6505 /* Currently we only support 64x64 cursors */
6506 if (width != 64 || height != 64) {
6507 DRM_ERROR("we currently only support 64x64 cursors\n");
6508 return -EINVAL;
6509 }
6510
6511 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6512 if (&obj->base == NULL)
6513 return -ENOENT;
6514
6515 if (obj->base.size < width * height * 4) {
6516 DRM_ERROR("buffer is to small\n");
6517 ret = -ENOMEM;
6518 goto fail;
6519 }
6520
6521 /* we only need to pin inside GTT if cursor is non-phy */
6522 mutex_lock(&dev->struct_mutex);
6523 if (!dev_priv->info->cursor_needs_physical) {
6524 unsigned alignment;
6525
6526 if (obj->tiling_mode) {
6527 DRM_ERROR("cursor cannot be tiled\n");
6528 ret = -EINVAL;
6529 goto fail_locked;
6530 }
6531
6532 /* Note that the w/a also requires 2 PTE of padding following
6533 * the bo. We currently fill all unused PTE with the shadow
6534 * page and so we should always have valid PTE following the
6535 * cursor preventing the VT-d warning.
6536 */
6537 alignment = 0;
6538 if (need_vtd_wa(dev))
6539 alignment = 64*1024;
6540
6541 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6542 if (ret) {
6543 DRM_ERROR("failed to move cursor bo into the GTT\n");
6544 goto fail_locked;
6545 }
6546
6547 ret = i915_gem_object_put_fence(obj);
6548 if (ret) {
6549 DRM_ERROR("failed to release fence for cursor");
6550 goto fail_unpin;
6551 }
6552
6553 addr = obj->gtt_offset;
6554 } else {
6555 int align = IS_I830(dev) ? 16 * 1024 : 256;
6556 ret = i915_gem_attach_phys_object(dev, obj,
6557 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6558 align);
6559 if (ret) {
6560 DRM_ERROR("failed to attach phys object\n");
6561 goto fail_locked;
6562 }
6563 addr = obj->phys_obj->handle->busaddr;
6564 }
6565
6566 if (IS_GEN2(dev))
6567 I915_WRITE(CURSIZE, (height << 12) | width);
6568
6569 finish:
6570 if (intel_crtc->cursor_bo) {
6571 if (dev_priv->info->cursor_needs_physical) {
6572 if (intel_crtc->cursor_bo != obj)
6573 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6574 } else
6575 i915_gem_object_unpin(intel_crtc->cursor_bo);
6576 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6577 }
6578
6579 mutex_unlock(&dev->struct_mutex);
6580
6581 intel_crtc->cursor_addr = addr;
6582 intel_crtc->cursor_bo = obj;
6583 intel_crtc->cursor_width = width;
6584 intel_crtc->cursor_height = height;
6585
6586 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6587
6588 return 0;
6589 fail_unpin:
6590 i915_gem_object_unpin(obj);
6591 fail_locked:
6592 mutex_unlock(&dev->struct_mutex);
6593 fail:
6594 drm_gem_object_unreference_unlocked(&obj->base);
6595 return ret;
6596 }
6597
6598 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6599 {
6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601
6602 intel_crtc->cursor_x = x;
6603 intel_crtc->cursor_y = y;
6604
6605 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6606
6607 return 0;
6608 }
6609
6610 /** Sets the color ramps on behalf of RandR */
6611 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6612 u16 blue, int regno)
6613 {
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615
6616 intel_crtc->lut_r[regno] = red >> 8;
6617 intel_crtc->lut_g[regno] = green >> 8;
6618 intel_crtc->lut_b[regno] = blue >> 8;
6619 }
6620
6621 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6622 u16 *blue, int regno)
6623 {
6624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6625
6626 *red = intel_crtc->lut_r[regno] << 8;
6627 *green = intel_crtc->lut_g[regno] << 8;
6628 *blue = intel_crtc->lut_b[regno] << 8;
6629 }
6630
6631 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6632 u16 *blue, uint32_t start, uint32_t size)
6633 {
6634 int end = (start + size > 256) ? 256 : start + size, i;
6635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6636
6637 for (i = start; i < end; i++) {
6638 intel_crtc->lut_r[i] = red[i] >> 8;
6639 intel_crtc->lut_g[i] = green[i] >> 8;
6640 intel_crtc->lut_b[i] = blue[i] >> 8;
6641 }
6642
6643 intel_crtc_load_lut(crtc);
6644 }
6645
6646 /* VESA 640x480x72Hz mode to set on the pipe */
6647 static struct drm_display_mode load_detect_mode = {
6648 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6649 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6650 };
6651
6652 static struct drm_framebuffer *
6653 intel_framebuffer_create(struct drm_device *dev,
6654 struct drm_mode_fb_cmd2 *mode_cmd,
6655 struct drm_i915_gem_object *obj)
6656 {
6657 struct intel_framebuffer *intel_fb;
6658 int ret;
6659
6660 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6661 if (!intel_fb) {
6662 drm_gem_object_unreference_unlocked(&obj->base);
6663 return ERR_PTR(-ENOMEM);
6664 }
6665
6666 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6667 if (ret) {
6668 drm_gem_object_unreference_unlocked(&obj->base);
6669 kfree(intel_fb);
6670 return ERR_PTR(ret);
6671 }
6672
6673 return &intel_fb->base;
6674 }
6675
6676 static u32
6677 intel_framebuffer_pitch_for_width(int width, int bpp)
6678 {
6679 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6680 return ALIGN(pitch, 64);
6681 }
6682
6683 static u32
6684 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6685 {
6686 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6687 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6688 }
6689
6690 static struct drm_framebuffer *
6691 intel_framebuffer_create_for_mode(struct drm_device *dev,
6692 struct drm_display_mode *mode,
6693 int depth, int bpp)
6694 {
6695 struct drm_i915_gem_object *obj;
6696 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6697
6698 obj = i915_gem_alloc_object(dev,
6699 intel_framebuffer_size_for_mode(mode, bpp));
6700 if (obj == NULL)
6701 return ERR_PTR(-ENOMEM);
6702
6703 mode_cmd.width = mode->hdisplay;
6704 mode_cmd.height = mode->vdisplay;
6705 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6706 bpp);
6707 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6708
6709 return intel_framebuffer_create(dev, &mode_cmd, obj);
6710 }
6711
6712 static struct drm_framebuffer *
6713 mode_fits_in_fbdev(struct drm_device *dev,
6714 struct drm_display_mode *mode)
6715 {
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717 struct drm_i915_gem_object *obj;
6718 struct drm_framebuffer *fb;
6719
6720 if (dev_priv->fbdev == NULL)
6721 return NULL;
6722
6723 obj = dev_priv->fbdev->ifb.obj;
6724 if (obj == NULL)
6725 return NULL;
6726
6727 fb = &dev_priv->fbdev->ifb.base;
6728 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6729 fb->bits_per_pixel))
6730 return NULL;
6731
6732 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6733 return NULL;
6734
6735 return fb;
6736 }
6737
6738 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6739 struct drm_display_mode *mode,
6740 struct intel_load_detect_pipe *old)
6741 {
6742 struct intel_crtc *intel_crtc;
6743 struct intel_encoder *intel_encoder =
6744 intel_attached_encoder(connector);
6745 struct drm_crtc *possible_crtc;
6746 struct drm_encoder *encoder = &intel_encoder->base;
6747 struct drm_crtc *crtc = NULL;
6748 struct drm_device *dev = encoder->dev;
6749 struct drm_framebuffer *fb;
6750 int i = -1;
6751
6752 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6753 connector->base.id, drm_get_connector_name(connector),
6754 encoder->base.id, drm_get_encoder_name(encoder));
6755
6756 /*
6757 * Algorithm gets a little messy:
6758 *
6759 * - if the connector already has an assigned crtc, use it (but make
6760 * sure it's on first)
6761 *
6762 * - try to find the first unused crtc that can drive this connector,
6763 * and use that if we find one
6764 */
6765
6766 /* See if we already have a CRTC for this connector */
6767 if (encoder->crtc) {
6768 crtc = encoder->crtc;
6769
6770 mutex_lock(&crtc->mutex);
6771
6772 old->dpms_mode = connector->dpms;
6773 old->load_detect_temp = false;
6774
6775 /* Make sure the crtc and connector are running */
6776 if (connector->dpms != DRM_MODE_DPMS_ON)
6777 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6778
6779 return true;
6780 }
6781
6782 /* Find an unused one (if possible) */
6783 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6784 i++;
6785 if (!(encoder->possible_crtcs & (1 << i)))
6786 continue;
6787 if (!possible_crtc->enabled) {
6788 crtc = possible_crtc;
6789 break;
6790 }
6791 }
6792
6793 /*
6794 * If we didn't find an unused CRTC, don't use any.
6795 */
6796 if (!crtc) {
6797 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6798 return false;
6799 }
6800
6801 mutex_lock(&crtc->mutex);
6802 intel_encoder->new_crtc = to_intel_crtc(crtc);
6803 to_intel_connector(connector)->new_encoder = intel_encoder;
6804
6805 intel_crtc = to_intel_crtc(crtc);
6806 old->dpms_mode = connector->dpms;
6807 old->load_detect_temp = true;
6808 old->release_fb = NULL;
6809
6810 if (!mode)
6811 mode = &load_detect_mode;
6812
6813 /* We need a framebuffer large enough to accommodate all accesses
6814 * that the plane may generate whilst we perform load detection.
6815 * We can not rely on the fbcon either being present (we get called
6816 * during its initialisation to detect all boot displays, or it may
6817 * not even exist) or that it is large enough to satisfy the
6818 * requested mode.
6819 */
6820 fb = mode_fits_in_fbdev(dev, mode);
6821 if (fb == NULL) {
6822 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6823 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6824 old->release_fb = fb;
6825 } else
6826 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6827 if (IS_ERR(fb)) {
6828 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6829 mutex_unlock(&crtc->mutex);
6830 return false;
6831 }
6832
6833 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6834 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6835 if (old->release_fb)
6836 old->release_fb->funcs->destroy(old->release_fb);
6837 mutex_unlock(&crtc->mutex);
6838 return false;
6839 }
6840
6841 /* let the connector get through one full cycle before testing */
6842 intel_wait_for_vblank(dev, intel_crtc->pipe);
6843 return true;
6844 }
6845
6846 void intel_release_load_detect_pipe(struct drm_connector *connector,
6847 struct intel_load_detect_pipe *old)
6848 {
6849 struct intel_encoder *intel_encoder =
6850 intel_attached_encoder(connector);
6851 struct drm_encoder *encoder = &intel_encoder->base;
6852 struct drm_crtc *crtc = encoder->crtc;
6853
6854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6855 connector->base.id, drm_get_connector_name(connector),
6856 encoder->base.id, drm_get_encoder_name(encoder));
6857
6858 if (old->load_detect_temp) {
6859 to_intel_connector(connector)->new_encoder = NULL;
6860 intel_encoder->new_crtc = NULL;
6861 intel_set_mode(crtc, NULL, 0, 0, NULL);
6862
6863 if (old->release_fb) {
6864 drm_framebuffer_unregister_private(old->release_fb);
6865 drm_framebuffer_unreference(old->release_fb);
6866 }
6867
6868 mutex_unlock(&crtc->mutex);
6869 return;
6870 }
6871
6872 /* Switch crtc and encoder back off if necessary */
6873 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6874 connector->funcs->dpms(connector, old->dpms_mode);
6875
6876 mutex_unlock(&crtc->mutex);
6877 }
6878
6879 /* Returns the clock of the currently programmed mode of the given pipe. */
6880 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6881 {
6882 struct drm_i915_private *dev_priv = dev->dev_private;
6883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6884 int pipe = intel_crtc->pipe;
6885 u32 dpll = I915_READ(DPLL(pipe));
6886 u32 fp;
6887 intel_clock_t clock;
6888
6889 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6890 fp = I915_READ(FP0(pipe));
6891 else
6892 fp = I915_READ(FP1(pipe));
6893
6894 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6895 if (IS_PINEVIEW(dev)) {
6896 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6897 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6898 } else {
6899 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6900 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6901 }
6902
6903 if (!IS_GEN2(dev)) {
6904 if (IS_PINEVIEW(dev))
6905 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6906 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6907 else
6908 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6909 DPLL_FPA01_P1_POST_DIV_SHIFT);
6910
6911 switch (dpll & DPLL_MODE_MASK) {
6912 case DPLLB_MODE_DAC_SERIAL:
6913 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6914 5 : 10;
6915 break;
6916 case DPLLB_MODE_LVDS:
6917 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6918 7 : 14;
6919 break;
6920 default:
6921 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6922 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6923 return 0;
6924 }
6925
6926 if (IS_PINEVIEW(dev))
6927 pineview_clock(96000, &clock);
6928 else
6929 i9xx_clock(96000, &clock);
6930 } else {
6931 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6932
6933 if (is_lvds) {
6934 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6935 DPLL_FPA01_P1_POST_DIV_SHIFT);
6936 clock.p2 = 14;
6937
6938 if ((dpll & PLL_REF_INPUT_MASK) ==
6939 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6940 /* XXX: might not be 66MHz */
6941 i9xx_clock(66000, &clock);
6942 } else
6943 i9xx_clock(48000, &clock);
6944 } else {
6945 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6946 clock.p1 = 2;
6947 else {
6948 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6949 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6950 }
6951 if (dpll & PLL_P2_DIVIDE_BY_4)
6952 clock.p2 = 4;
6953 else
6954 clock.p2 = 2;
6955
6956 i9xx_clock(48000, &clock);
6957 }
6958 }
6959
6960 /* XXX: It would be nice to validate the clocks, but we can't reuse
6961 * i830PllIsValid() because it relies on the xf86_config connector
6962 * configuration being accurate, which it isn't necessarily.
6963 */
6964
6965 return clock.dot;
6966 }
6967
6968 /** Returns the currently programmed mode of the given pipe. */
6969 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6970 struct drm_crtc *crtc)
6971 {
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6974 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6975 struct drm_display_mode *mode;
6976 int htot = I915_READ(HTOTAL(cpu_transcoder));
6977 int hsync = I915_READ(HSYNC(cpu_transcoder));
6978 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6979 int vsync = I915_READ(VSYNC(cpu_transcoder));
6980
6981 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6982 if (!mode)
6983 return NULL;
6984
6985 mode->clock = intel_crtc_clock_get(dev, crtc);
6986 mode->hdisplay = (htot & 0xffff) + 1;
6987 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6988 mode->hsync_start = (hsync & 0xffff) + 1;
6989 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6990 mode->vdisplay = (vtot & 0xffff) + 1;
6991 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6992 mode->vsync_start = (vsync & 0xffff) + 1;
6993 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6994
6995 drm_mode_set_name(mode);
6996
6997 return mode;
6998 }
6999
7000 static void intel_increase_pllclock(struct drm_crtc *crtc)
7001 {
7002 struct drm_device *dev = crtc->dev;
7003 drm_i915_private_t *dev_priv = dev->dev_private;
7004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7005 int pipe = intel_crtc->pipe;
7006 int dpll_reg = DPLL(pipe);
7007 int dpll;
7008
7009 if (HAS_PCH_SPLIT(dev))
7010 return;
7011
7012 if (!dev_priv->lvds_downclock_avail)
7013 return;
7014
7015 dpll = I915_READ(dpll_reg);
7016 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7017 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7018
7019 assert_panel_unlocked(dev_priv, pipe);
7020
7021 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7022 I915_WRITE(dpll_reg, dpll);
7023 intel_wait_for_vblank(dev, pipe);
7024
7025 dpll = I915_READ(dpll_reg);
7026 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7027 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7028 }
7029 }
7030
7031 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7032 {
7033 struct drm_device *dev = crtc->dev;
7034 drm_i915_private_t *dev_priv = dev->dev_private;
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7036
7037 if (HAS_PCH_SPLIT(dev))
7038 return;
7039
7040 if (!dev_priv->lvds_downclock_avail)
7041 return;
7042
7043 /*
7044 * Since this is called by a timer, we should never get here in
7045 * the manual case.
7046 */
7047 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7048 int pipe = intel_crtc->pipe;
7049 int dpll_reg = DPLL(pipe);
7050 int dpll;
7051
7052 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7053
7054 assert_panel_unlocked(dev_priv, pipe);
7055
7056 dpll = I915_READ(dpll_reg);
7057 dpll |= DISPLAY_RATE_SELECT_FPA1;
7058 I915_WRITE(dpll_reg, dpll);
7059 intel_wait_for_vblank(dev, pipe);
7060 dpll = I915_READ(dpll_reg);
7061 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7062 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7063 }
7064
7065 }
7066
7067 void intel_mark_busy(struct drm_device *dev)
7068 {
7069 i915_update_gfx_val(dev->dev_private);
7070 }
7071
7072 void intel_mark_idle(struct drm_device *dev)
7073 {
7074 struct drm_crtc *crtc;
7075
7076 if (!i915_powersave)
7077 return;
7078
7079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7080 if (!crtc->fb)
7081 continue;
7082
7083 intel_decrease_pllclock(crtc);
7084 }
7085 }
7086
7087 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7088 struct intel_ring_buffer *ring)
7089 {
7090 struct drm_device *dev = obj->base.dev;
7091 struct drm_crtc *crtc;
7092
7093 if (!i915_powersave)
7094 return;
7095
7096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7097 if (!crtc->fb)
7098 continue;
7099
7100 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7101 continue;
7102
7103 intel_increase_pllclock(crtc);
7104 if (ring && intel_fbc_enabled(dev))
7105 ring->fbc_dirty = true;
7106 }
7107 }
7108
7109 static void intel_crtc_destroy(struct drm_crtc *crtc)
7110 {
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7112 struct drm_device *dev = crtc->dev;
7113 struct intel_unpin_work *work;
7114 unsigned long flags;
7115
7116 spin_lock_irqsave(&dev->event_lock, flags);
7117 work = intel_crtc->unpin_work;
7118 intel_crtc->unpin_work = NULL;
7119 spin_unlock_irqrestore(&dev->event_lock, flags);
7120
7121 if (work) {
7122 cancel_work_sync(&work->work);
7123 kfree(work);
7124 }
7125
7126 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7127
7128 drm_crtc_cleanup(crtc);
7129
7130 kfree(intel_crtc);
7131 }
7132
7133 static void intel_unpin_work_fn(struct work_struct *__work)
7134 {
7135 struct intel_unpin_work *work =
7136 container_of(__work, struct intel_unpin_work, work);
7137 struct drm_device *dev = work->crtc->dev;
7138
7139 mutex_lock(&dev->struct_mutex);
7140 intel_unpin_fb_obj(work->old_fb_obj);
7141 drm_gem_object_unreference(&work->pending_flip_obj->base);
7142 drm_gem_object_unreference(&work->old_fb_obj->base);
7143
7144 intel_update_fbc(dev);
7145 mutex_unlock(&dev->struct_mutex);
7146
7147 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7148 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7149
7150 kfree(work);
7151 }
7152
7153 static void do_intel_finish_page_flip(struct drm_device *dev,
7154 struct drm_crtc *crtc)
7155 {
7156 drm_i915_private_t *dev_priv = dev->dev_private;
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158 struct intel_unpin_work *work;
7159 unsigned long flags;
7160
7161 /* Ignore early vblank irqs */
7162 if (intel_crtc == NULL)
7163 return;
7164
7165 spin_lock_irqsave(&dev->event_lock, flags);
7166 work = intel_crtc->unpin_work;
7167
7168 /* Ensure we don't miss a work->pending update ... */
7169 smp_rmb();
7170
7171 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7172 spin_unlock_irqrestore(&dev->event_lock, flags);
7173 return;
7174 }
7175
7176 /* and that the unpin work is consistent wrt ->pending. */
7177 smp_rmb();
7178
7179 intel_crtc->unpin_work = NULL;
7180
7181 if (work->event)
7182 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7183
7184 drm_vblank_put(dev, intel_crtc->pipe);
7185
7186 spin_unlock_irqrestore(&dev->event_lock, flags);
7187
7188 wake_up_all(&dev_priv->pending_flip_queue);
7189
7190 queue_work(dev_priv->wq, &work->work);
7191
7192 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7193 }
7194
7195 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7196 {
7197 drm_i915_private_t *dev_priv = dev->dev_private;
7198 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7199
7200 do_intel_finish_page_flip(dev, crtc);
7201 }
7202
7203 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7204 {
7205 drm_i915_private_t *dev_priv = dev->dev_private;
7206 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7207
7208 do_intel_finish_page_flip(dev, crtc);
7209 }
7210
7211 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7212 {
7213 drm_i915_private_t *dev_priv = dev->dev_private;
7214 struct intel_crtc *intel_crtc =
7215 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7216 unsigned long flags;
7217
7218 /* NB: An MMIO update of the plane base pointer will also
7219 * generate a page-flip completion irq, i.e. every modeset
7220 * is also accompanied by a spurious intel_prepare_page_flip().
7221 */
7222 spin_lock_irqsave(&dev->event_lock, flags);
7223 if (intel_crtc->unpin_work)
7224 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7225 spin_unlock_irqrestore(&dev->event_lock, flags);
7226 }
7227
7228 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7229 {
7230 /* Ensure that the work item is consistent when activating it ... */
7231 smp_wmb();
7232 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7233 /* and that it is marked active as soon as the irq could fire. */
7234 smp_wmb();
7235 }
7236
7237 static int intel_gen2_queue_flip(struct drm_device *dev,
7238 struct drm_crtc *crtc,
7239 struct drm_framebuffer *fb,
7240 struct drm_i915_gem_object *obj)
7241 {
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244 u32 flip_mask;
7245 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7246 int ret;
7247
7248 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7249 if (ret)
7250 goto err;
7251
7252 ret = intel_ring_begin(ring, 6);
7253 if (ret)
7254 goto err_unpin;
7255
7256 /* Can't queue multiple flips, so wait for the previous
7257 * one to finish before executing the next.
7258 */
7259 if (intel_crtc->plane)
7260 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7261 else
7262 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7263 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7264 intel_ring_emit(ring, MI_NOOP);
7265 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7266 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7267 intel_ring_emit(ring, fb->pitches[0]);
7268 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7269 intel_ring_emit(ring, 0); /* aux display base address, unused */
7270
7271 intel_mark_page_flip_active(intel_crtc);
7272 intel_ring_advance(ring);
7273 return 0;
7274
7275 err_unpin:
7276 intel_unpin_fb_obj(obj);
7277 err:
7278 return ret;
7279 }
7280
7281 static int intel_gen3_queue_flip(struct drm_device *dev,
7282 struct drm_crtc *crtc,
7283 struct drm_framebuffer *fb,
7284 struct drm_i915_gem_object *obj)
7285 {
7286 struct drm_i915_private *dev_priv = dev->dev_private;
7287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7288 u32 flip_mask;
7289 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7290 int ret;
7291
7292 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7293 if (ret)
7294 goto err;
7295
7296 ret = intel_ring_begin(ring, 6);
7297 if (ret)
7298 goto err_unpin;
7299
7300 if (intel_crtc->plane)
7301 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7302 else
7303 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7304 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7305 intel_ring_emit(ring, MI_NOOP);
7306 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7307 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7308 intel_ring_emit(ring, fb->pitches[0]);
7309 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7310 intel_ring_emit(ring, MI_NOOP);
7311
7312 intel_mark_page_flip_active(intel_crtc);
7313 intel_ring_advance(ring);
7314 return 0;
7315
7316 err_unpin:
7317 intel_unpin_fb_obj(obj);
7318 err:
7319 return ret;
7320 }
7321
7322 static int intel_gen4_queue_flip(struct drm_device *dev,
7323 struct drm_crtc *crtc,
7324 struct drm_framebuffer *fb,
7325 struct drm_i915_gem_object *obj)
7326 {
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7329 uint32_t pf, pipesrc;
7330 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7331 int ret;
7332
7333 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7334 if (ret)
7335 goto err;
7336
7337 ret = intel_ring_begin(ring, 4);
7338 if (ret)
7339 goto err_unpin;
7340
7341 /* i965+ uses the linear or tiled offsets from the
7342 * Display Registers (which do not change across a page-flip)
7343 * so we need only reprogram the base address.
7344 */
7345 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7347 intel_ring_emit(ring, fb->pitches[0]);
7348 intel_ring_emit(ring,
7349 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7350 obj->tiling_mode);
7351
7352 /* XXX Enabling the panel-fitter across page-flip is so far
7353 * untested on non-native modes, so ignore it for now.
7354 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7355 */
7356 pf = 0;
7357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7358 intel_ring_emit(ring, pf | pipesrc);
7359
7360 intel_mark_page_flip_active(intel_crtc);
7361 intel_ring_advance(ring);
7362 return 0;
7363
7364 err_unpin:
7365 intel_unpin_fb_obj(obj);
7366 err:
7367 return ret;
7368 }
7369
7370 static int intel_gen6_queue_flip(struct drm_device *dev,
7371 struct drm_crtc *crtc,
7372 struct drm_framebuffer *fb,
7373 struct drm_i915_gem_object *obj)
7374 {
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7377 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7378 uint32_t pf, pipesrc;
7379 int ret;
7380
7381 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7382 if (ret)
7383 goto err;
7384
7385 ret = intel_ring_begin(ring, 4);
7386 if (ret)
7387 goto err_unpin;
7388
7389 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7390 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7391 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7392 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7393
7394 /* Contrary to the suggestions in the documentation,
7395 * "Enable Panel Fitter" does not seem to be required when page
7396 * flipping with a non-native mode, and worse causes a normal
7397 * modeset to fail.
7398 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7399 */
7400 pf = 0;
7401 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7402 intel_ring_emit(ring, pf | pipesrc);
7403
7404 intel_mark_page_flip_active(intel_crtc);
7405 intel_ring_advance(ring);
7406 return 0;
7407
7408 err_unpin:
7409 intel_unpin_fb_obj(obj);
7410 err:
7411 return ret;
7412 }
7413
7414 /*
7415 * On gen7 we currently use the blit ring because (in early silicon at least)
7416 * the render ring doesn't give us interrpts for page flip completion, which
7417 * means clients will hang after the first flip is queued. Fortunately the
7418 * blit ring generates interrupts properly, so use it instead.
7419 */
7420 static int intel_gen7_queue_flip(struct drm_device *dev,
7421 struct drm_crtc *crtc,
7422 struct drm_framebuffer *fb,
7423 struct drm_i915_gem_object *obj)
7424 {
7425 struct drm_i915_private *dev_priv = dev->dev_private;
7426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7427 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7428 uint32_t plane_bit = 0;
7429 int ret;
7430
7431 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7432 if (ret)
7433 goto err;
7434
7435 switch(intel_crtc->plane) {
7436 case PLANE_A:
7437 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7438 break;
7439 case PLANE_B:
7440 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7441 break;
7442 case PLANE_C:
7443 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7444 break;
7445 default:
7446 WARN_ONCE(1, "unknown plane in flip command\n");
7447 ret = -ENODEV;
7448 goto err_unpin;
7449 }
7450
7451 ret = intel_ring_begin(ring, 4);
7452 if (ret)
7453 goto err_unpin;
7454
7455 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7456 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7457 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7458 intel_ring_emit(ring, (MI_NOOP));
7459
7460 intel_mark_page_flip_active(intel_crtc);
7461 intel_ring_advance(ring);
7462 return 0;
7463
7464 err_unpin:
7465 intel_unpin_fb_obj(obj);
7466 err:
7467 return ret;
7468 }
7469
7470 static int intel_default_queue_flip(struct drm_device *dev,
7471 struct drm_crtc *crtc,
7472 struct drm_framebuffer *fb,
7473 struct drm_i915_gem_object *obj)
7474 {
7475 return -ENODEV;
7476 }
7477
7478 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7479 struct drm_framebuffer *fb,
7480 struct drm_pending_vblank_event *event)
7481 {
7482 struct drm_device *dev = crtc->dev;
7483 struct drm_i915_private *dev_priv = dev->dev_private;
7484 struct drm_framebuffer *old_fb = crtc->fb;
7485 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7487 struct intel_unpin_work *work;
7488 unsigned long flags;
7489 int ret;
7490
7491 /* Can't change pixel format via MI display flips. */
7492 if (fb->pixel_format != crtc->fb->pixel_format)
7493 return -EINVAL;
7494
7495 /*
7496 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7497 * Note that pitch changes could also affect these register.
7498 */
7499 if (INTEL_INFO(dev)->gen > 3 &&
7500 (fb->offsets[0] != crtc->fb->offsets[0] ||
7501 fb->pitches[0] != crtc->fb->pitches[0]))
7502 return -EINVAL;
7503
7504 work = kzalloc(sizeof *work, GFP_KERNEL);
7505 if (work == NULL)
7506 return -ENOMEM;
7507
7508 work->event = event;
7509 work->crtc = crtc;
7510 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7511 INIT_WORK(&work->work, intel_unpin_work_fn);
7512
7513 ret = drm_vblank_get(dev, intel_crtc->pipe);
7514 if (ret)
7515 goto free_work;
7516
7517 /* We borrow the event spin lock for protecting unpin_work */
7518 spin_lock_irqsave(&dev->event_lock, flags);
7519 if (intel_crtc->unpin_work) {
7520 spin_unlock_irqrestore(&dev->event_lock, flags);
7521 kfree(work);
7522 drm_vblank_put(dev, intel_crtc->pipe);
7523
7524 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7525 return -EBUSY;
7526 }
7527 intel_crtc->unpin_work = work;
7528 spin_unlock_irqrestore(&dev->event_lock, flags);
7529
7530 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7531 flush_workqueue(dev_priv->wq);
7532
7533 ret = i915_mutex_lock_interruptible(dev);
7534 if (ret)
7535 goto cleanup;
7536
7537 /* Reference the objects for the scheduled work. */
7538 drm_gem_object_reference(&work->old_fb_obj->base);
7539 drm_gem_object_reference(&obj->base);
7540
7541 crtc->fb = fb;
7542
7543 work->pending_flip_obj = obj;
7544
7545 work->enable_stall_check = true;
7546
7547 atomic_inc(&intel_crtc->unpin_work_count);
7548 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7549
7550 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7551 if (ret)
7552 goto cleanup_pending;
7553
7554 intel_disable_fbc(dev);
7555 intel_mark_fb_busy(obj, NULL);
7556 mutex_unlock(&dev->struct_mutex);
7557
7558 trace_i915_flip_request(intel_crtc->plane, obj);
7559
7560 return 0;
7561
7562 cleanup_pending:
7563 atomic_dec(&intel_crtc->unpin_work_count);
7564 crtc->fb = old_fb;
7565 drm_gem_object_unreference(&work->old_fb_obj->base);
7566 drm_gem_object_unreference(&obj->base);
7567 mutex_unlock(&dev->struct_mutex);
7568
7569 cleanup:
7570 spin_lock_irqsave(&dev->event_lock, flags);
7571 intel_crtc->unpin_work = NULL;
7572 spin_unlock_irqrestore(&dev->event_lock, flags);
7573
7574 drm_vblank_put(dev, intel_crtc->pipe);
7575 free_work:
7576 kfree(work);
7577
7578 return ret;
7579 }
7580
7581 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7582 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7583 .load_lut = intel_crtc_load_lut,
7584 };
7585
7586 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7587 struct drm_crtc *crtc)
7588 {
7589 struct drm_device *dev;
7590 struct drm_crtc *tmp;
7591 int crtc_mask = 1;
7592
7593 WARN(!crtc, "checking null crtc?\n");
7594
7595 dev = crtc->dev;
7596
7597 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7598 if (tmp == crtc)
7599 break;
7600 crtc_mask <<= 1;
7601 }
7602
7603 if (encoder->possible_crtcs & crtc_mask)
7604 return true;
7605 return false;
7606 }
7607
7608 /**
7609 * intel_modeset_update_staged_output_state
7610 *
7611 * Updates the staged output configuration state, e.g. after we've read out the
7612 * current hw state.
7613 */
7614 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7615 {
7616 struct intel_encoder *encoder;
7617 struct intel_connector *connector;
7618
7619 list_for_each_entry(connector, &dev->mode_config.connector_list,
7620 base.head) {
7621 connector->new_encoder =
7622 to_intel_encoder(connector->base.encoder);
7623 }
7624
7625 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7626 base.head) {
7627 encoder->new_crtc =
7628 to_intel_crtc(encoder->base.crtc);
7629 }
7630 }
7631
7632 /**
7633 * intel_modeset_commit_output_state
7634 *
7635 * This function copies the stage display pipe configuration to the real one.
7636 */
7637 static void intel_modeset_commit_output_state(struct drm_device *dev)
7638 {
7639 struct intel_encoder *encoder;
7640 struct intel_connector *connector;
7641
7642 list_for_each_entry(connector, &dev->mode_config.connector_list,
7643 base.head) {
7644 connector->base.encoder = &connector->new_encoder->base;
7645 }
7646
7647 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7648 base.head) {
7649 encoder->base.crtc = &encoder->new_crtc->base;
7650 }
7651 }
7652
7653 static void
7654 connected_sink_compute_bpp(struct intel_connector * connector,
7655 struct intel_crtc_config *pipe_config)
7656 {
7657 int bpp = pipe_config->pipe_bpp;
7658
7659 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7660 connector->base.base.id,
7661 drm_get_connector_name(&connector->base));
7662
7663 /* Don't use an invalid EDID bpc value */
7664 if (connector->base.display_info.bpc &&
7665 connector->base.display_info.bpc * 3 < bpp) {
7666 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7667 bpp, connector->base.display_info.bpc*3);
7668 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7669 }
7670
7671 /* Clamp bpp to 8 on screens without EDID 1.4 */
7672 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7673 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7674 bpp);
7675 pipe_config->pipe_bpp = 24;
7676 }
7677 }
7678
7679 static int
7680 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7681 struct drm_framebuffer *fb,
7682 struct intel_crtc_config *pipe_config)
7683 {
7684 struct drm_device *dev = crtc->base.dev;
7685 struct intel_connector *connector;
7686 int bpp;
7687
7688 switch (fb->pixel_format) {
7689 case DRM_FORMAT_C8:
7690 bpp = 8*3; /* since we go through a colormap */
7691 break;
7692 case DRM_FORMAT_XRGB1555:
7693 case DRM_FORMAT_ARGB1555:
7694 /* checked in intel_framebuffer_init already */
7695 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7696 return -EINVAL;
7697 case DRM_FORMAT_RGB565:
7698 bpp = 6*3; /* min is 18bpp */
7699 break;
7700 case DRM_FORMAT_XBGR8888:
7701 case DRM_FORMAT_ABGR8888:
7702 /* checked in intel_framebuffer_init already */
7703 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7704 return -EINVAL;
7705 case DRM_FORMAT_XRGB8888:
7706 case DRM_FORMAT_ARGB8888:
7707 bpp = 8*3;
7708 break;
7709 case DRM_FORMAT_XRGB2101010:
7710 case DRM_FORMAT_ARGB2101010:
7711 case DRM_FORMAT_XBGR2101010:
7712 case DRM_FORMAT_ABGR2101010:
7713 /* checked in intel_framebuffer_init already */
7714 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7715 return -EINVAL;
7716 bpp = 10*3;
7717 break;
7718 /* TODO: gen4+ supports 16 bpc floating point, too. */
7719 default:
7720 DRM_DEBUG_KMS("unsupported depth\n");
7721 return -EINVAL;
7722 }
7723
7724 pipe_config->pipe_bpp = bpp;
7725
7726 /* Clamp display bpp to EDID value */
7727 list_for_each_entry(connector, &dev->mode_config.connector_list,
7728 base.head) {
7729 if (!connector->new_encoder ||
7730 connector->new_encoder->new_crtc != crtc)
7731 continue;
7732
7733 connected_sink_compute_bpp(connector, pipe_config);
7734 }
7735
7736 return bpp;
7737 }
7738
7739 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7740 struct intel_crtc_config *pipe_config,
7741 const char *context)
7742 {
7743 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7744 context, pipe_name(crtc->pipe));
7745
7746 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7747 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7748 pipe_config->pipe_bpp, pipe_config->dither);
7749 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7750 pipe_config->has_pch_encoder,
7751 pipe_config->fdi_lanes,
7752 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7753 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7754 pipe_config->fdi_m_n.tu);
7755 DRM_DEBUG_KMS("requested mode:\n");
7756 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7757 DRM_DEBUG_KMS("adjusted mode:\n");
7758 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7759 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7760 pipe_config->gmch_pfit.control,
7761 pipe_config->gmch_pfit.pgm_ratios,
7762 pipe_config->gmch_pfit.lvds_border_bits);
7763 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7764 pipe_config->pch_pfit.pos,
7765 pipe_config->pch_pfit.size);
7766 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7767 }
7768
7769 static bool check_encoder_cloning(struct drm_crtc *crtc)
7770 {
7771 int num_encoders = 0;
7772 bool uncloneable_encoders = false;
7773 struct intel_encoder *encoder;
7774
7775 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7776 base.head) {
7777 if (&encoder->new_crtc->base != crtc)
7778 continue;
7779
7780 num_encoders++;
7781 if (!encoder->cloneable)
7782 uncloneable_encoders = true;
7783 }
7784
7785 return !(num_encoders > 1 && uncloneable_encoders);
7786 }
7787
7788 static struct intel_crtc_config *
7789 intel_modeset_pipe_config(struct drm_crtc *crtc,
7790 struct drm_framebuffer *fb,
7791 struct drm_display_mode *mode)
7792 {
7793 struct drm_device *dev = crtc->dev;
7794 struct drm_encoder_helper_funcs *encoder_funcs;
7795 struct intel_encoder *encoder;
7796 struct intel_crtc_config *pipe_config;
7797 int plane_bpp, ret = -EINVAL;
7798 bool retry = true;
7799
7800 if (!check_encoder_cloning(crtc)) {
7801 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7802 return ERR_PTR(-EINVAL);
7803 }
7804
7805 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7806 if (!pipe_config)
7807 return ERR_PTR(-ENOMEM);
7808
7809 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7810 drm_mode_copy(&pipe_config->requested_mode, mode);
7811 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7812 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7813
7814 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7815 * plane pixel format and any sink constraints into account. Returns the
7816 * source plane bpp so that dithering can be selected on mismatches
7817 * after encoders and crtc also have had their say. */
7818 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7819 fb, pipe_config);
7820 if (plane_bpp < 0)
7821 goto fail;
7822
7823 encoder_retry:
7824 /* Ensure the port clock defaults are reset when retrying. */
7825 pipe_config->port_clock = 0;
7826 pipe_config->pixel_multiplier = 1;
7827
7828 /* Pass our mode to the connectors and the CRTC to give them a chance to
7829 * adjust it according to limitations or connector properties, and also
7830 * a chance to reject the mode entirely.
7831 */
7832 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7833 base.head) {
7834
7835 if (&encoder->new_crtc->base != crtc)
7836 continue;
7837
7838 if (encoder->compute_config) {
7839 if (!(encoder->compute_config(encoder, pipe_config))) {
7840 DRM_DEBUG_KMS("Encoder config failure\n");
7841 goto fail;
7842 }
7843
7844 continue;
7845 }
7846
7847 encoder_funcs = encoder->base.helper_private;
7848 if (!(encoder_funcs->mode_fixup(&encoder->base,
7849 &pipe_config->requested_mode,
7850 &pipe_config->adjusted_mode))) {
7851 DRM_DEBUG_KMS("Encoder fixup failed\n");
7852 goto fail;
7853 }
7854 }
7855
7856 /* Set default port clock if not overwritten by the encoder. Needs to be
7857 * done afterwards in case the encoder adjusts the mode. */
7858 if (!pipe_config->port_clock)
7859 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7860
7861 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7862 if (ret < 0) {
7863 DRM_DEBUG_KMS("CRTC fixup failed\n");
7864 goto fail;
7865 }
7866
7867 if (ret == RETRY) {
7868 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7869 ret = -EINVAL;
7870 goto fail;
7871 }
7872
7873 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7874 retry = false;
7875 goto encoder_retry;
7876 }
7877
7878 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7879 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7880 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7881
7882 return pipe_config;
7883 fail:
7884 kfree(pipe_config);
7885 return ERR_PTR(ret);
7886 }
7887
7888 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7889 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7890 static void
7891 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7892 unsigned *prepare_pipes, unsigned *disable_pipes)
7893 {
7894 struct intel_crtc *intel_crtc;
7895 struct drm_device *dev = crtc->dev;
7896 struct intel_encoder *encoder;
7897 struct intel_connector *connector;
7898 struct drm_crtc *tmp_crtc;
7899
7900 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7901
7902 /* Check which crtcs have changed outputs connected to them, these need
7903 * to be part of the prepare_pipes mask. We don't (yet) support global
7904 * modeset across multiple crtcs, so modeset_pipes will only have one
7905 * bit set at most. */
7906 list_for_each_entry(connector, &dev->mode_config.connector_list,
7907 base.head) {
7908 if (connector->base.encoder == &connector->new_encoder->base)
7909 continue;
7910
7911 if (connector->base.encoder) {
7912 tmp_crtc = connector->base.encoder->crtc;
7913
7914 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7915 }
7916
7917 if (connector->new_encoder)
7918 *prepare_pipes |=
7919 1 << connector->new_encoder->new_crtc->pipe;
7920 }
7921
7922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7923 base.head) {
7924 if (encoder->base.crtc == &encoder->new_crtc->base)
7925 continue;
7926
7927 if (encoder->base.crtc) {
7928 tmp_crtc = encoder->base.crtc;
7929
7930 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7931 }
7932
7933 if (encoder->new_crtc)
7934 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7935 }
7936
7937 /* Check for any pipes that will be fully disabled ... */
7938 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7939 base.head) {
7940 bool used = false;
7941
7942 /* Don't try to disable disabled crtcs. */
7943 if (!intel_crtc->base.enabled)
7944 continue;
7945
7946 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7947 base.head) {
7948 if (encoder->new_crtc == intel_crtc)
7949 used = true;
7950 }
7951
7952 if (!used)
7953 *disable_pipes |= 1 << intel_crtc->pipe;
7954 }
7955
7956
7957 /* set_mode is also used to update properties on life display pipes. */
7958 intel_crtc = to_intel_crtc(crtc);
7959 if (crtc->enabled)
7960 *prepare_pipes |= 1 << intel_crtc->pipe;
7961
7962 /*
7963 * For simplicity do a full modeset on any pipe where the output routing
7964 * changed. We could be more clever, but that would require us to be
7965 * more careful with calling the relevant encoder->mode_set functions.
7966 */
7967 if (*prepare_pipes)
7968 *modeset_pipes = *prepare_pipes;
7969
7970 /* ... and mask these out. */
7971 *modeset_pipes &= ~(*disable_pipes);
7972 *prepare_pipes &= ~(*disable_pipes);
7973
7974 /*
7975 * HACK: We don't (yet) fully support global modesets. intel_set_config
7976 * obies this rule, but the modeset restore mode of
7977 * intel_modeset_setup_hw_state does not.
7978 */
7979 *modeset_pipes &= 1 << intel_crtc->pipe;
7980 *prepare_pipes &= 1 << intel_crtc->pipe;
7981
7982 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7983 *modeset_pipes, *prepare_pipes, *disable_pipes);
7984 }
7985
7986 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7987 {
7988 struct drm_encoder *encoder;
7989 struct drm_device *dev = crtc->dev;
7990
7991 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7992 if (encoder->crtc == crtc)
7993 return true;
7994
7995 return false;
7996 }
7997
7998 static void
7999 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8000 {
8001 struct intel_encoder *intel_encoder;
8002 struct intel_crtc *intel_crtc;
8003 struct drm_connector *connector;
8004
8005 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8006 base.head) {
8007 if (!intel_encoder->base.crtc)
8008 continue;
8009
8010 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8011
8012 if (prepare_pipes & (1 << intel_crtc->pipe))
8013 intel_encoder->connectors_active = false;
8014 }
8015
8016 intel_modeset_commit_output_state(dev);
8017
8018 /* Update computed state. */
8019 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8020 base.head) {
8021 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8022 }
8023
8024 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8025 if (!connector->encoder || !connector->encoder->crtc)
8026 continue;
8027
8028 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8029
8030 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8031 struct drm_property *dpms_property =
8032 dev->mode_config.dpms_property;
8033
8034 connector->dpms = DRM_MODE_DPMS_ON;
8035 drm_object_property_set_value(&connector->base,
8036 dpms_property,
8037 DRM_MODE_DPMS_ON);
8038
8039 intel_encoder = to_intel_encoder(connector->encoder);
8040 intel_encoder->connectors_active = true;
8041 }
8042 }
8043
8044 }
8045
8046 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8047 list_for_each_entry((intel_crtc), \
8048 &(dev)->mode_config.crtc_list, \
8049 base.head) \
8050 if (mask & (1 <<(intel_crtc)->pipe))
8051
8052 static bool
8053 intel_pipe_config_compare(struct drm_device *dev,
8054 struct intel_crtc_config *current_config,
8055 struct intel_crtc_config *pipe_config)
8056 {
8057 #define PIPE_CONF_CHECK_X(name) \
8058 if (current_config->name != pipe_config->name) { \
8059 DRM_ERROR("mismatch in " #name " " \
8060 "(expected 0x%08x, found 0x%08x)\n", \
8061 current_config->name, \
8062 pipe_config->name); \
8063 return false; \
8064 }
8065
8066 #define PIPE_CONF_CHECK_I(name) \
8067 if (current_config->name != pipe_config->name) { \
8068 DRM_ERROR("mismatch in " #name " " \
8069 "(expected %i, found %i)\n", \
8070 current_config->name, \
8071 pipe_config->name); \
8072 return false; \
8073 }
8074
8075 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8076 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8077 DRM_ERROR("mismatch in " #name " " \
8078 "(expected %i, found %i)\n", \
8079 current_config->name & (mask), \
8080 pipe_config->name & (mask)); \
8081 return false; \
8082 }
8083
8084 #define PIPE_CONF_QUIRK(quirk) \
8085 ((current_config->quirks | pipe_config->quirks) & (quirk))
8086
8087 PIPE_CONF_CHECK_I(cpu_transcoder);
8088
8089 PIPE_CONF_CHECK_I(has_pch_encoder);
8090 PIPE_CONF_CHECK_I(fdi_lanes);
8091 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8092 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8093 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8094 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8095 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8096
8097 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8101 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8102 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8103
8104 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8105 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8106 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8107 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8108 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8109 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8110
8111 if (!HAS_PCH_SPLIT(dev))
8112 PIPE_CONF_CHECK_I(pixel_multiplier);
8113
8114 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8115 DRM_MODE_FLAG_INTERLACE);
8116
8117 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8118 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8119 DRM_MODE_FLAG_PHSYNC);
8120 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8121 DRM_MODE_FLAG_NHSYNC);
8122 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8123 DRM_MODE_FLAG_PVSYNC);
8124 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8125 DRM_MODE_FLAG_NVSYNC);
8126 }
8127
8128 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8129 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8130
8131 PIPE_CONF_CHECK_I(gmch_pfit.control);
8132 /* pfit ratios are autocomputed by the hw on gen4+ */
8133 if (INTEL_INFO(dev)->gen < 4)
8134 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8135 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8136 PIPE_CONF_CHECK_I(pch_pfit.pos);
8137 PIPE_CONF_CHECK_I(pch_pfit.size);
8138
8139 PIPE_CONF_CHECK_I(ips_enabled);
8140
8141 PIPE_CONF_CHECK_I(shared_dpll);
8142 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8143 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8144 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8145
8146 #undef PIPE_CONF_CHECK_X
8147 #undef PIPE_CONF_CHECK_I
8148 #undef PIPE_CONF_CHECK_FLAGS
8149 #undef PIPE_CONF_QUIRK
8150
8151 return true;
8152 }
8153
8154 static void
8155 check_connector_state(struct drm_device *dev)
8156 {
8157 struct intel_connector *connector;
8158
8159 list_for_each_entry(connector, &dev->mode_config.connector_list,
8160 base.head) {
8161 /* This also checks the encoder/connector hw state with the
8162 * ->get_hw_state callbacks. */
8163 intel_connector_check_state(connector);
8164
8165 WARN(&connector->new_encoder->base != connector->base.encoder,
8166 "connector's staged encoder doesn't match current encoder\n");
8167 }
8168 }
8169
8170 static void
8171 check_encoder_state(struct drm_device *dev)
8172 {
8173 struct intel_encoder *encoder;
8174 struct intel_connector *connector;
8175
8176 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8177 base.head) {
8178 bool enabled = false;
8179 bool active = false;
8180 enum pipe pipe, tracked_pipe;
8181
8182 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8183 encoder->base.base.id,
8184 drm_get_encoder_name(&encoder->base));
8185
8186 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8187 "encoder's stage crtc doesn't match current crtc\n");
8188 WARN(encoder->connectors_active && !encoder->base.crtc,
8189 "encoder's active_connectors set, but no crtc\n");
8190
8191 list_for_each_entry(connector, &dev->mode_config.connector_list,
8192 base.head) {
8193 if (connector->base.encoder != &encoder->base)
8194 continue;
8195 enabled = true;
8196 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8197 active = true;
8198 }
8199 WARN(!!encoder->base.crtc != enabled,
8200 "encoder's enabled state mismatch "
8201 "(expected %i, found %i)\n",
8202 !!encoder->base.crtc, enabled);
8203 WARN(active && !encoder->base.crtc,
8204 "active encoder with no crtc\n");
8205
8206 WARN(encoder->connectors_active != active,
8207 "encoder's computed active state doesn't match tracked active state "
8208 "(expected %i, found %i)\n", active, encoder->connectors_active);
8209
8210 active = encoder->get_hw_state(encoder, &pipe);
8211 WARN(active != encoder->connectors_active,
8212 "encoder's hw state doesn't match sw tracking "
8213 "(expected %i, found %i)\n",
8214 encoder->connectors_active, active);
8215
8216 if (!encoder->base.crtc)
8217 continue;
8218
8219 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8220 WARN(active && pipe != tracked_pipe,
8221 "active encoder's pipe doesn't match"
8222 "(expected %i, found %i)\n",
8223 tracked_pipe, pipe);
8224
8225 }
8226 }
8227
8228 static void
8229 check_crtc_state(struct drm_device *dev)
8230 {
8231 drm_i915_private_t *dev_priv = dev->dev_private;
8232 struct intel_crtc *crtc;
8233 struct intel_encoder *encoder;
8234 struct intel_crtc_config pipe_config;
8235
8236 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8237 base.head) {
8238 bool enabled = false;
8239 bool active = false;
8240
8241 memset(&pipe_config, 0, sizeof(pipe_config));
8242
8243 DRM_DEBUG_KMS("[CRTC:%d]\n",
8244 crtc->base.base.id);
8245
8246 WARN(crtc->active && !crtc->base.enabled,
8247 "active crtc, but not enabled in sw tracking\n");
8248
8249 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8250 base.head) {
8251 if (encoder->base.crtc != &crtc->base)
8252 continue;
8253 enabled = true;
8254 if (encoder->connectors_active)
8255 active = true;
8256 }
8257
8258 WARN(active != crtc->active,
8259 "crtc's computed active state doesn't match tracked active state "
8260 "(expected %i, found %i)\n", active, crtc->active);
8261 WARN(enabled != crtc->base.enabled,
8262 "crtc's computed enabled state doesn't match tracked enabled state "
8263 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8264
8265 active = dev_priv->display.get_pipe_config(crtc,
8266 &pipe_config);
8267
8268 /* hw state is inconsistent with the pipe A quirk */
8269 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8270 active = crtc->active;
8271
8272 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8273 base.head) {
8274 if (encoder->base.crtc != &crtc->base)
8275 continue;
8276 if (encoder->get_config)
8277 encoder->get_config(encoder, &pipe_config);
8278 }
8279
8280 WARN(crtc->active != active,
8281 "crtc active state doesn't match with hw state "
8282 "(expected %i, found %i)\n", crtc->active, active);
8283
8284 if (active &&
8285 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8286 WARN(1, "pipe state doesn't match!\n");
8287 intel_dump_pipe_config(crtc, &pipe_config,
8288 "[hw state]");
8289 intel_dump_pipe_config(crtc, &crtc->config,
8290 "[sw state]");
8291 }
8292 }
8293 }
8294
8295 static void
8296 check_shared_dpll_state(struct drm_device *dev)
8297 {
8298 drm_i915_private_t *dev_priv = dev->dev_private;
8299 struct intel_crtc *crtc;
8300 struct intel_dpll_hw_state dpll_hw_state;
8301 int i;
8302
8303 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8304 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8305 int enabled_crtcs = 0, active_crtcs = 0;
8306 bool active;
8307
8308 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8309
8310 DRM_DEBUG_KMS("%s\n", pll->name);
8311
8312 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8313
8314 WARN(pll->active > pll->refcount,
8315 "more active pll users than references: %i vs %i\n",
8316 pll->active, pll->refcount);
8317 WARN(pll->active && !pll->on,
8318 "pll in active use but not on in sw tracking\n");
8319 WARN(pll->on != active,
8320 "pll on state mismatch (expected %i, found %i)\n",
8321 pll->on, active);
8322
8323 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8324 base.head) {
8325 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8326 enabled_crtcs++;
8327 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8328 active_crtcs++;
8329 }
8330 WARN(pll->active != active_crtcs,
8331 "pll active crtcs mismatch (expected %i, found %i)\n",
8332 pll->active, active_crtcs);
8333 WARN(pll->refcount != enabled_crtcs,
8334 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8335 pll->refcount, enabled_crtcs);
8336
8337 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8338 sizeof(dpll_hw_state)),
8339 "pll hw state mismatch\n");
8340 }
8341 }
8342
8343 void
8344 intel_modeset_check_state(struct drm_device *dev)
8345 {
8346 check_connector_state(dev);
8347 check_encoder_state(dev);
8348 check_crtc_state(dev);
8349 check_shared_dpll_state(dev);
8350 }
8351
8352 static int __intel_set_mode(struct drm_crtc *crtc,
8353 struct drm_display_mode *mode,
8354 int x, int y, struct drm_framebuffer *fb)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 drm_i915_private_t *dev_priv = dev->dev_private;
8358 struct drm_display_mode *saved_mode, *saved_hwmode;
8359 struct intel_crtc_config *pipe_config = NULL;
8360 struct intel_crtc *intel_crtc;
8361 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8362 int ret = 0;
8363
8364 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8365 if (!saved_mode)
8366 return -ENOMEM;
8367 saved_hwmode = saved_mode + 1;
8368
8369 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8370 &prepare_pipes, &disable_pipes);
8371
8372 *saved_hwmode = crtc->hwmode;
8373 *saved_mode = crtc->mode;
8374
8375 /* Hack: Because we don't (yet) support global modeset on multiple
8376 * crtcs, we don't keep track of the new mode for more than one crtc.
8377 * Hence simply check whether any bit is set in modeset_pipes in all the
8378 * pieces of code that are not yet converted to deal with mutliple crtcs
8379 * changing their mode at the same time. */
8380 if (modeset_pipes) {
8381 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8382 if (IS_ERR(pipe_config)) {
8383 ret = PTR_ERR(pipe_config);
8384 pipe_config = NULL;
8385
8386 goto out;
8387 }
8388 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8389 "[modeset]");
8390 }
8391
8392 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8393 intel_crtc_disable(&intel_crtc->base);
8394
8395 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8396 if (intel_crtc->base.enabled)
8397 dev_priv->display.crtc_disable(&intel_crtc->base);
8398 }
8399
8400 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8401 * to set it here already despite that we pass it down the callchain.
8402 */
8403 if (modeset_pipes) {
8404 crtc->mode = *mode;
8405 /* mode_set/enable/disable functions rely on a correct pipe
8406 * config. */
8407 to_intel_crtc(crtc)->config = *pipe_config;
8408 }
8409
8410 /* Only after disabling all output pipelines that will be changed can we
8411 * update the the output configuration. */
8412 intel_modeset_update_state(dev, prepare_pipes);
8413
8414 if (dev_priv->display.modeset_global_resources)
8415 dev_priv->display.modeset_global_resources(dev);
8416
8417 /* Set up the DPLL and any encoders state that needs to adjust or depend
8418 * on the DPLL.
8419 */
8420 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8421 ret = intel_crtc_mode_set(&intel_crtc->base,
8422 x, y, fb);
8423 if (ret)
8424 goto done;
8425 }
8426
8427 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8428 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8429 dev_priv->display.crtc_enable(&intel_crtc->base);
8430
8431 if (modeset_pipes) {
8432 /* Store real post-adjustment hardware mode. */
8433 crtc->hwmode = pipe_config->adjusted_mode;
8434
8435 /* Calculate and store various constants which
8436 * are later needed by vblank and swap-completion
8437 * timestamping. They are derived from true hwmode.
8438 */
8439 drm_calc_timestamping_constants(crtc);
8440 }
8441
8442 /* FIXME: add subpixel order */
8443 done:
8444 if (ret && crtc->enabled) {
8445 crtc->hwmode = *saved_hwmode;
8446 crtc->mode = *saved_mode;
8447 }
8448
8449 out:
8450 kfree(pipe_config);
8451 kfree(saved_mode);
8452 return ret;
8453 }
8454
8455 int intel_set_mode(struct drm_crtc *crtc,
8456 struct drm_display_mode *mode,
8457 int x, int y, struct drm_framebuffer *fb)
8458 {
8459 int ret;
8460
8461 ret = __intel_set_mode(crtc, mode, x, y, fb);
8462
8463 if (ret == 0)
8464 intel_modeset_check_state(crtc->dev);
8465
8466 return ret;
8467 }
8468
8469 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8470 {
8471 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8472 }
8473
8474 #undef for_each_intel_crtc_masked
8475
8476 static void intel_set_config_free(struct intel_set_config *config)
8477 {
8478 if (!config)
8479 return;
8480
8481 kfree(config->save_connector_encoders);
8482 kfree(config->save_encoder_crtcs);
8483 kfree(config);
8484 }
8485
8486 static int intel_set_config_save_state(struct drm_device *dev,
8487 struct intel_set_config *config)
8488 {
8489 struct drm_encoder *encoder;
8490 struct drm_connector *connector;
8491 int count;
8492
8493 config->save_encoder_crtcs =
8494 kcalloc(dev->mode_config.num_encoder,
8495 sizeof(struct drm_crtc *), GFP_KERNEL);
8496 if (!config->save_encoder_crtcs)
8497 return -ENOMEM;
8498
8499 config->save_connector_encoders =
8500 kcalloc(dev->mode_config.num_connector,
8501 sizeof(struct drm_encoder *), GFP_KERNEL);
8502 if (!config->save_connector_encoders)
8503 return -ENOMEM;
8504
8505 /* Copy data. Note that driver private data is not affected.
8506 * Should anything bad happen only the expected state is
8507 * restored, not the drivers personal bookkeeping.
8508 */
8509 count = 0;
8510 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8511 config->save_encoder_crtcs[count++] = encoder->crtc;
8512 }
8513
8514 count = 0;
8515 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8516 config->save_connector_encoders[count++] = connector->encoder;
8517 }
8518
8519 return 0;
8520 }
8521
8522 static void intel_set_config_restore_state(struct drm_device *dev,
8523 struct intel_set_config *config)
8524 {
8525 struct intel_encoder *encoder;
8526 struct intel_connector *connector;
8527 int count;
8528
8529 count = 0;
8530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8531 encoder->new_crtc =
8532 to_intel_crtc(config->save_encoder_crtcs[count++]);
8533 }
8534
8535 count = 0;
8536 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8537 connector->new_encoder =
8538 to_intel_encoder(config->save_connector_encoders[count++]);
8539 }
8540 }
8541
8542 static bool
8543 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8544 int num_connectors)
8545 {
8546 int i;
8547
8548 for (i = 0; i < num_connectors; i++)
8549 if (connectors[i].encoder &&
8550 connectors[i].encoder->crtc == crtc &&
8551 connectors[i].dpms != DRM_MODE_DPMS_ON)
8552 return true;
8553
8554 return false;
8555 }
8556
8557 static void
8558 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8559 struct intel_set_config *config)
8560 {
8561
8562 /* We should be able to check here if the fb has the same properties
8563 * and then just flip_or_move it */
8564 if (set->connectors != NULL &&
8565 is_crtc_connector_off(set->crtc, *set->connectors,
8566 set->num_connectors)) {
8567 config->mode_changed = true;
8568 } else if (set->crtc->fb != set->fb) {
8569 /* If we have no fb then treat it as a full mode set */
8570 if (set->crtc->fb == NULL) {
8571 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8572 config->mode_changed = true;
8573 } else if (set->fb == NULL) {
8574 config->mode_changed = true;
8575 } else if (set->fb->pixel_format !=
8576 set->crtc->fb->pixel_format) {
8577 config->mode_changed = true;
8578 } else {
8579 config->fb_changed = true;
8580 }
8581 }
8582
8583 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8584 config->fb_changed = true;
8585
8586 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8587 DRM_DEBUG_KMS("modes are different, full mode set\n");
8588 drm_mode_debug_printmodeline(&set->crtc->mode);
8589 drm_mode_debug_printmodeline(set->mode);
8590 config->mode_changed = true;
8591 }
8592 }
8593
8594 static int
8595 intel_modeset_stage_output_state(struct drm_device *dev,
8596 struct drm_mode_set *set,
8597 struct intel_set_config *config)
8598 {
8599 struct drm_crtc *new_crtc;
8600 struct intel_connector *connector;
8601 struct intel_encoder *encoder;
8602 int count, ro;
8603
8604 /* The upper layers ensure that we either disable a crtc or have a list
8605 * of connectors. For paranoia, double-check this. */
8606 WARN_ON(!set->fb && (set->num_connectors != 0));
8607 WARN_ON(set->fb && (set->num_connectors == 0));
8608
8609 count = 0;
8610 list_for_each_entry(connector, &dev->mode_config.connector_list,
8611 base.head) {
8612 /* Otherwise traverse passed in connector list and get encoders
8613 * for them. */
8614 for (ro = 0; ro < set->num_connectors; ro++) {
8615 if (set->connectors[ro] == &connector->base) {
8616 connector->new_encoder = connector->encoder;
8617 break;
8618 }
8619 }
8620
8621 /* If we disable the crtc, disable all its connectors. Also, if
8622 * the connector is on the changing crtc but not on the new
8623 * connector list, disable it. */
8624 if ((!set->fb || ro == set->num_connectors) &&
8625 connector->base.encoder &&
8626 connector->base.encoder->crtc == set->crtc) {
8627 connector->new_encoder = NULL;
8628
8629 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8630 connector->base.base.id,
8631 drm_get_connector_name(&connector->base));
8632 }
8633
8634
8635 if (&connector->new_encoder->base != connector->base.encoder) {
8636 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8637 config->mode_changed = true;
8638 }
8639 }
8640 /* connector->new_encoder is now updated for all connectors. */
8641
8642 /* Update crtc of enabled connectors. */
8643 count = 0;
8644 list_for_each_entry(connector, &dev->mode_config.connector_list,
8645 base.head) {
8646 if (!connector->new_encoder)
8647 continue;
8648
8649 new_crtc = connector->new_encoder->base.crtc;
8650
8651 for (ro = 0; ro < set->num_connectors; ro++) {
8652 if (set->connectors[ro] == &connector->base)
8653 new_crtc = set->crtc;
8654 }
8655
8656 /* Make sure the new CRTC will work with the encoder */
8657 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8658 new_crtc)) {
8659 return -EINVAL;
8660 }
8661 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8662
8663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8664 connector->base.base.id,
8665 drm_get_connector_name(&connector->base),
8666 new_crtc->base.id);
8667 }
8668
8669 /* Check for any encoders that needs to be disabled. */
8670 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8671 base.head) {
8672 list_for_each_entry(connector,
8673 &dev->mode_config.connector_list,
8674 base.head) {
8675 if (connector->new_encoder == encoder) {
8676 WARN_ON(!connector->new_encoder->new_crtc);
8677
8678 goto next_encoder;
8679 }
8680 }
8681 encoder->new_crtc = NULL;
8682 next_encoder:
8683 /* Only now check for crtc changes so we don't miss encoders
8684 * that will be disabled. */
8685 if (&encoder->new_crtc->base != encoder->base.crtc) {
8686 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8687 config->mode_changed = true;
8688 }
8689 }
8690 /* Now we've also updated encoder->new_crtc for all encoders. */
8691
8692 return 0;
8693 }
8694
8695 static int intel_crtc_set_config(struct drm_mode_set *set)
8696 {
8697 struct drm_device *dev;
8698 struct drm_mode_set save_set;
8699 struct intel_set_config *config;
8700 int ret;
8701
8702 BUG_ON(!set);
8703 BUG_ON(!set->crtc);
8704 BUG_ON(!set->crtc->helper_private);
8705
8706 /* Enforce sane interface api - has been abused by the fb helper. */
8707 BUG_ON(!set->mode && set->fb);
8708 BUG_ON(set->fb && set->num_connectors == 0);
8709
8710 if (set->fb) {
8711 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8712 set->crtc->base.id, set->fb->base.id,
8713 (int)set->num_connectors, set->x, set->y);
8714 } else {
8715 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8716 }
8717
8718 dev = set->crtc->dev;
8719
8720 ret = -ENOMEM;
8721 config = kzalloc(sizeof(*config), GFP_KERNEL);
8722 if (!config)
8723 goto out_config;
8724
8725 ret = intel_set_config_save_state(dev, config);
8726 if (ret)
8727 goto out_config;
8728
8729 save_set.crtc = set->crtc;
8730 save_set.mode = &set->crtc->mode;
8731 save_set.x = set->crtc->x;
8732 save_set.y = set->crtc->y;
8733 save_set.fb = set->crtc->fb;
8734
8735 /* Compute whether we need a full modeset, only an fb base update or no
8736 * change at all. In the future we might also check whether only the
8737 * mode changed, e.g. for LVDS where we only change the panel fitter in
8738 * such cases. */
8739 intel_set_config_compute_mode_changes(set, config);
8740
8741 ret = intel_modeset_stage_output_state(dev, set, config);
8742 if (ret)
8743 goto fail;
8744
8745 if (config->mode_changed) {
8746 ret = intel_set_mode(set->crtc, set->mode,
8747 set->x, set->y, set->fb);
8748 } else if (config->fb_changed) {
8749 intel_crtc_wait_for_pending_flips(set->crtc);
8750
8751 ret = intel_pipe_set_base(set->crtc,
8752 set->x, set->y, set->fb);
8753 }
8754
8755 if (ret) {
8756 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8757 set->crtc->base.id, ret);
8758 fail:
8759 intel_set_config_restore_state(dev, config);
8760
8761 /* Try to restore the config */
8762 if (config->mode_changed &&
8763 intel_set_mode(save_set.crtc, save_set.mode,
8764 save_set.x, save_set.y, save_set.fb))
8765 DRM_ERROR("failed to restore config after modeset failure\n");
8766 }
8767
8768 out_config:
8769 intel_set_config_free(config);
8770 return ret;
8771 }
8772
8773 static const struct drm_crtc_funcs intel_crtc_funcs = {
8774 .cursor_set = intel_crtc_cursor_set,
8775 .cursor_move = intel_crtc_cursor_move,
8776 .gamma_set = intel_crtc_gamma_set,
8777 .set_config = intel_crtc_set_config,
8778 .destroy = intel_crtc_destroy,
8779 .page_flip = intel_crtc_page_flip,
8780 };
8781
8782 static void intel_cpu_pll_init(struct drm_device *dev)
8783 {
8784 if (HAS_DDI(dev))
8785 intel_ddi_pll_init(dev);
8786 }
8787
8788 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8789 struct intel_shared_dpll *pll,
8790 struct intel_dpll_hw_state *hw_state)
8791 {
8792 uint32_t val;
8793
8794 val = I915_READ(PCH_DPLL(pll->id));
8795 hw_state->dpll = val;
8796 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8797 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8798
8799 return val & DPLL_VCO_ENABLE;
8800 }
8801
8802 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8803 struct intel_shared_dpll *pll)
8804 {
8805 uint32_t reg, val;
8806
8807 /* PCH refclock must be enabled first */
8808 assert_pch_refclk_enabled(dev_priv);
8809
8810 reg = PCH_DPLL(pll->id);
8811 val = I915_READ(reg);
8812 val |= DPLL_VCO_ENABLE;
8813 I915_WRITE(reg, val);
8814 POSTING_READ(reg);
8815 udelay(200);
8816 }
8817
8818 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8819 struct intel_shared_dpll *pll)
8820 {
8821 struct drm_device *dev = dev_priv->dev;
8822 struct intel_crtc *crtc;
8823 uint32_t reg, val;
8824
8825 /* Make sure no transcoder isn't still depending on us. */
8826 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8827 if (intel_crtc_to_shared_dpll(crtc) == pll)
8828 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8829 }
8830
8831 reg = PCH_DPLL(pll->id);
8832 val = I915_READ(reg);
8833 val &= ~DPLL_VCO_ENABLE;
8834 I915_WRITE(reg, val);
8835 POSTING_READ(reg);
8836 udelay(200);
8837 }
8838
8839 static char *ibx_pch_dpll_names[] = {
8840 "PCH DPLL A",
8841 "PCH DPLL B",
8842 };
8843
8844 static void ibx_pch_dpll_init(struct drm_device *dev)
8845 {
8846 struct drm_i915_private *dev_priv = dev->dev_private;
8847 int i;
8848
8849 dev_priv->num_shared_dpll = 2;
8850
8851 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8852 dev_priv->shared_dplls[i].id = i;
8853 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8854 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8855 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8856 dev_priv->shared_dplls[i].get_hw_state =
8857 ibx_pch_dpll_get_hw_state;
8858 }
8859 }
8860
8861 static void intel_shared_dpll_init(struct drm_device *dev)
8862 {
8863 struct drm_i915_private *dev_priv = dev->dev_private;
8864
8865 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8866 ibx_pch_dpll_init(dev);
8867 else
8868 dev_priv->num_shared_dpll = 0;
8869
8870 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8871 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8872 dev_priv->num_shared_dpll);
8873 }
8874
8875 static void intel_crtc_init(struct drm_device *dev, int pipe)
8876 {
8877 drm_i915_private_t *dev_priv = dev->dev_private;
8878 struct intel_crtc *intel_crtc;
8879 int i;
8880
8881 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8882 if (intel_crtc == NULL)
8883 return;
8884
8885 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8886
8887 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8888 for (i = 0; i < 256; i++) {
8889 intel_crtc->lut_r[i] = i;
8890 intel_crtc->lut_g[i] = i;
8891 intel_crtc->lut_b[i] = i;
8892 }
8893
8894 /* Swap pipes & planes for FBC on pre-965 */
8895 intel_crtc->pipe = pipe;
8896 intel_crtc->plane = pipe;
8897 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8898 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8899 intel_crtc->plane = !pipe;
8900 }
8901
8902 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8903 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8904 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8905 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8906
8907 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8908 }
8909
8910 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8911 struct drm_file *file)
8912 {
8913 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8914 struct drm_mode_object *drmmode_obj;
8915 struct intel_crtc *crtc;
8916
8917 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8918 return -ENODEV;
8919
8920 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8921 DRM_MODE_OBJECT_CRTC);
8922
8923 if (!drmmode_obj) {
8924 DRM_ERROR("no such CRTC id\n");
8925 return -EINVAL;
8926 }
8927
8928 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8929 pipe_from_crtc_id->pipe = crtc->pipe;
8930
8931 return 0;
8932 }
8933
8934 static int intel_encoder_clones(struct intel_encoder *encoder)
8935 {
8936 struct drm_device *dev = encoder->base.dev;
8937 struct intel_encoder *source_encoder;
8938 int index_mask = 0;
8939 int entry = 0;
8940
8941 list_for_each_entry(source_encoder,
8942 &dev->mode_config.encoder_list, base.head) {
8943
8944 if (encoder == source_encoder)
8945 index_mask |= (1 << entry);
8946
8947 /* Intel hw has only one MUX where enocoders could be cloned. */
8948 if (encoder->cloneable && source_encoder->cloneable)
8949 index_mask |= (1 << entry);
8950
8951 entry++;
8952 }
8953
8954 return index_mask;
8955 }
8956
8957 static bool has_edp_a(struct drm_device *dev)
8958 {
8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960
8961 if (!IS_MOBILE(dev))
8962 return false;
8963
8964 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8965 return false;
8966
8967 if (IS_GEN5(dev) &&
8968 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8969 return false;
8970
8971 return true;
8972 }
8973
8974 static void intel_setup_outputs(struct drm_device *dev)
8975 {
8976 struct drm_i915_private *dev_priv = dev->dev_private;
8977 struct intel_encoder *encoder;
8978 bool dpd_is_edp = false;
8979
8980 intel_lvds_init(dev);
8981
8982 if (!IS_ULT(dev))
8983 intel_crt_init(dev);
8984
8985 if (HAS_DDI(dev)) {
8986 int found;
8987
8988 /* Haswell uses DDI functions to detect digital outputs */
8989 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8990 /* DDI A only supports eDP */
8991 if (found)
8992 intel_ddi_init(dev, PORT_A);
8993
8994 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8995 * register */
8996 found = I915_READ(SFUSE_STRAP);
8997
8998 if (found & SFUSE_STRAP_DDIB_DETECTED)
8999 intel_ddi_init(dev, PORT_B);
9000 if (found & SFUSE_STRAP_DDIC_DETECTED)
9001 intel_ddi_init(dev, PORT_C);
9002 if (found & SFUSE_STRAP_DDID_DETECTED)
9003 intel_ddi_init(dev, PORT_D);
9004 } else if (HAS_PCH_SPLIT(dev)) {
9005 int found;
9006 dpd_is_edp = intel_dpd_is_edp(dev);
9007
9008 if (has_edp_a(dev))
9009 intel_dp_init(dev, DP_A, PORT_A);
9010
9011 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9012 /* PCH SDVOB multiplex with HDMIB */
9013 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9014 if (!found)
9015 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9016 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9017 intel_dp_init(dev, PCH_DP_B, PORT_B);
9018 }
9019
9020 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9021 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9022
9023 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9024 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9025
9026 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9027 intel_dp_init(dev, PCH_DP_C, PORT_C);
9028
9029 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9030 intel_dp_init(dev, PCH_DP_D, PORT_D);
9031 } else if (IS_VALLEYVIEW(dev)) {
9032 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9033 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9034 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9035
9036 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9037 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9038 PORT_B);
9039 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9040 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9041 }
9042 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9043 bool found = false;
9044
9045 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9046 DRM_DEBUG_KMS("probing SDVOB\n");
9047 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9048 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9049 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9050 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9051 }
9052
9053 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9054 intel_dp_init(dev, DP_B, PORT_B);
9055 }
9056
9057 /* Before G4X SDVOC doesn't have its own detect register */
9058
9059 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9060 DRM_DEBUG_KMS("probing SDVOC\n");
9061 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9062 }
9063
9064 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9065
9066 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9067 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9068 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9069 }
9070 if (SUPPORTS_INTEGRATED_DP(dev))
9071 intel_dp_init(dev, DP_C, PORT_C);
9072 }
9073
9074 if (SUPPORTS_INTEGRATED_DP(dev) &&
9075 (I915_READ(DP_D) & DP_DETECTED))
9076 intel_dp_init(dev, DP_D, PORT_D);
9077 } else if (IS_GEN2(dev))
9078 intel_dvo_init(dev);
9079
9080 if (SUPPORTS_TV(dev))
9081 intel_tv_init(dev);
9082
9083 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9084 encoder->base.possible_crtcs = encoder->crtc_mask;
9085 encoder->base.possible_clones =
9086 intel_encoder_clones(encoder);
9087 }
9088
9089 intel_init_pch_refclk(dev);
9090
9091 drm_helper_move_panel_connectors_to_head(dev);
9092 }
9093
9094 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9095 {
9096 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9097
9098 drm_framebuffer_cleanup(fb);
9099 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9100
9101 kfree(intel_fb);
9102 }
9103
9104 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9105 struct drm_file *file,
9106 unsigned int *handle)
9107 {
9108 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9109 struct drm_i915_gem_object *obj = intel_fb->obj;
9110
9111 return drm_gem_handle_create(file, &obj->base, handle);
9112 }
9113
9114 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9115 .destroy = intel_user_framebuffer_destroy,
9116 .create_handle = intel_user_framebuffer_create_handle,
9117 };
9118
9119 int intel_framebuffer_init(struct drm_device *dev,
9120 struct intel_framebuffer *intel_fb,
9121 struct drm_mode_fb_cmd2 *mode_cmd,
9122 struct drm_i915_gem_object *obj)
9123 {
9124 int ret;
9125
9126 if (obj->tiling_mode == I915_TILING_Y) {
9127 DRM_DEBUG("hardware does not support tiling Y\n");
9128 return -EINVAL;
9129 }
9130
9131 if (mode_cmd->pitches[0] & 63) {
9132 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9133 mode_cmd->pitches[0]);
9134 return -EINVAL;
9135 }
9136
9137 /* FIXME <= Gen4 stride limits are bit unclear */
9138 if (mode_cmd->pitches[0] > 32768) {
9139 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9140 mode_cmd->pitches[0]);
9141 return -EINVAL;
9142 }
9143
9144 if (obj->tiling_mode != I915_TILING_NONE &&
9145 mode_cmd->pitches[0] != obj->stride) {
9146 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9147 mode_cmd->pitches[0], obj->stride);
9148 return -EINVAL;
9149 }
9150
9151 /* Reject formats not supported by any plane early. */
9152 switch (mode_cmd->pixel_format) {
9153 case DRM_FORMAT_C8:
9154 case DRM_FORMAT_RGB565:
9155 case DRM_FORMAT_XRGB8888:
9156 case DRM_FORMAT_ARGB8888:
9157 break;
9158 case DRM_FORMAT_XRGB1555:
9159 case DRM_FORMAT_ARGB1555:
9160 if (INTEL_INFO(dev)->gen > 3) {
9161 DRM_DEBUG("unsupported pixel format: %s\n",
9162 drm_get_format_name(mode_cmd->pixel_format));
9163 return -EINVAL;
9164 }
9165 break;
9166 case DRM_FORMAT_XBGR8888:
9167 case DRM_FORMAT_ABGR8888:
9168 case DRM_FORMAT_XRGB2101010:
9169 case DRM_FORMAT_ARGB2101010:
9170 case DRM_FORMAT_XBGR2101010:
9171 case DRM_FORMAT_ABGR2101010:
9172 if (INTEL_INFO(dev)->gen < 4) {
9173 DRM_DEBUG("unsupported pixel format: %s\n",
9174 drm_get_format_name(mode_cmd->pixel_format));
9175 return -EINVAL;
9176 }
9177 break;
9178 case DRM_FORMAT_YUYV:
9179 case DRM_FORMAT_UYVY:
9180 case DRM_FORMAT_YVYU:
9181 case DRM_FORMAT_VYUY:
9182 if (INTEL_INFO(dev)->gen < 5) {
9183 DRM_DEBUG("unsupported pixel format: %s\n",
9184 drm_get_format_name(mode_cmd->pixel_format));
9185 return -EINVAL;
9186 }
9187 break;
9188 default:
9189 DRM_DEBUG("unsupported pixel format: %s\n",
9190 drm_get_format_name(mode_cmd->pixel_format));
9191 return -EINVAL;
9192 }
9193
9194 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9195 if (mode_cmd->offsets[0] != 0)
9196 return -EINVAL;
9197
9198 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9199 intel_fb->obj = obj;
9200
9201 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9202 if (ret) {
9203 DRM_ERROR("framebuffer init failed %d\n", ret);
9204 return ret;
9205 }
9206
9207 return 0;
9208 }
9209
9210 static struct drm_framebuffer *
9211 intel_user_framebuffer_create(struct drm_device *dev,
9212 struct drm_file *filp,
9213 struct drm_mode_fb_cmd2 *mode_cmd)
9214 {
9215 struct drm_i915_gem_object *obj;
9216
9217 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9218 mode_cmd->handles[0]));
9219 if (&obj->base == NULL)
9220 return ERR_PTR(-ENOENT);
9221
9222 return intel_framebuffer_create(dev, mode_cmd, obj);
9223 }
9224
9225 static const struct drm_mode_config_funcs intel_mode_funcs = {
9226 .fb_create = intel_user_framebuffer_create,
9227 .output_poll_changed = intel_fb_output_poll_changed,
9228 };
9229
9230 /* Set up chip specific display functions */
9231 static void intel_init_display(struct drm_device *dev)
9232 {
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234
9235 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9236 dev_priv->display.find_dpll = g4x_find_best_dpll;
9237 else if (IS_VALLEYVIEW(dev))
9238 dev_priv->display.find_dpll = vlv_find_best_dpll;
9239 else if (IS_PINEVIEW(dev))
9240 dev_priv->display.find_dpll = pnv_find_best_dpll;
9241 else
9242 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9243
9244 if (HAS_DDI(dev)) {
9245 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9246 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9247 dev_priv->display.crtc_enable = haswell_crtc_enable;
9248 dev_priv->display.crtc_disable = haswell_crtc_disable;
9249 dev_priv->display.off = haswell_crtc_off;
9250 dev_priv->display.update_plane = ironlake_update_plane;
9251 } else if (HAS_PCH_SPLIT(dev)) {
9252 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9253 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9254 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9255 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9256 dev_priv->display.off = ironlake_crtc_off;
9257 dev_priv->display.update_plane = ironlake_update_plane;
9258 } else if (IS_VALLEYVIEW(dev)) {
9259 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9260 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9261 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9262 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9263 dev_priv->display.off = i9xx_crtc_off;
9264 dev_priv->display.update_plane = i9xx_update_plane;
9265 } else {
9266 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9267 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9268 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9269 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9270 dev_priv->display.off = i9xx_crtc_off;
9271 dev_priv->display.update_plane = i9xx_update_plane;
9272 }
9273
9274 /* Returns the core display clock speed */
9275 if (IS_VALLEYVIEW(dev))
9276 dev_priv->display.get_display_clock_speed =
9277 valleyview_get_display_clock_speed;
9278 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9279 dev_priv->display.get_display_clock_speed =
9280 i945_get_display_clock_speed;
9281 else if (IS_I915G(dev))
9282 dev_priv->display.get_display_clock_speed =
9283 i915_get_display_clock_speed;
9284 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9285 dev_priv->display.get_display_clock_speed =
9286 i9xx_misc_get_display_clock_speed;
9287 else if (IS_I915GM(dev))
9288 dev_priv->display.get_display_clock_speed =
9289 i915gm_get_display_clock_speed;
9290 else if (IS_I865G(dev))
9291 dev_priv->display.get_display_clock_speed =
9292 i865_get_display_clock_speed;
9293 else if (IS_I85X(dev))
9294 dev_priv->display.get_display_clock_speed =
9295 i855_get_display_clock_speed;
9296 else /* 852, 830 */
9297 dev_priv->display.get_display_clock_speed =
9298 i830_get_display_clock_speed;
9299
9300 if (HAS_PCH_SPLIT(dev)) {
9301 if (IS_GEN5(dev)) {
9302 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9303 dev_priv->display.write_eld = ironlake_write_eld;
9304 } else if (IS_GEN6(dev)) {
9305 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9306 dev_priv->display.write_eld = ironlake_write_eld;
9307 } else if (IS_IVYBRIDGE(dev)) {
9308 /* FIXME: detect B0+ stepping and use auto training */
9309 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9310 dev_priv->display.write_eld = ironlake_write_eld;
9311 dev_priv->display.modeset_global_resources =
9312 ivb_modeset_global_resources;
9313 } else if (IS_HASWELL(dev)) {
9314 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9315 dev_priv->display.write_eld = haswell_write_eld;
9316 dev_priv->display.modeset_global_resources =
9317 haswell_modeset_global_resources;
9318 }
9319 } else if (IS_G4X(dev)) {
9320 dev_priv->display.write_eld = g4x_write_eld;
9321 }
9322
9323 /* Default just returns -ENODEV to indicate unsupported */
9324 dev_priv->display.queue_flip = intel_default_queue_flip;
9325
9326 switch (INTEL_INFO(dev)->gen) {
9327 case 2:
9328 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9329 break;
9330
9331 case 3:
9332 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9333 break;
9334
9335 case 4:
9336 case 5:
9337 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9338 break;
9339
9340 case 6:
9341 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9342 break;
9343 case 7:
9344 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9345 break;
9346 }
9347 }
9348
9349 /*
9350 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9351 * resume, or other times. This quirk makes sure that's the case for
9352 * affected systems.
9353 */
9354 static void quirk_pipea_force(struct drm_device *dev)
9355 {
9356 struct drm_i915_private *dev_priv = dev->dev_private;
9357
9358 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9359 DRM_INFO("applying pipe a force quirk\n");
9360 }
9361
9362 /*
9363 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9364 */
9365 static void quirk_ssc_force_disable(struct drm_device *dev)
9366 {
9367 struct drm_i915_private *dev_priv = dev->dev_private;
9368 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9369 DRM_INFO("applying lvds SSC disable quirk\n");
9370 }
9371
9372 /*
9373 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9374 * brightness value
9375 */
9376 static void quirk_invert_brightness(struct drm_device *dev)
9377 {
9378 struct drm_i915_private *dev_priv = dev->dev_private;
9379 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9380 DRM_INFO("applying inverted panel brightness quirk\n");
9381 }
9382
9383 struct intel_quirk {
9384 int device;
9385 int subsystem_vendor;
9386 int subsystem_device;
9387 void (*hook)(struct drm_device *dev);
9388 };
9389
9390 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9391 struct intel_dmi_quirk {
9392 void (*hook)(struct drm_device *dev);
9393 const struct dmi_system_id (*dmi_id_list)[];
9394 };
9395
9396 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9397 {
9398 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9399 return 1;
9400 }
9401
9402 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9403 {
9404 .dmi_id_list = &(const struct dmi_system_id[]) {
9405 {
9406 .callback = intel_dmi_reverse_brightness,
9407 .ident = "NCR Corporation",
9408 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9409 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9410 },
9411 },
9412 { } /* terminating entry */
9413 },
9414 .hook = quirk_invert_brightness,
9415 },
9416 };
9417
9418 static struct intel_quirk intel_quirks[] = {
9419 /* HP Mini needs pipe A force quirk (LP: #322104) */
9420 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9421
9422 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9423 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9424
9425 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9426 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9427
9428 /* 830/845 need to leave pipe A & dpll A up */
9429 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9430 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9431
9432 /* Lenovo U160 cannot use SSC on LVDS */
9433 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9434
9435 /* Sony Vaio Y cannot use SSC on LVDS */
9436 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9437
9438 /* Acer Aspire 5734Z must invert backlight brightness */
9439 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9440
9441 /* Acer/eMachines G725 */
9442 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9443
9444 /* Acer/eMachines e725 */
9445 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9446
9447 /* Acer/Packard Bell NCL20 */
9448 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9449
9450 /* Acer Aspire 4736Z */
9451 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9452 };
9453
9454 static void intel_init_quirks(struct drm_device *dev)
9455 {
9456 struct pci_dev *d = dev->pdev;
9457 int i;
9458
9459 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9460 struct intel_quirk *q = &intel_quirks[i];
9461
9462 if (d->device == q->device &&
9463 (d->subsystem_vendor == q->subsystem_vendor ||
9464 q->subsystem_vendor == PCI_ANY_ID) &&
9465 (d->subsystem_device == q->subsystem_device ||
9466 q->subsystem_device == PCI_ANY_ID))
9467 q->hook(dev);
9468 }
9469 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9470 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9471 intel_dmi_quirks[i].hook(dev);
9472 }
9473 }
9474
9475 /* Disable the VGA plane that we never use */
9476 static void i915_disable_vga(struct drm_device *dev)
9477 {
9478 struct drm_i915_private *dev_priv = dev->dev_private;
9479 u8 sr1;
9480 u32 vga_reg = i915_vgacntrl_reg(dev);
9481
9482 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9483 outb(SR01, VGA_SR_INDEX);
9484 sr1 = inb(VGA_SR_DATA);
9485 outb(sr1 | 1<<5, VGA_SR_DATA);
9486 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9487 udelay(300);
9488
9489 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9490 POSTING_READ(vga_reg);
9491 }
9492
9493 void intel_modeset_init_hw(struct drm_device *dev)
9494 {
9495 intel_init_power_well(dev);
9496
9497 intel_prepare_ddi(dev);
9498
9499 intel_init_clock_gating(dev);
9500
9501 mutex_lock(&dev->struct_mutex);
9502 intel_enable_gt_powersave(dev);
9503 mutex_unlock(&dev->struct_mutex);
9504 }
9505
9506 void intel_modeset_suspend_hw(struct drm_device *dev)
9507 {
9508 intel_suspend_hw(dev);
9509 }
9510
9511 void intel_modeset_init(struct drm_device *dev)
9512 {
9513 struct drm_i915_private *dev_priv = dev->dev_private;
9514 int i, j, ret;
9515
9516 drm_mode_config_init(dev);
9517
9518 dev->mode_config.min_width = 0;
9519 dev->mode_config.min_height = 0;
9520
9521 dev->mode_config.preferred_depth = 24;
9522 dev->mode_config.prefer_shadow = 1;
9523
9524 dev->mode_config.funcs = &intel_mode_funcs;
9525
9526 intel_init_quirks(dev);
9527
9528 intel_init_pm(dev);
9529
9530 if (INTEL_INFO(dev)->num_pipes == 0)
9531 return;
9532
9533 intel_init_display(dev);
9534
9535 if (IS_GEN2(dev)) {
9536 dev->mode_config.max_width = 2048;
9537 dev->mode_config.max_height = 2048;
9538 } else if (IS_GEN3(dev)) {
9539 dev->mode_config.max_width = 4096;
9540 dev->mode_config.max_height = 4096;
9541 } else {
9542 dev->mode_config.max_width = 8192;
9543 dev->mode_config.max_height = 8192;
9544 }
9545 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9546
9547 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9548 INTEL_INFO(dev)->num_pipes,
9549 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9550
9551 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9552 intel_crtc_init(dev, i);
9553 for (j = 0; j < dev_priv->num_plane; j++) {
9554 ret = intel_plane_init(dev, i, j);
9555 if (ret)
9556 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9557 pipe_name(i), sprite_name(i, j), ret);
9558 }
9559 }
9560
9561 intel_cpu_pll_init(dev);
9562 intel_shared_dpll_init(dev);
9563
9564 /* Just disable it once at startup */
9565 i915_disable_vga(dev);
9566 intel_setup_outputs(dev);
9567
9568 /* Just in case the BIOS is doing something questionable. */
9569 intel_disable_fbc(dev);
9570 }
9571
9572 static void
9573 intel_connector_break_all_links(struct intel_connector *connector)
9574 {
9575 connector->base.dpms = DRM_MODE_DPMS_OFF;
9576 connector->base.encoder = NULL;
9577 connector->encoder->connectors_active = false;
9578 connector->encoder->base.crtc = NULL;
9579 }
9580
9581 static void intel_enable_pipe_a(struct drm_device *dev)
9582 {
9583 struct intel_connector *connector;
9584 struct drm_connector *crt = NULL;
9585 struct intel_load_detect_pipe load_detect_temp;
9586
9587 /* We can't just switch on the pipe A, we need to set things up with a
9588 * proper mode and output configuration. As a gross hack, enable pipe A
9589 * by enabling the load detect pipe once. */
9590 list_for_each_entry(connector,
9591 &dev->mode_config.connector_list,
9592 base.head) {
9593 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9594 crt = &connector->base;
9595 break;
9596 }
9597 }
9598
9599 if (!crt)
9600 return;
9601
9602 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9603 intel_release_load_detect_pipe(crt, &load_detect_temp);
9604
9605
9606 }
9607
9608 static bool
9609 intel_check_plane_mapping(struct intel_crtc *crtc)
9610 {
9611 struct drm_device *dev = crtc->base.dev;
9612 struct drm_i915_private *dev_priv = dev->dev_private;
9613 u32 reg, val;
9614
9615 if (INTEL_INFO(dev)->num_pipes == 1)
9616 return true;
9617
9618 reg = DSPCNTR(!crtc->plane);
9619 val = I915_READ(reg);
9620
9621 if ((val & DISPLAY_PLANE_ENABLE) &&
9622 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9623 return false;
9624
9625 return true;
9626 }
9627
9628 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9629 {
9630 struct drm_device *dev = crtc->base.dev;
9631 struct drm_i915_private *dev_priv = dev->dev_private;
9632 u32 reg;
9633
9634 /* Clear any frame start delays used for debugging left by the BIOS */
9635 reg = PIPECONF(crtc->config.cpu_transcoder);
9636 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9637
9638 /* We need to sanitize the plane -> pipe mapping first because this will
9639 * disable the crtc (and hence change the state) if it is wrong. Note
9640 * that gen4+ has a fixed plane -> pipe mapping. */
9641 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9642 struct intel_connector *connector;
9643 bool plane;
9644
9645 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9646 crtc->base.base.id);
9647
9648 /* Pipe has the wrong plane attached and the plane is active.
9649 * Temporarily change the plane mapping and disable everything
9650 * ... */
9651 plane = crtc->plane;
9652 crtc->plane = !plane;
9653 dev_priv->display.crtc_disable(&crtc->base);
9654 crtc->plane = plane;
9655
9656 /* ... and break all links. */
9657 list_for_each_entry(connector, &dev->mode_config.connector_list,
9658 base.head) {
9659 if (connector->encoder->base.crtc != &crtc->base)
9660 continue;
9661
9662 intel_connector_break_all_links(connector);
9663 }
9664
9665 WARN_ON(crtc->active);
9666 crtc->base.enabled = false;
9667 }
9668
9669 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9670 crtc->pipe == PIPE_A && !crtc->active) {
9671 /* BIOS forgot to enable pipe A, this mostly happens after
9672 * resume. Force-enable the pipe to fix this, the update_dpms
9673 * call below we restore the pipe to the right state, but leave
9674 * the required bits on. */
9675 intel_enable_pipe_a(dev);
9676 }
9677
9678 /* Adjust the state of the output pipe according to whether we
9679 * have active connectors/encoders. */
9680 intel_crtc_update_dpms(&crtc->base);
9681
9682 if (crtc->active != crtc->base.enabled) {
9683 struct intel_encoder *encoder;
9684
9685 /* This can happen either due to bugs in the get_hw_state
9686 * functions or because the pipe is force-enabled due to the
9687 * pipe A quirk. */
9688 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9689 crtc->base.base.id,
9690 crtc->base.enabled ? "enabled" : "disabled",
9691 crtc->active ? "enabled" : "disabled");
9692
9693 crtc->base.enabled = crtc->active;
9694
9695 /* Because we only establish the connector -> encoder ->
9696 * crtc links if something is active, this means the
9697 * crtc is now deactivated. Break the links. connector
9698 * -> encoder links are only establish when things are
9699 * actually up, hence no need to break them. */
9700 WARN_ON(crtc->active);
9701
9702 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9703 WARN_ON(encoder->connectors_active);
9704 encoder->base.crtc = NULL;
9705 }
9706 }
9707 }
9708
9709 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9710 {
9711 struct intel_connector *connector;
9712 struct drm_device *dev = encoder->base.dev;
9713
9714 /* We need to check both for a crtc link (meaning that the
9715 * encoder is active and trying to read from a pipe) and the
9716 * pipe itself being active. */
9717 bool has_active_crtc = encoder->base.crtc &&
9718 to_intel_crtc(encoder->base.crtc)->active;
9719
9720 if (encoder->connectors_active && !has_active_crtc) {
9721 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9722 encoder->base.base.id,
9723 drm_get_encoder_name(&encoder->base));
9724
9725 /* Connector is active, but has no active pipe. This is
9726 * fallout from our resume register restoring. Disable
9727 * the encoder manually again. */
9728 if (encoder->base.crtc) {
9729 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9730 encoder->base.base.id,
9731 drm_get_encoder_name(&encoder->base));
9732 encoder->disable(encoder);
9733 }
9734
9735 /* Inconsistent output/port/pipe state happens presumably due to
9736 * a bug in one of the get_hw_state functions. Or someplace else
9737 * in our code, like the register restore mess on resume. Clamp
9738 * things to off as a safer default. */
9739 list_for_each_entry(connector,
9740 &dev->mode_config.connector_list,
9741 base.head) {
9742 if (connector->encoder != encoder)
9743 continue;
9744
9745 intel_connector_break_all_links(connector);
9746 }
9747 }
9748 /* Enabled encoders without active connectors will be fixed in
9749 * the crtc fixup. */
9750 }
9751
9752 void i915_redisable_vga(struct drm_device *dev)
9753 {
9754 struct drm_i915_private *dev_priv = dev->dev_private;
9755 u32 vga_reg = i915_vgacntrl_reg(dev);
9756
9757 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9758 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9759 i915_disable_vga(dev);
9760 }
9761 }
9762
9763 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9764 {
9765 struct drm_i915_private *dev_priv = dev->dev_private;
9766 enum pipe pipe;
9767 struct intel_crtc *crtc;
9768 struct intel_encoder *encoder;
9769 struct intel_connector *connector;
9770 int i;
9771
9772 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9773 base.head) {
9774 memset(&crtc->config, 0, sizeof(crtc->config));
9775
9776 crtc->active = dev_priv->display.get_pipe_config(crtc,
9777 &crtc->config);
9778
9779 crtc->base.enabled = crtc->active;
9780
9781 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9782 crtc->base.base.id,
9783 crtc->active ? "enabled" : "disabled");
9784 }
9785
9786 /* FIXME: Smash this into the new shared dpll infrastructure. */
9787 if (HAS_DDI(dev))
9788 intel_ddi_setup_hw_pll_state(dev);
9789
9790 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9791 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9792
9793 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9794 pll->active = 0;
9795 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9796 base.head) {
9797 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9798 pll->active++;
9799 }
9800 pll->refcount = pll->active;
9801
9802 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9803 pll->name, pll->refcount);
9804 }
9805
9806 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9807 base.head) {
9808 pipe = 0;
9809
9810 if (encoder->get_hw_state(encoder, &pipe)) {
9811 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9812 encoder->base.crtc = &crtc->base;
9813 if (encoder->get_config)
9814 encoder->get_config(encoder, &crtc->config);
9815 } else {
9816 encoder->base.crtc = NULL;
9817 }
9818
9819 encoder->connectors_active = false;
9820 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9821 encoder->base.base.id,
9822 drm_get_encoder_name(&encoder->base),
9823 encoder->base.crtc ? "enabled" : "disabled",
9824 pipe);
9825 }
9826
9827 list_for_each_entry(connector, &dev->mode_config.connector_list,
9828 base.head) {
9829 if (connector->get_hw_state(connector)) {
9830 connector->base.dpms = DRM_MODE_DPMS_ON;
9831 connector->encoder->connectors_active = true;
9832 connector->base.encoder = &connector->encoder->base;
9833 } else {
9834 connector->base.dpms = DRM_MODE_DPMS_OFF;
9835 connector->base.encoder = NULL;
9836 }
9837 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9838 connector->base.base.id,
9839 drm_get_connector_name(&connector->base),
9840 connector->base.encoder ? "enabled" : "disabled");
9841 }
9842 }
9843
9844 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9845 * and i915 state tracking structures. */
9846 void intel_modeset_setup_hw_state(struct drm_device *dev,
9847 bool force_restore)
9848 {
9849 struct drm_i915_private *dev_priv = dev->dev_private;
9850 enum pipe pipe;
9851 struct drm_plane *plane;
9852 struct intel_crtc *crtc;
9853 struct intel_encoder *encoder;
9854
9855 intel_modeset_readout_hw_state(dev);
9856
9857 /* HW state is read out, now we need to sanitize this mess. */
9858 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9859 base.head) {
9860 intel_sanitize_encoder(encoder);
9861 }
9862
9863 for_each_pipe(pipe) {
9864 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9865 intel_sanitize_crtc(crtc);
9866 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9867 }
9868
9869 if (force_restore) {
9870 /*
9871 * We need to use raw interfaces for restoring state to avoid
9872 * checking (bogus) intermediate states.
9873 */
9874 for_each_pipe(pipe) {
9875 struct drm_crtc *crtc =
9876 dev_priv->pipe_to_crtc_mapping[pipe];
9877
9878 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9879 crtc->fb);
9880 }
9881 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9882 intel_plane_restore(plane);
9883
9884 i915_redisable_vga(dev);
9885 } else {
9886 intel_modeset_update_staged_output_state(dev);
9887 }
9888
9889 intel_modeset_check_state(dev);
9890
9891 drm_mode_config_reset(dev);
9892 }
9893
9894 void intel_modeset_gem_init(struct drm_device *dev)
9895 {
9896 intel_modeset_init_hw(dev);
9897
9898 intel_setup_overlay(dev);
9899
9900 intel_modeset_setup_hw_state(dev, false);
9901 }
9902
9903 void intel_modeset_cleanup(struct drm_device *dev)
9904 {
9905 struct drm_i915_private *dev_priv = dev->dev_private;
9906 struct drm_crtc *crtc;
9907 struct intel_crtc *intel_crtc;
9908
9909 /*
9910 * Interrupts and polling as the first thing to avoid creating havoc.
9911 * Too much stuff here (turning of rps, connectors, ...) would
9912 * experience fancy races otherwise.
9913 */
9914 drm_irq_uninstall(dev);
9915 cancel_work_sync(&dev_priv->hotplug_work);
9916 /*
9917 * Due to the hpd irq storm handling the hotplug work can re-arm the
9918 * poll handlers. Hence disable polling after hpd handling is shut down.
9919 */
9920 drm_kms_helper_poll_fini(dev);
9921
9922 mutex_lock(&dev->struct_mutex);
9923
9924 intel_unregister_dsm_handler();
9925
9926 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9927 /* Skip inactive CRTCs */
9928 if (!crtc->fb)
9929 continue;
9930
9931 intel_crtc = to_intel_crtc(crtc);
9932 intel_increase_pllclock(crtc);
9933 }
9934
9935 intel_disable_fbc(dev);
9936
9937 intel_disable_gt_powersave(dev);
9938
9939 ironlake_teardown_rc6(dev);
9940
9941 mutex_unlock(&dev->struct_mutex);
9942
9943 /* flush any delayed tasks or pending work */
9944 flush_scheduled_work();
9945
9946 /* destroy backlight, if any, before the connectors */
9947 intel_panel_destroy_backlight(dev);
9948
9949 drm_mode_config_cleanup(dev);
9950
9951 intel_cleanup_overlay(dev);
9952 }
9953
9954 /*
9955 * Return which encoder is currently attached for connector.
9956 */
9957 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9958 {
9959 return &intel_attached_encoder(connector)->base;
9960 }
9961
9962 void intel_connector_attach_encoder(struct intel_connector *connector,
9963 struct intel_encoder *encoder)
9964 {
9965 connector->encoder = encoder;
9966 drm_mode_connector_attach_encoder(&connector->base,
9967 &encoder->base);
9968 }
9969
9970 /*
9971 * set vga decode state - true == enable VGA decode
9972 */
9973 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9974 {
9975 struct drm_i915_private *dev_priv = dev->dev_private;
9976 u16 gmch_ctrl;
9977
9978 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9979 if (state)
9980 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9981 else
9982 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9983 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9984 return 0;
9985 }
9986
9987 #ifdef CONFIG_DEBUG_FS
9988 #include <linux/seq_file.h>
9989
9990 struct intel_display_error_state {
9991
9992 u32 power_well_driver;
9993
9994 struct intel_cursor_error_state {
9995 u32 control;
9996 u32 position;
9997 u32 base;
9998 u32 size;
9999 } cursor[I915_MAX_PIPES];
10000
10001 struct intel_pipe_error_state {
10002 enum transcoder cpu_transcoder;
10003 u32 conf;
10004 u32 source;
10005
10006 u32 htotal;
10007 u32 hblank;
10008 u32 hsync;
10009 u32 vtotal;
10010 u32 vblank;
10011 u32 vsync;
10012 } pipe[I915_MAX_PIPES];
10013
10014 struct intel_plane_error_state {
10015 u32 control;
10016 u32 stride;
10017 u32 size;
10018 u32 pos;
10019 u32 addr;
10020 u32 surface;
10021 u32 tile_offset;
10022 } plane[I915_MAX_PIPES];
10023 };
10024
10025 struct intel_display_error_state *
10026 intel_display_capture_error_state(struct drm_device *dev)
10027 {
10028 drm_i915_private_t *dev_priv = dev->dev_private;
10029 struct intel_display_error_state *error;
10030 enum transcoder cpu_transcoder;
10031 int i;
10032
10033 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10034 if (error == NULL)
10035 return NULL;
10036
10037 if (HAS_POWER_WELL(dev))
10038 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10039
10040 for_each_pipe(i) {
10041 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10042 error->pipe[i].cpu_transcoder = cpu_transcoder;
10043
10044 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10045 error->cursor[i].control = I915_READ(CURCNTR(i));
10046 error->cursor[i].position = I915_READ(CURPOS(i));
10047 error->cursor[i].base = I915_READ(CURBASE(i));
10048 } else {
10049 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10050 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10051 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10052 }
10053
10054 error->plane[i].control = I915_READ(DSPCNTR(i));
10055 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10056 if (INTEL_INFO(dev)->gen <= 3) {
10057 error->plane[i].size = I915_READ(DSPSIZE(i));
10058 error->plane[i].pos = I915_READ(DSPPOS(i));
10059 }
10060 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10061 error->plane[i].addr = I915_READ(DSPADDR(i));
10062 if (INTEL_INFO(dev)->gen >= 4) {
10063 error->plane[i].surface = I915_READ(DSPSURF(i));
10064 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10065 }
10066
10067 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10068 error->pipe[i].source = I915_READ(PIPESRC(i));
10069 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10070 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10071 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10072 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10073 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10074 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10075 }
10076
10077 /* In the code above we read the registers without checking if the power
10078 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10079 * prevent the next I915_WRITE from detecting it and printing an error
10080 * message. */
10081 if (HAS_POWER_WELL(dev))
10082 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10083
10084 return error;
10085 }
10086
10087 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10088
10089 void
10090 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10091 struct drm_device *dev,
10092 struct intel_display_error_state *error)
10093 {
10094 int i;
10095
10096 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10097 if (HAS_POWER_WELL(dev))
10098 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10099 error->power_well_driver);
10100 for_each_pipe(i) {
10101 err_printf(m, "Pipe [%d]:\n", i);
10102 err_printf(m, " CPU transcoder: %c\n",
10103 transcoder_name(error->pipe[i].cpu_transcoder));
10104 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10105 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10106 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10107 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10108 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10109 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10110 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10111 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10112
10113 err_printf(m, "Plane [%d]:\n", i);
10114 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10115 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10116 if (INTEL_INFO(dev)->gen <= 3) {
10117 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10118 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10119 }
10120 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10121 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10122 if (INTEL_INFO(dev)->gen >= 4) {
10123 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10124 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10125 }
10126
10127 err_printf(m, "Cursor [%d]:\n", i);
10128 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10129 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10130 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10131 }
10132 }
10133 #endif
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