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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev,
124 struct drm_modeset_acquire_ctx *ctx);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126
127 struct intel_limit {
128 struct {
129 int min, max;
130 } dot, vco, n, m, m1, m2, p, p1;
131
132 struct {
133 int dot_limit;
134 int p2_slow, p2_fast;
135 } p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154 {
155 u32 val;
156 int divider;
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 }
170
171 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
172 const char *name, u32 reg)
173 {
174 if (dev_priv->hpll_freq == 0)
175 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
176
177 return vlv_get_cck_clock(dev_priv, name, reg,
178 dev_priv->hpll_freq);
179 }
180
181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 {
183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
184 return;
185
186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
187 CCK_CZ_CLOCK_CONTROL);
188
189 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
190 }
191
192 static inline u32 /* units of 100MHz */
193 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
194 const struct intel_crtc_state *pipe_config)
195 {
196 if (HAS_DDI(dev_priv))
197 return pipe_config->port_clock; /* SPLL */
198 else if (IS_GEN5(dev_priv))
199 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
200 else
201 return 270000;
202 }
203
204 static const struct intel_limit intel_limits_i8xx_dac = {
205 .dot = { .min = 25000, .max = 350000 },
206 .vco = { .min = 908000, .max = 1512000 },
207 .n = { .min = 2, .max = 16 },
208 .m = { .min = 96, .max = 140 },
209 .m1 = { .min = 18, .max = 26 },
210 .m2 = { .min = 6, .max = 16 },
211 .p = { .min = 4, .max = 128 },
212 .p1 = { .min = 2, .max = 33 },
213 .p2 = { .dot_limit = 165000,
214 .p2_slow = 4, .p2_fast = 2 },
215 };
216
217 static const struct intel_limit intel_limits_i8xx_dvo = {
218 .dot = { .min = 25000, .max = 350000 },
219 .vco = { .min = 908000, .max = 1512000 },
220 .n = { .min = 2, .max = 16 },
221 .m = { .min = 96, .max = 140 },
222 .m1 = { .min = 18, .max = 26 },
223 .m2 = { .min = 6, .max = 16 },
224 .p = { .min = 4, .max = 128 },
225 .p1 = { .min = 2, .max = 33 },
226 .p2 = { .dot_limit = 165000,
227 .p2_slow = 4, .p2_fast = 4 },
228 };
229
230 static const struct intel_limit intel_limits_i8xx_lvds = {
231 .dot = { .min = 25000, .max = 350000 },
232 .vco = { .min = 908000, .max = 1512000 },
233 .n = { .min = 2, .max = 16 },
234 .m = { .min = 96, .max = 140 },
235 .m1 = { .min = 18, .max = 26 },
236 .m2 = { .min = 6, .max = 16 },
237 .p = { .min = 4, .max = 128 },
238 .p1 = { .min = 1, .max = 6 },
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 14, .p2_fast = 7 },
241 };
242
243 static const struct intel_limit intel_limits_i9xx_sdvo = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1400000, .max = 2800000 },
246 .n = { .min = 1, .max = 6 },
247 .m = { .min = 70, .max = 120 },
248 .m1 = { .min = 8, .max = 18 },
249 .m2 = { .min = 3, .max = 7 },
250 .p = { .min = 5, .max = 80 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 200000,
253 .p2_slow = 10, .p2_fast = 5 },
254 };
255
256 static const struct intel_limit intel_limits_i9xx_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1400000, .max = 2800000 },
259 .n = { .min = 1, .max = 6 },
260 .m = { .min = 70, .max = 120 },
261 .m1 = { .min = 8, .max = 18 },
262 .m2 = { .min = 3, .max = 7 },
263 .p = { .min = 7, .max = 98 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 7 },
267 };
268
269
270 static const struct intel_limit intel_limits_g4x_sdvo = {
271 .dot = { .min = 25000, .max = 270000 },
272 .vco = { .min = 1750000, .max = 3500000},
273 .n = { .min = 1, .max = 4 },
274 .m = { .min = 104, .max = 138 },
275 .m1 = { .min = 17, .max = 23 },
276 .m2 = { .min = 5, .max = 11 },
277 .p = { .min = 10, .max = 30 },
278 .p1 = { .min = 1, .max = 3},
279 .p2 = { .dot_limit = 270000,
280 .p2_slow = 10,
281 .p2_fast = 10
282 },
283 };
284
285 static const struct intel_limit intel_limits_g4x_hdmi = {
286 .dot = { .min = 22000, .max = 400000 },
287 .vco = { .min = 1750000, .max = 3500000},
288 .n = { .min = 1, .max = 4 },
289 .m = { .min = 104, .max = 138 },
290 .m1 = { .min = 16, .max = 23 },
291 .m2 = { .min = 5, .max = 11 },
292 .p = { .min = 5, .max = 80 },
293 .p1 = { .min = 1, .max = 8},
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 10, .p2_fast = 5 },
296 };
297
298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
299 .dot = { .min = 20000, .max = 115000 },
300 .vco = { .min = 1750000, .max = 3500000 },
301 .n = { .min = 1, .max = 3 },
302 .m = { .min = 104, .max = 138 },
303 .m1 = { .min = 17, .max = 23 },
304 .m2 = { .min = 5, .max = 11 },
305 .p = { .min = 28, .max = 112 },
306 .p1 = { .min = 2, .max = 8 },
307 .p2 = { .dot_limit = 0,
308 .p2_slow = 14, .p2_fast = 14
309 },
310 };
311
312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
313 .dot = { .min = 80000, .max = 224000 },
314 .vco = { .min = 1750000, .max = 3500000 },
315 .n = { .min = 1, .max = 3 },
316 .m = { .min = 104, .max = 138 },
317 .m1 = { .min = 17, .max = 23 },
318 .m2 = { .min = 5, .max = 11 },
319 .p = { .min = 14, .max = 42 },
320 .p1 = { .min = 2, .max = 6 },
321 .p2 = { .dot_limit = 0,
322 .p2_slow = 7, .p2_fast = 7
323 },
324 };
325
326 static const struct intel_limit intel_limits_pineview_sdvo = {
327 .dot = { .min = 20000, .max = 400000},
328 .vco = { .min = 1700000, .max = 3500000 },
329 /* Pineview's Ncounter is a ring counter */
330 .n = { .min = 3, .max = 6 },
331 .m = { .min = 2, .max = 256 },
332 /* Pineview only has one combined m divider, which we treat as m2. */
333 .m1 = { .min = 0, .max = 0 },
334 .m2 = { .min = 0, .max = 254 },
335 .p = { .min = 5, .max = 80 },
336 .p1 = { .min = 1, .max = 8 },
337 .p2 = { .dot_limit = 200000,
338 .p2_slow = 10, .p2_fast = 5 },
339 };
340
341 static const struct intel_limit intel_limits_pineview_lvds = {
342 .dot = { .min = 20000, .max = 400000 },
343 .vco = { .min = 1700000, .max = 3500000 },
344 .n = { .min = 3, .max = 6 },
345 .m = { .min = 2, .max = 256 },
346 .m1 = { .min = 0, .max = 0 },
347 .m2 = { .min = 0, .max = 254 },
348 .p = { .min = 7, .max = 112 },
349 .p1 = { .min = 1, .max = 8 },
350 .p2 = { .dot_limit = 112000,
351 .p2_slow = 14, .p2_fast = 14 },
352 };
353
354 /* Ironlake / Sandybridge
355 *
356 * We calculate clock using (register_value + 2) for N/M1/M2, so here
357 * the range value for them is (actual_value - 2).
358 */
359 static const struct intel_limit intel_limits_ironlake_dac = {
360 .dot = { .min = 25000, .max = 350000 },
361 .vco = { .min = 1760000, .max = 3510000 },
362 .n = { .min = 1, .max = 5 },
363 .m = { .min = 79, .max = 127 },
364 .m1 = { .min = 12, .max = 22 },
365 .m2 = { .min = 5, .max = 9 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 225000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
373 .dot = { .min = 25000, .max = 350000 },
374 .vco = { .min = 1760000, .max = 3510000 },
375 .n = { .min = 1, .max = 3 },
376 .m = { .min = 79, .max = 118 },
377 .m1 = { .min = 12, .max = 22 },
378 .m2 = { .min = 5, .max = 9 },
379 .p = { .min = 28, .max = 112 },
380 .p1 = { .min = 2, .max = 8 },
381 .p2 = { .dot_limit = 225000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
386 .dot = { .min = 25000, .max = 350000 },
387 .vco = { .min = 1760000, .max = 3510000 },
388 .n = { .min = 1, .max = 3 },
389 .m = { .min = 79, .max = 127 },
390 .m1 = { .min = 12, .max = 22 },
391 .m2 = { .min = 5, .max = 9 },
392 .p = { .min = 14, .max = 56 },
393 .p1 = { .min = 2, .max = 8 },
394 .p2 = { .dot_limit = 225000,
395 .p2_slow = 7, .p2_fast = 7 },
396 };
397
398 /* LVDS 100mhz refclk limits. */
399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
400 .dot = { .min = 25000, .max = 350000 },
401 .vco = { .min = 1760000, .max = 3510000 },
402 .n = { .min = 1, .max = 2 },
403 .m = { .min = 79, .max = 126 },
404 .m1 = { .min = 12, .max = 22 },
405 .m2 = { .min = 5, .max = 9 },
406 .p = { .min = 28, .max = 112 },
407 .p1 = { .min = 2, .max = 8 },
408 .p2 = { .dot_limit = 225000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 3 },
416 .m = { .min = 79, .max = 126 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 14, .max = 42 },
420 .p1 = { .min = 2, .max = 6 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 7, .p2_fast = 7 },
423 };
424
425 static const struct intel_limit intel_limits_vlv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
433 .vco = { .min = 4000000, .max = 6000000 },
434 .n = { .min = 1, .max = 7 },
435 .m1 = { .min = 2, .max = 3 },
436 .m2 = { .min = 11, .max = 156 },
437 .p1 = { .min = 2, .max = 3 },
438 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
439 };
440
441 static const struct intel_limit intel_limits_chv = {
442 /*
443 * These are the data rate limits (measured in fast clocks)
444 * since those are the strictest limits we have. The fast
445 * clock and actual rate limits are more relaxed, so checking
446 * them would make no difference.
447 */
448 .dot = { .min = 25000 * 5, .max = 540000 * 5},
449 .vco = { .min = 4800000, .max = 6480000 },
450 .n = { .min = 1, .max = 1 },
451 .m1 = { .min = 2, .max = 2 },
452 .m2 = { .min = 24 << 22, .max = 175 << 22 },
453 .p1 = { .min = 2, .max = 4 },
454 .p2 = { .p2_slow = 1, .p2_fast = 14 },
455 };
456
457 static const struct intel_limit intel_limits_bxt = {
458 /* FIXME: find real dot limits */
459 .dot = { .min = 0, .max = INT_MAX },
460 .vco = { .min = 4800000, .max = 6700000 },
461 .n = { .min = 1, .max = 1 },
462 .m1 = { .min = 2, .max = 2 },
463 /* FIXME: find real m2 limits */
464 .m2 = { .min = 2 << 22, .max = 255 << 22 },
465 .p1 = { .min = 2, .max = 4 },
466 .p2 = { .p2_slow = 1, .p2_fast = 20 },
467 };
468
469 static bool
470 needs_modeset(struct drm_crtc_state *state)
471 {
472 return drm_atomic_crtc_needs_modeset(state);
473 }
474
475 /*
476 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
477 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
478 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
479 * The helpers' return value is the rate of the clock that is fed to the
480 * display engine's pipe which can be the above fast dot clock rate or a
481 * divided-down version of it.
482 */
483 /* m1 is reserved as 0 in Pineview, n is a ring counter */
484 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
485 {
486 clock->m = clock->m2 + 2;
487 clock->p = clock->p1 * clock->p2;
488 if (WARN_ON(clock->n == 0 || clock->p == 0))
489 return 0;
490 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
491 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
492
493 return clock->dot;
494 }
495
496 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
497 {
498 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
499 }
500
501 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
502 {
503 clock->m = i9xx_dpll_compute_m(clock);
504 clock->p = clock->p1 * clock->p2;
505 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
506 return 0;
507 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
508 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
509
510 return clock->dot;
511 }
512
513 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
514 {
515 clock->m = clock->m1 * clock->m2;
516 clock->p = clock->p1 * clock->p2;
517 if (WARN_ON(clock->n == 0 || clock->p == 0))
518 return 0;
519 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
520 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
521
522 return clock->dot / 5;
523 }
524
525 int chv_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = clock->m1 * clock->m2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
532 clock->n << 22);
533 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534
535 return clock->dot / 5;
536 }
537
538 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 /**
540 * Returns whether the given set of divisors are valid for a given refclk with
541 * the given connectors.
542 */
543
544 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
545 const struct intel_limit *limit,
546 const struct dpll *clock)
547 {
548 if (clock->n < limit->n.min || limit->n.max < clock->n)
549 INTELPllInvalid("n out of range\n");
550 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
551 INTELPllInvalid("p1 out of range\n");
552 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
553 INTELPllInvalid("m2 out of range\n");
554 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
555 INTELPllInvalid("m1 out of range\n");
556
557 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
558 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
561
562 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
563 !IS_GEN9_LP(dev_priv)) {
564 if (clock->p < limit->p.min || limit->p.max < clock->p)
565 INTELPllInvalid("p out of range\n");
566 if (clock->m < limit->m.min || limit->m.max < clock->m)
567 INTELPllInvalid("m out of range\n");
568 }
569
570 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
571 INTELPllInvalid("vco out of range\n");
572 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
573 * connector, etc., rather than just a single range.
574 */
575 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
576 INTELPllInvalid("dot out of range\n");
577
578 return true;
579 }
580
581 static int
582 i9xx_select_p2_div(const struct intel_limit *limit,
583 const struct intel_crtc_state *crtc_state,
584 int target)
585 {
586 struct drm_device *dev = crtc_state->base.crtc->dev;
587
588 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 /*
590 * For LVDS just rely on its current settings for dual-channel.
591 * We haven't figured out how to reliably set up different
592 * single/dual channel state, if we even can.
593 */
594 if (intel_is_dual_link_lvds(dev))
595 return limit->p2.p2_fast;
596 else
597 return limit->p2.p2_slow;
598 } else {
599 if (target < limit->p2.dot_limit)
600 return limit->p2.p2_slow;
601 else
602 return limit->p2.p2_fast;
603 }
604 }
605
606 /*
607 * Returns a set of divisors for the desired target clock with the given
608 * refclk, or FALSE. The returned values represent the clock equation:
609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
610 *
611 * Target and reference clocks are specified in kHz.
612 *
613 * If match_clock is provided, then best_clock P divider must match the P
614 * divider from @match_clock used for LVDS downclocking.
615 */
616 static bool
617 i9xx_find_best_dpll(const struct intel_limit *limit,
618 struct intel_crtc_state *crtc_state,
619 int target, int refclk, struct dpll *match_clock,
620 struct dpll *best_clock)
621 {
622 struct drm_device *dev = crtc_state->base.crtc->dev;
623 struct dpll clock;
624 int err = target;
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_calc_dpll_params(refclk, &clock);
643 if (!intel_PLL_is_valid(to_i915(dev),
644 limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 pnv_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 for (clock.n = limit->n.min;
693 clock.n <= limit->n.max; clock.n++) {
694 for (clock.p1 = limit->p1.min;
695 clock.p1 <= limit->p1.max; clock.p1++) {
696 int this_err;
697
698 pnv_calc_dpll_params(refclk, &clock);
699 if (!intel_PLL_is_valid(to_i915(dev),
700 limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 /*
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724 *
725 * Target and reference clocks are specified in kHz.
726 *
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
729 */
730 static bool
731 g4x_find_best_dpll(const struct intel_limit *limit,
732 struct intel_crtc_state *crtc_state,
733 int target, int refclk, struct dpll *match_clock,
734 struct dpll *best_clock)
735 {
736 struct drm_device *dev = crtc_state->base.crtc->dev;
737 struct dpll clock;
738 int max_n;
739 bool found = false;
740 /* approximately equals target * 0.00585 */
741 int err_most = (target >> 8) + (target >> 9);
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_calc_dpll_params(refclk, &clock);
760 if (!intel_PLL_is_valid(to_i915(dev),
761 limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const struct dpll *calculated_clock,
785 const struct dpll *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(to_i915(dev))) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 /*
820 * Returns a set of divisors for the desired target clock with the given
821 * refclk, or FALSE. The returned values represent the clock equation:
822 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 */
824 static bool
825 vlv_find_best_dpll(const struct intel_limit *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, struct dpll *match_clock,
828 struct dpll *best_clock)
829 {
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct dpll clock;
833 unsigned int bestppm = 1000000;
834 /* min update 19.2 MHz */
835 int max_n = min(limit->n.max, refclk / 19200);
836 bool found = false;
837
838 target *= 5; /* fast clock */
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
844 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
845 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
846 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
847 clock.p = clock.p1 * clock.p2;
848 /* based on hardware requirement, prefer bigger m1,m2 values */
849 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
850 unsigned int ppm;
851
852 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
853 refclk * clock.m1);
854
855 vlv_calc_dpll_params(refclk, &clock);
856
857 if (!intel_PLL_is_valid(to_i915(dev),
858 limit,
859 &clock))
860 continue;
861
862 if (!vlv_PLL_is_optimal(dev, target,
863 &clock,
864 best_clock,
865 bestppm, &ppm))
866 continue;
867
868 *best_clock = clock;
869 bestppm = ppm;
870 found = true;
871 }
872 }
873 }
874 }
875
876 return found;
877 }
878
879 /*
880 * Returns a set of divisors for the desired target clock with the given
881 * refclk, or FALSE. The returned values represent the clock equation:
882 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
883 */
884 static bool
885 chv_find_best_dpll(const struct intel_limit *limit,
886 struct intel_crtc_state *crtc_state,
887 int target, int refclk, struct dpll *match_clock,
888 struct dpll *best_clock)
889 {
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
891 struct drm_device *dev = crtc->base.dev;
892 unsigned int best_error_ppm;
893 struct dpll clock;
894 uint64_t m2;
895 int found = false;
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 best_error_ppm = 1000000;
899
900 /*
901 * Based on hardware doc, the n always set to 1, and m1 always
902 * set to 2. If requires to support 200Mhz refclk, we need to
903 * revisit this because n may not 1 anymore.
904 */
905 clock.n = 1, clock.m1 = 2;
906 target *= 5; /* fast clock */
907
908 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
909 for (clock.p2 = limit->p2.p2_fast;
910 clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 unsigned int error_ppm;
913
914 clock.p = clock.p1 * clock.p2;
915
916 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
917 clock.n) << 22, refclk * clock.m1);
918
919 if (m2 > INT_MAX/clock.m1)
920 continue;
921
922 clock.m2 = m2;
923
924 chv_calc_dpll_params(refclk, &clock);
925
926 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
927 continue;
928
929 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
930 best_error_ppm, &error_ppm))
931 continue;
932
933 *best_clock = clock;
934 best_error_ppm = error_ppm;
935 found = true;
936 }
937 }
938
939 return found;
940 }
941
942 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
943 struct dpll *best_clock)
944 {
945 int refclk = 100000;
946 const struct intel_limit *limit = &intel_limits_bxt;
947
948 return chv_find_best_dpll(limit, crtc_state,
949 target_clock, refclk, NULL, best_clock);
950 }
951
952 bool intel_crtc_active(struct intel_crtc *crtc)
953 {
954 /* Be paranoid as we can arrive here with only partial
955 * state retrieved from the hardware during setup.
956 *
957 * We can ditch the adjusted_mode.crtc_clock check as soon
958 * as Haswell has gained clock readout/fastboot support.
959 *
960 * We can ditch the crtc->primary->fb check as soon as we can
961 * properly reconstruct framebuffers.
962 *
963 * FIXME: The intel_crtc->active here should be switched to
964 * crtc->state->active once we have proper CRTC states wired up
965 * for atomic.
966 */
967 return crtc->active && crtc->base.primary->state->fb &&
968 crtc->config->base.adjusted_mode.crtc_clock;
969 }
970
971 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
972 enum pipe pipe)
973 {
974 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
975
976 return crtc->config->cpu_transcoder;
977 }
978
979 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
980 {
981 i915_reg_t reg = PIPEDSL(pipe);
982 u32 line1, line2;
983 u32 line_mask;
984
985 if (IS_GEN2(dev_priv))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 line1 = I915_READ(reg) & line_mask;
991 msleep(5);
992 line2 = I915_READ(reg) & line_mask;
993
994 return line1 == line2;
995 }
996
997 /*
998 * intel_wait_for_pipe_off - wait for pipe to turn off
999 * @crtc: crtc whose pipe to wait for
1000 *
1001 * After disabling a pipe, we can't wait for vblank in the usual way,
1002 * spinning on the vblank interrupt status bit, since we won't actually
1003 * see an interrupt when the pipe is disabled.
1004 *
1005 * On Gen4 and above:
1006 * wait for the pipe register state bit to turn off
1007 *
1008 * Otherwise:
1009 * wait for the display line value to settle (it usually
1010 * ends up stopping at the start of the next frame).
1011 *
1012 */
1013 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 {
1015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1016 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1017 enum pipe pipe = crtc->pipe;
1018
1019 if (INTEL_GEN(dev_priv) >= 4) {
1020 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021
1022 /* Wait for the Pipe State to go off */
1023 if (intel_wait_for_register(dev_priv,
1024 reg, I965_PIPECONF_ACTIVE, 0,
1025 100))
1026 WARN(1, "pipe_off wait timed out\n");
1027 } else {
1028 /* Wait for the display line to settle */
1029 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 }
1032 }
1033
1034 /* Only for pre-ILK configs */
1035 void assert_pll(struct drm_i915_private *dev_priv,
1036 enum pipe pipe, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 val = I915_READ(DPLL(pipe));
1042 cur_state = !!(val & DPLL_VCO_ENABLE);
1043 I915_STATE_WARN(cur_state != state,
1044 "PLL state assertion failure (expected %s, current %s)\n",
1045 onoff(state), onoff(cur_state));
1046 }
1047
1048 /* XXX: the dsi pll is shared between MIPI DSI ports */
1049 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1050 {
1051 u32 val;
1052 bool cur_state;
1053
1054 mutex_lock(&dev_priv->sb_lock);
1055 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1056 mutex_unlock(&dev_priv->sb_lock);
1057
1058 cur_state = val & DSI_PLL_VCO_EN;
1059 I915_STATE_WARN(cur_state != state,
1060 "DSI PLL state assertion failure (expected %s, current %s)\n",
1061 onoff(state), onoff(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 bool cur_state;
1068 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1069 pipe);
1070
1071 if (HAS_DDI(dev_priv)) {
1072 /* DDI does not have a specific FDI_TX register */
1073 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1074 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075 } else {
1076 u32 val = I915_READ(FDI_TX_CTL(pipe));
1077 cur_state = !!(val & FDI_TX_ENABLE);
1078 }
1079 I915_STATE_WARN(cur_state != state,
1080 "FDI TX state assertion failure (expected %s, current %s)\n",
1081 onoff(state), onoff(cur_state));
1082 }
1083 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1084 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085
1086 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 u32 val;
1090 bool cur_state;
1091
1092 val = I915_READ(FDI_RX_CTL(pipe));
1093 cur_state = !!(val & FDI_RX_ENABLE);
1094 I915_STATE_WARN(cur_state != state,
1095 "FDI RX state assertion failure (expected %s, current %s)\n",
1096 onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1099 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100
1101 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1102 enum pipe pipe)
1103 {
1104 u32 val;
1105
1106 /* ILK FDI PLL is always enabled */
1107 if (IS_GEN5(dev_priv))
1108 return;
1109
1110 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1111 if (HAS_DDI(dev_priv))
1112 return;
1113
1114 val = I915_READ(FDI_TX_CTL(pipe));
1115 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1116 }
1117
1118 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1123
1124 val = I915_READ(FDI_RX_CTL(pipe));
1125 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1126 I915_STATE_WARN(cur_state != state,
1127 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1128 onoff(state), onoff(cur_state));
1129 }
1130
1131 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133 i915_reg_t pp_reg;
1134 u32 val;
1135 enum pipe panel_pipe = PIPE_A;
1136 bool locked = true;
1137
1138 if (WARN_ON(HAS_DDI(dev_priv)))
1139 return;
1140
1141 if (HAS_PCH_SPLIT(dev_priv)) {
1142 u32 port_sel;
1143
1144 pp_reg = PP_CONTROL(0);
1145 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146
1147 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1148 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1149 panel_pipe = PIPE_B;
1150 /* XXX: else fix for eDP */
1151 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152 /* presumably write lock depends on pipe, not port select */
1153 pp_reg = PP_CONTROL(pipe);
1154 panel_pipe = pipe;
1155 } else {
1156 pp_reg = PP_CONTROL(0);
1157 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1158 panel_pipe = PIPE_B;
1159 }
1160
1161 val = I915_READ(pp_reg);
1162 if (!(val & PANEL_POWER_ON) ||
1163 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1164 locked = false;
1165
1166 I915_STATE_WARN(panel_pipe == pipe && locked,
1167 "panel assertion failure, pipe %c regs locked\n",
1168 pipe_name(pipe));
1169 }
1170
1171 static void assert_cursor(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1173 {
1174 bool cur_state;
1175
1176 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1177 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178 else
1179 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180
1181 I915_STATE_WARN(cur_state != state,
1182 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1183 pipe_name(pipe), onoff(state), onoff(cur_state));
1184 }
1185 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1186 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187
1188 void assert_pipe(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 bool cur_state;
1192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 pipe);
1194 enum intel_display_power_domain power_domain;
1195
1196 /* we keep both pipes enabled on 830 */
1197 if (IS_I830(dev_priv))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552 int i;
1553
1554 assert_pipe_disabled(dev_priv, crtc->pipe);
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 /* Enable DVO 2x clock on both PLLs if necessary */
1561 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562 /*
1563 * It appears to be important that we don't enable this
1564 * for the current pipe before otherwise configuring the
1565 * PLL. No idea how this should be handled if multiple
1566 * DVO outputs are enabled simultaneosly.
1567 */
1568 dpll |= DPLL_DVO_2X_MODE;
1569 I915_WRITE(DPLL(!crtc->pipe),
1570 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1571 }
1572
1573 /*
1574 * Apparently we need to have VGA mode enabled prior to changing
1575 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1576 * dividers, even though the register value does change.
1577 */
1578 I915_WRITE(reg, 0);
1579
1580 I915_WRITE(reg, dpll);
1581
1582 /* Wait for the clocks to stabilize. */
1583 POSTING_READ(reg);
1584 udelay(150);
1585
1586 if (INTEL_GEN(dev_priv) >= 4) {
1587 I915_WRITE(DPLL_MD(crtc->pipe),
1588 crtc->config->dpll_hw_state.dpll_md);
1589 } else {
1590 /* The pixel multiplier can only be updated once the
1591 * DPLL is enabled and the clocks are stable.
1592 *
1593 * So write it again.
1594 */
1595 I915_WRITE(reg, dpll);
1596 }
1597
1598 /* We do this three times for luck */
1599 for (i = 0; i < 3; i++) {
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150); /* wait for warmup */
1603 }
1604 }
1605
1606 /**
1607 * i9xx_disable_pll - disable a PLL
1608 * @dev_priv: i915 private structure
1609 * @pipe: pipe PLL to disable
1610 *
1611 * Disable the PLL for @pipe, making sure the pipe is off first.
1612 *
1613 * Note! This is for pre-ILK only.
1614 */
1615 static void i9xx_disable_pll(struct intel_crtc *crtc)
1616 {
1617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618 enum pipe pipe = crtc->pipe;
1619
1620 /* Disable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev_priv) &&
1622 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1623 !intel_num_dvo_pipes(dev_priv)) {
1624 I915_WRITE(DPLL(PIPE_B),
1625 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1626 I915_WRITE(DPLL(PIPE_A),
1627 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1628 }
1629
1630 /* Don't disable pipe or pipe PLLs if needed */
1631 if (IS_I830(dev_priv))
1632 return;
1633
1634 /* Make sure the pipe isn't still relying on us */
1635 assert_pipe_disabled(dev_priv, pipe);
1636
1637 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1638 POSTING_READ(DPLL(pipe));
1639 }
1640
1641 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1642 {
1643 u32 val;
1644
1645 /* Make sure the pipe isn't still relying on us */
1646 assert_pipe_disabled(dev_priv, pipe);
1647
1648 val = DPLL_INTEGRATED_REF_CLK_VLV |
1649 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1650 if (pipe != PIPE_A)
1651 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1652
1653 I915_WRITE(DPLL(pipe), val);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660 u32 val;
1661
1662 /* Make sure the pipe isn't still relying on us */
1663 assert_pipe_disabled(dev_priv, pipe);
1664
1665 val = DPLL_SSC_REF_CLK_CHV |
1666 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1667 if (pipe != PIPE_A)
1668 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1669
1670 I915_WRITE(DPLL(pipe), val);
1671 POSTING_READ(DPLL(pipe));
1672
1673 mutex_lock(&dev_priv->sb_lock);
1674
1675 /* Disable 10bit clock to display controller */
1676 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1677 val &= ~DPIO_DCLKP_EN;
1678 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1679
1680 mutex_unlock(&dev_priv->sb_lock);
1681 }
1682
1683 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1684 struct intel_digital_port *dport,
1685 unsigned int expected_mask)
1686 {
1687 u32 port_mask;
1688 i915_reg_t dpll_reg;
1689
1690 switch (dport->port) {
1691 case PORT_B:
1692 port_mask = DPLL_PORTB_READY_MASK;
1693 dpll_reg = DPLL(0);
1694 break;
1695 case PORT_C:
1696 port_mask = DPLL_PORTC_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 expected_mask <<= 4;
1699 break;
1700 case PORT_D:
1701 port_mask = DPLL_PORTD_READY_MASK;
1702 dpll_reg = DPIO_PHY_STATUS;
1703 break;
1704 default:
1705 BUG();
1706 }
1707
1708 if (intel_wait_for_register(dev_priv,
1709 dpll_reg, port_mask, expected_mask,
1710 1000))
1711 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1712 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1713 }
1714
1715 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1716 enum pipe pipe)
1717 {
1718 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1719 pipe);
1720 i915_reg_t reg;
1721 uint32_t val, pipeconf_val;
1722
1723 /* Make sure PCH DPLL is enabled */
1724 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, pipe);
1728 assert_fdi_rx_enabled(dev_priv, pipe);
1729
1730 if (HAS_PCH_CPT(dev_priv)) {
1731 /* Workaround: Set the timing override bit before enabling the
1732 * pch transcoder. */
1733 reg = TRANS_CHICKEN2(pipe);
1734 val = I915_READ(reg);
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(reg, val);
1737 }
1738
1739 reg = PCH_TRANSCONF(pipe);
1740 val = I915_READ(reg);
1741 pipeconf_val = I915_READ(PIPECONF(pipe));
1742
1743 if (HAS_PCH_IBX(dev_priv)) {
1744 /*
1745 * Make the BPC in transcoder be consistent with
1746 * that in pipeconf reg. For HDMI we must use 8bpc
1747 * here for both 8bpc and 12bpc.
1748 */
1749 val &= ~PIPECONF_BPC_MASK;
1750 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1751 val |= PIPECONF_8BPC;
1752 else
1753 val |= pipeconf_val & PIPECONF_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv) &&
1759 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else
1764 val |= TRANS_PROGRESSIVE;
1765
1766 I915_WRITE(reg, val | TRANS_ENABLE);
1767 if (intel_wait_for_register(dev_priv,
1768 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1769 100))
1770 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1771 }
1772
1773 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 enum transcoder cpu_transcoder)
1775 {
1776 u32 val, pipeconf_val;
1777
1778 /* FDI must be feeding us bits for PCH ports */
1779 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1780 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1781
1782 /* Workaround: set timing override bit. */
1783 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1785 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786
1787 val = TRANS_ENABLE;
1788 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1789
1790 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1791 PIPECONF_INTERLACED_ILK)
1792 val |= TRANS_INTERLACED;
1793 else
1794 val |= TRANS_PROGRESSIVE;
1795
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 if (intel_wait_for_register(dev_priv,
1798 LPT_TRANSCONF,
1799 TRANS_STATE_ENABLE,
1800 TRANS_STATE_ENABLE,
1801 100))
1802 DRM_ERROR("Failed to enable PCH transcoder\n");
1803 }
1804
1805 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 i915_reg_t reg;
1809 uint32_t val;
1810
1811 /* FDI relies on the transcoder */
1812 assert_fdi_tx_disabled(dev_priv, pipe);
1813 assert_fdi_rx_disabled(dev_priv, pipe);
1814
1815 /* Ports must be off as well */
1816 assert_pch_ports_disabled(dev_priv, pipe);
1817
1818 reg = PCH_TRANSCONF(pipe);
1819 val = I915_READ(reg);
1820 val &= ~TRANS_ENABLE;
1821 I915_WRITE(reg, val);
1822 /* wait for PCH transcoder off, transcoder state */
1823 if (intel_wait_for_register(dev_priv,
1824 reg, TRANS_STATE_ENABLE, 0,
1825 50))
1826 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1827
1828 if (HAS_PCH_CPT(dev_priv)) {
1829 /* Workaround: Clear the timing override chicken bit again. */
1830 reg = TRANS_CHICKEN2(pipe);
1831 val = I915_READ(reg);
1832 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1833 I915_WRITE(reg, val);
1834 }
1835 }
1836
1837 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1838 {
1839 u32 val;
1840
1841 val = I915_READ(LPT_TRANSCONF);
1842 val &= ~TRANS_ENABLE;
1843 I915_WRITE(LPT_TRANSCONF, val);
1844 /* wait for PCH transcoder off, transcoder state */
1845 if (intel_wait_for_register(dev_priv,
1846 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1847 50))
1848 DRM_ERROR("Failed to disable PCH transcoder\n");
1849
1850 /* Workaround: clear timing override bit. */
1851 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1852 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1853 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1854 }
1855
1856 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1857 {
1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859
1860 WARN_ON(!crtc->config->has_pch_encoder);
1861
1862 if (HAS_PCH_LPT(dev_priv))
1863 return TRANSCODER_A;
1864 else
1865 return (enum transcoder) crtc->pipe;
1866 }
1867
1868 /**
1869 * intel_enable_pipe - enable a pipe, asserting requirements
1870 * @crtc: crtc responsible for the pipe
1871 *
1872 * Enable @crtc's pipe, making sure that various hardware specific requirements
1873 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1874 */
1875 static void intel_enable_pipe(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = to_i915(dev);
1879 enum pipe pipe = crtc->pipe;
1880 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1881 i915_reg_t reg;
1882 u32 val;
1883
1884 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1885
1886 assert_planes_disabled(dev_priv, pipe);
1887 assert_cursor_disabled(dev_priv, pipe);
1888 assert_sprites_disabled(dev_priv, pipe);
1889
1890 /*
1891 * A pipe without a PLL won't actually be able to drive bits from
1892 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1893 * need the check.
1894 */
1895 if (HAS_GMCH_DISPLAY(dev_priv)) {
1896 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1897 assert_dsi_pll_enabled(dev_priv);
1898 else
1899 assert_pll_enabled(dev_priv, pipe);
1900 } else {
1901 if (crtc->config->has_pch_encoder) {
1902 /* if driving the PCH, we need FDI enabled */
1903 assert_fdi_rx_pll_enabled(dev_priv,
1904 (enum pipe) intel_crtc_pch_transcoder(crtc));
1905 assert_fdi_tx_pll_enabled(dev_priv,
1906 (enum pipe) cpu_transcoder);
1907 }
1908 /* FIXME: assert CPU port conditions for SNB+ */
1909 }
1910
1911 reg = PIPECONF(cpu_transcoder);
1912 val = I915_READ(reg);
1913 if (val & PIPECONF_ENABLE) {
1914 /* we keep both pipes enabled on 830 */
1915 WARN_ON(!IS_I830(dev_priv));
1916 return;
1917 }
1918
1919 I915_WRITE(reg, val | PIPECONF_ENABLE);
1920 POSTING_READ(reg);
1921
1922 /*
1923 * Until the pipe starts DSL will read as 0, which would cause
1924 * an apparent vblank timestamp jump, which messes up also the
1925 * frame count when it's derived from the timestamps. So let's
1926 * wait for the pipe to start properly before we call
1927 * drm_crtc_vblank_on()
1928 */
1929 if (dev->max_vblank_count == 0 &&
1930 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1931 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1932 }
1933
1934 /**
1935 * intel_disable_pipe - disable a pipe, asserting requirements
1936 * @crtc: crtc whose pipes is to be disabled
1937 *
1938 * Disable the pipe of @crtc, making sure that various hardware
1939 * specific requirements are met, if applicable, e.g. plane
1940 * disabled, panel fitter off, etc.
1941 *
1942 * Will wait until the pipe has shut down before returning.
1943 */
1944 static void intel_disable_pipe(struct intel_crtc *crtc)
1945 {
1946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1948 enum pipe pipe = crtc->pipe;
1949 i915_reg_t reg;
1950 u32 val;
1951
1952 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1953
1954 /*
1955 * Make sure planes won't keep trying to pump pixels to us,
1956 * or we might hang the display.
1957 */
1958 assert_planes_disabled(dev_priv, pipe);
1959 assert_cursor_disabled(dev_priv, pipe);
1960 assert_sprites_disabled(dev_priv, pipe);
1961
1962 reg = PIPECONF(cpu_transcoder);
1963 val = I915_READ(reg);
1964 if ((val & PIPECONF_ENABLE) == 0)
1965 return;
1966
1967 /*
1968 * Double wide has implications for planes
1969 * so best keep it disabled when not needed.
1970 */
1971 if (crtc->config->double_wide)
1972 val &= ~PIPECONF_DOUBLE_WIDE;
1973
1974 /* Don't disable pipe or pipe PLLs if needed */
1975 if (!IS_I830(dev_priv))
1976 val &= ~PIPECONF_ENABLE;
1977
1978 I915_WRITE(reg, val);
1979 if ((val & PIPECONF_ENABLE) == 0)
1980 intel_wait_for_pipe_off(crtc);
1981 }
1982
1983 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1984 {
1985 return IS_GEN2(dev_priv) ? 2048 : 4096;
1986 }
1987
1988 static unsigned int
1989 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1990 {
1991 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1992 unsigned int cpp = fb->format->cpp[plane];
1993
1994 switch (fb->modifier) {
1995 case DRM_FORMAT_MOD_LINEAR:
1996 return cpp;
1997 case I915_FORMAT_MOD_X_TILED:
1998 if (IS_GEN2(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Y_TILED:
2003 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Yf_TILED:
2008 switch (cpp) {
2009 case 1:
2010 return 64;
2011 case 2:
2012 case 4:
2013 return 128;
2014 case 8:
2015 case 16:
2016 return 256;
2017 default:
2018 MISSING_CASE(cpp);
2019 return cpp;
2020 }
2021 break;
2022 default:
2023 MISSING_CASE(fb->modifier);
2024 return cpp;
2025 }
2026 }
2027
2028 static unsigned int
2029 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2030 {
2031 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2032 return 1;
2033 else
2034 return intel_tile_size(to_i915(fb->dev)) /
2035 intel_tile_width_bytes(fb, plane);
2036 }
2037
2038 /* Return the tile dimensions in pixel units */
2039 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2040 unsigned int *tile_width,
2041 unsigned int *tile_height)
2042 {
2043 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2044 unsigned int cpp = fb->format->cpp[plane];
2045
2046 *tile_width = tile_width_bytes / cpp;
2047 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2048 }
2049
2050 unsigned int
2051 intel_fb_align_height(const struct drm_framebuffer *fb,
2052 int plane, unsigned int height)
2053 {
2054 unsigned int tile_height = intel_tile_height(fb, plane);
2055
2056 return ALIGN(height, tile_height);
2057 }
2058
2059 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2060 {
2061 unsigned int size = 0;
2062 int i;
2063
2064 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2065 size += rot_info->plane[i].width * rot_info->plane[i].height;
2066
2067 return size;
2068 }
2069
2070 static void
2071 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2072 const struct drm_framebuffer *fb,
2073 unsigned int rotation)
2074 {
2075 view->type = I915_GGTT_VIEW_NORMAL;
2076 if (drm_rotation_90_or_270(rotation)) {
2077 view->type = I915_GGTT_VIEW_ROTATED;
2078 view->rotated = to_intel_framebuffer(fb)->rot_info;
2079 }
2080 }
2081
2082 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2083 {
2084 if (IS_I830(dev_priv))
2085 return 16 * 1024;
2086 else if (IS_I85X(dev_priv))
2087 return 256;
2088 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2089 return 32;
2090 else
2091 return 4 * 1024;
2092 }
2093
2094 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2095 {
2096 if (INTEL_INFO(dev_priv)->gen >= 9)
2097 return 256 * 1024;
2098 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2099 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2100 return 128 * 1024;
2101 else if (INTEL_INFO(dev_priv)->gen >= 4)
2102 return 4 * 1024;
2103 else
2104 return 0;
2105 }
2106
2107 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2108 int plane)
2109 {
2110 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2111
2112 /* AUX_DIST needs only 4K alignment */
2113 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2114 return 4096;
2115
2116 switch (fb->modifier) {
2117 case DRM_FORMAT_MOD_LINEAR:
2118 return intel_linear_alignment(dev_priv);
2119 case I915_FORMAT_MOD_X_TILED:
2120 if (INTEL_GEN(dev_priv) >= 9)
2121 return 256 * 1024;
2122 return 0;
2123 case I915_FORMAT_MOD_Y_TILED:
2124 case I915_FORMAT_MOD_Yf_TILED:
2125 return 1 * 1024 * 1024;
2126 default:
2127 MISSING_CASE(fb->modifier);
2128 return 0;
2129 }
2130 }
2131
2132 struct i915_vma *
2133 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2134 {
2135 struct drm_device *dev = fb->dev;
2136 struct drm_i915_private *dev_priv = to_i915(dev);
2137 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2138 struct i915_ggtt_view view;
2139 struct i915_vma *vma;
2140 u32 alignment;
2141
2142 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2143
2144 alignment = intel_surf_alignment(fb, 0);
2145
2146 intel_fill_fb_ggtt_view(&view, fb, rotation);
2147
2148 /* Note that the w/a also requires 64 PTE of padding following the
2149 * bo. We currently fill all unused PTE with the shadow page and so
2150 * we should always have valid PTE following the scanout preventing
2151 * the VT-d warning.
2152 */
2153 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2154 alignment = 256 * 1024;
2155
2156 /*
2157 * Global gtt pte registers are special registers which actually forward
2158 * writes to a chunk of system memory. Which means that there is no risk
2159 * that the register values disappear as soon as we call
2160 * intel_runtime_pm_put(), so it is correct to wrap only the
2161 * pin/unpin/fence and not more.
2162 */
2163 intel_runtime_pm_get(dev_priv);
2164
2165 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2166 if (IS_ERR(vma))
2167 goto err;
2168
2169 if (i915_vma_is_map_and_fenceable(vma)) {
2170 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2171 * fence, whereas 965+ only requires a fence if using
2172 * framebuffer compression. For simplicity, we always, when
2173 * possible, install a fence as the cost is not that onerous.
2174 *
2175 * If we fail to fence the tiled scanout, then either the
2176 * modeset will reject the change (which is highly unlikely as
2177 * the affected systems, all but one, do not have unmappable
2178 * space) or we will not be able to enable full powersaving
2179 * techniques (also likely not to apply due to various limits
2180 * FBC and the like impose on the size of the buffer, which
2181 * presumably we violated anyway with this unmappable buffer).
2182 * Anyway, it is presumably better to stumble onwards with
2183 * something and try to run the system in a "less than optimal"
2184 * mode that matches the user configuration.
2185 */
2186 if (i915_vma_get_fence(vma) == 0)
2187 i915_vma_pin_fence(vma);
2188 }
2189
2190 i915_vma_get(vma);
2191 err:
2192 intel_runtime_pm_put(dev_priv);
2193 return vma;
2194 }
2195
2196 void intel_unpin_fb_vma(struct i915_vma *vma)
2197 {
2198 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2199
2200 i915_vma_unpin_fence(vma);
2201 i915_gem_object_unpin_from_display_plane(vma);
2202 i915_vma_put(vma);
2203 }
2204
2205 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2206 unsigned int rotation)
2207 {
2208 if (drm_rotation_90_or_270(rotation))
2209 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2210 else
2211 return fb->pitches[plane];
2212 }
2213
2214 /*
2215 * Convert the x/y offsets into a linear offset.
2216 * Only valid with 0/180 degree rotation, which is fine since linear
2217 * offset is only used with linear buffers on pre-hsw and tiled buffers
2218 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2219 */
2220 u32 intel_fb_xy_to_linear(int x, int y,
2221 const struct intel_plane_state *state,
2222 int plane)
2223 {
2224 const struct drm_framebuffer *fb = state->base.fb;
2225 unsigned int cpp = fb->format->cpp[plane];
2226 unsigned int pitch = fb->pitches[plane];
2227
2228 return y * pitch + x * cpp;
2229 }
2230
2231 /*
2232 * Add the x/y offsets derived from fb->offsets[] to the user
2233 * specified plane src x/y offsets. The resulting x/y offsets
2234 * specify the start of scanout from the beginning of the gtt mapping.
2235 */
2236 void intel_add_fb_offsets(int *x, int *y,
2237 const struct intel_plane_state *state,
2238 int plane)
2239
2240 {
2241 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2242 unsigned int rotation = state->base.rotation;
2243
2244 if (drm_rotation_90_or_270(rotation)) {
2245 *x += intel_fb->rotated[plane].x;
2246 *y += intel_fb->rotated[plane].y;
2247 } else {
2248 *x += intel_fb->normal[plane].x;
2249 *y += intel_fb->normal[plane].y;
2250 }
2251 }
2252
2253 /*
2254 * Input tile dimensions and pitch must already be
2255 * rotated to match x and y, and in pixel units.
2256 */
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258 unsigned int tile_width,
2259 unsigned int tile_height,
2260 unsigned int tile_size,
2261 unsigned int pitch_tiles,
2262 u32 old_offset,
2263 u32 new_offset)
2264 {
2265 unsigned int pitch_pixels = pitch_tiles * tile_width;
2266 unsigned int tiles;
2267
2268 WARN_ON(old_offset & (tile_size - 1));
2269 WARN_ON(new_offset & (tile_size - 1));
2270 WARN_ON(new_offset > old_offset);
2271
2272 tiles = (old_offset - new_offset) / tile_size;
2273
2274 *y += tiles / pitch_tiles * tile_height;
2275 *x += tiles % pitch_tiles * tile_width;
2276
2277 /* minimize x in case it got needlessly big */
2278 *y += *x / pitch_pixels * tile_height;
2279 *x %= pitch_pixels;
2280
2281 return new_offset;
2282 }
2283
2284 /*
2285 * Adjust the tile offset by moving the difference into
2286 * the x/y offsets.
2287 */
2288 static u32 intel_adjust_tile_offset(int *x, int *y,
2289 const struct intel_plane_state *state, int plane,
2290 u32 old_offset, u32 new_offset)
2291 {
2292 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2293 const struct drm_framebuffer *fb = state->base.fb;
2294 unsigned int cpp = fb->format->cpp[plane];
2295 unsigned int rotation = state->base.rotation;
2296 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2297
2298 WARN_ON(new_offset > old_offset);
2299
2300 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2301 unsigned int tile_size, tile_width, tile_height;
2302 unsigned int pitch_tiles;
2303
2304 tile_size = intel_tile_size(dev_priv);
2305 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2306
2307 if (drm_rotation_90_or_270(rotation)) {
2308 pitch_tiles = pitch / tile_height;
2309 swap(tile_width, tile_height);
2310 } else {
2311 pitch_tiles = pitch / (tile_width * cpp);
2312 }
2313
2314 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2315 tile_size, pitch_tiles,
2316 old_offset, new_offset);
2317 } else {
2318 old_offset += *y * pitch + *x * cpp;
2319
2320 *y = (old_offset - new_offset) / pitch;
2321 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2322 }
2323
2324 return new_offset;
2325 }
2326
2327 /*
2328 * Computes the linear offset to the base tile and adjusts
2329 * x, y. bytes per pixel is assumed to be a power-of-two.
2330 *
2331 * In the 90/270 rotated case, x and y are assumed
2332 * to be already rotated to match the rotated GTT view, and
2333 * pitch is the tile_height aligned framebuffer height.
2334 *
2335 * This function is used when computing the derived information
2336 * under intel_framebuffer, so using any of that information
2337 * here is not allowed. Anything under drm_framebuffer can be
2338 * used. This is why the user has to pass in the pitch since it
2339 * is specified in the rotated orientation.
2340 */
2341 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2342 int *x, int *y,
2343 const struct drm_framebuffer *fb, int plane,
2344 unsigned int pitch,
2345 unsigned int rotation,
2346 u32 alignment)
2347 {
2348 uint64_t fb_modifier = fb->modifier;
2349 unsigned int cpp = fb->format->cpp[plane];
2350 u32 offset, offset_aligned;
2351
2352 if (alignment)
2353 alignment--;
2354
2355 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int tile_rows, tiles, pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2361
2362 if (drm_rotation_90_or_270(rotation)) {
2363 pitch_tiles = pitch / tile_height;
2364 swap(tile_width, tile_height);
2365 } else {
2366 pitch_tiles = pitch / (tile_width * cpp);
2367 }
2368
2369 tile_rows = *y / tile_height;
2370 *y %= tile_height;
2371
2372 tiles = *x / tile_width;
2373 *x %= tile_width;
2374
2375 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2376 offset_aligned = offset & ~alignment;
2377
2378 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2379 tile_size, pitch_tiles,
2380 offset, offset_aligned);
2381 } else {
2382 offset = *y * pitch + *x * cpp;
2383 offset_aligned = offset & ~alignment;
2384
2385 *y = (offset & alignment) / pitch;
2386 *x = ((offset & alignment) - *y * pitch) / cpp;
2387 }
2388
2389 return offset_aligned;
2390 }
2391
2392 u32 intel_compute_tile_offset(int *x, int *y,
2393 const struct intel_plane_state *state,
2394 int plane)
2395 {
2396 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2397 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2398 const struct drm_framebuffer *fb = state->base.fb;
2399 unsigned int rotation = state->base.rotation;
2400 int pitch = intel_fb_pitch(fb, plane, rotation);
2401 u32 alignment;
2402
2403 if (intel_plane->id == PLANE_CURSOR)
2404 alignment = intel_cursor_alignment(dev_priv);
2405 else
2406 alignment = intel_surf_alignment(fb, plane);
2407
2408 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2409 rotation, alignment);
2410 }
2411
2412 /* Convert the fb->offset[] linear offset into x/y offsets */
2413 static void intel_fb_offset_to_xy(int *x, int *y,
2414 const struct drm_framebuffer *fb, int plane)
2415 {
2416 unsigned int cpp = fb->format->cpp[plane];
2417 unsigned int pitch = fb->pitches[plane];
2418 u32 linear_offset = fb->offsets[plane];
2419
2420 *y = linear_offset / pitch;
2421 *x = linear_offset % pitch / cpp;
2422 }
2423
2424 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2425 {
2426 switch (fb_modifier) {
2427 case I915_FORMAT_MOD_X_TILED:
2428 return I915_TILING_X;
2429 case I915_FORMAT_MOD_Y_TILED:
2430 return I915_TILING_Y;
2431 default:
2432 return I915_TILING_NONE;
2433 }
2434 }
2435
2436 static int
2437 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2438 struct drm_framebuffer *fb)
2439 {
2440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2441 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2442 u32 gtt_offset_rotated = 0;
2443 unsigned int max_size = 0;
2444 int i, num_planes = fb->format->num_planes;
2445 unsigned int tile_size = intel_tile_size(dev_priv);
2446
2447 for (i = 0; i < num_planes; i++) {
2448 unsigned int width, height;
2449 unsigned int cpp, size;
2450 u32 offset;
2451 int x, y;
2452
2453 cpp = fb->format->cpp[i];
2454 width = drm_framebuffer_plane_width(fb->width, fb, i);
2455 height = drm_framebuffer_plane_height(fb->height, fb, i);
2456
2457 intel_fb_offset_to_xy(&x, &y, fb, i);
2458
2459 /*
2460 * The fence (if used) is aligned to the start of the object
2461 * so having the framebuffer wrap around across the edge of the
2462 * fenced region doesn't really work. We have no API to configure
2463 * the fence start offset within the object (nor could we probably
2464 * on gen2/3). So it's just easier if we just require that the
2465 * fb layout agrees with the fence layout. We already check that the
2466 * fb stride matches the fence stride elsewhere.
2467 */
2468 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2469 (x + width) * cpp > fb->pitches[i]) {
2470 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2471 i, fb->offsets[i]);
2472 return -EINVAL;
2473 }
2474
2475 /*
2476 * First pixel of the framebuffer from
2477 * the start of the normal gtt mapping.
2478 */
2479 intel_fb->normal[i].x = x;
2480 intel_fb->normal[i].y = y;
2481
2482 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2483 fb, i, fb->pitches[i],
2484 DRM_MODE_ROTATE_0, tile_size);
2485 offset /= tile_size;
2486
2487 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2488 unsigned int tile_width, tile_height;
2489 unsigned int pitch_tiles;
2490 struct drm_rect r;
2491
2492 intel_tile_dims(fb, i, &tile_width, &tile_height);
2493
2494 rot_info->plane[i].offset = offset;
2495 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2496 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2497 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2498
2499 intel_fb->rotated[i].pitch =
2500 rot_info->plane[i].height * tile_height;
2501
2502 /* how many tiles does this plane need */
2503 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2504 /*
2505 * If the plane isn't horizontally tile aligned,
2506 * we need one more tile.
2507 */
2508 if (x != 0)
2509 size++;
2510
2511 /* rotate the x/y offsets to match the GTT view */
2512 r.x1 = x;
2513 r.y1 = y;
2514 r.x2 = x + width;
2515 r.y2 = y + height;
2516 drm_rect_rotate(&r,
2517 rot_info->plane[i].width * tile_width,
2518 rot_info->plane[i].height * tile_height,
2519 DRM_MODE_ROTATE_270);
2520 x = r.x1;
2521 y = r.y1;
2522
2523 /* rotate the tile dimensions to match the GTT view */
2524 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2525 swap(tile_width, tile_height);
2526
2527 /*
2528 * We only keep the x/y offsets, so push all of the
2529 * gtt offset into the x/y offsets.
2530 */
2531 _intel_adjust_tile_offset(&x, &y,
2532 tile_width, tile_height,
2533 tile_size, pitch_tiles,
2534 gtt_offset_rotated * tile_size, 0);
2535
2536 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2537
2538 /*
2539 * First pixel of the framebuffer from
2540 * the start of the rotated gtt mapping.
2541 */
2542 intel_fb->rotated[i].x = x;
2543 intel_fb->rotated[i].y = y;
2544 } else {
2545 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2546 x * cpp, tile_size);
2547 }
2548
2549 /* how many tiles in total needed in the bo */
2550 max_size = max(max_size, offset + size);
2551 }
2552
2553 if (max_size * tile_size > intel_fb->obj->base.size) {
2554 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2555 max_size * tile_size, intel_fb->obj->base.size);
2556 return -EINVAL;
2557 }
2558
2559 return 0;
2560 }
2561
2562 static int i9xx_format_to_fourcc(int format)
2563 {
2564 switch (format) {
2565 case DISPPLANE_8BPP:
2566 return DRM_FORMAT_C8;
2567 case DISPPLANE_BGRX555:
2568 return DRM_FORMAT_XRGB1555;
2569 case DISPPLANE_BGRX565:
2570 return DRM_FORMAT_RGB565;
2571 default:
2572 case DISPPLANE_BGRX888:
2573 return DRM_FORMAT_XRGB8888;
2574 case DISPPLANE_RGBX888:
2575 return DRM_FORMAT_XBGR8888;
2576 case DISPPLANE_BGRX101010:
2577 return DRM_FORMAT_XRGB2101010;
2578 case DISPPLANE_RGBX101010:
2579 return DRM_FORMAT_XBGR2101010;
2580 }
2581 }
2582
2583 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2584 {
2585 switch (format) {
2586 case PLANE_CTL_FORMAT_RGB_565:
2587 return DRM_FORMAT_RGB565;
2588 default:
2589 case PLANE_CTL_FORMAT_XRGB_8888:
2590 if (rgb_order) {
2591 if (alpha)
2592 return DRM_FORMAT_ABGR8888;
2593 else
2594 return DRM_FORMAT_XBGR8888;
2595 } else {
2596 if (alpha)
2597 return DRM_FORMAT_ARGB8888;
2598 else
2599 return DRM_FORMAT_XRGB8888;
2600 }
2601 case PLANE_CTL_FORMAT_XRGB_2101010:
2602 if (rgb_order)
2603 return DRM_FORMAT_XBGR2101010;
2604 else
2605 return DRM_FORMAT_XRGB2101010;
2606 }
2607 }
2608
2609 static bool
2610 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2611 struct intel_initial_plane_config *plane_config)
2612 {
2613 struct drm_device *dev = crtc->base.dev;
2614 struct drm_i915_private *dev_priv = to_i915(dev);
2615 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2616 struct drm_i915_gem_object *obj = NULL;
2617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2618 struct drm_framebuffer *fb = &plane_config->fb->base;
2619 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2620 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2621 PAGE_SIZE);
2622
2623 size_aligned -= base_aligned;
2624
2625 if (plane_config->size == 0)
2626 return false;
2627
2628 /* If the FB is too big, just don't use it since fbdev is not very
2629 * important and we should probably use that space with FBC or other
2630 * features. */
2631 if (size_aligned * 2 > ggtt->stolen_usable_size)
2632 return false;
2633
2634 mutex_lock(&dev->struct_mutex);
2635 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2636 base_aligned,
2637 base_aligned,
2638 size_aligned);
2639 mutex_unlock(&dev->struct_mutex);
2640 if (!obj)
2641 return false;
2642
2643 if (plane_config->tiling == I915_TILING_X)
2644 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2645
2646 mode_cmd.pixel_format = fb->format->format;
2647 mode_cmd.width = fb->width;
2648 mode_cmd.height = fb->height;
2649 mode_cmd.pitches[0] = fb->pitches[0];
2650 mode_cmd.modifier[0] = fb->modifier;
2651 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2652
2653 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2654 DRM_DEBUG_KMS("intel fb init failed\n");
2655 goto out_unref_obj;
2656 }
2657
2658
2659 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2660 return true;
2661
2662 out_unref_obj:
2663 i915_gem_object_put(obj);
2664 return false;
2665 }
2666
2667 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2668 static void
2669 update_state_fb(struct drm_plane *plane)
2670 {
2671 if (plane->fb == plane->state->fb)
2672 return;
2673
2674 if (plane->state->fb)
2675 drm_framebuffer_unreference(plane->state->fb);
2676 plane->state->fb = plane->fb;
2677 if (plane->state->fb)
2678 drm_framebuffer_reference(plane->state->fb);
2679 }
2680
2681 static void
2682 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2683 struct intel_plane_state *plane_state,
2684 bool visible)
2685 {
2686 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2687
2688 plane_state->base.visible = visible;
2689
2690 /* FIXME pre-g4x don't work like this */
2691 if (visible) {
2692 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2693 crtc_state->active_planes |= BIT(plane->id);
2694 } else {
2695 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2696 crtc_state->active_planes &= ~BIT(plane->id);
2697 }
2698
2699 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2700 crtc_state->base.crtc->name,
2701 crtc_state->active_planes);
2702 }
2703
2704 static void
2705 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2706 struct intel_initial_plane_config *plane_config)
2707 {
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = to_i915(dev);
2710 struct drm_crtc *c;
2711 struct drm_i915_gem_object *obj;
2712 struct drm_plane *primary = intel_crtc->base.primary;
2713 struct drm_plane_state *plane_state = primary->state;
2714 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2715 struct intel_plane *intel_plane = to_intel_plane(primary);
2716 struct intel_plane_state *intel_state =
2717 to_intel_plane_state(plane_state);
2718 struct drm_framebuffer *fb;
2719
2720 if (!plane_config->fb)
2721 return;
2722
2723 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2724 fb = &plane_config->fb->base;
2725 goto valid_fb;
2726 }
2727
2728 kfree(plane_config->fb);
2729
2730 /*
2731 * Failed to alloc the obj, check to see if we should share
2732 * an fb with another CRTC instead
2733 */
2734 for_each_crtc(dev, c) {
2735 struct intel_plane_state *state;
2736
2737 if (c == &intel_crtc->base)
2738 continue;
2739
2740 if (!to_intel_crtc(c)->active)
2741 continue;
2742
2743 state = to_intel_plane_state(c->primary->state);
2744 if (!state->vma)
2745 continue;
2746
2747 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2748 fb = c->primary->fb;
2749 drm_framebuffer_reference(fb);
2750 goto valid_fb;
2751 }
2752 }
2753
2754 /*
2755 * We've failed to reconstruct the BIOS FB. Current display state
2756 * indicates that the primary plane is visible, but has a NULL FB,
2757 * which will lead to problems later if we don't fix it up. The
2758 * simplest solution is to just disable the primary plane now and
2759 * pretend the BIOS never had it enabled.
2760 */
2761 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2762 to_intel_plane_state(plane_state),
2763 false);
2764 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2765 trace_intel_disable_plane(primary, intel_crtc);
2766 intel_plane->disable_plane(intel_plane, intel_crtc);
2767
2768 return;
2769
2770 valid_fb:
2771 mutex_lock(&dev->struct_mutex);
2772 intel_state->vma =
2773 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2774 mutex_unlock(&dev->struct_mutex);
2775 if (IS_ERR(intel_state->vma)) {
2776 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2777 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2778
2779 intel_state->vma = NULL;
2780 drm_framebuffer_unreference(fb);
2781 return;
2782 }
2783
2784 plane_state->src_x = 0;
2785 plane_state->src_y = 0;
2786 plane_state->src_w = fb->width << 16;
2787 plane_state->src_h = fb->height << 16;
2788
2789 plane_state->crtc_x = 0;
2790 plane_state->crtc_y = 0;
2791 plane_state->crtc_w = fb->width;
2792 plane_state->crtc_h = fb->height;
2793
2794 intel_state->base.src = drm_plane_state_src(plane_state);
2795 intel_state->base.dst = drm_plane_state_dest(plane_state);
2796
2797 obj = intel_fb_obj(fb);
2798 if (i915_gem_object_is_tiled(obj))
2799 dev_priv->preserve_bios_swizzle = true;
2800
2801 drm_framebuffer_reference(fb);
2802 primary->fb = primary->state->fb = fb;
2803 primary->crtc = primary->state->crtc = &intel_crtc->base;
2804
2805 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2806 to_intel_plane_state(plane_state),
2807 true);
2808
2809 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2810 &obj->frontbuffer_bits);
2811 }
2812
2813 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2814 unsigned int rotation)
2815 {
2816 int cpp = fb->format->cpp[plane];
2817
2818 switch (fb->modifier) {
2819 case DRM_FORMAT_MOD_LINEAR:
2820 case I915_FORMAT_MOD_X_TILED:
2821 switch (cpp) {
2822 case 8:
2823 return 4096;
2824 case 4:
2825 case 2:
2826 case 1:
2827 return 8192;
2828 default:
2829 MISSING_CASE(cpp);
2830 break;
2831 }
2832 break;
2833 case I915_FORMAT_MOD_Y_TILED:
2834 case I915_FORMAT_MOD_Yf_TILED:
2835 switch (cpp) {
2836 case 8:
2837 return 2048;
2838 case 4:
2839 return 4096;
2840 case 2:
2841 case 1:
2842 return 8192;
2843 default:
2844 MISSING_CASE(cpp);
2845 break;
2846 }
2847 break;
2848 default:
2849 MISSING_CASE(fb->modifier);
2850 }
2851
2852 return 2048;
2853 }
2854
2855 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2856 {
2857 const struct drm_framebuffer *fb = plane_state->base.fb;
2858 unsigned int rotation = plane_state->base.rotation;
2859 int x = plane_state->base.src.x1 >> 16;
2860 int y = plane_state->base.src.y1 >> 16;
2861 int w = drm_rect_width(&plane_state->base.src) >> 16;
2862 int h = drm_rect_height(&plane_state->base.src) >> 16;
2863 int max_width = skl_max_plane_width(fb, 0, rotation);
2864 int max_height = 4096;
2865 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2866
2867 if (w > max_width || h > max_height) {
2868 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2869 w, h, max_width, max_height);
2870 return -EINVAL;
2871 }
2872
2873 intel_add_fb_offsets(&x, &y, plane_state, 0);
2874 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2875 alignment = intel_surf_alignment(fb, 0);
2876
2877 /*
2878 * AUX surface offset is specified as the distance from the
2879 * main surface offset, and it must be non-negative. Make
2880 * sure that is what we will get.
2881 */
2882 if (offset > aux_offset)
2883 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2884 offset, aux_offset & ~(alignment - 1));
2885
2886 /*
2887 * When using an X-tiled surface, the plane blows up
2888 * if the x offset + width exceed the stride.
2889 *
2890 * TODO: linear and Y-tiled seem fine, Yf untested,
2891 */
2892 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2893 int cpp = fb->format->cpp[0];
2894
2895 while ((x + w) * cpp > fb->pitches[0]) {
2896 if (offset == 0) {
2897 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2898 return -EINVAL;
2899 }
2900
2901 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2902 offset, offset - alignment);
2903 }
2904 }
2905
2906 plane_state->main.offset = offset;
2907 plane_state->main.x = x;
2908 plane_state->main.y = y;
2909
2910 return 0;
2911 }
2912
2913 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2914 {
2915 const struct drm_framebuffer *fb = plane_state->base.fb;
2916 unsigned int rotation = plane_state->base.rotation;
2917 int max_width = skl_max_plane_width(fb, 1, rotation);
2918 int max_height = 4096;
2919 int x = plane_state->base.src.x1 >> 17;
2920 int y = plane_state->base.src.y1 >> 17;
2921 int w = drm_rect_width(&plane_state->base.src) >> 17;
2922 int h = drm_rect_height(&plane_state->base.src) >> 17;
2923 u32 offset;
2924
2925 intel_add_fb_offsets(&x, &y, plane_state, 1);
2926 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2927
2928 /* FIXME not quite sure how/if these apply to the chroma plane */
2929 if (w > max_width || h > max_height) {
2930 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2931 w, h, max_width, max_height);
2932 return -EINVAL;
2933 }
2934
2935 plane_state->aux.offset = offset;
2936 plane_state->aux.x = x;
2937 plane_state->aux.y = y;
2938
2939 return 0;
2940 }
2941
2942 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2943 {
2944 const struct drm_framebuffer *fb = plane_state->base.fb;
2945 unsigned int rotation = plane_state->base.rotation;
2946 int ret;
2947
2948 if (!plane_state->base.visible)
2949 return 0;
2950
2951 /* Rotate src coordinates to match rotated GTT view */
2952 if (drm_rotation_90_or_270(rotation))
2953 drm_rect_rotate(&plane_state->base.src,
2954 fb->width << 16, fb->height << 16,
2955 DRM_MODE_ROTATE_270);
2956
2957 /*
2958 * Handle the AUX surface first since
2959 * the main surface setup depends on it.
2960 */
2961 if (fb->format->format == DRM_FORMAT_NV12) {
2962 ret = skl_check_nv12_aux_surface(plane_state);
2963 if (ret)
2964 return ret;
2965 } else {
2966 plane_state->aux.offset = ~0xfff;
2967 plane_state->aux.x = 0;
2968 plane_state->aux.y = 0;
2969 }
2970
2971 ret = skl_check_main_surface(plane_state);
2972 if (ret)
2973 return ret;
2974
2975 return 0;
2976 }
2977
2978 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2979 const struct intel_plane_state *plane_state)
2980 {
2981 struct drm_i915_private *dev_priv =
2982 to_i915(plane_state->base.plane->dev);
2983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2984 const struct drm_framebuffer *fb = plane_state->base.fb;
2985 unsigned int rotation = plane_state->base.rotation;
2986 u32 dspcntr;
2987
2988 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2989
2990 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2991 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2992 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2993
2994 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2995 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2996
2997 if (INTEL_GEN(dev_priv) < 4)
2998 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2999
3000 switch (fb->format->format) {
3001 case DRM_FORMAT_C8:
3002 dspcntr |= DISPPLANE_8BPP;
3003 break;
3004 case DRM_FORMAT_XRGB1555:
3005 dspcntr |= DISPPLANE_BGRX555;
3006 break;
3007 case DRM_FORMAT_RGB565:
3008 dspcntr |= DISPPLANE_BGRX565;
3009 break;
3010 case DRM_FORMAT_XRGB8888:
3011 dspcntr |= DISPPLANE_BGRX888;
3012 break;
3013 case DRM_FORMAT_XBGR8888:
3014 dspcntr |= DISPPLANE_RGBX888;
3015 break;
3016 case DRM_FORMAT_XRGB2101010:
3017 dspcntr |= DISPPLANE_BGRX101010;
3018 break;
3019 case DRM_FORMAT_XBGR2101010:
3020 dspcntr |= DISPPLANE_RGBX101010;
3021 break;
3022 default:
3023 MISSING_CASE(fb->format->format);
3024 return 0;
3025 }
3026
3027 if (INTEL_GEN(dev_priv) >= 4 &&
3028 fb->modifier == I915_FORMAT_MOD_X_TILED)
3029 dspcntr |= DISPPLANE_TILED;
3030
3031 if (rotation & DRM_MODE_ROTATE_180)
3032 dspcntr |= DISPPLANE_ROTATE_180;
3033
3034 if (rotation & DRM_MODE_REFLECT_X)
3035 dspcntr |= DISPPLANE_MIRROR;
3036
3037 return dspcntr;
3038 }
3039
3040 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3041 {
3042 struct drm_i915_private *dev_priv =
3043 to_i915(plane_state->base.plane->dev);
3044 int src_x = plane_state->base.src.x1 >> 16;
3045 int src_y = plane_state->base.src.y1 >> 16;
3046 u32 offset;
3047
3048 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3049
3050 if (INTEL_GEN(dev_priv) >= 4)
3051 offset = intel_compute_tile_offset(&src_x, &src_y,
3052 plane_state, 0);
3053 else
3054 offset = 0;
3055
3056 /* HSW/BDW do this automagically in hardware */
3057 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3058 unsigned int rotation = plane_state->base.rotation;
3059 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3060 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3061
3062 if (rotation & DRM_MODE_ROTATE_180) {
3063 src_x += src_w - 1;
3064 src_y += src_h - 1;
3065 } else if (rotation & DRM_MODE_REFLECT_X) {
3066 src_x += src_w - 1;
3067 }
3068 }
3069
3070 plane_state->main.offset = offset;
3071 plane_state->main.x = src_x;
3072 plane_state->main.y = src_y;
3073
3074 return 0;
3075 }
3076
3077 static void i9xx_update_primary_plane(struct intel_plane *primary,
3078 const struct intel_crtc_state *crtc_state,
3079 const struct intel_plane_state *plane_state)
3080 {
3081 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3083 const struct drm_framebuffer *fb = plane_state->base.fb;
3084 enum plane plane = primary->plane;
3085 u32 linear_offset;
3086 u32 dspcntr = plane_state->ctl;
3087 i915_reg_t reg = DSPCNTR(plane);
3088 int x = plane_state->main.x;
3089 int y = plane_state->main.y;
3090 unsigned long irqflags;
3091
3092 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3093
3094 if (INTEL_GEN(dev_priv) >= 4)
3095 crtc->dspaddr_offset = plane_state->main.offset;
3096 else
3097 crtc->dspaddr_offset = linear_offset;
3098
3099 crtc->adjusted_x = x;
3100 crtc->adjusted_y = y;
3101
3102 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3103
3104 if (INTEL_GEN(dev_priv) < 4) {
3105 /* pipesrc and dspsize control the size that is scaled from,
3106 * which should always be the user's requested size.
3107 */
3108 I915_WRITE_FW(DSPSIZE(plane),
3109 ((crtc_state->pipe_src_h - 1) << 16) |
3110 (crtc_state->pipe_src_w - 1));
3111 I915_WRITE_FW(DSPPOS(plane), 0);
3112 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3113 I915_WRITE_FW(PRIMSIZE(plane),
3114 ((crtc_state->pipe_src_h - 1) << 16) |
3115 (crtc_state->pipe_src_w - 1));
3116 I915_WRITE_FW(PRIMPOS(plane), 0);
3117 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3118 }
3119
3120 I915_WRITE_FW(reg, dspcntr);
3121
3122 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3123 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3124 I915_WRITE_FW(DSPSURF(plane),
3125 intel_plane_ggtt_offset(plane_state) +
3126 crtc->dspaddr_offset);
3127 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3128 } else if (INTEL_GEN(dev_priv) >= 4) {
3129 I915_WRITE_FW(DSPSURF(plane),
3130 intel_plane_ggtt_offset(plane_state) +
3131 crtc->dspaddr_offset);
3132 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3133 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3134 } else {
3135 I915_WRITE_FW(DSPADDR(plane),
3136 intel_plane_ggtt_offset(plane_state) +
3137 crtc->dspaddr_offset);
3138 }
3139 POSTING_READ_FW(reg);
3140
3141 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3142 }
3143
3144 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3145 struct intel_crtc *crtc)
3146 {
3147 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3148 enum plane plane = primary->plane;
3149 unsigned long irqflags;
3150
3151 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3152
3153 I915_WRITE_FW(DSPCNTR(plane), 0);
3154 if (INTEL_INFO(dev_priv)->gen >= 4)
3155 I915_WRITE_FW(DSPSURF(plane), 0);
3156 else
3157 I915_WRITE_FW(DSPADDR(plane), 0);
3158 POSTING_READ_FW(DSPCNTR(plane));
3159
3160 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3161 }
3162
3163 static u32
3164 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3165 {
3166 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3167 return 64;
3168 else
3169 return intel_tile_width_bytes(fb, plane);
3170 }
3171
3172 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3173 {
3174 struct drm_device *dev = intel_crtc->base.dev;
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3178 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3179 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3180 }
3181
3182 /*
3183 * This function detaches (aka. unbinds) unused scalers in hardware
3184 */
3185 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3186 {
3187 struct intel_crtc_scaler_state *scaler_state;
3188 int i;
3189
3190 scaler_state = &intel_crtc->config->scaler_state;
3191
3192 /* loop through and disable scalers that aren't in use */
3193 for (i = 0; i < intel_crtc->num_scalers; i++) {
3194 if (!scaler_state->scalers[i].in_use)
3195 skl_detach_scaler(intel_crtc, i);
3196 }
3197 }
3198
3199 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3200 unsigned int rotation)
3201 {
3202 u32 stride;
3203
3204 if (plane >= fb->format->num_planes)
3205 return 0;
3206
3207 stride = intel_fb_pitch(fb, plane, rotation);
3208
3209 /*
3210 * The stride is either expressed as a multiple of 64 bytes chunks for
3211 * linear buffers or in number of tiles for tiled buffers.
3212 */
3213 if (drm_rotation_90_or_270(rotation))
3214 stride /= intel_tile_height(fb, plane);
3215 else
3216 stride /= intel_fb_stride_alignment(fb, plane);
3217
3218 return stride;
3219 }
3220
3221 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3222 {
3223 switch (pixel_format) {
3224 case DRM_FORMAT_C8:
3225 return PLANE_CTL_FORMAT_INDEXED;
3226 case DRM_FORMAT_RGB565:
3227 return PLANE_CTL_FORMAT_RGB_565;
3228 case DRM_FORMAT_XBGR8888:
3229 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3230 case DRM_FORMAT_XRGB8888:
3231 return PLANE_CTL_FORMAT_XRGB_8888;
3232 /*
3233 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3234 * to be already pre-multiplied. We need to add a knob (or a different
3235 * DRM_FORMAT) for user-space to configure that.
3236 */
3237 case DRM_FORMAT_ABGR8888:
3238 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3239 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3240 case DRM_FORMAT_ARGB8888:
3241 return PLANE_CTL_FORMAT_XRGB_8888 |
3242 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3243 case DRM_FORMAT_XRGB2101010:
3244 return PLANE_CTL_FORMAT_XRGB_2101010;
3245 case DRM_FORMAT_XBGR2101010:
3246 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3247 case DRM_FORMAT_YUYV:
3248 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3249 case DRM_FORMAT_YVYU:
3250 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3251 case DRM_FORMAT_UYVY:
3252 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3253 case DRM_FORMAT_VYUY:
3254 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3255 default:
3256 MISSING_CASE(pixel_format);
3257 }
3258
3259 return 0;
3260 }
3261
3262 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3263 {
3264 switch (fb_modifier) {
3265 case DRM_FORMAT_MOD_LINEAR:
3266 break;
3267 case I915_FORMAT_MOD_X_TILED:
3268 return PLANE_CTL_TILED_X;
3269 case I915_FORMAT_MOD_Y_TILED:
3270 return PLANE_CTL_TILED_Y;
3271 case I915_FORMAT_MOD_Yf_TILED:
3272 return PLANE_CTL_TILED_YF;
3273 default:
3274 MISSING_CASE(fb_modifier);
3275 }
3276
3277 return 0;
3278 }
3279
3280 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3281 {
3282 switch (rotation) {
3283 case DRM_MODE_ROTATE_0:
3284 break;
3285 /*
3286 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3287 * while i915 HW rotation is clockwise, thats why this swapping.
3288 */
3289 case DRM_MODE_ROTATE_90:
3290 return PLANE_CTL_ROTATE_270;
3291 case DRM_MODE_ROTATE_180:
3292 return PLANE_CTL_ROTATE_180;
3293 case DRM_MODE_ROTATE_270:
3294 return PLANE_CTL_ROTATE_90;
3295 default:
3296 MISSING_CASE(rotation);
3297 }
3298
3299 return 0;
3300 }
3301
3302 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3303 const struct intel_plane_state *plane_state)
3304 {
3305 struct drm_i915_private *dev_priv =
3306 to_i915(plane_state->base.plane->dev);
3307 const struct drm_framebuffer *fb = plane_state->base.fb;
3308 unsigned int rotation = plane_state->base.rotation;
3309 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3310 u32 plane_ctl;
3311
3312 plane_ctl = PLANE_CTL_ENABLE;
3313
3314 if (!IS_GEMINILAKE(dev_priv)) {
3315 plane_ctl |=
3316 PLANE_CTL_PIPE_GAMMA_ENABLE |
3317 PLANE_CTL_PIPE_CSC_ENABLE |
3318 PLANE_CTL_PLANE_GAMMA_DISABLE;
3319 }
3320
3321 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3322 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3323 plane_ctl |= skl_plane_ctl_rotation(rotation);
3324
3325 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3326 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3327 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3328 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3329
3330 return plane_ctl;
3331 }
3332
3333 static void skylake_update_primary_plane(struct intel_plane *plane,
3334 const struct intel_crtc_state *crtc_state,
3335 const struct intel_plane_state *plane_state)
3336 {
3337 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3339 const struct drm_framebuffer *fb = plane_state->base.fb;
3340 enum plane_id plane_id = plane->id;
3341 enum pipe pipe = plane->pipe;
3342 u32 plane_ctl = plane_state->ctl;
3343 unsigned int rotation = plane_state->base.rotation;
3344 u32 stride = skl_plane_stride(fb, 0, rotation);
3345 u32 surf_addr = plane_state->main.offset;
3346 int scaler_id = plane_state->scaler_id;
3347 int src_x = plane_state->main.x;
3348 int src_y = plane_state->main.y;
3349 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3350 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3351 int dst_x = plane_state->base.dst.x1;
3352 int dst_y = plane_state->base.dst.y1;
3353 int dst_w = drm_rect_width(&plane_state->base.dst);
3354 int dst_h = drm_rect_height(&plane_state->base.dst);
3355 unsigned long irqflags;
3356
3357 /* Sizes are 0 based */
3358 src_w--;
3359 src_h--;
3360 dst_w--;
3361 dst_h--;
3362
3363 crtc->dspaddr_offset = surf_addr;
3364
3365 crtc->adjusted_x = src_x;
3366 crtc->adjusted_y = src_y;
3367
3368 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3369
3370 if (IS_GEMINILAKE(dev_priv)) {
3371 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3372 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3373 PLANE_COLOR_PIPE_CSC_ENABLE |
3374 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3375 }
3376
3377 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3378 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3379 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3380 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3381
3382 if (scaler_id >= 0) {
3383 uint32_t ps_ctrl = 0;
3384
3385 WARN_ON(!dst_w || !dst_h);
3386 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3387 crtc_state->scaler_state.scalers[scaler_id].mode;
3388 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3389 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3390 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3391 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3392 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3393 } else {
3394 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3395 }
3396
3397 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3398 intel_plane_ggtt_offset(plane_state) + surf_addr);
3399
3400 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3401
3402 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3403 }
3404
3405 static void skylake_disable_primary_plane(struct intel_plane *primary,
3406 struct intel_crtc *crtc)
3407 {
3408 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3409 enum plane_id plane_id = primary->id;
3410 enum pipe pipe = primary->pipe;
3411 unsigned long irqflags;
3412
3413 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3414
3415 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3416 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3417 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3418
3419 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3420 }
3421
3422 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3423 {
3424 struct intel_crtc *crtc;
3425
3426 for_each_intel_crtc(&dev_priv->drm, crtc)
3427 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3428 }
3429
3430 static void intel_update_primary_planes(struct drm_device *dev)
3431 {
3432 struct drm_crtc *crtc;
3433
3434 for_each_crtc(dev, crtc) {
3435 struct intel_plane *plane = to_intel_plane(crtc->primary);
3436 struct intel_plane_state *plane_state =
3437 to_intel_plane_state(plane->base.state);
3438
3439 if (plane_state->base.visible) {
3440 trace_intel_update_plane(&plane->base,
3441 to_intel_crtc(crtc));
3442
3443 plane->update_plane(plane,
3444 to_intel_crtc_state(crtc->state),
3445 plane_state);
3446 }
3447 }
3448 }
3449
3450 static int
3451 __intel_display_resume(struct drm_device *dev,
3452 struct drm_atomic_state *state,
3453 struct drm_modeset_acquire_ctx *ctx)
3454 {
3455 struct drm_crtc_state *crtc_state;
3456 struct drm_crtc *crtc;
3457 int i, ret;
3458
3459 intel_modeset_setup_hw_state(dev, ctx);
3460 i915_redisable_vga(to_i915(dev));
3461
3462 if (!state)
3463 return 0;
3464
3465 /*
3466 * We've duplicated the state, pointers to the old state are invalid.
3467 *
3468 * Don't attempt to use the old state until we commit the duplicated state.
3469 */
3470 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3471 /*
3472 * Force recalculation even if we restore
3473 * current state. With fast modeset this may not result
3474 * in a modeset when the state is compatible.
3475 */
3476 crtc_state->mode_changed = true;
3477 }
3478
3479 /* ignore any reset values/BIOS leftovers in the WM registers */
3480 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3481 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3482
3483 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3484
3485 WARN_ON(ret == -EDEADLK);
3486 return ret;
3487 }
3488
3489 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3490 {
3491 return intel_has_gpu_reset(dev_priv) &&
3492 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3493 }
3494
3495 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3496 {
3497 struct drm_device *dev = &dev_priv->drm;
3498 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3499 struct drm_atomic_state *state;
3500 int ret;
3501
3502 /*
3503 * Need mode_config.mutex so that we don't
3504 * trample ongoing ->detect() and whatnot.
3505 */
3506 mutex_lock(&dev->mode_config.mutex);
3507 drm_modeset_acquire_init(ctx, 0);
3508 while (1) {
3509 ret = drm_modeset_lock_all_ctx(dev, ctx);
3510 if (ret != -EDEADLK)
3511 break;
3512
3513 drm_modeset_backoff(ctx);
3514 }
3515
3516 /* reset doesn't touch the display, but flips might get nuked anyway, */
3517 if (!i915.force_reset_modeset_test &&
3518 !gpu_reset_clobbers_display(dev_priv))
3519 return;
3520
3521 /*
3522 * Disabling the crtcs gracefully seems nicer. Also the
3523 * g33 docs say we should at least disable all the planes.
3524 */
3525 state = drm_atomic_helper_duplicate_state(dev, ctx);
3526 if (IS_ERR(state)) {
3527 ret = PTR_ERR(state);
3528 DRM_ERROR("Duplicating state failed with %i\n", ret);
3529 return;
3530 }
3531
3532 ret = drm_atomic_helper_disable_all(dev, ctx);
3533 if (ret) {
3534 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3535 drm_atomic_state_put(state);
3536 return;
3537 }
3538
3539 dev_priv->modeset_restore_state = state;
3540 state->acquire_ctx = ctx;
3541 }
3542
3543 void intel_finish_reset(struct drm_i915_private *dev_priv)
3544 {
3545 struct drm_device *dev = &dev_priv->drm;
3546 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3547 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3548 int ret;
3549
3550 /*
3551 * Flips in the rings will be nuked by the reset,
3552 * so complete all pending flips so that user space
3553 * will get its events and not get stuck.
3554 */
3555 intel_complete_page_flips(dev_priv);
3556
3557 dev_priv->modeset_restore_state = NULL;
3558
3559 /* reset doesn't touch the display */
3560 if (!gpu_reset_clobbers_display(dev_priv)) {
3561 if (!state) {
3562 /*
3563 * Flips in the rings have been nuked by the reset,
3564 * so update the base address of all primary
3565 * planes to the the last fb to make sure we're
3566 * showing the correct fb after a reset.
3567 *
3568 * FIXME: Atomic will make this obsolete since we won't schedule
3569 * CS-based flips (which might get lost in gpu resets) any more.
3570 */
3571 intel_update_primary_planes(dev);
3572 } else {
3573 ret = __intel_display_resume(dev, state, ctx);
3574 if (ret)
3575 DRM_ERROR("Restoring old state failed with %i\n", ret);
3576 }
3577 } else {
3578 /*
3579 * The display has been reset as well,
3580 * so need a full re-initialization.
3581 */
3582 intel_runtime_pm_disable_interrupts(dev_priv);
3583 intel_runtime_pm_enable_interrupts(dev_priv);
3584
3585 intel_pps_unlock_regs_wa(dev_priv);
3586 intel_modeset_init_hw(dev);
3587
3588 spin_lock_irq(&dev_priv->irq_lock);
3589 if (dev_priv->display.hpd_irq_setup)
3590 dev_priv->display.hpd_irq_setup(dev_priv);
3591 spin_unlock_irq(&dev_priv->irq_lock);
3592
3593 ret = __intel_display_resume(dev, state, ctx);
3594 if (ret)
3595 DRM_ERROR("Restoring old state failed with %i\n", ret);
3596
3597 intel_hpd_init(dev_priv);
3598 }
3599
3600 if (state)
3601 drm_atomic_state_put(state);
3602 drm_modeset_drop_locks(ctx);
3603 drm_modeset_acquire_fini(ctx);
3604 mutex_unlock(&dev->mode_config.mutex);
3605 }
3606
3607 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3608 {
3609 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3610
3611 if (i915_reset_backoff(error))
3612 return true;
3613
3614 if (crtc->reset_count != i915_reset_count(error))
3615 return true;
3616
3617 return false;
3618 }
3619
3620 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3621 {
3622 struct drm_device *dev = crtc->dev;
3623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624 bool pending;
3625
3626 if (abort_flip_on_reset(intel_crtc))
3627 return false;
3628
3629 spin_lock_irq(&dev->event_lock);
3630 pending = to_intel_crtc(crtc)->flip_work != NULL;
3631 spin_unlock_irq(&dev->event_lock);
3632
3633 return pending;
3634 }
3635
3636 static void intel_update_pipe_config(struct intel_crtc *crtc,
3637 struct intel_crtc_state *old_crtc_state)
3638 {
3639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3640 struct intel_crtc_state *pipe_config =
3641 to_intel_crtc_state(crtc->base.state);
3642
3643 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3644 crtc->base.mode = crtc->base.state->mode;
3645
3646 /*
3647 * Update pipe size and adjust fitter if needed: the reason for this is
3648 * that in compute_mode_changes we check the native mode (not the pfit
3649 * mode) to see if we can flip rather than do a full mode set. In the
3650 * fastboot case, we'll flip, but if we don't update the pipesrc and
3651 * pfit state, we'll end up with a big fb scanned out into the wrong
3652 * sized surface.
3653 */
3654
3655 I915_WRITE(PIPESRC(crtc->pipe),
3656 ((pipe_config->pipe_src_w - 1) << 16) |
3657 (pipe_config->pipe_src_h - 1));
3658
3659 /* on skylake this is done by detaching scalers */
3660 if (INTEL_GEN(dev_priv) >= 9) {
3661 skl_detach_scalers(crtc);
3662
3663 if (pipe_config->pch_pfit.enabled)
3664 skylake_pfit_enable(crtc);
3665 } else if (HAS_PCH_SPLIT(dev_priv)) {
3666 if (pipe_config->pch_pfit.enabled)
3667 ironlake_pfit_enable(crtc);
3668 else if (old_crtc_state->pch_pfit.enabled)
3669 ironlake_pfit_disable(crtc, true);
3670 }
3671 }
3672
3673 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3674 {
3675 struct drm_device *dev = crtc->base.dev;
3676 struct drm_i915_private *dev_priv = to_i915(dev);
3677 int pipe = crtc->pipe;
3678 i915_reg_t reg;
3679 u32 temp;
3680
3681 /* enable normal train */
3682 reg = FDI_TX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 if (IS_IVYBRIDGE(dev_priv)) {
3685 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3686 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3687 } else {
3688 temp &= ~FDI_LINK_TRAIN_NONE;
3689 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3690 }
3691 I915_WRITE(reg, temp);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 if (HAS_PCH_CPT(dev_priv)) {
3696 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3697 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3698 } else {
3699 temp &= ~FDI_LINK_TRAIN_NONE;
3700 temp |= FDI_LINK_TRAIN_NONE;
3701 }
3702 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3703
3704 /* wait one idle pattern time */
3705 POSTING_READ(reg);
3706 udelay(1000);
3707
3708 /* IVB wants error correction enabled */
3709 if (IS_IVYBRIDGE(dev_priv))
3710 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3711 FDI_FE_ERRC_ENABLE);
3712 }
3713
3714 /* The FDI link training functions for ILK/Ibexpeak. */
3715 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3716 const struct intel_crtc_state *crtc_state)
3717 {
3718 struct drm_device *dev = crtc->base.dev;
3719 struct drm_i915_private *dev_priv = to_i915(dev);
3720 int pipe = crtc->pipe;
3721 i915_reg_t reg;
3722 u32 temp, tries;
3723
3724 /* FDI needs bits from pipe first */
3725 assert_pipe_enabled(dev_priv, pipe);
3726
3727 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3728 for train result */
3729 reg = FDI_RX_IMR(pipe);
3730 temp = I915_READ(reg);
3731 temp &= ~FDI_RX_SYMBOL_LOCK;
3732 temp &= ~FDI_RX_BIT_LOCK;
3733 I915_WRITE(reg, temp);
3734 I915_READ(reg);
3735 udelay(150);
3736
3737 /* enable CPU FDI TX and PCH FDI RX */
3738 reg = FDI_TX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3741 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3742 temp &= ~FDI_LINK_TRAIN_NONE;
3743 temp |= FDI_LINK_TRAIN_PATTERN_1;
3744 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3745
3746 reg = FDI_RX_CTL(pipe);
3747 temp = I915_READ(reg);
3748 temp &= ~FDI_LINK_TRAIN_NONE;
3749 temp |= FDI_LINK_TRAIN_PATTERN_1;
3750 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3751
3752 POSTING_READ(reg);
3753 udelay(150);
3754
3755 /* Ironlake workaround, enable clock pointer after FDI enable*/
3756 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3757 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3758 FDI_RX_PHASE_SYNC_POINTER_EN);
3759
3760 reg = FDI_RX_IIR(pipe);
3761 for (tries = 0; tries < 5; tries++) {
3762 temp = I915_READ(reg);
3763 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3764
3765 if ((temp & FDI_RX_BIT_LOCK)) {
3766 DRM_DEBUG_KMS("FDI train 1 done.\n");
3767 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3768 break;
3769 }
3770 }
3771 if (tries == 5)
3772 DRM_ERROR("FDI train 1 fail!\n");
3773
3774 /* Train 2 */
3775 reg = FDI_TX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 temp &= ~FDI_LINK_TRAIN_NONE;
3778 temp |= FDI_LINK_TRAIN_PATTERN_2;
3779 I915_WRITE(reg, temp);
3780
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 temp &= ~FDI_LINK_TRAIN_NONE;
3784 temp |= FDI_LINK_TRAIN_PATTERN_2;
3785 I915_WRITE(reg, temp);
3786
3787 POSTING_READ(reg);
3788 udelay(150);
3789
3790 reg = FDI_RX_IIR(pipe);
3791 for (tries = 0; tries < 5; tries++) {
3792 temp = I915_READ(reg);
3793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3794
3795 if (temp & FDI_RX_SYMBOL_LOCK) {
3796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3797 DRM_DEBUG_KMS("FDI train 2 done.\n");
3798 break;
3799 }
3800 }
3801 if (tries == 5)
3802 DRM_ERROR("FDI train 2 fail!\n");
3803
3804 DRM_DEBUG_KMS("FDI train done\n");
3805
3806 }
3807
3808 static const int snb_b_fdi_train_param[] = {
3809 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3810 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3811 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3812 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3813 };
3814
3815 /* The FDI link training functions for SNB/Cougarpoint. */
3816 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3817 const struct intel_crtc_state *crtc_state)
3818 {
3819 struct drm_device *dev = crtc->base.dev;
3820 struct drm_i915_private *dev_priv = to_i915(dev);
3821 int pipe = crtc->pipe;
3822 i915_reg_t reg;
3823 u32 temp, i, retry;
3824
3825 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3826 for train result */
3827 reg = FDI_RX_IMR(pipe);
3828 temp = I915_READ(reg);
3829 temp &= ~FDI_RX_SYMBOL_LOCK;
3830 temp &= ~FDI_RX_BIT_LOCK;
3831 I915_WRITE(reg, temp);
3832
3833 POSTING_READ(reg);
3834 udelay(150);
3835
3836 /* enable CPU FDI TX and PCH FDI RX */
3837 reg = FDI_TX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3840 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3841 temp &= ~FDI_LINK_TRAIN_NONE;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1;
3843 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3844 /* SNB-B */
3845 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3846 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3847
3848 I915_WRITE(FDI_RX_MISC(pipe),
3849 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3850
3851 reg = FDI_RX_CTL(pipe);
3852 temp = I915_READ(reg);
3853 if (HAS_PCH_CPT(dev_priv)) {
3854 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3855 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3856 } else {
3857 temp &= ~FDI_LINK_TRAIN_NONE;
3858 temp |= FDI_LINK_TRAIN_PATTERN_1;
3859 }
3860 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3861
3862 POSTING_READ(reg);
3863 udelay(150);
3864
3865 for (i = 0; i < 4; i++) {
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3869 temp |= snb_b_fdi_train_param[i];
3870 I915_WRITE(reg, temp);
3871
3872 POSTING_READ(reg);
3873 udelay(500);
3874
3875 for (retry = 0; retry < 5; retry++) {
3876 reg = FDI_RX_IIR(pipe);
3877 temp = I915_READ(reg);
3878 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3879 if (temp & FDI_RX_BIT_LOCK) {
3880 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3881 DRM_DEBUG_KMS("FDI train 1 done.\n");
3882 break;
3883 }
3884 udelay(50);
3885 }
3886 if (retry < 5)
3887 break;
3888 }
3889 if (i == 4)
3890 DRM_ERROR("FDI train 1 fail!\n");
3891
3892 /* Train 2 */
3893 reg = FDI_TX_CTL(pipe);
3894 temp = I915_READ(reg);
3895 temp &= ~FDI_LINK_TRAIN_NONE;
3896 temp |= FDI_LINK_TRAIN_PATTERN_2;
3897 if (IS_GEN6(dev_priv)) {
3898 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3899 /* SNB-B */
3900 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3901 }
3902 I915_WRITE(reg, temp);
3903
3904 reg = FDI_RX_CTL(pipe);
3905 temp = I915_READ(reg);
3906 if (HAS_PCH_CPT(dev_priv)) {
3907 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3908 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3909 } else {
3910 temp &= ~FDI_LINK_TRAIN_NONE;
3911 temp |= FDI_LINK_TRAIN_PATTERN_2;
3912 }
3913 I915_WRITE(reg, temp);
3914
3915 POSTING_READ(reg);
3916 udelay(150);
3917
3918 for (i = 0; i < 4; i++) {
3919 reg = FDI_TX_CTL(pipe);
3920 temp = I915_READ(reg);
3921 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3922 temp |= snb_b_fdi_train_param[i];
3923 I915_WRITE(reg, temp);
3924
3925 POSTING_READ(reg);
3926 udelay(500);
3927
3928 for (retry = 0; retry < 5; retry++) {
3929 reg = FDI_RX_IIR(pipe);
3930 temp = I915_READ(reg);
3931 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3932 if (temp & FDI_RX_SYMBOL_LOCK) {
3933 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3934 DRM_DEBUG_KMS("FDI train 2 done.\n");
3935 break;
3936 }
3937 udelay(50);
3938 }
3939 if (retry < 5)
3940 break;
3941 }
3942 if (i == 4)
3943 DRM_ERROR("FDI train 2 fail!\n");
3944
3945 DRM_DEBUG_KMS("FDI train done.\n");
3946 }
3947
3948 /* Manual link training for Ivy Bridge A0 parts */
3949 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3950 const struct intel_crtc_state *crtc_state)
3951 {
3952 struct drm_device *dev = crtc->base.dev;
3953 struct drm_i915_private *dev_priv = to_i915(dev);
3954 int pipe = crtc->pipe;
3955 i915_reg_t reg;
3956 u32 temp, i, j;
3957
3958 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3959 for train result */
3960 reg = FDI_RX_IMR(pipe);
3961 temp = I915_READ(reg);
3962 temp &= ~FDI_RX_SYMBOL_LOCK;
3963 temp &= ~FDI_RX_BIT_LOCK;
3964 I915_WRITE(reg, temp);
3965
3966 POSTING_READ(reg);
3967 udelay(150);
3968
3969 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3970 I915_READ(FDI_RX_IIR(pipe)));
3971
3972 /* Try each vswing and preemphasis setting twice before moving on */
3973 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3974 /* disable first in case we need to retry */
3975 reg = FDI_TX_CTL(pipe);
3976 temp = I915_READ(reg);
3977 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3978 temp &= ~FDI_TX_ENABLE;
3979 I915_WRITE(reg, temp);
3980
3981 reg = FDI_RX_CTL(pipe);
3982 temp = I915_READ(reg);
3983 temp &= ~FDI_LINK_TRAIN_AUTO;
3984 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3985 temp &= ~FDI_RX_ENABLE;
3986 I915_WRITE(reg, temp);
3987
3988 /* enable CPU FDI TX and PCH FDI RX */
3989 reg = FDI_TX_CTL(pipe);
3990 temp = I915_READ(reg);
3991 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3992 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3993 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3994 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3995 temp |= snb_b_fdi_train_param[j/2];
3996 temp |= FDI_COMPOSITE_SYNC;
3997 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3998
3999 I915_WRITE(FDI_RX_MISC(pipe),
4000 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4001
4002 reg = FDI_RX_CTL(pipe);
4003 temp = I915_READ(reg);
4004 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4005 temp |= FDI_COMPOSITE_SYNC;
4006 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4007
4008 POSTING_READ(reg);
4009 udelay(1); /* should be 0.5us */
4010
4011 for (i = 0; i < 4; i++) {
4012 reg = FDI_RX_IIR(pipe);
4013 temp = I915_READ(reg);
4014 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4015
4016 if (temp & FDI_RX_BIT_LOCK ||
4017 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4018 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4019 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4020 i);
4021 break;
4022 }
4023 udelay(1); /* should be 0.5us */
4024 }
4025 if (i == 4) {
4026 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4027 continue;
4028 }
4029
4030 /* Train 2 */
4031 reg = FDI_TX_CTL(pipe);
4032 temp = I915_READ(reg);
4033 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4034 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4035 I915_WRITE(reg, temp);
4036
4037 reg = FDI_RX_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4040 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4041 I915_WRITE(reg, temp);
4042
4043 POSTING_READ(reg);
4044 udelay(2); /* should be 1.5us */
4045
4046 for (i = 0; i < 4; i++) {
4047 reg = FDI_RX_IIR(pipe);
4048 temp = I915_READ(reg);
4049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4050
4051 if (temp & FDI_RX_SYMBOL_LOCK ||
4052 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4053 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4054 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4055 i);
4056 goto train_done;
4057 }
4058 udelay(2); /* should be 1.5us */
4059 }
4060 if (i == 4)
4061 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4062 }
4063
4064 train_done:
4065 DRM_DEBUG_KMS("FDI train done.\n");
4066 }
4067
4068 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4069 {
4070 struct drm_device *dev = intel_crtc->base.dev;
4071 struct drm_i915_private *dev_priv = to_i915(dev);
4072 int pipe = intel_crtc->pipe;
4073 i915_reg_t reg;
4074 u32 temp;
4075
4076 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4077 reg = FDI_RX_CTL(pipe);
4078 temp = I915_READ(reg);
4079 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4080 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4081 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4082 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4083
4084 POSTING_READ(reg);
4085 udelay(200);
4086
4087 /* Switch from Rawclk to PCDclk */
4088 temp = I915_READ(reg);
4089 I915_WRITE(reg, temp | FDI_PCDCLK);
4090
4091 POSTING_READ(reg);
4092 udelay(200);
4093
4094 /* Enable CPU FDI TX PLL, always on for Ironlake */
4095 reg = FDI_TX_CTL(pipe);
4096 temp = I915_READ(reg);
4097 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4098 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4099
4100 POSTING_READ(reg);
4101 udelay(100);
4102 }
4103 }
4104
4105 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4106 {
4107 struct drm_device *dev = intel_crtc->base.dev;
4108 struct drm_i915_private *dev_priv = to_i915(dev);
4109 int pipe = intel_crtc->pipe;
4110 i915_reg_t reg;
4111 u32 temp;
4112
4113 /* Switch from PCDclk to Rawclk */
4114 reg = FDI_RX_CTL(pipe);
4115 temp = I915_READ(reg);
4116 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4117
4118 /* Disable CPU FDI TX PLL */
4119 reg = FDI_TX_CTL(pipe);
4120 temp = I915_READ(reg);
4121 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4122
4123 POSTING_READ(reg);
4124 udelay(100);
4125
4126 reg = FDI_RX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4129
4130 /* Wait for the clocks to turn off. */
4131 POSTING_READ(reg);
4132 udelay(100);
4133 }
4134
4135 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4136 {
4137 struct drm_device *dev = crtc->dev;
4138 struct drm_i915_private *dev_priv = to_i915(dev);
4139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4140 int pipe = intel_crtc->pipe;
4141 i915_reg_t reg;
4142 u32 temp;
4143
4144 /* disable CPU FDI tx and PCH FDI rx */
4145 reg = FDI_TX_CTL(pipe);
4146 temp = I915_READ(reg);
4147 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4148 POSTING_READ(reg);
4149
4150 reg = FDI_RX_CTL(pipe);
4151 temp = I915_READ(reg);
4152 temp &= ~(0x7 << 16);
4153 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4154 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4155
4156 POSTING_READ(reg);
4157 udelay(100);
4158
4159 /* Ironlake workaround, disable clock pointer after downing FDI */
4160 if (HAS_PCH_IBX(dev_priv))
4161 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4162
4163 /* still set train pattern 1 */
4164 reg = FDI_TX_CTL(pipe);
4165 temp = I915_READ(reg);
4166 temp &= ~FDI_LINK_TRAIN_NONE;
4167 temp |= FDI_LINK_TRAIN_PATTERN_1;
4168 I915_WRITE(reg, temp);
4169
4170 reg = FDI_RX_CTL(pipe);
4171 temp = I915_READ(reg);
4172 if (HAS_PCH_CPT(dev_priv)) {
4173 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4174 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4175 } else {
4176 temp &= ~FDI_LINK_TRAIN_NONE;
4177 temp |= FDI_LINK_TRAIN_PATTERN_1;
4178 }
4179 /* BPC in FDI rx is consistent with that in PIPECONF */
4180 temp &= ~(0x07 << 16);
4181 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4182 I915_WRITE(reg, temp);
4183
4184 POSTING_READ(reg);
4185 udelay(100);
4186 }
4187
4188 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4189 {
4190 struct intel_crtc *crtc;
4191
4192 /* Note that we don't need to be called with mode_config.lock here
4193 * as our list of CRTC objects is static for the lifetime of the
4194 * device and so cannot disappear as we iterate. Similarly, we can
4195 * happily treat the predicates as racy, atomic checks as userspace
4196 * cannot claim and pin a new fb without at least acquring the
4197 * struct_mutex and so serialising with us.
4198 */
4199 for_each_intel_crtc(&dev_priv->drm, crtc) {
4200 if (atomic_read(&crtc->unpin_work_count) == 0)
4201 continue;
4202
4203 if (crtc->flip_work)
4204 intel_wait_for_vblank(dev_priv, crtc->pipe);
4205
4206 return true;
4207 }
4208
4209 return false;
4210 }
4211
4212 static void page_flip_completed(struct intel_crtc *intel_crtc)
4213 {
4214 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4215 struct intel_flip_work *work = intel_crtc->flip_work;
4216
4217 intel_crtc->flip_work = NULL;
4218
4219 if (work->event)
4220 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4221
4222 drm_crtc_vblank_put(&intel_crtc->base);
4223
4224 wake_up_all(&dev_priv->pending_flip_queue);
4225 trace_i915_flip_complete(intel_crtc->plane,
4226 work->pending_flip_obj);
4227
4228 queue_work(dev_priv->wq, &work->unpin_work);
4229 }
4230
4231 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4232 {
4233 struct drm_device *dev = crtc->dev;
4234 struct drm_i915_private *dev_priv = to_i915(dev);
4235 long ret;
4236
4237 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4238
4239 ret = wait_event_interruptible_timeout(
4240 dev_priv->pending_flip_queue,
4241 !intel_crtc_has_pending_flip(crtc),
4242 60*HZ);
4243
4244 if (ret < 0)
4245 return ret;
4246
4247 if (ret == 0) {
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249 struct intel_flip_work *work;
4250
4251 spin_lock_irq(&dev->event_lock);
4252 work = intel_crtc->flip_work;
4253 if (work && !is_mmio_work(work)) {
4254 WARN_ONCE(1, "Removing stuck page flip\n");
4255 page_flip_completed(intel_crtc);
4256 }
4257 spin_unlock_irq(&dev->event_lock);
4258 }
4259
4260 return 0;
4261 }
4262
4263 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4264 {
4265 u32 temp;
4266
4267 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4268
4269 mutex_lock(&dev_priv->sb_lock);
4270
4271 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4272 temp |= SBI_SSCCTL_DISABLE;
4273 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4274
4275 mutex_unlock(&dev_priv->sb_lock);
4276 }
4277
4278 /* Program iCLKIP clock to the desired frequency */
4279 static void lpt_program_iclkip(struct intel_crtc *crtc)
4280 {
4281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4282 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4283 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4284 u32 temp;
4285
4286 lpt_disable_iclkip(dev_priv);
4287
4288 /* The iCLK virtual clock root frequency is in MHz,
4289 * but the adjusted_mode->crtc_clock in in KHz. To get the
4290 * divisors, it is necessary to divide one by another, so we
4291 * convert the virtual clock precision to KHz here for higher
4292 * precision.
4293 */
4294 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4295 u32 iclk_virtual_root_freq = 172800 * 1000;
4296 u32 iclk_pi_range = 64;
4297 u32 desired_divisor;
4298
4299 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4300 clock << auxdiv);
4301 divsel = (desired_divisor / iclk_pi_range) - 2;
4302 phaseinc = desired_divisor % iclk_pi_range;
4303
4304 /*
4305 * Near 20MHz is a corner case which is
4306 * out of range for the 7-bit divisor
4307 */
4308 if (divsel <= 0x7f)
4309 break;
4310 }
4311
4312 /* This should not happen with any sane values */
4313 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4314 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4315 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4316 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4317
4318 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4319 clock,
4320 auxdiv,
4321 divsel,
4322 phasedir,
4323 phaseinc);
4324
4325 mutex_lock(&dev_priv->sb_lock);
4326
4327 /* Program SSCDIVINTPHASE6 */
4328 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4329 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4330 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4331 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4332 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4333 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4334 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4335 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4336
4337 /* Program SSCAUXDIV */
4338 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4339 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4340 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4341 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4342
4343 /* Enable modulator and associated divider */
4344 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4345 temp &= ~SBI_SSCCTL_DISABLE;
4346 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4347
4348 mutex_unlock(&dev_priv->sb_lock);
4349
4350 /* Wait for initialization time */
4351 udelay(24);
4352
4353 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4354 }
4355
4356 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4357 {
4358 u32 divsel, phaseinc, auxdiv;
4359 u32 iclk_virtual_root_freq = 172800 * 1000;
4360 u32 iclk_pi_range = 64;
4361 u32 desired_divisor;
4362 u32 temp;
4363
4364 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4365 return 0;
4366
4367 mutex_lock(&dev_priv->sb_lock);
4368
4369 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4370 if (temp & SBI_SSCCTL_DISABLE) {
4371 mutex_unlock(&dev_priv->sb_lock);
4372 return 0;
4373 }
4374
4375 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4376 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4377 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4378 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4379 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4380
4381 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4382 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4383 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4384
4385 mutex_unlock(&dev_priv->sb_lock);
4386
4387 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4388
4389 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4390 desired_divisor << auxdiv);
4391 }
4392
4393 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4394 enum pipe pch_transcoder)
4395 {
4396 struct drm_device *dev = crtc->base.dev;
4397 struct drm_i915_private *dev_priv = to_i915(dev);
4398 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4399
4400 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4401 I915_READ(HTOTAL(cpu_transcoder)));
4402 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4403 I915_READ(HBLANK(cpu_transcoder)));
4404 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4405 I915_READ(HSYNC(cpu_transcoder)));
4406
4407 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4408 I915_READ(VTOTAL(cpu_transcoder)));
4409 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4410 I915_READ(VBLANK(cpu_transcoder)));
4411 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4412 I915_READ(VSYNC(cpu_transcoder)));
4413 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4414 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4415 }
4416
4417 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4418 {
4419 struct drm_i915_private *dev_priv = to_i915(dev);
4420 uint32_t temp;
4421
4422 temp = I915_READ(SOUTH_CHICKEN1);
4423 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4424 return;
4425
4426 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4427 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4428
4429 temp &= ~FDI_BC_BIFURCATION_SELECT;
4430 if (enable)
4431 temp |= FDI_BC_BIFURCATION_SELECT;
4432
4433 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4434 I915_WRITE(SOUTH_CHICKEN1, temp);
4435 POSTING_READ(SOUTH_CHICKEN1);
4436 }
4437
4438 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4439 {
4440 struct drm_device *dev = intel_crtc->base.dev;
4441
4442 switch (intel_crtc->pipe) {
4443 case PIPE_A:
4444 break;
4445 case PIPE_B:
4446 if (intel_crtc->config->fdi_lanes > 2)
4447 cpt_set_fdi_bc_bifurcation(dev, false);
4448 else
4449 cpt_set_fdi_bc_bifurcation(dev, true);
4450
4451 break;
4452 case PIPE_C:
4453 cpt_set_fdi_bc_bifurcation(dev, true);
4454
4455 break;
4456 default:
4457 BUG();
4458 }
4459 }
4460
4461 /* Return which DP Port should be selected for Transcoder DP control */
4462 static enum port
4463 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4464 {
4465 struct drm_device *dev = crtc->base.dev;
4466 struct intel_encoder *encoder;
4467
4468 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4469 if (encoder->type == INTEL_OUTPUT_DP ||
4470 encoder->type == INTEL_OUTPUT_EDP)
4471 return enc_to_dig_port(&encoder->base)->port;
4472 }
4473
4474 return -1;
4475 }
4476
4477 /*
4478 * Enable PCH resources required for PCH ports:
4479 * - PCH PLLs
4480 * - FDI training & RX/TX
4481 * - update transcoder timings
4482 * - DP transcoding bits
4483 * - transcoder
4484 */
4485 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4486 {
4487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4488 struct drm_device *dev = crtc->base.dev;
4489 struct drm_i915_private *dev_priv = to_i915(dev);
4490 int pipe = crtc->pipe;
4491 u32 temp;
4492
4493 assert_pch_transcoder_disabled(dev_priv, pipe);
4494
4495 if (IS_IVYBRIDGE(dev_priv))
4496 ivybridge_update_fdi_bc_bifurcation(crtc);
4497
4498 /* Write the TU size bits before fdi link training, so that error
4499 * detection works. */
4500 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4501 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4502
4503 /* For PCH output, training FDI link */
4504 dev_priv->display.fdi_link_train(crtc, crtc_state);
4505
4506 /* We need to program the right clock selection before writing the pixel
4507 * mutliplier into the DPLL. */
4508 if (HAS_PCH_CPT(dev_priv)) {
4509 u32 sel;
4510
4511 temp = I915_READ(PCH_DPLL_SEL);
4512 temp |= TRANS_DPLL_ENABLE(pipe);
4513 sel = TRANS_DPLLB_SEL(pipe);
4514 if (crtc_state->shared_dpll ==
4515 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4516 temp |= sel;
4517 else
4518 temp &= ~sel;
4519 I915_WRITE(PCH_DPLL_SEL, temp);
4520 }
4521
4522 /* XXX: pch pll's can be enabled any time before we enable the PCH
4523 * transcoder, and we actually should do this to not upset any PCH
4524 * transcoder that already use the clock when we share it.
4525 *
4526 * Note that enable_shared_dpll tries to do the right thing, but
4527 * get_shared_dpll unconditionally resets the pll - we need that to have
4528 * the right LVDS enable sequence. */
4529 intel_enable_shared_dpll(crtc);
4530
4531 /* set transcoder timing, panel must allow it */
4532 assert_panel_unlocked(dev_priv, pipe);
4533 ironlake_pch_transcoder_set_timings(crtc, pipe);
4534
4535 intel_fdi_normal_train(crtc);
4536
4537 /* For PCH DP, enable TRANS_DP_CTL */
4538 if (HAS_PCH_CPT(dev_priv) &&
4539 intel_crtc_has_dp_encoder(crtc_state)) {
4540 const struct drm_display_mode *adjusted_mode =
4541 &crtc_state->base.adjusted_mode;
4542 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4543 i915_reg_t reg = TRANS_DP_CTL(pipe);
4544 temp = I915_READ(reg);
4545 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4546 TRANS_DP_SYNC_MASK |
4547 TRANS_DP_BPC_MASK);
4548 temp |= TRANS_DP_OUTPUT_ENABLE;
4549 temp |= bpc << 9; /* same format but at 11:9 */
4550
4551 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4552 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4553 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4554 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4555
4556 switch (intel_trans_dp_port_sel(crtc)) {
4557 case PORT_B:
4558 temp |= TRANS_DP_PORT_SEL_B;
4559 break;
4560 case PORT_C:
4561 temp |= TRANS_DP_PORT_SEL_C;
4562 break;
4563 case PORT_D:
4564 temp |= TRANS_DP_PORT_SEL_D;
4565 break;
4566 default:
4567 BUG();
4568 }
4569
4570 I915_WRITE(reg, temp);
4571 }
4572
4573 ironlake_enable_pch_transcoder(dev_priv, pipe);
4574 }
4575
4576 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4577 {
4578 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4580 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4581
4582 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4583
4584 lpt_program_iclkip(crtc);
4585
4586 /* Set transcoder timing. */
4587 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4588
4589 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4590 }
4591
4592 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4593 {
4594 struct drm_i915_private *dev_priv = to_i915(dev);
4595 i915_reg_t dslreg = PIPEDSL(pipe);
4596 u32 temp;
4597
4598 temp = I915_READ(dslreg);
4599 udelay(500);
4600 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4601 if (wait_for(I915_READ(dslreg) != temp, 5))
4602 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4603 }
4604 }
4605
4606 static int
4607 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4608 unsigned int scaler_user, int *scaler_id,
4609 int src_w, int src_h, int dst_w, int dst_h)
4610 {
4611 struct intel_crtc_scaler_state *scaler_state =
4612 &crtc_state->scaler_state;
4613 struct intel_crtc *intel_crtc =
4614 to_intel_crtc(crtc_state->base.crtc);
4615 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4616 const struct drm_display_mode *adjusted_mode =
4617 &crtc_state->base.adjusted_mode;
4618 int need_scaling;
4619
4620 /*
4621 * Src coordinates are already rotated by 270 degrees for
4622 * the 90/270 degree plane rotation cases (to match the
4623 * GTT mapping), hence no need to account for rotation here.
4624 */
4625 need_scaling = src_w != dst_w || src_h != dst_h;
4626
4627 /*
4628 * Scaling/fitting not supported in IF-ID mode in GEN9+
4629 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4630 * Once NV12 is enabled, handle it here while allocating scaler
4631 * for NV12.
4632 */
4633 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4634 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4635 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4636 return -EINVAL;
4637 }
4638
4639 /*
4640 * if plane is being disabled or scaler is no more required or force detach
4641 * - free scaler binded to this plane/crtc
4642 * - in order to do this, update crtc->scaler_usage
4643 *
4644 * Here scaler state in crtc_state is set free so that
4645 * scaler can be assigned to other user. Actual register
4646 * update to free the scaler is done in plane/panel-fit programming.
4647 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4648 */
4649 if (force_detach || !need_scaling) {
4650 if (*scaler_id >= 0) {
4651 scaler_state->scaler_users &= ~(1 << scaler_user);
4652 scaler_state->scalers[*scaler_id].in_use = 0;
4653
4654 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4655 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4656 intel_crtc->pipe, scaler_user, *scaler_id,
4657 scaler_state->scaler_users);
4658 *scaler_id = -1;
4659 }
4660 return 0;
4661 }
4662
4663 /* range checks */
4664 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4665 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4666
4667 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4668 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4669 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4670 "size is out of scaler range\n",
4671 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4672 return -EINVAL;
4673 }
4674
4675 /* mark this plane as a scaler user in crtc_state */
4676 scaler_state->scaler_users |= (1 << scaler_user);
4677 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4678 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4679 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4680 scaler_state->scaler_users);
4681
4682 return 0;
4683 }
4684
4685 /**
4686 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4687 *
4688 * @state: crtc's scaler state
4689 *
4690 * Return
4691 * 0 - scaler_usage updated successfully
4692 * error - requested scaling cannot be supported or other error condition
4693 */
4694 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4695 {
4696 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4697
4698 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4699 &state->scaler_state.scaler_id,
4700 state->pipe_src_w, state->pipe_src_h,
4701 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4702 }
4703
4704 /**
4705 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4706 *
4707 * @state: crtc's scaler state
4708 * @plane_state: atomic plane state to update
4709 *
4710 * Return
4711 * 0 - scaler_usage updated successfully
4712 * error - requested scaling cannot be supported or other error condition
4713 */
4714 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4715 struct intel_plane_state *plane_state)
4716 {
4717
4718 struct intel_plane *intel_plane =
4719 to_intel_plane(plane_state->base.plane);
4720 struct drm_framebuffer *fb = plane_state->base.fb;
4721 int ret;
4722
4723 bool force_detach = !fb || !plane_state->base.visible;
4724
4725 ret = skl_update_scaler(crtc_state, force_detach,
4726 drm_plane_index(&intel_plane->base),
4727 &plane_state->scaler_id,
4728 drm_rect_width(&plane_state->base.src) >> 16,
4729 drm_rect_height(&plane_state->base.src) >> 16,
4730 drm_rect_width(&plane_state->base.dst),
4731 drm_rect_height(&plane_state->base.dst));
4732
4733 if (ret || plane_state->scaler_id < 0)
4734 return ret;
4735
4736 /* check colorkey */
4737 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4738 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4739 intel_plane->base.base.id,
4740 intel_plane->base.name);
4741 return -EINVAL;
4742 }
4743
4744 /* Check src format */
4745 switch (fb->format->format) {
4746 case DRM_FORMAT_RGB565:
4747 case DRM_FORMAT_XBGR8888:
4748 case DRM_FORMAT_XRGB8888:
4749 case DRM_FORMAT_ABGR8888:
4750 case DRM_FORMAT_ARGB8888:
4751 case DRM_FORMAT_XRGB2101010:
4752 case DRM_FORMAT_XBGR2101010:
4753 case DRM_FORMAT_YUYV:
4754 case DRM_FORMAT_YVYU:
4755 case DRM_FORMAT_UYVY:
4756 case DRM_FORMAT_VYUY:
4757 break;
4758 default:
4759 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4760 intel_plane->base.base.id, intel_plane->base.name,
4761 fb->base.id, fb->format->format);
4762 return -EINVAL;
4763 }
4764
4765 return 0;
4766 }
4767
4768 static void skylake_scaler_disable(struct intel_crtc *crtc)
4769 {
4770 int i;
4771
4772 for (i = 0; i < crtc->num_scalers; i++)
4773 skl_detach_scaler(crtc, i);
4774 }
4775
4776 static void skylake_pfit_enable(struct intel_crtc *crtc)
4777 {
4778 struct drm_device *dev = crtc->base.dev;
4779 struct drm_i915_private *dev_priv = to_i915(dev);
4780 int pipe = crtc->pipe;
4781 struct intel_crtc_scaler_state *scaler_state =
4782 &crtc->config->scaler_state;
4783
4784 if (crtc->config->pch_pfit.enabled) {
4785 int id;
4786
4787 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4788 return;
4789
4790 id = scaler_state->scaler_id;
4791 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4792 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4793 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4794 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4795 }
4796 }
4797
4798 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4799 {
4800 struct drm_device *dev = crtc->base.dev;
4801 struct drm_i915_private *dev_priv = to_i915(dev);
4802 int pipe = crtc->pipe;
4803
4804 if (crtc->config->pch_pfit.enabled) {
4805 /* Force use of hard-coded filter coefficients
4806 * as some pre-programmed values are broken,
4807 * e.g. x201.
4808 */
4809 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4810 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4811 PF_PIPE_SEL_IVB(pipe));
4812 else
4813 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4814 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4815 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4816 }
4817 }
4818
4819 void hsw_enable_ips(struct intel_crtc *crtc)
4820 {
4821 struct drm_device *dev = crtc->base.dev;
4822 struct drm_i915_private *dev_priv = to_i915(dev);
4823
4824 if (!crtc->config->ips_enabled)
4825 return;
4826
4827 /*
4828 * We can only enable IPS after we enable a plane and wait for a vblank
4829 * This function is called from post_plane_update, which is run after
4830 * a vblank wait.
4831 */
4832
4833 assert_plane_enabled(dev_priv, crtc->plane);
4834 if (IS_BROADWELL(dev_priv)) {
4835 mutex_lock(&dev_priv->rps.hw_lock);
4836 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4837 mutex_unlock(&dev_priv->rps.hw_lock);
4838 /* Quoting Art Runyan: "its not safe to expect any particular
4839 * value in IPS_CTL bit 31 after enabling IPS through the
4840 * mailbox." Moreover, the mailbox may return a bogus state,
4841 * so we need to just enable it and continue on.
4842 */
4843 } else {
4844 I915_WRITE(IPS_CTL, IPS_ENABLE);
4845 /* The bit only becomes 1 in the next vblank, so this wait here
4846 * is essentially intel_wait_for_vblank. If we don't have this
4847 * and don't wait for vblanks until the end of crtc_enable, then
4848 * the HW state readout code will complain that the expected
4849 * IPS_CTL value is not the one we read. */
4850 if (intel_wait_for_register(dev_priv,
4851 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4852 50))
4853 DRM_ERROR("Timed out waiting for IPS enable\n");
4854 }
4855 }
4856
4857 void hsw_disable_ips(struct intel_crtc *crtc)
4858 {
4859 struct drm_device *dev = crtc->base.dev;
4860 struct drm_i915_private *dev_priv = to_i915(dev);
4861
4862 if (!crtc->config->ips_enabled)
4863 return;
4864
4865 assert_plane_enabled(dev_priv, crtc->plane);
4866 if (IS_BROADWELL(dev_priv)) {
4867 mutex_lock(&dev_priv->rps.hw_lock);
4868 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4869 mutex_unlock(&dev_priv->rps.hw_lock);
4870 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4871 if (intel_wait_for_register(dev_priv,
4872 IPS_CTL, IPS_ENABLE, 0,
4873 42))
4874 DRM_ERROR("Timed out waiting for IPS disable\n");
4875 } else {
4876 I915_WRITE(IPS_CTL, 0);
4877 POSTING_READ(IPS_CTL);
4878 }
4879
4880 /* We need to wait for a vblank before we can disable the plane. */
4881 intel_wait_for_vblank(dev_priv, crtc->pipe);
4882 }
4883
4884 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4885 {
4886 if (intel_crtc->overlay) {
4887 struct drm_device *dev = intel_crtc->base.dev;
4888
4889 mutex_lock(&dev->struct_mutex);
4890 (void) intel_overlay_switch_off(intel_crtc->overlay);
4891 mutex_unlock(&dev->struct_mutex);
4892 }
4893
4894 /* Let userspace switch the overlay on again. In most cases userspace
4895 * has to recompute where to put it anyway.
4896 */
4897 }
4898
4899 /**
4900 * intel_post_enable_primary - Perform operations after enabling primary plane
4901 * @crtc: the CRTC whose primary plane was just enabled
4902 *
4903 * Performs potentially sleeping operations that must be done after the primary
4904 * plane is enabled, such as updating FBC and IPS. Note that this may be
4905 * called due to an explicit primary plane update, or due to an implicit
4906 * re-enable that is caused when a sprite plane is updated to no longer
4907 * completely hide the primary plane.
4908 */
4909 static void
4910 intel_post_enable_primary(struct drm_crtc *crtc)
4911 {
4912 struct drm_device *dev = crtc->dev;
4913 struct drm_i915_private *dev_priv = to_i915(dev);
4914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915 int pipe = intel_crtc->pipe;
4916
4917 /*
4918 * FIXME IPS should be fine as long as one plane is
4919 * enabled, but in practice it seems to have problems
4920 * when going from primary only to sprite only and vice
4921 * versa.
4922 */
4923 hsw_enable_ips(intel_crtc);
4924
4925 /*
4926 * Gen2 reports pipe underruns whenever all planes are disabled.
4927 * So don't enable underrun reporting before at least some planes
4928 * are enabled.
4929 * FIXME: Need to fix the logic to work when we turn off all planes
4930 * but leave the pipe running.
4931 */
4932 if (IS_GEN2(dev_priv))
4933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934
4935 /* Underruns don't always raise interrupts, so check manually. */
4936 intel_check_cpu_fifo_underruns(dev_priv);
4937 intel_check_pch_fifo_underruns(dev_priv);
4938 }
4939
4940 /* FIXME move all this to pre_plane_update() with proper state tracking */
4941 static void
4942 intel_pre_disable_primary(struct drm_crtc *crtc)
4943 {
4944 struct drm_device *dev = crtc->dev;
4945 struct drm_i915_private *dev_priv = to_i915(dev);
4946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4947 int pipe = intel_crtc->pipe;
4948
4949 /*
4950 * Gen2 reports pipe underruns whenever all planes are disabled.
4951 * So diasble underrun reporting before all the planes get disabled.
4952 * FIXME: Need to fix the logic to work when we turn off all planes
4953 * but leave the pipe running.
4954 */
4955 if (IS_GEN2(dev_priv))
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4957
4958 /*
4959 * FIXME IPS should be fine as long as one plane is
4960 * enabled, but in practice it seems to have problems
4961 * when going from primary only to sprite only and vice
4962 * versa.
4963 */
4964 hsw_disable_ips(intel_crtc);
4965 }
4966
4967 /* FIXME get rid of this and use pre_plane_update */
4968 static void
4969 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4970 {
4971 struct drm_device *dev = crtc->dev;
4972 struct drm_i915_private *dev_priv = to_i915(dev);
4973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974 int pipe = intel_crtc->pipe;
4975
4976 intel_pre_disable_primary(crtc);
4977
4978 /*
4979 * Vblank time updates from the shadow to live plane control register
4980 * are blocked if the memory self-refresh mode is active at that
4981 * moment. So to make sure the plane gets truly disabled, disable
4982 * first the self-refresh mode. The self-refresh enable bit in turn
4983 * will be checked/applied by the HW only at the next frame start
4984 * event which is after the vblank start event, so we need to have a
4985 * wait-for-vblank between disabling the plane and the pipe.
4986 */
4987 if (HAS_GMCH_DISPLAY(dev_priv) &&
4988 intel_set_memory_cxsr(dev_priv, false))
4989 intel_wait_for_vblank(dev_priv, pipe);
4990 }
4991
4992 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4993 {
4994 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4995 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4996 struct intel_crtc_state *pipe_config =
4997 to_intel_crtc_state(crtc->base.state);
4998 struct drm_plane *primary = crtc->base.primary;
4999 struct drm_plane_state *old_pri_state =
5000 drm_atomic_get_existing_plane_state(old_state, primary);
5001
5002 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5003
5004 if (pipe_config->update_wm_post && pipe_config->base.active)
5005 intel_update_watermarks(crtc);
5006
5007 if (old_pri_state) {
5008 struct intel_plane_state *primary_state =
5009 to_intel_plane_state(primary->state);
5010 struct intel_plane_state *old_primary_state =
5011 to_intel_plane_state(old_pri_state);
5012
5013 intel_fbc_post_update(crtc);
5014
5015 if (primary_state->base.visible &&
5016 (needs_modeset(&pipe_config->base) ||
5017 !old_primary_state->base.visible))
5018 intel_post_enable_primary(&crtc->base);
5019 }
5020 }
5021
5022 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5023 struct intel_crtc_state *pipe_config)
5024 {
5025 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5026 struct drm_device *dev = crtc->base.dev;
5027 struct drm_i915_private *dev_priv = to_i915(dev);
5028 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5029 struct drm_plane *primary = crtc->base.primary;
5030 struct drm_plane_state *old_pri_state =
5031 drm_atomic_get_existing_plane_state(old_state, primary);
5032 bool modeset = needs_modeset(&pipe_config->base);
5033 struct intel_atomic_state *old_intel_state =
5034 to_intel_atomic_state(old_state);
5035
5036 if (old_pri_state) {
5037 struct intel_plane_state *primary_state =
5038 to_intel_plane_state(primary->state);
5039 struct intel_plane_state *old_primary_state =
5040 to_intel_plane_state(old_pri_state);
5041
5042 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5043
5044 if (old_primary_state->base.visible &&
5045 (modeset || !primary_state->base.visible))
5046 intel_pre_disable_primary(&crtc->base);
5047 }
5048
5049 /*
5050 * Vblank time updates from the shadow to live plane control register
5051 * are blocked if the memory self-refresh mode is active at that
5052 * moment. So to make sure the plane gets truly disabled, disable
5053 * first the self-refresh mode. The self-refresh enable bit in turn
5054 * will be checked/applied by the HW only at the next frame start
5055 * event which is after the vblank start event, so we need to have a
5056 * wait-for-vblank between disabling the plane and the pipe.
5057 */
5058 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5059 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5060 intel_wait_for_vblank(dev_priv, crtc->pipe);
5061
5062 /*
5063 * IVB workaround: must disable low power watermarks for at least
5064 * one frame before enabling scaling. LP watermarks can be re-enabled
5065 * when scaling is disabled.
5066 *
5067 * WaCxSRDisabledForSpriteScaling:ivb
5068 */
5069 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5070 intel_wait_for_vblank(dev_priv, crtc->pipe);
5071
5072 /*
5073 * If we're doing a modeset, we're done. No need to do any pre-vblank
5074 * watermark programming here.
5075 */
5076 if (needs_modeset(&pipe_config->base))
5077 return;
5078
5079 /*
5080 * For platforms that support atomic watermarks, program the
5081 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5082 * will be the intermediate values that are safe for both pre- and
5083 * post- vblank; when vblank happens, the 'active' values will be set
5084 * to the final 'target' values and we'll do this again to get the
5085 * optimal watermarks. For gen9+ platforms, the values we program here
5086 * will be the final target values which will get automatically latched
5087 * at vblank time; no further programming will be necessary.
5088 *
5089 * If a platform hasn't been transitioned to atomic watermarks yet,
5090 * we'll continue to update watermarks the old way, if flags tell
5091 * us to.
5092 */
5093 if (dev_priv->display.initial_watermarks != NULL)
5094 dev_priv->display.initial_watermarks(old_intel_state,
5095 pipe_config);
5096 else if (pipe_config->update_wm_pre)
5097 intel_update_watermarks(crtc);
5098 }
5099
5100 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5101 {
5102 struct drm_device *dev = crtc->dev;
5103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5104 struct drm_plane *p;
5105 int pipe = intel_crtc->pipe;
5106
5107 intel_crtc_dpms_overlay_disable(intel_crtc);
5108
5109 drm_for_each_plane_mask(p, dev, plane_mask)
5110 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5111
5112 /*
5113 * FIXME: Once we grow proper nuclear flip support out of this we need
5114 * to compute the mask of flip planes precisely. For the time being
5115 * consider this a flip to a NULL plane.
5116 */
5117 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5118 }
5119
5120 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5121 struct intel_crtc_state *crtc_state,
5122 struct drm_atomic_state *old_state)
5123 {
5124 struct drm_connector_state *conn_state;
5125 struct drm_connector *conn;
5126 int i;
5127
5128 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5129 struct intel_encoder *encoder =
5130 to_intel_encoder(conn_state->best_encoder);
5131
5132 if (conn_state->crtc != crtc)
5133 continue;
5134
5135 if (encoder->pre_pll_enable)
5136 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5137 }
5138 }
5139
5140 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5141 struct intel_crtc_state *crtc_state,
5142 struct drm_atomic_state *old_state)
5143 {
5144 struct drm_connector_state *conn_state;
5145 struct drm_connector *conn;
5146 int i;
5147
5148 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5149 struct intel_encoder *encoder =
5150 to_intel_encoder(conn_state->best_encoder);
5151
5152 if (conn_state->crtc != crtc)
5153 continue;
5154
5155 if (encoder->pre_enable)
5156 encoder->pre_enable(encoder, crtc_state, conn_state);
5157 }
5158 }
5159
5160 static void intel_encoders_enable(struct drm_crtc *crtc,
5161 struct intel_crtc_state *crtc_state,
5162 struct drm_atomic_state *old_state)
5163 {
5164 struct drm_connector_state *conn_state;
5165 struct drm_connector *conn;
5166 int i;
5167
5168 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5169 struct intel_encoder *encoder =
5170 to_intel_encoder(conn_state->best_encoder);
5171
5172 if (conn_state->crtc != crtc)
5173 continue;
5174
5175 encoder->enable(encoder, crtc_state, conn_state);
5176 intel_opregion_notify_encoder(encoder, true);
5177 }
5178 }
5179
5180 static void intel_encoders_disable(struct drm_crtc *crtc,
5181 struct intel_crtc_state *old_crtc_state,
5182 struct drm_atomic_state *old_state)
5183 {
5184 struct drm_connector_state *old_conn_state;
5185 struct drm_connector *conn;
5186 int i;
5187
5188 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5189 struct intel_encoder *encoder =
5190 to_intel_encoder(old_conn_state->best_encoder);
5191
5192 if (old_conn_state->crtc != crtc)
5193 continue;
5194
5195 intel_opregion_notify_encoder(encoder, false);
5196 encoder->disable(encoder, old_crtc_state, old_conn_state);
5197 }
5198 }
5199
5200 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5201 struct intel_crtc_state *old_crtc_state,
5202 struct drm_atomic_state *old_state)
5203 {
5204 struct drm_connector_state *old_conn_state;
5205 struct drm_connector *conn;
5206 int i;
5207
5208 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5209 struct intel_encoder *encoder =
5210 to_intel_encoder(old_conn_state->best_encoder);
5211
5212 if (old_conn_state->crtc != crtc)
5213 continue;
5214
5215 if (encoder->post_disable)
5216 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5217 }
5218 }
5219
5220 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5221 struct intel_crtc_state *old_crtc_state,
5222 struct drm_atomic_state *old_state)
5223 {
5224 struct drm_connector_state *old_conn_state;
5225 struct drm_connector *conn;
5226 int i;
5227
5228 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5229 struct intel_encoder *encoder =
5230 to_intel_encoder(old_conn_state->best_encoder);
5231
5232 if (old_conn_state->crtc != crtc)
5233 continue;
5234
5235 if (encoder->post_pll_disable)
5236 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5237 }
5238 }
5239
5240 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5241 struct drm_atomic_state *old_state)
5242 {
5243 struct drm_crtc *crtc = pipe_config->base.crtc;
5244 struct drm_device *dev = crtc->dev;
5245 struct drm_i915_private *dev_priv = to_i915(dev);
5246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5247 int pipe = intel_crtc->pipe;
5248 struct intel_atomic_state *old_intel_state =
5249 to_intel_atomic_state(old_state);
5250
5251 if (WARN_ON(intel_crtc->active))
5252 return;
5253
5254 /*
5255 * Sometimes spurious CPU pipe underruns happen during FDI
5256 * training, at least with VGA+HDMI cloning. Suppress them.
5257 *
5258 * On ILK we get an occasional spurious CPU pipe underruns
5259 * between eDP port A enable and vdd enable. Also PCH port
5260 * enable seems to result in the occasional CPU pipe underrun.
5261 *
5262 * Spurious PCH underruns also occur during PCH enabling.
5263 */
5264 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5265 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5266 if (intel_crtc->config->has_pch_encoder)
5267 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5268
5269 if (intel_crtc->config->has_pch_encoder)
5270 intel_prepare_shared_dpll(intel_crtc);
5271
5272 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5273 intel_dp_set_m_n(intel_crtc, M1_N1);
5274
5275 intel_set_pipe_timings(intel_crtc);
5276 intel_set_pipe_src_size(intel_crtc);
5277
5278 if (intel_crtc->config->has_pch_encoder) {
5279 intel_cpu_transcoder_set_m_n(intel_crtc,
5280 &intel_crtc->config->fdi_m_n, NULL);
5281 }
5282
5283 ironlake_set_pipeconf(crtc);
5284
5285 intel_crtc->active = true;
5286
5287 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5288
5289 if (intel_crtc->config->has_pch_encoder) {
5290 /* Note: FDI PLL enabling _must_ be done before we enable the
5291 * cpu pipes, hence this is separate from all the other fdi/pch
5292 * enabling. */
5293 ironlake_fdi_pll_enable(intel_crtc);
5294 } else {
5295 assert_fdi_tx_disabled(dev_priv, pipe);
5296 assert_fdi_rx_disabled(dev_priv, pipe);
5297 }
5298
5299 ironlake_pfit_enable(intel_crtc);
5300
5301 /*
5302 * On ILK+ LUT must be loaded before the pipe is running but with
5303 * clocks enabled
5304 */
5305 intel_color_load_luts(&pipe_config->base);
5306
5307 if (dev_priv->display.initial_watermarks != NULL)
5308 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5309 intel_enable_pipe(intel_crtc);
5310
5311 if (intel_crtc->config->has_pch_encoder)
5312 ironlake_pch_enable(pipe_config);
5313
5314 assert_vblank_disabled(crtc);
5315 drm_crtc_vblank_on(crtc);
5316
5317 intel_encoders_enable(crtc, pipe_config, old_state);
5318
5319 if (HAS_PCH_CPT(dev_priv))
5320 cpt_verify_modeset(dev, intel_crtc->pipe);
5321
5322 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5323 if (intel_crtc->config->has_pch_encoder)
5324 intel_wait_for_vblank(dev_priv, pipe);
5325 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5326 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5327 }
5328
5329 /* IPS only exists on ULT machines and is tied to pipe A. */
5330 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5331 {
5332 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5333 }
5334
5335 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5336 struct drm_atomic_state *old_state)
5337 {
5338 struct drm_crtc *crtc = pipe_config->base.crtc;
5339 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5341 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5342 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5343 struct intel_atomic_state *old_intel_state =
5344 to_intel_atomic_state(old_state);
5345
5346 if (WARN_ON(intel_crtc->active))
5347 return;
5348
5349 if (intel_crtc->config->has_pch_encoder)
5350 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5351 false);
5352
5353 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5354
5355 if (intel_crtc->config->shared_dpll)
5356 intel_enable_shared_dpll(intel_crtc);
5357
5358 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5359 intel_dp_set_m_n(intel_crtc, M1_N1);
5360
5361 if (!transcoder_is_dsi(cpu_transcoder))
5362 intel_set_pipe_timings(intel_crtc);
5363
5364 intel_set_pipe_src_size(intel_crtc);
5365
5366 if (cpu_transcoder != TRANSCODER_EDP &&
5367 !transcoder_is_dsi(cpu_transcoder)) {
5368 I915_WRITE(PIPE_MULT(cpu_transcoder),
5369 intel_crtc->config->pixel_multiplier - 1);
5370 }
5371
5372 if (intel_crtc->config->has_pch_encoder) {
5373 intel_cpu_transcoder_set_m_n(intel_crtc,
5374 &intel_crtc->config->fdi_m_n, NULL);
5375 }
5376
5377 if (!transcoder_is_dsi(cpu_transcoder))
5378 haswell_set_pipeconf(crtc);
5379
5380 haswell_set_pipemisc(crtc);
5381
5382 intel_color_set_csc(&pipe_config->base);
5383
5384 intel_crtc->active = true;
5385
5386 if (intel_crtc->config->has_pch_encoder)
5387 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5388 else
5389 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5390
5391 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5392
5393 if (intel_crtc->config->has_pch_encoder)
5394 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5395
5396 if (!transcoder_is_dsi(cpu_transcoder))
5397 intel_ddi_enable_pipe_clock(pipe_config);
5398
5399 if (INTEL_GEN(dev_priv) >= 9)
5400 skylake_pfit_enable(intel_crtc);
5401 else
5402 ironlake_pfit_enable(intel_crtc);
5403
5404 /*
5405 * On ILK+ LUT must be loaded before the pipe is running but with
5406 * clocks enabled
5407 */
5408 intel_color_load_luts(&pipe_config->base);
5409
5410 intel_ddi_set_pipe_settings(pipe_config);
5411 if (!transcoder_is_dsi(cpu_transcoder))
5412 intel_ddi_enable_transcoder_func(pipe_config);
5413
5414 if (dev_priv->display.initial_watermarks != NULL)
5415 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5416
5417 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5418 if (!transcoder_is_dsi(cpu_transcoder))
5419 intel_enable_pipe(intel_crtc);
5420
5421 if (intel_crtc->config->has_pch_encoder)
5422 lpt_pch_enable(pipe_config);
5423
5424 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5425 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5426
5427 assert_vblank_disabled(crtc);
5428 drm_crtc_vblank_on(crtc);
5429
5430 intel_encoders_enable(crtc, pipe_config, old_state);
5431
5432 if (intel_crtc->config->has_pch_encoder) {
5433 intel_wait_for_vblank(dev_priv, pipe);
5434 intel_wait_for_vblank(dev_priv, pipe);
5435 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5436 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5437 true);
5438 }
5439
5440 /* If we change the relative order between pipe/planes enabling, we need
5441 * to change the workaround. */
5442 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5443 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5444 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5445 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5446 }
5447 }
5448
5449 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5450 {
5451 struct drm_device *dev = crtc->base.dev;
5452 struct drm_i915_private *dev_priv = to_i915(dev);
5453 int pipe = crtc->pipe;
5454
5455 /* To avoid upsetting the power well on haswell only disable the pfit if
5456 * it's in use. The hw state code will make sure we get this right. */
5457 if (force || crtc->config->pch_pfit.enabled) {
5458 I915_WRITE(PF_CTL(pipe), 0);
5459 I915_WRITE(PF_WIN_POS(pipe), 0);
5460 I915_WRITE(PF_WIN_SZ(pipe), 0);
5461 }
5462 }
5463
5464 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5465 struct drm_atomic_state *old_state)
5466 {
5467 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5468 struct drm_device *dev = crtc->dev;
5469 struct drm_i915_private *dev_priv = to_i915(dev);
5470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5471 int pipe = intel_crtc->pipe;
5472
5473 /*
5474 * Sometimes spurious CPU pipe underruns happen when the
5475 * pipe is already disabled, but FDI RX/TX is still enabled.
5476 * Happens at least with VGA+HDMI cloning. Suppress them.
5477 */
5478 if (intel_crtc->config->has_pch_encoder) {
5479 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5480 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5481 }
5482
5483 intel_encoders_disable(crtc, old_crtc_state, old_state);
5484
5485 drm_crtc_vblank_off(crtc);
5486 assert_vblank_disabled(crtc);
5487
5488 intel_disable_pipe(intel_crtc);
5489
5490 ironlake_pfit_disable(intel_crtc, false);
5491
5492 if (intel_crtc->config->has_pch_encoder)
5493 ironlake_fdi_disable(crtc);
5494
5495 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5496
5497 if (intel_crtc->config->has_pch_encoder) {
5498 ironlake_disable_pch_transcoder(dev_priv, pipe);
5499
5500 if (HAS_PCH_CPT(dev_priv)) {
5501 i915_reg_t reg;
5502 u32 temp;
5503
5504 /* disable TRANS_DP_CTL */
5505 reg = TRANS_DP_CTL(pipe);
5506 temp = I915_READ(reg);
5507 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5508 TRANS_DP_PORT_SEL_MASK);
5509 temp |= TRANS_DP_PORT_SEL_NONE;
5510 I915_WRITE(reg, temp);
5511
5512 /* disable DPLL_SEL */
5513 temp = I915_READ(PCH_DPLL_SEL);
5514 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5515 I915_WRITE(PCH_DPLL_SEL, temp);
5516 }
5517
5518 ironlake_fdi_pll_disable(intel_crtc);
5519 }
5520
5521 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5522 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5523 }
5524
5525 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5526 struct drm_atomic_state *old_state)
5527 {
5528 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5529 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5531 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5532
5533 if (intel_crtc->config->has_pch_encoder)
5534 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5535 false);
5536
5537 intel_encoders_disable(crtc, old_crtc_state, old_state);
5538
5539 drm_crtc_vblank_off(crtc);
5540 assert_vblank_disabled(crtc);
5541
5542 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5543 if (!transcoder_is_dsi(cpu_transcoder))
5544 intel_disable_pipe(intel_crtc);
5545
5546 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5547 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5548
5549 if (!transcoder_is_dsi(cpu_transcoder))
5550 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5551
5552 if (INTEL_GEN(dev_priv) >= 9)
5553 skylake_scaler_disable(intel_crtc);
5554 else
5555 ironlake_pfit_disable(intel_crtc, false);
5556
5557 if (!transcoder_is_dsi(cpu_transcoder))
5558 intel_ddi_disable_pipe_clock(intel_crtc->config);
5559
5560 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5561
5562 if (old_crtc_state->has_pch_encoder)
5563 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5564 true);
5565 }
5566
5567 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5568 {
5569 struct drm_device *dev = crtc->base.dev;
5570 struct drm_i915_private *dev_priv = to_i915(dev);
5571 struct intel_crtc_state *pipe_config = crtc->config;
5572
5573 if (!pipe_config->gmch_pfit.control)
5574 return;
5575
5576 /*
5577 * The panel fitter should only be adjusted whilst the pipe is disabled,
5578 * according to register description and PRM.
5579 */
5580 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5581 assert_pipe_disabled(dev_priv, crtc->pipe);
5582
5583 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5584 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5585
5586 /* Border color in case we don't scale up to the full screen. Black by
5587 * default, change to something else for debugging. */
5588 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5589 }
5590
5591 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5592 {
5593 switch (port) {
5594 case PORT_A:
5595 return POWER_DOMAIN_PORT_DDI_A_LANES;
5596 case PORT_B:
5597 return POWER_DOMAIN_PORT_DDI_B_LANES;
5598 case PORT_C:
5599 return POWER_DOMAIN_PORT_DDI_C_LANES;
5600 case PORT_D:
5601 return POWER_DOMAIN_PORT_DDI_D_LANES;
5602 case PORT_E:
5603 return POWER_DOMAIN_PORT_DDI_E_LANES;
5604 default:
5605 MISSING_CASE(port);
5606 return POWER_DOMAIN_PORT_OTHER;
5607 }
5608 }
5609
5610 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5611 struct intel_crtc_state *crtc_state)
5612 {
5613 struct drm_device *dev = crtc->dev;
5614 struct drm_i915_private *dev_priv = to_i915(dev);
5615 struct drm_encoder *encoder;
5616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5617 enum pipe pipe = intel_crtc->pipe;
5618 u64 mask;
5619 enum transcoder transcoder = crtc_state->cpu_transcoder;
5620
5621 if (!crtc_state->base.active)
5622 return 0;
5623
5624 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5625 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5626 if (crtc_state->pch_pfit.enabled ||
5627 crtc_state->pch_pfit.force_thru)
5628 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5629
5630 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5631 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5632
5633 mask |= BIT_ULL(intel_encoder->power_domain);
5634 }
5635
5636 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5637 mask |= BIT(POWER_DOMAIN_AUDIO);
5638
5639 if (crtc_state->shared_dpll)
5640 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5641
5642 return mask;
5643 }
5644
5645 static u64
5646 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5647 struct intel_crtc_state *crtc_state)
5648 {
5649 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5651 enum intel_display_power_domain domain;
5652 u64 domains, new_domains, old_domains;
5653
5654 old_domains = intel_crtc->enabled_power_domains;
5655 intel_crtc->enabled_power_domains = new_domains =
5656 get_crtc_power_domains(crtc, crtc_state);
5657
5658 domains = new_domains & ~old_domains;
5659
5660 for_each_power_domain(domain, domains)
5661 intel_display_power_get(dev_priv, domain);
5662
5663 return old_domains & ~new_domains;
5664 }
5665
5666 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5667 u64 domains)
5668 {
5669 enum intel_display_power_domain domain;
5670
5671 for_each_power_domain(domain, domains)
5672 intel_display_power_put(dev_priv, domain);
5673 }
5674
5675 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5676 struct drm_atomic_state *old_state)
5677 {
5678 struct intel_atomic_state *old_intel_state =
5679 to_intel_atomic_state(old_state);
5680 struct drm_crtc *crtc = pipe_config->base.crtc;
5681 struct drm_device *dev = crtc->dev;
5682 struct drm_i915_private *dev_priv = to_i915(dev);
5683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5684 int pipe = intel_crtc->pipe;
5685
5686 if (WARN_ON(intel_crtc->active))
5687 return;
5688
5689 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5690 intel_dp_set_m_n(intel_crtc, M1_N1);
5691
5692 intel_set_pipe_timings(intel_crtc);
5693 intel_set_pipe_src_size(intel_crtc);
5694
5695 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5696 struct drm_i915_private *dev_priv = to_i915(dev);
5697
5698 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5699 I915_WRITE(CHV_CANVAS(pipe), 0);
5700 }
5701
5702 i9xx_set_pipeconf(intel_crtc);
5703
5704 intel_crtc->active = true;
5705
5706 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5707
5708 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5709
5710 if (IS_CHERRYVIEW(dev_priv)) {
5711 chv_prepare_pll(intel_crtc, intel_crtc->config);
5712 chv_enable_pll(intel_crtc, intel_crtc->config);
5713 } else {
5714 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5715 vlv_enable_pll(intel_crtc, intel_crtc->config);
5716 }
5717
5718 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5719
5720 i9xx_pfit_enable(intel_crtc);
5721
5722 intel_color_load_luts(&pipe_config->base);
5723
5724 dev_priv->display.initial_watermarks(old_intel_state,
5725 pipe_config);
5726 intel_enable_pipe(intel_crtc);
5727
5728 assert_vblank_disabled(crtc);
5729 drm_crtc_vblank_on(crtc);
5730
5731 intel_encoders_enable(crtc, pipe_config, old_state);
5732 }
5733
5734 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5735 {
5736 struct drm_device *dev = crtc->base.dev;
5737 struct drm_i915_private *dev_priv = to_i915(dev);
5738
5739 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5740 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5741 }
5742
5743 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5744 struct drm_atomic_state *old_state)
5745 {
5746 struct intel_atomic_state *old_intel_state =
5747 to_intel_atomic_state(old_state);
5748 struct drm_crtc *crtc = pipe_config->base.crtc;
5749 struct drm_device *dev = crtc->dev;
5750 struct drm_i915_private *dev_priv = to_i915(dev);
5751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5752 enum pipe pipe = intel_crtc->pipe;
5753
5754 if (WARN_ON(intel_crtc->active))
5755 return;
5756
5757 i9xx_set_pll_dividers(intel_crtc);
5758
5759 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5760 intel_dp_set_m_n(intel_crtc, M1_N1);
5761
5762 intel_set_pipe_timings(intel_crtc);
5763 intel_set_pipe_src_size(intel_crtc);
5764
5765 i9xx_set_pipeconf(intel_crtc);
5766
5767 intel_crtc->active = true;
5768
5769 if (!IS_GEN2(dev_priv))
5770 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5771
5772 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5773
5774 i9xx_enable_pll(intel_crtc);
5775
5776 i9xx_pfit_enable(intel_crtc);
5777
5778 intel_color_load_luts(&pipe_config->base);
5779
5780 if (dev_priv->display.initial_watermarks != NULL)
5781 dev_priv->display.initial_watermarks(old_intel_state,
5782 intel_crtc->config);
5783 else
5784 intel_update_watermarks(intel_crtc);
5785 intel_enable_pipe(intel_crtc);
5786
5787 assert_vblank_disabled(crtc);
5788 drm_crtc_vblank_on(crtc);
5789
5790 intel_encoders_enable(crtc, pipe_config, old_state);
5791 }
5792
5793 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5794 {
5795 struct drm_device *dev = crtc->base.dev;
5796 struct drm_i915_private *dev_priv = to_i915(dev);
5797
5798 if (!crtc->config->gmch_pfit.control)
5799 return;
5800
5801 assert_pipe_disabled(dev_priv, crtc->pipe);
5802
5803 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5804 I915_READ(PFIT_CONTROL));
5805 I915_WRITE(PFIT_CONTROL, 0);
5806 }
5807
5808 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5809 struct drm_atomic_state *old_state)
5810 {
5811 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5812 struct drm_device *dev = crtc->dev;
5813 struct drm_i915_private *dev_priv = to_i915(dev);
5814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5815 int pipe = intel_crtc->pipe;
5816
5817 /*
5818 * On gen2 planes are double buffered but the pipe isn't, so we must
5819 * wait for planes to fully turn off before disabling the pipe.
5820 */
5821 if (IS_GEN2(dev_priv))
5822 intel_wait_for_vblank(dev_priv, pipe);
5823
5824 intel_encoders_disable(crtc, old_crtc_state, old_state);
5825
5826 drm_crtc_vblank_off(crtc);
5827 assert_vblank_disabled(crtc);
5828
5829 intel_disable_pipe(intel_crtc);
5830
5831 i9xx_pfit_disable(intel_crtc);
5832
5833 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5834
5835 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5836 if (IS_CHERRYVIEW(dev_priv))
5837 chv_disable_pll(dev_priv, pipe);
5838 else if (IS_VALLEYVIEW(dev_priv))
5839 vlv_disable_pll(dev_priv, pipe);
5840 else
5841 i9xx_disable_pll(intel_crtc);
5842 }
5843
5844 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5845
5846 if (!IS_GEN2(dev_priv))
5847 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5848
5849 if (!dev_priv->display.initial_watermarks)
5850 intel_update_watermarks(intel_crtc);
5851
5852 /* clock the pipe down to 640x480@60 to potentially save power */
5853 if (IS_I830(dev_priv))
5854 i830_enable_pipe(dev_priv, pipe);
5855 }
5856
5857 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5858 struct drm_modeset_acquire_ctx *ctx)
5859 {
5860 struct intel_encoder *encoder;
5861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5862 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5863 enum intel_display_power_domain domain;
5864 u64 domains;
5865 struct drm_atomic_state *state;
5866 struct intel_crtc_state *crtc_state;
5867 int ret;
5868
5869 if (!intel_crtc->active)
5870 return;
5871
5872 if (crtc->primary->state->visible) {
5873 WARN_ON(intel_crtc->flip_work);
5874
5875 intel_pre_disable_primary_noatomic(crtc);
5876
5877 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5878 crtc->primary->state->visible = false;
5879 }
5880
5881 state = drm_atomic_state_alloc(crtc->dev);
5882 if (!state) {
5883 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5884 crtc->base.id, crtc->name);
5885 return;
5886 }
5887
5888 state->acquire_ctx = ctx;
5889
5890 /* Everything's already locked, -EDEADLK can't happen. */
5891 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5892 ret = drm_atomic_add_affected_connectors(state, crtc);
5893
5894 WARN_ON(IS_ERR(crtc_state) || ret);
5895
5896 dev_priv->display.crtc_disable(crtc_state, state);
5897
5898 drm_atomic_state_put(state);
5899
5900 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5901 crtc->base.id, crtc->name);
5902
5903 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5904 crtc->state->active = false;
5905 intel_crtc->active = false;
5906 crtc->enabled = false;
5907 crtc->state->connector_mask = 0;
5908 crtc->state->encoder_mask = 0;
5909
5910 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5911 encoder->base.crtc = NULL;
5912
5913 intel_fbc_disable(intel_crtc);
5914 intel_update_watermarks(intel_crtc);
5915 intel_disable_shared_dpll(intel_crtc);
5916
5917 domains = intel_crtc->enabled_power_domains;
5918 for_each_power_domain(domain, domains)
5919 intel_display_power_put(dev_priv, domain);
5920 intel_crtc->enabled_power_domains = 0;
5921
5922 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5923 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5924 }
5925
5926 /*
5927 * turn all crtc's off, but do not adjust state
5928 * This has to be paired with a call to intel_modeset_setup_hw_state.
5929 */
5930 int intel_display_suspend(struct drm_device *dev)
5931 {
5932 struct drm_i915_private *dev_priv = to_i915(dev);
5933 struct drm_atomic_state *state;
5934 int ret;
5935
5936 state = drm_atomic_helper_suspend(dev);
5937 ret = PTR_ERR_OR_ZERO(state);
5938 if (ret)
5939 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5940 else
5941 dev_priv->modeset_restore_state = state;
5942 return ret;
5943 }
5944
5945 void intel_encoder_destroy(struct drm_encoder *encoder)
5946 {
5947 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5948
5949 drm_encoder_cleanup(encoder);
5950 kfree(intel_encoder);
5951 }
5952
5953 /* Cross check the actual hw state with our own modeset state tracking (and it's
5954 * internal consistency). */
5955 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5956 struct drm_connector_state *conn_state)
5957 {
5958 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5959
5960 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5961 connector->base.base.id,
5962 connector->base.name);
5963
5964 if (connector->get_hw_state(connector)) {
5965 struct intel_encoder *encoder = connector->encoder;
5966
5967 I915_STATE_WARN(!crtc_state,
5968 "connector enabled without attached crtc\n");
5969
5970 if (!crtc_state)
5971 return;
5972
5973 I915_STATE_WARN(!crtc_state->active,
5974 "connector is active, but attached crtc isn't\n");
5975
5976 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5977 return;
5978
5979 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5980 "atomic encoder doesn't match attached encoder\n");
5981
5982 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5983 "attached encoder crtc differs from connector crtc\n");
5984 } else {
5985 I915_STATE_WARN(crtc_state && crtc_state->active,
5986 "attached crtc is active, but connector isn't\n");
5987 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5988 "best encoder set without crtc!\n");
5989 }
5990 }
5991
5992 int intel_connector_init(struct intel_connector *connector)
5993 {
5994 struct intel_digital_connector_state *conn_state;
5995
5996 /*
5997 * Allocate enough memory to hold intel_digital_connector_state,
5998 * This might be a few bytes too many, but for connectors that don't
5999 * need it we'll free the state and allocate a smaller one on the first
6000 * succesful commit anyway.
6001 */
6002 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6003 if (!conn_state)
6004 return -ENOMEM;
6005
6006 __drm_atomic_helper_connector_reset(&connector->base,
6007 &conn_state->base);
6008
6009 return 0;
6010 }
6011
6012 struct intel_connector *intel_connector_alloc(void)
6013 {
6014 struct intel_connector *connector;
6015
6016 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6017 if (!connector)
6018 return NULL;
6019
6020 if (intel_connector_init(connector) < 0) {
6021 kfree(connector);
6022 return NULL;
6023 }
6024
6025 return connector;
6026 }
6027
6028 /* Simple connector->get_hw_state implementation for encoders that support only
6029 * one connector and no cloning and hence the encoder state determines the state
6030 * of the connector. */
6031 bool intel_connector_get_hw_state(struct intel_connector *connector)
6032 {
6033 enum pipe pipe = 0;
6034 struct intel_encoder *encoder = connector->encoder;
6035
6036 return encoder->get_hw_state(encoder, &pipe);
6037 }
6038
6039 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6040 {
6041 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6042 return crtc_state->fdi_lanes;
6043
6044 return 0;
6045 }
6046
6047 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6048 struct intel_crtc_state *pipe_config)
6049 {
6050 struct drm_i915_private *dev_priv = to_i915(dev);
6051 struct drm_atomic_state *state = pipe_config->base.state;
6052 struct intel_crtc *other_crtc;
6053 struct intel_crtc_state *other_crtc_state;
6054
6055 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6056 pipe_name(pipe), pipe_config->fdi_lanes);
6057 if (pipe_config->fdi_lanes > 4) {
6058 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6059 pipe_name(pipe), pipe_config->fdi_lanes);
6060 return -EINVAL;
6061 }
6062
6063 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6064 if (pipe_config->fdi_lanes > 2) {
6065 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6066 pipe_config->fdi_lanes);
6067 return -EINVAL;
6068 } else {
6069 return 0;
6070 }
6071 }
6072
6073 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6074 return 0;
6075
6076 /* Ivybridge 3 pipe is really complicated */
6077 switch (pipe) {
6078 case PIPE_A:
6079 return 0;
6080 case PIPE_B:
6081 if (pipe_config->fdi_lanes <= 2)
6082 return 0;
6083
6084 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6085 other_crtc_state =
6086 intel_atomic_get_crtc_state(state, other_crtc);
6087 if (IS_ERR(other_crtc_state))
6088 return PTR_ERR(other_crtc_state);
6089
6090 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6091 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6092 pipe_name(pipe), pipe_config->fdi_lanes);
6093 return -EINVAL;
6094 }
6095 return 0;
6096 case PIPE_C:
6097 if (pipe_config->fdi_lanes > 2) {
6098 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6099 pipe_name(pipe), pipe_config->fdi_lanes);
6100 return -EINVAL;
6101 }
6102
6103 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6104 other_crtc_state =
6105 intel_atomic_get_crtc_state(state, other_crtc);
6106 if (IS_ERR(other_crtc_state))
6107 return PTR_ERR(other_crtc_state);
6108
6109 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6110 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6111 return -EINVAL;
6112 }
6113 return 0;
6114 default:
6115 BUG();
6116 }
6117 }
6118
6119 #define RETRY 1
6120 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6121 struct intel_crtc_state *pipe_config)
6122 {
6123 struct drm_device *dev = intel_crtc->base.dev;
6124 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6125 int lane, link_bw, fdi_dotclock, ret;
6126 bool needs_recompute = false;
6127
6128 retry:
6129 /* FDI is a binary signal running at ~2.7GHz, encoding
6130 * each output octet as 10 bits. The actual frequency
6131 * is stored as a divider into a 100MHz clock, and the
6132 * mode pixel clock is stored in units of 1KHz.
6133 * Hence the bw of each lane in terms of the mode signal
6134 * is:
6135 */
6136 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6137
6138 fdi_dotclock = adjusted_mode->crtc_clock;
6139
6140 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6141 pipe_config->pipe_bpp);
6142
6143 pipe_config->fdi_lanes = lane;
6144
6145 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6146 link_bw, &pipe_config->fdi_m_n);
6147
6148 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6149 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6150 pipe_config->pipe_bpp -= 2*3;
6151 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6152 pipe_config->pipe_bpp);
6153 needs_recompute = true;
6154 pipe_config->bw_constrained = true;
6155
6156 goto retry;
6157 }
6158
6159 if (needs_recompute)
6160 return RETRY;
6161
6162 return ret;
6163 }
6164
6165 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6166 struct intel_crtc_state *pipe_config)
6167 {
6168 if (pipe_config->pipe_bpp > 24)
6169 return false;
6170
6171 /* HSW can handle pixel rate up to cdclk? */
6172 if (IS_HASWELL(dev_priv))
6173 return true;
6174
6175 /*
6176 * We compare against max which means we must take
6177 * the increased cdclk requirement into account when
6178 * calculating the new cdclk.
6179 *
6180 * Should measure whether using a lower cdclk w/o IPS
6181 */
6182 return pipe_config->pixel_rate <=
6183 dev_priv->max_cdclk_freq * 95 / 100;
6184 }
6185
6186 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6187 struct intel_crtc_state *pipe_config)
6188 {
6189 struct drm_device *dev = crtc->base.dev;
6190 struct drm_i915_private *dev_priv = to_i915(dev);
6191
6192 pipe_config->ips_enabled = i915.enable_ips &&
6193 hsw_crtc_supports_ips(crtc) &&
6194 pipe_config_supports_ips(dev_priv, pipe_config);
6195 }
6196
6197 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6198 {
6199 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6200
6201 /* GDG double wide on either pipe, otherwise pipe A only */
6202 return INTEL_INFO(dev_priv)->gen < 4 &&
6203 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6204 }
6205
6206 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6207 {
6208 uint32_t pixel_rate;
6209
6210 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6211
6212 /*
6213 * We only use IF-ID interlacing. If we ever use
6214 * PF-ID we'll need to adjust the pixel_rate here.
6215 */
6216
6217 if (pipe_config->pch_pfit.enabled) {
6218 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6219 uint32_t pfit_size = pipe_config->pch_pfit.size;
6220
6221 pipe_w = pipe_config->pipe_src_w;
6222 pipe_h = pipe_config->pipe_src_h;
6223
6224 pfit_w = (pfit_size >> 16) & 0xFFFF;
6225 pfit_h = pfit_size & 0xFFFF;
6226 if (pipe_w < pfit_w)
6227 pipe_w = pfit_w;
6228 if (pipe_h < pfit_h)
6229 pipe_h = pfit_h;
6230
6231 if (WARN_ON(!pfit_w || !pfit_h))
6232 return pixel_rate;
6233
6234 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6235 pfit_w * pfit_h);
6236 }
6237
6238 return pixel_rate;
6239 }
6240
6241 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6242 {
6243 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6244
6245 if (HAS_GMCH_DISPLAY(dev_priv))
6246 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6247 crtc_state->pixel_rate =
6248 crtc_state->base.adjusted_mode.crtc_clock;
6249 else
6250 crtc_state->pixel_rate =
6251 ilk_pipe_pixel_rate(crtc_state);
6252 }
6253
6254 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6255 struct intel_crtc_state *pipe_config)
6256 {
6257 struct drm_device *dev = crtc->base.dev;
6258 struct drm_i915_private *dev_priv = to_i915(dev);
6259 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6260 int clock_limit = dev_priv->max_dotclk_freq;
6261
6262 if (INTEL_GEN(dev_priv) < 4) {
6263 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6264
6265 /*
6266 * Enable double wide mode when the dot clock
6267 * is > 90% of the (display) core speed.
6268 */
6269 if (intel_crtc_supports_double_wide(crtc) &&
6270 adjusted_mode->crtc_clock > clock_limit) {
6271 clock_limit = dev_priv->max_dotclk_freq;
6272 pipe_config->double_wide = true;
6273 }
6274 }
6275
6276 if (adjusted_mode->crtc_clock > clock_limit) {
6277 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6278 adjusted_mode->crtc_clock, clock_limit,
6279 yesno(pipe_config->double_wide));
6280 return -EINVAL;
6281 }
6282
6283 /*
6284 * Pipe horizontal size must be even in:
6285 * - DVO ganged mode
6286 * - LVDS dual channel mode
6287 * - Double wide pipe
6288 */
6289 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6290 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6291 pipe_config->pipe_src_w &= ~1;
6292
6293 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6294 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6295 */
6296 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6297 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6298 return -EINVAL;
6299
6300 intel_crtc_compute_pixel_rate(pipe_config);
6301
6302 if (HAS_IPS(dev_priv))
6303 hsw_compute_ips_config(crtc, pipe_config);
6304
6305 if (pipe_config->has_pch_encoder)
6306 return ironlake_fdi_compute_config(crtc, pipe_config);
6307
6308 return 0;
6309 }
6310
6311 static void
6312 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6313 {
6314 while (*num > DATA_LINK_M_N_MASK ||
6315 *den > DATA_LINK_M_N_MASK) {
6316 *num >>= 1;
6317 *den >>= 1;
6318 }
6319 }
6320
6321 static void compute_m_n(unsigned int m, unsigned int n,
6322 uint32_t *ret_m, uint32_t *ret_n)
6323 {
6324 /*
6325 * Reduce M/N as much as possible without loss in precision. Several DP
6326 * dongles in particular seem to be fussy about too large *link* M/N
6327 * values. The passed in values are more likely to have the least
6328 * significant bits zero than M after rounding below, so do this first.
6329 */
6330 while ((m & 1) == 0 && (n & 1) == 0) {
6331 m >>= 1;
6332 n >>= 1;
6333 }
6334
6335 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6336 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6337 intel_reduce_m_n_ratio(ret_m, ret_n);
6338 }
6339
6340 void
6341 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6342 int pixel_clock, int link_clock,
6343 struct intel_link_m_n *m_n)
6344 {
6345 m_n->tu = 64;
6346
6347 compute_m_n(bits_per_pixel * pixel_clock,
6348 link_clock * nlanes * 8,
6349 &m_n->gmch_m, &m_n->gmch_n);
6350
6351 compute_m_n(pixel_clock, link_clock,
6352 &m_n->link_m, &m_n->link_n);
6353 }
6354
6355 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6356 {
6357 if (i915.panel_use_ssc >= 0)
6358 return i915.panel_use_ssc != 0;
6359 return dev_priv->vbt.lvds_use_ssc
6360 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6361 }
6362
6363 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6364 {
6365 return (1 << dpll->n) << 16 | dpll->m2;
6366 }
6367
6368 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6369 {
6370 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6371 }
6372
6373 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6374 struct intel_crtc_state *crtc_state,
6375 struct dpll *reduced_clock)
6376 {
6377 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6378 u32 fp, fp2 = 0;
6379
6380 if (IS_PINEVIEW(dev_priv)) {
6381 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6382 if (reduced_clock)
6383 fp2 = pnv_dpll_compute_fp(reduced_clock);
6384 } else {
6385 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6386 if (reduced_clock)
6387 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6388 }
6389
6390 crtc_state->dpll_hw_state.fp0 = fp;
6391
6392 crtc->lowfreq_avail = false;
6393 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6394 reduced_clock) {
6395 crtc_state->dpll_hw_state.fp1 = fp2;
6396 crtc->lowfreq_avail = true;
6397 } else {
6398 crtc_state->dpll_hw_state.fp1 = fp;
6399 }
6400 }
6401
6402 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6403 pipe)
6404 {
6405 u32 reg_val;
6406
6407 /*
6408 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6409 * and set it to a reasonable value instead.
6410 */
6411 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6412 reg_val &= 0xffffff00;
6413 reg_val |= 0x00000030;
6414 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6415
6416 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6417 reg_val &= 0x00ffffff;
6418 reg_val |= 0x8c000000;
6419 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6420
6421 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6422 reg_val &= 0xffffff00;
6423 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6424
6425 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6426 reg_val &= 0x00ffffff;
6427 reg_val |= 0xb0000000;
6428 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6429 }
6430
6431 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6432 struct intel_link_m_n *m_n)
6433 {
6434 struct drm_device *dev = crtc->base.dev;
6435 struct drm_i915_private *dev_priv = to_i915(dev);
6436 int pipe = crtc->pipe;
6437
6438 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6439 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6440 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6441 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6442 }
6443
6444 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6445 struct intel_link_m_n *m_n,
6446 struct intel_link_m_n *m2_n2)
6447 {
6448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6449 int pipe = crtc->pipe;
6450 enum transcoder transcoder = crtc->config->cpu_transcoder;
6451
6452 if (INTEL_GEN(dev_priv) >= 5) {
6453 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6454 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6455 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6456 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6457 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6458 * for gen < 8) and if DRRS is supported (to make sure the
6459 * registers are not unnecessarily accessed).
6460 */
6461 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6462 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6463 I915_WRITE(PIPE_DATA_M2(transcoder),
6464 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6465 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6466 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6467 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6468 }
6469 } else {
6470 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6471 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6472 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6473 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6474 }
6475 }
6476
6477 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6478 {
6479 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6480
6481 if (m_n == M1_N1) {
6482 dp_m_n = &crtc->config->dp_m_n;
6483 dp_m2_n2 = &crtc->config->dp_m2_n2;
6484 } else if (m_n == M2_N2) {
6485
6486 /*
6487 * M2_N2 registers are not supported. Hence m2_n2 divider value
6488 * needs to be programmed into M1_N1.
6489 */
6490 dp_m_n = &crtc->config->dp_m2_n2;
6491 } else {
6492 DRM_ERROR("Unsupported divider value\n");
6493 return;
6494 }
6495
6496 if (crtc->config->has_pch_encoder)
6497 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6498 else
6499 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6500 }
6501
6502 static void vlv_compute_dpll(struct intel_crtc *crtc,
6503 struct intel_crtc_state *pipe_config)
6504 {
6505 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6506 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6507 if (crtc->pipe != PIPE_A)
6508 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6509
6510 /* DPLL not used with DSI, but still need the rest set up */
6511 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6512 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6513 DPLL_EXT_BUFFER_ENABLE_VLV;
6514
6515 pipe_config->dpll_hw_state.dpll_md =
6516 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6517 }
6518
6519 static void chv_compute_dpll(struct intel_crtc *crtc,
6520 struct intel_crtc_state *pipe_config)
6521 {
6522 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6523 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6524 if (crtc->pipe != PIPE_A)
6525 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6526
6527 /* DPLL not used with DSI, but still need the rest set up */
6528 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6529 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6530
6531 pipe_config->dpll_hw_state.dpll_md =
6532 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6533 }
6534
6535 static void vlv_prepare_pll(struct intel_crtc *crtc,
6536 const struct intel_crtc_state *pipe_config)
6537 {
6538 struct drm_device *dev = crtc->base.dev;
6539 struct drm_i915_private *dev_priv = to_i915(dev);
6540 enum pipe pipe = crtc->pipe;
6541 u32 mdiv;
6542 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6543 u32 coreclk, reg_val;
6544
6545 /* Enable Refclk */
6546 I915_WRITE(DPLL(pipe),
6547 pipe_config->dpll_hw_state.dpll &
6548 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6549
6550 /* No need to actually set up the DPLL with DSI */
6551 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6552 return;
6553
6554 mutex_lock(&dev_priv->sb_lock);
6555
6556 bestn = pipe_config->dpll.n;
6557 bestm1 = pipe_config->dpll.m1;
6558 bestm2 = pipe_config->dpll.m2;
6559 bestp1 = pipe_config->dpll.p1;
6560 bestp2 = pipe_config->dpll.p2;
6561
6562 /* See eDP HDMI DPIO driver vbios notes doc */
6563
6564 /* PLL B needs special handling */
6565 if (pipe == PIPE_B)
6566 vlv_pllb_recal_opamp(dev_priv, pipe);
6567
6568 /* Set up Tx target for periodic Rcomp update */
6569 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6570
6571 /* Disable target IRef on PLL */
6572 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6573 reg_val &= 0x00ffffff;
6574 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6575
6576 /* Disable fast lock */
6577 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6578
6579 /* Set idtafcrecal before PLL is enabled */
6580 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6581 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6582 mdiv |= ((bestn << DPIO_N_SHIFT));
6583 mdiv |= (1 << DPIO_K_SHIFT);
6584
6585 /*
6586 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6587 * but we don't support that).
6588 * Note: don't use the DAC post divider as it seems unstable.
6589 */
6590 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6592
6593 mdiv |= DPIO_ENABLE_CALIBRATION;
6594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6595
6596 /* Set HBR and RBR LPF coefficients */
6597 if (pipe_config->port_clock == 162000 ||
6598 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6599 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6600 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6601 0x009f0003);
6602 else
6603 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6604 0x00d0000f);
6605
6606 if (intel_crtc_has_dp_encoder(pipe_config)) {
6607 /* Use SSC source */
6608 if (pipe == PIPE_A)
6609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6610 0x0df40000);
6611 else
6612 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6613 0x0df70000);
6614 } else { /* HDMI or VGA */
6615 /* Use bend source */
6616 if (pipe == PIPE_A)
6617 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6618 0x0df70000);
6619 else
6620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6621 0x0df40000);
6622 }
6623
6624 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6625 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6626 if (intel_crtc_has_dp_encoder(crtc->config))
6627 coreclk |= 0x01000000;
6628 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6629
6630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6631 mutex_unlock(&dev_priv->sb_lock);
6632 }
6633
6634 static void chv_prepare_pll(struct intel_crtc *crtc,
6635 const struct intel_crtc_state *pipe_config)
6636 {
6637 struct drm_device *dev = crtc->base.dev;
6638 struct drm_i915_private *dev_priv = to_i915(dev);
6639 enum pipe pipe = crtc->pipe;
6640 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6641 u32 loopfilter, tribuf_calcntr;
6642 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6643 u32 dpio_val;
6644 int vco;
6645
6646 /* Enable Refclk and SSC */
6647 I915_WRITE(DPLL(pipe),
6648 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6649
6650 /* No need to actually set up the DPLL with DSI */
6651 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6652 return;
6653
6654 bestn = pipe_config->dpll.n;
6655 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6656 bestm1 = pipe_config->dpll.m1;
6657 bestm2 = pipe_config->dpll.m2 >> 22;
6658 bestp1 = pipe_config->dpll.p1;
6659 bestp2 = pipe_config->dpll.p2;
6660 vco = pipe_config->dpll.vco;
6661 dpio_val = 0;
6662 loopfilter = 0;
6663
6664 mutex_lock(&dev_priv->sb_lock);
6665
6666 /* p1 and p2 divider */
6667 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6668 5 << DPIO_CHV_S1_DIV_SHIFT |
6669 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6670 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6671 1 << DPIO_CHV_K_DIV_SHIFT);
6672
6673 /* Feedback post-divider - m2 */
6674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6675
6676 /* Feedback refclk divider - n and m1 */
6677 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6678 DPIO_CHV_M1_DIV_BY_2 |
6679 1 << DPIO_CHV_N_DIV_SHIFT);
6680
6681 /* M2 fraction division */
6682 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6683
6684 /* M2 fraction division enable */
6685 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6686 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6687 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6688 if (bestm2_frac)
6689 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6690 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6691
6692 /* Program digital lock detect threshold */
6693 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6694 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6695 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6696 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6697 if (!bestm2_frac)
6698 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6699 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6700
6701 /* Loop filter */
6702 if (vco == 5400000) {
6703 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6704 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6705 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6706 tribuf_calcntr = 0x9;
6707 } else if (vco <= 6200000) {
6708 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6709 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6710 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6711 tribuf_calcntr = 0x9;
6712 } else if (vco <= 6480000) {
6713 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6714 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6715 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6716 tribuf_calcntr = 0x8;
6717 } else {
6718 /* Not supported. Apply the same limits as in the max case */
6719 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6720 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6721 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6722 tribuf_calcntr = 0;
6723 }
6724 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6725
6726 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6727 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6728 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6729 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6730
6731 /* AFC Recal */
6732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6733 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6734 DPIO_AFC_RECAL);
6735
6736 mutex_unlock(&dev_priv->sb_lock);
6737 }
6738
6739 /**
6740 * vlv_force_pll_on - forcibly enable just the PLL
6741 * @dev_priv: i915 private structure
6742 * @pipe: pipe PLL to enable
6743 * @dpll: PLL configuration
6744 *
6745 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6746 * in cases where we need the PLL enabled even when @pipe is not going to
6747 * be enabled.
6748 */
6749 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6750 const struct dpll *dpll)
6751 {
6752 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6753 struct intel_crtc_state *pipe_config;
6754
6755 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6756 if (!pipe_config)
6757 return -ENOMEM;
6758
6759 pipe_config->base.crtc = &crtc->base;
6760 pipe_config->pixel_multiplier = 1;
6761 pipe_config->dpll = *dpll;
6762
6763 if (IS_CHERRYVIEW(dev_priv)) {
6764 chv_compute_dpll(crtc, pipe_config);
6765 chv_prepare_pll(crtc, pipe_config);
6766 chv_enable_pll(crtc, pipe_config);
6767 } else {
6768 vlv_compute_dpll(crtc, pipe_config);
6769 vlv_prepare_pll(crtc, pipe_config);
6770 vlv_enable_pll(crtc, pipe_config);
6771 }
6772
6773 kfree(pipe_config);
6774
6775 return 0;
6776 }
6777
6778 /**
6779 * vlv_force_pll_off - forcibly disable just the PLL
6780 * @dev_priv: i915 private structure
6781 * @pipe: pipe PLL to disable
6782 *
6783 * Disable the PLL for @pipe. To be used in cases where we need
6784 * the PLL enabled even when @pipe is not going to be enabled.
6785 */
6786 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6787 {
6788 if (IS_CHERRYVIEW(dev_priv))
6789 chv_disable_pll(dev_priv, pipe);
6790 else
6791 vlv_disable_pll(dev_priv, pipe);
6792 }
6793
6794 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6795 struct intel_crtc_state *crtc_state,
6796 struct dpll *reduced_clock)
6797 {
6798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6799 u32 dpll;
6800 struct dpll *clock = &crtc_state->dpll;
6801
6802 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6803
6804 dpll = DPLL_VGA_MODE_DIS;
6805
6806 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6807 dpll |= DPLLB_MODE_LVDS;
6808 else
6809 dpll |= DPLLB_MODE_DAC_SERIAL;
6810
6811 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6812 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6813 dpll |= (crtc_state->pixel_multiplier - 1)
6814 << SDVO_MULTIPLIER_SHIFT_HIRES;
6815 }
6816
6817 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6818 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6819 dpll |= DPLL_SDVO_HIGH_SPEED;
6820
6821 if (intel_crtc_has_dp_encoder(crtc_state))
6822 dpll |= DPLL_SDVO_HIGH_SPEED;
6823
6824 /* compute bitmask from p1 value */
6825 if (IS_PINEVIEW(dev_priv))
6826 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6827 else {
6828 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6829 if (IS_G4X(dev_priv) && reduced_clock)
6830 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6831 }
6832 switch (clock->p2) {
6833 case 5:
6834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6835 break;
6836 case 7:
6837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6838 break;
6839 case 10:
6840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6841 break;
6842 case 14:
6843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6844 break;
6845 }
6846 if (INTEL_GEN(dev_priv) >= 4)
6847 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6848
6849 if (crtc_state->sdvo_tv_clock)
6850 dpll |= PLL_REF_INPUT_TVCLKINBC;
6851 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6852 intel_panel_use_ssc(dev_priv))
6853 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6854 else
6855 dpll |= PLL_REF_INPUT_DREFCLK;
6856
6857 dpll |= DPLL_VCO_ENABLE;
6858 crtc_state->dpll_hw_state.dpll = dpll;
6859
6860 if (INTEL_GEN(dev_priv) >= 4) {
6861 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6862 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6863 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6864 }
6865 }
6866
6867 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6868 struct intel_crtc_state *crtc_state,
6869 struct dpll *reduced_clock)
6870 {
6871 struct drm_device *dev = crtc->base.dev;
6872 struct drm_i915_private *dev_priv = to_i915(dev);
6873 u32 dpll;
6874 struct dpll *clock = &crtc_state->dpll;
6875
6876 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6877
6878 dpll = DPLL_VGA_MODE_DIS;
6879
6880 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6881 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6882 } else {
6883 if (clock->p1 == 2)
6884 dpll |= PLL_P1_DIVIDE_BY_TWO;
6885 else
6886 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6887 if (clock->p2 == 4)
6888 dpll |= PLL_P2_DIVIDE_BY_4;
6889 }
6890
6891 if (!IS_I830(dev_priv) &&
6892 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6893 dpll |= DPLL_DVO_2X_MODE;
6894
6895 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6896 intel_panel_use_ssc(dev_priv))
6897 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6898 else
6899 dpll |= PLL_REF_INPUT_DREFCLK;
6900
6901 dpll |= DPLL_VCO_ENABLE;
6902 crtc_state->dpll_hw_state.dpll = dpll;
6903 }
6904
6905 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6906 {
6907 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6908 enum pipe pipe = intel_crtc->pipe;
6909 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6910 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6911 uint32_t crtc_vtotal, crtc_vblank_end;
6912 int vsyncshift = 0;
6913
6914 /* We need to be careful not to changed the adjusted mode, for otherwise
6915 * the hw state checker will get angry at the mismatch. */
6916 crtc_vtotal = adjusted_mode->crtc_vtotal;
6917 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6918
6919 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6920 /* the chip adds 2 halflines automatically */
6921 crtc_vtotal -= 1;
6922 crtc_vblank_end -= 1;
6923
6924 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6925 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6926 else
6927 vsyncshift = adjusted_mode->crtc_hsync_start -
6928 adjusted_mode->crtc_htotal / 2;
6929 if (vsyncshift < 0)
6930 vsyncshift += adjusted_mode->crtc_htotal;
6931 }
6932
6933 if (INTEL_GEN(dev_priv) > 3)
6934 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6935
6936 I915_WRITE(HTOTAL(cpu_transcoder),
6937 (adjusted_mode->crtc_hdisplay - 1) |
6938 ((adjusted_mode->crtc_htotal - 1) << 16));
6939 I915_WRITE(HBLANK(cpu_transcoder),
6940 (adjusted_mode->crtc_hblank_start - 1) |
6941 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6942 I915_WRITE(HSYNC(cpu_transcoder),
6943 (adjusted_mode->crtc_hsync_start - 1) |
6944 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6945
6946 I915_WRITE(VTOTAL(cpu_transcoder),
6947 (adjusted_mode->crtc_vdisplay - 1) |
6948 ((crtc_vtotal - 1) << 16));
6949 I915_WRITE(VBLANK(cpu_transcoder),
6950 (adjusted_mode->crtc_vblank_start - 1) |
6951 ((crtc_vblank_end - 1) << 16));
6952 I915_WRITE(VSYNC(cpu_transcoder),
6953 (adjusted_mode->crtc_vsync_start - 1) |
6954 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6955
6956 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6957 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6958 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6959 * bits. */
6960 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6961 (pipe == PIPE_B || pipe == PIPE_C))
6962 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6963
6964 }
6965
6966 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6967 {
6968 struct drm_device *dev = intel_crtc->base.dev;
6969 struct drm_i915_private *dev_priv = to_i915(dev);
6970 enum pipe pipe = intel_crtc->pipe;
6971
6972 /* pipesrc controls the size that is scaled from, which should
6973 * always be the user's requested size.
6974 */
6975 I915_WRITE(PIPESRC(pipe),
6976 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6977 (intel_crtc->config->pipe_src_h - 1));
6978 }
6979
6980 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6981 struct intel_crtc_state *pipe_config)
6982 {
6983 struct drm_device *dev = crtc->base.dev;
6984 struct drm_i915_private *dev_priv = to_i915(dev);
6985 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6986 uint32_t tmp;
6987
6988 tmp = I915_READ(HTOTAL(cpu_transcoder));
6989 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6990 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6991 tmp = I915_READ(HBLANK(cpu_transcoder));
6992 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6993 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6994 tmp = I915_READ(HSYNC(cpu_transcoder));
6995 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6996 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6997
6998 tmp = I915_READ(VTOTAL(cpu_transcoder));
6999 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7000 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7001 tmp = I915_READ(VBLANK(cpu_transcoder));
7002 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7003 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7004 tmp = I915_READ(VSYNC(cpu_transcoder));
7005 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7006 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7007
7008 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7009 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7010 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7011 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7012 }
7013 }
7014
7015 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7016 struct intel_crtc_state *pipe_config)
7017 {
7018 struct drm_device *dev = crtc->base.dev;
7019 struct drm_i915_private *dev_priv = to_i915(dev);
7020 u32 tmp;
7021
7022 tmp = I915_READ(PIPESRC(crtc->pipe));
7023 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7024 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7025
7026 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7027 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7028 }
7029
7030 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7031 struct intel_crtc_state *pipe_config)
7032 {
7033 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7034 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7035 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7036 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7037
7038 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7039 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7040 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7041 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7042
7043 mode->flags = pipe_config->base.adjusted_mode.flags;
7044 mode->type = DRM_MODE_TYPE_DRIVER;
7045
7046 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7047
7048 mode->hsync = drm_mode_hsync(mode);
7049 mode->vrefresh = drm_mode_vrefresh(mode);
7050 drm_mode_set_name(mode);
7051 }
7052
7053 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7054 {
7055 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7056 uint32_t pipeconf;
7057
7058 pipeconf = 0;
7059
7060 /* we keep both pipes enabled on 830 */
7061 if (IS_I830(dev_priv))
7062 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7063
7064 if (intel_crtc->config->double_wide)
7065 pipeconf |= PIPECONF_DOUBLE_WIDE;
7066
7067 /* only g4x and later have fancy bpc/dither controls */
7068 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7069 IS_CHERRYVIEW(dev_priv)) {
7070 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7071 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7072 pipeconf |= PIPECONF_DITHER_EN |
7073 PIPECONF_DITHER_TYPE_SP;
7074
7075 switch (intel_crtc->config->pipe_bpp) {
7076 case 18:
7077 pipeconf |= PIPECONF_6BPC;
7078 break;
7079 case 24:
7080 pipeconf |= PIPECONF_8BPC;
7081 break;
7082 case 30:
7083 pipeconf |= PIPECONF_10BPC;
7084 break;
7085 default:
7086 /* Case prevented by intel_choose_pipe_bpp_dither. */
7087 BUG();
7088 }
7089 }
7090
7091 if (HAS_PIPE_CXSR(dev_priv)) {
7092 if (intel_crtc->lowfreq_avail) {
7093 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7094 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7095 } else {
7096 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7097 }
7098 }
7099
7100 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7101 if (INTEL_GEN(dev_priv) < 4 ||
7102 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7103 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7104 else
7105 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7106 } else
7107 pipeconf |= PIPECONF_PROGRESSIVE;
7108
7109 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7110 intel_crtc->config->limited_color_range)
7111 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7112
7113 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7114 POSTING_READ(PIPECONF(intel_crtc->pipe));
7115 }
7116
7117 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7118 struct intel_crtc_state *crtc_state)
7119 {
7120 struct drm_device *dev = crtc->base.dev;
7121 struct drm_i915_private *dev_priv = to_i915(dev);
7122 const struct intel_limit *limit;
7123 int refclk = 48000;
7124
7125 memset(&crtc_state->dpll_hw_state, 0,
7126 sizeof(crtc_state->dpll_hw_state));
7127
7128 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7129 if (intel_panel_use_ssc(dev_priv)) {
7130 refclk = dev_priv->vbt.lvds_ssc_freq;
7131 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7132 }
7133
7134 limit = &intel_limits_i8xx_lvds;
7135 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7136 limit = &intel_limits_i8xx_dvo;
7137 } else {
7138 limit = &intel_limits_i8xx_dac;
7139 }
7140
7141 if (!crtc_state->clock_set &&
7142 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7143 refclk, NULL, &crtc_state->dpll)) {
7144 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7145 return -EINVAL;
7146 }
7147
7148 i8xx_compute_dpll(crtc, crtc_state, NULL);
7149
7150 return 0;
7151 }
7152
7153 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7154 struct intel_crtc_state *crtc_state)
7155 {
7156 struct drm_device *dev = crtc->base.dev;
7157 struct drm_i915_private *dev_priv = to_i915(dev);
7158 const struct intel_limit *limit;
7159 int refclk = 96000;
7160
7161 memset(&crtc_state->dpll_hw_state, 0,
7162 sizeof(crtc_state->dpll_hw_state));
7163
7164 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7165 if (intel_panel_use_ssc(dev_priv)) {
7166 refclk = dev_priv->vbt.lvds_ssc_freq;
7167 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7168 }
7169
7170 if (intel_is_dual_link_lvds(dev))
7171 limit = &intel_limits_g4x_dual_channel_lvds;
7172 else
7173 limit = &intel_limits_g4x_single_channel_lvds;
7174 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7175 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7176 limit = &intel_limits_g4x_hdmi;
7177 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7178 limit = &intel_limits_g4x_sdvo;
7179 } else {
7180 /* The option is for other outputs */
7181 limit = &intel_limits_i9xx_sdvo;
7182 }
7183
7184 if (!crtc_state->clock_set &&
7185 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7186 refclk, NULL, &crtc_state->dpll)) {
7187 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7188 return -EINVAL;
7189 }
7190
7191 i9xx_compute_dpll(crtc, crtc_state, NULL);
7192
7193 return 0;
7194 }
7195
7196 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7197 struct intel_crtc_state *crtc_state)
7198 {
7199 struct drm_device *dev = crtc->base.dev;
7200 struct drm_i915_private *dev_priv = to_i915(dev);
7201 const struct intel_limit *limit;
7202 int refclk = 96000;
7203
7204 memset(&crtc_state->dpll_hw_state, 0,
7205 sizeof(crtc_state->dpll_hw_state));
7206
7207 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7208 if (intel_panel_use_ssc(dev_priv)) {
7209 refclk = dev_priv->vbt.lvds_ssc_freq;
7210 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7211 }
7212
7213 limit = &intel_limits_pineview_lvds;
7214 } else {
7215 limit = &intel_limits_pineview_sdvo;
7216 }
7217
7218 if (!crtc_state->clock_set &&
7219 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7220 refclk, NULL, &crtc_state->dpll)) {
7221 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7222 return -EINVAL;
7223 }
7224
7225 i9xx_compute_dpll(crtc, crtc_state, NULL);
7226
7227 return 0;
7228 }
7229
7230 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7231 struct intel_crtc_state *crtc_state)
7232 {
7233 struct drm_device *dev = crtc->base.dev;
7234 struct drm_i915_private *dev_priv = to_i915(dev);
7235 const struct intel_limit *limit;
7236 int refclk = 96000;
7237
7238 memset(&crtc_state->dpll_hw_state, 0,
7239 sizeof(crtc_state->dpll_hw_state));
7240
7241 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7242 if (intel_panel_use_ssc(dev_priv)) {
7243 refclk = dev_priv->vbt.lvds_ssc_freq;
7244 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7245 }
7246
7247 limit = &intel_limits_i9xx_lvds;
7248 } else {
7249 limit = &intel_limits_i9xx_sdvo;
7250 }
7251
7252 if (!crtc_state->clock_set &&
7253 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7254 refclk, NULL, &crtc_state->dpll)) {
7255 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7256 return -EINVAL;
7257 }
7258
7259 i9xx_compute_dpll(crtc, crtc_state, NULL);
7260
7261 return 0;
7262 }
7263
7264 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7265 struct intel_crtc_state *crtc_state)
7266 {
7267 int refclk = 100000;
7268 const struct intel_limit *limit = &intel_limits_chv;
7269
7270 memset(&crtc_state->dpll_hw_state, 0,
7271 sizeof(crtc_state->dpll_hw_state));
7272
7273 if (!crtc_state->clock_set &&
7274 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7275 refclk, NULL, &crtc_state->dpll)) {
7276 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7277 return -EINVAL;
7278 }
7279
7280 chv_compute_dpll(crtc, crtc_state);
7281
7282 return 0;
7283 }
7284
7285 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7286 struct intel_crtc_state *crtc_state)
7287 {
7288 int refclk = 100000;
7289 const struct intel_limit *limit = &intel_limits_vlv;
7290
7291 memset(&crtc_state->dpll_hw_state, 0,
7292 sizeof(crtc_state->dpll_hw_state));
7293
7294 if (!crtc_state->clock_set &&
7295 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7296 refclk, NULL, &crtc_state->dpll)) {
7297 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7298 return -EINVAL;
7299 }
7300
7301 vlv_compute_dpll(crtc, crtc_state);
7302
7303 return 0;
7304 }
7305
7306 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7307 struct intel_crtc_state *pipe_config)
7308 {
7309 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7310 uint32_t tmp;
7311
7312 if (INTEL_GEN(dev_priv) <= 3 &&
7313 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7314 return;
7315
7316 tmp = I915_READ(PFIT_CONTROL);
7317 if (!(tmp & PFIT_ENABLE))
7318 return;
7319
7320 /* Check whether the pfit is attached to our pipe. */
7321 if (INTEL_GEN(dev_priv) < 4) {
7322 if (crtc->pipe != PIPE_B)
7323 return;
7324 } else {
7325 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7326 return;
7327 }
7328
7329 pipe_config->gmch_pfit.control = tmp;
7330 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7331 }
7332
7333 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7334 struct intel_crtc_state *pipe_config)
7335 {
7336 struct drm_device *dev = crtc->base.dev;
7337 struct drm_i915_private *dev_priv = to_i915(dev);
7338 int pipe = pipe_config->cpu_transcoder;
7339 struct dpll clock;
7340 u32 mdiv;
7341 int refclk = 100000;
7342
7343 /* In case of DSI, DPLL will not be used */
7344 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7345 return;
7346
7347 mutex_lock(&dev_priv->sb_lock);
7348 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7349 mutex_unlock(&dev_priv->sb_lock);
7350
7351 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7352 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7353 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7354 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7355 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7356
7357 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7358 }
7359
7360 static void
7361 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7362 struct intel_initial_plane_config *plane_config)
7363 {
7364 struct drm_device *dev = crtc->base.dev;
7365 struct drm_i915_private *dev_priv = to_i915(dev);
7366 u32 val, base, offset;
7367 int pipe = crtc->pipe, plane = crtc->plane;
7368 int fourcc, pixel_format;
7369 unsigned int aligned_height;
7370 struct drm_framebuffer *fb;
7371 struct intel_framebuffer *intel_fb;
7372
7373 val = I915_READ(DSPCNTR(plane));
7374 if (!(val & DISPLAY_PLANE_ENABLE))
7375 return;
7376
7377 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7378 if (!intel_fb) {
7379 DRM_DEBUG_KMS("failed to alloc fb\n");
7380 return;
7381 }
7382
7383 fb = &intel_fb->base;
7384
7385 fb->dev = dev;
7386
7387 if (INTEL_GEN(dev_priv) >= 4) {
7388 if (val & DISPPLANE_TILED) {
7389 plane_config->tiling = I915_TILING_X;
7390 fb->modifier = I915_FORMAT_MOD_X_TILED;
7391 }
7392 }
7393
7394 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7395 fourcc = i9xx_format_to_fourcc(pixel_format);
7396 fb->format = drm_format_info(fourcc);
7397
7398 if (INTEL_GEN(dev_priv) >= 4) {
7399 if (plane_config->tiling)
7400 offset = I915_READ(DSPTILEOFF(plane));
7401 else
7402 offset = I915_READ(DSPLINOFF(plane));
7403 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7404 } else {
7405 base = I915_READ(DSPADDR(plane));
7406 }
7407 plane_config->base = base;
7408
7409 val = I915_READ(PIPESRC(pipe));
7410 fb->width = ((val >> 16) & 0xfff) + 1;
7411 fb->height = ((val >> 0) & 0xfff) + 1;
7412
7413 val = I915_READ(DSPSTRIDE(pipe));
7414 fb->pitches[0] = val & 0xffffffc0;
7415
7416 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7417
7418 plane_config->size = fb->pitches[0] * aligned_height;
7419
7420 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7421 pipe_name(pipe), plane, fb->width, fb->height,
7422 fb->format->cpp[0] * 8, base, fb->pitches[0],
7423 plane_config->size);
7424
7425 plane_config->fb = intel_fb;
7426 }
7427
7428 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7429 struct intel_crtc_state *pipe_config)
7430 {
7431 struct drm_device *dev = crtc->base.dev;
7432 struct drm_i915_private *dev_priv = to_i915(dev);
7433 int pipe = pipe_config->cpu_transcoder;
7434 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7435 struct dpll clock;
7436 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7437 int refclk = 100000;
7438
7439 /* In case of DSI, DPLL will not be used */
7440 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7441 return;
7442
7443 mutex_lock(&dev_priv->sb_lock);
7444 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7445 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7446 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7447 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7448 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7449 mutex_unlock(&dev_priv->sb_lock);
7450
7451 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7452 clock.m2 = (pll_dw0 & 0xff) << 22;
7453 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7454 clock.m2 |= pll_dw2 & 0x3fffff;
7455 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7456 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7457 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7458
7459 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7460 }
7461
7462 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7463 struct intel_crtc_state *pipe_config)
7464 {
7465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7466 enum intel_display_power_domain power_domain;
7467 uint32_t tmp;
7468 bool ret;
7469
7470 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7471 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7472 return false;
7473
7474 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7475 pipe_config->shared_dpll = NULL;
7476
7477 ret = false;
7478
7479 tmp = I915_READ(PIPECONF(crtc->pipe));
7480 if (!(tmp & PIPECONF_ENABLE))
7481 goto out;
7482
7483 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7484 IS_CHERRYVIEW(dev_priv)) {
7485 switch (tmp & PIPECONF_BPC_MASK) {
7486 case PIPECONF_6BPC:
7487 pipe_config->pipe_bpp = 18;
7488 break;
7489 case PIPECONF_8BPC:
7490 pipe_config->pipe_bpp = 24;
7491 break;
7492 case PIPECONF_10BPC:
7493 pipe_config->pipe_bpp = 30;
7494 break;
7495 default:
7496 break;
7497 }
7498 }
7499
7500 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7501 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7502 pipe_config->limited_color_range = true;
7503
7504 if (INTEL_GEN(dev_priv) < 4)
7505 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7506
7507 intel_get_pipe_timings(crtc, pipe_config);
7508 intel_get_pipe_src_size(crtc, pipe_config);
7509
7510 i9xx_get_pfit_config(crtc, pipe_config);
7511
7512 if (INTEL_GEN(dev_priv) >= 4) {
7513 /* No way to read it out on pipes B and C */
7514 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7515 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7516 else
7517 tmp = I915_READ(DPLL_MD(crtc->pipe));
7518 pipe_config->pixel_multiplier =
7519 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7520 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7521 pipe_config->dpll_hw_state.dpll_md = tmp;
7522 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7523 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7524 tmp = I915_READ(DPLL(crtc->pipe));
7525 pipe_config->pixel_multiplier =
7526 ((tmp & SDVO_MULTIPLIER_MASK)
7527 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7528 } else {
7529 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7530 * port and will be fixed up in the encoder->get_config
7531 * function. */
7532 pipe_config->pixel_multiplier = 1;
7533 }
7534 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7535 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7536 /*
7537 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7538 * on 830. Filter it out here so that we don't
7539 * report errors due to that.
7540 */
7541 if (IS_I830(dev_priv))
7542 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7543
7544 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7545 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7546 } else {
7547 /* Mask out read-only status bits. */
7548 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7549 DPLL_PORTC_READY_MASK |
7550 DPLL_PORTB_READY_MASK);
7551 }
7552
7553 if (IS_CHERRYVIEW(dev_priv))
7554 chv_crtc_clock_get(crtc, pipe_config);
7555 else if (IS_VALLEYVIEW(dev_priv))
7556 vlv_crtc_clock_get(crtc, pipe_config);
7557 else
7558 i9xx_crtc_clock_get(crtc, pipe_config);
7559
7560 /*
7561 * Normally the dotclock is filled in by the encoder .get_config()
7562 * but in case the pipe is enabled w/o any ports we need a sane
7563 * default.
7564 */
7565 pipe_config->base.adjusted_mode.crtc_clock =
7566 pipe_config->port_clock / pipe_config->pixel_multiplier;
7567
7568 ret = true;
7569
7570 out:
7571 intel_display_power_put(dev_priv, power_domain);
7572
7573 return ret;
7574 }
7575
7576 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7577 {
7578 struct intel_encoder *encoder;
7579 int i;
7580 u32 val, final;
7581 bool has_lvds = false;
7582 bool has_cpu_edp = false;
7583 bool has_panel = false;
7584 bool has_ck505 = false;
7585 bool can_ssc = false;
7586 bool using_ssc_source = false;
7587
7588 /* We need to take the global config into account */
7589 for_each_intel_encoder(&dev_priv->drm, encoder) {
7590 switch (encoder->type) {
7591 case INTEL_OUTPUT_LVDS:
7592 has_panel = true;
7593 has_lvds = true;
7594 break;
7595 case INTEL_OUTPUT_EDP:
7596 has_panel = true;
7597 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7598 has_cpu_edp = true;
7599 break;
7600 default:
7601 break;
7602 }
7603 }
7604
7605 if (HAS_PCH_IBX(dev_priv)) {
7606 has_ck505 = dev_priv->vbt.display_clock_mode;
7607 can_ssc = has_ck505;
7608 } else {
7609 has_ck505 = false;
7610 can_ssc = true;
7611 }
7612
7613 /* Check if any DPLLs are using the SSC source */
7614 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7615 u32 temp = I915_READ(PCH_DPLL(i));
7616
7617 if (!(temp & DPLL_VCO_ENABLE))
7618 continue;
7619
7620 if ((temp & PLL_REF_INPUT_MASK) ==
7621 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7622 using_ssc_source = true;
7623 break;
7624 }
7625 }
7626
7627 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7628 has_panel, has_lvds, has_ck505, using_ssc_source);
7629
7630 /* Ironlake: try to setup display ref clock before DPLL
7631 * enabling. This is only under driver's control after
7632 * PCH B stepping, previous chipset stepping should be
7633 * ignoring this setting.
7634 */
7635 val = I915_READ(PCH_DREF_CONTROL);
7636
7637 /* As we must carefully and slowly disable/enable each source in turn,
7638 * compute the final state we want first and check if we need to
7639 * make any changes at all.
7640 */
7641 final = val;
7642 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7643 if (has_ck505)
7644 final |= DREF_NONSPREAD_CK505_ENABLE;
7645 else
7646 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7647
7648 final &= ~DREF_SSC_SOURCE_MASK;
7649 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7650 final &= ~DREF_SSC1_ENABLE;
7651
7652 if (has_panel) {
7653 final |= DREF_SSC_SOURCE_ENABLE;
7654
7655 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7656 final |= DREF_SSC1_ENABLE;
7657
7658 if (has_cpu_edp) {
7659 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7660 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7661 else
7662 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7663 } else
7664 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7665 } else if (using_ssc_source) {
7666 final |= DREF_SSC_SOURCE_ENABLE;
7667 final |= DREF_SSC1_ENABLE;
7668 }
7669
7670 if (final == val)
7671 return;
7672
7673 /* Always enable nonspread source */
7674 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7675
7676 if (has_ck505)
7677 val |= DREF_NONSPREAD_CK505_ENABLE;
7678 else
7679 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7680
7681 if (has_panel) {
7682 val &= ~DREF_SSC_SOURCE_MASK;
7683 val |= DREF_SSC_SOURCE_ENABLE;
7684
7685 /* SSC must be turned on before enabling the CPU output */
7686 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7687 DRM_DEBUG_KMS("Using SSC on panel\n");
7688 val |= DREF_SSC1_ENABLE;
7689 } else
7690 val &= ~DREF_SSC1_ENABLE;
7691
7692 /* Get SSC going before enabling the outputs */
7693 I915_WRITE(PCH_DREF_CONTROL, val);
7694 POSTING_READ(PCH_DREF_CONTROL);
7695 udelay(200);
7696
7697 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7698
7699 /* Enable CPU source on CPU attached eDP */
7700 if (has_cpu_edp) {
7701 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7702 DRM_DEBUG_KMS("Using SSC on eDP\n");
7703 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7704 } else
7705 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7706 } else
7707 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7708
7709 I915_WRITE(PCH_DREF_CONTROL, val);
7710 POSTING_READ(PCH_DREF_CONTROL);
7711 udelay(200);
7712 } else {
7713 DRM_DEBUG_KMS("Disabling CPU source output\n");
7714
7715 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7716
7717 /* Turn off CPU output */
7718 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7719
7720 I915_WRITE(PCH_DREF_CONTROL, val);
7721 POSTING_READ(PCH_DREF_CONTROL);
7722 udelay(200);
7723
7724 if (!using_ssc_source) {
7725 DRM_DEBUG_KMS("Disabling SSC source\n");
7726
7727 /* Turn off the SSC source */
7728 val &= ~DREF_SSC_SOURCE_MASK;
7729 val |= DREF_SSC_SOURCE_DISABLE;
7730
7731 /* Turn off SSC1 */
7732 val &= ~DREF_SSC1_ENABLE;
7733
7734 I915_WRITE(PCH_DREF_CONTROL, val);
7735 POSTING_READ(PCH_DREF_CONTROL);
7736 udelay(200);
7737 }
7738 }
7739
7740 BUG_ON(val != final);
7741 }
7742
7743 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7744 {
7745 uint32_t tmp;
7746
7747 tmp = I915_READ(SOUTH_CHICKEN2);
7748 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7749 I915_WRITE(SOUTH_CHICKEN2, tmp);
7750
7751 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7752 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7753 DRM_ERROR("FDI mPHY reset assert timeout\n");
7754
7755 tmp = I915_READ(SOUTH_CHICKEN2);
7756 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7757 I915_WRITE(SOUTH_CHICKEN2, tmp);
7758
7759 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7760 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7761 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7762 }
7763
7764 /* WaMPhyProgramming:hsw */
7765 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7766 {
7767 uint32_t tmp;
7768
7769 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7770 tmp &= ~(0xFF << 24);
7771 tmp |= (0x12 << 24);
7772 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7773
7774 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7775 tmp |= (1 << 11);
7776 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7777
7778 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7779 tmp |= (1 << 11);
7780 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7781
7782 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7783 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7784 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7785
7786 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7787 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7788 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7789
7790 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7791 tmp &= ~(7 << 13);
7792 tmp |= (5 << 13);
7793 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7794
7795 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7796 tmp &= ~(7 << 13);
7797 tmp |= (5 << 13);
7798 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7799
7800 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7801 tmp &= ~0xFF;
7802 tmp |= 0x1C;
7803 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7804
7805 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7806 tmp &= ~0xFF;
7807 tmp |= 0x1C;
7808 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7809
7810 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7811 tmp &= ~(0xFF << 16);
7812 tmp |= (0x1C << 16);
7813 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7814
7815 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7816 tmp &= ~(0xFF << 16);
7817 tmp |= (0x1C << 16);
7818 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7819
7820 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7821 tmp |= (1 << 27);
7822 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7823
7824 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7825 tmp |= (1 << 27);
7826 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7827
7828 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7829 tmp &= ~(0xF << 28);
7830 tmp |= (4 << 28);
7831 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7832
7833 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7834 tmp &= ~(0xF << 28);
7835 tmp |= (4 << 28);
7836 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7837 }
7838
7839 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7840 * Programming" based on the parameters passed:
7841 * - Sequence to enable CLKOUT_DP
7842 * - Sequence to enable CLKOUT_DP without spread
7843 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7844 */
7845 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7846 bool with_spread, bool with_fdi)
7847 {
7848 uint32_t reg, tmp;
7849
7850 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7851 with_spread = true;
7852 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7853 with_fdi, "LP PCH doesn't have FDI\n"))
7854 with_fdi = false;
7855
7856 mutex_lock(&dev_priv->sb_lock);
7857
7858 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7859 tmp &= ~SBI_SSCCTL_DISABLE;
7860 tmp |= SBI_SSCCTL_PATHALT;
7861 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7862
7863 udelay(24);
7864
7865 if (with_spread) {
7866 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7867 tmp &= ~SBI_SSCCTL_PATHALT;
7868 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7869
7870 if (with_fdi) {
7871 lpt_reset_fdi_mphy(dev_priv);
7872 lpt_program_fdi_mphy(dev_priv);
7873 }
7874 }
7875
7876 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7877 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7878 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7879 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7880
7881 mutex_unlock(&dev_priv->sb_lock);
7882 }
7883
7884 /* Sequence to disable CLKOUT_DP */
7885 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7886 {
7887 uint32_t reg, tmp;
7888
7889 mutex_lock(&dev_priv->sb_lock);
7890
7891 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7892 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7893 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7894 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7895
7896 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7897 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7898 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7899 tmp |= SBI_SSCCTL_PATHALT;
7900 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7901 udelay(32);
7902 }
7903 tmp |= SBI_SSCCTL_DISABLE;
7904 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7905 }
7906
7907 mutex_unlock(&dev_priv->sb_lock);
7908 }
7909
7910 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7911
7912 static const uint16_t sscdivintphase[] = {
7913 [BEND_IDX( 50)] = 0x3B23,
7914 [BEND_IDX( 45)] = 0x3B23,
7915 [BEND_IDX( 40)] = 0x3C23,
7916 [BEND_IDX( 35)] = 0x3C23,
7917 [BEND_IDX( 30)] = 0x3D23,
7918 [BEND_IDX( 25)] = 0x3D23,
7919 [BEND_IDX( 20)] = 0x3E23,
7920 [BEND_IDX( 15)] = 0x3E23,
7921 [BEND_IDX( 10)] = 0x3F23,
7922 [BEND_IDX( 5)] = 0x3F23,
7923 [BEND_IDX( 0)] = 0x0025,
7924 [BEND_IDX( -5)] = 0x0025,
7925 [BEND_IDX(-10)] = 0x0125,
7926 [BEND_IDX(-15)] = 0x0125,
7927 [BEND_IDX(-20)] = 0x0225,
7928 [BEND_IDX(-25)] = 0x0225,
7929 [BEND_IDX(-30)] = 0x0325,
7930 [BEND_IDX(-35)] = 0x0325,
7931 [BEND_IDX(-40)] = 0x0425,
7932 [BEND_IDX(-45)] = 0x0425,
7933 [BEND_IDX(-50)] = 0x0525,
7934 };
7935
7936 /*
7937 * Bend CLKOUT_DP
7938 * steps -50 to 50 inclusive, in steps of 5
7939 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7940 * change in clock period = -(steps / 10) * 5.787 ps
7941 */
7942 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7943 {
7944 uint32_t tmp;
7945 int idx = BEND_IDX(steps);
7946
7947 if (WARN_ON(steps % 5 != 0))
7948 return;
7949
7950 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7951 return;
7952
7953 mutex_lock(&dev_priv->sb_lock);
7954
7955 if (steps % 10 != 0)
7956 tmp = 0xAAAAAAAB;
7957 else
7958 tmp = 0x00000000;
7959 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7960
7961 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7962 tmp &= 0xffff0000;
7963 tmp |= sscdivintphase[idx];
7964 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7965
7966 mutex_unlock(&dev_priv->sb_lock);
7967 }
7968
7969 #undef BEND_IDX
7970
7971 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7972 {
7973 struct intel_encoder *encoder;
7974 bool has_vga = false;
7975
7976 for_each_intel_encoder(&dev_priv->drm, encoder) {
7977 switch (encoder->type) {
7978 case INTEL_OUTPUT_ANALOG:
7979 has_vga = true;
7980 break;
7981 default:
7982 break;
7983 }
7984 }
7985
7986 if (has_vga) {
7987 lpt_bend_clkout_dp(dev_priv, 0);
7988 lpt_enable_clkout_dp(dev_priv, true, true);
7989 } else {
7990 lpt_disable_clkout_dp(dev_priv);
7991 }
7992 }
7993
7994 /*
7995 * Initialize reference clocks when the driver loads
7996 */
7997 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7998 {
7999 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8000 ironlake_init_pch_refclk(dev_priv);
8001 else if (HAS_PCH_LPT(dev_priv))
8002 lpt_init_pch_refclk(dev_priv);
8003 }
8004
8005 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8006 {
8007 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8009 int pipe = intel_crtc->pipe;
8010 uint32_t val;
8011
8012 val = 0;
8013
8014 switch (intel_crtc->config->pipe_bpp) {
8015 case 18:
8016 val |= PIPECONF_6BPC;
8017 break;
8018 case 24:
8019 val |= PIPECONF_8BPC;
8020 break;
8021 case 30:
8022 val |= PIPECONF_10BPC;
8023 break;
8024 case 36:
8025 val |= PIPECONF_12BPC;
8026 break;
8027 default:
8028 /* Case prevented by intel_choose_pipe_bpp_dither. */
8029 BUG();
8030 }
8031
8032 if (intel_crtc->config->dither)
8033 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8034
8035 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8036 val |= PIPECONF_INTERLACED_ILK;
8037 else
8038 val |= PIPECONF_PROGRESSIVE;
8039
8040 if (intel_crtc->config->limited_color_range)
8041 val |= PIPECONF_COLOR_RANGE_SELECT;
8042
8043 I915_WRITE(PIPECONF(pipe), val);
8044 POSTING_READ(PIPECONF(pipe));
8045 }
8046
8047 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8048 {
8049 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8051 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8052 u32 val = 0;
8053
8054 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8055 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8056
8057 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8058 val |= PIPECONF_INTERLACED_ILK;
8059 else
8060 val |= PIPECONF_PROGRESSIVE;
8061
8062 I915_WRITE(PIPECONF(cpu_transcoder), val);
8063 POSTING_READ(PIPECONF(cpu_transcoder));
8064 }
8065
8066 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8067 {
8068 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8070
8071 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8072 u32 val = 0;
8073
8074 switch (intel_crtc->config->pipe_bpp) {
8075 case 18:
8076 val |= PIPEMISC_DITHER_6_BPC;
8077 break;
8078 case 24:
8079 val |= PIPEMISC_DITHER_8_BPC;
8080 break;
8081 case 30:
8082 val |= PIPEMISC_DITHER_10_BPC;
8083 break;
8084 case 36:
8085 val |= PIPEMISC_DITHER_12_BPC;
8086 break;
8087 default:
8088 /* Case prevented by pipe_config_set_bpp. */
8089 BUG();
8090 }
8091
8092 if (intel_crtc->config->dither)
8093 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8094
8095 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8096 }
8097 }
8098
8099 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8100 {
8101 /*
8102 * Account for spread spectrum to avoid
8103 * oversubscribing the link. Max center spread
8104 * is 2.5%; use 5% for safety's sake.
8105 */
8106 u32 bps = target_clock * bpp * 21 / 20;
8107 return DIV_ROUND_UP(bps, link_bw * 8);
8108 }
8109
8110 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8111 {
8112 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8113 }
8114
8115 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8116 struct intel_crtc_state *crtc_state,
8117 struct dpll *reduced_clock)
8118 {
8119 struct drm_crtc *crtc = &intel_crtc->base;
8120 struct drm_device *dev = crtc->dev;
8121 struct drm_i915_private *dev_priv = to_i915(dev);
8122 u32 dpll, fp, fp2;
8123 int factor;
8124
8125 /* Enable autotuning of the PLL clock (if permissible) */
8126 factor = 21;
8127 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8128 if ((intel_panel_use_ssc(dev_priv) &&
8129 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8130 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8131 factor = 25;
8132 } else if (crtc_state->sdvo_tv_clock)
8133 factor = 20;
8134
8135 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8136
8137 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8138 fp |= FP_CB_TUNE;
8139
8140 if (reduced_clock) {
8141 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8142
8143 if (reduced_clock->m < factor * reduced_clock->n)
8144 fp2 |= FP_CB_TUNE;
8145 } else {
8146 fp2 = fp;
8147 }
8148
8149 dpll = 0;
8150
8151 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8152 dpll |= DPLLB_MODE_LVDS;
8153 else
8154 dpll |= DPLLB_MODE_DAC_SERIAL;
8155
8156 dpll |= (crtc_state->pixel_multiplier - 1)
8157 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8158
8159 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8160 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8161 dpll |= DPLL_SDVO_HIGH_SPEED;
8162
8163 if (intel_crtc_has_dp_encoder(crtc_state))
8164 dpll |= DPLL_SDVO_HIGH_SPEED;
8165
8166 /*
8167 * The high speed IO clock is only really required for
8168 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8169 * possible to share the DPLL between CRT and HDMI. Enabling
8170 * the clock needlessly does no real harm, except use up a
8171 * bit of power potentially.
8172 *
8173 * We'll limit this to IVB with 3 pipes, since it has only two
8174 * DPLLs and so DPLL sharing is the only way to get three pipes
8175 * driving PCH ports at the same time. On SNB we could do this,
8176 * and potentially avoid enabling the second DPLL, but it's not
8177 * clear if it''s a win or loss power wise. No point in doing
8178 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8179 */
8180 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8181 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8182 dpll |= DPLL_SDVO_HIGH_SPEED;
8183
8184 /* compute bitmask from p1 value */
8185 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8186 /* also FPA1 */
8187 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8188
8189 switch (crtc_state->dpll.p2) {
8190 case 5:
8191 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8192 break;
8193 case 7:
8194 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8195 break;
8196 case 10:
8197 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8198 break;
8199 case 14:
8200 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8201 break;
8202 }
8203
8204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8205 intel_panel_use_ssc(dev_priv))
8206 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8207 else
8208 dpll |= PLL_REF_INPUT_DREFCLK;
8209
8210 dpll |= DPLL_VCO_ENABLE;
8211
8212 crtc_state->dpll_hw_state.dpll = dpll;
8213 crtc_state->dpll_hw_state.fp0 = fp;
8214 crtc_state->dpll_hw_state.fp1 = fp2;
8215 }
8216
8217 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8218 struct intel_crtc_state *crtc_state)
8219 {
8220 struct drm_device *dev = crtc->base.dev;
8221 struct drm_i915_private *dev_priv = to_i915(dev);
8222 const struct intel_limit *limit;
8223 int refclk = 120000;
8224
8225 memset(&crtc_state->dpll_hw_state, 0,
8226 sizeof(crtc_state->dpll_hw_state));
8227
8228 crtc->lowfreq_avail = false;
8229
8230 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8231 if (!crtc_state->has_pch_encoder)
8232 return 0;
8233
8234 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8235 if (intel_panel_use_ssc(dev_priv)) {
8236 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8237 dev_priv->vbt.lvds_ssc_freq);
8238 refclk = dev_priv->vbt.lvds_ssc_freq;
8239 }
8240
8241 if (intel_is_dual_link_lvds(dev)) {
8242 if (refclk == 100000)
8243 limit = &intel_limits_ironlake_dual_lvds_100m;
8244 else
8245 limit = &intel_limits_ironlake_dual_lvds;
8246 } else {
8247 if (refclk == 100000)
8248 limit = &intel_limits_ironlake_single_lvds_100m;
8249 else
8250 limit = &intel_limits_ironlake_single_lvds;
8251 }
8252 } else {
8253 limit = &intel_limits_ironlake_dac;
8254 }
8255
8256 if (!crtc_state->clock_set &&
8257 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8258 refclk, NULL, &crtc_state->dpll)) {
8259 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8260 return -EINVAL;
8261 }
8262
8263 ironlake_compute_dpll(crtc, crtc_state, NULL);
8264
8265 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8266 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8267 pipe_name(crtc->pipe));
8268 return -EINVAL;
8269 }
8270
8271 return 0;
8272 }
8273
8274 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8275 struct intel_link_m_n *m_n)
8276 {
8277 struct drm_device *dev = crtc->base.dev;
8278 struct drm_i915_private *dev_priv = to_i915(dev);
8279 enum pipe pipe = crtc->pipe;
8280
8281 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8282 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8283 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8284 & ~TU_SIZE_MASK;
8285 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8286 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8287 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8288 }
8289
8290 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8291 enum transcoder transcoder,
8292 struct intel_link_m_n *m_n,
8293 struct intel_link_m_n *m2_n2)
8294 {
8295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8296 enum pipe pipe = crtc->pipe;
8297
8298 if (INTEL_GEN(dev_priv) >= 5) {
8299 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8300 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8301 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8302 & ~TU_SIZE_MASK;
8303 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8304 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8305 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8306 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8307 * gen < 8) and if DRRS is supported (to make sure the
8308 * registers are not unnecessarily read).
8309 */
8310 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8311 crtc->config->has_drrs) {
8312 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8313 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8314 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8315 & ~TU_SIZE_MASK;
8316 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8317 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8318 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8319 }
8320 } else {
8321 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8322 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8323 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8324 & ~TU_SIZE_MASK;
8325 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8326 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8327 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8328 }
8329 }
8330
8331 void intel_dp_get_m_n(struct intel_crtc *crtc,
8332 struct intel_crtc_state *pipe_config)
8333 {
8334 if (pipe_config->has_pch_encoder)
8335 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8336 else
8337 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8338 &pipe_config->dp_m_n,
8339 &pipe_config->dp_m2_n2);
8340 }
8341
8342 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8343 struct intel_crtc_state *pipe_config)
8344 {
8345 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8346 &pipe_config->fdi_m_n, NULL);
8347 }
8348
8349 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8350 struct intel_crtc_state *pipe_config)
8351 {
8352 struct drm_device *dev = crtc->base.dev;
8353 struct drm_i915_private *dev_priv = to_i915(dev);
8354 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8355 uint32_t ps_ctrl = 0;
8356 int id = -1;
8357 int i;
8358
8359 /* find scaler attached to this pipe */
8360 for (i = 0; i < crtc->num_scalers; i++) {
8361 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8362 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8363 id = i;
8364 pipe_config->pch_pfit.enabled = true;
8365 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8366 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8367 break;
8368 }
8369 }
8370
8371 scaler_state->scaler_id = id;
8372 if (id >= 0) {
8373 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8374 } else {
8375 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8376 }
8377 }
8378
8379 static void
8380 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8381 struct intel_initial_plane_config *plane_config)
8382 {
8383 struct drm_device *dev = crtc->base.dev;
8384 struct drm_i915_private *dev_priv = to_i915(dev);
8385 u32 val, base, offset, stride_mult, tiling;
8386 int pipe = crtc->pipe;
8387 int fourcc, pixel_format;
8388 unsigned int aligned_height;
8389 struct drm_framebuffer *fb;
8390 struct intel_framebuffer *intel_fb;
8391
8392 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8393 if (!intel_fb) {
8394 DRM_DEBUG_KMS("failed to alloc fb\n");
8395 return;
8396 }
8397
8398 fb = &intel_fb->base;
8399
8400 fb->dev = dev;
8401
8402 val = I915_READ(PLANE_CTL(pipe, 0));
8403 if (!(val & PLANE_CTL_ENABLE))
8404 goto error;
8405
8406 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8407 fourcc = skl_format_to_fourcc(pixel_format,
8408 val & PLANE_CTL_ORDER_RGBX,
8409 val & PLANE_CTL_ALPHA_MASK);
8410 fb->format = drm_format_info(fourcc);
8411
8412 tiling = val & PLANE_CTL_TILED_MASK;
8413 switch (tiling) {
8414 case PLANE_CTL_TILED_LINEAR:
8415 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8416 break;
8417 case PLANE_CTL_TILED_X:
8418 plane_config->tiling = I915_TILING_X;
8419 fb->modifier = I915_FORMAT_MOD_X_TILED;
8420 break;
8421 case PLANE_CTL_TILED_Y:
8422 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8423 break;
8424 case PLANE_CTL_TILED_YF:
8425 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8426 break;
8427 default:
8428 MISSING_CASE(tiling);
8429 goto error;
8430 }
8431
8432 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8433 plane_config->base = base;
8434
8435 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8436
8437 val = I915_READ(PLANE_SIZE(pipe, 0));
8438 fb->height = ((val >> 16) & 0xfff) + 1;
8439 fb->width = ((val >> 0) & 0x1fff) + 1;
8440
8441 val = I915_READ(PLANE_STRIDE(pipe, 0));
8442 stride_mult = intel_fb_stride_alignment(fb, 0);
8443 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8444
8445 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8446
8447 plane_config->size = fb->pitches[0] * aligned_height;
8448
8449 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8450 pipe_name(pipe), fb->width, fb->height,
8451 fb->format->cpp[0] * 8, base, fb->pitches[0],
8452 plane_config->size);
8453
8454 plane_config->fb = intel_fb;
8455 return;
8456
8457 error:
8458 kfree(intel_fb);
8459 }
8460
8461 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8462 struct intel_crtc_state *pipe_config)
8463 {
8464 struct drm_device *dev = crtc->base.dev;
8465 struct drm_i915_private *dev_priv = to_i915(dev);
8466 uint32_t tmp;
8467
8468 tmp = I915_READ(PF_CTL(crtc->pipe));
8469
8470 if (tmp & PF_ENABLE) {
8471 pipe_config->pch_pfit.enabled = true;
8472 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8473 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8474
8475 /* We currently do not free assignements of panel fitters on
8476 * ivb/hsw (since we don't use the higher upscaling modes which
8477 * differentiates them) so just WARN about this case for now. */
8478 if (IS_GEN7(dev_priv)) {
8479 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8480 PF_PIPE_SEL_IVB(crtc->pipe));
8481 }
8482 }
8483 }
8484
8485 static void
8486 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8487 struct intel_initial_plane_config *plane_config)
8488 {
8489 struct drm_device *dev = crtc->base.dev;
8490 struct drm_i915_private *dev_priv = to_i915(dev);
8491 u32 val, base, offset;
8492 int pipe = crtc->pipe;
8493 int fourcc, pixel_format;
8494 unsigned int aligned_height;
8495 struct drm_framebuffer *fb;
8496 struct intel_framebuffer *intel_fb;
8497
8498 val = I915_READ(DSPCNTR(pipe));
8499 if (!(val & DISPLAY_PLANE_ENABLE))
8500 return;
8501
8502 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8503 if (!intel_fb) {
8504 DRM_DEBUG_KMS("failed to alloc fb\n");
8505 return;
8506 }
8507
8508 fb = &intel_fb->base;
8509
8510 fb->dev = dev;
8511
8512 if (INTEL_GEN(dev_priv) >= 4) {
8513 if (val & DISPPLANE_TILED) {
8514 plane_config->tiling = I915_TILING_X;
8515 fb->modifier = I915_FORMAT_MOD_X_TILED;
8516 }
8517 }
8518
8519 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8520 fourcc = i9xx_format_to_fourcc(pixel_format);
8521 fb->format = drm_format_info(fourcc);
8522
8523 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8524 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8525 offset = I915_READ(DSPOFFSET(pipe));
8526 } else {
8527 if (plane_config->tiling)
8528 offset = I915_READ(DSPTILEOFF(pipe));
8529 else
8530 offset = I915_READ(DSPLINOFF(pipe));
8531 }
8532 plane_config->base = base;
8533
8534 val = I915_READ(PIPESRC(pipe));
8535 fb->width = ((val >> 16) & 0xfff) + 1;
8536 fb->height = ((val >> 0) & 0xfff) + 1;
8537
8538 val = I915_READ(DSPSTRIDE(pipe));
8539 fb->pitches[0] = val & 0xffffffc0;
8540
8541 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8542
8543 plane_config->size = fb->pitches[0] * aligned_height;
8544
8545 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8546 pipe_name(pipe), fb->width, fb->height,
8547 fb->format->cpp[0] * 8, base, fb->pitches[0],
8548 plane_config->size);
8549
8550 plane_config->fb = intel_fb;
8551 }
8552
8553 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8554 struct intel_crtc_state *pipe_config)
8555 {
8556 struct drm_device *dev = crtc->base.dev;
8557 struct drm_i915_private *dev_priv = to_i915(dev);
8558 enum intel_display_power_domain power_domain;
8559 uint32_t tmp;
8560 bool ret;
8561
8562 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8563 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8564 return false;
8565
8566 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8567 pipe_config->shared_dpll = NULL;
8568
8569 ret = false;
8570 tmp = I915_READ(PIPECONF(crtc->pipe));
8571 if (!(tmp & PIPECONF_ENABLE))
8572 goto out;
8573
8574 switch (tmp & PIPECONF_BPC_MASK) {
8575 case PIPECONF_6BPC:
8576 pipe_config->pipe_bpp = 18;
8577 break;
8578 case PIPECONF_8BPC:
8579 pipe_config->pipe_bpp = 24;
8580 break;
8581 case PIPECONF_10BPC:
8582 pipe_config->pipe_bpp = 30;
8583 break;
8584 case PIPECONF_12BPC:
8585 pipe_config->pipe_bpp = 36;
8586 break;
8587 default:
8588 break;
8589 }
8590
8591 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8592 pipe_config->limited_color_range = true;
8593
8594 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8595 struct intel_shared_dpll *pll;
8596 enum intel_dpll_id pll_id;
8597
8598 pipe_config->has_pch_encoder = true;
8599
8600 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8601 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8602 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8603
8604 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8605
8606 if (HAS_PCH_IBX(dev_priv)) {
8607 /*
8608 * The pipe->pch transcoder and pch transcoder->pll
8609 * mapping is fixed.
8610 */
8611 pll_id = (enum intel_dpll_id) crtc->pipe;
8612 } else {
8613 tmp = I915_READ(PCH_DPLL_SEL);
8614 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8615 pll_id = DPLL_ID_PCH_PLL_B;
8616 else
8617 pll_id= DPLL_ID_PCH_PLL_A;
8618 }
8619
8620 pipe_config->shared_dpll =
8621 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8622 pll = pipe_config->shared_dpll;
8623
8624 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8625 &pipe_config->dpll_hw_state));
8626
8627 tmp = pipe_config->dpll_hw_state.dpll;
8628 pipe_config->pixel_multiplier =
8629 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8630 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8631
8632 ironlake_pch_clock_get(crtc, pipe_config);
8633 } else {
8634 pipe_config->pixel_multiplier = 1;
8635 }
8636
8637 intel_get_pipe_timings(crtc, pipe_config);
8638 intel_get_pipe_src_size(crtc, pipe_config);
8639
8640 ironlake_get_pfit_config(crtc, pipe_config);
8641
8642 ret = true;
8643
8644 out:
8645 intel_display_power_put(dev_priv, power_domain);
8646
8647 return ret;
8648 }
8649
8650 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8651 {
8652 struct drm_device *dev = &dev_priv->drm;
8653 struct intel_crtc *crtc;
8654
8655 for_each_intel_crtc(dev, crtc)
8656 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8657 pipe_name(crtc->pipe));
8658
8659 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8660 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8661 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8662 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8663 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8664 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8665 "CPU PWM1 enabled\n");
8666 if (IS_HASWELL(dev_priv))
8667 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8668 "CPU PWM2 enabled\n");
8669 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8670 "PCH PWM1 enabled\n");
8671 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8672 "Utility pin enabled\n");
8673 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8674
8675 /*
8676 * In theory we can still leave IRQs enabled, as long as only the HPD
8677 * interrupts remain enabled. We used to check for that, but since it's
8678 * gen-specific and since we only disable LCPLL after we fully disable
8679 * the interrupts, the check below should be enough.
8680 */
8681 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8682 }
8683
8684 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8685 {
8686 if (IS_HASWELL(dev_priv))
8687 return I915_READ(D_COMP_HSW);
8688 else
8689 return I915_READ(D_COMP_BDW);
8690 }
8691
8692 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8693 {
8694 if (IS_HASWELL(dev_priv)) {
8695 mutex_lock(&dev_priv->rps.hw_lock);
8696 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8697 val))
8698 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8699 mutex_unlock(&dev_priv->rps.hw_lock);
8700 } else {
8701 I915_WRITE(D_COMP_BDW, val);
8702 POSTING_READ(D_COMP_BDW);
8703 }
8704 }
8705
8706 /*
8707 * This function implements pieces of two sequences from BSpec:
8708 * - Sequence for display software to disable LCPLL
8709 * - Sequence for display software to allow package C8+
8710 * The steps implemented here are just the steps that actually touch the LCPLL
8711 * register. Callers should take care of disabling all the display engine
8712 * functions, doing the mode unset, fixing interrupts, etc.
8713 */
8714 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8715 bool switch_to_fclk, bool allow_power_down)
8716 {
8717 uint32_t val;
8718
8719 assert_can_disable_lcpll(dev_priv);
8720
8721 val = I915_READ(LCPLL_CTL);
8722
8723 if (switch_to_fclk) {
8724 val |= LCPLL_CD_SOURCE_FCLK;
8725 I915_WRITE(LCPLL_CTL, val);
8726
8727 if (wait_for_us(I915_READ(LCPLL_CTL) &
8728 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8729 DRM_ERROR("Switching to FCLK failed\n");
8730
8731 val = I915_READ(LCPLL_CTL);
8732 }
8733
8734 val |= LCPLL_PLL_DISABLE;
8735 I915_WRITE(LCPLL_CTL, val);
8736 POSTING_READ(LCPLL_CTL);
8737
8738 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8739 DRM_ERROR("LCPLL still locked\n");
8740
8741 val = hsw_read_dcomp(dev_priv);
8742 val |= D_COMP_COMP_DISABLE;
8743 hsw_write_dcomp(dev_priv, val);
8744 ndelay(100);
8745
8746 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8747 1))
8748 DRM_ERROR("D_COMP RCOMP still in progress\n");
8749
8750 if (allow_power_down) {
8751 val = I915_READ(LCPLL_CTL);
8752 val |= LCPLL_POWER_DOWN_ALLOW;
8753 I915_WRITE(LCPLL_CTL, val);
8754 POSTING_READ(LCPLL_CTL);
8755 }
8756 }
8757
8758 /*
8759 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8760 * source.
8761 */
8762 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8763 {
8764 uint32_t val;
8765
8766 val = I915_READ(LCPLL_CTL);
8767
8768 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8769 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8770 return;
8771
8772 /*
8773 * Make sure we're not on PC8 state before disabling PC8, otherwise
8774 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8775 */
8776 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8777
8778 if (val & LCPLL_POWER_DOWN_ALLOW) {
8779 val &= ~LCPLL_POWER_DOWN_ALLOW;
8780 I915_WRITE(LCPLL_CTL, val);
8781 POSTING_READ(LCPLL_CTL);
8782 }
8783
8784 val = hsw_read_dcomp(dev_priv);
8785 val |= D_COMP_COMP_FORCE;
8786 val &= ~D_COMP_COMP_DISABLE;
8787 hsw_write_dcomp(dev_priv, val);
8788
8789 val = I915_READ(LCPLL_CTL);
8790 val &= ~LCPLL_PLL_DISABLE;
8791 I915_WRITE(LCPLL_CTL, val);
8792
8793 if (intel_wait_for_register(dev_priv,
8794 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8795 5))
8796 DRM_ERROR("LCPLL not locked yet\n");
8797
8798 if (val & LCPLL_CD_SOURCE_FCLK) {
8799 val = I915_READ(LCPLL_CTL);
8800 val &= ~LCPLL_CD_SOURCE_FCLK;
8801 I915_WRITE(LCPLL_CTL, val);
8802
8803 if (wait_for_us((I915_READ(LCPLL_CTL) &
8804 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8805 DRM_ERROR("Switching back to LCPLL failed\n");
8806 }
8807
8808 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8809 intel_update_cdclk(dev_priv);
8810 }
8811
8812 /*
8813 * Package states C8 and deeper are really deep PC states that can only be
8814 * reached when all the devices on the system allow it, so even if the graphics
8815 * device allows PC8+, it doesn't mean the system will actually get to these
8816 * states. Our driver only allows PC8+ when going into runtime PM.
8817 *
8818 * The requirements for PC8+ are that all the outputs are disabled, the power
8819 * well is disabled and most interrupts are disabled, and these are also
8820 * requirements for runtime PM. When these conditions are met, we manually do
8821 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8822 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8823 * hang the machine.
8824 *
8825 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8826 * the state of some registers, so when we come back from PC8+ we need to
8827 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8828 * need to take care of the registers kept by RC6. Notice that this happens even
8829 * if we don't put the device in PCI D3 state (which is what currently happens
8830 * because of the runtime PM support).
8831 *
8832 * For more, read "Display Sequences for Package C8" on the hardware
8833 * documentation.
8834 */
8835 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8836 {
8837 uint32_t val;
8838
8839 DRM_DEBUG_KMS("Enabling package C8+\n");
8840
8841 if (HAS_PCH_LPT_LP(dev_priv)) {
8842 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8843 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8844 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8845 }
8846
8847 lpt_disable_clkout_dp(dev_priv);
8848 hsw_disable_lcpll(dev_priv, true, true);
8849 }
8850
8851 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8852 {
8853 uint32_t val;
8854
8855 DRM_DEBUG_KMS("Disabling package C8+\n");
8856
8857 hsw_restore_lcpll(dev_priv);
8858 lpt_init_pch_refclk(dev_priv);
8859
8860 if (HAS_PCH_LPT_LP(dev_priv)) {
8861 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8862 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8863 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8864 }
8865 }
8866
8867 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8868 struct intel_crtc_state *crtc_state)
8869 {
8870 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8871 struct intel_encoder *encoder =
8872 intel_ddi_get_crtc_new_encoder(crtc_state);
8873
8874 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8875 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8876 pipe_name(crtc->pipe));
8877 return -EINVAL;
8878 }
8879 }
8880
8881 crtc->lowfreq_avail = false;
8882
8883 return 0;
8884 }
8885
8886 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8887 enum port port,
8888 struct intel_crtc_state *pipe_config)
8889 {
8890 enum intel_dpll_id id;
8891 u32 temp;
8892
8893 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8894 id = temp >> (port * 2);
8895
8896 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8897 return;
8898
8899 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8900 }
8901
8902 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8903 enum port port,
8904 struct intel_crtc_state *pipe_config)
8905 {
8906 enum intel_dpll_id id;
8907
8908 switch (port) {
8909 case PORT_A:
8910 id = DPLL_ID_SKL_DPLL0;
8911 break;
8912 case PORT_B:
8913 id = DPLL_ID_SKL_DPLL1;
8914 break;
8915 case PORT_C:
8916 id = DPLL_ID_SKL_DPLL2;
8917 break;
8918 default:
8919 DRM_ERROR("Incorrect port type\n");
8920 return;
8921 }
8922
8923 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8924 }
8925
8926 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8927 enum port port,
8928 struct intel_crtc_state *pipe_config)
8929 {
8930 enum intel_dpll_id id;
8931 u32 temp;
8932
8933 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8934 id = temp >> (port * 3 + 1);
8935
8936 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8937 return;
8938
8939 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8940 }
8941
8942 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8943 enum port port,
8944 struct intel_crtc_state *pipe_config)
8945 {
8946 enum intel_dpll_id id;
8947 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8948
8949 switch (ddi_pll_sel) {
8950 case PORT_CLK_SEL_WRPLL1:
8951 id = DPLL_ID_WRPLL1;
8952 break;
8953 case PORT_CLK_SEL_WRPLL2:
8954 id = DPLL_ID_WRPLL2;
8955 break;
8956 case PORT_CLK_SEL_SPLL:
8957 id = DPLL_ID_SPLL;
8958 break;
8959 case PORT_CLK_SEL_LCPLL_810:
8960 id = DPLL_ID_LCPLL_810;
8961 break;
8962 case PORT_CLK_SEL_LCPLL_1350:
8963 id = DPLL_ID_LCPLL_1350;
8964 break;
8965 case PORT_CLK_SEL_LCPLL_2700:
8966 id = DPLL_ID_LCPLL_2700;
8967 break;
8968 default:
8969 MISSING_CASE(ddi_pll_sel);
8970 /* fall through */
8971 case PORT_CLK_SEL_NONE:
8972 return;
8973 }
8974
8975 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8976 }
8977
8978 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8979 struct intel_crtc_state *pipe_config,
8980 u64 *power_domain_mask)
8981 {
8982 struct drm_device *dev = crtc->base.dev;
8983 struct drm_i915_private *dev_priv = to_i915(dev);
8984 enum intel_display_power_domain power_domain;
8985 u32 tmp;
8986
8987 /*
8988 * The pipe->transcoder mapping is fixed with the exception of the eDP
8989 * transcoder handled below.
8990 */
8991 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8992
8993 /*
8994 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8995 * consistency and less surprising code; it's in always on power).
8996 */
8997 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8998 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8999 enum pipe trans_edp_pipe;
9000 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9001 default:
9002 WARN(1, "unknown pipe linked to edp transcoder\n");
9003 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9004 case TRANS_DDI_EDP_INPUT_A_ON:
9005 trans_edp_pipe = PIPE_A;
9006 break;
9007 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9008 trans_edp_pipe = PIPE_B;
9009 break;
9010 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9011 trans_edp_pipe = PIPE_C;
9012 break;
9013 }
9014
9015 if (trans_edp_pipe == crtc->pipe)
9016 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9017 }
9018
9019 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9020 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9021 return false;
9022 *power_domain_mask |= BIT_ULL(power_domain);
9023
9024 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9025
9026 return tmp & PIPECONF_ENABLE;
9027 }
9028
9029 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9030 struct intel_crtc_state *pipe_config,
9031 u64 *power_domain_mask)
9032 {
9033 struct drm_device *dev = crtc->base.dev;
9034 struct drm_i915_private *dev_priv = to_i915(dev);
9035 enum intel_display_power_domain power_domain;
9036 enum port port;
9037 enum transcoder cpu_transcoder;
9038 u32 tmp;
9039
9040 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9041 if (port == PORT_A)
9042 cpu_transcoder = TRANSCODER_DSI_A;
9043 else
9044 cpu_transcoder = TRANSCODER_DSI_C;
9045
9046 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9047 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9048 continue;
9049 *power_domain_mask |= BIT_ULL(power_domain);
9050
9051 /*
9052 * The PLL needs to be enabled with a valid divider
9053 * configuration, otherwise accessing DSI registers will hang
9054 * the machine. See BSpec North Display Engine
9055 * registers/MIPI[BXT]. We can break out here early, since we
9056 * need the same DSI PLL to be enabled for both DSI ports.
9057 */
9058 if (!intel_dsi_pll_is_enabled(dev_priv))
9059 break;
9060
9061 /* XXX: this works for video mode only */
9062 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9063 if (!(tmp & DPI_ENABLE))
9064 continue;
9065
9066 tmp = I915_READ(MIPI_CTRL(port));
9067 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9068 continue;
9069
9070 pipe_config->cpu_transcoder = cpu_transcoder;
9071 break;
9072 }
9073
9074 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9075 }
9076
9077 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9078 struct intel_crtc_state *pipe_config)
9079 {
9080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9081 struct intel_shared_dpll *pll;
9082 enum port port;
9083 uint32_t tmp;
9084
9085 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9086
9087 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9088
9089 if (IS_CANNONLAKE(dev_priv))
9090 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9091 else if (IS_GEN9_BC(dev_priv))
9092 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9093 else if (IS_GEN9_LP(dev_priv))
9094 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9095 else
9096 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9097
9098 pll = pipe_config->shared_dpll;
9099 if (pll) {
9100 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9101 &pipe_config->dpll_hw_state));
9102 }
9103
9104 /*
9105 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9106 * DDI E. So just check whether this pipe is wired to DDI E and whether
9107 * the PCH transcoder is on.
9108 */
9109 if (INTEL_GEN(dev_priv) < 9 &&
9110 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9111 pipe_config->has_pch_encoder = true;
9112
9113 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9114 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9115 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9116
9117 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9118 }
9119 }
9120
9121 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9122 struct intel_crtc_state *pipe_config)
9123 {
9124 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9125 enum intel_display_power_domain power_domain;
9126 u64 power_domain_mask;
9127 bool active;
9128
9129 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9130 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9131 return false;
9132 power_domain_mask = BIT_ULL(power_domain);
9133
9134 pipe_config->shared_dpll = NULL;
9135
9136 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9137
9138 if (IS_GEN9_LP(dev_priv) &&
9139 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9140 WARN_ON(active);
9141 active = true;
9142 }
9143
9144 if (!active)
9145 goto out;
9146
9147 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9148 haswell_get_ddi_port_state(crtc, pipe_config);
9149 intel_get_pipe_timings(crtc, pipe_config);
9150 }
9151
9152 intel_get_pipe_src_size(crtc, pipe_config);
9153
9154 pipe_config->gamma_mode =
9155 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9156
9157 if (INTEL_GEN(dev_priv) >= 9) {
9158 intel_crtc_init_scalers(crtc, pipe_config);
9159
9160 pipe_config->scaler_state.scaler_id = -1;
9161 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9162 }
9163
9164 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9165 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9166 power_domain_mask |= BIT_ULL(power_domain);
9167 if (INTEL_GEN(dev_priv) >= 9)
9168 skylake_get_pfit_config(crtc, pipe_config);
9169 else
9170 ironlake_get_pfit_config(crtc, pipe_config);
9171 }
9172
9173 if (IS_HASWELL(dev_priv))
9174 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9175 (I915_READ(IPS_CTL) & IPS_ENABLE);
9176
9177 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9178 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9179 pipe_config->pixel_multiplier =
9180 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9181 } else {
9182 pipe_config->pixel_multiplier = 1;
9183 }
9184
9185 out:
9186 for_each_power_domain(power_domain, power_domain_mask)
9187 intel_display_power_put(dev_priv, power_domain);
9188
9189 return active;
9190 }
9191
9192 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9193 {
9194 struct drm_i915_private *dev_priv =
9195 to_i915(plane_state->base.plane->dev);
9196 const struct drm_framebuffer *fb = plane_state->base.fb;
9197 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9198 u32 base;
9199
9200 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9201 base = obj->phys_handle->busaddr;
9202 else
9203 base = intel_plane_ggtt_offset(plane_state);
9204
9205 base += plane_state->main.offset;
9206
9207 /* ILK+ do this automagically */
9208 if (HAS_GMCH_DISPLAY(dev_priv) &&
9209 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9210 base += (plane_state->base.crtc_h *
9211 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9212
9213 return base;
9214 }
9215
9216 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9217 {
9218 int x = plane_state->base.crtc_x;
9219 int y = plane_state->base.crtc_y;
9220 u32 pos = 0;
9221
9222 if (x < 0) {
9223 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9224 x = -x;
9225 }
9226 pos |= x << CURSOR_X_SHIFT;
9227
9228 if (y < 0) {
9229 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9230 y = -y;
9231 }
9232 pos |= y << CURSOR_Y_SHIFT;
9233
9234 return pos;
9235 }
9236
9237 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9238 {
9239 const struct drm_mode_config *config =
9240 &plane_state->base.plane->dev->mode_config;
9241 int width = plane_state->base.crtc_w;
9242 int height = plane_state->base.crtc_h;
9243
9244 return width > 0 && width <= config->cursor_width &&
9245 height > 0 && height <= config->cursor_height;
9246 }
9247
9248 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9249 struct intel_plane_state *plane_state)
9250 {
9251 const struct drm_framebuffer *fb = plane_state->base.fb;
9252 int src_x, src_y;
9253 u32 offset;
9254 int ret;
9255
9256 ret = drm_plane_helper_check_state(&plane_state->base,
9257 &plane_state->clip,
9258 DRM_PLANE_HELPER_NO_SCALING,
9259 DRM_PLANE_HELPER_NO_SCALING,
9260 true, true);
9261 if (ret)
9262 return ret;
9263
9264 if (!fb)
9265 return 0;
9266
9267 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9268 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9269 return -EINVAL;
9270 }
9271
9272 src_x = plane_state->base.src_x >> 16;
9273 src_y = plane_state->base.src_y >> 16;
9274
9275 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9276 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9277
9278 if (src_x != 0 || src_y != 0) {
9279 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9280 return -EINVAL;
9281 }
9282
9283 plane_state->main.offset = offset;
9284
9285 return 0;
9286 }
9287
9288 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9289 const struct intel_plane_state *plane_state)
9290 {
9291 const struct drm_framebuffer *fb = plane_state->base.fb;
9292
9293 return CURSOR_ENABLE |
9294 CURSOR_GAMMA_ENABLE |
9295 CURSOR_FORMAT_ARGB |
9296 CURSOR_STRIDE(fb->pitches[0]);
9297 }
9298
9299 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9300 {
9301 int width = plane_state->base.crtc_w;
9302
9303 /*
9304 * 845g/865g are only limited by the width of their cursors,
9305 * the height is arbitrary up to the precision of the register.
9306 */
9307 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9308 }
9309
9310 static int i845_check_cursor(struct intel_plane *plane,
9311 struct intel_crtc_state *crtc_state,
9312 struct intel_plane_state *plane_state)
9313 {
9314 const struct drm_framebuffer *fb = plane_state->base.fb;
9315 int ret;
9316
9317 ret = intel_check_cursor(crtc_state, plane_state);
9318 if (ret)
9319 return ret;
9320
9321 /* if we want to turn off the cursor ignore width and height */
9322 if (!fb)
9323 return 0;
9324
9325 /* Check for which cursor types we support */
9326 if (!i845_cursor_size_ok(plane_state)) {
9327 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9328 plane_state->base.crtc_w,
9329 plane_state->base.crtc_h);
9330 return -EINVAL;
9331 }
9332
9333 switch (fb->pitches[0]) {
9334 case 256:
9335 case 512:
9336 case 1024:
9337 case 2048:
9338 break;
9339 default:
9340 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9341 fb->pitches[0]);
9342 return -EINVAL;
9343 }
9344
9345 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9346
9347 return 0;
9348 }
9349
9350 static void i845_update_cursor(struct intel_plane *plane,
9351 const struct intel_crtc_state *crtc_state,
9352 const struct intel_plane_state *plane_state)
9353 {
9354 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9355 u32 cntl = 0, base = 0, pos = 0, size = 0;
9356 unsigned long irqflags;
9357
9358 if (plane_state && plane_state->base.visible) {
9359 unsigned int width = plane_state->base.crtc_w;
9360 unsigned int height = plane_state->base.crtc_h;
9361
9362 cntl = plane_state->ctl;
9363 size = (height << 12) | width;
9364
9365 base = intel_cursor_base(plane_state);
9366 pos = intel_cursor_position(plane_state);
9367 }
9368
9369 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9370
9371 /* On these chipsets we can only modify the base/size/stride
9372 * whilst the cursor is disabled.
9373 */
9374 if (plane->cursor.base != base ||
9375 plane->cursor.size != size ||
9376 plane->cursor.cntl != cntl) {
9377 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9378 I915_WRITE_FW(CURBASE(PIPE_A), base);
9379 I915_WRITE_FW(CURSIZE, size);
9380 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9381 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9382
9383 plane->cursor.base = base;
9384 plane->cursor.size = size;
9385 plane->cursor.cntl = cntl;
9386 } else {
9387 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9388 }
9389
9390 POSTING_READ_FW(CURCNTR(PIPE_A));
9391
9392 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9393 }
9394
9395 static void i845_disable_cursor(struct intel_plane *plane,
9396 struct intel_crtc *crtc)
9397 {
9398 i845_update_cursor(plane, NULL, NULL);
9399 }
9400
9401 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9402 const struct intel_plane_state *plane_state)
9403 {
9404 struct drm_i915_private *dev_priv =
9405 to_i915(plane_state->base.plane->dev);
9406 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9407 u32 cntl;
9408
9409 cntl = MCURSOR_GAMMA_ENABLE;
9410
9411 if (HAS_DDI(dev_priv))
9412 cntl |= CURSOR_PIPE_CSC_ENABLE;
9413
9414 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9415
9416 switch (plane_state->base.crtc_w) {
9417 case 64:
9418 cntl |= CURSOR_MODE_64_ARGB_AX;
9419 break;
9420 case 128:
9421 cntl |= CURSOR_MODE_128_ARGB_AX;
9422 break;
9423 case 256:
9424 cntl |= CURSOR_MODE_256_ARGB_AX;
9425 break;
9426 default:
9427 MISSING_CASE(plane_state->base.crtc_w);
9428 return 0;
9429 }
9430
9431 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9432 cntl |= CURSOR_ROTATE_180;
9433
9434 return cntl;
9435 }
9436
9437 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9438 {
9439 struct drm_i915_private *dev_priv =
9440 to_i915(plane_state->base.plane->dev);
9441 int width = plane_state->base.crtc_w;
9442 int height = plane_state->base.crtc_h;
9443
9444 if (!intel_cursor_size_ok(plane_state))
9445 return false;
9446
9447 /* Cursor width is limited to a few power-of-two sizes */
9448 switch (width) {
9449 case 256:
9450 case 128:
9451 case 64:
9452 break;
9453 default:
9454 return false;
9455 }
9456
9457 /*
9458 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9459 * height from 8 lines up to the cursor width, when the
9460 * cursor is not rotated. Everything else requires square
9461 * cursors.
9462 */
9463 if (HAS_CUR_FBC(dev_priv) &&
9464 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9465 if (height < 8 || height > width)
9466 return false;
9467 } else {
9468 if (height != width)
9469 return false;
9470 }
9471
9472 return true;
9473 }
9474
9475 static int i9xx_check_cursor(struct intel_plane *plane,
9476 struct intel_crtc_state *crtc_state,
9477 struct intel_plane_state *plane_state)
9478 {
9479 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9480 const struct drm_framebuffer *fb = plane_state->base.fb;
9481 enum pipe pipe = plane->pipe;
9482 int ret;
9483
9484 ret = intel_check_cursor(crtc_state, plane_state);
9485 if (ret)
9486 return ret;
9487
9488 /* if we want to turn off the cursor ignore width and height */
9489 if (!fb)
9490 return 0;
9491
9492 /* Check for which cursor types we support */
9493 if (!i9xx_cursor_size_ok(plane_state)) {
9494 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9495 plane_state->base.crtc_w,
9496 plane_state->base.crtc_h);
9497 return -EINVAL;
9498 }
9499
9500 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9501 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9502 fb->pitches[0], plane_state->base.crtc_w);
9503 return -EINVAL;
9504 }
9505
9506 /*
9507 * There's something wrong with the cursor on CHV pipe C.
9508 * If it straddles the left edge of the screen then
9509 * moving it away from the edge or disabling it often
9510 * results in a pipe underrun, and often that can lead to
9511 * dead pipe (constant underrun reported, and it scans
9512 * out just a solid color). To recover from that, the
9513 * display power well must be turned off and on again.
9514 * Refuse the put the cursor into that compromised position.
9515 */
9516 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9517 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9518 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9519 return -EINVAL;
9520 }
9521
9522 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9523
9524 return 0;
9525 }
9526
9527 static void i9xx_update_cursor(struct intel_plane *plane,
9528 const struct intel_crtc_state *crtc_state,
9529 const struct intel_plane_state *plane_state)
9530 {
9531 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9532 enum pipe pipe = plane->pipe;
9533 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9534 unsigned long irqflags;
9535
9536 if (plane_state && plane_state->base.visible) {
9537 cntl = plane_state->ctl;
9538
9539 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9540 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9541
9542 base = intel_cursor_base(plane_state);
9543 pos = intel_cursor_position(plane_state);
9544 }
9545
9546 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9547
9548 /*
9549 * On some platforms writing CURCNTR first will also
9550 * cause CURPOS to be armed by the CURBASE write.
9551 * Without the CURCNTR write the CURPOS write would
9552 * arm itself.
9553 *
9554 * CURCNTR and CUR_FBC_CTL are always
9555 * armed by the CURBASE write only.
9556 */
9557 if (plane->cursor.base != base ||
9558 plane->cursor.size != fbc_ctl ||
9559 plane->cursor.cntl != cntl) {
9560 I915_WRITE_FW(CURCNTR(pipe), cntl);
9561 if (HAS_CUR_FBC(dev_priv))
9562 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9563 I915_WRITE_FW(CURPOS(pipe), pos);
9564 I915_WRITE_FW(CURBASE(pipe), base);
9565
9566 plane->cursor.base = base;
9567 plane->cursor.size = fbc_ctl;
9568 plane->cursor.cntl = cntl;
9569 } else {
9570 I915_WRITE_FW(CURPOS(pipe), pos);
9571 }
9572
9573 POSTING_READ_FW(CURBASE(pipe));
9574
9575 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9576 }
9577
9578 static void i9xx_disable_cursor(struct intel_plane *plane,
9579 struct intel_crtc *crtc)
9580 {
9581 i9xx_update_cursor(plane, NULL, NULL);
9582 }
9583
9584
9585 /* VESA 640x480x72Hz mode to set on the pipe */
9586 static struct drm_display_mode load_detect_mode = {
9587 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9588 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9589 };
9590
9591 struct drm_framebuffer *
9592 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9593 struct drm_mode_fb_cmd2 *mode_cmd)
9594 {
9595 struct intel_framebuffer *intel_fb;
9596 int ret;
9597
9598 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9599 if (!intel_fb)
9600 return ERR_PTR(-ENOMEM);
9601
9602 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9603 if (ret)
9604 goto err;
9605
9606 return &intel_fb->base;
9607
9608 err:
9609 kfree(intel_fb);
9610 return ERR_PTR(ret);
9611 }
9612
9613 static u32
9614 intel_framebuffer_pitch_for_width(int width, int bpp)
9615 {
9616 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9617 return ALIGN(pitch, 64);
9618 }
9619
9620 static u32
9621 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9622 {
9623 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9624 return PAGE_ALIGN(pitch * mode->vdisplay);
9625 }
9626
9627 static struct drm_framebuffer *
9628 intel_framebuffer_create_for_mode(struct drm_device *dev,
9629 struct drm_display_mode *mode,
9630 int depth, int bpp)
9631 {
9632 struct drm_framebuffer *fb;
9633 struct drm_i915_gem_object *obj;
9634 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9635
9636 obj = i915_gem_object_create(to_i915(dev),
9637 intel_framebuffer_size_for_mode(mode, bpp));
9638 if (IS_ERR(obj))
9639 return ERR_CAST(obj);
9640
9641 mode_cmd.width = mode->hdisplay;
9642 mode_cmd.height = mode->vdisplay;
9643 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9644 bpp);
9645 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9646
9647 fb = intel_framebuffer_create(obj, &mode_cmd);
9648 if (IS_ERR(fb))
9649 i915_gem_object_put(obj);
9650
9651 return fb;
9652 }
9653
9654 static struct drm_framebuffer *
9655 mode_fits_in_fbdev(struct drm_device *dev,
9656 struct drm_display_mode *mode)
9657 {
9658 #ifdef CONFIG_DRM_FBDEV_EMULATION
9659 struct drm_i915_private *dev_priv = to_i915(dev);
9660 struct drm_i915_gem_object *obj;
9661 struct drm_framebuffer *fb;
9662
9663 if (!dev_priv->fbdev)
9664 return NULL;
9665
9666 if (!dev_priv->fbdev->fb)
9667 return NULL;
9668
9669 obj = dev_priv->fbdev->fb->obj;
9670 BUG_ON(!obj);
9671
9672 fb = &dev_priv->fbdev->fb->base;
9673 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9674 fb->format->cpp[0] * 8))
9675 return NULL;
9676
9677 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9678 return NULL;
9679
9680 drm_framebuffer_reference(fb);
9681 return fb;
9682 #else
9683 return NULL;
9684 #endif
9685 }
9686
9687 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9688 struct drm_crtc *crtc,
9689 struct drm_display_mode *mode,
9690 struct drm_framebuffer *fb,
9691 int x, int y)
9692 {
9693 struct drm_plane_state *plane_state;
9694 int hdisplay, vdisplay;
9695 int ret;
9696
9697 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9698 if (IS_ERR(plane_state))
9699 return PTR_ERR(plane_state);
9700
9701 if (mode)
9702 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9703 else
9704 hdisplay = vdisplay = 0;
9705
9706 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9707 if (ret)
9708 return ret;
9709 drm_atomic_set_fb_for_plane(plane_state, fb);
9710 plane_state->crtc_x = 0;
9711 plane_state->crtc_y = 0;
9712 plane_state->crtc_w = hdisplay;
9713 plane_state->crtc_h = vdisplay;
9714 plane_state->src_x = x << 16;
9715 plane_state->src_y = y << 16;
9716 plane_state->src_w = hdisplay << 16;
9717 plane_state->src_h = vdisplay << 16;
9718
9719 return 0;
9720 }
9721
9722 int intel_get_load_detect_pipe(struct drm_connector *connector,
9723 struct drm_display_mode *mode,
9724 struct intel_load_detect_pipe *old,
9725 struct drm_modeset_acquire_ctx *ctx)
9726 {
9727 struct intel_crtc *intel_crtc;
9728 struct intel_encoder *intel_encoder =
9729 intel_attached_encoder(connector);
9730 struct drm_crtc *possible_crtc;
9731 struct drm_encoder *encoder = &intel_encoder->base;
9732 struct drm_crtc *crtc = NULL;
9733 struct drm_device *dev = encoder->dev;
9734 struct drm_i915_private *dev_priv = to_i915(dev);
9735 struct drm_framebuffer *fb;
9736 struct drm_mode_config *config = &dev->mode_config;
9737 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9738 struct drm_connector_state *connector_state;
9739 struct intel_crtc_state *crtc_state;
9740 int ret, i = -1;
9741
9742 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9743 connector->base.id, connector->name,
9744 encoder->base.id, encoder->name);
9745
9746 old->restore_state = NULL;
9747
9748 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9749
9750 /*
9751 * Algorithm gets a little messy:
9752 *
9753 * - if the connector already has an assigned crtc, use it (but make
9754 * sure it's on first)
9755 *
9756 * - try to find the first unused crtc that can drive this connector,
9757 * and use that if we find one
9758 */
9759
9760 /* See if we already have a CRTC for this connector */
9761 if (connector->state->crtc) {
9762 crtc = connector->state->crtc;
9763
9764 ret = drm_modeset_lock(&crtc->mutex, ctx);
9765 if (ret)
9766 goto fail;
9767
9768 /* Make sure the crtc and connector are running */
9769 goto found;
9770 }
9771
9772 /* Find an unused one (if possible) */
9773 for_each_crtc(dev, possible_crtc) {
9774 i++;
9775 if (!(encoder->possible_crtcs & (1 << i)))
9776 continue;
9777
9778 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9779 if (ret)
9780 goto fail;
9781
9782 if (possible_crtc->state->enable) {
9783 drm_modeset_unlock(&possible_crtc->mutex);
9784 continue;
9785 }
9786
9787 crtc = possible_crtc;
9788 break;
9789 }
9790
9791 /*
9792 * If we didn't find an unused CRTC, don't use any.
9793 */
9794 if (!crtc) {
9795 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9796 ret = -ENODEV;
9797 goto fail;
9798 }
9799
9800 found:
9801 intel_crtc = to_intel_crtc(crtc);
9802
9803 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9804 if (ret)
9805 goto fail;
9806
9807 state = drm_atomic_state_alloc(dev);
9808 restore_state = drm_atomic_state_alloc(dev);
9809 if (!state || !restore_state) {
9810 ret = -ENOMEM;
9811 goto fail;
9812 }
9813
9814 state->acquire_ctx = ctx;
9815 restore_state->acquire_ctx = ctx;
9816
9817 connector_state = drm_atomic_get_connector_state(state, connector);
9818 if (IS_ERR(connector_state)) {
9819 ret = PTR_ERR(connector_state);
9820 goto fail;
9821 }
9822
9823 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9824 if (ret)
9825 goto fail;
9826
9827 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9828 if (IS_ERR(crtc_state)) {
9829 ret = PTR_ERR(crtc_state);
9830 goto fail;
9831 }
9832
9833 crtc_state->base.active = crtc_state->base.enable = true;
9834
9835 if (!mode)
9836 mode = &load_detect_mode;
9837
9838 /* We need a framebuffer large enough to accommodate all accesses
9839 * that the plane may generate whilst we perform load detection.
9840 * We can not rely on the fbcon either being present (we get called
9841 * during its initialisation to detect all boot displays, or it may
9842 * not even exist) or that it is large enough to satisfy the
9843 * requested mode.
9844 */
9845 fb = mode_fits_in_fbdev(dev, mode);
9846 if (fb == NULL) {
9847 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9848 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9849 } else
9850 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9851 if (IS_ERR(fb)) {
9852 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9853 ret = PTR_ERR(fb);
9854 goto fail;
9855 }
9856
9857 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9858 if (ret)
9859 goto fail;
9860
9861 drm_framebuffer_unreference(fb);
9862
9863 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9864 if (ret)
9865 goto fail;
9866
9867 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9868 if (!ret)
9869 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9870 if (!ret)
9871 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9872 if (ret) {
9873 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9874 goto fail;
9875 }
9876
9877 ret = drm_atomic_commit(state);
9878 if (ret) {
9879 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9880 goto fail;
9881 }
9882
9883 old->restore_state = restore_state;
9884 drm_atomic_state_put(state);
9885
9886 /* let the connector get through one full cycle before testing */
9887 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9888 return true;
9889
9890 fail:
9891 if (state) {
9892 drm_atomic_state_put(state);
9893 state = NULL;
9894 }
9895 if (restore_state) {
9896 drm_atomic_state_put(restore_state);
9897 restore_state = NULL;
9898 }
9899
9900 if (ret == -EDEADLK)
9901 return ret;
9902
9903 return false;
9904 }
9905
9906 void intel_release_load_detect_pipe(struct drm_connector *connector,
9907 struct intel_load_detect_pipe *old,
9908 struct drm_modeset_acquire_ctx *ctx)
9909 {
9910 struct intel_encoder *intel_encoder =
9911 intel_attached_encoder(connector);
9912 struct drm_encoder *encoder = &intel_encoder->base;
9913 struct drm_atomic_state *state = old->restore_state;
9914 int ret;
9915
9916 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9917 connector->base.id, connector->name,
9918 encoder->base.id, encoder->name);
9919
9920 if (!state)
9921 return;
9922
9923 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9924 if (ret)
9925 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9926 drm_atomic_state_put(state);
9927 }
9928
9929 static int i9xx_pll_refclk(struct drm_device *dev,
9930 const struct intel_crtc_state *pipe_config)
9931 {
9932 struct drm_i915_private *dev_priv = to_i915(dev);
9933 u32 dpll = pipe_config->dpll_hw_state.dpll;
9934
9935 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9936 return dev_priv->vbt.lvds_ssc_freq;
9937 else if (HAS_PCH_SPLIT(dev_priv))
9938 return 120000;
9939 else if (!IS_GEN2(dev_priv))
9940 return 96000;
9941 else
9942 return 48000;
9943 }
9944
9945 /* Returns the clock of the currently programmed mode of the given pipe. */
9946 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9947 struct intel_crtc_state *pipe_config)
9948 {
9949 struct drm_device *dev = crtc->base.dev;
9950 struct drm_i915_private *dev_priv = to_i915(dev);
9951 int pipe = pipe_config->cpu_transcoder;
9952 u32 dpll = pipe_config->dpll_hw_state.dpll;
9953 u32 fp;
9954 struct dpll clock;
9955 int port_clock;
9956 int refclk = i9xx_pll_refclk(dev, pipe_config);
9957
9958 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9959 fp = pipe_config->dpll_hw_state.fp0;
9960 else
9961 fp = pipe_config->dpll_hw_state.fp1;
9962
9963 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9964 if (IS_PINEVIEW(dev_priv)) {
9965 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9966 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9967 } else {
9968 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9969 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9970 }
9971
9972 if (!IS_GEN2(dev_priv)) {
9973 if (IS_PINEVIEW(dev_priv))
9974 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9975 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9976 else
9977 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9978 DPLL_FPA01_P1_POST_DIV_SHIFT);
9979
9980 switch (dpll & DPLL_MODE_MASK) {
9981 case DPLLB_MODE_DAC_SERIAL:
9982 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9983 5 : 10;
9984 break;
9985 case DPLLB_MODE_LVDS:
9986 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9987 7 : 14;
9988 break;
9989 default:
9990 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9991 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9992 return;
9993 }
9994
9995 if (IS_PINEVIEW(dev_priv))
9996 port_clock = pnv_calc_dpll_params(refclk, &clock);
9997 else
9998 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9999 } else {
10000 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10001 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10002
10003 if (is_lvds) {
10004 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10005 DPLL_FPA01_P1_POST_DIV_SHIFT);
10006
10007 if (lvds & LVDS_CLKB_POWER_UP)
10008 clock.p2 = 7;
10009 else
10010 clock.p2 = 14;
10011 } else {
10012 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10013 clock.p1 = 2;
10014 else {
10015 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10016 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10017 }
10018 if (dpll & PLL_P2_DIVIDE_BY_4)
10019 clock.p2 = 4;
10020 else
10021 clock.p2 = 2;
10022 }
10023
10024 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10025 }
10026
10027 /*
10028 * This value includes pixel_multiplier. We will use
10029 * port_clock to compute adjusted_mode.crtc_clock in the
10030 * encoder's get_config() function.
10031 */
10032 pipe_config->port_clock = port_clock;
10033 }
10034
10035 int intel_dotclock_calculate(int link_freq,
10036 const struct intel_link_m_n *m_n)
10037 {
10038 /*
10039 * The calculation for the data clock is:
10040 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10041 * But we want to avoid losing precison if possible, so:
10042 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10043 *
10044 * and the link clock is simpler:
10045 * link_clock = (m * link_clock) / n
10046 */
10047
10048 if (!m_n->link_n)
10049 return 0;
10050
10051 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10052 }
10053
10054 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10055 struct intel_crtc_state *pipe_config)
10056 {
10057 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10058
10059 /* read out port_clock from the DPLL */
10060 i9xx_crtc_clock_get(crtc, pipe_config);
10061
10062 /*
10063 * In case there is an active pipe without active ports,
10064 * we may need some idea for the dotclock anyway.
10065 * Calculate one based on the FDI configuration.
10066 */
10067 pipe_config->base.adjusted_mode.crtc_clock =
10068 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10069 &pipe_config->fdi_m_n);
10070 }
10071
10072 /** Returns the currently programmed mode of the given pipe. */
10073 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10074 struct drm_crtc *crtc)
10075 {
10076 struct drm_i915_private *dev_priv = to_i915(dev);
10077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10079 struct drm_display_mode *mode;
10080 struct intel_crtc_state *pipe_config;
10081 int htot = I915_READ(HTOTAL(cpu_transcoder));
10082 int hsync = I915_READ(HSYNC(cpu_transcoder));
10083 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10084 int vsync = I915_READ(VSYNC(cpu_transcoder));
10085 enum pipe pipe = intel_crtc->pipe;
10086
10087 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10088 if (!mode)
10089 return NULL;
10090
10091 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10092 if (!pipe_config) {
10093 kfree(mode);
10094 return NULL;
10095 }
10096
10097 /*
10098 * Construct a pipe_config sufficient for getting the clock info
10099 * back out of crtc_clock_get.
10100 *
10101 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10102 * to use a real value here instead.
10103 */
10104 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10105 pipe_config->pixel_multiplier = 1;
10106 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10107 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10108 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10109 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10110
10111 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10112 mode->hdisplay = (htot & 0xffff) + 1;
10113 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10114 mode->hsync_start = (hsync & 0xffff) + 1;
10115 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10116 mode->vdisplay = (vtot & 0xffff) + 1;
10117 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10118 mode->vsync_start = (vsync & 0xffff) + 1;
10119 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10120
10121 drm_mode_set_name(mode);
10122
10123 kfree(pipe_config);
10124
10125 return mode;
10126 }
10127
10128 static void intel_crtc_destroy(struct drm_crtc *crtc)
10129 {
10130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10131 struct drm_device *dev = crtc->dev;
10132 struct intel_flip_work *work;
10133
10134 spin_lock_irq(&dev->event_lock);
10135 work = intel_crtc->flip_work;
10136 intel_crtc->flip_work = NULL;
10137 spin_unlock_irq(&dev->event_lock);
10138
10139 if (work) {
10140 cancel_work_sync(&work->mmio_work);
10141 cancel_work_sync(&work->unpin_work);
10142 kfree(work);
10143 }
10144
10145 drm_crtc_cleanup(crtc);
10146
10147 kfree(intel_crtc);
10148 }
10149
10150 static void intel_unpin_work_fn(struct work_struct *__work)
10151 {
10152 struct intel_flip_work *work =
10153 container_of(__work, struct intel_flip_work, unpin_work);
10154 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10155 struct drm_device *dev = crtc->base.dev;
10156 struct drm_plane *primary = crtc->base.primary;
10157
10158 if (is_mmio_work(work))
10159 flush_work(&work->mmio_work);
10160
10161 mutex_lock(&dev->struct_mutex);
10162 intel_unpin_fb_vma(work->old_vma);
10163 i915_gem_object_put(work->pending_flip_obj);
10164 mutex_unlock(&dev->struct_mutex);
10165
10166 i915_gem_request_put(work->flip_queued_req);
10167
10168 intel_frontbuffer_flip_complete(to_i915(dev),
10169 to_intel_plane(primary)->frontbuffer_bit);
10170 intel_fbc_post_update(crtc);
10171 drm_framebuffer_unreference(work->old_fb);
10172
10173 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10174 atomic_dec(&crtc->unpin_work_count);
10175
10176 kfree(work);
10177 }
10178
10179 /* Is 'a' after or equal to 'b'? */
10180 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10181 {
10182 return !((a - b) & 0x80000000);
10183 }
10184
10185 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10186 struct intel_flip_work *work)
10187 {
10188 struct drm_device *dev = crtc->base.dev;
10189 struct drm_i915_private *dev_priv = to_i915(dev);
10190
10191 if (abort_flip_on_reset(crtc))
10192 return true;
10193
10194 /*
10195 * The relevant registers doen't exist on pre-ctg.
10196 * As the flip done interrupt doesn't trigger for mmio
10197 * flips on gmch platforms, a flip count check isn't
10198 * really needed there. But since ctg has the registers,
10199 * include it in the check anyway.
10200 */
10201 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10202 return true;
10203
10204 /*
10205 * BDW signals flip done immediately if the plane
10206 * is disabled, even if the plane enable is already
10207 * armed to occur at the next vblank :(
10208 */
10209
10210 /*
10211 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10212 * used the same base address. In that case the mmio flip might
10213 * have completed, but the CS hasn't even executed the flip yet.
10214 *
10215 * A flip count check isn't enough as the CS might have updated
10216 * the base address just after start of vblank, but before we
10217 * managed to process the interrupt. This means we'd complete the
10218 * CS flip too soon.
10219 *
10220 * Combining both checks should get us a good enough result. It may
10221 * still happen that the CS flip has been executed, but has not
10222 * yet actually completed. But in case the base address is the same
10223 * anyway, we don't really care.
10224 */
10225 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10226 crtc->flip_work->gtt_offset &&
10227 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10228 crtc->flip_work->flip_count);
10229 }
10230
10231 static bool
10232 __pageflip_finished_mmio(struct intel_crtc *crtc,
10233 struct intel_flip_work *work)
10234 {
10235 /*
10236 * MMIO work completes when vblank is different from
10237 * flip_queued_vblank.
10238 *
10239 * Reset counter value doesn't matter, this is handled by
10240 * i915_wait_request finishing early, so no need to handle
10241 * reset here.
10242 */
10243 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10244 }
10245
10246
10247 static bool pageflip_finished(struct intel_crtc *crtc,
10248 struct intel_flip_work *work)
10249 {
10250 if (!atomic_read(&work->pending))
10251 return false;
10252
10253 smp_rmb();
10254
10255 if (is_mmio_work(work))
10256 return __pageflip_finished_mmio(crtc, work);
10257 else
10258 return __pageflip_finished_cs(crtc, work);
10259 }
10260
10261 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10262 {
10263 struct drm_device *dev = &dev_priv->drm;
10264 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10265 struct intel_flip_work *work;
10266 unsigned long flags;
10267
10268 /* Ignore early vblank irqs */
10269 if (!crtc)
10270 return;
10271
10272 /*
10273 * This is called both by irq handlers and the reset code (to complete
10274 * lost pageflips) so needs the full irqsave spinlocks.
10275 */
10276 spin_lock_irqsave(&dev->event_lock, flags);
10277 work = crtc->flip_work;
10278
10279 if (work != NULL &&
10280 !is_mmio_work(work) &&
10281 pageflip_finished(crtc, work))
10282 page_flip_completed(crtc);
10283
10284 spin_unlock_irqrestore(&dev->event_lock, flags);
10285 }
10286
10287 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10288 {
10289 struct drm_device *dev = &dev_priv->drm;
10290 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10291 struct intel_flip_work *work;
10292 unsigned long flags;
10293
10294 /* Ignore early vblank irqs */
10295 if (!crtc)
10296 return;
10297
10298 /*
10299 * This is called both by irq handlers and the reset code (to complete
10300 * lost pageflips) so needs the full irqsave spinlocks.
10301 */
10302 spin_lock_irqsave(&dev->event_lock, flags);
10303 work = crtc->flip_work;
10304
10305 if (work != NULL &&
10306 is_mmio_work(work) &&
10307 pageflip_finished(crtc, work))
10308 page_flip_completed(crtc);
10309
10310 spin_unlock_irqrestore(&dev->event_lock, flags);
10311 }
10312
10313 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10314 struct intel_flip_work *work)
10315 {
10316 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10317
10318 /* Ensure that the work item is consistent when activating it ... */
10319 smp_mb__before_atomic();
10320 atomic_set(&work->pending, 1);
10321 }
10322
10323 static int intel_gen2_queue_flip(struct drm_device *dev,
10324 struct drm_crtc *crtc,
10325 struct drm_framebuffer *fb,
10326 struct drm_i915_gem_object *obj,
10327 struct drm_i915_gem_request *req,
10328 uint32_t flags)
10329 {
10330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10331 u32 flip_mask, *cs;
10332
10333 cs = intel_ring_begin(req, 6);
10334 if (IS_ERR(cs))
10335 return PTR_ERR(cs);
10336
10337 /* Can't queue multiple flips, so wait for the previous
10338 * one to finish before executing the next.
10339 */
10340 if (intel_crtc->plane)
10341 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10342 else
10343 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10344 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10345 *cs++ = MI_NOOP;
10346 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10347 *cs++ = fb->pitches[0];
10348 *cs++ = intel_crtc->flip_work->gtt_offset;
10349 *cs++ = 0; /* aux display base address, unused */
10350
10351 return 0;
10352 }
10353
10354 static int intel_gen3_queue_flip(struct drm_device *dev,
10355 struct drm_crtc *crtc,
10356 struct drm_framebuffer *fb,
10357 struct drm_i915_gem_object *obj,
10358 struct drm_i915_gem_request *req,
10359 uint32_t flags)
10360 {
10361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10362 u32 flip_mask, *cs;
10363
10364 cs = intel_ring_begin(req, 6);
10365 if (IS_ERR(cs))
10366 return PTR_ERR(cs);
10367
10368 if (intel_crtc->plane)
10369 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10370 else
10371 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10372 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10373 *cs++ = MI_NOOP;
10374 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10375 *cs++ = fb->pitches[0];
10376 *cs++ = intel_crtc->flip_work->gtt_offset;
10377 *cs++ = MI_NOOP;
10378
10379 return 0;
10380 }
10381
10382 static int intel_gen4_queue_flip(struct drm_device *dev,
10383 struct drm_crtc *crtc,
10384 struct drm_framebuffer *fb,
10385 struct drm_i915_gem_object *obj,
10386 struct drm_i915_gem_request *req,
10387 uint32_t flags)
10388 {
10389 struct drm_i915_private *dev_priv = to_i915(dev);
10390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10391 u32 pf, pipesrc, *cs;
10392
10393 cs = intel_ring_begin(req, 4);
10394 if (IS_ERR(cs))
10395 return PTR_ERR(cs);
10396
10397 /* i965+ uses the linear or tiled offsets from the
10398 * Display Registers (which do not change across a page-flip)
10399 * so we need only reprogram the base address.
10400 */
10401 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10402 *cs++ = fb->pitches[0];
10403 *cs++ = intel_crtc->flip_work->gtt_offset |
10404 intel_fb_modifier_to_tiling(fb->modifier);
10405
10406 /* XXX Enabling the panel-fitter across page-flip is so far
10407 * untested on non-native modes, so ignore it for now.
10408 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10409 */
10410 pf = 0;
10411 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10412 *cs++ = pf | pipesrc;
10413
10414 return 0;
10415 }
10416
10417 static int intel_gen6_queue_flip(struct drm_device *dev,
10418 struct drm_crtc *crtc,
10419 struct drm_framebuffer *fb,
10420 struct drm_i915_gem_object *obj,
10421 struct drm_i915_gem_request *req,
10422 uint32_t flags)
10423 {
10424 struct drm_i915_private *dev_priv = to_i915(dev);
10425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10426 u32 pf, pipesrc, *cs;
10427
10428 cs = intel_ring_begin(req, 4);
10429 if (IS_ERR(cs))
10430 return PTR_ERR(cs);
10431
10432 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10433 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10434 *cs++ = intel_crtc->flip_work->gtt_offset;
10435
10436 /* Contrary to the suggestions in the documentation,
10437 * "Enable Panel Fitter" does not seem to be required when page
10438 * flipping with a non-native mode, and worse causes a normal
10439 * modeset to fail.
10440 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10441 */
10442 pf = 0;
10443 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10444 *cs++ = pf | pipesrc;
10445
10446 return 0;
10447 }
10448
10449 static int intel_gen7_queue_flip(struct drm_device *dev,
10450 struct drm_crtc *crtc,
10451 struct drm_framebuffer *fb,
10452 struct drm_i915_gem_object *obj,
10453 struct drm_i915_gem_request *req,
10454 uint32_t flags)
10455 {
10456 struct drm_i915_private *dev_priv = to_i915(dev);
10457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10458 u32 *cs, plane_bit = 0;
10459 int len, ret;
10460
10461 switch (intel_crtc->plane) {
10462 case PLANE_A:
10463 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10464 break;
10465 case PLANE_B:
10466 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10467 break;
10468 case PLANE_C:
10469 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10470 break;
10471 default:
10472 WARN_ONCE(1, "unknown plane in flip command\n");
10473 return -ENODEV;
10474 }
10475
10476 len = 4;
10477 if (req->engine->id == RCS) {
10478 len += 6;
10479 /*
10480 * On Gen 8, SRM is now taking an extra dword to accommodate
10481 * 48bits addresses, and we need a NOOP for the batch size to
10482 * stay even.
10483 */
10484 if (IS_GEN8(dev_priv))
10485 len += 2;
10486 }
10487
10488 /*
10489 * BSpec MI_DISPLAY_FLIP for IVB:
10490 * "The full packet must be contained within the same cache line."
10491 *
10492 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10493 * cacheline, if we ever start emitting more commands before
10494 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10495 * then do the cacheline alignment, and finally emit the
10496 * MI_DISPLAY_FLIP.
10497 */
10498 ret = intel_ring_cacheline_align(req);
10499 if (ret)
10500 return ret;
10501
10502 cs = intel_ring_begin(req, len);
10503 if (IS_ERR(cs))
10504 return PTR_ERR(cs);
10505
10506 /* Unmask the flip-done completion message. Note that the bspec says that
10507 * we should do this for both the BCS and RCS, and that we must not unmask
10508 * more than one flip event at any time (or ensure that one flip message
10509 * can be sent by waiting for flip-done prior to queueing new flips).
10510 * Experimentation says that BCS works despite DERRMR masking all
10511 * flip-done completion events and that unmasking all planes at once
10512 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10513 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10514 */
10515 if (req->engine->id == RCS) {
10516 *cs++ = MI_LOAD_REGISTER_IMM(1);
10517 *cs++ = i915_mmio_reg_offset(DERRMR);
10518 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10519 DERRMR_PIPEB_PRI_FLIP_DONE |
10520 DERRMR_PIPEC_PRI_FLIP_DONE);
10521 if (IS_GEN8(dev_priv))
10522 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10523 MI_SRM_LRM_GLOBAL_GTT;
10524 else
10525 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10526 *cs++ = i915_mmio_reg_offset(DERRMR);
10527 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10528 if (IS_GEN8(dev_priv)) {
10529 *cs++ = 0;
10530 *cs++ = MI_NOOP;
10531 }
10532 }
10533
10534 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10535 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10536 *cs++ = intel_crtc->flip_work->gtt_offset;
10537 *cs++ = MI_NOOP;
10538
10539 return 0;
10540 }
10541
10542 static bool use_mmio_flip(struct intel_engine_cs *engine,
10543 struct drm_i915_gem_object *obj)
10544 {
10545 /*
10546 * This is not being used for older platforms, because
10547 * non-availability of flip done interrupt forces us to use
10548 * CS flips. Older platforms derive flip done using some clever
10549 * tricks involving the flip_pending status bits and vblank irqs.
10550 * So using MMIO flips there would disrupt this mechanism.
10551 */
10552
10553 if (engine == NULL)
10554 return true;
10555
10556 if (INTEL_GEN(engine->i915) < 5)
10557 return false;
10558
10559 if (i915.use_mmio_flip < 0)
10560 return false;
10561 else if (i915.use_mmio_flip > 0)
10562 return true;
10563 else if (i915.enable_execlists)
10564 return true;
10565
10566 return engine != i915_gem_object_last_write_engine(obj);
10567 }
10568
10569 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10570 unsigned int rotation,
10571 struct intel_flip_work *work)
10572 {
10573 struct drm_device *dev = intel_crtc->base.dev;
10574 struct drm_i915_private *dev_priv = to_i915(dev);
10575 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10576 const enum pipe pipe = intel_crtc->pipe;
10577 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10578
10579 ctl = I915_READ(PLANE_CTL(pipe, 0));
10580 ctl &= ~PLANE_CTL_TILED_MASK;
10581 switch (fb->modifier) {
10582 case DRM_FORMAT_MOD_LINEAR:
10583 break;
10584 case I915_FORMAT_MOD_X_TILED:
10585 ctl |= PLANE_CTL_TILED_X;
10586 break;
10587 case I915_FORMAT_MOD_Y_TILED:
10588 ctl |= PLANE_CTL_TILED_Y;
10589 break;
10590 case I915_FORMAT_MOD_Yf_TILED:
10591 ctl |= PLANE_CTL_TILED_YF;
10592 break;
10593 default:
10594 MISSING_CASE(fb->modifier);
10595 }
10596
10597 /*
10598 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10599 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10600 */
10601 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10602 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10603
10604 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10605 POSTING_READ(PLANE_SURF(pipe, 0));
10606 }
10607
10608 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10609 struct intel_flip_work *work)
10610 {
10611 struct drm_device *dev = intel_crtc->base.dev;
10612 struct drm_i915_private *dev_priv = to_i915(dev);
10613 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10614 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10615 u32 dspcntr;
10616
10617 dspcntr = I915_READ(reg);
10618
10619 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10620 dspcntr |= DISPPLANE_TILED;
10621 else
10622 dspcntr &= ~DISPPLANE_TILED;
10623
10624 I915_WRITE(reg, dspcntr);
10625
10626 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10627 POSTING_READ(DSPSURF(intel_crtc->plane));
10628 }
10629
10630 static void intel_mmio_flip_work_func(struct work_struct *w)
10631 {
10632 struct intel_flip_work *work =
10633 container_of(w, struct intel_flip_work, mmio_work);
10634 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10636 struct intel_framebuffer *intel_fb =
10637 to_intel_framebuffer(crtc->base.primary->fb);
10638 struct drm_i915_gem_object *obj = intel_fb->obj;
10639
10640 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10641
10642 intel_pipe_update_start(crtc);
10643
10644 if (INTEL_GEN(dev_priv) >= 9)
10645 skl_do_mmio_flip(crtc, work->rotation, work);
10646 else
10647 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10648 ilk_do_mmio_flip(crtc, work);
10649
10650 intel_pipe_update_end(crtc, work);
10651 }
10652
10653 static int intel_default_queue_flip(struct drm_device *dev,
10654 struct drm_crtc *crtc,
10655 struct drm_framebuffer *fb,
10656 struct drm_i915_gem_object *obj,
10657 struct drm_i915_gem_request *req,
10658 uint32_t flags)
10659 {
10660 return -ENODEV;
10661 }
10662
10663 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10664 struct intel_crtc *intel_crtc,
10665 struct intel_flip_work *work)
10666 {
10667 u32 addr, vblank;
10668
10669 if (!atomic_read(&work->pending))
10670 return false;
10671
10672 smp_rmb();
10673
10674 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10675 if (work->flip_ready_vblank == 0) {
10676 if (work->flip_queued_req &&
10677 !i915_gem_request_completed(work->flip_queued_req))
10678 return false;
10679
10680 work->flip_ready_vblank = vblank;
10681 }
10682
10683 if (vblank - work->flip_ready_vblank < 3)
10684 return false;
10685
10686 /* Potential stall - if we see that the flip has happened,
10687 * assume a missed interrupt. */
10688 if (INTEL_GEN(dev_priv) >= 4)
10689 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10690 else
10691 addr = I915_READ(DSPADDR(intel_crtc->plane));
10692
10693 /* There is a potential issue here with a false positive after a flip
10694 * to the same address. We could address this by checking for a
10695 * non-incrementing frame counter.
10696 */
10697 return addr == work->gtt_offset;
10698 }
10699
10700 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10701 {
10702 struct drm_device *dev = &dev_priv->drm;
10703 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10704 struct intel_flip_work *work;
10705
10706 WARN_ON(!in_interrupt());
10707
10708 if (crtc == NULL)
10709 return;
10710
10711 spin_lock(&dev->event_lock);
10712 work = crtc->flip_work;
10713
10714 if (work != NULL && !is_mmio_work(work) &&
10715 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10716 WARN_ONCE(1,
10717 "Kicking stuck page flip: queued at %d, now %d\n",
10718 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10719 page_flip_completed(crtc);
10720 work = NULL;
10721 }
10722
10723 if (work != NULL && !is_mmio_work(work) &&
10724 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10725 intel_queue_rps_boost_for_request(work->flip_queued_req);
10726 spin_unlock(&dev->event_lock);
10727 }
10728
10729 __maybe_unused
10730 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10731 struct drm_framebuffer *fb,
10732 struct drm_pending_vblank_event *event,
10733 uint32_t page_flip_flags)
10734 {
10735 struct drm_device *dev = crtc->dev;
10736 struct drm_i915_private *dev_priv = to_i915(dev);
10737 struct drm_framebuffer *old_fb = crtc->primary->fb;
10738 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10740 struct drm_plane *primary = crtc->primary;
10741 enum pipe pipe = intel_crtc->pipe;
10742 struct intel_flip_work *work;
10743 struct intel_engine_cs *engine;
10744 bool mmio_flip;
10745 struct drm_i915_gem_request *request;
10746 struct i915_vma *vma;
10747 int ret;
10748
10749 /*
10750 * drm_mode_page_flip_ioctl() should already catch this, but double
10751 * check to be safe. In the future we may enable pageflipping from
10752 * a disabled primary plane.
10753 */
10754 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10755 return -EBUSY;
10756
10757 /* Can't change pixel format via MI display flips. */
10758 if (fb->format != crtc->primary->fb->format)
10759 return -EINVAL;
10760
10761 /*
10762 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10763 * Note that pitch changes could also affect these register.
10764 */
10765 if (INTEL_GEN(dev_priv) > 3 &&
10766 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10767 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10768 return -EINVAL;
10769
10770 if (i915_terminally_wedged(&dev_priv->gpu_error))
10771 goto out_hang;
10772
10773 work = kzalloc(sizeof(*work), GFP_KERNEL);
10774 if (work == NULL)
10775 return -ENOMEM;
10776
10777 work->event = event;
10778 work->crtc = crtc;
10779 work->old_fb = old_fb;
10780 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10781
10782 ret = drm_crtc_vblank_get(crtc);
10783 if (ret)
10784 goto free_work;
10785
10786 /* We borrow the event spin lock for protecting flip_work */
10787 spin_lock_irq(&dev->event_lock);
10788 if (intel_crtc->flip_work) {
10789 /* Before declaring the flip queue wedged, check if
10790 * the hardware completed the operation behind our backs.
10791 */
10792 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10793 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10794 page_flip_completed(intel_crtc);
10795 } else {
10796 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10797 spin_unlock_irq(&dev->event_lock);
10798
10799 drm_crtc_vblank_put(crtc);
10800 kfree(work);
10801 return -EBUSY;
10802 }
10803 }
10804 intel_crtc->flip_work = work;
10805 spin_unlock_irq(&dev->event_lock);
10806
10807 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10808 flush_workqueue(dev_priv->wq);
10809
10810 /* Reference the objects for the scheduled work. */
10811 drm_framebuffer_reference(work->old_fb);
10812
10813 crtc->primary->fb = fb;
10814 update_state_fb(crtc->primary);
10815
10816 work->pending_flip_obj = i915_gem_object_get(obj);
10817
10818 ret = i915_mutex_lock_interruptible(dev);
10819 if (ret)
10820 goto cleanup;
10821
10822 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10823 if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10824 ret = -EIO;
10825 goto unlock;
10826 }
10827
10828 atomic_inc(&intel_crtc->unpin_work_count);
10829
10830 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10831 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10832
10833 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10834 engine = dev_priv->engine[BCS];
10835 if (fb->modifier != old_fb->modifier)
10836 /* vlv: DISPLAY_FLIP fails to change tiling */
10837 engine = NULL;
10838 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10839 engine = dev_priv->engine[BCS];
10840 } else if (INTEL_GEN(dev_priv) >= 7) {
10841 engine = i915_gem_object_last_write_engine(obj);
10842 if (engine == NULL || engine->id != RCS)
10843 engine = dev_priv->engine[BCS];
10844 } else {
10845 engine = dev_priv->engine[RCS];
10846 }
10847
10848 mmio_flip = use_mmio_flip(engine, obj);
10849
10850 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10851 if (IS_ERR(vma)) {
10852 ret = PTR_ERR(vma);
10853 goto cleanup_pending;
10854 }
10855
10856 work->old_vma = to_intel_plane_state(primary->state)->vma;
10857 to_intel_plane_state(primary->state)->vma = vma;
10858
10859 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10860 work->rotation = crtc->primary->state->rotation;
10861
10862 /*
10863 * There's the potential that the next frame will not be compatible with
10864 * FBC, so we want to call pre_update() before the actual page flip.
10865 * The problem is that pre_update() caches some information about the fb
10866 * object, so we want to do this only after the object is pinned. Let's
10867 * be on the safe side and do this immediately before scheduling the
10868 * flip.
10869 */
10870 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10871 to_intel_plane_state(primary->state));
10872
10873 if (mmio_flip) {
10874 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10875 queue_work(system_unbound_wq, &work->mmio_work);
10876 } else {
10877 request = i915_gem_request_alloc(engine,
10878 dev_priv->kernel_context);
10879 if (IS_ERR(request)) {
10880 ret = PTR_ERR(request);
10881 goto cleanup_unpin;
10882 }
10883
10884 ret = i915_gem_request_await_object(request, obj, false);
10885 if (ret)
10886 goto cleanup_request;
10887
10888 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10889 page_flip_flags);
10890 if (ret)
10891 goto cleanup_request;
10892
10893 intel_mark_page_flip_active(intel_crtc, work);
10894
10895 work->flip_queued_req = i915_gem_request_get(request);
10896 i915_add_request(request);
10897 }
10898
10899 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10900 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10901 to_intel_plane(primary)->frontbuffer_bit);
10902 mutex_unlock(&dev->struct_mutex);
10903
10904 intel_frontbuffer_flip_prepare(to_i915(dev),
10905 to_intel_plane(primary)->frontbuffer_bit);
10906
10907 trace_i915_flip_request(intel_crtc->plane, obj);
10908
10909 return 0;
10910
10911 cleanup_request:
10912 i915_add_request(request);
10913 cleanup_unpin:
10914 to_intel_plane_state(primary->state)->vma = work->old_vma;
10915 intel_unpin_fb_vma(vma);
10916 cleanup_pending:
10917 atomic_dec(&intel_crtc->unpin_work_count);
10918 unlock:
10919 mutex_unlock(&dev->struct_mutex);
10920 cleanup:
10921 crtc->primary->fb = old_fb;
10922 update_state_fb(crtc->primary);
10923
10924 i915_gem_object_put(obj);
10925 drm_framebuffer_unreference(work->old_fb);
10926
10927 spin_lock_irq(&dev->event_lock);
10928 intel_crtc->flip_work = NULL;
10929 spin_unlock_irq(&dev->event_lock);
10930
10931 drm_crtc_vblank_put(crtc);
10932 free_work:
10933 kfree(work);
10934
10935 if (ret == -EIO) {
10936 struct drm_atomic_state *state;
10937 struct drm_plane_state *plane_state;
10938
10939 out_hang:
10940 state = drm_atomic_state_alloc(dev);
10941 if (!state)
10942 return -ENOMEM;
10943 state->acquire_ctx = dev->mode_config.acquire_ctx;
10944
10945 retry:
10946 plane_state = drm_atomic_get_plane_state(state, primary);
10947 ret = PTR_ERR_OR_ZERO(plane_state);
10948 if (!ret) {
10949 drm_atomic_set_fb_for_plane(plane_state, fb);
10950
10951 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10952 if (!ret)
10953 ret = drm_atomic_commit(state);
10954 }
10955
10956 if (ret == -EDEADLK) {
10957 drm_modeset_backoff(state->acquire_ctx);
10958 drm_atomic_state_clear(state);
10959 goto retry;
10960 }
10961
10962 drm_atomic_state_put(state);
10963
10964 if (ret == 0 && event) {
10965 spin_lock_irq(&dev->event_lock);
10966 drm_crtc_send_vblank_event(crtc, event);
10967 spin_unlock_irq(&dev->event_lock);
10968 }
10969 }
10970 return ret;
10971 }
10972
10973
10974 /**
10975 * intel_wm_need_update - Check whether watermarks need updating
10976 * @plane: drm plane
10977 * @state: new plane state
10978 *
10979 * Check current plane state versus the new one to determine whether
10980 * watermarks need to be recalculated.
10981 *
10982 * Returns true or false.
10983 */
10984 static bool intel_wm_need_update(struct drm_plane *plane,
10985 struct drm_plane_state *state)
10986 {
10987 struct intel_plane_state *new = to_intel_plane_state(state);
10988 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10989
10990 /* Update watermarks on tiling or size changes. */
10991 if (new->base.visible != cur->base.visible)
10992 return true;
10993
10994 if (!cur->base.fb || !new->base.fb)
10995 return false;
10996
10997 if (cur->base.fb->modifier != new->base.fb->modifier ||
10998 cur->base.rotation != new->base.rotation ||
10999 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11000 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11001 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11002 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11003 return true;
11004
11005 return false;
11006 }
11007
11008 static bool needs_scaling(struct intel_plane_state *state)
11009 {
11010 int src_w = drm_rect_width(&state->base.src) >> 16;
11011 int src_h = drm_rect_height(&state->base.src) >> 16;
11012 int dst_w = drm_rect_width(&state->base.dst);
11013 int dst_h = drm_rect_height(&state->base.dst);
11014
11015 return (src_w != dst_w || src_h != dst_h);
11016 }
11017
11018 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11019 struct drm_plane_state *plane_state)
11020 {
11021 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11022 struct drm_crtc *crtc = crtc_state->crtc;
11023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11024 struct intel_plane *plane = to_intel_plane(plane_state->plane);
11025 struct drm_device *dev = crtc->dev;
11026 struct drm_i915_private *dev_priv = to_i915(dev);
11027 struct intel_plane_state *old_plane_state =
11028 to_intel_plane_state(plane->base.state);
11029 bool mode_changed = needs_modeset(crtc_state);
11030 bool was_crtc_enabled = crtc->state->active;
11031 bool is_crtc_enabled = crtc_state->active;
11032 bool turn_off, turn_on, visible, was_visible;
11033 struct drm_framebuffer *fb = plane_state->fb;
11034 int ret;
11035
11036 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11037 ret = skl_update_scaler_plane(
11038 to_intel_crtc_state(crtc_state),
11039 to_intel_plane_state(plane_state));
11040 if (ret)
11041 return ret;
11042 }
11043
11044 was_visible = old_plane_state->base.visible;
11045 visible = plane_state->visible;
11046
11047 if (!was_crtc_enabled && WARN_ON(was_visible))
11048 was_visible = false;
11049
11050 /*
11051 * Visibility is calculated as if the crtc was on, but
11052 * after scaler setup everything depends on it being off
11053 * when the crtc isn't active.
11054 *
11055 * FIXME this is wrong for watermarks. Watermarks should also
11056 * be computed as if the pipe would be active. Perhaps move
11057 * per-plane wm computation to the .check_plane() hook, and
11058 * only combine the results from all planes in the current place?
11059 */
11060 if (!is_crtc_enabled) {
11061 plane_state->visible = visible = false;
11062 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11063 }
11064
11065 if (!was_visible && !visible)
11066 return 0;
11067
11068 if (fb != old_plane_state->base.fb)
11069 pipe_config->fb_changed = true;
11070
11071 turn_off = was_visible && (!visible || mode_changed);
11072 turn_on = visible && (!was_visible || mode_changed);
11073
11074 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11075 intel_crtc->base.base.id, intel_crtc->base.name,
11076 plane->base.base.id, plane->base.name,
11077 fb ? fb->base.id : -1);
11078
11079 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11080 plane->base.base.id, plane->base.name,
11081 was_visible, visible,
11082 turn_off, turn_on, mode_changed);
11083
11084 if (turn_on) {
11085 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11086 pipe_config->update_wm_pre = true;
11087
11088 /* must disable cxsr around plane enable/disable */
11089 if (plane->id != PLANE_CURSOR)
11090 pipe_config->disable_cxsr = true;
11091 } else if (turn_off) {
11092 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11093 pipe_config->update_wm_post = true;
11094
11095 /* must disable cxsr around plane enable/disable */
11096 if (plane->id != PLANE_CURSOR)
11097 pipe_config->disable_cxsr = true;
11098 } else if (intel_wm_need_update(&plane->base, plane_state)) {
11099 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11100 /* FIXME bollocks */
11101 pipe_config->update_wm_pre = true;
11102 pipe_config->update_wm_post = true;
11103 }
11104 }
11105
11106 if (visible || was_visible)
11107 pipe_config->fb_bits |= plane->frontbuffer_bit;
11108
11109 /*
11110 * WaCxSRDisabledForSpriteScaling:ivb
11111 *
11112 * cstate->update_wm was already set above, so this flag will
11113 * take effect when we commit and program watermarks.
11114 */
11115 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
11116 needs_scaling(to_intel_plane_state(plane_state)) &&
11117 !needs_scaling(old_plane_state))
11118 pipe_config->disable_lp_wm = true;
11119
11120 return 0;
11121 }
11122
11123 static bool encoders_cloneable(const struct intel_encoder *a,
11124 const struct intel_encoder *b)
11125 {
11126 /* masks could be asymmetric, so check both ways */
11127 return a == b || (a->cloneable & (1 << b->type) &&
11128 b->cloneable & (1 << a->type));
11129 }
11130
11131 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11132 struct intel_crtc *crtc,
11133 struct intel_encoder *encoder)
11134 {
11135 struct intel_encoder *source_encoder;
11136 struct drm_connector *connector;
11137 struct drm_connector_state *connector_state;
11138 int i;
11139
11140 for_each_new_connector_in_state(state, connector, connector_state, i) {
11141 if (connector_state->crtc != &crtc->base)
11142 continue;
11143
11144 source_encoder =
11145 to_intel_encoder(connector_state->best_encoder);
11146 if (!encoders_cloneable(encoder, source_encoder))
11147 return false;
11148 }
11149
11150 return true;
11151 }
11152
11153 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11154 struct drm_crtc_state *crtc_state)
11155 {
11156 struct drm_device *dev = crtc->dev;
11157 struct drm_i915_private *dev_priv = to_i915(dev);
11158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11159 struct intel_crtc_state *pipe_config =
11160 to_intel_crtc_state(crtc_state);
11161 struct drm_atomic_state *state = crtc_state->state;
11162 int ret;
11163 bool mode_changed = needs_modeset(crtc_state);
11164
11165 if (mode_changed && !crtc_state->active)
11166 pipe_config->update_wm_post = true;
11167
11168 if (mode_changed && crtc_state->enable &&
11169 dev_priv->display.crtc_compute_clock &&
11170 !WARN_ON(pipe_config->shared_dpll)) {
11171 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11172 pipe_config);
11173 if (ret)
11174 return ret;
11175 }
11176
11177 if (crtc_state->color_mgmt_changed) {
11178 ret = intel_color_check(crtc, crtc_state);
11179 if (ret)
11180 return ret;
11181
11182 /*
11183 * Changing color management on Intel hardware is
11184 * handled as part of planes update.
11185 */
11186 crtc_state->planes_changed = true;
11187 }
11188
11189 ret = 0;
11190 if (dev_priv->display.compute_pipe_wm) {
11191 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11192 if (ret) {
11193 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11194 return ret;
11195 }
11196 }
11197
11198 if (dev_priv->display.compute_intermediate_wm &&
11199 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11200 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11201 return 0;
11202
11203 /*
11204 * Calculate 'intermediate' watermarks that satisfy both the
11205 * old state and the new state. We can program these
11206 * immediately.
11207 */
11208 ret = dev_priv->display.compute_intermediate_wm(dev,
11209 intel_crtc,
11210 pipe_config);
11211 if (ret) {
11212 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11213 return ret;
11214 }
11215 } else if (dev_priv->display.compute_intermediate_wm) {
11216 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11217 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11218 }
11219
11220 if (INTEL_GEN(dev_priv) >= 9) {
11221 if (mode_changed)
11222 ret = skl_update_scaler_crtc(pipe_config);
11223
11224 if (!ret)
11225 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11226 pipe_config);
11227 if (!ret)
11228 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11229 pipe_config);
11230 }
11231
11232 return ret;
11233 }
11234
11235 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11236 .atomic_begin = intel_begin_crtc_commit,
11237 .atomic_flush = intel_finish_crtc_commit,
11238 .atomic_check = intel_crtc_atomic_check,
11239 };
11240
11241 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11242 {
11243 struct intel_connector *connector;
11244 struct drm_connector_list_iter conn_iter;
11245
11246 drm_connector_list_iter_begin(dev, &conn_iter);
11247 for_each_intel_connector_iter(connector, &conn_iter) {
11248 if (connector->base.state->crtc)
11249 drm_connector_unreference(&connector->base);
11250
11251 if (connector->base.encoder) {
11252 connector->base.state->best_encoder =
11253 connector->base.encoder;
11254 connector->base.state->crtc =
11255 connector->base.encoder->crtc;
11256
11257 drm_connector_reference(&connector->base);
11258 } else {
11259 connector->base.state->best_encoder = NULL;
11260 connector->base.state->crtc = NULL;
11261 }
11262 }
11263 drm_connector_list_iter_end(&conn_iter);
11264 }
11265
11266 static void
11267 connected_sink_compute_bpp(struct intel_connector *connector,
11268 struct intel_crtc_state *pipe_config)
11269 {
11270 const struct drm_display_info *info = &connector->base.display_info;
11271 int bpp = pipe_config->pipe_bpp;
11272
11273 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11274 connector->base.base.id,
11275 connector->base.name);
11276
11277 /* Don't use an invalid EDID bpc value */
11278 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11279 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11280 bpp, info->bpc * 3);
11281 pipe_config->pipe_bpp = info->bpc * 3;
11282 }
11283
11284 /* Clamp bpp to 8 on screens without EDID 1.4 */
11285 if (info->bpc == 0 && bpp > 24) {
11286 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11287 bpp);
11288 pipe_config->pipe_bpp = 24;
11289 }
11290 }
11291
11292 static int
11293 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11294 struct intel_crtc_state *pipe_config)
11295 {
11296 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11297 struct drm_atomic_state *state;
11298 struct drm_connector *connector;
11299 struct drm_connector_state *connector_state;
11300 int bpp, i;
11301
11302 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11303 IS_CHERRYVIEW(dev_priv)))
11304 bpp = 10*3;
11305 else if (INTEL_GEN(dev_priv) >= 5)
11306 bpp = 12*3;
11307 else
11308 bpp = 8*3;
11309
11310
11311 pipe_config->pipe_bpp = bpp;
11312
11313 state = pipe_config->base.state;
11314
11315 /* Clamp display bpp to EDID value */
11316 for_each_new_connector_in_state(state, connector, connector_state, i) {
11317 if (connector_state->crtc != &crtc->base)
11318 continue;
11319
11320 connected_sink_compute_bpp(to_intel_connector(connector),
11321 pipe_config);
11322 }
11323
11324 return bpp;
11325 }
11326
11327 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11328 {
11329 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11330 "type: 0x%x flags: 0x%x\n",
11331 mode->crtc_clock,
11332 mode->crtc_hdisplay, mode->crtc_hsync_start,
11333 mode->crtc_hsync_end, mode->crtc_htotal,
11334 mode->crtc_vdisplay, mode->crtc_vsync_start,
11335 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11336 }
11337
11338 static inline void
11339 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11340 unsigned int lane_count, struct intel_link_m_n *m_n)
11341 {
11342 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11343 id, lane_count,
11344 m_n->gmch_m, m_n->gmch_n,
11345 m_n->link_m, m_n->link_n, m_n->tu);
11346 }
11347
11348 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11349 struct intel_crtc_state *pipe_config,
11350 const char *context)
11351 {
11352 struct drm_device *dev = crtc->base.dev;
11353 struct drm_i915_private *dev_priv = to_i915(dev);
11354 struct drm_plane *plane;
11355 struct intel_plane *intel_plane;
11356 struct intel_plane_state *state;
11357 struct drm_framebuffer *fb;
11358
11359 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11360 crtc->base.base.id, crtc->base.name, context);
11361
11362 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11363 transcoder_name(pipe_config->cpu_transcoder),
11364 pipe_config->pipe_bpp, pipe_config->dither);
11365
11366 if (pipe_config->has_pch_encoder)
11367 intel_dump_m_n_config(pipe_config, "fdi",
11368 pipe_config->fdi_lanes,
11369 &pipe_config->fdi_m_n);
11370
11371 if (intel_crtc_has_dp_encoder(pipe_config)) {
11372 intel_dump_m_n_config(pipe_config, "dp m_n",
11373 pipe_config->lane_count, &pipe_config->dp_m_n);
11374 if (pipe_config->has_drrs)
11375 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11376 pipe_config->lane_count,
11377 &pipe_config->dp_m2_n2);
11378 }
11379
11380 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11381 pipe_config->has_audio, pipe_config->has_infoframe);
11382
11383 DRM_DEBUG_KMS("requested mode:\n");
11384 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11385 DRM_DEBUG_KMS("adjusted mode:\n");
11386 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11387 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11388 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11389 pipe_config->port_clock,
11390 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11391 pipe_config->pixel_rate);
11392
11393 if (INTEL_GEN(dev_priv) >= 9)
11394 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11395 crtc->num_scalers,
11396 pipe_config->scaler_state.scaler_users,
11397 pipe_config->scaler_state.scaler_id);
11398
11399 if (HAS_GMCH_DISPLAY(dev_priv))
11400 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11401 pipe_config->gmch_pfit.control,
11402 pipe_config->gmch_pfit.pgm_ratios,
11403 pipe_config->gmch_pfit.lvds_border_bits);
11404 else
11405 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11406 pipe_config->pch_pfit.pos,
11407 pipe_config->pch_pfit.size,
11408 enableddisabled(pipe_config->pch_pfit.enabled));
11409
11410 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11411 pipe_config->ips_enabled, pipe_config->double_wide);
11412
11413 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11414
11415 DRM_DEBUG_KMS("planes on this crtc\n");
11416 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11417 struct drm_format_name_buf format_name;
11418 intel_plane = to_intel_plane(plane);
11419 if (intel_plane->pipe != crtc->pipe)
11420 continue;
11421
11422 state = to_intel_plane_state(plane->state);
11423 fb = state->base.fb;
11424 if (!fb) {
11425 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11426 plane->base.id, plane->name, state->scaler_id);
11427 continue;
11428 }
11429
11430 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11431 plane->base.id, plane->name,
11432 fb->base.id, fb->width, fb->height,
11433 drm_get_format_name(fb->format->format, &format_name));
11434 if (INTEL_GEN(dev_priv) >= 9)
11435 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11436 state->scaler_id,
11437 state->base.src.x1 >> 16,
11438 state->base.src.y1 >> 16,
11439 drm_rect_width(&state->base.src) >> 16,
11440 drm_rect_height(&state->base.src) >> 16,
11441 state->base.dst.x1, state->base.dst.y1,
11442 drm_rect_width(&state->base.dst),
11443 drm_rect_height(&state->base.dst));
11444 }
11445 }
11446
11447 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11448 {
11449 struct drm_device *dev = state->dev;
11450 struct drm_connector *connector;
11451 unsigned int used_ports = 0;
11452 unsigned int used_mst_ports = 0;
11453
11454 /*
11455 * Walk the connector list instead of the encoder
11456 * list to detect the problem on ddi platforms
11457 * where there's just one encoder per digital port.
11458 */
11459 drm_for_each_connector(connector, dev) {
11460 struct drm_connector_state *connector_state;
11461 struct intel_encoder *encoder;
11462
11463 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11464 if (!connector_state)
11465 connector_state = connector->state;
11466
11467 if (!connector_state->best_encoder)
11468 continue;
11469
11470 encoder = to_intel_encoder(connector_state->best_encoder);
11471
11472 WARN_ON(!connector_state->crtc);
11473
11474 switch (encoder->type) {
11475 unsigned int port_mask;
11476 case INTEL_OUTPUT_UNKNOWN:
11477 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11478 break;
11479 case INTEL_OUTPUT_DP:
11480 case INTEL_OUTPUT_HDMI:
11481 case INTEL_OUTPUT_EDP:
11482 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11483
11484 /* the same port mustn't appear more than once */
11485 if (used_ports & port_mask)
11486 return false;
11487
11488 used_ports |= port_mask;
11489 break;
11490 case INTEL_OUTPUT_DP_MST:
11491 used_mst_ports |=
11492 1 << enc_to_mst(&encoder->base)->primary->port;
11493 break;
11494 default:
11495 break;
11496 }
11497 }
11498
11499 /* can't mix MST and SST/HDMI on the same port */
11500 if (used_ports & used_mst_ports)
11501 return false;
11502
11503 return true;
11504 }
11505
11506 static void
11507 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11508 {
11509 struct drm_i915_private *dev_priv =
11510 to_i915(crtc_state->base.crtc->dev);
11511 struct intel_crtc_scaler_state scaler_state;
11512 struct intel_dpll_hw_state dpll_hw_state;
11513 struct intel_shared_dpll *shared_dpll;
11514 struct intel_crtc_wm_state wm_state;
11515 bool force_thru;
11516
11517 /* FIXME: before the switch to atomic started, a new pipe_config was
11518 * kzalloc'd. Code that depends on any field being zero should be
11519 * fixed, so that the crtc_state can be safely duplicated. For now,
11520 * only fields that are know to not cause problems are preserved. */
11521
11522 scaler_state = crtc_state->scaler_state;
11523 shared_dpll = crtc_state->shared_dpll;
11524 dpll_hw_state = crtc_state->dpll_hw_state;
11525 force_thru = crtc_state->pch_pfit.force_thru;
11526 if (IS_G4X(dev_priv) ||
11527 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11528 wm_state = crtc_state->wm;
11529
11530 /* Keep base drm_crtc_state intact, only clear our extended struct */
11531 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11532 memset(&crtc_state->base + 1, 0,
11533 sizeof(*crtc_state) - sizeof(crtc_state->base));
11534
11535 crtc_state->scaler_state = scaler_state;
11536 crtc_state->shared_dpll = shared_dpll;
11537 crtc_state->dpll_hw_state = dpll_hw_state;
11538 crtc_state->pch_pfit.force_thru = force_thru;
11539 if (IS_G4X(dev_priv) ||
11540 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11541 crtc_state->wm = wm_state;
11542 }
11543
11544 static int
11545 intel_modeset_pipe_config(struct drm_crtc *crtc,
11546 struct intel_crtc_state *pipe_config)
11547 {
11548 struct drm_atomic_state *state = pipe_config->base.state;
11549 struct intel_encoder *encoder;
11550 struct drm_connector *connector;
11551 struct drm_connector_state *connector_state;
11552 int base_bpp, ret = -EINVAL;
11553 int i;
11554 bool retry = true;
11555
11556 clear_intel_crtc_state(pipe_config);
11557
11558 pipe_config->cpu_transcoder =
11559 (enum transcoder) to_intel_crtc(crtc)->pipe;
11560
11561 /*
11562 * Sanitize sync polarity flags based on requested ones. If neither
11563 * positive or negative polarity is requested, treat this as meaning
11564 * negative polarity.
11565 */
11566 if (!(pipe_config->base.adjusted_mode.flags &
11567 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11568 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11569
11570 if (!(pipe_config->base.adjusted_mode.flags &
11571 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11572 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11573
11574 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11575 pipe_config);
11576 if (base_bpp < 0)
11577 goto fail;
11578
11579 /*
11580 * Determine the real pipe dimensions. Note that stereo modes can
11581 * increase the actual pipe size due to the frame doubling and
11582 * insertion of additional space for blanks between the frame. This
11583 * is stored in the crtc timings. We use the requested mode to do this
11584 * computation to clearly distinguish it from the adjusted mode, which
11585 * can be changed by the connectors in the below retry loop.
11586 */
11587 drm_mode_get_hv_timing(&pipe_config->base.mode,
11588 &pipe_config->pipe_src_w,
11589 &pipe_config->pipe_src_h);
11590
11591 for_each_new_connector_in_state(state, connector, connector_state, i) {
11592 if (connector_state->crtc != crtc)
11593 continue;
11594
11595 encoder = to_intel_encoder(connector_state->best_encoder);
11596
11597 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11598 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11599 goto fail;
11600 }
11601
11602 /*
11603 * Determine output_types before calling the .compute_config()
11604 * hooks so that the hooks can use this information safely.
11605 */
11606 pipe_config->output_types |= 1 << encoder->type;
11607 }
11608
11609 encoder_retry:
11610 /* Ensure the port clock defaults are reset when retrying. */
11611 pipe_config->port_clock = 0;
11612 pipe_config->pixel_multiplier = 1;
11613
11614 /* Fill in default crtc timings, allow encoders to overwrite them. */
11615 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11616 CRTC_STEREO_DOUBLE);
11617
11618 /* Pass our mode to the connectors and the CRTC to give them a chance to
11619 * adjust it according to limitations or connector properties, and also
11620 * a chance to reject the mode entirely.
11621 */
11622 for_each_new_connector_in_state(state, connector, connector_state, i) {
11623 if (connector_state->crtc != crtc)
11624 continue;
11625
11626 encoder = to_intel_encoder(connector_state->best_encoder);
11627
11628 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11629 DRM_DEBUG_KMS("Encoder config failure\n");
11630 goto fail;
11631 }
11632 }
11633
11634 /* Set default port clock if not overwritten by the encoder. Needs to be
11635 * done afterwards in case the encoder adjusts the mode. */
11636 if (!pipe_config->port_clock)
11637 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11638 * pipe_config->pixel_multiplier;
11639
11640 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11641 if (ret < 0) {
11642 DRM_DEBUG_KMS("CRTC fixup failed\n");
11643 goto fail;
11644 }
11645
11646 if (ret == RETRY) {
11647 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11648 ret = -EINVAL;
11649 goto fail;
11650 }
11651
11652 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11653 retry = false;
11654 goto encoder_retry;
11655 }
11656
11657 /* Dithering seems to not pass-through bits correctly when it should, so
11658 * only enable it on 6bpc panels and when its not a compliance
11659 * test requesting 6bpc video pattern.
11660 */
11661 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11662 !pipe_config->dither_force_disable;
11663 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11664 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11665
11666 fail:
11667 return ret;
11668 }
11669
11670 static void
11671 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11672 {
11673 struct drm_crtc *crtc;
11674 struct drm_crtc_state *new_crtc_state;
11675 int i;
11676
11677 /* Double check state. */
11678 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11679 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11680
11681 /*
11682 * Update legacy state to satisfy fbc code. This can
11683 * be removed when fbc uses the atomic state.
11684 */
11685 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11686 struct drm_plane_state *plane_state = crtc->primary->state;
11687
11688 crtc->primary->fb = plane_state->fb;
11689 crtc->x = plane_state->src_x >> 16;
11690 crtc->y = plane_state->src_y >> 16;
11691 }
11692 }
11693 }
11694
11695 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11696 {
11697 int diff;
11698
11699 if (clock1 == clock2)
11700 return true;
11701
11702 if (!clock1 || !clock2)
11703 return false;
11704
11705 diff = abs(clock1 - clock2);
11706
11707 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11708 return true;
11709
11710 return false;
11711 }
11712
11713 static bool
11714 intel_compare_m_n(unsigned int m, unsigned int n,
11715 unsigned int m2, unsigned int n2,
11716 bool exact)
11717 {
11718 if (m == m2 && n == n2)
11719 return true;
11720
11721 if (exact || !m || !n || !m2 || !n2)
11722 return false;
11723
11724 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11725
11726 if (n > n2) {
11727 while (n > n2) {
11728 m2 <<= 1;
11729 n2 <<= 1;
11730 }
11731 } else if (n < n2) {
11732 while (n < n2) {
11733 m <<= 1;
11734 n <<= 1;
11735 }
11736 }
11737
11738 if (n != n2)
11739 return false;
11740
11741 return intel_fuzzy_clock_check(m, m2);
11742 }
11743
11744 static bool
11745 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11746 struct intel_link_m_n *m2_n2,
11747 bool adjust)
11748 {
11749 if (m_n->tu == m2_n2->tu &&
11750 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11751 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11752 intel_compare_m_n(m_n->link_m, m_n->link_n,
11753 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11754 if (adjust)
11755 *m2_n2 = *m_n;
11756
11757 return true;
11758 }
11759
11760 return false;
11761 }
11762
11763 static void __printf(3, 4)
11764 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11765 {
11766 char *level;
11767 unsigned int category;
11768 struct va_format vaf;
11769 va_list args;
11770
11771 if (adjust) {
11772 level = KERN_DEBUG;
11773 category = DRM_UT_KMS;
11774 } else {
11775 level = KERN_ERR;
11776 category = DRM_UT_NONE;
11777 }
11778
11779 va_start(args, format);
11780 vaf.fmt = format;
11781 vaf.va = &args;
11782
11783 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11784
11785 va_end(args);
11786 }
11787
11788 static bool
11789 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11790 struct intel_crtc_state *current_config,
11791 struct intel_crtc_state *pipe_config,
11792 bool adjust)
11793 {
11794 bool ret = true;
11795
11796 #define PIPE_CONF_CHECK_X(name) \
11797 if (current_config->name != pipe_config->name) { \
11798 pipe_config_err(adjust, __stringify(name), \
11799 "(expected 0x%08x, found 0x%08x)\n", \
11800 current_config->name, \
11801 pipe_config->name); \
11802 ret = false; \
11803 }
11804
11805 #define PIPE_CONF_CHECK_I(name) \
11806 if (current_config->name != pipe_config->name) { \
11807 pipe_config_err(adjust, __stringify(name), \
11808 "(expected %i, found %i)\n", \
11809 current_config->name, \
11810 pipe_config->name); \
11811 ret = false; \
11812 }
11813
11814 #define PIPE_CONF_CHECK_P(name) \
11815 if (current_config->name != pipe_config->name) { \
11816 pipe_config_err(adjust, __stringify(name), \
11817 "(expected %p, found %p)\n", \
11818 current_config->name, \
11819 pipe_config->name); \
11820 ret = false; \
11821 }
11822
11823 #define PIPE_CONF_CHECK_M_N(name) \
11824 if (!intel_compare_link_m_n(&current_config->name, \
11825 &pipe_config->name,\
11826 adjust)) { \
11827 pipe_config_err(adjust, __stringify(name), \
11828 "(expected tu %i gmch %i/%i link %i/%i, " \
11829 "found tu %i, gmch %i/%i link %i/%i)\n", \
11830 current_config->name.tu, \
11831 current_config->name.gmch_m, \
11832 current_config->name.gmch_n, \
11833 current_config->name.link_m, \
11834 current_config->name.link_n, \
11835 pipe_config->name.tu, \
11836 pipe_config->name.gmch_m, \
11837 pipe_config->name.gmch_n, \
11838 pipe_config->name.link_m, \
11839 pipe_config->name.link_n); \
11840 ret = false; \
11841 }
11842
11843 /* This is required for BDW+ where there is only one set of registers for
11844 * switching between high and low RR.
11845 * This macro can be used whenever a comparison has to be made between one
11846 * hw state and multiple sw state variables.
11847 */
11848 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11849 if (!intel_compare_link_m_n(&current_config->name, \
11850 &pipe_config->name, adjust) && \
11851 !intel_compare_link_m_n(&current_config->alt_name, \
11852 &pipe_config->name, adjust)) { \
11853 pipe_config_err(adjust, __stringify(name), \
11854 "(expected tu %i gmch %i/%i link %i/%i, " \
11855 "or tu %i gmch %i/%i link %i/%i, " \
11856 "found tu %i, gmch %i/%i link %i/%i)\n", \
11857 current_config->name.tu, \
11858 current_config->name.gmch_m, \
11859 current_config->name.gmch_n, \
11860 current_config->name.link_m, \
11861 current_config->name.link_n, \
11862 current_config->alt_name.tu, \
11863 current_config->alt_name.gmch_m, \
11864 current_config->alt_name.gmch_n, \
11865 current_config->alt_name.link_m, \
11866 current_config->alt_name.link_n, \
11867 pipe_config->name.tu, \
11868 pipe_config->name.gmch_m, \
11869 pipe_config->name.gmch_n, \
11870 pipe_config->name.link_m, \
11871 pipe_config->name.link_n); \
11872 ret = false; \
11873 }
11874
11875 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11876 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11877 pipe_config_err(adjust, __stringify(name), \
11878 "(%x) (expected %i, found %i)\n", \
11879 (mask), \
11880 current_config->name & (mask), \
11881 pipe_config->name & (mask)); \
11882 ret = false; \
11883 }
11884
11885 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11886 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11887 pipe_config_err(adjust, __stringify(name), \
11888 "(expected %i, found %i)\n", \
11889 current_config->name, \
11890 pipe_config->name); \
11891 ret = false; \
11892 }
11893
11894 #define PIPE_CONF_QUIRK(quirk) \
11895 ((current_config->quirks | pipe_config->quirks) & (quirk))
11896
11897 PIPE_CONF_CHECK_I(cpu_transcoder);
11898
11899 PIPE_CONF_CHECK_I(has_pch_encoder);
11900 PIPE_CONF_CHECK_I(fdi_lanes);
11901 PIPE_CONF_CHECK_M_N(fdi_m_n);
11902
11903 PIPE_CONF_CHECK_I(lane_count);
11904 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11905
11906 if (INTEL_GEN(dev_priv) < 8) {
11907 PIPE_CONF_CHECK_M_N(dp_m_n);
11908
11909 if (current_config->has_drrs)
11910 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11911 } else
11912 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11913
11914 PIPE_CONF_CHECK_X(output_types);
11915
11916 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11917 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11918 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11919 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11920 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11921 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11922
11923 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11924 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11925 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11926 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11927 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11928 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11929
11930 PIPE_CONF_CHECK_I(pixel_multiplier);
11931 PIPE_CONF_CHECK_I(has_hdmi_sink);
11932 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11933 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11934 PIPE_CONF_CHECK_I(limited_color_range);
11935
11936 PIPE_CONF_CHECK_I(hdmi_scrambling);
11937 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11938 PIPE_CONF_CHECK_I(has_infoframe);
11939
11940 PIPE_CONF_CHECK_I(has_audio);
11941
11942 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11943 DRM_MODE_FLAG_INTERLACE);
11944
11945 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11946 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11947 DRM_MODE_FLAG_PHSYNC);
11948 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11949 DRM_MODE_FLAG_NHSYNC);
11950 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11951 DRM_MODE_FLAG_PVSYNC);
11952 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11953 DRM_MODE_FLAG_NVSYNC);
11954 }
11955
11956 PIPE_CONF_CHECK_X(gmch_pfit.control);
11957 /* pfit ratios are autocomputed by the hw on gen4+ */
11958 if (INTEL_GEN(dev_priv) < 4)
11959 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11960 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11961
11962 if (!adjust) {
11963 PIPE_CONF_CHECK_I(pipe_src_w);
11964 PIPE_CONF_CHECK_I(pipe_src_h);
11965
11966 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11967 if (current_config->pch_pfit.enabled) {
11968 PIPE_CONF_CHECK_X(pch_pfit.pos);
11969 PIPE_CONF_CHECK_X(pch_pfit.size);
11970 }
11971
11972 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11973 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11974 }
11975
11976 /* BDW+ don't expose a synchronous way to read the state */
11977 if (IS_HASWELL(dev_priv))
11978 PIPE_CONF_CHECK_I(ips_enabled);
11979
11980 PIPE_CONF_CHECK_I(double_wide);
11981
11982 PIPE_CONF_CHECK_P(shared_dpll);
11983 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11984 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11985 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11986 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11987 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11988 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11989 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11990 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11991 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11992
11993 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11994 PIPE_CONF_CHECK_X(dsi_pll.div);
11995
11996 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11997 PIPE_CONF_CHECK_I(pipe_bpp);
11998
11999 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12000 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12001
12002 #undef PIPE_CONF_CHECK_X
12003 #undef PIPE_CONF_CHECK_I
12004 #undef PIPE_CONF_CHECK_P
12005 #undef PIPE_CONF_CHECK_FLAGS
12006 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12007 #undef PIPE_CONF_QUIRK
12008
12009 return ret;
12010 }
12011
12012 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12013 const struct intel_crtc_state *pipe_config)
12014 {
12015 if (pipe_config->has_pch_encoder) {
12016 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12017 &pipe_config->fdi_m_n);
12018 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12019
12020 /*
12021 * FDI already provided one idea for the dotclock.
12022 * Yell if the encoder disagrees.
12023 */
12024 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12025 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12026 fdi_dotclock, dotclock);
12027 }
12028 }
12029
12030 static void verify_wm_state(struct drm_crtc *crtc,
12031 struct drm_crtc_state *new_state)
12032 {
12033 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12034 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12035 struct skl_pipe_wm hw_wm, *sw_wm;
12036 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12037 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12039 const enum pipe pipe = intel_crtc->pipe;
12040 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12041
12042 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12043 return;
12044
12045 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
12046 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12047
12048 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12049 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12050
12051 /* planes */
12052 for_each_universal_plane(dev_priv, pipe, plane) {
12053 hw_plane_wm = &hw_wm.planes[plane];
12054 sw_plane_wm = &sw_wm->planes[plane];
12055
12056 /* Watermarks */
12057 for (level = 0; level <= max_level; level++) {
12058 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12059 &sw_plane_wm->wm[level]))
12060 continue;
12061
12062 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12063 pipe_name(pipe), plane + 1, level,
12064 sw_plane_wm->wm[level].plane_en,
12065 sw_plane_wm->wm[level].plane_res_b,
12066 sw_plane_wm->wm[level].plane_res_l,
12067 hw_plane_wm->wm[level].plane_en,
12068 hw_plane_wm->wm[level].plane_res_b,
12069 hw_plane_wm->wm[level].plane_res_l);
12070 }
12071
12072 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12073 &sw_plane_wm->trans_wm)) {
12074 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12075 pipe_name(pipe), plane + 1,
12076 sw_plane_wm->trans_wm.plane_en,
12077 sw_plane_wm->trans_wm.plane_res_b,
12078 sw_plane_wm->trans_wm.plane_res_l,
12079 hw_plane_wm->trans_wm.plane_en,
12080 hw_plane_wm->trans_wm.plane_res_b,
12081 hw_plane_wm->trans_wm.plane_res_l);
12082 }
12083
12084 /* DDB */
12085 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
12086 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
12087
12088 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12089 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12090 pipe_name(pipe), plane + 1,
12091 sw_ddb_entry->start, sw_ddb_entry->end,
12092 hw_ddb_entry->start, hw_ddb_entry->end);
12093 }
12094 }
12095
12096 /*
12097 * cursor
12098 * If the cursor plane isn't active, we may not have updated it's ddb
12099 * allocation. In that case since the ddb allocation will be updated
12100 * once the plane becomes visible, we can skip this check
12101 */
12102 if (1) {
12103 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
12104 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12105
12106 /* Watermarks */
12107 for (level = 0; level <= max_level; level++) {
12108 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12109 &sw_plane_wm->wm[level]))
12110 continue;
12111
12112 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12113 pipe_name(pipe), level,
12114 sw_plane_wm->wm[level].plane_en,
12115 sw_plane_wm->wm[level].plane_res_b,
12116 sw_plane_wm->wm[level].plane_res_l,
12117 hw_plane_wm->wm[level].plane_en,
12118 hw_plane_wm->wm[level].plane_res_b,
12119 hw_plane_wm->wm[level].plane_res_l);
12120 }
12121
12122 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12123 &sw_plane_wm->trans_wm)) {
12124 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12125 pipe_name(pipe),
12126 sw_plane_wm->trans_wm.plane_en,
12127 sw_plane_wm->trans_wm.plane_res_b,
12128 sw_plane_wm->trans_wm.plane_res_l,
12129 hw_plane_wm->trans_wm.plane_en,
12130 hw_plane_wm->trans_wm.plane_res_b,
12131 hw_plane_wm->trans_wm.plane_res_l);
12132 }
12133
12134 /* DDB */
12135 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12136 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12137
12138 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12139 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12140 pipe_name(pipe),
12141 sw_ddb_entry->start, sw_ddb_entry->end,
12142 hw_ddb_entry->start, hw_ddb_entry->end);
12143 }
12144 }
12145 }
12146
12147 static void
12148 verify_connector_state(struct drm_device *dev,
12149 struct drm_atomic_state *state,
12150 struct drm_crtc *crtc)
12151 {
12152 struct drm_connector *connector;
12153 struct drm_connector_state *new_conn_state;
12154 int i;
12155
12156 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12157 struct drm_encoder *encoder = connector->encoder;
12158 struct drm_crtc_state *crtc_state = NULL;
12159
12160 if (new_conn_state->crtc != crtc)
12161 continue;
12162
12163 if (crtc)
12164 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12165
12166 intel_connector_verify_state(crtc_state, new_conn_state);
12167
12168 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12169 "connector's atomic encoder doesn't match legacy encoder\n");
12170 }
12171 }
12172
12173 static void
12174 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12175 {
12176 struct intel_encoder *encoder;
12177 struct drm_connector *connector;
12178 struct drm_connector_state *old_conn_state, *new_conn_state;
12179 int i;
12180
12181 for_each_intel_encoder(dev, encoder) {
12182 bool enabled = false, found = false;
12183 enum pipe pipe;
12184
12185 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12186 encoder->base.base.id,
12187 encoder->base.name);
12188
12189 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12190 new_conn_state, i) {
12191 if (old_conn_state->best_encoder == &encoder->base)
12192 found = true;
12193
12194 if (new_conn_state->best_encoder != &encoder->base)
12195 continue;
12196 found = enabled = true;
12197
12198 I915_STATE_WARN(new_conn_state->crtc !=
12199 encoder->base.crtc,
12200 "connector's crtc doesn't match encoder crtc\n");
12201 }
12202
12203 if (!found)
12204 continue;
12205
12206 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12207 "encoder's enabled state mismatch "
12208 "(expected %i, found %i)\n",
12209 !!encoder->base.crtc, enabled);
12210
12211 if (!encoder->base.crtc) {
12212 bool active;
12213
12214 active = encoder->get_hw_state(encoder, &pipe);
12215 I915_STATE_WARN(active,
12216 "encoder detached but still enabled on pipe %c.\n",
12217 pipe_name(pipe));
12218 }
12219 }
12220 }
12221
12222 static void
12223 verify_crtc_state(struct drm_crtc *crtc,
12224 struct drm_crtc_state *old_crtc_state,
12225 struct drm_crtc_state *new_crtc_state)
12226 {
12227 struct drm_device *dev = crtc->dev;
12228 struct drm_i915_private *dev_priv = to_i915(dev);
12229 struct intel_encoder *encoder;
12230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12231 struct intel_crtc_state *pipe_config, *sw_config;
12232 struct drm_atomic_state *old_state;
12233 bool active;
12234
12235 old_state = old_crtc_state->state;
12236 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12237 pipe_config = to_intel_crtc_state(old_crtc_state);
12238 memset(pipe_config, 0, sizeof(*pipe_config));
12239 pipe_config->base.crtc = crtc;
12240 pipe_config->base.state = old_state;
12241
12242 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12243
12244 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12245
12246 /* we keep both pipes enabled on 830 */
12247 if (IS_I830(dev_priv))
12248 active = new_crtc_state->active;
12249
12250 I915_STATE_WARN(new_crtc_state->active != active,
12251 "crtc active state doesn't match with hw state "
12252 "(expected %i, found %i)\n", new_crtc_state->active, active);
12253
12254 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12255 "transitional active state does not match atomic hw state "
12256 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12257
12258 for_each_encoder_on_crtc(dev, crtc, encoder) {
12259 enum pipe pipe;
12260
12261 active = encoder->get_hw_state(encoder, &pipe);
12262 I915_STATE_WARN(active != new_crtc_state->active,
12263 "[ENCODER:%i] active %i with crtc active %i\n",
12264 encoder->base.base.id, active, new_crtc_state->active);
12265
12266 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12267 "Encoder connected to wrong pipe %c\n",
12268 pipe_name(pipe));
12269
12270 if (active) {
12271 pipe_config->output_types |= 1 << encoder->type;
12272 encoder->get_config(encoder, pipe_config);
12273 }
12274 }
12275
12276 intel_crtc_compute_pixel_rate(pipe_config);
12277
12278 if (!new_crtc_state->active)
12279 return;
12280
12281 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12282
12283 sw_config = to_intel_crtc_state(new_crtc_state);
12284 if (!intel_pipe_config_compare(dev_priv, sw_config,
12285 pipe_config, false)) {
12286 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12287 intel_dump_pipe_config(intel_crtc, pipe_config,
12288 "[hw state]");
12289 intel_dump_pipe_config(intel_crtc, sw_config,
12290 "[sw state]");
12291 }
12292 }
12293
12294 static void
12295 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12296 struct intel_shared_dpll *pll,
12297 struct drm_crtc *crtc,
12298 struct drm_crtc_state *new_state)
12299 {
12300 struct intel_dpll_hw_state dpll_hw_state;
12301 unsigned crtc_mask;
12302 bool active;
12303
12304 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12305
12306 DRM_DEBUG_KMS("%s\n", pll->name);
12307
12308 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12309
12310 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12311 I915_STATE_WARN(!pll->on && pll->active_mask,
12312 "pll in active use but not on in sw tracking\n");
12313 I915_STATE_WARN(pll->on && !pll->active_mask,
12314 "pll is on but not used by any active crtc\n");
12315 I915_STATE_WARN(pll->on != active,
12316 "pll on state mismatch (expected %i, found %i)\n",
12317 pll->on, active);
12318 }
12319
12320 if (!crtc) {
12321 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12322 "more active pll users than references: %x vs %x\n",
12323 pll->active_mask, pll->state.crtc_mask);
12324
12325 return;
12326 }
12327
12328 crtc_mask = 1 << drm_crtc_index(crtc);
12329
12330 if (new_state->active)
12331 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12332 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12333 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12334 else
12335 I915_STATE_WARN(pll->active_mask & crtc_mask,
12336 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12337 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12338
12339 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12340 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12341 crtc_mask, pll->state.crtc_mask);
12342
12343 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12344 &dpll_hw_state,
12345 sizeof(dpll_hw_state)),
12346 "pll hw state mismatch\n");
12347 }
12348
12349 static void
12350 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12351 struct drm_crtc_state *old_crtc_state,
12352 struct drm_crtc_state *new_crtc_state)
12353 {
12354 struct drm_i915_private *dev_priv = to_i915(dev);
12355 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12356 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12357
12358 if (new_state->shared_dpll)
12359 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12360
12361 if (old_state->shared_dpll &&
12362 old_state->shared_dpll != new_state->shared_dpll) {
12363 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12364 struct intel_shared_dpll *pll = old_state->shared_dpll;
12365
12366 I915_STATE_WARN(pll->active_mask & crtc_mask,
12367 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12368 pipe_name(drm_crtc_index(crtc)));
12369 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12370 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12371 pipe_name(drm_crtc_index(crtc)));
12372 }
12373 }
12374
12375 static void
12376 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12377 struct drm_atomic_state *state,
12378 struct drm_crtc_state *old_state,
12379 struct drm_crtc_state *new_state)
12380 {
12381 if (!needs_modeset(new_state) &&
12382 !to_intel_crtc_state(new_state)->update_pipe)
12383 return;
12384
12385 verify_wm_state(crtc, new_state);
12386 verify_connector_state(crtc->dev, state, crtc);
12387 verify_crtc_state(crtc, old_state, new_state);
12388 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12389 }
12390
12391 static void
12392 verify_disabled_dpll_state(struct drm_device *dev)
12393 {
12394 struct drm_i915_private *dev_priv = to_i915(dev);
12395 int i;
12396
12397 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12398 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12399 }
12400
12401 static void
12402 intel_modeset_verify_disabled(struct drm_device *dev,
12403 struct drm_atomic_state *state)
12404 {
12405 verify_encoder_state(dev, state);
12406 verify_connector_state(dev, state, NULL);
12407 verify_disabled_dpll_state(dev);
12408 }
12409
12410 static void update_scanline_offset(struct intel_crtc *crtc)
12411 {
12412 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12413
12414 /*
12415 * The scanline counter increments at the leading edge of hsync.
12416 *
12417 * On most platforms it starts counting from vtotal-1 on the
12418 * first active line. That means the scanline counter value is
12419 * always one less than what we would expect. Ie. just after
12420 * start of vblank, which also occurs at start of hsync (on the
12421 * last active line), the scanline counter will read vblank_start-1.
12422 *
12423 * On gen2 the scanline counter starts counting from 1 instead
12424 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12425 * to keep the value positive), instead of adding one.
12426 *
12427 * On HSW+ the behaviour of the scanline counter depends on the output
12428 * type. For DP ports it behaves like most other platforms, but on HDMI
12429 * there's an extra 1 line difference. So we need to add two instead of
12430 * one to the value.
12431 *
12432 * On VLV/CHV DSI the scanline counter would appear to increment
12433 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12434 * that means we can't tell whether we're in vblank or not while
12435 * we're on that particular line. We must still set scanline_offset
12436 * to 1 so that the vblank timestamps come out correct when we query
12437 * the scanline counter from within the vblank interrupt handler.
12438 * However if queried just before the start of vblank we'll get an
12439 * answer that's slightly in the future.
12440 */
12441 if (IS_GEN2(dev_priv)) {
12442 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12443 int vtotal;
12444
12445 vtotal = adjusted_mode->crtc_vtotal;
12446 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12447 vtotal /= 2;
12448
12449 crtc->scanline_offset = vtotal - 1;
12450 } else if (HAS_DDI(dev_priv) &&
12451 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12452 crtc->scanline_offset = 2;
12453 } else
12454 crtc->scanline_offset = 1;
12455 }
12456
12457 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12458 {
12459 struct drm_device *dev = state->dev;
12460 struct drm_i915_private *dev_priv = to_i915(dev);
12461 struct drm_crtc *crtc;
12462 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12463 int i;
12464
12465 if (!dev_priv->display.crtc_compute_clock)
12466 return;
12467
12468 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12470 struct intel_shared_dpll *old_dpll =
12471 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12472
12473 if (!needs_modeset(new_crtc_state))
12474 continue;
12475
12476 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12477
12478 if (!old_dpll)
12479 continue;
12480
12481 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12482 }
12483 }
12484
12485 /*
12486 * This implements the workaround described in the "notes" section of the mode
12487 * set sequence documentation. When going from no pipes or single pipe to
12488 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12489 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12490 */
12491 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12492 {
12493 struct drm_crtc_state *crtc_state;
12494 struct intel_crtc *intel_crtc;
12495 struct drm_crtc *crtc;
12496 struct intel_crtc_state *first_crtc_state = NULL;
12497 struct intel_crtc_state *other_crtc_state = NULL;
12498 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12499 int i;
12500
12501 /* look at all crtc's that are going to be enabled in during modeset */
12502 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12503 intel_crtc = to_intel_crtc(crtc);
12504
12505 if (!crtc_state->active || !needs_modeset(crtc_state))
12506 continue;
12507
12508 if (first_crtc_state) {
12509 other_crtc_state = to_intel_crtc_state(crtc_state);
12510 break;
12511 } else {
12512 first_crtc_state = to_intel_crtc_state(crtc_state);
12513 first_pipe = intel_crtc->pipe;
12514 }
12515 }
12516
12517 /* No workaround needed? */
12518 if (!first_crtc_state)
12519 return 0;
12520
12521 /* w/a possibly needed, check how many crtc's are already enabled. */
12522 for_each_intel_crtc(state->dev, intel_crtc) {
12523 struct intel_crtc_state *pipe_config;
12524
12525 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12526 if (IS_ERR(pipe_config))
12527 return PTR_ERR(pipe_config);
12528
12529 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12530
12531 if (!pipe_config->base.active ||
12532 needs_modeset(&pipe_config->base))
12533 continue;
12534
12535 /* 2 or more enabled crtcs means no need for w/a */
12536 if (enabled_pipe != INVALID_PIPE)
12537 return 0;
12538
12539 enabled_pipe = intel_crtc->pipe;
12540 }
12541
12542 if (enabled_pipe != INVALID_PIPE)
12543 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12544 else if (other_crtc_state)
12545 other_crtc_state->hsw_workaround_pipe = first_pipe;
12546
12547 return 0;
12548 }
12549
12550 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12551 {
12552 struct drm_crtc *crtc;
12553
12554 /* Add all pipes to the state */
12555 for_each_crtc(state->dev, crtc) {
12556 struct drm_crtc_state *crtc_state;
12557
12558 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12559 if (IS_ERR(crtc_state))
12560 return PTR_ERR(crtc_state);
12561 }
12562
12563 return 0;
12564 }
12565
12566 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12567 {
12568 struct drm_crtc *crtc;
12569
12570 /*
12571 * Add all pipes to the state, and force
12572 * a modeset on all the active ones.
12573 */
12574 for_each_crtc(state->dev, crtc) {
12575 struct drm_crtc_state *crtc_state;
12576 int ret;
12577
12578 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12579 if (IS_ERR(crtc_state))
12580 return PTR_ERR(crtc_state);
12581
12582 if (!crtc_state->active || needs_modeset(crtc_state))
12583 continue;
12584
12585 crtc_state->mode_changed = true;
12586
12587 ret = drm_atomic_add_affected_connectors(state, crtc);
12588 if (ret)
12589 return ret;
12590
12591 ret = drm_atomic_add_affected_planes(state, crtc);
12592 if (ret)
12593 return ret;
12594 }
12595
12596 return 0;
12597 }
12598
12599 static int intel_modeset_checks(struct drm_atomic_state *state)
12600 {
12601 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12602 struct drm_i915_private *dev_priv = to_i915(state->dev);
12603 struct drm_crtc *crtc;
12604 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12605 int ret = 0, i;
12606
12607 if (!check_digital_port_conflicts(state)) {
12608 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12609 return -EINVAL;
12610 }
12611
12612 intel_state->modeset = true;
12613 intel_state->active_crtcs = dev_priv->active_crtcs;
12614 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12615 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12616
12617 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12618 if (new_crtc_state->active)
12619 intel_state->active_crtcs |= 1 << i;
12620 else
12621 intel_state->active_crtcs &= ~(1 << i);
12622
12623 if (old_crtc_state->active != new_crtc_state->active)
12624 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12625 }
12626
12627 /*
12628 * See if the config requires any additional preparation, e.g.
12629 * to adjust global state with pipes off. We need to do this
12630 * here so we can get the modeset_pipe updated config for the new
12631 * mode set on this crtc. For other crtcs we need to use the
12632 * adjusted_mode bits in the crtc directly.
12633 */
12634 if (dev_priv->display.modeset_calc_cdclk) {
12635 ret = dev_priv->display.modeset_calc_cdclk(state);
12636 if (ret < 0)
12637 return ret;
12638
12639 /*
12640 * Writes to dev_priv->cdclk.logical must protected by
12641 * holding all the crtc locks, even if we don't end up
12642 * touching the hardware
12643 */
12644 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12645 &intel_state->cdclk.logical)) {
12646 ret = intel_lock_all_pipes(state);
12647 if (ret < 0)
12648 return ret;
12649 }
12650
12651 /* All pipes must be switched off while we change the cdclk. */
12652 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12653 &intel_state->cdclk.actual)) {
12654 ret = intel_modeset_all_pipes(state);
12655 if (ret < 0)
12656 return ret;
12657 }
12658
12659 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12660 intel_state->cdclk.logical.cdclk,
12661 intel_state->cdclk.actual.cdclk);
12662 } else {
12663 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12664 }
12665
12666 intel_modeset_clear_plls(state);
12667
12668 if (IS_HASWELL(dev_priv))
12669 return haswell_mode_set_planes_workaround(state);
12670
12671 return 0;
12672 }
12673
12674 /*
12675 * Handle calculation of various watermark data at the end of the atomic check
12676 * phase. The code here should be run after the per-crtc and per-plane 'check'
12677 * handlers to ensure that all derived state has been updated.
12678 */
12679 static int calc_watermark_data(struct drm_atomic_state *state)
12680 {
12681 struct drm_device *dev = state->dev;
12682 struct drm_i915_private *dev_priv = to_i915(dev);
12683
12684 /* Is there platform-specific watermark information to calculate? */
12685 if (dev_priv->display.compute_global_watermarks)
12686 return dev_priv->display.compute_global_watermarks(state);
12687
12688 return 0;
12689 }
12690
12691 /**
12692 * intel_atomic_check - validate state object
12693 * @dev: drm device
12694 * @state: state to validate
12695 */
12696 static int intel_atomic_check(struct drm_device *dev,
12697 struct drm_atomic_state *state)
12698 {
12699 struct drm_i915_private *dev_priv = to_i915(dev);
12700 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12701 struct drm_crtc *crtc;
12702 struct drm_crtc_state *old_crtc_state, *crtc_state;
12703 int ret, i;
12704 bool any_ms = false;
12705
12706 ret = drm_atomic_helper_check_modeset(dev, state);
12707 if (ret)
12708 return ret;
12709
12710 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12711 struct intel_crtc_state *pipe_config =
12712 to_intel_crtc_state(crtc_state);
12713
12714 /* Catch I915_MODE_FLAG_INHERITED */
12715 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12716 crtc_state->mode_changed = true;
12717
12718 if (!needs_modeset(crtc_state))
12719 continue;
12720
12721 if (!crtc_state->enable) {
12722 any_ms = true;
12723 continue;
12724 }
12725
12726 /* FIXME: For only active_changed we shouldn't need to do any
12727 * state recomputation at all. */
12728
12729 ret = drm_atomic_add_affected_connectors(state, crtc);
12730 if (ret)
12731 return ret;
12732
12733 ret = intel_modeset_pipe_config(crtc, pipe_config);
12734 if (ret) {
12735 intel_dump_pipe_config(to_intel_crtc(crtc),
12736 pipe_config, "[failed]");
12737 return ret;
12738 }
12739
12740 if (i915.fastboot &&
12741 intel_pipe_config_compare(dev_priv,
12742 to_intel_crtc_state(old_crtc_state),
12743 pipe_config, true)) {
12744 crtc_state->mode_changed = false;
12745 pipe_config->update_pipe = true;
12746 }
12747
12748 if (needs_modeset(crtc_state))
12749 any_ms = true;
12750
12751 ret = drm_atomic_add_affected_planes(state, crtc);
12752 if (ret)
12753 return ret;
12754
12755 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12756 needs_modeset(crtc_state) ?
12757 "[modeset]" : "[fastset]");
12758 }
12759
12760 if (any_ms) {
12761 ret = intel_modeset_checks(state);
12762
12763 if (ret)
12764 return ret;
12765 } else {
12766 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12767 }
12768
12769 ret = drm_atomic_helper_check_planes(dev, state);
12770 if (ret)
12771 return ret;
12772
12773 intel_fbc_choose_crtc(dev_priv, state);
12774 return calc_watermark_data(state);
12775 }
12776
12777 static int intel_atomic_prepare_commit(struct drm_device *dev,
12778 struct drm_atomic_state *state)
12779 {
12780 struct drm_i915_private *dev_priv = to_i915(dev);
12781 struct drm_crtc_state *crtc_state;
12782 struct drm_crtc *crtc;
12783 int i, ret;
12784
12785 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12786 if (state->legacy_cursor_update)
12787 continue;
12788
12789 ret = intel_crtc_wait_for_pending_flips(crtc);
12790 if (ret)
12791 return ret;
12792
12793 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12794 flush_workqueue(dev_priv->wq);
12795 }
12796
12797 ret = mutex_lock_interruptible(&dev->struct_mutex);
12798 if (ret)
12799 return ret;
12800
12801 ret = drm_atomic_helper_prepare_planes(dev, state);
12802 mutex_unlock(&dev->struct_mutex);
12803
12804 return ret;
12805 }
12806
12807 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12808 {
12809 struct drm_device *dev = crtc->base.dev;
12810
12811 if (!dev->max_vblank_count)
12812 return drm_accurate_vblank_count(&crtc->base);
12813
12814 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12815 }
12816
12817 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12818 struct drm_i915_private *dev_priv,
12819 unsigned crtc_mask)
12820 {
12821 unsigned last_vblank_count[I915_MAX_PIPES];
12822 enum pipe pipe;
12823 int ret;
12824
12825 if (!crtc_mask)
12826 return;
12827
12828 for_each_pipe(dev_priv, pipe) {
12829 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12830 pipe);
12831
12832 if (!((1 << pipe) & crtc_mask))
12833 continue;
12834
12835 ret = drm_crtc_vblank_get(&crtc->base);
12836 if (WARN_ON(ret != 0)) {
12837 crtc_mask &= ~(1 << pipe);
12838 continue;
12839 }
12840
12841 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12842 }
12843
12844 for_each_pipe(dev_priv, pipe) {
12845 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12846 pipe);
12847 long lret;
12848
12849 if (!((1 << pipe) & crtc_mask))
12850 continue;
12851
12852 lret = wait_event_timeout(dev->vblank[pipe].queue,
12853 last_vblank_count[pipe] !=
12854 drm_crtc_vblank_count(&crtc->base),
12855 msecs_to_jiffies(50));
12856
12857 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12858
12859 drm_crtc_vblank_put(&crtc->base);
12860 }
12861 }
12862
12863 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12864 {
12865 /* fb updated, need to unpin old fb */
12866 if (crtc_state->fb_changed)
12867 return true;
12868
12869 /* wm changes, need vblank before final wm's */
12870 if (crtc_state->update_wm_post)
12871 return true;
12872
12873 if (crtc_state->wm.need_postvbl_update)
12874 return true;
12875
12876 return false;
12877 }
12878
12879 static void intel_update_crtc(struct drm_crtc *crtc,
12880 struct drm_atomic_state *state,
12881 struct drm_crtc_state *old_crtc_state,
12882 struct drm_crtc_state *new_crtc_state,
12883 unsigned int *crtc_vblank_mask)
12884 {
12885 struct drm_device *dev = crtc->dev;
12886 struct drm_i915_private *dev_priv = to_i915(dev);
12887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12888 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12889 bool modeset = needs_modeset(new_crtc_state);
12890
12891 if (modeset) {
12892 update_scanline_offset(intel_crtc);
12893 dev_priv->display.crtc_enable(pipe_config, state);
12894 } else {
12895 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12896 pipe_config);
12897 }
12898
12899 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12900 intel_fbc_enable(
12901 intel_crtc, pipe_config,
12902 to_intel_plane_state(crtc->primary->state));
12903 }
12904
12905 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12906
12907 if (needs_vblank_wait(pipe_config))
12908 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12909 }
12910
12911 static void intel_update_crtcs(struct drm_atomic_state *state,
12912 unsigned int *crtc_vblank_mask)
12913 {
12914 struct drm_crtc *crtc;
12915 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12916 int i;
12917
12918 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12919 if (!new_crtc_state->active)
12920 continue;
12921
12922 intel_update_crtc(crtc, state, old_crtc_state,
12923 new_crtc_state, crtc_vblank_mask);
12924 }
12925 }
12926
12927 static void skl_update_crtcs(struct drm_atomic_state *state,
12928 unsigned int *crtc_vblank_mask)
12929 {
12930 struct drm_i915_private *dev_priv = to_i915(state->dev);
12931 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12932 struct drm_crtc *crtc;
12933 struct intel_crtc *intel_crtc;
12934 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12935 struct intel_crtc_state *cstate;
12936 unsigned int updated = 0;
12937 bool progress;
12938 enum pipe pipe;
12939 int i;
12940
12941 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12942
12943 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12944 /* ignore allocations for crtc's that have been turned off. */
12945 if (new_crtc_state->active)
12946 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12947
12948 /*
12949 * Whenever the number of active pipes changes, we need to make sure we
12950 * update the pipes in the right order so that their ddb allocations
12951 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12952 * cause pipe underruns and other bad stuff.
12953 */
12954 do {
12955 progress = false;
12956
12957 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12958 bool vbl_wait = false;
12959 unsigned int cmask = drm_crtc_mask(crtc);
12960
12961 intel_crtc = to_intel_crtc(crtc);
12962 cstate = to_intel_crtc_state(crtc->state);
12963 pipe = intel_crtc->pipe;
12964
12965 if (updated & cmask || !cstate->base.active)
12966 continue;
12967
12968 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12969 continue;
12970
12971 updated |= cmask;
12972 entries[i] = &cstate->wm.skl.ddb;
12973
12974 /*
12975 * If this is an already active pipe, it's DDB changed,
12976 * and this isn't the last pipe that needs updating
12977 * then we need to wait for a vblank to pass for the
12978 * new ddb allocation to take effect.
12979 */
12980 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12981 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12982 !new_crtc_state->active_changed &&
12983 intel_state->wm_results.dirty_pipes != updated)
12984 vbl_wait = true;
12985
12986 intel_update_crtc(crtc, state, old_crtc_state,
12987 new_crtc_state, crtc_vblank_mask);
12988
12989 if (vbl_wait)
12990 intel_wait_for_vblank(dev_priv, pipe);
12991
12992 progress = true;
12993 }
12994 } while (progress);
12995 }
12996
12997 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12998 {
12999 struct intel_atomic_state *state, *next;
13000 struct llist_node *freed;
13001
13002 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13003 llist_for_each_entry_safe(state, next, freed, freed)
13004 drm_atomic_state_put(&state->base);
13005 }
13006
13007 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13008 {
13009 struct drm_i915_private *dev_priv =
13010 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13011
13012 intel_atomic_helper_free_state(dev_priv);
13013 }
13014
13015 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13016 {
13017 struct drm_device *dev = state->dev;
13018 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13019 struct drm_i915_private *dev_priv = to_i915(dev);
13020 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13021 struct drm_crtc *crtc;
13022 struct intel_crtc_state *intel_cstate;
13023 bool hw_check = intel_state->modeset;
13024 u64 put_domains[I915_MAX_PIPES] = {};
13025 unsigned crtc_vblank_mask = 0;
13026 int i;
13027
13028 drm_atomic_helper_wait_for_dependencies(state);
13029
13030 if (intel_state->modeset)
13031 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13032
13033 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13035
13036 if (needs_modeset(new_crtc_state) ||
13037 to_intel_crtc_state(new_crtc_state)->update_pipe) {
13038 hw_check = true;
13039
13040 put_domains[to_intel_crtc(crtc)->pipe] =
13041 modeset_get_crtc_power_domains(crtc,
13042 to_intel_crtc_state(new_crtc_state));
13043 }
13044
13045 if (!needs_modeset(new_crtc_state))
13046 continue;
13047
13048 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13049 to_intel_crtc_state(new_crtc_state));
13050
13051 if (old_crtc_state->active) {
13052 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13053 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
13054 intel_crtc->active = false;
13055 intel_fbc_disable(intel_crtc);
13056 intel_disable_shared_dpll(intel_crtc);
13057
13058 /*
13059 * Underruns don't always raise
13060 * interrupts, so check manually.
13061 */
13062 intel_check_cpu_fifo_underruns(dev_priv);
13063 intel_check_pch_fifo_underruns(dev_priv);
13064
13065 if (!crtc->state->active) {
13066 /*
13067 * Make sure we don't call initial_watermarks
13068 * for ILK-style watermark updates.
13069 *
13070 * No clue what this is supposed to achieve.
13071 */
13072 if (INTEL_GEN(dev_priv) >= 9)
13073 dev_priv->display.initial_watermarks(intel_state,
13074 to_intel_crtc_state(crtc->state));
13075 }
13076 }
13077 }
13078
13079 /* Only after disabling all output pipelines that will be changed can we
13080 * update the the output configuration. */
13081 intel_modeset_update_crtc_state(state);
13082
13083 if (intel_state->modeset) {
13084 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13085
13086 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13087
13088 /*
13089 * SKL workaround: bspec recommends we disable the SAGV when we
13090 * have more then one pipe enabled
13091 */
13092 if (!intel_can_enable_sagv(state))
13093 intel_disable_sagv(dev_priv);
13094
13095 intel_modeset_verify_disabled(dev, state);
13096 }
13097
13098 /* Complete the events for pipes that have now been disabled */
13099 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13100 bool modeset = needs_modeset(new_crtc_state);
13101
13102 /* Complete events for now disable pipes here. */
13103 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13104 spin_lock_irq(&dev->event_lock);
13105 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13106 spin_unlock_irq(&dev->event_lock);
13107
13108 new_crtc_state->event = NULL;
13109 }
13110 }
13111
13112 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13113 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
13114
13115 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13116 * already, but still need the state for the delayed optimization. To
13117 * fix this:
13118 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13119 * - schedule that vblank worker _before_ calling hw_done
13120 * - at the start of commit_tail, cancel it _synchrously
13121 * - switch over to the vblank wait helper in the core after that since
13122 * we don't need out special handling any more.
13123 */
13124 if (!state->legacy_cursor_update)
13125 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13126
13127 /*
13128 * Now that the vblank has passed, we can go ahead and program the
13129 * optimal watermarks on platforms that need two-step watermark
13130 * programming.
13131 *
13132 * TODO: Move this (and other cleanup) to an async worker eventually.
13133 */
13134 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13135 intel_cstate = to_intel_crtc_state(new_crtc_state);
13136
13137 if (dev_priv->display.optimize_watermarks)
13138 dev_priv->display.optimize_watermarks(intel_state,
13139 intel_cstate);
13140 }
13141
13142 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13143 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13144
13145 if (put_domains[i])
13146 modeset_put_power_domains(dev_priv, put_domains[i]);
13147
13148 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13149 }
13150
13151 if (intel_state->modeset && intel_can_enable_sagv(state))
13152 intel_enable_sagv(dev_priv);
13153
13154 drm_atomic_helper_commit_hw_done(state);
13155
13156 if (intel_state->modeset) {
13157 /* As one of the primary mmio accessors, KMS has a high
13158 * likelihood of triggering bugs in unclaimed access. After we
13159 * finish modesetting, see if an error has been flagged, and if
13160 * so enable debugging for the next modeset - and hope we catch
13161 * the culprit.
13162 */
13163 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13164 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13165 }
13166
13167 mutex_lock(&dev->struct_mutex);
13168 drm_atomic_helper_cleanup_planes(dev, state);
13169 mutex_unlock(&dev->struct_mutex);
13170
13171 drm_atomic_helper_commit_cleanup_done(state);
13172
13173 drm_atomic_state_put(state);
13174
13175 intel_atomic_helper_free_state(dev_priv);
13176 }
13177
13178 static void intel_atomic_commit_work(struct work_struct *work)
13179 {
13180 struct drm_atomic_state *state =
13181 container_of(work, struct drm_atomic_state, commit_work);
13182
13183 intel_atomic_commit_tail(state);
13184 }
13185
13186 static int __i915_sw_fence_call
13187 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13188 enum i915_sw_fence_notify notify)
13189 {
13190 struct intel_atomic_state *state =
13191 container_of(fence, struct intel_atomic_state, commit_ready);
13192
13193 switch (notify) {
13194 case FENCE_COMPLETE:
13195 if (state->base.commit_work.func)
13196 queue_work(system_unbound_wq, &state->base.commit_work);
13197 break;
13198
13199 case FENCE_FREE:
13200 {
13201 struct intel_atomic_helper *helper =
13202 &to_i915(state->base.dev)->atomic_helper;
13203
13204 if (llist_add(&state->freed, &helper->free_list))
13205 schedule_work(&helper->free_work);
13206 break;
13207 }
13208 }
13209
13210 return NOTIFY_DONE;
13211 }
13212
13213 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13214 {
13215 struct drm_plane_state *old_plane_state, *new_plane_state;
13216 struct drm_plane *plane;
13217 int i;
13218
13219 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13220 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13221 intel_fb_obj(new_plane_state->fb),
13222 to_intel_plane(plane)->frontbuffer_bit);
13223 }
13224
13225 /**
13226 * intel_atomic_commit - commit validated state object
13227 * @dev: DRM device
13228 * @state: the top-level driver state object
13229 * @nonblock: nonblocking commit
13230 *
13231 * This function commits a top-level state object that has been validated
13232 * with drm_atomic_helper_check().
13233 *
13234 * RETURNS
13235 * Zero for success or -errno.
13236 */
13237 static int intel_atomic_commit(struct drm_device *dev,
13238 struct drm_atomic_state *state,
13239 bool nonblock)
13240 {
13241 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13242 struct drm_i915_private *dev_priv = to_i915(dev);
13243 int ret = 0;
13244
13245 ret = drm_atomic_helper_setup_commit(state, nonblock);
13246 if (ret)
13247 return ret;
13248
13249 drm_atomic_state_get(state);
13250 i915_sw_fence_init(&intel_state->commit_ready,
13251 intel_atomic_commit_ready);
13252
13253 ret = intel_atomic_prepare_commit(dev, state);
13254 if (ret) {
13255 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13256 i915_sw_fence_commit(&intel_state->commit_ready);
13257 return ret;
13258 }
13259
13260 /*
13261 * The intel_legacy_cursor_update() fast path takes care
13262 * of avoiding the vblank waits for simple cursor
13263 * movement and flips. For cursor on/off and size changes,
13264 * we want to perform the vblank waits so that watermark
13265 * updates happen during the correct frames. Gen9+ have
13266 * double buffered watermarks and so shouldn't need this.
13267 *
13268 * Do this after drm_atomic_helper_setup_commit() and
13269 * intel_atomic_prepare_commit() because we still want
13270 * to skip the flip and fb cleanup waits. Although that
13271 * does risk yanking the mapping from under the display
13272 * engine.
13273 *
13274 * FIXME doing watermarks and fb cleanup from a vblank worker
13275 * (assuming we had any) would solve these problems.
13276 */
13277 if (INTEL_GEN(dev_priv) < 9)
13278 state->legacy_cursor_update = false;
13279
13280 drm_atomic_helper_swap_state(state, true);
13281 dev_priv->wm.distrust_bios_wm = false;
13282 intel_shared_dpll_swap_state(state);
13283 intel_atomic_track_fbs(state);
13284
13285 if (intel_state->modeset) {
13286 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13287 sizeof(intel_state->min_pixclk));
13288 dev_priv->active_crtcs = intel_state->active_crtcs;
13289 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13290 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13291 }
13292
13293 drm_atomic_state_get(state);
13294 INIT_WORK(&state->commit_work,
13295 nonblock ? intel_atomic_commit_work : NULL);
13296
13297 i915_sw_fence_commit(&intel_state->commit_ready);
13298 if (!nonblock) {
13299 i915_sw_fence_wait(&intel_state->commit_ready);
13300 intel_atomic_commit_tail(state);
13301 }
13302
13303 return 0;
13304 }
13305
13306 static const struct drm_crtc_funcs intel_crtc_funcs = {
13307 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13308 .set_config = drm_atomic_helper_set_config,
13309 .set_property = drm_atomic_helper_crtc_set_property,
13310 .destroy = intel_crtc_destroy,
13311 .page_flip = drm_atomic_helper_page_flip,
13312 .atomic_duplicate_state = intel_crtc_duplicate_state,
13313 .atomic_destroy_state = intel_crtc_destroy_state,
13314 .set_crc_source = intel_crtc_set_crc_source,
13315 };
13316
13317 /**
13318 * intel_prepare_plane_fb - Prepare fb for usage on plane
13319 * @plane: drm plane to prepare for
13320 * @fb: framebuffer to prepare for presentation
13321 *
13322 * Prepares a framebuffer for usage on a display plane. Generally this
13323 * involves pinning the underlying object and updating the frontbuffer tracking
13324 * bits. Some older platforms need special physical address handling for
13325 * cursor planes.
13326 *
13327 * Must be called with struct_mutex held.
13328 *
13329 * Returns 0 on success, negative error code on failure.
13330 */
13331 int
13332 intel_prepare_plane_fb(struct drm_plane *plane,
13333 struct drm_plane_state *new_state)
13334 {
13335 struct intel_atomic_state *intel_state =
13336 to_intel_atomic_state(new_state->state);
13337 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13338 struct drm_framebuffer *fb = new_state->fb;
13339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13340 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13341 int ret;
13342
13343 if (obj) {
13344 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13345 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13346 const int align = intel_cursor_alignment(dev_priv);
13347
13348 ret = i915_gem_object_attach_phys(obj, align);
13349 if (ret) {
13350 DRM_DEBUG_KMS("failed to attach phys object\n");
13351 return ret;
13352 }
13353 } else {
13354 struct i915_vma *vma;
13355
13356 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13357 if (IS_ERR(vma)) {
13358 DRM_DEBUG_KMS("failed to pin object\n");
13359 return PTR_ERR(vma);
13360 }
13361
13362 to_intel_plane_state(new_state)->vma = vma;
13363 }
13364 }
13365
13366 if (!obj && !old_obj)
13367 return 0;
13368
13369 if (old_obj) {
13370 struct drm_crtc_state *crtc_state =
13371 drm_atomic_get_existing_crtc_state(new_state->state,
13372 plane->state->crtc);
13373
13374 /* Big Hammer, we also need to ensure that any pending
13375 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13376 * current scanout is retired before unpinning the old
13377 * framebuffer. Note that we rely on userspace rendering
13378 * into the buffer attached to the pipe they are waiting
13379 * on. If not, userspace generates a GPU hang with IPEHR
13380 * point to the MI_WAIT_FOR_EVENT.
13381 *
13382 * This should only fail upon a hung GPU, in which case we
13383 * can safely continue.
13384 */
13385 if (needs_modeset(crtc_state)) {
13386 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13387 old_obj->resv, NULL,
13388 false, 0,
13389 GFP_KERNEL);
13390 if (ret < 0)
13391 return ret;
13392 }
13393 }
13394
13395 if (new_state->fence) { /* explicit fencing */
13396 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13397 new_state->fence,
13398 I915_FENCE_TIMEOUT,
13399 GFP_KERNEL);
13400 if (ret < 0)
13401 return ret;
13402 }
13403
13404 if (!obj)
13405 return 0;
13406
13407 if (!new_state->fence) { /* implicit fencing */
13408 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13409 obj->resv, NULL,
13410 false, I915_FENCE_TIMEOUT,
13411 GFP_KERNEL);
13412 if (ret < 0)
13413 return ret;
13414
13415 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13416 }
13417
13418 return 0;
13419 }
13420
13421 /**
13422 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13423 * @plane: drm plane to clean up for
13424 * @fb: old framebuffer that was on plane
13425 *
13426 * Cleans up a framebuffer that has just been removed from a plane.
13427 *
13428 * Must be called with struct_mutex held.
13429 */
13430 void
13431 intel_cleanup_plane_fb(struct drm_plane *plane,
13432 struct drm_plane_state *old_state)
13433 {
13434 struct i915_vma *vma;
13435
13436 /* Should only be called after a successful intel_prepare_plane_fb()! */
13437 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13438 if (vma)
13439 intel_unpin_fb_vma(vma);
13440 }
13441
13442 int
13443 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13444 {
13445 struct drm_i915_private *dev_priv;
13446 int max_scale;
13447 int crtc_clock, max_dotclk;
13448
13449 if (!intel_crtc || !crtc_state->base.enable)
13450 return DRM_PLANE_HELPER_NO_SCALING;
13451
13452 dev_priv = to_i915(intel_crtc->base.dev);
13453
13454 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13455 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13456
13457 if (IS_GEMINILAKE(dev_priv))
13458 max_dotclk *= 2;
13459
13460 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13461 return DRM_PLANE_HELPER_NO_SCALING;
13462
13463 /*
13464 * skl max scale is lower of:
13465 * close to 3 but not 3, -1 is for that purpose
13466 * or
13467 * cdclk/crtc_clock
13468 */
13469 max_scale = min((1 << 16) * 3 - 1,
13470 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13471
13472 return max_scale;
13473 }
13474
13475 static int
13476 intel_check_primary_plane(struct intel_plane *plane,
13477 struct intel_crtc_state *crtc_state,
13478 struct intel_plane_state *state)
13479 {
13480 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13481 struct drm_crtc *crtc = state->base.crtc;
13482 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13483 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13484 bool can_position = false;
13485 int ret;
13486
13487 if (INTEL_GEN(dev_priv) >= 9) {
13488 /* use scaler when colorkey is not required */
13489 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13490 min_scale = 1;
13491 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13492 }
13493 can_position = true;
13494 }
13495
13496 ret = drm_plane_helper_check_state(&state->base,
13497 &state->clip,
13498 min_scale, max_scale,
13499 can_position, true);
13500 if (ret)
13501 return ret;
13502
13503 if (!state->base.fb)
13504 return 0;
13505
13506 if (INTEL_GEN(dev_priv) >= 9) {
13507 ret = skl_check_plane_surface(state);
13508 if (ret)
13509 return ret;
13510
13511 state->ctl = skl_plane_ctl(crtc_state, state);
13512 } else {
13513 ret = i9xx_check_plane_surface(state);
13514 if (ret)
13515 return ret;
13516
13517 state->ctl = i9xx_plane_ctl(crtc_state, state);
13518 }
13519
13520 return 0;
13521 }
13522
13523 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13524 struct drm_crtc_state *old_crtc_state)
13525 {
13526 struct drm_device *dev = crtc->dev;
13527 struct drm_i915_private *dev_priv = to_i915(dev);
13528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13529 struct intel_crtc_state *intel_cstate =
13530 to_intel_crtc_state(crtc->state);
13531 struct intel_crtc_state *old_intel_cstate =
13532 to_intel_crtc_state(old_crtc_state);
13533 struct intel_atomic_state *old_intel_state =
13534 to_intel_atomic_state(old_crtc_state->state);
13535 bool modeset = needs_modeset(crtc->state);
13536
13537 if (!modeset &&
13538 (intel_cstate->base.color_mgmt_changed ||
13539 intel_cstate->update_pipe)) {
13540 intel_color_set_csc(crtc->state);
13541 intel_color_load_luts(crtc->state);
13542 }
13543
13544 /* Perform vblank evasion around commit operation */
13545 intel_pipe_update_start(intel_crtc);
13546
13547 if (modeset)
13548 goto out;
13549
13550 if (intel_cstate->update_pipe)
13551 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13552 else if (INTEL_GEN(dev_priv) >= 9)
13553 skl_detach_scalers(intel_crtc);
13554
13555 out:
13556 if (dev_priv->display.atomic_update_watermarks)
13557 dev_priv->display.atomic_update_watermarks(old_intel_state,
13558 intel_cstate);
13559 }
13560
13561 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13562 struct drm_crtc_state *old_crtc_state)
13563 {
13564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13565
13566 intel_pipe_update_end(intel_crtc, NULL);
13567 }
13568
13569 /**
13570 * intel_plane_destroy - destroy a plane
13571 * @plane: plane to destroy
13572 *
13573 * Common destruction function for all types of planes (primary, cursor,
13574 * sprite).
13575 */
13576 void intel_plane_destroy(struct drm_plane *plane)
13577 {
13578 drm_plane_cleanup(plane);
13579 kfree(to_intel_plane(plane));
13580 }
13581
13582 const struct drm_plane_funcs intel_plane_funcs = {
13583 .update_plane = drm_atomic_helper_update_plane,
13584 .disable_plane = drm_atomic_helper_disable_plane,
13585 .destroy = intel_plane_destroy,
13586 .set_property = drm_atomic_helper_plane_set_property,
13587 .atomic_get_property = intel_plane_atomic_get_property,
13588 .atomic_set_property = intel_plane_atomic_set_property,
13589 .atomic_duplicate_state = intel_plane_duplicate_state,
13590 .atomic_destroy_state = intel_plane_destroy_state,
13591 };
13592
13593 static int
13594 intel_legacy_cursor_update(struct drm_plane *plane,
13595 struct drm_crtc *crtc,
13596 struct drm_framebuffer *fb,
13597 int crtc_x, int crtc_y,
13598 unsigned int crtc_w, unsigned int crtc_h,
13599 uint32_t src_x, uint32_t src_y,
13600 uint32_t src_w, uint32_t src_h,
13601 struct drm_modeset_acquire_ctx *ctx)
13602 {
13603 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13604 int ret;
13605 struct drm_plane_state *old_plane_state, *new_plane_state;
13606 struct intel_plane *intel_plane = to_intel_plane(plane);
13607 struct drm_framebuffer *old_fb;
13608 struct drm_crtc_state *crtc_state = crtc->state;
13609 struct i915_vma *old_vma;
13610
13611 /*
13612 * When crtc is inactive or there is a modeset pending,
13613 * wait for it to complete in the slowpath
13614 */
13615 if (!crtc_state->active || needs_modeset(crtc_state) ||
13616 to_intel_crtc_state(crtc_state)->update_pipe)
13617 goto slow;
13618
13619 old_plane_state = plane->state;
13620
13621 /*
13622 * If any parameters change that may affect watermarks,
13623 * take the slowpath. Only changing fb or position should be
13624 * in the fastpath.
13625 */
13626 if (old_plane_state->crtc != crtc ||
13627 old_plane_state->src_w != src_w ||
13628 old_plane_state->src_h != src_h ||
13629 old_plane_state->crtc_w != crtc_w ||
13630 old_plane_state->crtc_h != crtc_h ||
13631 !old_plane_state->fb != !fb)
13632 goto slow;
13633
13634 new_plane_state = intel_plane_duplicate_state(plane);
13635 if (!new_plane_state)
13636 return -ENOMEM;
13637
13638 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13639
13640 new_plane_state->src_x = src_x;
13641 new_plane_state->src_y = src_y;
13642 new_plane_state->src_w = src_w;
13643 new_plane_state->src_h = src_h;
13644 new_plane_state->crtc_x = crtc_x;
13645 new_plane_state->crtc_y = crtc_y;
13646 new_plane_state->crtc_w = crtc_w;
13647 new_plane_state->crtc_h = crtc_h;
13648
13649 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13650 to_intel_plane_state(new_plane_state));
13651 if (ret)
13652 goto out_free;
13653
13654 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13655 if (ret)
13656 goto out_free;
13657
13658 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13659 int align = intel_cursor_alignment(dev_priv);
13660
13661 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13662 if (ret) {
13663 DRM_DEBUG_KMS("failed to attach phys object\n");
13664 goto out_unlock;
13665 }
13666 } else {
13667 struct i915_vma *vma;
13668
13669 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13670 if (IS_ERR(vma)) {
13671 DRM_DEBUG_KMS("failed to pin object\n");
13672
13673 ret = PTR_ERR(vma);
13674 goto out_unlock;
13675 }
13676
13677 to_intel_plane_state(new_plane_state)->vma = vma;
13678 }
13679
13680 old_fb = old_plane_state->fb;
13681 old_vma = to_intel_plane_state(old_plane_state)->vma;
13682
13683 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13684 intel_plane->frontbuffer_bit);
13685
13686 /* Swap plane state */
13687 new_plane_state->fence = old_plane_state->fence;
13688 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13689 new_plane_state->fence = NULL;
13690 new_plane_state->fb = old_fb;
13691 to_intel_plane_state(new_plane_state)->vma = old_vma;
13692
13693 if (plane->state->visible) {
13694 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13695 intel_plane->update_plane(intel_plane,
13696 to_intel_crtc_state(crtc->state),
13697 to_intel_plane_state(plane->state));
13698 } else {
13699 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13700 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13701 }
13702
13703 intel_cleanup_plane_fb(plane, new_plane_state);
13704
13705 out_unlock:
13706 mutex_unlock(&dev_priv->drm.struct_mutex);
13707 out_free:
13708 intel_plane_destroy_state(plane, new_plane_state);
13709 return ret;
13710
13711 slow:
13712 return drm_atomic_helper_update_plane(plane, crtc, fb,
13713 crtc_x, crtc_y, crtc_w, crtc_h,
13714 src_x, src_y, src_w, src_h, ctx);
13715 }
13716
13717 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13718 .update_plane = intel_legacy_cursor_update,
13719 .disable_plane = drm_atomic_helper_disable_plane,
13720 .destroy = intel_plane_destroy,
13721 .set_property = drm_atomic_helper_plane_set_property,
13722 .atomic_get_property = intel_plane_atomic_get_property,
13723 .atomic_set_property = intel_plane_atomic_set_property,
13724 .atomic_duplicate_state = intel_plane_duplicate_state,
13725 .atomic_destroy_state = intel_plane_destroy_state,
13726 };
13727
13728 static struct intel_plane *
13729 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13730 {
13731 struct intel_plane *primary = NULL;
13732 struct intel_plane_state *state = NULL;
13733 const uint32_t *intel_primary_formats;
13734 unsigned int supported_rotations;
13735 unsigned int num_formats;
13736 int ret;
13737
13738 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13739 if (!primary) {
13740 ret = -ENOMEM;
13741 goto fail;
13742 }
13743
13744 state = intel_create_plane_state(&primary->base);
13745 if (!state) {
13746 ret = -ENOMEM;
13747 goto fail;
13748 }
13749
13750 primary->base.state = &state->base;
13751
13752 primary->can_scale = false;
13753 primary->max_downscale = 1;
13754 if (INTEL_GEN(dev_priv) >= 9) {
13755 primary->can_scale = true;
13756 state->scaler_id = -1;
13757 }
13758 primary->pipe = pipe;
13759 /*
13760 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13761 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13762 */
13763 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13764 primary->plane = (enum plane) !pipe;
13765 else
13766 primary->plane = (enum plane) pipe;
13767 primary->id = PLANE_PRIMARY;
13768 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13769 primary->check_plane = intel_check_primary_plane;
13770
13771 if (INTEL_GEN(dev_priv) >= 9) {
13772 intel_primary_formats = skl_primary_formats;
13773 num_formats = ARRAY_SIZE(skl_primary_formats);
13774
13775 primary->update_plane = skylake_update_primary_plane;
13776 primary->disable_plane = skylake_disable_primary_plane;
13777 } else if (INTEL_GEN(dev_priv) >= 4) {
13778 intel_primary_formats = i965_primary_formats;
13779 num_formats = ARRAY_SIZE(i965_primary_formats);
13780
13781 primary->update_plane = i9xx_update_primary_plane;
13782 primary->disable_plane = i9xx_disable_primary_plane;
13783 } else {
13784 intel_primary_formats = i8xx_primary_formats;
13785 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13786
13787 primary->update_plane = i9xx_update_primary_plane;
13788 primary->disable_plane = i9xx_disable_primary_plane;
13789 }
13790
13791 if (INTEL_GEN(dev_priv) >= 9)
13792 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13793 0, &intel_plane_funcs,
13794 intel_primary_formats, num_formats,
13795 DRM_PLANE_TYPE_PRIMARY,
13796 "plane 1%c", pipe_name(pipe));
13797 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13798 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13799 0, &intel_plane_funcs,
13800 intel_primary_formats, num_formats,
13801 DRM_PLANE_TYPE_PRIMARY,
13802 "primary %c", pipe_name(pipe));
13803 else
13804 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13805 0, &intel_plane_funcs,
13806 intel_primary_formats, num_formats,
13807 DRM_PLANE_TYPE_PRIMARY,
13808 "plane %c", plane_name(primary->plane));
13809 if (ret)
13810 goto fail;
13811
13812 if (INTEL_GEN(dev_priv) >= 9) {
13813 supported_rotations =
13814 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13815 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13816 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13817 supported_rotations =
13818 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13819 DRM_MODE_REFLECT_X;
13820 } else if (INTEL_GEN(dev_priv) >= 4) {
13821 supported_rotations =
13822 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13823 } else {
13824 supported_rotations = DRM_MODE_ROTATE_0;
13825 }
13826
13827 if (INTEL_GEN(dev_priv) >= 4)
13828 drm_plane_create_rotation_property(&primary->base,
13829 DRM_MODE_ROTATE_0,
13830 supported_rotations);
13831
13832 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13833
13834 return primary;
13835
13836 fail:
13837 kfree(state);
13838 kfree(primary);
13839
13840 return ERR_PTR(ret);
13841 }
13842
13843 static struct intel_plane *
13844 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13845 enum pipe pipe)
13846 {
13847 struct intel_plane *cursor = NULL;
13848 struct intel_plane_state *state = NULL;
13849 int ret;
13850
13851 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13852 if (!cursor) {
13853 ret = -ENOMEM;
13854 goto fail;
13855 }
13856
13857 state = intel_create_plane_state(&cursor->base);
13858 if (!state) {
13859 ret = -ENOMEM;
13860 goto fail;
13861 }
13862
13863 cursor->base.state = &state->base;
13864
13865 cursor->can_scale = false;
13866 cursor->max_downscale = 1;
13867 cursor->pipe = pipe;
13868 cursor->plane = pipe;
13869 cursor->id = PLANE_CURSOR;
13870 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13871
13872 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13873 cursor->update_plane = i845_update_cursor;
13874 cursor->disable_plane = i845_disable_cursor;
13875 cursor->check_plane = i845_check_cursor;
13876 } else {
13877 cursor->update_plane = i9xx_update_cursor;
13878 cursor->disable_plane = i9xx_disable_cursor;
13879 cursor->check_plane = i9xx_check_cursor;
13880 }
13881
13882 cursor->cursor.base = ~0;
13883 cursor->cursor.cntl = ~0;
13884
13885 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13886 cursor->cursor.size = ~0;
13887
13888 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13889 0, &intel_cursor_plane_funcs,
13890 intel_cursor_formats,
13891 ARRAY_SIZE(intel_cursor_formats),
13892 DRM_PLANE_TYPE_CURSOR,
13893 "cursor %c", pipe_name(pipe));
13894 if (ret)
13895 goto fail;
13896
13897 if (INTEL_GEN(dev_priv) >= 4)
13898 drm_plane_create_rotation_property(&cursor->base,
13899 DRM_MODE_ROTATE_0,
13900 DRM_MODE_ROTATE_0 |
13901 DRM_MODE_ROTATE_180);
13902
13903 if (INTEL_GEN(dev_priv) >= 9)
13904 state->scaler_id = -1;
13905
13906 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13907
13908 return cursor;
13909
13910 fail:
13911 kfree(state);
13912 kfree(cursor);
13913
13914 return ERR_PTR(ret);
13915 }
13916
13917 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13918 struct intel_crtc_state *crtc_state)
13919 {
13920 struct intel_crtc_scaler_state *scaler_state =
13921 &crtc_state->scaler_state;
13922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13923 int i;
13924
13925 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13926 if (!crtc->num_scalers)
13927 return;
13928
13929 for (i = 0; i < crtc->num_scalers; i++) {
13930 struct intel_scaler *scaler = &scaler_state->scalers[i];
13931
13932 scaler->in_use = 0;
13933 scaler->mode = PS_SCALER_MODE_DYN;
13934 }
13935
13936 scaler_state->scaler_id = -1;
13937 }
13938
13939 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13940 {
13941 struct intel_crtc *intel_crtc;
13942 struct intel_crtc_state *crtc_state = NULL;
13943 struct intel_plane *primary = NULL;
13944 struct intel_plane *cursor = NULL;
13945 int sprite, ret;
13946
13947 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13948 if (!intel_crtc)
13949 return -ENOMEM;
13950
13951 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13952 if (!crtc_state) {
13953 ret = -ENOMEM;
13954 goto fail;
13955 }
13956 intel_crtc->config = crtc_state;
13957 intel_crtc->base.state = &crtc_state->base;
13958 crtc_state->base.crtc = &intel_crtc->base;
13959
13960 primary = intel_primary_plane_create(dev_priv, pipe);
13961 if (IS_ERR(primary)) {
13962 ret = PTR_ERR(primary);
13963 goto fail;
13964 }
13965 intel_crtc->plane_ids_mask |= BIT(primary->id);
13966
13967 for_each_sprite(dev_priv, pipe, sprite) {
13968 struct intel_plane *plane;
13969
13970 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13971 if (IS_ERR(plane)) {
13972 ret = PTR_ERR(plane);
13973 goto fail;
13974 }
13975 intel_crtc->plane_ids_mask |= BIT(plane->id);
13976 }
13977
13978 cursor = intel_cursor_plane_create(dev_priv, pipe);
13979 if (IS_ERR(cursor)) {
13980 ret = PTR_ERR(cursor);
13981 goto fail;
13982 }
13983 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13984
13985 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13986 &primary->base, &cursor->base,
13987 &intel_crtc_funcs,
13988 "pipe %c", pipe_name(pipe));
13989 if (ret)
13990 goto fail;
13991
13992 intel_crtc->pipe = pipe;
13993 intel_crtc->plane = primary->plane;
13994
13995 /* initialize shared scalers */
13996 intel_crtc_init_scalers(intel_crtc, crtc_state);
13997
13998 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13999 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14000 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
14001 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
14002
14003 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14004
14005 intel_color_init(&intel_crtc->base);
14006
14007 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14008
14009 return 0;
14010
14011 fail:
14012 /*
14013 * drm_mode_config_cleanup() will free up any
14014 * crtcs/planes already initialized.
14015 */
14016 kfree(crtc_state);
14017 kfree(intel_crtc);
14018
14019 return ret;
14020 }
14021
14022 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14023 {
14024 struct drm_device *dev = connector->base.dev;
14025
14026 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14027
14028 if (!connector->base.state->crtc)
14029 return INVALID_PIPE;
14030
14031 return to_intel_crtc(connector->base.state->crtc)->pipe;
14032 }
14033
14034 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14035 struct drm_file *file)
14036 {
14037 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14038 struct drm_crtc *drmmode_crtc;
14039 struct intel_crtc *crtc;
14040
14041 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14042 if (!drmmode_crtc)
14043 return -ENOENT;
14044
14045 crtc = to_intel_crtc(drmmode_crtc);
14046 pipe_from_crtc_id->pipe = crtc->pipe;
14047
14048 return 0;
14049 }
14050
14051 static int intel_encoder_clones(struct intel_encoder *encoder)
14052 {
14053 struct drm_device *dev = encoder->base.dev;
14054 struct intel_encoder *source_encoder;
14055 int index_mask = 0;
14056 int entry = 0;
14057
14058 for_each_intel_encoder(dev, source_encoder) {
14059 if (encoders_cloneable(encoder, source_encoder))
14060 index_mask |= (1 << entry);
14061
14062 entry++;
14063 }
14064
14065 return index_mask;
14066 }
14067
14068 static bool has_edp_a(struct drm_i915_private *dev_priv)
14069 {
14070 if (!IS_MOBILE(dev_priv))
14071 return false;
14072
14073 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14074 return false;
14075
14076 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14077 return false;
14078
14079 return true;
14080 }
14081
14082 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14083 {
14084 if (INTEL_GEN(dev_priv) >= 9)
14085 return false;
14086
14087 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14088 return false;
14089
14090 if (IS_CHERRYVIEW(dev_priv))
14091 return false;
14092
14093 if (HAS_PCH_LPT_H(dev_priv) &&
14094 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14095 return false;
14096
14097 /* DDI E can't be used if DDI A requires 4 lanes */
14098 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14099 return false;
14100
14101 if (!dev_priv->vbt.int_crt_support)
14102 return false;
14103
14104 return true;
14105 }
14106
14107 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14108 {
14109 int pps_num;
14110 int pps_idx;
14111
14112 if (HAS_DDI(dev_priv))
14113 return;
14114 /*
14115 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14116 * everywhere where registers can be write protected.
14117 */
14118 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14119 pps_num = 2;
14120 else
14121 pps_num = 1;
14122
14123 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14124 u32 val = I915_READ(PP_CONTROL(pps_idx));
14125
14126 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14127 I915_WRITE(PP_CONTROL(pps_idx), val);
14128 }
14129 }
14130
14131 static void intel_pps_init(struct drm_i915_private *dev_priv)
14132 {
14133 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14134 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14135 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14136 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14137 else
14138 dev_priv->pps_mmio_base = PPS_BASE;
14139
14140 intel_pps_unlock_regs_wa(dev_priv);
14141 }
14142
14143 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14144 {
14145 struct intel_encoder *encoder;
14146 bool dpd_is_edp = false;
14147
14148 intel_pps_init(dev_priv);
14149
14150 /*
14151 * intel_edp_init_connector() depends on this completing first, to
14152 * prevent the registeration of both eDP and LVDS and the incorrect
14153 * sharing of the PPS.
14154 */
14155 intel_lvds_init(dev_priv);
14156
14157 if (intel_crt_present(dev_priv))
14158 intel_crt_init(dev_priv);
14159
14160 if (IS_GEN9_LP(dev_priv)) {
14161 /*
14162 * FIXME: Broxton doesn't support port detection via the
14163 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14164 * detect the ports.
14165 */
14166 intel_ddi_init(dev_priv, PORT_A);
14167 intel_ddi_init(dev_priv, PORT_B);
14168 intel_ddi_init(dev_priv, PORT_C);
14169
14170 intel_dsi_init(dev_priv);
14171 } else if (HAS_DDI(dev_priv)) {
14172 int found;
14173
14174 /*
14175 * Haswell uses DDI functions to detect digital outputs.
14176 * On SKL pre-D0 the strap isn't connected, so we assume
14177 * it's there.
14178 */
14179 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14180 /* WaIgnoreDDIAStrap: skl */
14181 if (found || IS_GEN9_BC(dev_priv))
14182 intel_ddi_init(dev_priv, PORT_A);
14183
14184 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14185 * register */
14186 found = I915_READ(SFUSE_STRAP);
14187
14188 if (found & SFUSE_STRAP_DDIB_DETECTED)
14189 intel_ddi_init(dev_priv, PORT_B);
14190 if (found & SFUSE_STRAP_DDIC_DETECTED)
14191 intel_ddi_init(dev_priv, PORT_C);
14192 if (found & SFUSE_STRAP_DDID_DETECTED)
14193 intel_ddi_init(dev_priv, PORT_D);
14194 /*
14195 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14196 */
14197 if (IS_GEN9_BC(dev_priv) &&
14198 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14199 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14200 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14201 intel_ddi_init(dev_priv, PORT_E);
14202
14203 } else if (HAS_PCH_SPLIT(dev_priv)) {
14204 int found;
14205 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14206
14207 if (has_edp_a(dev_priv))
14208 intel_dp_init(dev_priv, DP_A, PORT_A);
14209
14210 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14211 /* PCH SDVOB multiplex with HDMIB */
14212 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14213 if (!found)
14214 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14215 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14216 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14217 }
14218
14219 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14220 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14221
14222 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14223 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14224
14225 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14226 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14227
14228 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14229 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14230 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14231 bool has_edp, has_port;
14232
14233 /*
14234 * The DP_DETECTED bit is the latched state of the DDC
14235 * SDA pin at boot. However since eDP doesn't require DDC
14236 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14237 * eDP ports may have been muxed to an alternate function.
14238 * Thus we can't rely on the DP_DETECTED bit alone to detect
14239 * eDP ports. Consult the VBT as well as DP_DETECTED to
14240 * detect eDP ports.
14241 *
14242 * Sadly the straps seem to be missing sometimes even for HDMI
14243 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14244 * and VBT for the presence of the port. Additionally we can't
14245 * trust the port type the VBT declares as we've seen at least
14246 * HDMI ports that the VBT claim are DP or eDP.
14247 */
14248 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14249 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14250 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14251 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14252 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14253 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14254
14255 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14256 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14257 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14258 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14259 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14260 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14261
14262 if (IS_CHERRYVIEW(dev_priv)) {
14263 /*
14264 * eDP not supported on port D,
14265 * so no need to worry about it
14266 */
14267 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14268 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14269 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14270 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14271 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14272 }
14273
14274 intel_dsi_init(dev_priv);
14275 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14276 bool found = false;
14277
14278 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14279 DRM_DEBUG_KMS("probing SDVOB\n");
14280 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14281 if (!found && IS_G4X(dev_priv)) {
14282 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14283 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14284 }
14285
14286 if (!found && IS_G4X(dev_priv))
14287 intel_dp_init(dev_priv, DP_B, PORT_B);
14288 }
14289
14290 /* Before G4X SDVOC doesn't have its own detect register */
14291
14292 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14293 DRM_DEBUG_KMS("probing SDVOC\n");
14294 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14295 }
14296
14297 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14298
14299 if (IS_G4X(dev_priv)) {
14300 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14301 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14302 }
14303 if (IS_G4X(dev_priv))
14304 intel_dp_init(dev_priv, DP_C, PORT_C);
14305 }
14306
14307 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14308 intel_dp_init(dev_priv, DP_D, PORT_D);
14309 } else if (IS_GEN2(dev_priv))
14310 intel_dvo_init(dev_priv);
14311
14312 if (SUPPORTS_TV(dev_priv))
14313 intel_tv_init(dev_priv);
14314
14315 intel_psr_init(dev_priv);
14316
14317 for_each_intel_encoder(&dev_priv->drm, encoder) {
14318 encoder->base.possible_crtcs = encoder->crtc_mask;
14319 encoder->base.possible_clones =
14320 intel_encoder_clones(encoder);
14321 }
14322
14323 intel_init_pch_refclk(dev_priv);
14324
14325 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14326 }
14327
14328 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14329 {
14330 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14331
14332 drm_framebuffer_cleanup(fb);
14333
14334 i915_gem_object_lock(intel_fb->obj);
14335 WARN_ON(!intel_fb->obj->framebuffer_references--);
14336 i915_gem_object_unlock(intel_fb->obj);
14337
14338 i915_gem_object_put(intel_fb->obj);
14339
14340 kfree(intel_fb);
14341 }
14342
14343 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14344 struct drm_file *file,
14345 unsigned int *handle)
14346 {
14347 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14348 struct drm_i915_gem_object *obj = intel_fb->obj;
14349
14350 if (obj->userptr.mm) {
14351 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14352 return -EINVAL;
14353 }
14354
14355 return drm_gem_handle_create(file, &obj->base, handle);
14356 }
14357
14358 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14359 struct drm_file *file,
14360 unsigned flags, unsigned color,
14361 struct drm_clip_rect *clips,
14362 unsigned num_clips)
14363 {
14364 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14365
14366 i915_gem_object_flush_if_display(obj);
14367 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14368
14369 return 0;
14370 }
14371
14372 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14373 .destroy = intel_user_framebuffer_destroy,
14374 .create_handle = intel_user_framebuffer_create_handle,
14375 .dirty = intel_user_framebuffer_dirty,
14376 };
14377
14378 static
14379 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14380 uint64_t fb_modifier, uint32_t pixel_format)
14381 {
14382 u32 gen = INTEL_GEN(dev_priv);
14383
14384 if (gen >= 9) {
14385 int cpp = drm_format_plane_cpp(pixel_format, 0);
14386
14387 /* "The stride in bytes must not exceed the of the size of 8K
14388 * pixels and 32K bytes."
14389 */
14390 return min(8192 * cpp, 32768);
14391 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14392 return 32*1024;
14393 } else if (gen >= 4) {
14394 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14395 return 16*1024;
14396 else
14397 return 32*1024;
14398 } else if (gen >= 3) {
14399 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14400 return 8*1024;
14401 else
14402 return 16*1024;
14403 } else {
14404 /* XXX DSPC is limited to 4k tiled */
14405 return 8*1024;
14406 }
14407 }
14408
14409 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14410 struct drm_i915_gem_object *obj,
14411 struct drm_mode_fb_cmd2 *mode_cmd)
14412 {
14413 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14414 struct drm_format_name_buf format_name;
14415 u32 pitch_limit, stride_alignment;
14416 unsigned int tiling, stride;
14417 int ret = -EINVAL;
14418
14419 i915_gem_object_lock(obj);
14420 obj->framebuffer_references++;
14421 tiling = i915_gem_object_get_tiling(obj);
14422 stride = i915_gem_object_get_stride(obj);
14423 i915_gem_object_unlock(obj);
14424
14425 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14426 /*
14427 * If there's a fence, enforce that
14428 * the fb modifier and tiling mode match.
14429 */
14430 if (tiling != I915_TILING_NONE &&
14431 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14432 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14433 goto err;
14434 }
14435 } else {
14436 if (tiling == I915_TILING_X) {
14437 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14438 } else if (tiling == I915_TILING_Y) {
14439 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14440 goto err;
14441 }
14442 }
14443
14444 /* Passed in modifier sanity checking. */
14445 switch (mode_cmd->modifier[0]) {
14446 case I915_FORMAT_MOD_Y_TILED:
14447 case I915_FORMAT_MOD_Yf_TILED:
14448 if (INTEL_GEN(dev_priv) < 9) {
14449 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14450 mode_cmd->modifier[0]);
14451 goto err;
14452 }
14453 case DRM_FORMAT_MOD_LINEAR:
14454 case I915_FORMAT_MOD_X_TILED:
14455 break;
14456 default:
14457 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14458 mode_cmd->modifier[0]);
14459 goto err;
14460 }
14461
14462 /*
14463 * gen2/3 display engine uses the fence if present,
14464 * so the tiling mode must match the fb modifier exactly.
14465 */
14466 if (INTEL_INFO(dev_priv)->gen < 4 &&
14467 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14468 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14469 goto err;
14470 }
14471
14472 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14473 mode_cmd->pixel_format);
14474 if (mode_cmd->pitches[0] > pitch_limit) {
14475 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14476 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14477 "tiled" : "linear",
14478 mode_cmd->pitches[0], pitch_limit);
14479 goto err;
14480 }
14481
14482 /*
14483 * If there's a fence, enforce that
14484 * the fb pitch and fence stride match.
14485 */
14486 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14487 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14488 mode_cmd->pitches[0], stride);
14489 goto err;
14490 }
14491
14492 /* Reject formats not supported by any plane early. */
14493 switch (mode_cmd->pixel_format) {
14494 case DRM_FORMAT_C8:
14495 case DRM_FORMAT_RGB565:
14496 case DRM_FORMAT_XRGB8888:
14497 case DRM_FORMAT_ARGB8888:
14498 break;
14499 case DRM_FORMAT_XRGB1555:
14500 if (INTEL_GEN(dev_priv) > 3) {
14501 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14502 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14503 goto err;
14504 }
14505 break;
14506 case DRM_FORMAT_ABGR8888:
14507 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14508 INTEL_GEN(dev_priv) < 9) {
14509 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14510 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14511 goto err;
14512 }
14513 break;
14514 case DRM_FORMAT_XBGR8888:
14515 case DRM_FORMAT_XRGB2101010:
14516 case DRM_FORMAT_XBGR2101010:
14517 if (INTEL_GEN(dev_priv) < 4) {
14518 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14519 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14520 goto err;
14521 }
14522 break;
14523 case DRM_FORMAT_ABGR2101010:
14524 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14525 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14526 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14527 goto err;
14528 }
14529 break;
14530 case DRM_FORMAT_YUYV:
14531 case DRM_FORMAT_UYVY:
14532 case DRM_FORMAT_YVYU:
14533 case DRM_FORMAT_VYUY:
14534 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14535 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14536 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14537 goto err;
14538 }
14539 break;
14540 default:
14541 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14542 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14543 goto err;
14544 }
14545
14546 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14547 if (mode_cmd->offsets[0] != 0)
14548 goto err;
14549
14550 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14551 &intel_fb->base, mode_cmd);
14552
14553 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14554 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14555 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14556 mode_cmd->pitches[0], stride_alignment);
14557 goto err;
14558 }
14559
14560 intel_fb->obj = obj;
14561
14562 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14563 if (ret)
14564 goto err;
14565
14566 ret = drm_framebuffer_init(obj->base.dev,
14567 &intel_fb->base,
14568 &intel_fb_funcs);
14569 if (ret) {
14570 DRM_ERROR("framebuffer init failed %d\n", ret);
14571 goto err;
14572 }
14573
14574 return 0;
14575
14576 err:
14577 i915_gem_object_lock(obj);
14578 obj->framebuffer_references--;
14579 i915_gem_object_unlock(obj);
14580 return ret;
14581 }
14582
14583 static struct drm_framebuffer *
14584 intel_user_framebuffer_create(struct drm_device *dev,
14585 struct drm_file *filp,
14586 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14587 {
14588 struct drm_framebuffer *fb;
14589 struct drm_i915_gem_object *obj;
14590 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14591
14592 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14593 if (!obj)
14594 return ERR_PTR(-ENOENT);
14595
14596 fb = intel_framebuffer_create(obj, &mode_cmd);
14597 if (IS_ERR(fb))
14598 i915_gem_object_put(obj);
14599
14600 return fb;
14601 }
14602
14603 static void intel_atomic_state_free(struct drm_atomic_state *state)
14604 {
14605 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14606
14607 drm_atomic_state_default_release(state);
14608
14609 i915_sw_fence_fini(&intel_state->commit_ready);
14610
14611 kfree(state);
14612 }
14613
14614 static const struct drm_mode_config_funcs intel_mode_funcs = {
14615 .fb_create = intel_user_framebuffer_create,
14616 .output_poll_changed = intel_fbdev_output_poll_changed,
14617 .atomic_check = intel_atomic_check,
14618 .atomic_commit = intel_atomic_commit,
14619 .atomic_state_alloc = intel_atomic_state_alloc,
14620 .atomic_state_clear = intel_atomic_state_clear,
14621 .atomic_state_free = intel_atomic_state_free,
14622 };
14623
14624 /**
14625 * intel_init_display_hooks - initialize the display modesetting hooks
14626 * @dev_priv: device private
14627 */
14628 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14629 {
14630 intel_init_cdclk_hooks(dev_priv);
14631
14632 if (INTEL_INFO(dev_priv)->gen >= 9) {
14633 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14634 dev_priv->display.get_initial_plane_config =
14635 skylake_get_initial_plane_config;
14636 dev_priv->display.crtc_compute_clock =
14637 haswell_crtc_compute_clock;
14638 dev_priv->display.crtc_enable = haswell_crtc_enable;
14639 dev_priv->display.crtc_disable = haswell_crtc_disable;
14640 } else if (HAS_DDI(dev_priv)) {
14641 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14642 dev_priv->display.get_initial_plane_config =
14643 ironlake_get_initial_plane_config;
14644 dev_priv->display.crtc_compute_clock =
14645 haswell_crtc_compute_clock;
14646 dev_priv->display.crtc_enable = haswell_crtc_enable;
14647 dev_priv->display.crtc_disable = haswell_crtc_disable;
14648 } else if (HAS_PCH_SPLIT(dev_priv)) {
14649 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14650 dev_priv->display.get_initial_plane_config =
14651 ironlake_get_initial_plane_config;
14652 dev_priv->display.crtc_compute_clock =
14653 ironlake_crtc_compute_clock;
14654 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14655 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14656 } else if (IS_CHERRYVIEW(dev_priv)) {
14657 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14658 dev_priv->display.get_initial_plane_config =
14659 i9xx_get_initial_plane_config;
14660 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14661 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14662 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14663 } else if (IS_VALLEYVIEW(dev_priv)) {
14664 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14665 dev_priv->display.get_initial_plane_config =
14666 i9xx_get_initial_plane_config;
14667 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14668 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14669 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14670 } else if (IS_G4X(dev_priv)) {
14671 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14672 dev_priv->display.get_initial_plane_config =
14673 i9xx_get_initial_plane_config;
14674 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14675 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14676 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14677 } else if (IS_PINEVIEW(dev_priv)) {
14678 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14679 dev_priv->display.get_initial_plane_config =
14680 i9xx_get_initial_plane_config;
14681 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14682 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14683 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14684 } else if (!IS_GEN2(dev_priv)) {
14685 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14686 dev_priv->display.get_initial_plane_config =
14687 i9xx_get_initial_plane_config;
14688 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14689 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14690 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14691 } else {
14692 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14693 dev_priv->display.get_initial_plane_config =
14694 i9xx_get_initial_plane_config;
14695 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14696 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14697 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14698 }
14699
14700 if (IS_GEN5(dev_priv)) {
14701 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14702 } else if (IS_GEN6(dev_priv)) {
14703 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14704 } else if (IS_IVYBRIDGE(dev_priv)) {
14705 /* FIXME: detect B0+ stepping and use auto training */
14706 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14707 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14708 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14709 }
14710
14711 if (dev_priv->info.gen >= 9)
14712 dev_priv->display.update_crtcs = skl_update_crtcs;
14713 else
14714 dev_priv->display.update_crtcs = intel_update_crtcs;
14715
14716 switch (INTEL_INFO(dev_priv)->gen) {
14717 case 2:
14718 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14719 break;
14720
14721 case 3:
14722 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14723 break;
14724
14725 case 4:
14726 case 5:
14727 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14728 break;
14729
14730 case 6:
14731 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14732 break;
14733 case 7:
14734 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14735 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14736 break;
14737 case 9:
14738 /* Drop through - unsupported since execlist only. */
14739 default:
14740 /* Default just returns -ENODEV to indicate unsupported */
14741 dev_priv->display.queue_flip = intel_default_queue_flip;
14742 }
14743 }
14744
14745 /*
14746 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14747 */
14748 static void quirk_ssc_force_disable(struct drm_device *dev)
14749 {
14750 struct drm_i915_private *dev_priv = to_i915(dev);
14751 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14752 DRM_INFO("applying lvds SSC disable quirk\n");
14753 }
14754
14755 /*
14756 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14757 * brightness value
14758 */
14759 static void quirk_invert_brightness(struct drm_device *dev)
14760 {
14761 struct drm_i915_private *dev_priv = to_i915(dev);
14762 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14763 DRM_INFO("applying inverted panel brightness quirk\n");
14764 }
14765
14766 /* Some VBT's incorrectly indicate no backlight is present */
14767 static void quirk_backlight_present(struct drm_device *dev)
14768 {
14769 struct drm_i915_private *dev_priv = to_i915(dev);
14770 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14771 DRM_INFO("applying backlight present quirk\n");
14772 }
14773
14774 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14775 * which is 300 ms greater than eDP spec T12 min.
14776 */
14777 static void quirk_increase_t12_delay(struct drm_device *dev)
14778 {
14779 struct drm_i915_private *dev_priv = to_i915(dev);
14780
14781 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14782 DRM_INFO("Applying T12 delay quirk\n");
14783 }
14784
14785 struct intel_quirk {
14786 int device;
14787 int subsystem_vendor;
14788 int subsystem_device;
14789 void (*hook)(struct drm_device *dev);
14790 };
14791
14792 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14793 struct intel_dmi_quirk {
14794 void (*hook)(struct drm_device *dev);
14795 const struct dmi_system_id (*dmi_id_list)[];
14796 };
14797
14798 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14799 {
14800 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14801 return 1;
14802 }
14803
14804 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14805 {
14806 .dmi_id_list = &(const struct dmi_system_id[]) {
14807 {
14808 .callback = intel_dmi_reverse_brightness,
14809 .ident = "NCR Corporation",
14810 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14811 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14812 },
14813 },
14814 { } /* terminating entry */
14815 },
14816 .hook = quirk_invert_brightness,
14817 },
14818 };
14819
14820 static struct intel_quirk intel_quirks[] = {
14821 /* Lenovo U160 cannot use SSC on LVDS */
14822 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14823
14824 /* Sony Vaio Y cannot use SSC on LVDS */
14825 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14826
14827 /* Acer Aspire 5734Z must invert backlight brightness */
14828 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14829
14830 /* Acer/eMachines G725 */
14831 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14832
14833 /* Acer/eMachines e725 */
14834 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14835
14836 /* Acer/Packard Bell NCL20 */
14837 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14838
14839 /* Acer Aspire 4736Z */
14840 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14841
14842 /* Acer Aspire 5336 */
14843 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14844
14845 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14846 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14847
14848 /* Acer C720 Chromebook (Core i3 4005U) */
14849 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14850
14851 /* Apple Macbook 2,1 (Core 2 T7400) */
14852 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14853
14854 /* Apple Macbook 4,1 */
14855 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14856
14857 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14858 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14859
14860 /* HP Chromebook 14 (Celeron 2955U) */
14861 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14862
14863 /* Dell Chromebook 11 */
14864 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14865
14866 /* Dell Chromebook 11 (2015 version) */
14867 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14868
14869 /* Toshiba Satellite P50-C-18C */
14870 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14871 };
14872
14873 static void intel_init_quirks(struct drm_device *dev)
14874 {
14875 struct pci_dev *d = dev->pdev;
14876 int i;
14877
14878 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14879 struct intel_quirk *q = &intel_quirks[i];
14880
14881 if (d->device == q->device &&
14882 (d->subsystem_vendor == q->subsystem_vendor ||
14883 q->subsystem_vendor == PCI_ANY_ID) &&
14884 (d->subsystem_device == q->subsystem_device ||
14885 q->subsystem_device == PCI_ANY_ID))
14886 q->hook(dev);
14887 }
14888 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14889 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14890 intel_dmi_quirks[i].hook(dev);
14891 }
14892 }
14893
14894 /* Disable the VGA plane that we never use */
14895 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14896 {
14897 struct pci_dev *pdev = dev_priv->drm.pdev;
14898 u8 sr1;
14899 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14900
14901 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14902 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14903 outb(SR01, VGA_SR_INDEX);
14904 sr1 = inb(VGA_SR_DATA);
14905 outb(sr1 | 1<<5, VGA_SR_DATA);
14906 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14907 udelay(300);
14908
14909 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14910 POSTING_READ(vga_reg);
14911 }
14912
14913 void intel_modeset_init_hw(struct drm_device *dev)
14914 {
14915 struct drm_i915_private *dev_priv = to_i915(dev);
14916
14917 intel_update_cdclk(dev_priv);
14918 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14919
14920 intel_init_clock_gating(dev_priv);
14921 }
14922
14923 /*
14924 * Calculate what we think the watermarks should be for the state we've read
14925 * out of the hardware and then immediately program those watermarks so that
14926 * we ensure the hardware settings match our internal state.
14927 *
14928 * We can calculate what we think WM's should be by creating a duplicate of the
14929 * current state (which was constructed during hardware readout) and running it
14930 * through the atomic check code to calculate new watermark values in the
14931 * state object.
14932 */
14933 static void sanitize_watermarks(struct drm_device *dev)
14934 {
14935 struct drm_i915_private *dev_priv = to_i915(dev);
14936 struct drm_atomic_state *state;
14937 struct intel_atomic_state *intel_state;
14938 struct drm_crtc *crtc;
14939 struct drm_crtc_state *cstate;
14940 struct drm_modeset_acquire_ctx ctx;
14941 int ret;
14942 int i;
14943
14944 /* Only supported on platforms that use atomic watermark design */
14945 if (!dev_priv->display.optimize_watermarks)
14946 return;
14947
14948 /*
14949 * We need to hold connection_mutex before calling duplicate_state so
14950 * that the connector loop is protected.
14951 */
14952 drm_modeset_acquire_init(&ctx, 0);
14953 retry:
14954 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14955 if (ret == -EDEADLK) {
14956 drm_modeset_backoff(&ctx);
14957 goto retry;
14958 } else if (WARN_ON(ret)) {
14959 goto fail;
14960 }
14961
14962 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14963 if (WARN_ON(IS_ERR(state)))
14964 goto fail;
14965
14966 intel_state = to_intel_atomic_state(state);
14967
14968 /*
14969 * Hardware readout is the only time we don't want to calculate
14970 * intermediate watermarks (since we don't trust the current
14971 * watermarks).
14972 */
14973 if (!HAS_GMCH_DISPLAY(dev_priv))
14974 intel_state->skip_intermediate_wm = true;
14975
14976 ret = intel_atomic_check(dev, state);
14977 if (ret) {
14978 /*
14979 * If we fail here, it means that the hardware appears to be
14980 * programmed in a way that shouldn't be possible, given our
14981 * understanding of watermark requirements. This might mean a
14982 * mistake in the hardware readout code or a mistake in the
14983 * watermark calculations for a given platform. Raise a WARN
14984 * so that this is noticeable.
14985 *
14986 * If this actually happens, we'll have to just leave the
14987 * BIOS-programmed watermarks untouched and hope for the best.
14988 */
14989 WARN(true, "Could not determine valid watermarks for inherited state\n");
14990 goto put_state;
14991 }
14992
14993 /* Write calculated watermark values back */
14994 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14995 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14996
14997 cs->wm.need_postvbl_update = true;
14998 dev_priv->display.optimize_watermarks(intel_state, cs);
14999 }
15000
15001 put_state:
15002 drm_atomic_state_put(state);
15003 fail:
15004 drm_modeset_drop_locks(&ctx);
15005 drm_modeset_acquire_fini(&ctx);
15006 }
15007
15008 int intel_modeset_init(struct drm_device *dev)
15009 {
15010 struct drm_i915_private *dev_priv = to_i915(dev);
15011 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15012 enum pipe pipe;
15013 struct intel_crtc *crtc;
15014
15015 drm_mode_config_init(dev);
15016
15017 dev->mode_config.min_width = 0;
15018 dev->mode_config.min_height = 0;
15019
15020 dev->mode_config.preferred_depth = 24;
15021 dev->mode_config.prefer_shadow = 1;
15022
15023 dev->mode_config.allow_fb_modifiers = true;
15024
15025 dev->mode_config.funcs = &intel_mode_funcs;
15026
15027 init_llist_head(&dev_priv->atomic_helper.free_list);
15028 INIT_WORK(&dev_priv->atomic_helper.free_work,
15029 intel_atomic_helper_free_state_worker);
15030
15031 intel_init_quirks(dev);
15032
15033 intel_init_pm(dev_priv);
15034
15035 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15036 return 0;
15037
15038 /*
15039 * There may be no VBT; and if the BIOS enabled SSC we can
15040 * just keep using it to avoid unnecessary flicker. Whereas if the
15041 * BIOS isn't using it, don't assume it will work even if the VBT
15042 * indicates as much.
15043 */
15044 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15045 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15046 DREF_SSC1_ENABLE);
15047
15048 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15049 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15050 bios_lvds_use_ssc ? "en" : "dis",
15051 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15052 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15053 }
15054 }
15055
15056 if (IS_GEN2(dev_priv)) {
15057 dev->mode_config.max_width = 2048;
15058 dev->mode_config.max_height = 2048;
15059 } else if (IS_GEN3(dev_priv)) {
15060 dev->mode_config.max_width = 4096;
15061 dev->mode_config.max_height = 4096;
15062 } else {
15063 dev->mode_config.max_width = 8192;
15064 dev->mode_config.max_height = 8192;
15065 }
15066
15067 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15068 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15069 dev->mode_config.cursor_height = 1023;
15070 } else if (IS_GEN2(dev_priv)) {
15071 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15072 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15073 } else {
15074 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15075 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15076 }
15077
15078 dev->mode_config.fb_base = ggtt->mappable_base;
15079
15080 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15081 INTEL_INFO(dev_priv)->num_pipes,
15082 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15083
15084 for_each_pipe(dev_priv, pipe) {
15085 int ret;
15086
15087 ret = intel_crtc_init(dev_priv, pipe);
15088 if (ret) {
15089 drm_mode_config_cleanup(dev);
15090 return ret;
15091 }
15092 }
15093
15094 intel_shared_dpll_init(dev);
15095
15096 intel_update_czclk(dev_priv);
15097 intel_modeset_init_hw(dev);
15098
15099 if (dev_priv->max_cdclk_freq == 0)
15100 intel_update_max_cdclk(dev_priv);
15101
15102 /* Just disable it once at startup */
15103 i915_disable_vga(dev_priv);
15104 intel_setup_outputs(dev_priv);
15105
15106 drm_modeset_lock_all(dev);
15107 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15108 drm_modeset_unlock_all(dev);
15109
15110 for_each_intel_crtc(dev, crtc) {
15111 struct intel_initial_plane_config plane_config = {};
15112
15113 if (!crtc->active)
15114 continue;
15115
15116 /*
15117 * Note that reserving the BIOS fb up front prevents us
15118 * from stuffing other stolen allocations like the ring
15119 * on top. This prevents some ugliness at boot time, and
15120 * can even allow for smooth boot transitions if the BIOS
15121 * fb is large enough for the active pipe configuration.
15122 */
15123 dev_priv->display.get_initial_plane_config(crtc,
15124 &plane_config);
15125
15126 /*
15127 * If the fb is shared between multiple heads, we'll
15128 * just get the first one.
15129 */
15130 intel_find_initial_plane_obj(crtc, &plane_config);
15131 }
15132
15133 /*
15134 * Make sure hardware watermarks really match the state we read out.
15135 * Note that we need to do this after reconstructing the BIOS fb's
15136 * since the watermark calculation done here will use pstate->fb.
15137 */
15138 if (!HAS_GMCH_DISPLAY(dev_priv))
15139 sanitize_watermarks(dev);
15140
15141 return 0;
15142 }
15143
15144 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15145 {
15146 /* 640x480@60Hz, ~25175 kHz */
15147 struct dpll clock = {
15148 .m1 = 18,
15149 .m2 = 7,
15150 .p1 = 13,
15151 .p2 = 4,
15152 .n = 2,
15153 };
15154 u32 dpll, fp;
15155 int i;
15156
15157 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15158
15159 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15160 pipe_name(pipe), clock.vco, clock.dot);
15161
15162 fp = i9xx_dpll_compute_fp(&clock);
15163 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15164 DPLL_VGA_MODE_DIS |
15165 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15166 PLL_P2_DIVIDE_BY_4 |
15167 PLL_REF_INPUT_DREFCLK |
15168 DPLL_VCO_ENABLE;
15169
15170 I915_WRITE(FP0(pipe), fp);
15171 I915_WRITE(FP1(pipe), fp);
15172
15173 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15174 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15175 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15176 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15177 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15178 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15179 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15180
15181 /*
15182 * Apparently we need to have VGA mode enabled prior to changing
15183 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15184 * dividers, even though the register value does change.
15185 */
15186 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15187 I915_WRITE(DPLL(pipe), dpll);
15188
15189 /* Wait for the clocks to stabilize. */
15190 POSTING_READ(DPLL(pipe));
15191 udelay(150);
15192
15193 /* The pixel multiplier can only be updated once the
15194 * DPLL is enabled and the clocks are stable.
15195 *
15196 * So write it again.
15197 */
15198 I915_WRITE(DPLL(pipe), dpll);
15199
15200 /* We do this three times for luck */
15201 for (i = 0; i < 3 ; i++) {
15202 I915_WRITE(DPLL(pipe), dpll);
15203 POSTING_READ(DPLL(pipe));
15204 udelay(150); /* wait for warmup */
15205 }
15206
15207 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15208 POSTING_READ(PIPECONF(pipe));
15209 }
15210
15211 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15212 {
15213 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15214 pipe_name(pipe));
15215
15216 assert_plane_disabled(dev_priv, PLANE_A);
15217 assert_plane_disabled(dev_priv, PLANE_B);
15218
15219 I915_WRITE(PIPECONF(pipe), 0);
15220 POSTING_READ(PIPECONF(pipe));
15221
15222 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
15223 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
15224
15225 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15226 POSTING_READ(DPLL(pipe));
15227 }
15228
15229 static bool
15230 intel_check_plane_mapping(struct intel_crtc *crtc)
15231 {
15232 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15233 u32 val;
15234
15235 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15236 return true;
15237
15238 val = I915_READ(DSPCNTR(!crtc->plane));
15239
15240 if ((val & DISPLAY_PLANE_ENABLE) &&
15241 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15242 return false;
15243
15244 return true;
15245 }
15246
15247 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15248 {
15249 struct drm_device *dev = crtc->base.dev;
15250 struct intel_encoder *encoder;
15251
15252 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15253 return true;
15254
15255 return false;
15256 }
15257
15258 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15259 {
15260 struct drm_device *dev = encoder->base.dev;
15261 struct intel_connector *connector;
15262
15263 for_each_connector_on_encoder(dev, &encoder->base, connector)
15264 return connector;
15265
15266 return NULL;
15267 }
15268
15269 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15270 enum transcoder pch_transcoder)
15271 {
15272 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15273 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15274 }
15275
15276 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15277 struct drm_modeset_acquire_ctx *ctx)
15278 {
15279 struct drm_device *dev = crtc->base.dev;
15280 struct drm_i915_private *dev_priv = to_i915(dev);
15281 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15282
15283 /* Clear any frame start delays used for debugging left by the BIOS */
15284 if (!transcoder_is_dsi(cpu_transcoder)) {
15285 i915_reg_t reg = PIPECONF(cpu_transcoder);
15286
15287 I915_WRITE(reg,
15288 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15289 }
15290
15291 /* restore vblank interrupts to correct state */
15292 drm_crtc_vblank_reset(&crtc->base);
15293 if (crtc->active) {
15294 struct intel_plane *plane;
15295
15296 drm_crtc_vblank_on(&crtc->base);
15297
15298 /* Disable everything but the primary plane */
15299 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15300 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15301 continue;
15302
15303 trace_intel_disable_plane(&plane->base, crtc);
15304 plane->disable_plane(plane, crtc);
15305 }
15306 }
15307
15308 /* We need to sanitize the plane -> pipe mapping first because this will
15309 * disable the crtc (and hence change the state) if it is wrong. Note
15310 * that gen4+ has a fixed plane -> pipe mapping. */
15311 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15312 bool plane;
15313
15314 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15315 crtc->base.base.id, crtc->base.name);
15316
15317 /* Pipe has the wrong plane attached and the plane is active.
15318 * Temporarily change the plane mapping and disable everything
15319 * ... */
15320 plane = crtc->plane;
15321 crtc->base.primary->state->visible = true;
15322 crtc->plane = !plane;
15323 intel_crtc_disable_noatomic(&crtc->base, ctx);
15324 crtc->plane = plane;
15325 }
15326
15327 /* Adjust the state of the output pipe according to whether we
15328 * have active connectors/encoders. */
15329 if (crtc->active && !intel_crtc_has_encoders(crtc))
15330 intel_crtc_disable_noatomic(&crtc->base, ctx);
15331
15332 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15333 /*
15334 * We start out with underrun reporting disabled to avoid races.
15335 * For correct bookkeeping mark this on active crtcs.
15336 *
15337 * Also on gmch platforms we dont have any hardware bits to
15338 * disable the underrun reporting. Which means we need to start
15339 * out with underrun reporting disabled also on inactive pipes,
15340 * since otherwise we'll complain about the garbage we read when
15341 * e.g. coming up after runtime pm.
15342 *
15343 * No protection against concurrent access is required - at
15344 * worst a fifo underrun happens which also sets this to false.
15345 */
15346 crtc->cpu_fifo_underrun_disabled = true;
15347 /*
15348 * We track the PCH trancoder underrun reporting state
15349 * within the crtc. With crtc for pipe A housing the underrun
15350 * reporting state for PCH transcoder A, crtc for pipe B housing
15351 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15352 * and marking underrun reporting as disabled for the non-existing
15353 * PCH transcoders B and C would prevent enabling the south
15354 * error interrupt (see cpt_can_enable_serr_int()).
15355 */
15356 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15357 crtc->pch_fifo_underrun_disabled = true;
15358 }
15359 }
15360
15361 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15362 {
15363 struct intel_connector *connector;
15364
15365 /* We need to check both for a crtc link (meaning that the
15366 * encoder is active and trying to read from a pipe) and the
15367 * pipe itself being active. */
15368 bool has_active_crtc = encoder->base.crtc &&
15369 to_intel_crtc(encoder->base.crtc)->active;
15370
15371 connector = intel_encoder_find_connector(encoder);
15372 if (connector && !has_active_crtc) {
15373 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15374 encoder->base.base.id,
15375 encoder->base.name);
15376
15377 /* Connector is active, but has no active pipe. This is
15378 * fallout from our resume register restoring. Disable
15379 * the encoder manually again. */
15380 if (encoder->base.crtc) {
15381 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15382
15383 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15384 encoder->base.base.id,
15385 encoder->base.name);
15386 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15387 if (encoder->post_disable)
15388 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15389 }
15390 encoder->base.crtc = NULL;
15391
15392 /* Inconsistent output/port/pipe state happens presumably due to
15393 * a bug in one of the get_hw_state functions. Or someplace else
15394 * in our code, like the register restore mess on resume. Clamp
15395 * things to off as a safer default. */
15396
15397 connector->base.dpms = DRM_MODE_DPMS_OFF;
15398 connector->base.encoder = NULL;
15399 }
15400 /* Enabled encoders without active connectors will be fixed in
15401 * the crtc fixup. */
15402 }
15403
15404 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15405 {
15406 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15407
15408 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15409 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15410 i915_disable_vga(dev_priv);
15411 }
15412 }
15413
15414 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15415 {
15416 /* This function can be called both from intel_modeset_setup_hw_state or
15417 * at a very early point in our resume sequence, where the power well
15418 * structures are not yet restored. Since this function is at a very
15419 * paranoid "someone might have enabled VGA while we were not looking"
15420 * level, just check if the power well is enabled instead of trying to
15421 * follow the "don't touch the power well if we don't need it" policy
15422 * the rest of the driver uses. */
15423 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15424 return;
15425
15426 i915_redisable_vga_power_on(dev_priv);
15427
15428 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15429 }
15430
15431 static bool primary_get_hw_state(struct intel_plane *plane)
15432 {
15433 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15434
15435 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15436 }
15437
15438 /* FIXME read out full plane state for all planes */
15439 static void readout_plane_state(struct intel_crtc *crtc)
15440 {
15441 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15442 bool visible;
15443
15444 visible = crtc->active && primary_get_hw_state(primary);
15445
15446 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15447 to_intel_plane_state(primary->base.state),
15448 visible);
15449 }
15450
15451 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15452 {
15453 struct drm_i915_private *dev_priv = to_i915(dev);
15454 enum pipe pipe;
15455 struct intel_crtc *crtc;
15456 struct intel_encoder *encoder;
15457 struct intel_connector *connector;
15458 struct drm_connector_list_iter conn_iter;
15459 int i;
15460
15461 dev_priv->active_crtcs = 0;
15462
15463 for_each_intel_crtc(dev, crtc) {
15464 struct intel_crtc_state *crtc_state =
15465 to_intel_crtc_state(crtc->base.state);
15466
15467 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15468 memset(crtc_state, 0, sizeof(*crtc_state));
15469 crtc_state->base.crtc = &crtc->base;
15470
15471 crtc_state->base.active = crtc_state->base.enable =
15472 dev_priv->display.get_pipe_config(crtc, crtc_state);
15473
15474 crtc->base.enabled = crtc_state->base.enable;
15475 crtc->active = crtc_state->base.active;
15476
15477 if (crtc_state->base.active)
15478 dev_priv->active_crtcs |= 1 << crtc->pipe;
15479
15480 readout_plane_state(crtc);
15481
15482 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15483 crtc->base.base.id, crtc->base.name,
15484 enableddisabled(crtc_state->base.active));
15485 }
15486
15487 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15488 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15489
15490 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15491 &pll->state.hw_state);
15492 pll->state.crtc_mask = 0;
15493 for_each_intel_crtc(dev, crtc) {
15494 struct intel_crtc_state *crtc_state =
15495 to_intel_crtc_state(crtc->base.state);
15496
15497 if (crtc_state->base.active &&
15498 crtc_state->shared_dpll == pll)
15499 pll->state.crtc_mask |= 1 << crtc->pipe;
15500 }
15501 pll->active_mask = pll->state.crtc_mask;
15502
15503 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15504 pll->name, pll->state.crtc_mask, pll->on);
15505 }
15506
15507 for_each_intel_encoder(dev, encoder) {
15508 pipe = 0;
15509
15510 if (encoder->get_hw_state(encoder, &pipe)) {
15511 struct intel_crtc_state *crtc_state;
15512
15513 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15514 crtc_state = to_intel_crtc_state(crtc->base.state);
15515
15516 encoder->base.crtc = &crtc->base;
15517 crtc_state->output_types |= 1 << encoder->type;
15518 encoder->get_config(encoder, crtc_state);
15519 } else {
15520 encoder->base.crtc = NULL;
15521 }
15522
15523 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15524 encoder->base.base.id, encoder->base.name,
15525 enableddisabled(encoder->base.crtc),
15526 pipe_name(pipe));
15527 }
15528
15529 drm_connector_list_iter_begin(dev, &conn_iter);
15530 for_each_intel_connector_iter(connector, &conn_iter) {
15531 if (connector->get_hw_state(connector)) {
15532 connector->base.dpms = DRM_MODE_DPMS_ON;
15533
15534 encoder = connector->encoder;
15535 connector->base.encoder = &encoder->base;
15536
15537 if (encoder->base.crtc &&
15538 encoder->base.crtc->state->active) {
15539 /*
15540 * This has to be done during hardware readout
15541 * because anything calling .crtc_disable may
15542 * rely on the connector_mask being accurate.
15543 */
15544 encoder->base.crtc->state->connector_mask |=
15545 1 << drm_connector_index(&connector->base);
15546 encoder->base.crtc->state->encoder_mask |=
15547 1 << drm_encoder_index(&encoder->base);
15548 }
15549
15550 } else {
15551 connector->base.dpms = DRM_MODE_DPMS_OFF;
15552 connector->base.encoder = NULL;
15553 }
15554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15555 connector->base.base.id, connector->base.name,
15556 enableddisabled(connector->base.encoder));
15557 }
15558 drm_connector_list_iter_end(&conn_iter);
15559
15560 for_each_intel_crtc(dev, crtc) {
15561 struct intel_crtc_state *crtc_state =
15562 to_intel_crtc_state(crtc->base.state);
15563 int pixclk = 0;
15564
15565 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15566 if (crtc_state->base.active) {
15567 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15568 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15569 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15570
15571 /*
15572 * The initial mode needs to be set in order to keep
15573 * the atomic core happy. It wants a valid mode if the
15574 * crtc's enabled, so we do the above call.
15575 *
15576 * But we don't set all the derived state fully, hence
15577 * set a flag to indicate that a full recalculation is
15578 * needed on the next commit.
15579 */
15580 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15581
15582 intel_crtc_compute_pixel_rate(crtc_state);
15583
15584 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15585 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15586 pixclk = crtc_state->pixel_rate;
15587 else
15588 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15589
15590 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15591 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15592 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15593
15594 drm_calc_timestamping_constants(&crtc->base,
15595 &crtc_state->base.adjusted_mode);
15596 update_scanline_offset(crtc);
15597 }
15598
15599 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15600
15601 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15602 }
15603 }
15604
15605 static void
15606 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15607 {
15608 struct intel_encoder *encoder;
15609
15610 for_each_intel_encoder(&dev_priv->drm, encoder) {
15611 u64 get_domains;
15612 enum intel_display_power_domain domain;
15613
15614 if (!encoder->get_power_domains)
15615 continue;
15616
15617 get_domains = encoder->get_power_domains(encoder);
15618 for_each_power_domain(domain, get_domains)
15619 intel_display_power_get(dev_priv, domain);
15620 }
15621 }
15622
15623 /* Scan out the current hw modeset state,
15624 * and sanitizes it to the current state
15625 */
15626 static void
15627 intel_modeset_setup_hw_state(struct drm_device *dev,
15628 struct drm_modeset_acquire_ctx *ctx)
15629 {
15630 struct drm_i915_private *dev_priv = to_i915(dev);
15631 enum pipe pipe;
15632 struct intel_crtc *crtc;
15633 struct intel_encoder *encoder;
15634 int i;
15635
15636 intel_modeset_readout_hw_state(dev);
15637
15638 /* HW state is read out, now we need to sanitize this mess. */
15639 get_encoder_power_domains(dev_priv);
15640
15641 for_each_intel_encoder(dev, encoder) {
15642 intel_sanitize_encoder(encoder);
15643 }
15644
15645 for_each_pipe(dev_priv, pipe) {
15646 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15647
15648 intel_sanitize_crtc(crtc, ctx);
15649 intel_dump_pipe_config(crtc, crtc->config,
15650 "[setup_hw_state]");
15651 }
15652
15653 intel_modeset_update_connector_atomic_state(dev);
15654
15655 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15656 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15657
15658 if (!pll->on || pll->active_mask)
15659 continue;
15660
15661 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15662
15663 pll->funcs.disable(dev_priv, pll);
15664 pll->on = false;
15665 }
15666
15667 if (IS_G4X(dev_priv)) {
15668 g4x_wm_get_hw_state(dev);
15669 g4x_wm_sanitize(dev_priv);
15670 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15671 vlv_wm_get_hw_state(dev);
15672 vlv_wm_sanitize(dev_priv);
15673 } else if (IS_GEN9(dev_priv)) {
15674 skl_wm_get_hw_state(dev);
15675 } else if (HAS_PCH_SPLIT(dev_priv)) {
15676 ilk_wm_get_hw_state(dev);
15677 }
15678
15679 for_each_intel_crtc(dev, crtc) {
15680 u64 put_domains;
15681
15682 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15683 if (WARN_ON(put_domains))
15684 modeset_put_power_domains(dev_priv, put_domains);
15685 }
15686 intel_display_set_init_power(dev_priv, false);
15687
15688 intel_power_domains_verify_state(dev_priv);
15689
15690 intel_fbc_init_pipe_state(dev_priv);
15691 }
15692
15693 void intel_display_resume(struct drm_device *dev)
15694 {
15695 struct drm_i915_private *dev_priv = to_i915(dev);
15696 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15697 struct drm_modeset_acquire_ctx ctx;
15698 int ret;
15699
15700 dev_priv->modeset_restore_state = NULL;
15701 if (state)
15702 state->acquire_ctx = &ctx;
15703
15704 drm_modeset_acquire_init(&ctx, 0);
15705
15706 while (1) {
15707 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15708 if (ret != -EDEADLK)
15709 break;
15710
15711 drm_modeset_backoff(&ctx);
15712 }
15713
15714 if (!ret)
15715 ret = __intel_display_resume(dev, state, &ctx);
15716
15717 drm_modeset_drop_locks(&ctx);
15718 drm_modeset_acquire_fini(&ctx);
15719
15720 if (ret)
15721 DRM_ERROR("Restoring old state failed with %i\n", ret);
15722 if (state)
15723 drm_atomic_state_put(state);
15724 }
15725
15726 void intel_modeset_gem_init(struct drm_device *dev)
15727 {
15728 struct drm_i915_private *dev_priv = to_i915(dev);
15729
15730 intel_init_gt_powersave(dev_priv);
15731
15732 intel_setup_overlay(dev_priv);
15733 }
15734
15735 int intel_connector_register(struct drm_connector *connector)
15736 {
15737 struct intel_connector *intel_connector = to_intel_connector(connector);
15738 int ret;
15739
15740 ret = intel_backlight_device_register(intel_connector);
15741 if (ret)
15742 goto err;
15743
15744 return 0;
15745
15746 err:
15747 return ret;
15748 }
15749
15750 void intel_connector_unregister(struct drm_connector *connector)
15751 {
15752 struct intel_connector *intel_connector = to_intel_connector(connector);
15753
15754 intel_backlight_device_unregister(intel_connector);
15755 intel_panel_destroy_backlight(connector);
15756 }
15757
15758 void intel_modeset_cleanup(struct drm_device *dev)
15759 {
15760 struct drm_i915_private *dev_priv = to_i915(dev);
15761
15762 flush_work(&dev_priv->atomic_helper.free_work);
15763 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15764
15765 intel_disable_gt_powersave(dev_priv);
15766
15767 /*
15768 * Interrupts and polling as the first thing to avoid creating havoc.
15769 * Too much stuff here (turning of connectors, ...) would
15770 * experience fancy races otherwise.
15771 */
15772 intel_irq_uninstall(dev_priv);
15773
15774 /*
15775 * Due to the hpd irq storm handling the hotplug work can re-arm the
15776 * poll handlers. Hence disable polling after hpd handling is shut down.
15777 */
15778 drm_kms_helper_poll_fini(dev);
15779
15780 intel_unregister_dsm_handler();
15781
15782 intel_fbc_global_disable(dev_priv);
15783
15784 /* flush any delayed tasks or pending work */
15785 flush_scheduled_work();
15786
15787 drm_mode_config_cleanup(dev);
15788
15789 intel_cleanup_overlay(dev_priv);
15790
15791 intel_cleanup_gt_powersave(dev_priv);
15792
15793 intel_teardown_gmbus(dev_priv);
15794 }
15795
15796 void intel_connector_attach_encoder(struct intel_connector *connector,
15797 struct intel_encoder *encoder)
15798 {
15799 connector->encoder = encoder;
15800 drm_mode_connector_attach_encoder(&connector->base,
15801 &encoder->base);
15802 }
15803
15804 /*
15805 * set vga decode state - true == enable VGA decode
15806 */
15807 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15808 {
15809 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15810 u16 gmch_ctrl;
15811
15812 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15813 DRM_ERROR("failed to read control word\n");
15814 return -EIO;
15815 }
15816
15817 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15818 return 0;
15819
15820 if (state)
15821 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15822 else
15823 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15824
15825 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15826 DRM_ERROR("failed to write control word\n");
15827 return -EIO;
15828 }
15829
15830 return 0;
15831 }
15832
15833 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15834
15835 struct intel_display_error_state {
15836
15837 u32 power_well_driver;
15838
15839 int num_transcoders;
15840
15841 struct intel_cursor_error_state {
15842 u32 control;
15843 u32 position;
15844 u32 base;
15845 u32 size;
15846 } cursor[I915_MAX_PIPES];
15847
15848 struct intel_pipe_error_state {
15849 bool power_domain_on;
15850 u32 source;
15851 u32 stat;
15852 } pipe[I915_MAX_PIPES];
15853
15854 struct intel_plane_error_state {
15855 u32 control;
15856 u32 stride;
15857 u32 size;
15858 u32 pos;
15859 u32 addr;
15860 u32 surface;
15861 u32 tile_offset;
15862 } plane[I915_MAX_PIPES];
15863
15864 struct intel_transcoder_error_state {
15865 bool power_domain_on;
15866 enum transcoder cpu_transcoder;
15867
15868 u32 conf;
15869
15870 u32 htotal;
15871 u32 hblank;
15872 u32 hsync;
15873 u32 vtotal;
15874 u32 vblank;
15875 u32 vsync;
15876 } transcoder[4];
15877 };
15878
15879 struct intel_display_error_state *
15880 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15881 {
15882 struct intel_display_error_state *error;
15883 int transcoders[] = {
15884 TRANSCODER_A,
15885 TRANSCODER_B,
15886 TRANSCODER_C,
15887 TRANSCODER_EDP,
15888 };
15889 int i;
15890
15891 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15892 return NULL;
15893
15894 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15895 if (error == NULL)
15896 return NULL;
15897
15898 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15899 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15900
15901 for_each_pipe(dev_priv, i) {
15902 error->pipe[i].power_domain_on =
15903 __intel_display_power_is_enabled(dev_priv,
15904 POWER_DOMAIN_PIPE(i));
15905 if (!error->pipe[i].power_domain_on)
15906 continue;
15907
15908 error->cursor[i].control = I915_READ(CURCNTR(i));
15909 error->cursor[i].position = I915_READ(CURPOS(i));
15910 error->cursor[i].base = I915_READ(CURBASE(i));
15911
15912 error->plane[i].control = I915_READ(DSPCNTR(i));
15913 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15914 if (INTEL_GEN(dev_priv) <= 3) {
15915 error->plane[i].size = I915_READ(DSPSIZE(i));
15916 error->plane[i].pos = I915_READ(DSPPOS(i));
15917 }
15918 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15919 error->plane[i].addr = I915_READ(DSPADDR(i));
15920 if (INTEL_GEN(dev_priv) >= 4) {
15921 error->plane[i].surface = I915_READ(DSPSURF(i));
15922 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15923 }
15924
15925 error->pipe[i].source = I915_READ(PIPESRC(i));
15926
15927 if (HAS_GMCH_DISPLAY(dev_priv))
15928 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15929 }
15930
15931 /* Note: this does not include DSI transcoders. */
15932 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15933 if (HAS_DDI(dev_priv))
15934 error->num_transcoders++; /* Account for eDP. */
15935
15936 for (i = 0; i < error->num_transcoders; i++) {
15937 enum transcoder cpu_transcoder = transcoders[i];
15938
15939 error->transcoder[i].power_domain_on =
15940 __intel_display_power_is_enabled(dev_priv,
15941 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15942 if (!error->transcoder[i].power_domain_on)
15943 continue;
15944
15945 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15946
15947 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15948 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15949 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15950 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15951 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15952 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15953 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15954 }
15955
15956 return error;
15957 }
15958
15959 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15960
15961 void
15962 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15963 struct intel_display_error_state *error)
15964 {
15965 struct drm_i915_private *dev_priv = m->i915;
15966 int i;
15967
15968 if (!error)
15969 return;
15970
15971 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15972 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15973 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15974 error->power_well_driver);
15975 for_each_pipe(dev_priv, i) {
15976 err_printf(m, "Pipe [%d]:\n", i);
15977 err_printf(m, " Power: %s\n",
15978 onoff(error->pipe[i].power_domain_on));
15979 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15980 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15981
15982 err_printf(m, "Plane [%d]:\n", i);
15983 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15984 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15985 if (INTEL_GEN(dev_priv) <= 3) {
15986 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15987 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15988 }
15989 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15990 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15991 if (INTEL_GEN(dev_priv) >= 4) {
15992 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15993 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15994 }
15995
15996 err_printf(m, "Cursor [%d]:\n", i);
15997 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15998 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15999 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16000 }
16001
16002 for (i = 0; i < error->num_transcoders; i++) {
16003 err_printf(m, "CPU transcoder: %s\n",
16004 transcoder_name(error->transcoder[i].cpu_transcoder));
16005 err_printf(m, " Power: %s\n",
16006 onoff(error->transcoder[i].power_domain_on));
16007 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16008 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16009 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16010 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16011 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16012 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16013 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16014 }
16015 }
16016
16017 #endif
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