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drm/i915: Don't expose ARGB1555 on gen2/3
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 DRM_FORMAT_ARGB8888,
55 };
56
57 /* Primary plane formats for gen >= 4 */
58 static const uint32_t i965_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB8888,
62 DRM_FORMAT_XBGR8888,
63 DRM_FORMAT_ARGB8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 /* Cursor formats */
70 static const uint32_t intel_cursor_formats[] = {
71 DRM_FORMAT_ARGB8888,
72 };
73
74 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
75
76 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
77 struct intel_crtc_state *pipe_config);
78 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_state *pipe_config);
80
81 static int intel_set_mode(struct drm_crtc *crtc,
82 struct drm_atomic_state *state);
83 static int intel_framebuffer_init(struct drm_device *dev,
84 struct intel_framebuffer *ifb,
85 struct drm_mode_fb_cmd2 *mode_cmd,
86 struct drm_i915_gem_object *obj);
87 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
88 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
89 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
90 struct intel_link_m_n *m_n,
91 struct intel_link_m_n *m2_n2);
92 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
93 static void haswell_set_pipeconf(struct drm_crtc *crtc);
94 static void intel_set_pipe_csc(struct drm_crtc *crtc);
95 static void vlv_prepare_pll(struct intel_crtc *crtc,
96 const struct intel_crtc_state *pipe_config);
97 static void chv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_state *pipe_config);
99 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
100 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
101 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
102 struct intel_crtc_state *crtc_state);
103 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
104 int num_connectors);
105 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
106 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
107
108 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
109 {
110 if (!connector->mst_port)
111 return connector->encoder;
112 else
113 return &connector->mst_port->mst_encoders[pipe]->base;
114 }
115
116 typedef struct {
117 int min, max;
118 } intel_range_t;
119
120 typedef struct {
121 int dot_limit;
122 int p2_slow, p2_fast;
123 } intel_p2_t;
124
125 typedef struct intel_limit intel_limit_t;
126 struct intel_limit {
127 intel_range_t dot, vco, n, m, m1, m2, p, p1;
128 intel_p2_t p2;
129 };
130
131 int
132 intel_pch_rawclk(struct drm_device *dev)
133 {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135
136 WARN_ON(!HAS_PCH_SPLIT(dev));
137
138 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
139 }
140
141 static inline u32 /* units of 100MHz */
142 intel_fdi_link_freq(struct drm_device *dev)
143 {
144 if (IS_GEN5(dev)) {
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
147 } else
148 return 27;
149 }
150
151 static const intel_limit_t intel_limits_i8xx_dac = {
152 .dot = { .min = 25000, .max = 350000 },
153 .vco = { .min = 908000, .max = 1512000 },
154 .n = { .min = 2, .max = 16 },
155 .m = { .min = 96, .max = 140 },
156 .m1 = { .min = 18, .max = 26 },
157 .m2 = { .min = 6, .max = 16 },
158 .p = { .min = 4, .max = 128 },
159 .p1 = { .min = 2, .max = 33 },
160 .p2 = { .dot_limit = 165000,
161 .p2_slow = 4, .p2_fast = 2 },
162 };
163
164 static const intel_limit_t intel_limits_i8xx_dvo = {
165 .dot = { .min = 25000, .max = 350000 },
166 .vco = { .min = 908000, .max = 1512000 },
167 .n = { .min = 2, .max = 16 },
168 .m = { .min = 96, .max = 140 },
169 .m1 = { .min = 18, .max = 26 },
170 .m2 = { .min = 6, .max = 16 },
171 .p = { .min = 4, .max = 128 },
172 .p1 = { .min = 2, .max = 33 },
173 .p2 = { .dot_limit = 165000,
174 .p2_slow = 4, .p2_fast = 4 },
175 };
176
177 static const intel_limit_t intel_limits_i8xx_lvds = {
178 .dot = { .min = 25000, .max = 350000 },
179 .vco = { .min = 908000, .max = 1512000 },
180 .n = { .min = 2, .max = 16 },
181 .m = { .min = 96, .max = 140 },
182 .m1 = { .min = 18, .max = 26 },
183 .m2 = { .min = 6, .max = 16 },
184 .p = { .min = 4, .max = 128 },
185 .p1 = { .min = 1, .max = 6 },
186 .p2 = { .dot_limit = 165000,
187 .p2_slow = 14, .p2_fast = 7 },
188 };
189
190 static const intel_limit_t intel_limits_i9xx_sdvo = {
191 .dot = { .min = 20000, .max = 400000 },
192 .vco = { .min = 1400000, .max = 2800000 },
193 .n = { .min = 1, .max = 6 },
194 .m = { .min = 70, .max = 120 },
195 .m1 = { .min = 8, .max = 18 },
196 .m2 = { .min = 3, .max = 7 },
197 .p = { .min = 5, .max = 80 },
198 .p1 = { .min = 1, .max = 8 },
199 .p2 = { .dot_limit = 200000,
200 .p2_slow = 10, .p2_fast = 5 },
201 };
202
203 static const intel_limit_t intel_limits_i9xx_lvds = {
204 .dot = { .min = 20000, .max = 400000 },
205 .vco = { .min = 1400000, .max = 2800000 },
206 .n = { .min = 1, .max = 6 },
207 .m = { .min = 70, .max = 120 },
208 .m1 = { .min = 8, .max = 18 },
209 .m2 = { .min = 3, .max = 7 },
210 .p = { .min = 7, .max = 98 },
211 .p1 = { .min = 1, .max = 8 },
212 .p2 = { .dot_limit = 112000,
213 .p2_slow = 14, .p2_fast = 7 },
214 };
215
216
217 static const intel_limit_t intel_limits_g4x_sdvo = {
218 .dot = { .min = 25000, .max = 270000 },
219 .vco = { .min = 1750000, .max = 3500000},
220 .n = { .min = 1, .max = 4 },
221 .m = { .min = 104, .max = 138 },
222 .m1 = { .min = 17, .max = 23 },
223 .m2 = { .min = 5, .max = 11 },
224 .p = { .min = 10, .max = 30 },
225 .p1 = { .min = 1, .max = 3},
226 .p2 = { .dot_limit = 270000,
227 .p2_slow = 10,
228 .p2_fast = 10
229 },
230 };
231
232 static const intel_limit_t intel_limits_g4x_hdmi = {
233 .dot = { .min = 22000, .max = 400000 },
234 .vco = { .min = 1750000, .max = 3500000},
235 .n = { .min = 1, .max = 4 },
236 .m = { .min = 104, .max = 138 },
237 .m1 = { .min = 16, .max = 23 },
238 .m2 = { .min = 5, .max = 11 },
239 .p = { .min = 5, .max = 80 },
240 .p1 = { .min = 1, .max = 8},
241 .p2 = { .dot_limit = 165000,
242 .p2_slow = 10, .p2_fast = 5 },
243 };
244
245 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
246 .dot = { .min = 20000, .max = 115000 },
247 .vco = { .min = 1750000, .max = 3500000 },
248 .n = { .min = 1, .max = 3 },
249 .m = { .min = 104, .max = 138 },
250 .m1 = { .min = 17, .max = 23 },
251 .m2 = { .min = 5, .max = 11 },
252 .p = { .min = 28, .max = 112 },
253 .p1 = { .min = 2, .max = 8 },
254 .p2 = { .dot_limit = 0,
255 .p2_slow = 14, .p2_fast = 14
256 },
257 };
258
259 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
260 .dot = { .min = 80000, .max = 224000 },
261 .vco = { .min = 1750000, .max = 3500000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 104, .max = 138 },
264 .m1 = { .min = 17, .max = 23 },
265 .m2 = { .min = 5, .max = 11 },
266 .p = { .min = 14, .max = 42 },
267 .p1 = { .min = 2, .max = 6 },
268 .p2 = { .dot_limit = 0,
269 .p2_slow = 7, .p2_fast = 7
270 },
271 };
272
273 static const intel_limit_t intel_limits_pineview_sdvo = {
274 .dot = { .min = 20000, .max = 400000},
275 .vco = { .min = 1700000, .max = 3500000 },
276 /* Pineview's Ncounter is a ring counter */
277 .n = { .min = 3, .max = 6 },
278 .m = { .min = 2, .max = 256 },
279 /* Pineview only has one combined m divider, which we treat as m2. */
280 .m1 = { .min = 0, .max = 0 },
281 .m2 = { .min = 0, .max = 254 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 200000,
285 .p2_slow = 10, .p2_fast = 5 },
286 };
287
288 static const intel_limit_t intel_limits_pineview_lvds = {
289 .dot = { .min = 20000, .max = 400000 },
290 .vco = { .min = 1700000, .max = 3500000 },
291 .n = { .min = 3, .max = 6 },
292 .m = { .min = 2, .max = 256 },
293 .m1 = { .min = 0, .max = 0 },
294 .m2 = { .min = 0, .max = 254 },
295 .p = { .min = 7, .max = 112 },
296 .p1 = { .min = 1, .max = 8 },
297 .p2 = { .dot_limit = 112000,
298 .p2_slow = 14, .p2_fast = 14 },
299 };
300
301 /* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 };
318
319 static const intel_limit_t intel_limits_ironlake_single_lvds = {
320 .dot = { .min = 25000, .max = 350000 },
321 .vco = { .min = 1760000, .max = 3510000 },
322 .n = { .min = 1, .max = 3 },
323 .m = { .min = 79, .max = 118 },
324 .m1 = { .min = 12, .max = 22 },
325 .m2 = { .min = 5, .max = 9 },
326 .p = { .min = 28, .max = 112 },
327 .p1 = { .min = 2, .max = 8 },
328 .p2 = { .dot_limit = 225000,
329 .p2_slow = 14, .p2_fast = 14 },
330 };
331
332 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
333 .dot = { .min = 25000, .max = 350000 },
334 .vco = { .min = 1760000, .max = 3510000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 79, .max = 127 },
337 .m1 = { .min = 12, .max = 22 },
338 .m2 = { .min = 5, .max = 9 },
339 .p = { .min = 14, .max = 56 },
340 .p1 = { .min = 2, .max = 8 },
341 .p2 = { .dot_limit = 225000,
342 .p2_slow = 7, .p2_fast = 7 },
343 };
344
345 /* LVDS 100mhz refclk limits. */
346 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000 },
349 .n = { .min = 1, .max = 2 },
350 .m = { .min = 79, .max = 126 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 28, .max = 112 },
354 .p1 = { .min = 2, .max = 8 },
355 .p2 = { .dot_limit = 225000,
356 .p2_slow = 14, .p2_fast = 14 },
357 };
358
359 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
360 .dot = { .min = 25000, .max = 350000 },
361 .vco = { .min = 1760000, .max = 3510000 },
362 .n = { .min = 1, .max = 3 },
363 .m = { .min = 79, .max = 126 },
364 .m1 = { .min = 12, .max = 22 },
365 .m2 = { .min = 5, .max = 9 },
366 .p = { .min = 14, .max = 42 },
367 .p1 = { .min = 2, .max = 6 },
368 .p2 = { .dot_limit = 225000,
369 .p2_slow = 7, .p2_fast = 7 },
370 };
371
372 static const intel_limit_t intel_limits_vlv = {
373 /*
374 * These are the data rate limits (measured in fast clocks)
375 * since those are the strictest limits we have. The fast
376 * clock and actual rate limits are more relaxed, so checking
377 * them would make no difference.
378 */
379 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
380 .vco = { .min = 4000000, .max = 6000000 },
381 .n = { .min = 1, .max = 7 },
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p1 = { .min = 2, .max = 3 },
385 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
386 };
387
388 static const intel_limit_t intel_limits_chv = {
389 /*
390 * These are the data rate limits (measured in fast clocks)
391 * since those are the strictest limits we have. The fast
392 * clock and actual rate limits are more relaxed, so checking
393 * them would make no difference.
394 */
395 .dot = { .min = 25000 * 5, .max = 540000 * 5},
396 .vco = { .min = 4800000, .max = 6480000 },
397 .n = { .min = 1, .max = 1 },
398 .m1 = { .min = 2, .max = 2 },
399 .m2 = { .min = 24 << 22, .max = 175 << 22 },
400 .p1 = { .min = 2, .max = 4 },
401 .p2 = { .p2_slow = 1, .p2_fast = 14 },
402 };
403
404 static const intel_limit_t intel_limits_bxt = {
405 /* FIXME: find real dot limits */
406 .dot = { .min = 0, .max = INT_MAX },
407 .vco = { .min = 4800000, .max = 6480000 },
408 .n = { .min = 1, .max = 1 },
409 .m1 = { .min = 2, .max = 2 },
410 /* FIXME: find real m2 limits */
411 .m2 = { .min = 2 << 22, .max = 255 << 22 },
412 .p1 = { .min = 2, .max = 4 },
413 .p2 = { .p2_slow = 1, .p2_fast = 20 },
414 };
415
416 static void vlv_clock(int refclk, intel_clock_t *clock)
417 {
418 clock->m = clock->m1 * clock->m2;
419 clock->p = clock->p1 * clock->p2;
420 if (WARN_ON(clock->n == 0 || clock->p == 0))
421 return;
422 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
423 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
424 }
425
426 /**
427 * Returns whether any output on the specified pipe is of the specified type
428 */
429 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
430 {
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
435 if (encoder->type == type)
436 return true;
437
438 return false;
439 }
440
441 /**
442 * Returns whether any output on the specified pipe will have the specified
443 * type after a staged modeset is complete, i.e., the same as
444 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
445 * encoder->crtc.
446 */
447 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
448 int type)
449 {
450 struct drm_atomic_state *state = crtc_state->base.state;
451 struct drm_connector *connector;
452 struct drm_connector_state *connector_state;
453 struct intel_encoder *encoder;
454 int i, num_connectors = 0;
455
456 for_each_connector_in_state(state, connector, connector_state, i) {
457 if (connector_state->crtc != crtc_state->base.crtc)
458 continue;
459
460 num_connectors++;
461
462 encoder = to_intel_encoder(connector_state->best_encoder);
463 if (encoder->type == type)
464 return true;
465 }
466
467 WARN_ON(num_connectors == 0);
468
469 return false;
470 }
471
472 static const intel_limit_t *
473 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
474 {
475 struct drm_device *dev = crtc_state->base.crtc->dev;
476 const intel_limit_t *limit;
477
478 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
479 if (intel_is_dual_link_lvds(dev)) {
480 if (refclk == 100000)
481 limit = &intel_limits_ironlake_dual_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_dual_lvds;
484 } else {
485 if (refclk == 100000)
486 limit = &intel_limits_ironlake_single_lvds_100m;
487 else
488 limit = &intel_limits_ironlake_single_lvds;
489 }
490 } else
491 limit = &intel_limits_ironlake_dac;
492
493 return limit;
494 }
495
496 static const intel_limit_t *
497 intel_g4x_limit(struct intel_crtc_state *crtc_state)
498 {
499 struct drm_device *dev = crtc_state->base.crtc->dev;
500 const intel_limit_t *limit;
501
502 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
503 if (intel_is_dual_link_lvds(dev))
504 limit = &intel_limits_g4x_dual_channel_lvds;
505 else
506 limit = &intel_limits_g4x_single_channel_lvds;
507 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
508 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
509 limit = &intel_limits_g4x_hdmi;
510 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
511 limit = &intel_limits_g4x_sdvo;
512 } else /* The option is for other outputs */
513 limit = &intel_limits_i9xx_sdvo;
514
515 return limit;
516 }
517
518 static const intel_limit_t *
519 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
520 {
521 struct drm_device *dev = crtc_state->base.crtc->dev;
522 const intel_limit_t *limit;
523
524 if (IS_BROXTON(dev))
525 limit = &intel_limits_bxt;
526 else if (HAS_PCH_SPLIT(dev))
527 limit = intel_ironlake_limit(crtc_state, refclk);
528 else if (IS_G4X(dev)) {
529 limit = intel_g4x_limit(crtc_state);
530 } else if (IS_PINEVIEW(dev)) {
531 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
532 limit = &intel_limits_pineview_lvds;
533 else
534 limit = &intel_limits_pineview_sdvo;
535 } else if (IS_CHERRYVIEW(dev)) {
536 limit = &intel_limits_chv;
537 } else if (IS_VALLEYVIEW(dev)) {
538 limit = &intel_limits_vlv;
539 } else if (!IS_GEN2(dev)) {
540 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
541 limit = &intel_limits_i9xx_lvds;
542 else
543 limit = &intel_limits_i9xx_sdvo;
544 } else {
545 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
546 limit = &intel_limits_i8xx_lvds;
547 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
548 limit = &intel_limits_i8xx_dvo;
549 else
550 limit = &intel_limits_i8xx_dac;
551 }
552 return limit;
553 }
554
555 /* m1 is reserved as 0 in Pineview, n is a ring counter */
556 static void pineview_clock(int refclk, intel_clock_t *clock)
557 {
558 clock->m = clock->m2 + 2;
559 clock->p = clock->p1 * clock->p2;
560 if (WARN_ON(clock->n == 0 || clock->p == 0))
561 return;
562 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
563 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
564 }
565
566 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
567 {
568 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
569 }
570
571 static void i9xx_clock(int refclk, intel_clock_t *clock)
572 {
573 clock->m = i9xx_dpll_compute_m(clock);
574 clock->p = clock->p1 * clock->p2;
575 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
576 return;
577 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
578 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
579 }
580
581 static void chv_clock(int refclk, intel_clock_t *clock)
582 {
583 clock->m = clock->m1 * clock->m2;
584 clock->p = clock->p1 * clock->p2;
585 if (WARN_ON(clock->n == 0 || clock->p == 0))
586 return;
587 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
588 clock->n << 22);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 }
591
592 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
593 /**
594 * Returns whether the given set of divisors are valid for a given refclk with
595 * the given connectors.
596 */
597
598 static bool intel_PLL_is_valid(struct drm_device *dev,
599 const intel_limit_t *limit,
600 const intel_clock_t *clock)
601 {
602 if (clock->n < limit->n.min || limit->n.max < clock->n)
603 INTELPllInvalid("n out of range\n");
604 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
605 INTELPllInvalid("p1 out of range\n");
606 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
607 INTELPllInvalid("m2 out of range\n");
608 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
609 INTELPllInvalid("m1 out of range\n");
610
611 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
612 if (clock->m1 <= clock->m2)
613 INTELPllInvalid("m1 <= m2\n");
614
615 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
616 if (clock->p < limit->p.min || limit->p.max < clock->p)
617 INTELPllInvalid("p out of range\n");
618 if (clock->m < limit->m.min || limit->m.max < clock->m)
619 INTELPllInvalid("m out of range\n");
620 }
621
622 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
623 INTELPllInvalid("vco out of range\n");
624 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
625 * connector, etc., rather than just a single range.
626 */
627 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
628 INTELPllInvalid("dot out of range\n");
629
630 return true;
631 }
632
633 static bool
634 i9xx_find_best_dpll(const intel_limit_t *limit,
635 struct intel_crtc_state *crtc_state,
636 int target, int refclk, intel_clock_t *match_clock,
637 intel_clock_t *best_clock)
638 {
639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
640 struct drm_device *dev = crtc->base.dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 if (clock.m2 >= clock.m1)
668 break;
669 for (clock.n = limit->n.min;
670 clock.n <= limit->n.max; clock.n++) {
671 for (clock.p1 = limit->p1.min;
672 clock.p1 <= limit->p1.max; clock.p1++) {
673 int this_err;
674
675 i9xx_clock(refclk, &clock);
676 if (!intel_PLL_is_valid(dev, limit,
677 &clock))
678 continue;
679 if (match_clock &&
680 clock.p != match_clock->p)
681 continue;
682
683 this_err = abs(clock.dot - target);
684 if (this_err < err) {
685 *best_clock = clock;
686 err = this_err;
687 }
688 }
689 }
690 }
691 }
692
693 return (err != target);
694 }
695
696 static bool
697 pnv_find_best_dpll(const intel_limit_t *limit,
698 struct intel_crtc_state *crtc_state,
699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
701 {
702 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
703 struct drm_device *dev = crtc->base.dev;
704 intel_clock_t clock;
705 int err = target;
706
707 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
708 /*
709 * For LVDS just rely on its current settings for dual-channel.
710 * We haven't figured out how to reliably set up different
711 * single/dual channel state, if we even can.
712 */
713 if (intel_is_dual_link_lvds(dev))
714 clock.p2 = limit->p2.p2_fast;
715 else
716 clock.p2 = limit->p2.p2_slow;
717 } else {
718 if (target < limit->p2.dot_limit)
719 clock.p2 = limit->p2.p2_slow;
720 else
721 clock.p2 = limit->p2.p2_fast;
722 }
723
724 memset(best_clock, 0, sizeof(*best_clock));
725
726 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
727 clock.m1++) {
728 for (clock.m2 = limit->m2.min;
729 clock.m2 <= limit->m2.max; clock.m2++) {
730 for (clock.n = limit->n.min;
731 clock.n <= limit->n.max; clock.n++) {
732 for (clock.p1 = limit->p1.min;
733 clock.p1 <= limit->p1.max; clock.p1++) {
734 int this_err;
735
736 pineview_clock(refclk, &clock);
737 if (!intel_PLL_is_valid(dev, limit,
738 &clock))
739 continue;
740 if (match_clock &&
741 clock.p != match_clock->p)
742 continue;
743
744 this_err = abs(clock.dot - target);
745 if (this_err < err) {
746 *best_clock = clock;
747 err = this_err;
748 }
749 }
750 }
751 }
752 }
753
754 return (err != target);
755 }
756
757 static bool
758 g4x_find_best_dpll(const intel_limit_t *limit,
759 struct intel_crtc_state *crtc_state,
760 int target, int refclk, intel_clock_t *match_clock,
761 intel_clock_t *best_clock)
762 {
763 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
764 struct drm_device *dev = crtc->base.dev;
765 intel_clock_t clock;
766 int max_n;
767 bool found;
768 /* approximately equals target * 0.00585 */
769 int err_most = (target >> 8) + (target >> 9);
770 found = false;
771
772 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
773 if (intel_is_dual_link_lvds(dev))
774 clock.p2 = limit->p2.p2_fast;
775 else
776 clock.p2 = limit->p2.p2_slow;
777 } else {
778 if (target < limit->p2.dot_limit)
779 clock.p2 = limit->p2.p2_slow;
780 else
781 clock.p2 = limit->p2.p2_fast;
782 }
783
784 memset(best_clock, 0, sizeof(*best_clock));
785 max_n = limit->n.max;
786 /* based on hardware requirement, prefer smaller n to precision */
787 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
788 /* based on hardware requirement, prefere larger m1,m2 */
789 for (clock.m1 = limit->m1.max;
790 clock.m1 >= limit->m1.min; clock.m1--) {
791 for (clock.m2 = limit->m2.max;
792 clock.m2 >= limit->m2.min; clock.m2--) {
793 for (clock.p1 = limit->p1.max;
794 clock.p1 >= limit->p1.min; clock.p1--) {
795 int this_err;
796
797 i9xx_clock(refclk, &clock);
798 if (!intel_PLL_is_valid(dev, limit,
799 &clock))
800 continue;
801
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813 return found;
814 }
815
816 /*
817 * Check if the calculated PLL configuration is more optimal compared to the
818 * best configuration and error found so far. Return the calculated error.
819 */
820 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
821 const intel_clock_t *calculated_clock,
822 const intel_clock_t *best_clock,
823 unsigned int best_error_ppm,
824 unsigned int *error_ppm)
825 {
826 /*
827 * For CHV ignore the error and consider only the P value.
828 * Prefer a bigger P value based on HW requirements.
829 */
830 if (IS_CHERRYVIEW(dev)) {
831 *error_ppm = 0;
832
833 return calculated_clock->p > best_clock->p;
834 }
835
836 if (WARN_ON_ONCE(!target_freq))
837 return false;
838
839 *error_ppm = div_u64(1000000ULL *
840 abs(target_freq - calculated_clock->dot),
841 target_freq);
842 /*
843 * Prefer a better P value over a better (smaller) error if the error
844 * is small. Ensure this preference for future configurations too by
845 * setting the error to 0.
846 */
847 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
848 *error_ppm = 0;
849
850 return true;
851 }
852
853 return *error_ppm + 10 < best_error_ppm;
854 }
855
856 static bool
857 vlv_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
863 struct drm_device *dev = crtc->base.dev;
864 intel_clock_t clock;
865 unsigned int bestppm = 1000000;
866 /* min update 19.2 MHz */
867 int max_n = min(limit->n.max, refclk / 19200);
868 bool found = false;
869
870 target *= 5; /* fast clock */
871
872 memset(best_clock, 0, sizeof(*best_clock));
873
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
877 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
878 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
879 clock.p = clock.p1 * clock.p2;
880 /* based on hardware requirement, prefer bigger m1,m2 values */
881 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
882 unsigned int ppm;
883
884 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
885 refclk * clock.m1);
886
887 vlv_clock(refclk, &clock);
888
889 if (!intel_PLL_is_valid(dev, limit,
890 &clock))
891 continue;
892
893 if (!vlv_PLL_is_optimal(dev, target,
894 &clock,
895 best_clock,
896 bestppm, &ppm))
897 continue;
898
899 *best_clock = clock;
900 bestppm = ppm;
901 found = true;
902 }
903 }
904 }
905 }
906
907 return found;
908 }
909
910 static bool
911 chv_find_best_dpll(const intel_limit_t *limit,
912 struct intel_crtc_state *crtc_state,
913 int target, int refclk, intel_clock_t *match_clock,
914 intel_clock_t *best_clock)
915 {
916 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
917 struct drm_device *dev = crtc->base.dev;
918 unsigned int best_error_ppm;
919 intel_clock_t clock;
920 uint64_t m2;
921 int found = false;
922
923 memset(best_clock, 0, sizeof(*best_clock));
924 best_error_ppm = 1000000;
925
926 /*
927 * Based on hardware doc, the n always set to 1, and m1 always
928 * set to 2. If requires to support 200Mhz refclk, we need to
929 * revisit this because n may not 1 anymore.
930 */
931 clock.n = 1, clock.m1 = 2;
932 target *= 5; /* fast clock */
933
934 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
935 for (clock.p2 = limit->p2.p2_fast;
936 clock.p2 >= limit->p2.p2_slow;
937 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
938 unsigned int error_ppm;
939
940 clock.p = clock.p1 * clock.p2;
941
942 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
943 clock.n) << 22, refclk * clock.m1);
944
945 if (m2 > INT_MAX/clock.m1)
946 continue;
947
948 clock.m2 = m2;
949
950 chv_clock(refclk, &clock);
951
952 if (!intel_PLL_is_valid(dev, limit, &clock))
953 continue;
954
955 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
956 best_error_ppm, &error_ppm))
957 continue;
958
959 *best_clock = clock;
960 best_error_ppm = error_ppm;
961 found = true;
962 }
963 }
964
965 return found;
966 }
967
968 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
969 intel_clock_t *best_clock)
970 {
971 int refclk = i9xx_get_refclk(crtc_state, 0);
972
973 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
974 target_clock, refclk, NULL, best_clock);
975 }
976
977 bool intel_crtc_active(struct drm_crtc *crtc)
978 {
979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
980
981 /* Be paranoid as we can arrive here with only partial
982 * state retrieved from the hardware during setup.
983 *
984 * We can ditch the adjusted_mode.crtc_clock check as soon
985 * as Haswell has gained clock readout/fastboot support.
986 *
987 * We can ditch the crtc->primary->fb check as soon as we can
988 * properly reconstruct framebuffers.
989 *
990 * FIXME: The intel_crtc->active here should be switched to
991 * crtc->state->active once we have proper CRTC states wired up
992 * for atomic.
993 */
994 return intel_crtc->active && crtc->primary->state->fb &&
995 intel_crtc->config->base.adjusted_mode.crtc_clock;
996 }
997
998 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
999 enum pipe pipe)
1000 {
1001 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1003
1004 return intel_crtc->config->cpu_transcoder;
1005 }
1006
1007 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1008 {
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 u32 reg = PIPEDSL(pipe);
1011 u32 line1, line2;
1012 u32 line_mask;
1013
1014 if (IS_GEN2(dev))
1015 line_mask = DSL_LINEMASK_GEN2;
1016 else
1017 line_mask = DSL_LINEMASK_GEN3;
1018
1019 line1 = I915_READ(reg) & line_mask;
1020 mdelay(5);
1021 line2 = I915_READ(reg) & line_mask;
1022
1023 return line1 == line2;
1024 }
1025
1026 /*
1027 * intel_wait_for_pipe_off - wait for pipe to turn off
1028 * @crtc: crtc whose pipe to wait for
1029 *
1030 * After disabling a pipe, we can't wait for vblank in the usual way,
1031 * spinning on the vblank interrupt status bit, since we won't actually
1032 * see an interrupt when the pipe is disabled.
1033 *
1034 * On Gen4 and above:
1035 * wait for the pipe register state bit to turn off
1036 *
1037 * Otherwise:
1038 * wait for the display line value to settle (it usually
1039 * ends up stopping at the start of the next frame).
1040 *
1041 */
1042 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1043 {
1044 struct drm_device *dev = crtc->base.dev;
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1047 enum pipe pipe = crtc->pipe;
1048
1049 if (INTEL_INFO(dev)->gen >= 4) {
1050 int reg = PIPECONF(cpu_transcoder);
1051
1052 /* Wait for the Pipe State to go off */
1053 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1054 100))
1055 WARN(1, "pipe_off wait timed out\n");
1056 } else {
1057 /* Wait for the display line to settle */
1058 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1059 WARN(1, "pipe_off wait timed out\n");
1060 }
1061 }
1062
1063 /*
1064 * ibx_digital_port_connected - is the specified port connected?
1065 * @dev_priv: i915 private structure
1066 * @port: the port to test
1067 *
1068 * Returns true if @port is connected, false otherwise.
1069 */
1070 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1071 struct intel_digital_port *port)
1072 {
1073 u32 bit;
1074
1075 if (HAS_PCH_IBX(dev_priv->dev)) {
1076 switch (port->port) {
1077 case PORT_B:
1078 bit = SDE_PORTB_HOTPLUG;
1079 break;
1080 case PORT_C:
1081 bit = SDE_PORTC_HOTPLUG;
1082 break;
1083 case PORT_D:
1084 bit = SDE_PORTD_HOTPLUG;
1085 break;
1086 default:
1087 return true;
1088 }
1089 } else {
1090 switch (port->port) {
1091 case PORT_B:
1092 bit = SDE_PORTB_HOTPLUG_CPT;
1093 break;
1094 case PORT_C:
1095 bit = SDE_PORTC_HOTPLUG_CPT;
1096 break;
1097 case PORT_D:
1098 bit = SDE_PORTD_HOTPLUG_CPT;
1099 break;
1100 default:
1101 return true;
1102 }
1103 }
1104
1105 return I915_READ(SDEISR) & bit;
1106 }
1107
1108 static const char *state_string(bool enabled)
1109 {
1110 return enabled ? "on" : "off";
1111 }
1112
1113 /* Only for pre-ILK configs */
1114 void assert_pll(struct drm_i915_private *dev_priv,
1115 enum pipe pipe, bool state)
1116 {
1117 int reg;
1118 u32 val;
1119 bool cur_state;
1120
1121 reg = DPLL(pipe);
1122 val = I915_READ(reg);
1123 cur_state = !!(val & DPLL_VCO_ENABLE);
1124 I915_STATE_WARN(cur_state != state,
1125 "PLL state assertion failure (expected %s, current %s)\n",
1126 state_string(state), state_string(cur_state));
1127 }
1128
1129 /* XXX: the dsi pll is shared between MIPI DSI ports */
1130 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1131 {
1132 u32 val;
1133 bool cur_state;
1134
1135 mutex_lock(&dev_priv->dpio_lock);
1136 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1137 mutex_unlock(&dev_priv->dpio_lock);
1138
1139 cur_state = val & DSI_PLL_VCO_EN;
1140 I915_STATE_WARN(cur_state != state,
1141 "DSI PLL state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143 }
1144 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1145 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1146
1147 struct intel_shared_dpll *
1148 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1149 {
1150 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1151
1152 if (crtc->config->shared_dpll < 0)
1153 return NULL;
1154
1155 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1156 }
1157
1158 /* For ILK+ */
1159 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1160 struct intel_shared_dpll *pll,
1161 bool state)
1162 {
1163 bool cur_state;
1164 struct intel_dpll_hw_state hw_state;
1165
1166 if (WARN (!pll,
1167 "asserting DPLL %s with no DPLL\n", state_string(state)))
1168 return;
1169
1170 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1171 I915_STATE_WARN(cur_state != state,
1172 "%s assertion failure (expected %s, current %s)\n",
1173 pll->name, state_string(state), state_string(cur_state));
1174 }
1175
1176 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1177 enum pipe pipe, bool state)
1178 {
1179 int reg;
1180 u32 val;
1181 bool cur_state;
1182 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1183 pipe);
1184
1185 if (HAS_DDI(dev_priv->dev)) {
1186 /* DDI does not have a specific FDI_TX register */
1187 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1190 } else {
1191 reg = FDI_TX_CTL(pipe);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & FDI_TX_ENABLE);
1194 }
1195 I915_STATE_WARN(cur_state != state,
1196 "FDI TX state assertion failure (expected %s, current %s)\n",
1197 state_string(state), state_string(cur_state));
1198 }
1199 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1200 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1201
1202 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, bool state)
1204 {
1205 int reg;
1206 u32 val;
1207 bool cur_state;
1208
1209 reg = FDI_RX_CTL(pipe);
1210 val = I915_READ(reg);
1211 cur_state = !!(val & FDI_RX_ENABLE);
1212 I915_STATE_WARN(cur_state != state,
1213 "FDI RX state assertion failure (expected %s, current %s)\n",
1214 state_string(state), state_string(cur_state));
1215 }
1216 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1217 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1218
1219 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1220 enum pipe pipe)
1221 {
1222 int reg;
1223 u32 val;
1224
1225 /* ILK FDI PLL is always enabled */
1226 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1227 return;
1228
1229 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1230 if (HAS_DDI(dev_priv->dev))
1231 return;
1232
1233 reg = FDI_TX_CTL(pipe);
1234 val = I915_READ(reg);
1235 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1236 }
1237
1238 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1239 enum pipe pipe, bool state)
1240 {
1241 int reg;
1242 u32 val;
1243 bool cur_state;
1244
1245 reg = FDI_RX_CTL(pipe);
1246 val = I915_READ(reg);
1247 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1248 I915_STATE_WARN(cur_state != state,
1249 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1250 state_string(state), state_string(cur_state));
1251 }
1252
1253 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1254 enum pipe pipe)
1255 {
1256 struct drm_device *dev = dev_priv->dev;
1257 int pp_reg;
1258 u32 val;
1259 enum pipe panel_pipe = PIPE_A;
1260 bool locked = true;
1261
1262 if (WARN_ON(HAS_DDI(dev)))
1263 return;
1264
1265 if (HAS_PCH_SPLIT(dev)) {
1266 u32 port_sel;
1267
1268 pp_reg = PCH_PP_CONTROL;
1269 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1270
1271 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1272 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1273 panel_pipe = PIPE_B;
1274 /* XXX: else fix for eDP */
1275 } else if (IS_VALLEYVIEW(dev)) {
1276 /* presumably write lock depends on pipe, not port select */
1277 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1278 panel_pipe = pipe;
1279 } else {
1280 pp_reg = PP_CONTROL;
1281 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 }
1284
1285 val = I915_READ(pp_reg);
1286 if (!(val & PANEL_POWER_ON) ||
1287 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1288 locked = false;
1289
1290 I915_STATE_WARN(panel_pipe == pipe && locked,
1291 "panel assertion failure, pipe %c regs locked\n",
1292 pipe_name(pipe));
1293 }
1294
1295 static void assert_cursor(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, bool state)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 bool cur_state;
1300
1301 if (IS_845G(dev) || IS_I865G(dev))
1302 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1303 else
1304 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1305
1306 I915_STATE_WARN(cur_state != state,
1307 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1308 pipe_name(pipe), state_string(state), state_string(cur_state));
1309 }
1310 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1311 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1312
1313 void assert_pipe(struct drm_i915_private *dev_priv,
1314 enum pipe pipe, bool state)
1315 {
1316 int reg;
1317 u32 val;
1318 bool cur_state;
1319 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1320 pipe);
1321
1322 /* if we need the pipe quirk it must be always on */
1323 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1324 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1325 state = true;
1326
1327 if (!intel_display_power_is_enabled(dev_priv,
1328 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1329 cur_state = false;
1330 } else {
1331 reg = PIPECONF(cpu_transcoder);
1332 val = I915_READ(reg);
1333 cur_state = !!(val & PIPECONF_ENABLE);
1334 }
1335
1336 I915_STATE_WARN(cur_state != state,
1337 "pipe %c assertion failure (expected %s, current %s)\n",
1338 pipe_name(pipe), state_string(state), state_string(cur_state));
1339 }
1340
1341 static void assert_plane(struct drm_i915_private *dev_priv,
1342 enum plane plane, bool state)
1343 {
1344 int reg;
1345 u32 val;
1346 bool cur_state;
1347
1348 reg = DSPCNTR(plane);
1349 val = I915_READ(reg);
1350 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1351 I915_STATE_WARN(cur_state != state,
1352 "plane %c assertion failure (expected %s, current %s)\n",
1353 plane_name(plane), state_string(state), state_string(cur_state));
1354 }
1355
1356 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1357 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1358
1359 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 struct drm_device *dev = dev_priv->dev;
1363 int reg, i;
1364 u32 val;
1365 int cur_pipe;
1366
1367 /* Primary planes are fixed to pipes on gen4+ */
1368 if (INTEL_INFO(dev)->gen >= 4) {
1369 reg = DSPCNTR(pipe);
1370 val = I915_READ(reg);
1371 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1372 "plane %c assertion failure, should be disabled but not\n",
1373 plane_name(pipe));
1374 return;
1375 }
1376
1377 /* Need to check both planes against the pipe */
1378 for_each_pipe(dev_priv, i) {
1379 reg = DSPCNTR(i);
1380 val = I915_READ(reg);
1381 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1382 DISPPLANE_SEL_PIPE_SHIFT;
1383 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1384 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1385 plane_name(i), pipe_name(pipe));
1386 }
1387 }
1388
1389 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1390 enum pipe pipe)
1391 {
1392 struct drm_device *dev = dev_priv->dev;
1393 int reg, sprite;
1394 u32 val;
1395
1396 if (INTEL_INFO(dev)->gen >= 9) {
1397 for_each_sprite(dev_priv, pipe, sprite) {
1398 val = I915_READ(PLANE_CTL(pipe, sprite));
1399 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1400 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1401 sprite, pipe_name(pipe));
1402 }
1403 } else if (IS_VALLEYVIEW(dev)) {
1404 for_each_sprite(dev_priv, pipe, sprite) {
1405 reg = SPCNTR(pipe, sprite);
1406 val = I915_READ(reg);
1407 I915_STATE_WARN(val & SP_ENABLE,
1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1409 sprite_name(pipe, sprite), pipe_name(pipe));
1410 }
1411 } else if (INTEL_INFO(dev)->gen >= 7) {
1412 reg = SPRCTL(pipe);
1413 val = I915_READ(reg);
1414 I915_STATE_WARN(val & SPRITE_ENABLE,
1415 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1416 plane_name(pipe), pipe_name(pipe));
1417 } else if (INTEL_INFO(dev)->gen >= 5) {
1418 reg = DVSCNTR(pipe);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & DVS_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 plane_name(pipe), pipe_name(pipe));
1423 }
1424 }
1425
1426 static void assert_vblank_disabled(struct drm_crtc *crtc)
1427 {
1428 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1429 drm_crtc_vblank_put(crtc);
1430 }
1431
1432 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1433 {
1434 u32 val;
1435 bool enabled;
1436
1437 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1438
1439 val = I915_READ(PCH_DREF_CONTROL);
1440 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1441 DREF_SUPERSPREAD_SOURCE_MASK));
1442 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1443 }
1444
1445 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1446 enum pipe pipe)
1447 {
1448 int reg;
1449 u32 val;
1450 bool enabled;
1451
1452 reg = PCH_TRANSCONF(pipe);
1453 val = I915_READ(reg);
1454 enabled = !!(val & TRANS_ENABLE);
1455 I915_STATE_WARN(enabled,
1456 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1457 pipe_name(pipe));
1458 }
1459
1460 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 port_sel, u32 val)
1462 {
1463 if ((val & DP_PORT_EN) == 0)
1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
1467 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1468 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1469 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1470 return false;
1471 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1472 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1473 return false;
1474 } else {
1475 if ((val & DP_PIPE_MASK) != (pipe << 30))
1476 return false;
1477 }
1478 return true;
1479 }
1480
1481 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, u32 val)
1483 {
1484 if ((val & SDVO_ENABLE) == 0)
1485 return false;
1486
1487 if (HAS_PCH_CPT(dev_priv->dev)) {
1488 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1489 return false;
1490 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1491 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1492 return false;
1493 } else {
1494 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1495 return false;
1496 }
1497 return true;
1498 }
1499
1500 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, u32 val)
1502 {
1503 if ((val & LVDS_PORT_EN) == 0)
1504 return false;
1505
1506 if (HAS_PCH_CPT(dev_priv->dev)) {
1507 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1508 return false;
1509 } else {
1510 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1511 return false;
1512 }
1513 return true;
1514 }
1515
1516 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518 {
1519 if ((val & ADPA_DAC_ENABLE) == 0)
1520 return false;
1521 if (HAS_PCH_CPT(dev_priv->dev)) {
1522 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523 return false;
1524 } else {
1525 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1526 return false;
1527 }
1528 return true;
1529 }
1530
1531 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1532 enum pipe pipe, int reg, u32 port_sel)
1533 {
1534 u32 val = I915_READ(reg);
1535 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1536 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1537 reg, pipe_name(pipe));
1538
1539 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1540 && (val & DP_PIPEB_SELECT),
1541 "IBX PCH dp port still using transcoder B\n");
1542 }
1543
1544 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg)
1546 {
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1549 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1551
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1553 && (val & SDVO_PIPE_B_SELECT),
1554 "IBX PCH hdmi port still using transcoder B\n");
1555 }
1556
1557 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe)
1559 {
1560 int reg;
1561 u32 val;
1562
1563 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1566
1567 reg = PCH_ADPA;
1568 val = I915_READ(reg);
1569 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1570 "PCH VGA enabled on transcoder %c, should be disabled\n",
1571 pipe_name(pipe));
1572
1573 reg = PCH_LVDS;
1574 val = I915_READ(reg);
1575 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1576 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1577 pipe_name(pipe));
1578
1579 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1582 }
1583
1584 static void intel_init_dpio(struct drm_device *dev)
1585 {
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587
1588 if (!IS_VALLEYVIEW(dev))
1589 return;
1590
1591 /*
1592 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1593 * CHV x1 PHY (DP/HDMI D)
1594 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1595 */
1596 if (IS_CHERRYVIEW(dev)) {
1597 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1599 } else {
1600 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1601 }
1602 }
1603
1604 static void vlv_enable_pll(struct intel_crtc *crtc,
1605 const struct intel_crtc_state *pipe_config)
1606 {
1607 struct drm_device *dev = crtc->base.dev;
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 int reg = DPLL(crtc->pipe);
1610 u32 dpll = pipe_config->dpll_hw_state.dpll;
1611
1612 assert_pipe_disabled(dev_priv, crtc->pipe);
1613
1614 /* No really, not for ILK+ */
1615 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1616
1617 /* PLL is protected by panel, make sure we can write it */
1618 if (IS_MOBILE(dev_priv->dev))
1619 assert_panel_unlocked(dev_priv, crtc->pipe);
1620
1621 I915_WRITE(reg, dpll);
1622 POSTING_READ(reg);
1623 udelay(150);
1624
1625 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1626 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1627
1628 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1629 POSTING_READ(DPLL_MD(crtc->pipe));
1630
1631 /* We do this three times for luck */
1632 I915_WRITE(reg, dpll);
1633 POSTING_READ(reg);
1634 udelay(150); /* wait for warmup */
1635 I915_WRITE(reg, dpll);
1636 POSTING_READ(reg);
1637 udelay(150); /* wait for warmup */
1638 I915_WRITE(reg, dpll);
1639 POSTING_READ(reg);
1640 udelay(150); /* wait for warmup */
1641 }
1642
1643 static void chv_enable_pll(struct intel_crtc *crtc,
1644 const struct intel_crtc_state *pipe_config)
1645 {
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int pipe = crtc->pipe;
1649 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1650 u32 tmp;
1651
1652 assert_pipe_disabled(dev_priv, crtc->pipe);
1653
1654 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1655
1656 mutex_lock(&dev_priv->dpio_lock);
1657
1658 /* Enable back the 10bit clock to display controller */
1659 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1660 tmp |= DPIO_DCLKP_EN;
1661 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1662
1663 /*
1664 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1665 */
1666 udelay(1);
1667
1668 /* Enable PLL */
1669 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1670
1671 /* Check PLL is locked */
1672 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1673 DRM_ERROR("PLL %d failed to lock\n", pipe);
1674
1675 /* not sure when this should be written */
1676 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1677 POSTING_READ(DPLL_MD(pipe));
1678
1679 mutex_unlock(&dev_priv->dpio_lock);
1680 }
1681
1682 static int intel_num_dvo_pipes(struct drm_device *dev)
1683 {
1684 struct intel_crtc *crtc;
1685 int count = 0;
1686
1687 for_each_intel_crtc(dev, crtc)
1688 count += crtc->active &&
1689 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1690
1691 return count;
1692 }
1693
1694 static void i9xx_enable_pll(struct intel_crtc *crtc)
1695 {
1696 struct drm_device *dev = crtc->base.dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 int reg = DPLL(crtc->pipe);
1699 u32 dpll = crtc->config->dpll_hw_state.dpll;
1700
1701 assert_pipe_disabled(dev_priv, crtc->pipe);
1702
1703 /* No really, not for ILK+ */
1704 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1705
1706 /* PLL is protected by panel, make sure we can write it */
1707 if (IS_MOBILE(dev) && !IS_I830(dev))
1708 assert_panel_unlocked(dev_priv, crtc->pipe);
1709
1710 /* Enable DVO 2x clock on both PLLs if necessary */
1711 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1712 /*
1713 * It appears to be important that we don't enable this
1714 * for the current pipe before otherwise configuring the
1715 * PLL. No idea how this should be handled if multiple
1716 * DVO outputs are enabled simultaneosly.
1717 */
1718 dpll |= DPLL_DVO_2X_MODE;
1719 I915_WRITE(DPLL(!crtc->pipe),
1720 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1721 }
1722
1723 /* Wait for the clocks to stabilize. */
1724 POSTING_READ(reg);
1725 udelay(150);
1726
1727 if (INTEL_INFO(dev)->gen >= 4) {
1728 I915_WRITE(DPLL_MD(crtc->pipe),
1729 crtc->config->dpll_hw_state.dpll_md);
1730 } else {
1731 /* The pixel multiplier can only be updated once the
1732 * DPLL is enabled and the clocks are stable.
1733 *
1734 * So write it again.
1735 */
1736 I915_WRITE(reg, dpll);
1737 }
1738
1739 /* We do this three times for luck */
1740 I915_WRITE(reg, dpll);
1741 POSTING_READ(reg);
1742 udelay(150); /* wait for warmup */
1743 I915_WRITE(reg, dpll);
1744 POSTING_READ(reg);
1745 udelay(150); /* wait for warmup */
1746 I915_WRITE(reg, dpll);
1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
1749 }
1750
1751 /**
1752 * i9xx_disable_pll - disable a PLL
1753 * @dev_priv: i915 private structure
1754 * @pipe: pipe PLL to disable
1755 *
1756 * Disable the PLL for @pipe, making sure the pipe is off first.
1757 *
1758 * Note! This is for pre-ILK only.
1759 */
1760 static void i9xx_disable_pll(struct intel_crtc *crtc)
1761 {
1762 struct drm_device *dev = crtc->base.dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 enum pipe pipe = crtc->pipe;
1765
1766 /* Disable DVO 2x clock on both PLLs if necessary */
1767 if (IS_I830(dev) &&
1768 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1769 intel_num_dvo_pipes(dev) == 1) {
1770 I915_WRITE(DPLL(PIPE_B),
1771 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1772 I915_WRITE(DPLL(PIPE_A),
1773 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1774 }
1775
1776 /* Don't disable pipe or pipe PLLs if needed */
1777 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1778 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1779 return;
1780
1781 /* Make sure the pipe isn't still relying on us */
1782 assert_pipe_disabled(dev_priv, pipe);
1783
1784 I915_WRITE(DPLL(pipe), 0);
1785 POSTING_READ(DPLL(pipe));
1786 }
1787
1788 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1789 {
1790 u32 val = 0;
1791
1792 /* Make sure the pipe isn't still relying on us */
1793 assert_pipe_disabled(dev_priv, pipe);
1794
1795 /*
1796 * Leave integrated clock source and reference clock enabled for pipe B.
1797 * The latter is needed for VGA hotplug / manual detection.
1798 */
1799 if (pipe == PIPE_B)
1800 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1801 I915_WRITE(DPLL(pipe), val);
1802 POSTING_READ(DPLL(pipe));
1803
1804 }
1805
1806 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1807 {
1808 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1809 u32 val;
1810
1811 /* Make sure the pipe isn't still relying on us */
1812 assert_pipe_disabled(dev_priv, pipe);
1813
1814 /* Set PLL en = 0 */
1815 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1816 if (pipe != PIPE_A)
1817 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1818 I915_WRITE(DPLL(pipe), val);
1819 POSTING_READ(DPLL(pipe));
1820
1821 mutex_lock(&dev_priv->dpio_lock);
1822
1823 /* Disable 10bit clock to display controller */
1824 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1825 val &= ~DPIO_DCLKP_EN;
1826 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1827
1828 /* disable left/right clock distribution */
1829 if (pipe != PIPE_B) {
1830 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1831 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1832 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1833 } else {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1835 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1837 }
1838
1839 mutex_unlock(&dev_priv->dpio_lock);
1840 }
1841
1842 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1843 struct intel_digital_port *dport,
1844 unsigned int expected_mask)
1845 {
1846 u32 port_mask;
1847 int dpll_reg;
1848
1849 switch (dport->port) {
1850 case PORT_B:
1851 port_mask = DPLL_PORTB_READY_MASK;
1852 dpll_reg = DPLL(0);
1853 break;
1854 case PORT_C:
1855 port_mask = DPLL_PORTC_READY_MASK;
1856 dpll_reg = DPLL(0);
1857 expected_mask <<= 4;
1858 break;
1859 case PORT_D:
1860 port_mask = DPLL_PORTD_READY_MASK;
1861 dpll_reg = DPIO_PHY_STATUS;
1862 break;
1863 default:
1864 BUG();
1865 }
1866
1867 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1868 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1869 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1870 }
1871
1872 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1873 {
1874 struct drm_device *dev = crtc->base.dev;
1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1877
1878 if (WARN_ON(pll == NULL))
1879 return;
1880
1881 WARN_ON(!pll->config.crtc_mask);
1882 if (pll->active == 0) {
1883 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1884 WARN_ON(pll->on);
1885 assert_shared_dpll_disabled(dev_priv, pll);
1886
1887 pll->mode_set(dev_priv, pll);
1888 }
1889 }
1890
1891 /**
1892 * intel_enable_shared_dpll - enable PCH PLL
1893 * @dev_priv: i915 private structure
1894 * @pipe: pipe PLL to enable
1895 *
1896 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1897 * drives the transcoder clock.
1898 */
1899 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1900 {
1901 struct drm_device *dev = crtc->base.dev;
1902 struct drm_i915_private *dev_priv = dev->dev_private;
1903 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1904
1905 if (WARN_ON(pll == NULL))
1906 return;
1907
1908 if (WARN_ON(pll->config.crtc_mask == 0))
1909 return;
1910
1911 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1912 pll->name, pll->active, pll->on,
1913 crtc->base.base.id);
1914
1915 if (pll->active++) {
1916 WARN_ON(!pll->on);
1917 assert_shared_dpll_enabled(dev_priv, pll);
1918 return;
1919 }
1920 WARN_ON(pll->on);
1921
1922 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1923
1924 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1925 pll->enable(dev_priv, pll);
1926 pll->on = true;
1927 }
1928
1929 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1930 {
1931 struct drm_device *dev = crtc->base.dev;
1932 struct drm_i915_private *dev_priv = dev->dev_private;
1933 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1934
1935 /* PCH only available on ILK+ */
1936 BUG_ON(INTEL_INFO(dev)->gen < 5);
1937 if (WARN_ON(pll == NULL))
1938 return;
1939
1940 if (WARN_ON(pll->config.crtc_mask == 0))
1941 return;
1942
1943 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1944 pll->name, pll->active, pll->on,
1945 crtc->base.base.id);
1946
1947 if (WARN_ON(pll->active == 0)) {
1948 assert_shared_dpll_disabled(dev_priv, pll);
1949 return;
1950 }
1951
1952 assert_shared_dpll_enabled(dev_priv, pll);
1953 WARN_ON(!pll->on);
1954 if (--pll->active)
1955 return;
1956
1957 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1958 pll->disable(dev_priv, pll);
1959 pll->on = false;
1960
1961 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1962 }
1963
1964 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1965 enum pipe pipe)
1966 {
1967 struct drm_device *dev = dev_priv->dev;
1968 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1970 uint32_t reg, val, pipeconf_val;
1971
1972 /* PCH only available on ILK+ */
1973 BUG_ON(!HAS_PCH_SPLIT(dev));
1974
1975 /* Make sure PCH DPLL is enabled */
1976 assert_shared_dpll_enabled(dev_priv,
1977 intel_crtc_to_shared_dpll(intel_crtc));
1978
1979 /* FDI must be feeding us bits for PCH ports */
1980 assert_fdi_tx_enabled(dev_priv, pipe);
1981 assert_fdi_rx_enabled(dev_priv, pipe);
1982
1983 if (HAS_PCH_CPT(dev)) {
1984 /* Workaround: Set the timing override bit before enabling the
1985 * pch transcoder. */
1986 reg = TRANS_CHICKEN2(pipe);
1987 val = I915_READ(reg);
1988 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1989 I915_WRITE(reg, val);
1990 }
1991
1992 reg = PCH_TRANSCONF(pipe);
1993 val = I915_READ(reg);
1994 pipeconf_val = I915_READ(PIPECONF(pipe));
1995
1996 if (HAS_PCH_IBX(dev_priv->dev)) {
1997 /*
1998 * make the BPC in transcoder be consistent with
1999 * that in pipeconf reg.
2000 */
2001 val &= ~PIPECONF_BPC_MASK;
2002 val |= pipeconf_val & PIPECONF_BPC_MASK;
2003 }
2004
2005 val &= ~TRANS_INTERLACE_MASK;
2006 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2007 if (HAS_PCH_IBX(dev_priv->dev) &&
2008 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2009 val |= TRANS_LEGACY_INTERLACED_ILK;
2010 else
2011 val |= TRANS_INTERLACED;
2012 else
2013 val |= TRANS_PROGRESSIVE;
2014
2015 I915_WRITE(reg, val | TRANS_ENABLE);
2016 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2017 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2018 }
2019
2020 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2021 enum transcoder cpu_transcoder)
2022 {
2023 u32 val, pipeconf_val;
2024
2025 /* PCH only available on ILK+ */
2026 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2027
2028 /* FDI must be feeding us bits for PCH ports */
2029 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2030 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031
2032 /* Workaround: set timing override bit. */
2033 val = I915_READ(_TRANSA_CHICKEN2);
2034 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2035 I915_WRITE(_TRANSA_CHICKEN2, val);
2036
2037 val = TRANS_ENABLE;
2038 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039
2040 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2041 PIPECONF_INTERLACED_ILK)
2042 val |= TRANS_INTERLACED;
2043 else
2044 val |= TRANS_PROGRESSIVE;
2045
2046 I915_WRITE(LPT_TRANSCONF, val);
2047 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2048 DRM_ERROR("Failed to enable PCH transcoder\n");
2049 }
2050
2051 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2052 enum pipe pipe)
2053 {
2054 struct drm_device *dev = dev_priv->dev;
2055 uint32_t reg, val;
2056
2057 /* FDI relies on the transcoder */
2058 assert_fdi_tx_disabled(dev_priv, pipe);
2059 assert_fdi_rx_disabled(dev_priv, pipe);
2060
2061 /* Ports must be off as well */
2062 assert_pch_ports_disabled(dev_priv, pipe);
2063
2064 reg = PCH_TRANSCONF(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_ENABLE;
2067 I915_WRITE(reg, val);
2068 /* wait for PCH transcoder off, transcoder state */
2069 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2070 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2071
2072 if (!HAS_PCH_IBX(dev)) {
2073 /* Workaround: Clear the timing override chicken bit again. */
2074 reg = TRANS_CHICKEN2(pipe);
2075 val = I915_READ(reg);
2076 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2077 I915_WRITE(reg, val);
2078 }
2079 }
2080
2081 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2082 {
2083 u32 val;
2084
2085 val = I915_READ(LPT_TRANSCONF);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(LPT_TRANSCONF, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2090 DRM_ERROR("Failed to disable PCH transcoder\n");
2091
2092 /* Workaround: clear timing override bit. */
2093 val = I915_READ(_TRANSA_CHICKEN2);
2094 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2095 I915_WRITE(_TRANSA_CHICKEN2, val);
2096 }
2097
2098 /**
2099 * intel_enable_pipe - enable a pipe, asserting requirements
2100 * @crtc: crtc responsible for the pipe
2101 *
2102 * Enable @crtc's pipe, making sure that various hardware specific requirements
2103 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2104 */
2105 static void intel_enable_pipe(struct intel_crtc *crtc)
2106 {
2107 struct drm_device *dev = crtc->base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 enum pipe pipe = crtc->pipe;
2110 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2111 pipe);
2112 enum pipe pch_transcoder;
2113 int reg;
2114 u32 val;
2115
2116 assert_planes_disabled(dev_priv, pipe);
2117 assert_cursor_disabled(dev_priv, pipe);
2118 assert_sprites_disabled(dev_priv, pipe);
2119
2120 if (HAS_PCH_LPT(dev_priv->dev))
2121 pch_transcoder = TRANSCODER_A;
2122 else
2123 pch_transcoder = pipe;
2124
2125 /*
2126 * A pipe without a PLL won't actually be able to drive bits from
2127 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2128 * need the check.
2129 */
2130 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2132 assert_dsi_pll_enabled(dev_priv);
2133 else
2134 assert_pll_enabled(dev_priv, pipe);
2135 else {
2136 if (crtc->config->has_pch_encoder) {
2137 /* if driving the PCH, we need FDI enabled */
2138 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2139 assert_fdi_tx_pll_enabled(dev_priv,
2140 (enum pipe) cpu_transcoder);
2141 }
2142 /* FIXME: assert CPU port conditions for SNB+ */
2143 }
2144
2145 reg = PIPECONF(cpu_transcoder);
2146 val = I915_READ(reg);
2147 if (val & PIPECONF_ENABLE) {
2148 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2149 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2150 return;
2151 }
2152
2153 I915_WRITE(reg, val | PIPECONF_ENABLE);
2154 POSTING_READ(reg);
2155 }
2156
2157 /**
2158 * intel_disable_pipe - disable a pipe, asserting requirements
2159 * @crtc: crtc whose pipes is to be disabled
2160 *
2161 * Disable the pipe of @crtc, making sure that various hardware
2162 * specific requirements are met, if applicable, e.g. plane
2163 * disabled, panel fitter off, etc.
2164 *
2165 * Will wait until the pipe has shut down before returning.
2166 */
2167 static void intel_disable_pipe(struct intel_crtc *crtc)
2168 {
2169 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2170 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2171 enum pipe pipe = crtc->pipe;
2172 int reg;
2173 u32 val;
2174
2175 /*
2176 * Make sure planes won't keep trying to pump pixels to us,
2177 * or we might hang the display.
2178 */
2179 assert_planes_disabled(dev_priv, pipe);
2180 assert_cursor_disabled(dev_priv, pipe);
2181 assert_sprites_disabled(dev_priv, pipe);
2182
2183 reg = PIPECONF(cpu_transcoder);
2184 val = I915_READ(reg);
2185 if ((val & PIPECONF_ENABLE) == 0)
2186 return;
2187
2188 /*
2189 * Double wide has implications for planes
2190 * so best keep it disabled when not needed.
2191 */
2192 if (crtc->config->double_wide)
2193 val &= ~PIPECONF_DOUBLE_WIDE;
2194
2195 /* Don't disable pipe or pipe PLLs if needed */
2196 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2197 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2198 val &= ~PIPECONF_ENABLE;
2199
2200 I915_WRITE(reg, val);
2201 if ((val & PIPECONF_ENABLE) == 0)
2202 intel_wait_for_pipe_off(crtc);
2203 }
2204
2205 /*
2206 * Plane regs are double buffered, going from enabled->disabled needs a
2207 * trigger in order to latch. The display address reg provides this.
2208 */
2209 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2210 enum plane plane)
2211 {
2212 struct drm_device *dev = dev_priv->dev;
2213 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2214
2215 I915_WRITE(reg, I915_READ(reg));
2216 POSTING_READ(reg);
2217 }
2218
2219 /**
2220 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2221 * @plane: plane to be enabled
2222 * @crtc: crtc for the plane
2223 *
2224 * Enable @plane on @crtc, making sure that the pipe is running first.
2225 */
2226 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2227 struct drm_crtc *crtc)
2228 {
2229 struct drm_device *dev = plane->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232
2233 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2234 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2235 to_intel_plane_state(plane->state)->visible = true;
2236
2237 dev_priv->display.update_primary_plane(crtc, plane->fb,
2238 crtc->x, crtc->y);
2239 }
2240
2241 static bool need_vtd_wa(struct drm_device *dev)
2242 {
2243 #ifdef CONFIG_INTEL_IOMMU
2244 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2245 return true;
2246 #endif
2247 return false;
2248 }
2249
2250 unsigned int
2251 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2252 uint64_t fb_format_modifier)
2253 {
2254 unsigned int tile_height;
2255 uint32_t pixel_bytes;
2256
2257 switch (fb_format_modifier) {
2258 case DRM_FORMAT_MOD_NONE:
2259 tile_height = 1;
2260 break;
2261 case I915_FORMAT_MOD_X_TILED:
2262 tile_height = IS_GEN2(dev) ? 16 : 8;
2263 break;
2264 case I915_FORMAT_MOD_Y_TILED:
2265 tile_height = 32;
2266 break;
2267 case I915_FORMAT_MOD_Yf_TILED:
2268 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2269 switch (pixel_bytes) {
2270 default:
2271 case 1:
2272 tile_height = 64;
2273 break;
2274 case 2:
2275 case 4:
2276 tile_height = 32;
2277 break;
2278 case 8:
2279 tile_height = 16;
2280 break;
2281 case 16:
2282 WARN_ONCE(1,
2283 "128-bit pixels are not supported for display!");
2284 tile_height = 16;
2285 break;
2286 }
2287 break;
2288 default:
2289 MISSING_CASE(fb_format_modifier);
2290 tile_height = 1;
2291 break;
2292 }
2293
2294 return tile_height;
2295 }
2296
2297 unsigned int
2298 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2299 uint32_t pixel_format, uint64_t fb_format_modifier)
2300 {
2301 return ALIGN(height, intel_tile_height(dev, pixel_format,
2302 fb_format_modifier));
2303 }
2304
2305 static int
2306 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2307 const struct drm_plane_state *plane_state)
2308 {
2309 struct intel_rotation_info *info = &view->rotation_info;
2310
2311 *view = i915_ggtt_view_normal;
2312
2313 if (!plane_state)
2314 return 0;
2315
2316 if (!intel_rotation_90_or_270(plane_state->rotation))
2317 return 0;
2318
2319 *view = i915_ggtt_view_rotated;
2320
2321 info->height = fb->height;
2322 info->pixel_format = fb->pixel_format;
2323 info->pitch = fb->pitches[0];
2324 info->fb_modifier = fb->modifier[0];
2325
2326 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331 struct drm_framebuffer *fb,
2332 const struct drm_plane_state *plane_state,
2333 struct intel_engine_cs *pipelined)
2334 {
2335 struct drm_device *dev = fb->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338 struct i915_ggtt_view view;
2339 u32 alignment;
2340 int ret;
2341
2342 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343
2344 switch (fb->modifier[0]) {
2345 case DRM_FORMAT_MOD_NONE:
2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2348 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2349 alignment = 128 * 1024;
2350 else if (INTEL_INFO(dev)->gen >= 4)
2351 alignment = 4 * 1024;
2352 else
2353 alignment = 64 * 1024;
2354 break;
2355 case I915_FORMAT_MOD_X_TILED:
2356 if (INTEL_INFO(dev)->gen >= 9)
2357 alignment = 256 * 1024;
2358 else {
2359 /* pin() will align the object as required by fence */
2360 alignment = 0;
2361 }
2362 break;
2363 case I915_FORMAT_MOD_Y_TILED:
2364 case I915_FORMAT_MOD_Yf_TILED:
2365 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2366 "Y tiling bo slipped through, driver bug!\n"))
2367 return -EINVAL;
2368 alignment = 1 * 1024 * 1024;
2369 break;
2370 default:
2371 MISSING_CASE(fb->modifier[0]);
2372 return -EINVAL;
2373 }
2374
2375 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376 if (ret)
2377 return ret;
2378
2379 /* Note that the w/a also requires 64 PTE of padding following the
2380 * bo. We currently fill all unused PTE with the shadow page and so
2381 * we should always have valid PTE following the scanout preventing
2382 * the VT-d warning.
2383 */
2384 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2385 alignment = 256 * 1024;
2386
2387 /*
2388 * Global gtt pte registers are special registers which actually forward
2389 * writes to a chunk of system memory. Which means that there is no risk
2390 * that the register values disappear as soon as we call
2391 * intel_runtime_pm_put(), so it is correct to wrap only the
2392 * pin/unpin/fence and not more.
2393 */
2394 intel_runtime_pm_get(dev_priv);
2395
2396 dev_priv->mm.interruptible = false;
2397 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2398 &view);
2399 if (ret)
2400 goto err_interruptible;
2401
2402 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2403 * fence, whereas 965+ only requires a fence if using
2404 * framebuffer compression. For simplicity, we always install
2405 * a fence as the cost is not that onerous.
2406 */
2407 ret = i915_gem_object_get_fence(obj);
2408 if (ret)
2409 goto err_unpin;
2410
2411 i915_gem_object_pin_fence(obj);
2412
2413 dev_priv->mm.interruptible = true;
2414 intel_runtime_pm_put(dev_priv);
2415 return 0;
2416
2417 err_unpin:
2418 i915_gem_object_unpin_from_display_plane(obj, &view);
2419 err_interruptible:
2420 dev_priv->mm.interruptible = true;
2421 intel_runtime_pm_put(dev_priv);
2422 return ret;
2423 }
2424
2425 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2426 const struct drm_plane_state *plane_state)
2427 {
2428 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2429 struct i915_ggtt_view view;
2430 int ret;
2431
2432 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433
2434 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435 WARN_ONCE(ret, "Couldn't get view from plane state!");
2436
2437 i915_gem_object_unpin_fence(obj);
2438 i915_gem_object_unpin_from_display_plane(obj, &view);
2439 }
2440
2441 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2442 * is assumed to be a power-of-two. */
2443 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2444 unsigned int tiling_mode,
2445 unsigned int cpp,
2446 unsigned int pitch)
2447 {
2448 if (tiling_mode != I915_TILING_NONE) {
2449 unsigned int tile_rows, tiles;
2450
2451 tile_rows = *y / 8;
2452 *y %= 8;
2453
2454 tiles = *x / (512/cpp);
2455 *x %= 512/cpp;
2456
2457 return tile_rows * pitch * 8 + tiles * 4096;
2458 } else {
2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
2462 *y = 0;
2463 *x = (offset & 4095) / cpp;
2464 return offset & -4096;
2465 }
2466 }
2467
2468 static int i9xx_format_to_fourcc(int format)
2469 {
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487 }
2488
2489 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490 {
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513 }
2514
2515 static bool
2516 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
2518 {
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2522 struct drm_framebuffer *fb = &plane_config->fb->base;
2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
2528
2529 if (plane_config->size == 0)
2530 return false;
2531
2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
2536 if (!obj)
2537 return false;
2538
2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
2541 obj->stride = fb->pitches[0];
2542
2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2549
2550 mutex_lock(&dev->struct_mutex);
2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2552 &mode_cmd, obj)) {
2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
2556 mutex_unlock(&dev->struct_mutex);
2557
2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2559 return true;
2560
2561 out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
2564 return false;
2565 }
2566
2567 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2568 static void
2569 update_state_fb(struct drm_plane *plane)
2570 {
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579 }
2580
2581 static void
2582 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
2584 {
2585 struct drm_device *dev = intel_crtc->base.dev;
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2589 struct drm_i915_gem_object *obj;
2590 struct drm_plane *primary = intel_crtc->base.primary;
2591 struct drm_framebuffer *fb;
2592
2593 if (!plane_config->fb)
2594 return;
2595
2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
2599 }
2600
2601 kfree(plane_config->fb);
2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
2607 for_each_crtc(dev, c) {
2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2613 if (!i->active)
2614 continue;
2615
2616 fb = c->primary->fb;
2617 if (!fb)
2618 continue;
2619
2620 obj = intel_fb_obj(fb);
2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
2624 }
2625 }
2626
2627 return;
2628
2629 valid_fb:
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 primary->fb = fb;
2635 primary->state->crtc = &intel_crtc->base;
2636 primary->crtc = &intel_crtc->base;
2637 update_state_fb(primary);
2638 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2642 struct drm_framebuffer *fb,
2643 int x, int y)
2644 {
2645 struct drm_device *dev = crtc->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648 struct drm_plane *primary = crtc->primary;
2649 bool visible = to_intel_plane_state(primary->state)->visible;
2650 struct drm_i915_gem_object *obj;
2651 int plane = intel_crtc->plane;
2652 unsigned long linear_offset;
2653 u32 dspcntr;
2654 u32 reg = DSPCNTR(plane);
2655 int pixel_size;
2656
2657 if (!visible || !fb) {
2658 I915_WRITE(reg, 0);
2659 if (INTEL_INFO(dev)->gen >= 4)
2660 I915_WRITE(DSPSURF(plane), 0);
2661 else
2662 I915_WRITE(DSPADDR(plane), 0);
2663 POSTING_READ(reg);
2664 return;
2665 }
2666
2667 obj = intel_fb_obj(fb);
2668 if (WARN_ON(obj == NULL))
2669 return;
2670
2671 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2672
2673 dspcntr = DISPPLANE_GAMMA_ENABLE;
2674
2675 dspcntr |= DISPLAY_PLANE_ENABLE;
2676
2677 if (INTEL_INFO(dev)->gen < 4) {
2678 if (intel_crtc->pipe == PIPE_B)
2679 dspcntr |= DISPPLANE_SEL_PIPE_B;
2680
2681 /* pipesrc and dspsize control the size that is scaled from,
2682 * which should always be the user's requested size.
2683 */
2684 I915_WRITE(DSPSIZE(plane),
2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
2687 I915_WRITE(DSPPOS(plane), 0);
2688 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2689 I915_WRITE(PRIMSIZE(plane),
2690 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2691 (intel_crtc->config->pipe_src_w - 1));
2692 I915_WRITE(PRIMPOS(plane), 0);
2693 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2694 }
2695
2696 switch (fb->pixel_format) {
2697 case DRM_FORMAT_C8:
2698 dspcntr |= DISPPLANE_8BPP;
2699 break;
2700 case DRM_FORMAT_XRGB1555:
2701 dspcntr |= DISPPLANE_BGRX555;
2702 break;
2703 case DRM_FORMAT_RGB565:
2704 dspcntr |= DISPPLANE_BGRX565;
2705 break;
2706 case DRM_FORMAT_XRGB8888:
2707 case DRM_FORMAT_ARGB8888:
2708 dspcntr |= DISPPLANE_BGRX888;
2709 break;
2710 case DRM_FORMAT_XBGR8888:
2711 case DRM_FORMAT_ABGR8888:
2712 dspcntr |= DISPPLANE_RGBX888;
2713 break;
2714 case DRM_FORMAT_XRGB2101010:
2715 dspcntr |= DISPPLANE_BGRX101010;
2716 break;
2717 case DRM_FORMAT_XBGR2101010:
2718 dspcntr |= DISPPLANE_RGBX101010;
2719 break;
2720 default:
2721 BUG();
2722 }
2723
2724 if (INTEL_INFO(dev)->gen >= 4 &&
2725 obj->tiling_mode != I915_TILING_NONE)
2726 dspcntr |= DISPPLANE_TILED;
2727
2728 if (IS_G4X(dev))
2729 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2730
2731 linear_offset = y * fb->pitches[0] + x * pixel_size;
2732
2733 if (INTEL_INFO(dev)->gen >= 4) {
2734 intel_crtc->dspaddr_offset =
2735 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2736 pixel_size,
2737 fb->pitches[0]);
2738 linear_offset -= intel_crtc->dspaddr_offset;
2739 } else {
2740 intel_crtc->dspaddr_offset = linear_offset;
2741 }
2742
2743 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2744 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746 x += (intel_crtc->config->pipe_src_w - 1);
2747 y += (intel_crtc->config->pipe_src_h - 1);
2748
2749 /* Finding the last pixel of the last line of the display
2750 data and adding to linear_offset*/
2751 linear_offset +=
2752 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2753 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2754 }
2755
2756 I915_WRITE(reg, dspcntr);
2757
2758 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2759 if (INTEL_INFO(dev)->gen >= 4) {
2760 I915_WRITE(DSPSURF(plane),
2761 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2762 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2763 I915_WRITE(DSPLINOFF(plane), linear_offset);
2764 } else
2765 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2766 POSTING_READ(reg);
2767 }
2768
2769 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2770 struct drm_framebuffer *fb,
2771 int x, int y)
2772 {
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 struct drm_plane *primary = crtc->primary;
2777 bool visible = to_intel_plane_state(primary->state)->visible;
2778 struct drm_i915_gem_object *obj;
2779 int plane = intel_crtc->plane;
2780 unsigned long linear_offset;
2781 u32 dspcntr;
2782 u32 reg = DSPCNTR(plane);
2783 int pixel_size;
2784
2785 if (!visible || !fb) {
2786 I915_WRITE(reg, 0);
2787 I915_WRITE(DSPSURF(plane), 0);
2788 POSTING_READ(reg);
2789 return;
2790 }
2791
2792 obj = intel_fb_obj(fb);
2793 if (WARN_ON(obj == NULL))
2794 return;
2795
2796 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2797
2798 dspcntr = DISPPLANE_GAMMA_ENABLE;
2799
2800 dspcntr |= DISPLAY_PLANE_ENABLE;
2801
2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2804
2805 switch (fb->pixel_format) {
2806 case DRM_FORMAT_C8:
2807 dspcntr |= DISPPLANE_8BPP;
2808 break;
2809 case DRM_FORMAT_RGB565:
2810 dspcntr |= DISPPLANE_BGRX565;
2811 break;
2812 case DRM_FORMAT_XRGB8888:
2813 case DRM_FORMAT_ARGB8888:
2814 dspcntr |= DISPPLANE_BGRX888;
2815 break;
2816 case DRM_FORMAT_XBGR8888:
2817 case DRM_FORMAT_ABGR8888:
2818 dspcntr |= DISPPLANE_RGBX888;
2819 break;
2820 case DRM_FORMAT_XRGB2101010:
2821 dspcntr |= DISPPLANE_BGRX101010;
2822 break;
2823 case DRM_FORMAT_XBGR2101010:
2824 dspcntr |= DISPPLANE_RGBX101010;
2825 break;
2826 default:
2827 BUG();
2828 }
2829
2830 if (obj->tiling_mode != I915_TILING_NONE)
2831 dspcntr |= DISPPLANE_TILED;
2832
2833 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2834 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2835
2836 linear_offset = y * fb->pitches[0] + x * pixel_size;
2837 intel_crtc->dspaddr_offset =
2838 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2839 pixel_size,
2840 fb->pitches[0]);
2841 linear_offset -= intel_crtc->dspaddr_offset;
2842 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2843 dspcntr |= DISPPLANE_ROTATE_180;
2844
2845 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2846 x += (intel_crtc->config->pipe_src_w - 1);
2847 y += (intel_crtc->config->pipe_src_h - 1);
2848
2849 /* Finding the last pixel of the last line of the display
2850 data and adding to linear_offset*/
2851 linear_offset +=
2852 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2853 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2854 }
2855 }
2856
2857 I915_WRITE(reg, dspcntr);
2858
2859 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2860 I915_WRITE(DSPSURF(plane),
2861 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2862 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2863 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2864 } else {
2865 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2866 I915_WRITE(DSPLINOFF(plane), linear_offset);
2867 }
2868 POSTING_READ(reg);
2869 }
2870
2871 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2872 uint32_t pixel_format)
2873 {
2874 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2875
2876 /*
2877 * The stride is either expressed as a multiple of 64 bytes
2878 * chunks for linear buffers or in number of tiles for tiled
2879 * buffers.
2880 */
2881 switch (fb_modifier) {
2882 case DRM_FORMAT_MOD_NONE:
2883 return 64;
2884 case I915_FORMAT_MOD_X_TILED:
2885 if (INTEL_INFO(dev)->gen == 2)
2886 return 128;
2887 return 512;
2888 case I915_FORMAT_MOD_Y_TILED:
2889 /* No need to check for old gens and Y tiling since this is
2890 * about the display engine and those will be blocked before
2891 * we get here.
2892 */
2893 return 128;
2894 case I915_FORMAT_MOD_Yf_TILED:
2895 if (bits_per_pixel == 8)
2896 return 64;
2897 else
2898 return 128;
2899 default:
2900 MISSING_CASE(fb_modifier);
2901 return 64;
2902 }
2903 }
2904
2905 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2906 struct drm_i915_gem_object *obj)
2907 {
2908 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2909
2910 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2911 view = &i915_ggtt_view_rotated;
2912
2913 return i915_gem_obj_ggtt_offset_view(obj, view);
2914 }
2915
2916 /*
2917 * This function detaches (aka. unbinds) unused scalers in hardware
2918 */
2919 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2920 {
2921 struct drm_device *dev;
2922 struct drm_i915_private *dev_priv;
2923 struct intel_crtc_scaler_state *scaler_state;
2924 int i;
2925
2926 if (!intel_crtc || !intel_crtc->config)
2927 return;
2928
2929 dev = intel_crtc->base.dev;
2930 dev_priv = dev->dev_private;
2931 scaler_state = &intel_crtc->config->scaler_state;
2932
2933 /* loop through and disable scalers that aren't in use */
2934 for (i = 0; i < intel_crtc->num_scalers; i++) {
2935 if (!scaler_state->scalers[i].in_use) {
2936 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2937 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2938 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2939 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2940 intel_crtc->base.base.id, intel_crtc->pipe, i);
2941 }
2942 }
2943 }
2944
2945 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 {
2947 switch (pixel_format) {
2948 case DRM_FORMAT_C8:
2949 return PLANE_CTL_FORMAT_INDEXED;
2950 case DRM_FORMAT_RGB565:
2951 return PLANE_CTL_FORMAT_RGB_565;
2952 case DRM_FORMAT_XBGR8888:
2953 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2954 case DRM_FORMAT_XRGB8888:
2955 return PLANE_CTL_FORMAT_XRGB_8888;
2956 /*
2957 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2958 * to be already pre-multiplied. We need to add a knob (or a different
2959 * DRM_FORMAT) for user-space to configure that.
2960 */
2961 case DRM_FORMAT_ABGR8888:
2962 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2963 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2964 case DRM_FORMAT_ARGB8888:
2965 return PLANE_CTL_FORMAT_XRGB_8888 |
2966 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2967 case DRM_FORMAT_XRGB2101010:
2968 return PLANE_CTL_FORMAT_XRGB_2101010;
2969 case DRM_FORMAT_XBGR2101010:
2970 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2971 case DRM_FORMAT_YUYV:
2972 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2973 case DRM_FORMAT_YVYU:
2974 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2975 case DRM_FORMAT_UYVY:
2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2977 case DRM_FORMAT_VYUY:
2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979 default:
2980 MISSING_CASE(pixel_format);
2981 }
2982
2983 return 0;
2984 }
2985
2986 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 {
2988 switch (fb_modifier) {
2989 case DRM_FORMAT_MOD_NONE:
2990 break;
2991 case I915_FORMAT_MOD_X_TILED:
2992 return PLANE_CTL_TILED_X;
2993 case I915_FORMAT_MOD_Y_TILED:
2994 return PLANE_CTL_TILED_Y;
2995 case I915_FORMAT_MOD_Yf_TILED:
2996 return PLANE_CTL_TILED_YF;
2997 default:
2998 MISSING_CASE(fb_modifier);
2999 }
3000
3001 return 0;
3002 }
3003
3004 u32 skl_plane_ctl_rotation(unsigned int rotation)
3005 {
3006 switch (rotation) {
3007 case BIT(DRM_ROTATE_0):
3008 break;
3009 case BIT(DRM_ROTATE_90):
3010 return PLANE_CTL_ROTATE_90;
3011 case BIT(DRM_ROTATE_180):
3012 return PLANE_CTL_ROTATE_180;
3013 case BIT(DRM_ROTATE_270):
3014 return PLANE_CTL_ROTATE_270;
3015 default:
3016 MISSING_CASE(rotation);
3017 }
3018
3019 return 0;
3020 }
3021
3022 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3023 struct drm_framebuffer *fb,
3024 int x, int y)
3025 {
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 struct drm_plane *plane = crtc->primary;
3030 bool visible = to_intel_plane_state(plane->state)->visible;
3031 struct drm_i915_gem_object *obj;
3032 int pipe = intel_crtc->pipe;
3033 u32 plane_ctl, stride_div, stride;
3034 u32 tile_height, plane_offset, plane_size;
3035 unsigned int rotation;
3036 int x_offset, y_offset;
3037 unsigned long surf_addr;
3038 struct intel_crtc_state *crtc_state = intel_crtc->config;
3039 struct intel_plane_state *plane_state;
3040 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3041 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3042 int scaler_id = -1;
3043
3044 plane_state = to_intel_plane_state(plane->state);
3045
3046 if (!visible || !fb) {
3047 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3048 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3049 POSTING_READ(PLANE_CTL(pipe, 0));
3050 return;
3051 }
3052
3053 plane_ctl = PLANE_CTL_ENABLE |
3054 PLANE_CTL_PIPE_GAMMA_ENABLE |
3055 PLANE_CTL_PIPE_CSC_ENABLE;
3056
3057 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3058 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3059 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3060
3061 rotation = plane->state->rotation;
3062 plane_ctl |= skl_plane_ctl_rotation(rotation);
3063
3064 obj = intel_fb_obj(fb);
3065 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3066 fb->pixel_format);
3067 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3068
3069 /*
3070 * FIXME: intel_plane_state->src, dst aren't set when transitional
3071 * update_plane helpers are called from legacy paths.
3072 * Once full atomic crtc is available, below check can be avoided.
3073 */
3074 if (drm_rect_width(&plane_state->src)) {
3075 scaler_id = plane_state->scaler_id;
3076 src_x = plane_state->src.x1 >> 16;
3077 src_y = plane_state->src.y1 >> 16;
3078 src_w = drm_rect_width(&plane_state->src) >> 16;
3079 src_h = drm_rect_height(&plane_state->src) >> 16;
3080 dst_x = plane_state->dst.x1;
3081 dst_y = plane_state->dst.y1;
3082 dst_w = drm_rect_width(&plane_state->dst);
3083 dst_h = drm_rect_height(&plane_state->dst);
3084
3085 WARN_ON(x != src_x || y != src_y);
3086 } else {
3087 src_w = intel_crtc->config->pipe_src_w;
3088 src_h = intel_crtc->config->pipe_src_h;
3089 }
3090
3091 if (intel_rotation_90_or_270(rotation)) {
3092 /* stride = Surface height in tiles */
3093 tile_height = intel_tile_height(dev, fb->pixel_format,
3094 fb->modifier[0]);
3095 stride = DIV_ROUND_UP(fb->height, tile_height);
3096 x_offset = stride * tile_height - y - src_h;
3097 y_offset = x;
3098 plane_size = (src_w - 1) << 16 | (src_h - 1);
3099 } else {
3100 stride = fb->pitches[0] / stride_div;
3101 x_offset = x;
3102 y_offset = y;
3103 plane_size = (src_h - 1) << 16 | (src_w - 1);
3104 }
3105 plane_offset = y_offset << 16 | x_offset;
3106
3107 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3108 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3109 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3110 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3111
3112 if (scaler_id >= 0) {
3113 uint32_t ps_ctrl = 0;
3114
3115 WARN_ON(!dst_w || !dst_h);
3116 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3117 crtc_state->scaler_state.scalers[scaler_id].mode;
3118 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3119 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3120 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3121 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3122 I915_WRITE(PLANE_POS(pipe, 0), 0);
3123 } else {
3124 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3125 }
3126
3127 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3128
3129 POSTING_READ(PLANE_SURF(pipe, 0));
3130 }
3131
3132 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3133 static int
3134 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3135 int x, int y, enum mode_set_atomic state)
3136 {
3137 struct drm_device *dev = crtc->dev;
3138 struct drm_i915_private *dev_priv = dev->dev_private;
3139
3140 if (dev_priv->display.disable_fbc)
3141 dev_priv->display.disable_fbc(dev);
3142
3143 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3144
3145 return 0;
3146 }
3147
3148 static void intel_complete_page_flips(struct drm_device *dev)
3149 {
3150 struct drm_crtc *crtc;
3151
3152 for_each_crtc(dev, crtc) {
3153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154 enum plane plane = intel_crtc->plane;
3155
3156 intel_prepare_page_flip(dev, plane);
3157 intel_finish_page_flip_plane(dev, plane);
3158 }
3159 }
3160
3161 static void intel_update_primary_planes(struct drm_device *dev)
3162 {
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct drm_crtc *crtc;
3165
3166 for_each_crtc(dev, crtc) {
3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168
3169 drm_modeset_lock(&crtc->mutex, NULL);
3170 /*
3171 * FIXME: Once we have proper support for primary planes (and
3172 * disabling them without disabling the entire crtc) allow again
3173 * a NULL crtc->primary->fb.
3174 */
3175 if (intel_crtc->active && crtc->primary->fb)
3176 dev_priv->display.update_primary_plane(crtc,
3177 crtc->primary->fb,
3178 crtc->x,
3179 crtc->y);
3180 drm_modeset_unlock(&crtc->mutex);
3181 }
3182 }
3183
3184 void intel_crtc_reset(struct intel_crtc *crtc)
3185 {
3186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3187
3188 if (!crtc->active)
3189 return;
3190
3191 intel_crtc_disable_planes(&crtc->base);
3192 dev_priv->display.crtc_disable(&crtc->base);
3193 dev_priv->display.crtc_enable(&crtc->base);
3194 intel_crtc_enable_planes(&crtc->base);
3195 }
3196
3197 void intel_prepare_reset(struct drm_device *dev)
3198 {
3199 struct drm_i915_private *dev_priv = to_i915(dev);
3200 struct intel_crtc *crtc;
3201
3202 /* no reset support for gen2 */
3203 if (IS_GEN2(dev))
3204 return;
3205
3206 /* reset doesn't touch the display */
3207 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3208 return;
3209
3210 drm_modeset_lock_all(dev);
3211
3212 /*
3213 * Disabling the crtcs gracefully seems nicer. Also the
3214 * g33 docs say we should at least disable all the planes.
3215 */
3216 for_each_intel_crtc(dev, crtc) {
3217 if (!crtc->active)
3218 continue;
3219
3220 intel_crtc_disable_planes(&crtc->base);
3221 dev_priv->display.crtc_disable(&crtc->base);
3222 }
3223 }
3224
3225 void intel_finish_reset(struct drm_device *dev)
3226 {
3227 struct drm_i915_private *dev_priv = to_i915(dev);
3228
3229 /*
3230 * Flips in the rings will be nuked by the reset,
3231 * so complete all pending flips so that user space
3232 * will get its events and not get stuck.
3233 */
3234 intel_complete_page_flips(dev);
3235
3236 /* no reset support for gen2 */
3237 if (IS_GEN2(dev))
3238 return;
3239
3240 /* reset doesn't touch the display */
3241 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3242 /*
3243 * Flips in the rings have been nuked by the reset,
3244 * so update the base address of all primary
3245 * planes to the the last fb to make sure we're
3246 * showing the correct fb after a reset.
3247 */
3248 intel_update_primary_planes(dev);
3249 return;
3250 }
3251
3252 /*
3253 * The display has been reset as well,
3254 * so need a full re-initialization.
3255 */
3256 intel_runtime_pm_disable_interrupts(dev_priv);
3257 intel_runtime_pm_enable_interrupts(dev_priv);
3258
3259 intel_modeset_init_hw(dev);
3260
3261 spin_lock_irq(&dev_priv->irq_lock);
3262 if (dev_priv->display.hpd_irq_setup)
3263 dev_priv->display.hpd_irq_setup(dev);
3264 spin_unlock_irq(&dev_priv->irq_lock);
3265
3266 intel_modeset_setup_hw_state(dev, true);
3267
3268 intel_hpd_init(dev_priv);
3269
3270 drm_modeset_unlock_all(dev);
3271 }
3272
3273 static void
3274 intel_finish_fb(struct drm_framebuffer *old_fb)
3275 {
3276 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3277 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3278 bool was_interruptible = dev_priv->mm.interruptible;
3279 int ret;
3280
3281 /* Big Hammer, we also need to ensure that any pending
3282 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3283 * current scanout is retired before unpinning the old
3284 * framebuffer. Note that we rely on userspace rendering
3285 * into the buffer attached to the pipe they are waiting
3286 * on. If not, userspace generates a GPU hang with IPEHR
3287 * point to the MI_WAIT_FOR_EVENT.
3288 *
3289 * This should only fail upon a hung GPU, in which case we
3290 * can safely continue.
3291 */
3292 dev_priv->mm.interruptible = false;
3293 ret = i915_gem_object_wait_rendering(obj, true);
3294 dev_priv->mm.interruptible = was_interruptible;
3295
3296 WARN_ON(ret);
3297 }
3298
3299 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3300 {
3301 struct drm_device *dev = crtc->dev;
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304 bool pending;
3305
3306 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3307 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3308 return false;
3309
3310 spin_lock_irq(&dev->event_lock);
3311 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3312 spin_unlock_irq(&dev->event_lock);
3313
3314 return pending;
3315 }
3316
3317 static void intel_update_pipe_size(struct intel_crtc *crtc)
3318 {
3319 struct drm_device *dev = crtc->base.dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 const struct drm_display_mode *adjusted_mode;
3322
3323 if (!i915.fastboot)
3324 return;
3325
3326 /*
3327 * Update pipe size and adjust fitter if needed: the reason for this is
3328 * that in compute_mode_changes we check the native mode (not the pfit
3329 * mode) to see if we can flip rather than do a full mode set. In the
3330 * fastboot case, we'll flip, but if we don't update the pipesrc and
3331 * pfit state, we'll end up with a big fb scanned out into the wrong
3332 * sized surface.
3333 *
3334 * To fix this properly, we need to hoist the checks up into
3335 * compute_mode_changes (or above), check the actual pfit state and
3336 * whether the platform allows pfit disable with pipe active, and only
3337 * then update the pipesrc and pfit state, even on the flip path.
3338 */
3339
3340 adjusted_mode = &crtc->config->base.adjusted_mode;
3341
3342 I915_WRITE(PIPESRC(crtc->pipe),
3343 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3344 (adjusted_mode->crtc_vdisplay - 1));
3345 if (!crtc->config->pch_pfit.enabled &&
3346 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3347 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3348 I915_WRITE(PF_CTL(crtc->pipe), 0);
3349 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3350 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3351 }
3352 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3353 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3354 }
3355
3356 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3357 {
3358 struct drm_device *dev = crtc->dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361 int pipe = intel_crtc->pipe;
3362 u32 reg, temp;
3363
3364 /* enable normal train */
3365 reg = FDI_TX_CTL(pipe);
3366 temp = I915_READ(reg);
3367 if (IS_IVYBRIDGE(dev)) {
3368 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3369 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3370 } else {
3371 temp &= ~FDI_LINK_TRAIN_NONE;
3372 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3373 }
3374 I915_WRITE(reg, temp);
3375
3376 reg = FDI_RX_CTL(pipe);
3377 temp = I915_READ(reg);
3378 if (HAS_PCH_CPT(dev)) {
3379 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3380 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3381 } else {
3382 temp &= ~FDI_LINK_TRAIN_NONE;
3383 temp |= FDI_LINK_TRAIN_NONE;
3384 }
3385 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3386
3387 /* wait one idle pattern time */
3388 POSTING_READ(reg);
3389 udelay(1000);
3390
3391 /* IVB wants error correction enabled */
3392 if (IS_IVYBRIDGE(dev))
3393 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3394 FDI_FE_ERRC_ENABLE);
3395 }
3396
3397 /* The FDI link training functions for ILK/Ibexpeak. */
3398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3399 {
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3403 int pipe = intel_crtc->pipe;
3404 u32 reg, temp, tries;
3405
3406 /* FDI needs bits from pipe first */
3407 assert_pipe_enabled(dev_priv, pipe);
3408
3409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3410 for train result */
3411 reg = FDI_RX_IMR(pipe);
3412 temp = I915_READ(reg);
3413 temp &= ~FDI_RX_SYMBOL_LOCK;
3414 temp &= ~FDI_RX_BIT_LOCK;
3415 I915_WRITE(reg, temp);
3416 I915_READ(reg);
3417 udelay(150);
3418
3419 /* enable CPU FDI TX and PCH FDI RX */
3420 reg = FDI_TX_CTL(pipe);
3421 temp = I915_READ(reg);
3422 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3423 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
3426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3427
3428 reg = FDI_RX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 temp &= ~FDI_LINK_TRAIN_NONE;
3431 temp |= FDI_LINK_TRAIN_PATTERN_1;
3432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3433
3434 POSTING_READ(reg);
3435 udelay(150);
3436
3437 /* Ironlake workaround, enable clock pointer after FDI enable*/
3438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3439 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3440 FDI_RX_PHASE_SYNC_POINTER_EN);
3441
3442 reg = FDI_RX_IIR(pipe);
3443 for (tries = 0; tries < 5; tries++) {
3444 temp = I915_READ(reg);
3445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3446
3447 if ((temp & FDI_RX_BIT_LOCK)) {
3448 DRM_DEBUG_KMS("FDI train 1 done.\n");
3449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3450 break;
3451 }
3452 }
3453 if (tries == 5)
3454 DRM_ERROR("FDI train 1 fail!\n");
3455
3456 /* Train 2 */
3457 reg = FDI_TX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
3461 I915_WRITE(reg, temp);
3462
3463 reg = FDI_RX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~FDI_LINK_TRAIN_NONE;
3466 temp |= FDI_LINK_TRAIN_PATTERN_2;
3467 I915_WRITE(reg, temp);
3468
3469 POSTING_READ(reg);
3470 udelay(150);
3471
3472 reg = FDI_RX_IIR(pipe);
3473 for (tries = 0; tries < 5; tries++) {
3474 temp = I915_READ(reg);
3475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3476
3477 if (temp & FDI_RX_SYMBOL_LOCK) {
3478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3479 DRM_DEBUG_KMS("FDI train 2 done.\n");
3480 break;
3481 }
3482 }
3483 if (tries == 5)
3484 DRM_ERROR("FDI train 2 fail!\n");
3485
3486 DRM_DEBUG_KMS("FDI train done\n");
3487
3488 }
3489
3490 static const int snb_b_fdi_train_param[] = {
3491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3495 };
3496
3497 /* The FDI link training functions for SNB/Cougarpoint. */
3498 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3499 {
3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3503 int pipe = intel_crtc->pipe;
3504 u32 reg, temp, i, retry;
3505
3506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3507 for train result */
3508 reg = FDI_RX_IMR(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~FDI_RX_SYMBOL_LOCK;
3511 temp &= ~FDI_RX_BIT_LOCK;
3512 I915_WRITE(reg, temp);
3513
3514 POSTING_READ(reg);
3515 udelay(150);
3516
3517 /* enable CPU FDI TX and PCH FDI RX */
3518 reg = FDI_TX_CTL(pipe);
3519 temp = I915_READ(reg);
3520 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3521 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3522 temp &= ~FDI_LINK_TRAIN_NONE;
3523 temp |= FDI_LINK_TRAIN_PATTERN_1;
3524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3525 /* SNB-B */
3526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3528
3529 I915_WRITE(FDI_RX_MISC(pipe),
3530 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3531
3532 reg = FDI_RX_CTL(pipe);
3533 temp = I915_READ(reg);
3534 if (HAS_PCH_CPT(dev)) {
3535 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3536 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3537 } else {
3538 temp &= ~FDI_LINK_TRAIN_NONE;
3539 temp |= FDI_LINK_TRAIN_PATTERN_1;
3540 }
3541 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3542
3543 POSTING_READ(reg);
3544 udelay(150);
3545
3546 for (i = 0; i < 4; i++) {
3547 reg = FDI_TX_CTL(pipe);
3548 temp = I915_READ(reg);
3549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3550 temp |= snb_b_fdi_train_param[i];
3551 I915_WRITE(reg, temp);
3552
3553 POSTING_READ(reg);
3554 udelay(500);
3555
3556 for (retry = 0; retry < 5; retry++) {
3557 reg = FDI_RX_IIR(pipe);
3558 temp = I915_READ(reg);
3559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3560 if (temp & FDI_RX_BIT_LOCK) {
3561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3562 DRM_DEBUG_KMS("FDI train 1 done.\n");
3563 break;
3564 }
3565 udelay(50);
3566 }
3567 if (retry < 5)
3568 break;
3569 }
3570 if (i == 4)
3571 DRM_ERROR("FDI train 1 fail!\n");
3572
3573 /* Train 2 */
3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~FDI_LINK_TRAIN_NONE;
3577 temp |= FDI_LINK_TRAIN_PATTERN_2;
3578 if (IS_GEN6(dev)) {
3579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3580 /* SNB-B */
3581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3582 }
3583 I915_WRITE(reg, temp);
3584
3585 reg = FDI_RX_CTL(pipe);
3586 temp = I915_READ(reg);
3587 if (HAS_PCH_CPT(dev)) {
3588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3589 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3590 } else {
3591 temp &= ~FDI_LINK_TRAIN_NONE;
3592 temp |= FDI_LINK_TRAIN_PATTERN_2;
3593 }
3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
3597 udelay(150);
3598
3599 for (i = 0; i < 4; i++) {
3600 reg = FDI_TX_CTL(pipe);
3601 temp = I915_READ(reg);
3602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3603 temp |= snb_b_fdi_train_param[i];
3604 I915_WRITE(reg, temp);
3605
3606 POSTING_READ(reg);
3607 udelay(500);
3608
3609 for (retry = 0; retry < 5; retry++) {
3610 reg = FDI_RX_IIR(pipe);
3611 temp = I915_READ(reg);
3612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3613 if (temp & FDI_RX_SYMBOL_LOCK) {
3614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3615 DRM_DEBUG_KMS("FDI train 2 done.\n");
3616 break;
3617 }
3618 udelay(50);
3619 }
3620 if (retry < 5)
3621 break;
3622 }
3623 if (i == 4)
3624 DRM_ERROR("FDI train 2 fail!\n");
3625
3626 DRM_DEBUG_KMS("FDI train done.\n");
3627 }
3628
3629 /* Manual link training for Ivy Bridge A0 parts */
3630 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3631 {
3632 struct drm_device *dev = crtc->dev;
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3635 int pipe = intel_crtc->pipe;
3636 u32 reg, temp, i, j;
3637
3638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3639 for train result */
3640 reg = FDI_RX_IMR(pipe);
3641 temp = I915_READ(reg);
3642 temp &= ~FDI_RX_SYMBOL_LOCK;
3643 temp &= ~FDI_RX_BIT_LOCK;
3644 I915_WRITE(reg, temp);
3645
3646 POSTING_READ(reg);
3647 udelay(150);
3648
3649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3650 I915_READ(FDI_RX_IIR(pipe)));
3651
3652 /* Try each vswing and preemphasis setting twice before moving on */
3653 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3654 /* disable first in case we need to retry */
3655 reg = FDI_TX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3658 temp &= ~FDI_TX_ENABLE;
3659 I915_WRITE(reg, temp);
3660
3661 reg = FDI_RX_CTL(pipe);
3662 temp = I915_READ(reg);
3663 temp &= ~FDI_LINK_TRAIN_AUTO;
3664 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3665 temp &= ~FDI_RX_ENABLE;
3666 I915_WRITE(reg, temp);
3667
3668 /* enable CPU FDI TX and PCH FDI RX */
3669 reg = FDI_TX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3672 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3673 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3675 temp |= snb_b_fdi_train_param[j/2];
3676 temp |= FDI_COMPOSITE_SYNC;
3677 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3678
3679 I915_WRITE(FDI_RX_MISC(pipe),
3680 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3681
3682 reg = FDI_RX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3685 temp |= FDI_COMPOSITE_SYNC;
3686 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3687
3688 POSTING_READ(reg);
3689 udelay(1); /* should be 0.5us */
3690
3691 for (i = 0; i < 4; i++) {
3692 reg = FDI_RX_IIR(pipe);
3693 temp = I915_READ(reg);
3694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3695
3696 if (temp & FDI_RX_BIT_LOCK ||
3697 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3698 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3699 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3700 i);
3701 break;
3702 }
3703 udelay(1); /* should be 0.5us */
3704 }
3705 if (i == 4) {
3706 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3707 continue;
3708 }
3709
3710 /* Train 2 */
3711 reg = FDI_TX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3715 I915_WRITE(reg, temp);
3716
3717 reg = FDI_RX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3720 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3721 I915_WRITE(reg, temp);
3722
3723 POSTING_READ(reg);
3724 udelay(2); /* should be 1.5us */
3725
3726 for (i = 0; i < 4; i++) {
3727 reg = FDI_RX_IIR(pipe);
3728 temp = I915_READ(reg);
3729 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3730
3731 if (temp & FDI_RX_SYMBOL_LOCK ||
3732 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3733 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3734 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3735 i);
3736 goto train_done;
3737 }
3738 udelay(2); /* should be 1.5us */
3739 }
3740 if (i == 4)
3741 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3742 }
3743
3744 train_done:
3745 DRM_DEBUG_KMS("FDI train done.\n");
3746 }
3747
3748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3749 {
3750 struct drm_device *dev = intel_crtc->base.dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 int pipe = intel_crtc->pipe;
3753 u32 reg, temp;
3754
3755
3756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3760 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3763
3764 POSTING_READ(reg);
3765 udelay(200);
3766
3767 /* Switch from Rawclk to PCDclk */
3768 temp = I915_READ(reg);
3769 I915_WRITE(reg, temp | FDI_PCDCLK);
3770
3771 POSTING_READ(reg);
3772 udelay(200);
3773
3774 /* Enable CPU FDI TX PLL, always on for Ironlake */
3775 reg = FDI_TX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3779
3780 POSTING_READ(reg);
3781 udelay(100);
3782 }
3783 }
3784
3785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3786 {
3787 struct drm_device *dev = intel_crtc->base.dev;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 int pipe = intel_crtc->pipe;
3790 u32 reg, temp;
3791
3792 /* Switch from PCDclk to Rawclk */
3793 reg = FDI_RX_CTL(pipe);
3794 temp = I915_READ(reg);
3795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3796
3797 /* Disable CPU FDI TX PLL */
3798 reg = FDI_TX_CTL(pipe);
3799 temp = I915_READ(reg);
3800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3801
3802 POSTING_READ(reg);
3803 udelay(100);
3804
3805 reg = FDI_RX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3808
3809 /* Wait for the clocks to turn off. */
3810 POSTING_READ(reg);
3811 udelay(100);
3812 }
3813
3814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3815 {
3816 struct drm_device *dev = crtc->dev;
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3819 int pipe = intel_crtc->pipe;
3820 u32 reg, temp;
3821
3822 /* disable CPU FDI tx and PCH FDI rx */
3823 reg = FDI_TX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3826 POSTING_READ(reg);
3827
3828 reg = FDI_RX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 temp &= ~(0x7 << 16);
3831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3833
3834 POSTING_READ(reg);
3835 udelay(100);
3836
3837 /* Ironlake workaround, disable clock pointer after downing FDI */
3838 if (HAS_PCH_IBX(dev))
3839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3840
3841 /* still set train pattern 1 */
3842 reg = FDI_TX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 temp &= ~FDI_LINK_TRAIN_NONE;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1;
3846 I915_WRITE(reg, temp);
3847
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 if (HAS_PCH_CPT(dev)) {
3851 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3852 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3853 } else {
3854 temp &= ~FDI_LINK_TRAIN_NONE;
3855 temp |= FDI_LINK_TRAIN_PATTERN_1;
3856 }
3857 /* BPC in FDI rx is consistent with that in PIPECONF */
3858 temp &= ~(0x07 << 16);
3859 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3860 I915_WRITE(reg, temp);
3861
3862 POSTING_READ(reg);
3863 udelay(100);
3864 }
3865
3866 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3867 {
3868 struct intel_crtc *crtc;
3869
3870 /* Note that we don't need to be called with mode_config.lock here
3871 * as our list of CRTC objects is static for the lifetime of the
3872 * device and so cannot disappear as we iterate. Similarly, we can
3873 * happily treat the predicates as racy, atomic checks as userspace
3874 * cannot claim and pin a new fb without at least acquring the
3875 * struct_mutex and so serialising with us.
3876 */
3877 for_each_intel_crtc(dev, crtc) {
3878 if (atomic_read(&crtc->unpin_work_count) == 0)
3879 continue;
3880
3881 if (crtc->unpin_work)
3882 intel_wait_for_vblank(dev, crtc->pipe);
3883
3884 return true;
3885 }
3886
3887 return false;
3888 }
3889
3890 static void page_flip_completed(struct intel_crtc *intel_crtc)
3891 {
3892 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3893 struct intel_unpin_work *work = intel_crtc->unpin_work;
3894
3895 /* ensure that the unpin work is consistent wrt ->pending. */
3896 smp_rmb();
3897 intel_crtc->unpin_work = NULL;
3898
3899 if (work->event)
3900 drm_send_vblank_event(intel_crtc->base.dev,
3901 intel_crtc->pipe,
3902 work->event);
3903
3904 drm_crtc_vblank_put(&intel_crtc->base);
3905
3906 wake_up_all(&dev_priv->pending_flip_queue);
3907 queue_work(dev_priv->wq, &work->work);
3908
3909 trace_i915_flip_complete(intel_crtc->plane,
3910 work->pending_flip_obj);
3911 }
3912
3913 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3914 {
3915 struct drm_device *dev = crtc->dev;
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917
3918 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3919 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3920 !intel_crtc_has_pending_flip(crtc),
3921 60*HZ) == 0)) {
3922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3923
3924 spin_lock_irq(&dev->event_lock);
3925 if (intel_crtc->unpin_work) {
3926 WARN_ONCE(1, "Removing stuck page flip\n");
3927 page_flip_completed(intel_crtc);
3928 }
3929 spin_unlock_irq(&dev->event_lock);
3930 }
3931
3932 if (crtc->primary->fb) {
3933 mutex_lock(&dev->struct_mutex);
3934 intel_finish_fb(crtc->primary->fb);
3935 mutex_unlock(&dev->struct_mutex);
3936 }
3937 }
3938
3939 /* Program iCLKIP clock to the desired frequency */
3940 static void lpt_program_iclkip(struct drm_crtc *crtc)
3941 {
3942 struct drm_device *dev = crtc->dev;
3943 struct drm_i915_private *dev_priv = dev->dev_private;
3944 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3945 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3946 u32 temp;
3947
3948 mutex_lock(&dev_priv->dpio_lock);
3949
3950 /* It is necessary to ungate the pixclk gate prior to programming
3951 * the divisors, and gate it back when it is done.
3952 */
3953 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3954
3955 /* Disable SSCCTL */
3956 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3957 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3958 SBI_SSCCTL_DISABLE,
3959 SBI_ICLK);
3960
3961 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3962 if (clock == 20000) {
3963 auxdiv = 1;
3964 divsel = 0x41;
3965 phaseinc = 0x20;
3966 } else {
3967 /* The iCLK virtual clock root frequency is in MHz,
3968 * but the adjusted_mode->crtc_clock in in KHz. To get the
3969 * divisors, it is necessary to divide one by another, so we
3970 * convert the virtual clock precision to KHz here for higher
3971 * precision.
3972 */
3973 u32 iclk_virtual_root_freq = 172800 * 1000;
3974 u32 iclk_pi_range = 64;
3975 u32 desired_divisor, msb_divisor_value, pi_value;
3976
3977 desired_divisor = (iclk_virtual_root_freq / clock);
3978 msb_divisor_value = desired_divisor / iclk_pi_range;
3979 pi_value = desired_divisor % iclk_pi_range;
3980
3981 auxdiv = 0;
3982 divsel = msb_divisor_value - 2;
3983 phaseinc = pi_value;
3984 }
3985
3986 /* This should not happen with any sane values */
3987 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3988 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3989 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3990 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3991
3992 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3993 clock,
3994 auxdiv,
3995 divsel,
3996 phasedir,
3997 phaseinc);
3998
3999 /* Program SSCDIVINTPHASE6 */
4000 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4001 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4002 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4003 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4004 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4005 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4006 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4007 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4008
4009 /* Program SSCAUXDIV */
4010 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4011 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4012 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4013 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4014
4015 /* Enable modulator and associated divider */
4016 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4017 temp &= ~SBI_SSCCTL_DISABLE;
4018 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4019
4020 /* Wait for initialization time */
4021 udelay(24);
4022
4023 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4024
4025 mutex_unlock(&dev_priv->dpio_lock);
4026 }
4027
4028 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4029 enum pipe pch_transcoder)
4030 {
4031 struct drm_device *dev = crtc->base.dev;
4032 struct drm_i915_private *dev_priv = dev->dev_private;
4033 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4034
4035 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4036 I915_READ(HTOTAL(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4038 I915_READ(HBLANK(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4040 I915_READ(HSYNC(cpu_transcoder)));
4041
4042 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4043 I915_READ(VTOTAL(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4045 I915_READ(VBLANK(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4047 I915_READ(VSYNC(cpu_transcoder)));
4048 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4049 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4050 }
4051
4052 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4053 {
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 uint32_t temp;
4056
4057 temp = I915_READ(SOUTH_CHICKEN1);
4058 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4059 return;
4060
4061 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4062 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4063
4064 temp &= ~FDI_BC_BIFURCATION_SELECT;
4065 if (enable)
4066 temp |= FDI_BC_BIFURCATION_SELECT;
4067
4068 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4069 I915_WRITE(SOUTH_CHICKEN1, temp);
4070 POSTING_READ(SOUTH_CHICKEN1);
4071 }
4072
4073 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4074 {
4075 struct drm_device *dev = intel_crtc->base.dev;
4076
4077 switch (intel_crtc->pipe) {
4078 case PIPE_A:
4079 break;
4080 case PIPE_B:
4081 if (intel_crtc->config->fdi_lanes > 2)
4082 cpt_set_fdi_bc_bifurcation(dev, false);
4083 else
4084 cpt_set_fdi_bc_bifurcation(dev, true);
4085
4086 break;
4087 case PIPE_C:
4088 cpt_set_fdi_bc_bifurcation(dev, true);
4089
4090 break;
4091 default:
4092 BUG();
4093 }
4094 }
4095
4096 /*
4097 * Enable PCH resources required for PCH ports:
4098 * - PCH PLLs
4099 * - FDI training & RX/TX
4100 * - update transcoder timings
4101 * - DP transcoding bits
4102 * - transcoder
4103 */
4104 static void ironlake_pch_enable(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109 int pipe = intel_crtc->pipe;
4110 u32 reg, temp;
4111
4112 assert_pch_transcoder_disabled(dev_priv, pipe);
4113
4114 if (IS_IVYBRIDGE(dev))
4115 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4116
4117 /* Write the TU size bits before fdi link training, so that error
4118 * detection works. */
4119 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4120 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4121
4122 /* For PCH output, training FDI link */
4123 dev_priv->display.fdi_link_train(crtc);
4124
4125 /* We need to program the right clock selection before writing the pixel
4126 * mutliplier into the DPLL. */
4127 if (HAS_PCH_CPT(dev)) {
4128 u32 sel;
4129
4130 temp = I915_READ(PCH_DPLL_SEL);
4131 temp |= TRANS_DPLL_ENABLE(pipe);
4132 sel = TRANS_DPLLB_SEL(pipe);
4133 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4134 temp |= sel;
4135 else
4136 temp &= ~sel;
4137 I915_WRITE(PCH_DPLL_SEL, temp);
4138 }
4139
4140 /* XXX: pch pll's can be enabled any time before we enable the PCH
4141 * transcoder, and we actually should do this to not upset any PCH
4142 * transcoder that already use the clock when we share it.
4143 *
4144 * Note that enable_shared_dpll tries to do the right thing, but
4145 * get_shared_dpll unconditionally resets the pll - we need that to have
4146 * the right LVDS enable sequence. */
4147 intel_enable_shared_dpll(intel_crtc);
4148
4149 /* set transcoder timing, panel must allow it */
4150 assert_panel_unlocked(dev_priv, pipe);
4151 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4152
4153 intel_fdi_normal_train(crtc);
4154
4155 /* For PCH DP, enable TRANS_DP_CTL */
4156 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4157 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4158 reg = TRANS_DP_CTL(pipe);
4159 temp = I915_READ(reg);
4160 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4161 TRANS_DP_SYNC_MASK |
4162 TRANS_DP_BPC_MASK);
4163 temp |= (TRANS_DP_OUTPUT_ENABLE |
4164 TRANS_DP_ENH_FRAMING);
4165 temp |= bpc << 9; /* same format but at 11:9 */
4166
4167 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4168 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4169 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4170 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4171
4172 switch (intel_trans_dp_port_sel(crtc)) {
4173 case PCH_DP_B:
4174 temp |= TRANS_DP_PORT_SEL_B;
4175 break;
4176 case PCH_DP_C:
4177 temp |= TRANS_DP_PORT_SEL_C;
4178 break;
4179 case PCH_DP_D:
4180 temp |= TRANS_DP_PORT_SEL_D;
4181 break;
4182 default:
4183 BUG();
4184 }
4185
4186 I915_WRITE(reg, temp);
4187 }
4188
4189 ironlake_enable_pch_transcoder(dev_priv, pipe);
4190 }
4191
4192 static void lpt_pch_enable(struct drm_crtc *crtc)
4193 {
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4198
4199 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4200
4201 lpt_program_iclkip(crtc);
4202
4203 /* Set transcoder timing. */
4204 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4205
4206 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4207 }
4208
4209 void intel_put_shared_dpll(struct intel_crtc *crtc)
4210 {
4211 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4212
4213 if (pll == NULL)
4214 return;
4215
4216 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4217 WARN(1, "bad %s crtc mask\n", pll->name);
4218 return;
4219 }
4220
4221 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4222 if (pll->config.crtc_mask == 0) {
4223 WARN_ON(pll->on);
4224 WARN_ON(pll->active);
4225 }
4226
4227 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4228 }
4229
4230 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4231 struct intel_crtc_state *crtc_state)
4232 {
4233 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4234 struct intel_shared_dpll *pll;
4235 enum intel_dpll_id i;
4236
4237 if (HAS_PCH_IBX(dev_priv->dev)) {
4238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4239 i = (enum intel_dpll_id) crtc->pipe;
4240 pll = &dev_priv->shared_dplls[i];
4241
4242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4243 crtc->base.base.id, pll->name);
4244
4245 WARN_ON(pll->new_config->crtc_mask);
4246
4247 goto found;
4248 }
4249
4250 if (IS_BROXTON(dev_priv->dev)) {
4251 /* PLL is attached to port in bxt */
4252 struct intel_encoder *encoder;
4253 struct intel_digital_port *intel_dig_port;
4254
4255 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4256 if (WARN_ON(!encoder))
4257 return NULL;
4258
4259 intel_dig_port = enc_to_dig_port(&encoder->base);
4260 /* 1:1 mapping between ports and PLLs */
4261 i = (enum intel_dpll_id)intel_dig_port->port;
4262 pll = &dev_priv->shared_dplls[i];
4263 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4264 crtc->base.base.id, pll->name);
4265 WARN_ON(pll->new_config->crtc_mask);
4266
4267 goto found;
4268 }
4269
4270 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4271 pll = &dev_priv->shared_dplls[i];
4272
4273 /* Only want to check enabled timings first */
4274 if (pll->new_config->crtc_mask == 0)
4275 continue;
4276
4277 if (memcmp(&crtc_state->dpll_hw_state,
4278 &pll->new_config->hw_state,
4279 sizeof(pll->new_config->hw_state)) == 0) {
4280 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4281 crtc->base.base.id, pll->name,
4282 pll->new_config->crtc_mask,
4283 pll->active);
4284 goto found;
4285 }
4286 }
4287
4288 /* Ok no matching timings, maybe there's a free one? */
4289 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4290 pll = &dev_priv->shared_dplls[i];
4291 if (pll->new_config->crtc_mask == 0) {
4292 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4293 crtc->base.base.id, pll->name);
4294 goto found;
4295 }
4296 }
4297
4298 return NULL;
4299
4300 found:
4301 if (pll->new_config->crtc_mask == 0)
4302 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4303
4304 crtc_state->shared_dpll = i;
4305 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4306 pipe_name(crtc->pipe));
4307
4308 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4309
4310 return pll;
4311 }
4312
4313 /**
4314 * intel_shared_dpll_start_config - start a new PLL staged config
4315 * @dev_priv: DRM device
4316 * @clear_pipes: mask of pipes that will have their PLLs freed
4317 *
4318 * Starts a new PLL staged config, copying the current config but
4319 * releasing the references of pipes specified in clear_pipes.
4320 */
4321 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4322 unsigned clear_pipes)
4323 {
4324 struct intel_shared_dpll *pll;
4325 enum intel_dpll_id i;
4326
4327 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4328 pll = &dev_priv->shared_dplls[i];
4329
4330 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4331 GFP_KERNEL);
4332 if (!pll->new_config)
4333 goto cleanup;
4334
4335 pll->new_config->crtc_mask &= ~clear_pipes;
4336 }
4337
4338 return 0;
4339
4340 cleanup:
4341 while (--i >= 0) {
4342 pll = &dev_priv->shared_dplls[i];
4343 kfree(pll->new_config);
4344 pll->new_config = NULL;
4345 }
4346
4347 return -ENOMEM;
4348 }
4349
4350 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4351 {
4352 struct intel_shared_dpll *pll;
4353 enum intel_dpll_id i;
4354
4355 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4356 pll = &dev_priv->shared_dplls[i];
4357
4358 WARN_ON(pll->new_config == &pll->config);
4359
4360 pll->config = *pll->new_config;
4361 kfree(pll->new_config);
4362 pll->new_config = NULL;
4363 }
4364 }
4365
4366 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4367 {
4368 struct intel_shared_dpll *pll;
4369 enum intel_dpll_id i;
4370
4371 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4372 pll = &dev_priv->shared_dplls[i];
4373
4374 WARN_ON(pll->new_config == &pll->config);
4375
4376 kfree(pll->new_config);
4377 pll->new_config = NULL;
4378 }
4379 }
4380
4381 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4382 {
4383 struct drm_i915_private *dev_priv = dev->dev_private;
4384 int dslreg = PIPEDSL(pipe);
4385 u32 temp;
4386
4387 temp = I915_READ(dslreg);
4388 udelay(500);
4389 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4390 if (wait_for(I915_READ(dslreg) != temp, 5))
4391 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4392 }
4393 }
4394
4395 /**
4396 * skl_update_scaler_users - Stages update to crtc's scaler state
4397 * @intel_crtc: crtc
4398 * @crtc_state: crtc_state
4399 * @plane: plane (NULL indicates crtc is requesting update)
4400 * @plane_state: plane's state
4401 * @force_detach: request unconditional detachment of scaler
4402 *
4403 * This function updates scaler state for requested plane or crtc.
4404 * To request scaler usage update for a plane, caller shall pass plane pointer.
4405 * To request scaler usage update for crtc, caller shall pass plane pointer
4406 * as NULL.
4407 *
4408 * Return
4409 * 0 - scaler_usage updated successfully
4410 * error - requested scaling cannot be supported or other error condition
4411 */
4412 int
4413 skl_update_scaler_users(
4414 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4415 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4416 int force_detach)
4417 {
4418 int need_scaling;
4419 int idx;
4420 int src_w, src_h, dst_w, dst_h;
4421 int *scaler_id;
4422 struct drm_framebuffer *fb;
4423 struct intel_crtc_scaler_state *scaler_state;
4424 unsigned int rotation;
4425
4426 if (!intel_crtc || !crtc_state)
4427 return 0;
4428
4429 scaler_state = &crtc_state->scaler_state;
4430
4431 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4432 fb = intel_plane ? plane_state->base.fb : NULL;
4433
4434 if (intel_plane) {
4435 src_w = drm_rect_width(&plane_state->src) >> 16;
4436 src_h = drm_rect_height(&plane_state->src) >> 16;
4437 dst_w = drm_rect_width(&plane_state->dst);
4438 dst_h = drm_rect_height(&plane_state->dst);
4439 scaler_id = &plane_state->scaler_id;
4440 rotation = plane_state->base.rotation;
4441 } else {
4442 struct drm_display_mode *adjusted_mode =
4443 &crtc_state->base.adjusted_mode;
4444 src_w = crtc_state->pipe_src_w;
4445 src_h = crtc_state->pipe_src_h;
4446 dst_w = adjusted_mode->hdisplay;
4447 dst_h = adjusted_mode->vdisplay;
4448 scaler_id = &scaler_state->scaler_id;
4449 rotation = DRM_ROTATE_0;
4450 }
4451
4452 need_scaling = intel_rotation_90_or_270(rotation) ?
4453 (src_h != dst_w || src_w != dst_h):
4454 (src_w != dst_w || src_h != dst_h);
4455
4456 /*
4457 * if plane is being disabled or scaler is no more required or force detach
4458 * - free scaler binded to this plane/crtc
4459 * - in order to do this, update crtc->scaler_usage
4460 *
4461 * Here scaler state in crtc_state is set free so that
4462 * scaler can be assigned to other user. Actual register
4463 * update to free the scaler is done in plane/panel-fit programming.
4464 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4465 */
4466 if (force_detach || !need_scaling || (intel_plane &&
4467 (!fb || !plane_state->visible))) {
4468 if (*scaler_id >= 0) {
4469 scaler_state->scaler_users &= ~(1 << idx);
4470 scaler_state->scalers[*scaler_id].in_use = 0;
4471
4472 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4473 "crtc_state = %p scaler_users = 0x%x\n",
4474 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4475 intel_plane ? intel_plane->base.base.id :
4476 intel_crtc->base.base.id, crtc_state,
4477 scaler_state->scaler_users);
4478 *scaler_id = -1;
4479 }
4480 return 0;
4481 }
4482
4483 /* range checks */
4484 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4485 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4486
4487 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4488 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4489 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4490 "size is out of scaler range\n",
4491 intel_plane ? "PLANE" : "CRTC",
4492 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4493 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4494 return -EINVAL;
4495 }
4496
4497 /* check colorkey */
4498 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4499 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4500 intel_plane->base.base.id);
4501 return -EINVAL;
4502 }
4503
4504 /* Check src format */
4505 if (intel_plane) {
4506 switch (fb->pixel_format) {
4507 case DRM_FORMAT_RGB565:
4508 case DRM_FORMAT_XBGR8888:
4509 case DRM_FORMAT_XRGB8888:
4510 case DRM_FORMAT_ABGR8888:
4511 case DRM_FORMAT_ARGB8888:
4512 case DRM_FORMAT_XRGB2101010:
4513 case DRM_FORMAT_XBGR2101010:
4514 case DRM_FORMAT_YUYV:
4515 case DRM_FORMAT_YVYU:
4516 case DRM_FORMAT_UYVY:
4517 case DRM_FORMAT_VYUY:
4518 break;
4519 default:
4520 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4521 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4522 return -EINVAL;
4523 }
4524 }
4525
4526 /* mark this plane as a scaler user in crtc_state */
4527 scaler_state->scaler_users |= (1 << idx);
4528 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4529 "crtc_state = %p scaler_users = 0x%x\n",
4530 intel_plane ? "PLANE" : "CRTC",
4531 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4532 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4533 return 0;
4534 }
4535
4536 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4537 {
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 int pipe = crtc->pipe;
4541 struct intel_crtc_scaler_state *scaler_state =
4542 &crtc->config->scaler_state;
4543
4544 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4545
4546 /* To update pfit, first update scaler state */
4547 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4548 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4549 skl_detach_scalers(crtc);
4550 if (!enable)
4551 return;
4552
4553 if (crtc->config->pch_pfit.enabled) {
4554 int id;
4555
4556 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4557 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4558 return;
4559 }
4560
4561 id = scaler_state->scaler_id;
4562 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4563 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4564 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4565 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4566
4567 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4568 }
4569 }
4570
4571 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4572 {
4573 struct drm_device *dev = crtc->base.dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 int pipe = crtc->pipe;
4576
4577 if (crtc->config->pch_pfit.enabled) {
4578 /* Force use of hard-coded filter coefficients
4579 * as some pre-programmed values are broken,
4580 * e.g. x201.
4581 */
4582 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4583 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4584 PF_PIPE_SEL_IVB(pipe));
4585 else
4586 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4587 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4588 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4589 }
4590 }
4591
4592 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4593 {
4594 struct drm_device *dev = crtc->dev;
4595 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4596 struct drm_plane *plane;
4597 struct intel_plane *intel_plane;
4598
4599 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4600 intel_plane = to_intel_plane(plane);
4601 if (intel_plane->pipe == pipe)
4602 intel_plane_restore(&intel_plane->base);
4603 }
4604 }
4605
4606 void hsw_enable_ips(struct intel_crtc *crtc)
4607 {
4608 struct drm_device *dev = crtc->base.dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610
4611 if (!crtc->config->ips_enabled)
4612 return;
4613
4614 /* We can only enable IPS after we enable a plane and wait for a vblank */
4615 intel_wait_for_vblank(dev, crtc->pipe);
4616
4617 assert_plane_enabled(dev_priv, crtc->plane);
4618 if (IS_BROADWELL(dev)) {
4619 mutex_lock(&dev_priv->rps.hw_lock);
4620 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4621 mutex_unlock(&dev_priv->rps.hw_lock);
4622 /* Quoting Art Runyan: "its not safe to expect any particular
4623 * value in IPS_CTL bit 31 after enabling IPS through the
4624 * mailbox." Moreover, the mailbox may return a bogus state,
4625 * so we need to just enable it and continue on.
4626 */
4627 } else {
4628 I915_WRITE(IPS_CTL, IPS_ENABLE);
4629 /* The bit only becomes 1 in the next vblank, so this wait here
4630 * is essentially intel_wait_for_vblank. If we don't have this
4631 * and don't wait for vblanks until the end of crtc_enable, then
4632 * the HW state readout code will complain that the expected
4633 * IPS_CTL value is not the one we read. */
4634 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4635 DRM_ERROR("Timed out waiting for IPS enable\n");
4636 }
4637 }
4638
4639 void hsw_disable_ips(struct intel_crtc *crtc)
4640 {
4641 struct drm_device *dev = crtc->base.dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643
4644 if (!crtc->config->ips_enabled)
4645 return;
4646
4647 assert_plane_enabled(dev_priv, crtc->plane);
4648 if (IS_BROADWELL(dev)) {
4649 mutex_lock(&dev_priv->rps.hw_lock);
4650 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4651 mutex_unlock(&dev_priv->rps.hw_lock);
4652 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4653 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4654 DRM_ERROR("Timed out waiting for IPS disable\n");
4655 } else {
4656 I915_WRITE(IPS_CTL, 0);
4657 POSTING_READ(IPS_CTL);
4658 }
4659
4660 /* We need to wait for a vblank before we can disable the plane. */
4661 intel_wait_for_vblank(dev, crtc->pipe);
4662 }
4663
4664 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4665 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4666 {
4667 struct drm_device *dev = crtc->dev;
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4670 enum pipe pipe = intel_crtc->pipe;
4671 int palreg = PALETTE(pipe);
4672 int i;
4673 bool reenable_ips = false;
4674
4675 /* The clocks have to be on to load the palette. */
4676 if (!crtc->state->enable || !intel_crtc->active)
4677 return;
4678
4679 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4680 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4681 assert_dsi_pll_enabled(dev_priv);
4682 else
4683 assert_pll_enabled(dev_priv, pipe);
4684 }
4685
4686 /* use legacy palette for Ironlake */
4687 if (!HAS_GMCH_DISPLAY(dev))
4688 palreg = LGC_PALETTE(pipe);
4689
4690 /* Workaround : Do not read or write the pipe palette/gamma data while
4691 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4692 */
4693 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4694 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4695 GAMMA_MODE_MODE_SPLIT)) {
4696 hsw_disable_ips(intel_crtc);
4697 reenable_ips = true;
4698 }
4699
4700 for (i = 0; i < 256; i++) {
4701 I915_WRITE(palreg + 4 * i,
4702 (intel_crtc->lut_r[i] << 16) |
4703 (intel_crtc->lut_g[i] << 8) |
4704 intel_crtc->lut_b[i]);
4705 }
4706
4707 if (reenable_ips)
4708 hsw_enable_ips(intel_crtc);
4709 }
4710
4711 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4712 {
4713 if (intel_crtc->overlay) {
4714 struct drm_device *dev = intel_crtc->base.dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716
4717 mutex_lock(&dev->struct_mutex);
4718 dev_priv->mm.interruptible = false;
4719 (void) intel_overlay_switch_off(intel_crtc->overlay);
4720 dev_priv->mm.interruptible = true;
4721 mutex_unlock(&dev->struct_mutex);
4722 }
4723
4724 /* Let userspace switch the overlay on again. In most cases userspace
4725 * has to recompute where to put it anyway.
4726 */
4727 }
4728
4729 /**
4730 * intel_post_enable_primary - Perform operations after enabling primary plane
4731 * @crtc: the CRTC whose primary plane was just enabled
4732 *
4733 * Performs potentially sleeping operations that must be done after the primary
4734 * plane is enabled, such as updating FBC and IPS. Note that this may be
4735 * called due to an explicit primary plane update, or due to an implicit
4736 * re-enable that is caused when a sprite plane is updated to no longer
4737 * completely hide the primary plane.
4738 */
4739 static void
4740 intel_post_enable_primary(struct drm_crtc *crtc)
4741 {
4742 struct drm_device *dev = crtc->dev;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4745 int pipe = intel_crtc->pipe;
4746
4747 /*
4748 * BDW signals flip done immediately if the plane
4749 * is disabled, even if the plane enable is already
4750 * armed to occur at the next vblank :(
4751 */
4752 if (IS_BROADWELL(dev))
4753 intel_wait_for_vblank(dev, pipe);
4754
4755 /*
4756 * FIXME IPS should be fine as long as one plane is
4757 * enabled, but in practice it seems to have problems
4758 * when going from primary only to sprite only and vice
4759 * versa.
4760 */
4761 hsw_enable_ips(intel_crtc);
4762
4763 mutex_lock(&dev->struct_mutex);
4764 intel_fbc_update(dev);
4765 mutex_unlock(&dev->struct_mutex);
4766
4767 /*
4768 * Gen2 reports pipe underruns whenever all planes are disabled.
4769 * So don't enable underrun reporting before at least some planes
4770 * are enabled.
4771 * FIXME: Need to fix the logic to work when we turn off all planes
4772 * but leave the pipe running.
4773 */
4774 if (IS_GEN2(dev))
4775 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4776
4777 /* Underruns don't raise interrupts, so check manually. */
4778 if (HAS_GMCH_DISPLAY(dev))
4779 i9xx_check_fifo_underruns(dev_priv);
4780 }
4781
4782 /**
4783 * intel_pre_disable_primary - Perform operations before disabling primary plane
4784 * @crtc: the CRTC whose primary plane is to be disabled
4785 *
4786 * Performs potentially sleeping operations that must be done before the
4787 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4788 * be called due to an explicit primary plane update, or due to an implicit
4789 * disable that is caused when a sprite plane completely hides the primary
4790 * plane.
4791 */
4792 static void
4793 intel_pre_disable_primary(struct drm_crtc *crtc)
4794 {
4795 struct drm_device *dev = crtc->dev;
4796 struct drm_i915_private *dev_priv = dev->dev_private;
4797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4798 int pipe = intel_crtc->pipe;
4799
4800 /*
4801 * Gen2 reports pipe underruns whenever all planes are disabled.
4802 * So diasble underrun reporting before all the planes get disabled.
4803 * FIXME: Need to fix the logic to work when we turn off all planes
4804 * but leave the pipe running.
4805 */
4806 if (IS_GEN2(dev))
4807 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4808
4809 /*
4810 * Vblank time updates from the shadow to live plane control register
4811 * are blocked if the memory self-refresh mode is active at that
4812 * moment. So to make sure the plane gets truly disabled, disable
4813 * first the self-refresh mode. The self-refresh enable bit in turn
4814 * will be checked/applied by the HW only at the next frame start
4815 * event which is after the vblank start event, so we need to have a
4816 * wait-for-vblank between disabling the plane and the pipe.
4817 */
4818 if (HAS_GMCH_DISPLAY(dev))
4819 intel_set_memory_cxsr(dev_priv, false);
4820
4821 mutex_lock(&dev->struct_mutex);
4822 if (dev_priv->fbc.crtc == intel_crtc)
4823 intel_fbc_disable(dev);
4824 mutex_unlock(&dev->struct_mutex);
4825
4826 /*
4827 * FIXME IPS should be fine as long as one plane is
4828 * enabled, but in practice it seems to have problems
4829 * when going from primary only to sprite only and vice
4830 * versa.
4831 */
4832 hsw_disable_ips(intel_crtc);
4833 }
4834
4835 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4836 {
4837 intel_enable_primary_hw_plane(crtc->primary, crtc);
4838 intel_enable_sprite_planes(crtc);
4839 intel_crtc_update_cursor(crtc, true);
4840
4841 intel_post_enable_primary(crtc);
4842 }
4843
4844 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4845 {
4846 struct drm_device *dev = crtc->dev;
4847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848 struct intel_plane *intel_plane;
4849 int pipe = intel_crtc->pipe;
4850
4851 intel_crtc_wait_for_pending_flips(crtc);
4852
4853 intel_pre_disable_primary(crtc);
4854
4855 intel_crtc_dpms_overlay_disable(intel_crtc);
4856 for_each_intel_plane(dev, intel_plane) {
4857 if (intel_plane->pipe == pipe) {
4858 struct drm_crtc *from = intel_plane->base.crtc;
4859
4860 intel_plane->disable_plane(&intel_plane->base,
4861 from ?: crtc, true);
4862 }
4863 }
4864
4865 /*
4866 * FIXME: Once we grow proper nuclear flip support out of this we need
4867 * to compute the mask of flip planes precisely. For the time being
4868 * consider this a flip to a NULL plane.
4869 */
4870 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4871 }
4872
4873 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4874 {
4875 struct drm_device *dev = crtc->dev;
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878 struct intel_encoder *encoder;
4879 int pipe = intel_crtc->pipe;
4880
4881 WARN_ON(!crtc->state->enable);
4882
4883 if (intel_crtc->active)
4884 return;
4885
4886 if (intel_crtc->config->has_pch_encoder)
4887 intel_prepare_shared_dpll(intel_crtc);
4888
4889 if (intel_crtc->config->has_dp_encoder)
4890 intel_dp_set_m_n(intel_crtc, M1_N1);
4891
4892 intel_set_pipe_timings(intel_crtc);
4893
4894 if (intel_crtc->config->has_pch_encoder) {
4895 intel_cpu_transcoder_set_m_n(intel_crtc,
4896 &intel_crtc->config->fdi_m_n, NULL);
4897 }
4898
4899 ironlake_set_pipeconf(crtc);
4900
4901 intel_crtc->active = true;
4902
4903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4904 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4905
4906 for_each_encoder_on_crtc(dev, crtc, encoder)
4907 if (encoder->pre_enable)
4908 encoder->pre_enable(encoder);
4909
4910 if (intel_crtc->config->has_pch_encoder) {
4911 /* Note: FDI PLL enabling _must_ be done before we enable the
4912 * cpu pipes, hence this is separate from all the other fdi/pch
4913 * enabling. */
4914 ironlake_fdi_pll_enable(intel_crtc);
4915 } else {
4916 assert_fdi_tx_disabled(dev_priv, pipe);
4917 assert_fdi_rx_disabled(dev_priv, pipe);
4918 }
4919
4920 ironlake_pfit_enable(intel_crtc);
4921
4922 /*
4923 * On ILK+ LUT must be loaded before the pipe is running but with
4924 * clocks enabled
4925 */
4926 intel_crtc_load_lut(crtc);
4927
4928 intel_update_watermarks(crtc);
4929 intel_enable_pipe(intel_crtc);
4930
4931 if (intel_crtc->config->has_pch_encoder)
4932 ironlake_pch_enable(crtc);
4933
4934 assert_vblank_disabled(crtc);
4935 drm_crtc_vblank_on(crtc);
4936
4937 for_each_encoder_on_crtc(dev, crtc, encoder)
4938 encoder->enable(encoder);
4939
4940 if (HAS_PCH_CPT(dev))
4941 cpt_verify_modeset(dev, intel_crtc->pipe);
4942 }
4943
4944 /* IPS only exists on ULT machines and is tied to pipe A. */
4945 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4946 {
4947 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4948 }
4949
4950 /*
4951 * This implements the workaround described in the "notes" section of the mode
4952 * set sequence documentation. When going from no pipes or single pipe to
4953 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4954 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4955 */
4956 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4957 {
4958 struct drm_device *dev = crtc->base.dev;
4959 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4960
4961 /* We want to get the other_active_crtc only if there's only 1 other
4962 * active crtc. */
4963 for_each_intel_crtc(dev, crtc_it) {
4964 if (!crtc_it->active || crtc_it == crtc)
4965 continue;
4966
4967 if (other_active_crtc)
4968 return;
4969
4970 other_active_crtc = crtc_it;
4971 }
4972 if (!other_active_crtc)
4973 return;
4974
4975 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4976 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4977 }
4978
4979 static void haswell_crtc_enable(struct drm_crtc *crtc)
4980 {
4981 struct drm_device *dev = crtc->dev;
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984 struct intel_encoder *encoder;
4985 int pipe = intel_crtc->pipe;
4986
4987 WARN_ON(!crtc->state->enable);
4988
4989 if (intel_crtc->active)
4990 return;
4991
4992 if (intel_crtc_to_shared_dpll(intel_crtc))
4993 intel_enable_shared_dpll(intel_crtc);
4994
4995 if (intel_crtc->config->has_dp_encoder)
4996 intel_dp_set_m_n(intel_crtc, M1_N1);
4997
4998 intel_set_pipe_timings(intel_crtc);
4999
5000 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5001 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5002 intel_crtc->config->pixel_multiplier - 1);
5003 }
5004
5005 if (intel_crtc->config->has_pch_encoder) {
5006 intel_cpu_transcoder_set_m_n(intel_crtc,
5007 &intel_crtc->config->fdi_m_n, NULL);
5008 }
5009
5010 haswell_set_pipeconf(crtc);
5011
5012 intel_set_pipe_csc(crtc);
5013
5014 intel_crtc->active = true;
5015
5016 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5017 for_each_encoder_on_crtc(dev, crtc, encoder)
5018 if (encoder->pre_enable)
5019 encoder->pre_enable(encoder);
5020
5021 if (intel_crtc->config->has_pch_encoder) {
5022 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5023 true);
5024 dev_priv->display.fdi_link_train(crtc);
5025 }
5026
5027 intel_ddi_enable_pipe_clock(intel_crtc);
5028
5029 if (INTEL_INFO(dev)->gen == 9)
5030 skylake_pfit_update(intel_crtc, 1);
5031 else if (INTEL_INFO(dev)->gen < 9)
5032 ironlake_pfit_enable(intel_crtc);
5033 else
5034 MISSING_CASE(INTEL_INFO(dev)->gen);
5035
5036 /*
5037 * On ILK+ LUT must be loaded before the pipe is running but with
5038 * clocks enabled
5039 */
5040 intel_crtc_load_lut(crtc);
5041
5042 intel_ddi_set_pipe_settings(crtc);
5043 intel_ddi_enable_transcoder_func(crtc);
5044
5045 intel_update_watermarks(crtc);
5046 intel_enable_pipe(intel_crtc);
5047
5048 if (intel_crtc->config->has_pch_encoder)
5049 lpt_pch_enable(crtc);
5050
5051 if (intel_crtc->config->dp_encoder_is_mst)
5052 intel_ddi_set_vc_payload_alloc(crtc, true);
5053
5054 assert_vblank_disabled(crtc);
5055 drm_crtc_vblank_on(crtc);
5056
5057 for_each_encoder_on_crtc(dev, crtc, encoder) {
5058 encoder->enable(encoder);
5059 intel_opregion_notify_encoder(encoder, true);
5060 }
5061
5062 /* If we change the relative order between pipe/planes enabling, we need
5063 * to change the workaround. */
5064 haswell_mode_set_planes_workaround(intel_crtc);
5065 }
5066
5067 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5068 {
5069 struct drm_device *dev = crtc->base.dev;
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 int pipe = crtc->pipe;
5072
5073 /* To avoid upsetting the power well on haswell only disable the pfit if
5074 * it's in use. The hw state code will make sure we get this right. */
5075 if (crtc->config->pch_pfit.enabled) {
5076 I915_WRITE(PF_CTL(pipe), 0);
5077 I915_WRITE(PF_WIN_POS(pipe), 0);
5078 I915_WRITE(PF_WIN_SZ(pipe), 0);
5079 }
5080 }
5081
5082 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5083 {
5084 struct drm_device *dev = crtc->dev;
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5087 struct intel_encoder *encoder;
5088 int pipe = intel_crtc->pipe;
5089 u32 reg, temp;
5090
5091 if (!intel_crtc->active)
5092 return;
5093
5094 for_each_encoder_on_crtc(dev, crtc, encoder)
5095 encoder->disable(encoder);
5096
5097 drm_crtc_vblank_off(crtc);
5098 assert_vblank_disabled(crtc);
5099
5100 if (intel_crtc->config->has_pch_encoder)
5101 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5102
5103 intel_disable_pipe(intel_crtc);
5104
5105 ironlake_pfit_disable(intel_crtc);
5106
5107 for_each_encoder_on_crtc(dev, crtc, encoder)
5108 if (encoder->post_disable)
5109 encoder->post_disable(encoder);
5110
5111 if (intel_crtc->config->has_pch_encoder) {
5112 ironlake_fdi_disable(crtc);
5113
5114 ironlake_disable_pch_transcoder(dev_priv, pipe);
5115
5116 if (HAS_PCH_CPT(dev)) {
5117 /* disable TRANS_DP_CTL */
5118 reg = TRANS_DP_CTL(pipe);
5119 temp = I915_READ(reg);
5120 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5121 TRANS_DP_PORT_SEL_MASK);
5122 temp |= TRANS_DP_PORT_SEL_NONE;
5123 I915_WRITE(reg, temp);
5124
5125 /* disable DPLL_SEL */
5126 temp = I915_READ(PCH_DPLL_SEL);
5127 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5128 I915_WRITE(PCH_DPLL_SEL, temp);
5129 }
5130
5131 /* disable PCH DPLL */
5132 intel_disable_shared_dpll(intel_crtc);
5133
5134 ironlake_fdi_pll_disable(intel_crtc);
5135 }
5136
5137 intel_crtc->active = false;
5138 intel_update_watermarks(crtc);
5139
5140 mutex_lock(&dev->struct_mutex);
5141 intel_fbc_update(dev);
5142 mutex_unlock(&dev->struct_mutex);
5143 }
5144
5145 static void haswell_crtc_disable(struct drm_crtc *crtc)
5146 {
5147 struct drm_device *dev = crtc->dev;
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150 struct intel_encoder *encoder;
5151 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5152
5153 if (!intel_crtc->active)
5154 return;
5155
5156 for_each_encoder_on_crtc(dev, crtc, encoder) {
5157 intel_opregion_notify_encoder(encoder, false);
5158 encoder->disable(encoder);
5159 }
5160
5161 drm_crtc_vblank_off(crtc);
5162 assert_vblank_disabled(crtc);
5163
5164 if (intel_crtc->config->has_pch_encoder)
5165 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5166 false);
5167 intel_disable_pipe(intel_crtc);
5168
5169 if (intel_crtc->config->dp_encoder_is_mst)
5170 intel_ddi_set_vc_payload_alloc(crtc, false);
5171
5172 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5173
5174 if (INTEL_INFO(dev)->gen == 9)
5175 skylake_pfit_update(intel_crtc, 0);
5176 else if (INTEL_INFO(dev)->gen < 9)
5177 ironlake_pfit_disable(intel_crtc);
5178 else
5179 MISSING_CASE(INTEL_INFO(dev)->gen);
5180
5181 intel_ddi_disable_pipe_clock(intel_crtc);
5182
5183 if (intel_crtc->config->has_pch_encoder) {
5184 lpt_disable_pch_transcoder(dev_priv);
5185 intel_ddi_fdi_disable(crtc);
5186 }
5187
5188 for_each_encoder_on_crtc(dev, crtc, encoder)
5189 if (encoder->post_disable)
5190 encoder->post_disable(encoder);
5191
5192 intel_crtc->active = false;
5193 intel_update_watermarks(crtc);
5194
5195 mutex_lock(&dev->struct_mutex);
5196 intel_fbc_update(dev);
5197 mutex_unlock(&dev->struct_mutex);
5198
5199 if (intel_crtc_to_shared_dpll(intel_crtc))
5200 intel_disable_shared_dpll(intel_crtc);
5201 }
5202
5203 static void ironlake_crtc_off(struct drm_crtc *crtc)
5204 {
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 intel_put_shared_dpll(intel_crtc);
5207 }
5208
5209
5210 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5211 {
5212 struct drm_device *dev = crtc->base.dev;
5213 struct drm_i915_private *dev_priv = dev->dev_private;
5214 struct intel_crtc_state *pipe_config = crtc->config;
5215
5216 if (!pipe_config->gmch_pfit.control)
5217 return;
5218
5219 /*
5220 * The panel fitter should only be adjusted whilst the pipe is disabled,
5221 * according to register description and PRM.
5222 */
5223 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5224 assert_pipe_disabled(dev_priv, crtc->pipe);
5225
5226 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5227 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5228
5229 /* Border color in case we don't scale up to the full screen. Black by
5230 * default, change to something else for debugging. */
5231 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5232 }
5233
5234 static enum intel_display_power_domain port_to_power_domain(enum port port)
5235 {
5236 switch (port) {
5237 case PORT_A:
5238 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5239 case PORT_B:
5240 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5241 case PORT_C:
5242 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5243 case PORT_D:
5244 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5245 default:
5246 WARN_ON_ONCE(1);
5247 return POWER_DOMAIN_PORT_OTHER;
5248 }
5249 }
5250
5251 #define for_each_power_domain(domain, mask) \
5252 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5253 if ((1 << (domain)) & (mask))
5254
5255 enum intel_display_power_domain
5256 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5257 {
5258 struct drm_device *dev = intel_encoder->base.dev;
5259 struct intel_digital_port *intel_dig_port;
5260
5261 switch (intel_encoder->type) {
5262 case INTEL_OUTPUT_UNKNOWN:
5263 /* Only DDI platforms should ever use this output type */
5264 WARN_ON_ONCE(!HAS_DDI(dev));
5265 case INTEL_OUTPUT_DISPLAYPORT:
5266 case INTEL_OUTPUT_HDMI:
5267 case INTEL_OUTPUT_EDP:
5268 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5269 return port_to_power_domain(intel_dig_port->port);
5270 case INTEL_OUTPUT_DP_MST:
5271 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5272 return port_to_power_domain(intel_dig_port->port);
5273 case INTEL_OUTPUT_ANALOG:
5274 return POWER_DOMAIN_PORT_CRT;
5275 case INTEL_OUTPUT_DSI:
5276 return POWER_DOMAIN_PORT_DSI;
5277 default:
5278 return POWER_DOMAIN_PORT_OTHER;
5279 }
5280 }
5281
5282 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5283 {
5284 struct drm_device *dev = crtc->dev;
5285 struct intel_encoder *intel_encoder;
5286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5287 enum pipe pipe = intel_crtc->pipe;
5288 unsigned long mask;
5289 enum transcoder transcoder;
5290
5291 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5292
5293 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5294 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5295 if (intel_crtc->config->pch_pfit.enabled ||
5296 intel_crtc->config->pch_pfit.force_thru)
5297 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5298
5299 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5300 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5301
5302 return mask;
5303 }
5304
5305 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5306 {
5307 struct drm_device *dev = state->dev;
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5310 struct intel_crtc *crtc;
5311
5312 /*
5313 * First get all needed power domains, then put all unneeded, to avoid
5314 * any unnecessary toggling of the power wells.
5315 */
5316 for_each_intel_crtc(dev, crtc) {
5317 enum intel_display_power_domain domain;
5318
5319 if (!crtc->base.state->enable)
5320 continue;
5321
5322 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5323
5324 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5325 intel_display_power_get(dev_priv, domain);
5326 }
5327
5328 if (dev_priv->display.modeset_global_resources)
5329 dev_priv->display.modeset_global_resources(state);
5330
5331 for_each_intel_crtc(dev, crtc) {
5332 enum intel_display_power_domain domain;
5333
5334 for_each_power_domain(domain, crtc->enabled_power_domains)
5335 intel_display_power_put(dev_priv, domain);
5336
5337 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5338 }
5339
5340 intel_display_set_init_power(dev_priv, false);
5341 }
5342
5343 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5344 {
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346 uint32_t divider;
5347 uint32_t ratio;
5348 uint32_t current_freq;
5349 int ret;
5350
5351 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5352 switch (frequency) {
5353 case 144000:
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5355 ratio = BXT_DE_PLL_RATIO(60);
5356 break;
5357 case 288000:
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5359 ratio = BXT_DE_PLL_RATIO(60);
5360 break;
5361 case 384000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 576000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 624000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371 ratio = BXT_DE_PLL_RATIO(65);
5372 break;
5373 case 19200:
5374 /*
5375 * Bypass frequency with DE PLL disabled. Init ratio, divider
5376 * to suppress GCC warning.
5377 */
5378 ratio = 0;
5379 divider = 0;
5380 break;
5381 default:
5382 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5383
5384 return;
5385 }
5386
5387 mutex_lock(&dev_priv->rps.hw_lock);
5388 /* Inform power controller of upcoming frequency change */
5389 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5390 0x80000000);
5391 mutex_unlock(&dev_priv->rps.hw_lock);
5392
5393 if (ret) {
5394 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5395 ret, frequency);
5396 return;
5397 }
5398
5399 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5400 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5401 current_freq = current_freq * 500 + 1000;
5402
5403 /*
5404 * DE PLL has to be disabled when
5405 * - setting to 19.2MHz (bypass, PLL isn't used)
5406 * - before setting to 624MHz (PLL needs toggling)
5407 * - before setting to any frequency from 624MHz (PLL needs toggling)
5408 */
5409 if (frequency == 19200 || frequency == 624000 ||
5410 current_freq == 624000) {
5411 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5412 /* Timeout 200us */
5413 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5414 1))
5415 DRM_ERROR("timout waiting for DE PLL unlock\n");
5416 }
5417
5418 if (frequency != 19200) {
5419 uint32_t val;
5420
5421 val = I915_READ(BXT_DE_PLL_CTL);
5422 val &= ~BXT_DE_PLL_RATIO_MASK;
5423 val |= ratio;
5424 I915_WRITE(BXT_DE_PLL_CTL, val);
5425
5426 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5427 /* Timeout 200us */
5428 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5429 DRM_ERROR("timeout waiting for DE PLL lock\n");
5430
5431 val = I915_READ(CDCLK_CTL);
5432 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5433 val |= divider;
5434 /*
5435 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5436 * enable otherwise.
5437 */
5438 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5439 if (frequency >= 500000)
5440 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5441
5442 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5443 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5444 val |= (frequency - 1000) / 500;
5445 I915_WRITE(CDCLK_CTL, val);
5446 }
5447
5448 mutex_lock(&dev_priv->rps.hw_lock);
5449 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5450 DIV_ROUND_UP(frequency, 25000));
5451 mutex_unlock(&dev_priv->rps.hw_lock);
5452
5453 if (ret) {
5454 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5455 ret, frequency);
5456 return;
5457 }
5458
5459 dev_priv->cdclk_freq = frequency;
5460 }
5461
5462 void broxton_init_cdclk(struct drm_device *dev)
5463 {
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465 uint32_t val;
5466
5467 /*
5468 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5469 * or else the reset will hang because there is no PCH to respond.
5470 * Move the handshake programming to initialization sequence.
5471 * Previously was left up to BIOS.
5472 */
5473 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5474 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5475 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5476
5477 /* Enable PG1 for cdclk */
5478 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5479
5480 /* check if cd clock is enabled */
5481 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5482 DRM_DEBUG_KMS("Display already initialized\n");
5483 return;
5484 }
5485
5486 /*
5487 * FIXME:
5488 * - The initial CDCLK needs to be read from VBT.
5489 * Need to make this change after VBT has changes for BXT.
5490 * - check if setting the max (or any) cdclk freq is really necessary
5491 * here, it belongs to modeset time
5492 */
5493 broxton_set_cdclk(dev, 624000);
5494
5495 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5496 POSTING_READ(DBUF_CTL);
5497
5498 udelay(10);
5499
5500 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5501 DRM_ERROR("DBuf power enable timeout!\n");
5502 }
5503
5504 void broxton_uninit_cdclk(struct drm_device *dev)
5505 {
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507
5508 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5509 POSTING_READ(DBUF_CTL);
5510
5511 udelay(10);
5512
5513 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5514 DRM_ERROR("DBuf power disable timeout!\n");
5515
5516 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5517 broxton_set_cdclk(dev, 19200);
5518
5519 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5520 }
5521
5522 /* returns HPLL frequency in kHz */
5523 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5524 {
5525 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5526
5527 /* Obtain SKU information */
5528 mutex_lock(&dev_priv->dpio_lock);
5529 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5530 CCK_FUSE_HPLL_FREQ_MASK;
5531 mutex_unlock(&dev_priv->dpio_lock);
5532
5533 return vco_freq[hpll_freq] * 1000;
5534 }
5535
5536 static void vlv_update_cdclk(struct drm_device *dev)
5537 {
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5539
5540 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5541 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5542 dev_priv->cdclk_freq);
5543
5544 /*
5545 * Program the gmbus_freq based on the cdclk frequency.
5546 * BSpec erroneously claims we should aim for 4MHz, but
5547 * in fact 1MHz is the correct frequency.
5548 */
5549 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5550 }
5551
5552 /* Adjust CDclk dividers to allow high res or save power if possible */
5553 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5554 {
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556 u32 val, cmd;
5557
5558 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5559 != dev_priv->cdclk_freq);
5560
5561 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5562 cmd = 2;
5563 else if (cdclk == 266667)
5564 cmd = 1;
5565 else
5566 cmd = 0;
5567
5568 mutex_lock(&dev_priv->rps.hw_lock);
5569 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5570 val &= ~DSPFREQGUAR_MASK;
5571 val |= (cmd << DSPFREQGUAR_SHIFT);
5572 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5573 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5574 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5575 50)) {
5576 DRM_ERROR("timed out waiting for CDclk change\n");
5577 }
5578 mutex_unlock(&dev_priv->rps.hw_lock);
5579
5580 if (cdclk == 400000) {
5581 u32 divider;
5582
5583 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5584
5585 mutex_lock(&dev_priv->dpio_lock);
5586 /* adjust cdclk divider */
5587 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5588 val &= ~DISPLAY_FREQUENCY_VALUES;
5589 val |= divider;
5590 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5591
5592 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5593 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5594 50))
5595 DRM_ERROR("timed out waiting for CDclk change\n");
5596 mutex_unlock(&dev_priv->dpio_lock);
5597 }
5598
5599 mutex_lock(&dev_priv->dpio_lock);
5600 /* adjust self-refresh exit latency value */
5601 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5602 val &= ~0x7f;
5603
5604 /*
5605 * For high bandwidth configs, we set a higher latency in the bunit
5606 * so that the core display fetch happens in time to avoid underruns.
5607 */
5608 if (cdclk == 400000)
5609 val |= 4500 / 250; /* 4.5 usec */
5610 else
5611 val |= 3000 / 250; /* 3.0 usec */
5612 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5613 mutex_unlock(&dev_priv->dpio_lock);
5614
5615 vlv_update_cdclk(dev);
5616 }
5617
5618 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5619 {
5620 struct drm_i915_private *dev_priv = dev->dev_private;
5621 u32 val, cmd;
5622
5623 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5624 != dev_priv->cdclk_freq);
5625
5626 switch (cdclk) {
5627 case 333333:
5628 case 320000:
5629 case 266667:
5630 case 200000:
5631 break;
5632 default:
5633 MISSING_CASE(cdclk);
5634 return;
5635 }
5636
5637 /*
5638 * Specs are full of misinformation, but testing on actual
5639 * hardware has shown that we just need to write the desired
5640 * CCK divider into the Punit register.
5641 */
5642 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5643
5644 mutex_lock(&dev_priv->rps.hw_lock);
5645 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5646 val &= ~DSPFREQGUAR_MASK_CHV;
5647 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5648 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5649 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5650 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5651 50)) {
5652 DRM_ERROR("timed out waiting for CDclk change\n");
5653 }
5654 mutex_unlock(&dev_priv->rps.hw_lock);
5655
5656 vlv_update_cdclk(dev);
5657 }
5658
5659 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5660 int max_pixclk)
5661 {
5662 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5663 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5664
5665 /*
5666 * Really only a few cases to deal with, as only 4 CDclks are supported:
5667 * 200MHz
5668 * 267MHz
5669 * 320/333MHz (depends on HPLL freq)
5670 * 400MHz (VLV only)
5671 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5672 * of the lower bin and adjust if needed.
5673 *
5674 * We seem to get an unstable or solid color picture at 200MHz.
5675 * Not sure what's wrong. For now use 200MHz only when all pipes
5676 * are off.
5677 */
5678 if (!IS_CHERRYVIEW(dev_priv) &&
5679 max_pixclk > freq_320*limit/100)
5680 return 400000;
5681 else if (max_pixclk > 266667*limit/100)
5682 return freq_320;
5683 else if (max_pixclk > 0)
5684 return 266667;
5685 else
5686 return 200000;
5687 }
5688
5689 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5690 int max_pixclk)
5691 {
5692 /*
5693 * FIXME:
5694 * - remove the guardband, it's not needed on BXT
5695 * - set 19.2MHz bypass frequency if there are no active pipes
5696 */
5697 if (max_pixclk > 576000*9/10)
5698 return 624000;
5699 else if (max_pixclk > 384000*9/10)
5700 return 576000;
5701 else if (max_pixclk > 288000*9/10)
5702 return 384000;
5703 else if (max_pixclk > 144000*9/10)
5704 return 288000;
5705 else
5706 return 144000;
5707 }
5708
5709 /* Compute the max pixel clock for new configuration. Uses atomic state if
5710 * that's non-NULL, look at current state otherwise. */
5711 static int intel_mode_max_pixclk(struct drm_device *dev,
5712 struct drm_atomic_state *state)
5713 {
5714 struct intel_crtc *intel_crtc;
5715 struct intel_crtc_state *crtc_state;
5716 int max_pixclk = 0;
5717
5718 for_each_intel_crtc(dev, intel_crtc) {
5719 if (state)
5720 crtc_state =
5721 intel_atomic_get_crtc_state(state, intel_crtc);
5722 else
5723 crtc_state = intel_crtc->config;
5724 if (IS_ERR(crtc_state))
5725 return PTR_ERR(crtc_state);
5726
5727 if (!crtc_state->base.enable)
5728 continue;
5729
5730 max_pixclk = max(max_pixclk,
5731 crtc_state->base.adjusted_mode.crtc_clock);
5732 }
5733
5734 return max_pixclk;
5735 }
5736
5737 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5738 {
5739 struct drm_i915_private *dev_priv = to_i915(state->dev);
5740 struct drm_crtc *crtc;
5741 struct drm_crtc_state *crtc_state;
5742 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5743 int cdclk, i;
5744
5745 if (max_pixclk < 0)
5746 return max_pixclk;
5747
5748 if (IS_VALLEYVIEW(dev_priv))
5749 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5750 else
5751 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5752
5753 if (cdclk == dev_priv->cdclk_freq)
5754 return 0;
5755
5756 /* add all active pipes to the state */
5757 for_each_crtc(state->dev, crtc) {
5758 if (!crtc->state->enable)
5759 continue;
5760
5761 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5762 if (IS_ERR(crtc_state))
5763 return PTR_ERR(crtc_state);
5764 }
5765
5766 /* disable/enable all currently active pipes while we change cdclk */
5767 for_each_crtc_in_state(state, crtc, crtc_state, i)
5768 if (crtc_state->enable)
5769 crtc_state->mode_changed = true;
5770
5771 return 0;
5772 }
5773
5774 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5775 {
5776 unsigned int credits, default_credits;
5777
5778 if (IS_CHERRYVIEW(dev_priv))
5779 default_credits = PFI_CREDIT(12);
5780 else
5781 default_credits = PFI_CREDIT(8);
5782
5783 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5784 /* CHV suggested value is 31 or 63 */
5785 if (IS_CHERRYVIEW(dev_priv))
5786 credits = PFI_CREDIT_31;
5787 else
5788 credits = PFI_CREDIT(15);
5789 } else {
5790 credits = default_credits;
5791 }
5792
5793 /*
5794 * WA - write default credits before re-programming
5795 * FIXME: should we also set the resend bit here?
5796 */
5797 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5798 default_credits);
5799
5800 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5801 credits | PFI_CREDIT_RESEND);
5802
5803 /*
5804 * FIXME is this guaranteed to clear
5805 * immediately or should we poll for it?
5806 */
5807 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5808 }
5809
5810 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5811 {
5812 struct drm_device *dev = old_state->dev;
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5815 int req_cdclk;
5816
5817 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5818 * never fail. */
5819 if (WARN_ON(max_pixclk < 0))
5820 return;
5821
5822 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5823
5824 if (req_cdclk != dev_priv->cdclk_freq) {
5825 /*
5826 * FIXME: We can end up here with all power domains off, yet
5827 * with a CDCLK frequency other than the minimum. To account
5828 * for this take the PIPE-A power domain, which covers the HW
5829 * blocks needed for the following programming. This can be
5830 * removed once it's guaranteed that we get here either with
5831 * the minimum CDCLK set, or the required power domains
5832 * enabled.
5833 */
5834 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5835
5836 if (IS_CHERRYVIEW(dev))
5837 cherryview_set_cdclk(dev, req_cdclk);
5838 else
5839 valleyview_set_cdclk(dev, req_cdclk);
5840
5841 vlv_program_pfi_credits(dev_priv);
5842
5843 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5844 }
5845 }
5846
5847 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5848 {
5849 struct drm_device *dev = crtc->dev;
5850 struct drm_i915_private *dev_priv = to_i915(dev);
5851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5852 struct intel_encoder *encoder;
5853 int pipe = intel_crtc->pipe;
5854 bool is_dsi;
5855
5856 WARN_ON(!crtc->state->enable);
5857
5858 if (intel_crtc->active)
5859 return;
5860
5861 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5862
5863 if (!is_dsi) {
5864 if (IS_CHERRYVIEW(dev))
5865 chv_prepare_pll(intel_crtc, intel_crtc->config);
5866 else
5867 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5868 }
5869
5870 if (intel_crtc->config->has_dp_encoder)
5871 intel_dp_set_m_n(intel_crtc, M1_N1);
5872
5873 intel_set_pipe_timings(intel_crtc);
5874
5875 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5876 struct drm_i915_private *dev_priv = dev->dev_private;
5877
5878 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5879 I915_WRITE(CHV_CANVAS(pipe), 0);
5880 }
5881
5882 i9xx_set_pipeconf(intel_crtc);
5883
5884 intel_crtc->active = true;
5885
5886 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5887
5888 for_each_encoder_on_crtc(dev, crtc, encoder)
5889 if (encoder->pre_pll_enable)
5890 encoder->pre_pll_enable(encoder);
5891
5892 if (!is_dsi) {
5893 if (IS_CHERRYVIEW(dev))
5894 chv_enable_pll(intel_crtc, intel_crtc->config);
5895 else
5896 vlv_enable_pll(intel_crtc, intel_crtc->config);
5897 }
5898
5899 for_each_encoder_on_crtc(dev, crtc, encoder)
5900 if (encoder->pre_enable)
5901 encoder->pre_enable(encoder);
5902
5903 i9xx_pfit_enable(intel_crtc);
5904
5905 intel_crtc_load_lut(crtc);
5906
5907 intel_update_watermarks(crtc);
5908 intel_enable_pipe(intel_crtc);
5909
5910 assert_vblank_disabled(crtc);
5911 drm_crtc_vblank_on(crtc);
5912
5913 for_each_encoder_on_crtc(dev, crtc, encoder)
5914 encoder->enable(encoder);
5915 }
5916
5917 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5918 {
5919 struct drm_device *dev = crtc->base.dev;
5920 struct drm_i915_private *dev_priv = dev->dev_private;
5921
5922 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5923 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5924 }
5925
5926 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5927 {
5928 struct drm_device *dev = crtc->dev;
5929 struct drm_i915_private *dev_priv = to_i915(dev);
5930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931 struct intel_encoder *encoder;
5932 int pipe = intel_crtc->pipe;
5933
5934 WARN_ON(!crtc->state->enable);
5935
5936 if (intel_crtc->active)
5937 return;
5938
5939 i9xx_set_pll_dividers(intel_crtc);
5940
5941 if (intel_crtc->config->has_dp_encoder)
5942 intel_dp_set_m_n(intel_crtc, M1_N1);
5943
5944 intel_set_pipe_timings(intel_crtc);
5945
5946 i9xx_set_pipeconf(intel_crtc);
5947
5948 intel_crtc->active = true;
5949
5950 if (!IS_GEN2(dev))
5951 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5952
5953 for_each_encoder_on_crtc(dev, crtc, encoder)
5954 if (encoder->pre_enable)
5955 encoder->pre_enable(encoder);
5956
5957 i9xx_enable_pll(intel_crtc);
5958
5959 i9xx_pfit_enable(intel_crtc);
5960
5961 intel_crtc_load_lut(crtc);
5962
5963 intel_update_watermarks(crtc);
5964 intel_enable_pipe(intel_crtc);
5965
5966 assert_vblank_disabled(crtc);
5967 drm_crtc_vblank_on(crtc);
5968
5969 for_each_encoder_on_crtc(dev, crtc, encoder)
5970 encoder->enable(encoder);
5971 }
5972
5973 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5974 {
5975 struct drm_device *dev = crtc->base.dev;
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977
5978 if (!crtc->config->gmch_pfit.control)
5979 return;
5980
5981 assert_pipe_disabled(dev_priv, crtc->pipe);
5982
5983 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5984 I915_READ(PFIT_CONTROL));
5985 I915_WRITE(PFIT_CONTROL, 0);
5986 }
5987
5988 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5989 {
5990 struct drm_device *dev = crtc->dev;
5991 struct drm_i915_private *dev_priv = dev->dev_private;
5992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993 struct intel_encoder *encoder;
5994 int pipe = intel_crtc->pipe;
5995
5996 if (!intel_crtc->active)
5997 return;
5998
5999 /*
6000 * On gen2 planes are double buffered but the pipe isn't, so we must
6001 * wait for planes to fully turn off before disabling the pipe.
6002 * We also need to wait on all gmch platforms because of the
6003 * self-refresh mode constraint explained above.
6004 */
6005 intel_wait_for_vblank(dev, pipe);
6006
6007 for_each_encoder_on_crtc(dev, crtc, encoder)
6008 encoder->disable(encoder);
6009
6010 drm_crtc_vblank_off(crtc);
6011 assert_vblank_disabled(crtc);
6012
6013 intel_disable_pipe(intel_crtc);
6014
6015 i9xx_pfit_disable(intel_crtc);
6016
6017 for_each_encoder_on_crtc(dev, crtc, encoder)
6018 if (encoder->post_disable)
6019 encoder->post_disable(encoder);
6020
6021 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6022 if (IS_CHERRYVIEW(dev))
6023 chv_disable_pll(dev_priv, pipe);
6024 else if (IS_VALLEYVIEW(dev))
6025 vlv_disable_pll(dev_priv, pipe);
6026 else
6027 i9xx_disable_pll(intel_crtc);
6028 }
6029
6030 if (!IS_GEN2(dev))
6031 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6032
6033 intel_crtc->active = false;
6034 intel_update_watermarks(crtc);
6035
6036 mutex_lock(&dev->struct_mutex);
6037 intel_fbc_update(dev);
6038 mutex_unlock(&dev->struct_mutex);
6039 }
6040
6041 static void i9xx_crtc_off(struct drm_crtc *crtc)
6042 {
6043 }
6044
6045 /* Master function to enable/disable CRTC and corresponding power wells */
6046 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6047 {
6048 struct drm_device *dev = crtc->dev;
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6051 enum intel_display_power_domain domain;
6052 unsigned long domains;
6053
6054 if (enable) {
6055 if (!intel_crtc->active) {
6056 domains = get_crtc_power_domains(crtc);
6057 for_each_power_domain(domain, domains)
6058 intel_display_power_get(dev_priv, domain);
6059 intel_crtc->enabled_power_domains = domains;
6060
6061 dev_priv->display.crtc_enable(crtc);
6062 intel_crtc_enable_planes(crtc);
6063 }
6064 } else {
6065 if (intel_crtc->active) {
6066 intel_crtc_disable_planes(crtc);
6067 dev_priv->display.crtc_disable(crtc);
6068
6069 domains = intel_crtc->enabled_power_domains;
6070 for_each_power_domain(domain, domains)
6071 intel_display_power_put(dev_priv, domain);
6072 intel_crtc->enabled_power_domains = 0;
6073 }
6074 }
6075 }
6076
6077 /**
6078 * Sets the power management mode of the pipe and plane.
6079 */
6080 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6081 {
6082 struct drm_device *dev = crtc->dev;
6083 struct intel_encoder *intel_encoder;
6084 bool enable = false;
6085
6086 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6087 enable |= intel_encoder->connectors_active;
6088
6089 intel_crtc_control(crtc, enable);
6090
6091 crtc->state->active = enable;
6092 }
6093
6094 static void intel_crtc_disable(struct drm_crtc *crtc)
6095 {
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_connector *connector;
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099
6100 /* crtc should still be enabled when we disable it. */
6101 WARN_ON(!crtc->state->enable);
6102
6103 intel_crtc_disable_planes(crtc);
6104 dev_priv->display.crtc_disable(crtc);
6105 dev_priv->display.off(crtc);
6106
6107 drm_plane_helper_disable(crtc->primary);
6108
6109 /* Update computed state. */
6110 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6111 if (!connector->encoder || !connector->encoder->crtc)
6112 continue;
6113
6114 if (connector->encoder->crtc != crtc)
6115 continue;
6116
6117 connector->dpms = DRM_MODE_DPMS_OFF;
6118 to_intel_encoder(connector->encoder)->connectors_active = false;
6119 }
6120 }
6121
6122 void intel_encoder_destroy(struct drm_encoder *encoder)
6123 {
6124 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6125
6126 drm_encoder_cleanup(encoder);
6127 kfree(intel_encoder);
6128 }
6129
6130 /* Simple dpms helper for encoders with just one connector, no cloning and only
6131 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6132 * state of the entire output pipe. */
6133 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6134 {
6135 if (mode == DRM_MODE_DPMS_ON) {
6136 encoder->connectors_active = true;
6137
6138 intel_crtc_update_dpms(encoder->base.crtc);
6139 } else {
6140 encoder->connectors_active = false;
6141
6142 intel_crtc_update_dpms(encoder->base.crtc);
6143 }
6144 }
6145
6146 /* Cross check the actual hw state with our own modeset state tracking (and it's
6147 * internal consistency). */
6148 static void intel_connector_check_state(struct intel_connector *connector)
6149 {
6150 if (connector->get_hw_state(connector)) {
6151 struct intel_encoder *encoder = connector->encoder;
6152 struct drm_crtc *crtc;
6153 bool encoder_enabled;
6154 enum pipe pipe;
6155
6156 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6157 connector->base.base.id,
6158 connector->base.name);
6159
6160 /* there is no real hw state for MST connectors */
6161 if (connector->mst_port)
6162 return;
6163
6164 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6165 "wrong connector dpms state\n");
6166 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6167 "active connector not linked to encoder\n");
6168
6169 if (encoder) {
6170 I915_STATE_WARN(!encoder->connectors_active,
6171 "encoder->connectors_active not set\n");
6172
6173 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6174 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6175 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6176 return;
6177
6178 crtc = encoder->base.crtc;
6179
6180 I915_STATE_WARN(!crtc->state->enable,
6181 "crtc not enabled\n");
6182 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6183 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6184 "encoder active on the wrong pipe\n");
6185 }
6186 }
6187 }
6188
6189 int intel_connector_init(struct intel_connector *connector)
6190 {
6191 struct drm_connector_state *connector_state;
6192
6193 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6194 if (!connector_state)
6195 return -ENOMEM;
6196
6197 connector->base.state = connector_state;
6198 return 0;
6199 }
6200
6201 struct intel_connector *intel_connector_alloc(void)
6202 {
6203 struct intel_connector *connector;
6204
6205 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6206 if (!connector)
6207 return NULL;
6208
6209 if (intel_connector_init(connector) < 0) {
6210 kfree(connector);
6211 return NULL;
6212 }
6213
6214 return connector;
6215 }
6216
6217 /* Even simpler default implementation, if there's really no special case to
6218 * consider. */
6219 void intel_connector_dpms(struct drm_connector *connector, int mode)
6220 {
6221 /* All the simple cases only support two dpms states. */
6222 if (mode != DRM_MODE_DPMS_ON)
6223 mode = DRM_MODE_DPMS_OFF;
6224
6225 if (mode == connector->dpms)
6226 return;
6227
6228 connector->dpms = mode;
6229
6230 /* Only need to change hw state when actually enabled */
6231 if (connector->encoder)
6232 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6233
6234 intel_modeset_check_state(connector->dev);
6235 }
6236
6237 /* Simple connector->get_hw_state implementation for encoders that support only
6238 * one connector and no cloning and hence the encoder state determines the state
6239 * of the connector. */
6240 bool intel_connector_get_hw_state(struct intel_connector *connector)
6241 {
6242 enum pipe pipe = 0;
6243 struct intel_encoder *encoder = connector->encoder;
6244
6245 return encoder->get_hw_state(encoder, &pipe);
6246 }
6247
6248 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6249 {
6250 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6251 return crtc_state->fdi_lanes;
6252
6253 return 0;
6254 }
6255
6256 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6257 struct intel_crtc_state *pipe_config)
6258 {
6259 struct drm_atomic_state *state = pipe_config->base.state;
6260 struct intel_crtc *other_crtc;
6261 struct intel_crtc_state *other_crtc_state;
6262
6263 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6264 pipe_name(pipe), pipe_config->fdi_lanes);
6265 if (pipe_config->fdi_lanes > 4) {
6266 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6267 pipe_name(pipe), pipe_config->fdi_lanes);
6268 return -EINVAL;
6269 }
6270
6271 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6272 if (pipe_config->fdi_lanes > 2) {
6273 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6274 pipe_config->fdi_lanes);
6275 return -EINVAL;
6276 } else {
6277 return 0;
6278 }
6279 }
6280
6281 if (INTEL_INFO(dev)->num_pipes == 2)
6282 return 0;
6283
6284 /* Ivybridge 3 pipe is really complicated */
6285 switch (pipe) {
6286 case PIPE_A:
6287 return 0;
6288 case PIPE_B:
6289 if (pipe_config->fdi_lanes <= 2)
6290 return 0;
6291
6292 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6293 other_crtc_state =
6294 intel_atomic_get_crtc_state(state, other_crtc);
6295 if (IS_ERR(other_crtc_state))
6296 return PTR_ERR(other_crtc_state);
6297
6298 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6299 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6300 pipe_name(pipe), pipe_config->fdi_lanes);
6301 return -EINVAL;
6302 }
6303 return 0;
6304 case PIPE_C:
6305 if (pipe_config->fdi_lanes > 2) {
6306 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6307 pipe_name(pipe), pipe_config->fdi_lanes);
6308 return -EINVAL;
6309 }
6310
6311 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6312 other_crtc_state =
6313 intel_atomic_get_crtc_state(state, other_crtc);
6314 if (IS_ERR(other_crtc_state))
6315 return PTR_ERR(other_crtc_state);
6316
6317 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6318 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6319 return -EINVAL;
6320 }
6321 return 0;
6322 default:
6323 BUG();
6324 }
6325 }
6326
6327 #define RETRY 1
6328 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6329 struct intel_crtc_state *pipe_config)
6330 {
6331 struct drm_device *dev = intel_crtc->base.dev;
6332 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6333 int lane, link_bw, fdi_dotclock, ret;
6334 bool needs_recompute = false;
6335
6336 retry:
6337 /* FDI is a binary signal running at ~2.7GHz, encoding
6338 * each output octet as 10 bits. The actual frequency
6339 * is stored as a divider into a 100MHz clock, and the
6340 * mode pixel clock is stored in units of 1KHz.
6341 * Hence the bw of each lane in terms of the mode signal
6342 * is:
6343 */
6344 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6345
6346 fdi_dotclock = adjusted_mode->crtc_clock;
6347
6348 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6349 pipe_config->pipe_bpp);
6350
6351 pipe_config->fdi_lanes = lane;
6352
6353 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6354 link_bw, &pipe_config->fdi_m_n);
6355
6356 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6357 intel_crtc->pipe, pipe_config);
6358 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6359 pipe_config->pipe_bpp -= 2*3;
6360 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6361 pipe_config->pipe_bpp);
6362 needs_recompute = true;
6363 pipe_config->bw_constrained = true;
6364
6365 goto retry;
6366 }
6367
6368 if (needs_recompute)
6369 return RETRY;
6370
6371 return ret;
6372 }
6373
6374 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6375 struct intel_crtc_state *pipe_config)
6376 {
6377 pipe_config->ips_enabled = i915.enable_ips &&
6378 hsw_crtc_supports_ips(crtc) &&
6379 pipe_config->pipe_bpp <= 24;
6380 }
6381
6382 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6383 struct intel_crtc_state *pipe_config)
6384 {
6385 struct drm_device *dev = crtc->base.dev;
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6387 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6388 int ret;
6389
6390 /* FIXME should check pixel clock limits on all platforms */
6391 if (INTEL_INFO(dev)->gen < 4) {
6392 int clock_limit =
6393 dev_priv->display.get_display_clock_speed(dev);
6394
6395 /*
6396 * Enable pixel doubling when the dot clock
6397 * is > 90% of the (display) core speed.
6398 *
6399 * GDG double wide on either pipe,
6400 * otherwise pipe A only.
6401 */
6402 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6403 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6404 clock_limit *= 2;
6405 pipe_config->double_wide = true;
6406 }
6407
6408 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6409 return -EINVAL;
6410 }
6411
6412 /*
6413 * Pipe horizontal size must be even in:
6414 * - DVO ganged mode
6415 * - LVDS dual channel mode
6416 * - Double wide pipe
6417 */
6418 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6419 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6420 pipe_config->pipe_src_w &= ~1;
6421
6422 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6423 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6424 */
6425 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6426 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6427 return -EINVAL;
6428
6429 if (HAS_IPS(dev))
6430 hsw_compute_ips_config(crtc, pipe_config);
6431
6432 if (pipe_config->has_pch_encoder)
6433 return ironlake_fdi_compute_config(crtc, pipe_config);
6434
6435 /* FIXME: remove below call once atomic mode set is place and all crtc
6436 * related checks called from atomic_crtc_check function */
6437 ret = 0;
6438 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6439 crtc, pipe_config->base.state);
6440 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6441
6442 return ret;
6443 }
6444
6445 static int skylake_get_display_clock_speed(struct drm_device *dev)
6446 {
6447 struct drm_i915_private *dev_priv = to_i915(dev);
6448 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6449 uint32_t cdctl = I915_READ(CDCLK_CTL);
6450 uint32_t linkrate;
6451
6452 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6453 WARN(1, "LCPLL1 not enabled\n");
6454 return 24000; /* 24MHz is the cd freq with NSSC ref */
6455 }
6456
6457 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6458 return 540000;
6459
6460 linkrate = (I915_READ(DPLL_CTRL1) &
6461 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6462
6463 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6464 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6465 /* vco 8640 */
6466 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6467 case CDCLK_FREQ_450_432:
6468 return 432000;
6469 case CDCLK_FREQ_337_308:
6470 return 308570;
6471 case CDCLK_FREQ_675_617:
6472 return 617140;
6473 default:
6474 WARN(1, "Unknown cd freq selection\n");
6475 }
6476 } else {
6477 /* vco 8100 */
6478 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6479 case CDCLK_FREQ_450_432:
6480 return 450000;
6481 case CDCLK_FREQ_337_308:
6482 return 337500;
6483 case CDCLK_FREQ_675_617:
6484 return 675000;
6485 default:
6486 WARN(1, "Unknown cd freq selection\n");
6487 }
6488 }
6489
6490 /* error case, do as if DPLL0 isn't enabled */
6491 return 24000;
6492 }
6493
6494 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6495 {
6496 struct drm_i915_private *dev_priv = dev->dev_private;
6497 uint32_t lcpll = I915_READ(LCPLL_CTL);
6498 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6499
6500 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6501 return 800000;
6502 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6503 return 450000;
6504 else if (freq == LCPLL_CLK_FREQ_450)
6505 return 450000;
6506 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6507 return 540000;
6508 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6509 return 337500;
6510 else
6511 return 675000;
6512 }
6513
6514 static int haswell_get_display_clock_speed(struct drm_device *dev)
6515 {
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 uint32_t lcpll = I915_READ(LCPLL_CTL);
6518 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6519
6520 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6521 return 800000;
6522 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6523 return 450000;
6524 else if (freq == LCPLL_CLK_FREQ_450)
6525 return 450000;
6526 else if (IS_HSW_ULT(dev))
6527 return 337500;
6528 else
6529 return 540000;
6530 }
6531
6532 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6533 {
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6535 u32 val;
6536 int divider;
6537
6538 if (dev_priv->hpll_freq == 0)
6539 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6540
6541 mutex_lock(&dev_priv->dpio_lock);
6542 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6543 mutex_unlock(&dev_priv->dpio_lock);
6544
6545 divider = val & DISPLAY_FREQUENCY_VALUES;
6546
6547 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6548 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6549 "cdclk change in progress\n");
6550
6551 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6552 }
6553
6554 static int ilk_get_display_clock_speed(struct drm_device *dev)
6555 {
6556 return 450000;
6557 }
6558
6559 static int i945_get_display_clock_speed(struct drm_device *dev)
6560 {
6561 return 400000;
6562 }
6563
6564 static int i915_get_display_clock_speed(struct drm_device *dev)
6565 {
6566 return 333333;
6567 }
6568
6569 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6570 {
6571 return 200000;
6572 }
6573
6574 static int pnv_get_display_clock_speed(struct drm_device *dev)
6575 {
6576 u16 gcfgc = 0;
6577
6578 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6579
6580 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6581 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6582 return 266667;
6583 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6584 return 333333;
6585 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6586 return 444444;
6587 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6588 return 200000;
6589 default:
6590 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6591 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6592 return 133333;
6593 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6594 return 166667;
6595 }
6596 }
6597
6598 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6599 {
6600 u16 gcfgc = 0;
6601
6602 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6603
6604 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6605 return 133333;
6606 else {
6607 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6608 case GC_DISPLAY_CLOCK_333_MHZ:
6609 return 333333;
6610 default:
6611 case GC_DISPLAY_CLOCK_190_200_MHZ:
6612 return 190000;
6613 }
6614 }
6615 }
6616
6617 static int i865_get_display_clock_speed(struct drm_device *dev)
6618 {
6619 return 266667;
6620 }
6621
6622 static int i855_get_display_clock_speed(struct drm_device *dev)
6623 {
6624 u16 hpllcc = 0;
6625 /* Assume that the hardware is in the high speed state. This
6626 * should be the default.
6627 */
6628 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6629 case GC_CLOCK_133_200:
6630 case GC_CLOCK_100_200:
6631 return 200000;
6632 case GC_CLOCK_166_250:
6633 return 250000;
6634 case GC_CLOCK_100_133:
6635 return 133333;
6636 }
6637
6638 /* Shouldn't happen */
6639 return 0;
6640 }
6641
6642 static int i830_get_display_clock_speed(struct drm_device *dev)
6643 {
6644 return 133333;
6645 }
6646
6647 static void
6648 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6649 {
6650 while (*num > DATA_LINK_M_N_MASK ||
6651 *den > DATA_LINK_M_N_MASK) {
6652 *num >>= 1;
6653 *den >>= 1;
6654 }
6655 }
6656
6657 static void compute_m_n(unsigned int m, unsigned int n,
6658 uint32_t *ret_m, uint32_t *ret_n)
6659 {
6660 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6661 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6662 intel_reduce_m_n_ratio(ret_m, ret_n);
6663 }
6664
6665 void
6666 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6667 int pixel_clock, int link_clock,
6668 struct intel_link_m_n *m_n)
6669 {
6670 m_n->tu = 64;
6671
6672 compute_m_n(bits_per_pixel * pixel_clock,
6673 link_clock * nlanes * 8,
6674 &m_n->gmch_m, &m_n->gmch_n);
6675
6676 compute_m_n(pixel_clock, link_clock,
6677 &m_n->link_m, &m_n->link_n);
6678 }
6679
6680 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6681 {
6682 if (i915.panel_use_ssc >= 0)
6683 return i915.panel_use_ssc != 0;
6684 return dev_priv->vbt.lvds_use_ssc
6685 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6686 }
6687
6688 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6689 int num_connectors)
6690 {
6691 struct drm_device *dev = crtc_state->base.crtc->dev;
6692 struct drm_i915_private *dev_priv = dev->dev_private;
6693 int refclk;
6694
6695 WARN_ON(!crtc_state->base.state);
6696
6697 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6698 refclk = 100000;
6699 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6700 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6701 refclk = dev_priv->vbt.lvds_ssc_freq;
6702 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6703 } else if (!IS_GEN2(dev)) {
6704 refclk = 96000;
6705 } else {
6706 refclk = 48000;
6707 }
6708
6709 return refclk;
6710 }
6711
6712 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6713 {
6714 return (1 << dpll->n) << 16 | dpll->m2;
6715 }
6716
6717 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6718 {
6719 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6720 }
6721
6722 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6723 struct intel_crtc_state *crtc_state,
6724 intel_clock_t *reduced_clock)
6725 {
6726 struct drm_device *dev = crtc->base.dev;
6727 u32 fp, fp2 = 0;
6728
6729 if (IS_PINEVIEW(dev)) {
6730 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6731 if (reduced_clock)
6732 fp2 = pnv_dpll_compute_fp(reduced_clock);
6733 } else {
6734 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6735 if (reduced_clock)
6736 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6737 }
6738
6739 crtc_state->dpll_hw_state.fp0 = fp;
6740
6741 crtc->lowfreq_avail = false;
6742 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6743 reduced_clock) {
6744 crtc_state->dpll_hw_state.fp1 = fp2;
6745 crtc->lowfreq_avail = true;
6746 } else {
6747 crtc_state->dpll_hw_state.fp1 = fp;
6748 }
6749 }
6750
6751 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6752 pipe)
6753 {
6754 u32 reg_val;
6755
6756 /*
6757 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6758 * and set it to a reasonable value instead.
6759 */
6760 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6761 reg_val &= 0xffffff00;
6762 reg_val |= 0x00000030;
6763 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6764
6765 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6766 reg_val &= 0x8cffffff;
6767 reg_val = 0x8c000000;
6768 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6769
6770 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6771 reg_val &= 0xffffff00;
6772 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6773
6774 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6775 reg_val &= 0x00ffffff;
6776 reg_val |= 0xb0000000;
6777 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6778 }
6779
6780 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6781 struct intel_link_m_n *m_n)
6782 {
6783 struct drm_device *dev = crtc->base.dev;
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6785 int pipe = crtc->pipe;
6786
6787 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6788 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6789 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6790 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6791 }
6792
6793 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6794 struct intel_link_m_n *m_n,
6795 struct intel_link_m_n *m2_n2)
6796 {
6797 struct drm_device *dev = crtc->base.dev;
6798 struct drm_i915_private *dev_priv = dev->dev_private;
6799 int pipe = crtc->pipe;
6800 enum transcoder transcoder = crtc->config->cpu_transcoder;
6801
6802 if (INTEL_INFO(dev)->gen >= 5) {
6803 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6804 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6805 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6806 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6807 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6808 * for gen < 8) and if DRRS is supported (to make sure the
6809 * registers are not unnecessarily accessed).
6810 */
6811 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6812 crtc->config->has_drrs) {
6813 I915_WRITE(PIPE_DATA_M2(transcoder),
6814 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6815 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6816 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6817 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6818 }
6819 } else {
6820 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6821 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6822 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6823 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6824 }
6825 }
6826
6827 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6828 {
6829 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6830
6831 if (m_n == M1_N1) {
6832 dp_m_n = &crtc->config->dp_m_n;
6833 dp_m2_n2 = &crtc->config->dp_m2_n2;
6834 } else if (m_n == M2_N2) {
6835
6836 /*
6837 * M2_N2 registers are not supported. Hence m2_n2 divider value
6838 * needs to be programmed into M1_N1.
6839 */
6840 dp_m_n = &crtc->config->dp_m2_n2;
6841 } else {
6842 DRM_ERROR("Unsupported divider value\n");
6843 return;
6844 }
6845
6846 if (crtc->config->has_pch_encoder)
6847 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6848 else
6849 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6850 }
6851
6852 static void vlv_update_pll(struct intel_crtc *crtc,
6853 struct intel_crtc_state *pipe_config)
6854 {
6855 u32 dpll, dpll_md;
6856
6857 /*
6858 * Enable DPIO clock input. We should never disable the reference
6859 * clock for pipe B, since VGA hotplug / manual detection depends
6860 * on it.
6861 */
6862 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6863 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6864 /* We should never disable this, set it here for state tracking */
6865 if (crtc->pipe == PIPE_B)
6866 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6867 dpll |= DPLL_VCO_ENABLE;
6868 pipe_config->dpll_hw_state.dpll = dpll;
6869
6870 dpll_md = (pipe_config->pixel_multiplier - 1)
6871 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6872 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6873 }
6874
6875 static void vlv_prepare_pll(struct intel_crtc *crtc,
6876 const struct intel_crtc_state *pipe_config)
6877 {
6878 struct drm_device *dev = crtc->base.dev;
6879 struct drm_i915_private *dev_priv = dev->dev_private;
6880 int pipe = crtc->pipe;
6881 u32 mdiv;
6882 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6883 u32 coreclk, reg_val;
6884
6885 mutex_lock(&dev_priv->dpio_lock);
6886
6887 bestn = pipe_config->dpll.n;
6888 bestm1 = pipe_config->dpll.m1;
6889 bestm2 = pipe_config->dpll.m2;
6890 bestp1 = pipe_config->dpll.p1;
6891 bestp2 = pipe_config->dpll.p2;
6892
6893 /* See eDP HDMI DPIO driver vbios notes doc */
6894
6895 /* PLL B needs special handling */
6896 if (pipe == PIPE_B)
6897 vlv_pllb_recal_opamp(dev_priv, pipe);
6898
6899 /* Set up Tx target for periodic Rcomp update */
6900 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6901
6902 /* Disable target IRef on PLL */
6903 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6904 reg_val &= 0x00ffffff;
6905 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6906
6907 /* Disable fast lock */
6908 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6909
6910 /* Set idtafcrecal before PLL is enabled */
6911 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6912 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6913 mdiv |= ((bestn << DPIO_N_SHIFT));
6914 mdiv |= (1 << DPIO_K_SHIFT);
6915
6916 /*
6917 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6918 * but we don't support that).
6919 * Note: don't use the DAC post divider as it seems unstable.
6920 */
6921 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6923
6924 mdiv |= DPIO_ENABLE_CALIBRATION;
6925 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6926
6927 /* Set HBR and RBR LPF coefficients */
6928 if (pipe_config->port_clock == 162000 ||
6929 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6930 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6931 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6932 0x009f0003);
6933 else
6934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6935 0x00d0000f);
6936
6937 if (pipe_config->has_dp_encoder) {
6938 /* Use SSC source */
6939 if (pipe == PIPE_A)
6940 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6941 0x0df40000);
6942 else
6943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6944 0x0df70000);
6945 } else { /* HDMI or VGA */
6946 /* Use bend source */
6947 if (pipe == PIPE_A)
6948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6949 0x0df70000);
6950 else
6951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6952 0x0df40000);
6953 }
6954
6955 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6956 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6957 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6958 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6959 coreclk |= 0x01000000;
6960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6961
6962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6963 mutex_unlock(&dev_priv->dpio_lock);
6964 }
6965
6966 static void chv_update_pll(struct intel_crtc *crtc,
6967 struct intel_crtc_state *pipe_config)
6968 {
6969 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6970 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6971 DPLL_VCO_ENABLE;
6972 if (crtc->pipe != PIPE_A)
6973 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6974
6975 pipe_config->dpll_hw_state.dpll_md =
6976 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6977 }
6978
6979 static void chv_prepare_pll(struct intel_crtc *crtc,
6980 const struct intel_crtc_state *pipe_config)
6981 {
6982 struct drm_device *dev = crtc->base.dev;
6983 struct drm_i915_private *dev_priv = dev->dev_private;
6984 int pipe = crtc->pipe;
6985 int dpll_reg = DPLL(crtc->pipe);
6986 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6987 u32 loopfilter, tribuf_calcntr;
6988 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6989 u32 dpio_val;
6990 int vco;
6991
6992 bestn = pipe_config->dpll.n;
6993 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6994 bestm1 = pipe_config->dpll.m1;
6995 bestm2 = pipe_config->dpll.m2 >> 22;
6996 bestp1 = pipe_config->dpll.p1;
6997 bestp2 = pipe_config->dpll.p2;
6998 vco = pipe_config->dpll.vco;
6999 dpio_val = 0;
7000 loopfilter = 0;
7001
7002 /*
7003 * Enable Refclk and SSC
7004 */
7005 I915_WRITE(dpll_reg,
7006 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7007
7008 mutex_lock(&dev_priv->dpio_lock);
7009
7010 /* p1 and p2 divider */
7011 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7012 5 << DPIO_CHV_S1_DIV_SHIFT |
7013 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7014 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7015 1 << DPIO_CHV_K_DIV_SHIFT);
7016
7017 /* Feedback post-divider - m2 */
7018 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7019
7020 /* Feedback refclk divider - n and m1 */
7021 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7022 DPIO_CHV_M1_DIV_BY_2 |
7023 1 << DPIO_CHV_N_DIV_SHIFT);
7024
7025 /* M2 fraction division */
7026 if (bestm2_frac)
7027 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7028
7029 /* M2 fraction division enable */
7030 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7031 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7032 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7033 if (bestm2_frac)
7034 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7035 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7036
7037 /* Program digital lock detect threshold */
7038 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7039 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7040 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7041 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7042 if (!bestm2_frac)
7043 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7044 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7045
7046 /* Loop filter */
7047 if (vco == 5400000) {
7048 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7049 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7050 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7051 tribuf_calcntr = 0x9;
7052 } else if (vco <= 6200000) {
7053 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7054 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7055 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7056 tribuf_calcntr = 0x9;
7057 } else if (vco <= 6480000) {
7058 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7059 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7060 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7061 tribuf_calcntr = 0x8;
7062 } else {
7063 /* Not supported. Apply the same limits as in the max case */
7064 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7065 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7066 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7067 tribuf_calcntr = 0;
7068 }
7069 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7070
7071 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7072 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7073 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7074 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7075
7076 /* AFC Recal */
7077 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7078 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7079 DPIO_AFC_RECAL);
7080
7081 mutex_unlock(&dev_priv->dpio_lock);
7082 }
7083
7084 /**
7085 * vlv_force_pll_on - forcibly enable just the PLL
7086 * @dev_priv: i915 private structure
7087 * @pipe: pipe PLL to enable
7088 * @dpll: PLL configuration
7089 *
7090 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7091 * in cases where we need the PLL enabled even when @pipe is not going to
7092 * be enabled.
7093 */
7094 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7095 const struct dpll *dpll)
7096 {
7097 struct intel_crtc *crtc =
7098 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7099 struct intel_crtc_state pipe_config = {
7100 .base.crtc = &crtc->base,
7101 .pixel_multiplier = 1,
7102 .dpll = *dpll,
7103 };
7104
7105 if (IS_CHERRYVIEW(dev)) {
7106 chv_update_pll(crtc, &pipe_config);
7107 chv_prepare_pll(crtc, &pipe_config);
7108 chv_enable_pll(crtc, &pipe_config);
7109 } else {
7110 vlv_update_pll(crtc, &pipe_config);
7111 vlv_prepare_pll(crtc, &pipe_config);
7112 vlv_enable_pll(crtc, &pipe_config);
7113 }
7114 }
7115
7116 /**
7117 * vlv_force_pll_off - forcibly disable just the PLL
7118 * @dev_priv: i915 private structure
7119 * @pipe: pipe PLL to disable
7120 *
7121 * Disable the PLL for @pipe. To be used in cases where we need
7122 * the PLL enabled even when @pipe is not going to be enabled.
7123 */
7124 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7125 {
7126 if (IS_CHERRYVIEW(dev))
7127 chv_disable_pll(to_i915(dev), pipe);
7128 else
7129 vlv_disable_pll(to_i915(dev), pipe);
7130 }
7131
7132 static void i9xx_update_pll(struct intel_crtc *crtc,
7133 struct intel_crtc_state *crtc_state,
7134 intel_clock_t *reduced_clock,
7135 int num_connectors)
7136 {
7137 struct drm_device *dev = crtc->base.dev;
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 u32 dpll;
7140 bool is_sdvo;
7141 struct dpll *clock = &crtc_state->dpll;
7142
7143 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7144
7145 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7146 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7147
7148 dpll = DPLL_VGA_MODE_DIS;
7149
7150 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7151 dpll |= DPLLB_MODE_LVDS;
7152 else
7153 dpll |= DPLLB_MODE_DAC_SERIAL;
7154
7155 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7156 dpll |= (crtc_state->pixel_multiplier - 1)
7157 << SDVO_MULTIPLIER_SHIFT_HIRES;
7158 }
7159
7160 if (is_sdvo)
7161 dpll |= DPLL_SDVO_HIGH_SPEED;
7162
7163 if (crtc_state->has_dp_encoder)
7164 dpll |= DPLL_SDVO_HIGH_SPEED;
7165
7166 /* compute bitmask from p1 value */
7167 if (IS_PINEVIEW(dev))
7168 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7169 else {
7170 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7171 if (IS_G4X(dev) && reduced_clock)
7172 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7173 }
7174 switch (clock->p2) {
7175 case 5:
7176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7177 break;
7178 case 7:
7179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7180 break;
7181 case 10:
7182 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7183 break;
7184 case 14:
7185 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7186 break;
7187 }
7188 if (INTEL_INFO(dev)->gen >= 4)
7189 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7190
7191 if (crtc_state->sdvo_tv_clock)
7192 dpll |= PLL_REF_INPUT_TVCLKINBC;
7193 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7194 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7195 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7196 else
7197 dpll |= PLL_REF_INPUT_DREFCLK;
7198
7199 dpll |= DPLL_VCO_ENABLE;
7200 crtc_state->dpll_hw_state.dpll = dpll;
7201
7202 if (INTEL_INFO(dev)->gen >= 4) {
7203 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7204 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7205 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7206 }
7207 }
7208
7209 static void i8xx_update_pll(struct intel_crtc *crtc,
7210 struct intel_crtc_state *crtc_state,
7211 intel_clock_t *reduced_clock,
7212 int num_connectors)
7213 {
7214 struct drm_device *dev = crtc->base.dev;
7215 struct drm_i915_private *dev_priv = dev->dev_private;
7216 u32 dpll;
7217 struct dpll *clock = &crtc_state->dpll;
7218
7219 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7220
7221 dpll = DPLL_VGA_MODE_DIS;
7222
7223 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7224 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7225 } else {
7226 if (clock->p1 == 2)
7227 dpll |= PLL_P1_DIVIDE_BY_TWO;
7228 else
7229 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7230 if (clock->p2 == 4)
7231 dpll |= PLL_P2_DIVIDE_BY_4;
7232 }
7233
7234 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7235 dpll |= DPLL_DVO_2X_MODE;
7236
7237 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7238 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7239 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7240 else
7241 dpll |= PLL_REF_INPUT_DREFCLK;
7242
7243 dpll |= DPLL_VCO_ENABLE;
7244 crtc_state->dpll_hw_state.dpll = dpll;
7245 }
7246
7247 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7248 {
7249 struct drm_device *dev = intel_crtc->base.dev;
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 enum pipe pipe = intel_crtc->pipe;
7252 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7253 struct drm_display_mode *adjusted_mode =
7254 &intel_crtc->config->base.adjusted_mode;
7255 uint32_t crtc_vtotal, crtc_vblank_end;
7256 int vsyncshift = 0;
7257
7258 /* We need to be careful not to changed the adjusted mode, for otherwise
7259 * the hw state checker will get angry at the mismatch. */
7260 crtc_vtotal = adjusted_mode->crtc_vtotal;
7261 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7262
7263 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7264 /* the chip adds 2 halflines automatically */
7265 crtc_vtotal -= 1;
7266 crtc_vblank_end -= 1;
7267
7268 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7269 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7270 else
7271 vsyncshift = adjusted_mode->crtc_hsync_start -
7272 adjusted_mode->crtc_htotal / 2;
7273 if (vsyncshift < 0)
7274 vsyncshift += adjusted_mode->crtc_htotal;
7275 }
7276
7277 if (INTEL_INFO(dev)->gen > 3)
7278 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7279
7280 I915_WRITE(HTOTAL(cpu_transcoder),
7281 (adjusted_mode->crtc_hdisplay - 1) |
7282 ((adjusted_mode->crtc_htotal - 1) << 16));
7283 I915_WRITE(HBLANK(cpu_transcoder),
7284 (adjusted_mode->crtc_hblank_start - 1) |
7285 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7286 I915_WRITE(HSYNC(cpu_transcoder),
7287 (adjusted_mode->crtc_hsync_start - 1) |
7288 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7289
7290 I915_WRITE(VTOTAL(cpu_transcoder),
7291 (adjusted_mode->crtc_vdisplay - 1) |
7292 ((crtc_vtotal - 1) << 16));
7293 I915_WRITE(VBLANK(cpu_transcoder),
7294 (adjusted_mode->crtc_vblank_start - 1) |
7295 ((crtc_vblank_end - 1) << 16));
7296 I915_WRITE(VSYNC(cpu_transcoder),
7297 (adjusted_mode->crtc_vsync_start - 1) |
7298 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7299
7300 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7301 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7302 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7303 * bits. */
7304 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7305 (pipe == PIPE_B || pipe == PIPE_C))
7306 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7307
7308 /* pipesrc controls the size that is scaled from, which should
7309 * always be the user's requested size.
7310 */
7311 I915_WRITE(PIPESRC(pipe),
7312 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7313 (intel_crtc->config->pipe_src_h - 1));
7314 }
7315
7316 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7317 struct intel_crtc_state *pipe_config)
7318 {
7319 struct drm_device *dev = crtc->base.dev;
7320 struct drm_i915_private *dev_priv = dev->dev_private;
7321 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7322 uint32_t tmp;
7323
7324 tmp = I915_READ(HTOTAL(cpu_transcoder));
7325 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7326 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7327 tmp = I915_READ(HBLANK(cpu_transcoder));
7328 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7329 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7330 tmp = I915_READ(HSYNC(cpu_transcoder));
7331 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7332 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7333
7334 tmp = I915_READ(VTOTAL(cpu_transcoder));
7335 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7336 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7337 tmp = I915_READ(VBLANK(cpu_transcoder));
7338 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7339 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7340 tmp = I915_READ(VSYNC(cpu_transcoder));
7341 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7342 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7343
7344 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7345 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7346 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7347 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7348 }
7349
7350 tmp = I915_READ(PIPESRC(crtc->pipe));
7351 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7352 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7353
7354 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7355 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7356 }
7357
7358 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7359 struct intel_crtc_state *pipe_config)
7360 {
7361 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7362 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7363 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7364 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7365
7366 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7367 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7368 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7369 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7370
7371 mode->flags = pipe_config->base.adjusted_mode.flags;
7372
7373 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7374 mode->flags |= pipe_config->base.adjusted_mode.flags;
7375 }
7376
7377 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7378 {
7379 struct drm_device *dev = intel_crtc->base.dev;
7380 struct drm_i915_private *dev_priv = dev->dev_private;
7381 uint32_t pipeconf;
7382
7383 pipeconf = 0;
7384
7385 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7386 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7387 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7388
7389 if (intel_crtc->config->double_wide)
7390 pipeconf |= PIPECONF_DOUBLE_WIDE;
7391
7392 /* only g4x and later have fancy bpc/dither controls */
7393 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7394 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7395 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7396 pipeconf |= PIPECONF_DITHER_EN |
7397 PIPECONF_DITHER_TYPE_SP;
7398
7399 switch (intel_crtc->config->pipe_bpp) {
7400 case 18:
7401 pipeconf |= PIPECONF_6BPC;
7402 break;
7403 case 24:
7404 pipeconf |= PIPECONF_8BPC;
7405 break;
7406 case 30:
7407 pipeconf |= PIPECONF_10BPC;
7408 break;
7409 default:
7410 /* Case prevented by intel_choose_pipe_bpp_dither. */
7411 BUG();
7412 }
7413 }
7414
7415 if (HAS_PIPE_CXSR(dev)) {
7416 if (intel_crtc->lowfreq_avail) {
7417 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7418 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7419 } else {
7420 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7421 }
7422 }
7423
7424 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7425 if (INTEL_INFO(dev)->gen < 4 ||
7426 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7427 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7428 else
7429 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7430 } else
7431 pipeconf |= PIPECONF_PROGRESSIVE;
7432
7433 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7434 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7435
7436 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7437 POSTING_READ(PIPECONF(intel_crtc->pipe));
7438 }
7439
7440 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7441 struct intel_crtc_state *crtc_state)
7442 {
7443 struct drm_device *dev = crtc->base.dev;
7444 struct drm_i915_private *dev_priv = dev->dev_private;
7445 int refclk, num_connectors = 0;
7446 intel_clock_t clock, reduced_clock;
7447 bool ok, has_reduced_clock = false;
7448 bool is_lvds = false, is_dsi = false;
7449 struct intel_encoder *encoder;
7450 const intel_limit_t *limit;
7451 struct drm_atomic_state *state = crtc_state->base.state;
7452 struct drm_connector *connector;
7453 struct drm_connector_state *connector_state;
7454 int i;
7455
7456 memset(&crtc_state->dpll_hw_state, 0,
7457 sizeof(crtc_state->dpll_hw_state));
7458
7459 for_each_connector_in_state(state, connector, connector_state, i) {
7460 if (connector_state->crtc != &crtc->base)
7461 continue;
7462
7463 encoder = to_intel_encoder(connector_state->best_encoder);
7464
7465 switch (encoder->type) {
7466 case INTEL_OUTPUT_LVDS:
7467 is_lvds = true;
7468 break;
7469 case INTEL_OUTPUT_DSI:
7470 is_dsi = true;
7471 break;
7472 default:
7473 break;
7474 }
7475
7476 num_connectors++;
7477 }
7478
7479 if (is_dsi)
7480 return 0;
7481
7482 if (!crtc_state->clock_set) {
7483 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7484
7485 /*
7486 * Returns a set of divisors for the desired target clock with
7487 * the given refclk, or FALSE. The returned values represent
7488 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7489 * 2) / p1 / p2.
7490 */
7491 limit = intel_limit(crtc_state, refclk);
7492 ok = dev_priv->display.find_dpll(limit, crtc_state,
7493 crtc_state->port_clock,
7494 refclk, NULL, &clock);
7495 if (!ok) {
7496 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7497 return -EINVAL;
7498 }
7499
7500 if (is_lvds && dev_priv->lvds_downclock_avail) {
7501 /*
7502 * Ensure we match the reduced clock's P to the target
7503 * clock. If the clocks don't match, we can't switch
7504 * the display clock by using the FP0/FP1. In such case
7505 * we will disable the LVDS downclock feature.
7506 */
7507 has_reduced_clock =
7508 dev_priv->display.find_dpll(limit, crtc_state,
7509 dev_priv->lvds_downclock,
7510 refclk, &clock,
7511 &reduced_clock);
7512 }
7513 /* Compat-code for transition, will disappear. */
7514 crtc_state->dpll.n = clock.n;
7515 crtc_state->dpll.m1 = clock.m1;
7516 crtc_state->dpll.m2 = clock.m2;
7517 crtc_state->dpll.p1 = clock.p1;
7518 crtc_state->dpll.p2 = clock.p2;
7519 }
7520
7521 if (IS_GEN2(dev)) {
7522 i8xx_update_pll(crtc, crtc_state,
7523 has_reduced_clock ? &reduced_clock : NULL,
7524 num_connectors);
7525 } else if (IS_CHERRYVIEW(dev)) {
7526 chv_update_pll(crtc, crtc_state);
7527 } else if (IS_VALLEYVIEW(dev)) {
7528 vlv_update_pll(crtc, crtc_state);
7529 } else {
7530 i9xx_update_pll(crtc, crtc_state,
7531 has_reduced_clock ? &reduced_clock : NULL,
7532 num_connectors);
7533 }
7534
7535 return 0;
7536 }
7537
7538 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7539 struct intel_crtc_state *pipe_config)
7540 {
7541 struct drm_device *dev = crtc->base.dev;
7542 struct drm_i915_private *dev_priv = dev->dev_private;
7543 uint32_t tmp;
7544
7545 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7546 return;
7547
7548 tmp = I915_READ(PFIT_CONTROL);
7549 if (!(tmp & PFIT_ENABLE))
7550 return;
7551
7552 /* Check whether the pfit is attached to our pipe. */
7553 if (INTEL_INFO(dev)->gen < 4) {
7554 if (crtc->pipe != PIPE_B)
7555 return;
7556 } else {
7557 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7558 return;
7559 }
7560
7561 pipe_config->gmch_pfit.control = tmp;
7562 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7563 if (INTEL_INFO(dev)->gen < 5)
7564 pipe_config->gmch_pfit.lvds_border_bits =
7565 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7566 }
7567
7568 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7569 struct intel_crtc_state *pipe_config)
7570 {
7571 struct drm_device *dev = crtc->base.dev;
7572 struct drm_i915_private *dev_priv = dev->dev_private;
7573 int pipe = pipe_config->cpu_transcoder;
7574 intel_clock_t clock;
7575 u32 mdiv;
7576 int refclk = 100000;
7577
7578 /* In case of MIPI DPLL will not even be used */
7579 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7580 return;
7581
7582 mutex_lock(&dev_priv->dpio_lock);
7583 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7584 mutex_unlock(&dev_priv->dpio_lock);
7585
7586 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7587 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7588 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7589 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7590 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7591
7592 vlv_clock(refclk, &clock);
7593
7594 /* clock.dot is the fast clock */
7595 pipe_config->port_clock = clock.dot / 5;
7596 }
7597
7598 static void
7599 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7600 struct intel_initial_plane_config *plane_config)
7601 {
7602 struct drm_device *dev = crtc->base.dev;
7603 struct drm_i915_private *dev_priv = dev->dev_private;
7604 u32 val, base, offset;
7605 int pipe = crtc->pipe, plane = crtc->plane;
7606 int fourcc, pixel_format;
7607 unsigned int aligned_height;
7608 struct drm_framebuffer *fb;
7609 struct intel_framebuffer *intel_fb;
7610
7611 val = I915_READ(DSPCNTR(plane));
7612 if (!(val & DISPLAY_PLANE_ENABLE))
7613 return;
7614
7615 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7616 if (!intel_fb) {
7617 DRM_DEBUG_KMS("failed to alloc fb\n");
7618 return;
7619 }
7620
7621 fb = &intel_fb->base;
7622
7623 if (INTEL_INFO(dev)->gen >= 4) {
7624 if (val & DISPPLANE_TILED) {
7625 plane_config->tiling = I915_TILING_X;
7626 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7627 }
7628 }
7629
7630 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7631 fourcc = i9xx_format_to_fourcc(pixel_format);
7632 fb->pixel_format = fourcc;
7633 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7634
7635 if (INTEL_INFO(dev)->gen >= 4) {
7636 if (plane_config->tiling)
7637 offset = I915_READ(DSPTILEOFF(plane));
7638 else
7639 offset = I915_READ(DSPLINOFF(plane));
7640 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7641 } else {
7642 base = I915_READ(DSPADDR(plane));
7643 }
7644 plane_config->base = base;
7645
7646 val = I915_READ(PIPESRC(pipe));
7647 fb->width = ((val >> 16) & 0xfff) + 1;
7648 fb->height = ((val >> 0) & 0xfff) + 1;
7649
7650 val = I915_READ(DSPSTRIDE(pipe));
7651 fb->pitches[0] = val & 0xffffffc0;
7652
7653 aligned_height = intel_fb_align_height(dev, fb->height,
7654 fb->pixel_format,
7655 fb->modifier[0]);
7656
7657 plane_config->size = fb->pitches[0] * aligned_height;
7658
7659 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7660 pipe_name(pipe), plane, fb->width, fb->height,
7661 fb->bits_per_pixel, base, fb->pitches[0],
7662 plane_config->size);
7663
7664 plane_config->fb = intel_fb;
7665 }
7666
7667 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7668 struct intel_crtc_state *pipe_config)
7669 {
7670 struct drm_device *dev = crtc->base.dev;
7671 struct drm_i915_private *dev_priv = dev->dev_private;
7672 int pipe = pipe_config->cpu_transcoder;
7673 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7674 intel_clock_t clock;
7675 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7676 int refclk = 100000;
7677
7678 mutex_lock(&dev_priv->dpio_lock);
7679 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7680 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7681 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7682 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7683 mutex_unlock(&dev_priv->dpio_lock);
7684
7685 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7686 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7687 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7688 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7689 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7690
7691 chv_clock(refclk, &clock);
7692
7693 /* clock.dot is the fast clock */
7694 pipe_config->port_clock = clock.dot / 5;
7695 }
7696
7697 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7698 struct intel_crtc_state *pipe_config)
7699 {
7700 struct drm_device *dev = crtc->base.dev;
7701 struct drm_i915_private *dev_priv = dev->dev_private;
7702 uint32_t tmp;
7703
7704 if (!intel_display_power_is_enabled(dev_priv,
7705 POWER_DOMAIN_PIPE(crtc->pipe)))
7706 return false;
7707
7708 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7709 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7710
7711 tmp = I915_READ(PIPECONF(crtc->pipe));
7712 if (!(tmp & PIPECONF_ENABLE))
7713 return false;
7714
7715 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7716 switch (tmp & PIPECONF_BPC_MASK) {
7717 case PIPECONF_6BPC:
7718 pipe_config->pipe_bpp = 18;
7719 break;
7720 case PIPECONF_8BPC:
7721 pipe_config->pipe_bpp = 24;
7722 break;
7723 case PIPECONF_10BPC:
7724 pipe_config->pipe_bpp = 30;
7725 break;
7726 default:
7727 break;
7728 }
7729 }
7730
7731 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7732 pipe_config->limited_color_range = true;
7733
7734 if (INTEL_INFO(dev)->gen < 4)
7735 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7736
7737 intel_get_pipe_timings(crtc, pipe_config);
7738
7739 i9xx_get_pfit_config(crtc, pipe_config);
7740
7741 if (INTEL_INFO(dev)->gen >= 4) {
7742 tmp = I915_READ(DPLL_MD(crtc->pipe));
7743 pipe_config->pixel_multiplier =
7744 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7745 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7746 pipe_config->dpll_hw_state.dpll_md = tmp;
7747 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7748 tmp = I915_READ(DPLL(crtc->pipe));
7749 pipe_config->pixel_multiplier =
7750 ((tmp & SDVO_MULTIPLIER_MASK)
7751 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7752 } else {
7753 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7754 * port and will be fixed up in the encoder->get_config
7755 * function. */
7756 pipe_config->pixel_multiplier = 1;
7757 }
7758 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7759 if (!IS_VALLEYVIEW(dev)) {
7760 /*
7761 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7762 * on 830. Filter it out here so that we don't
7763 * report errors due to that.
7764 */
7765 if (IS_I830(dev))
7766 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7767
7768 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7769 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7770 } else {
7771 /* Mask out read-only status bits. */
7772 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7773 DPLL_PORTC_READY_MASK |
7774 DPLL_PORTB_READY_MASK);
7775 }
7776
7777 if (IS_CHERRYVIEW(dev))
7778 chv_crtc_clock_get(crtc, pipe_config);
7779 else if (IS_VALLEYVIEW(dev))
7780 vlv_crtc_clock_get(crtc, pipe_config);
7781 else
7782 i9xx_crtc_clock_get(crtc, pipe_config);
7783
7784 return true;
7785 }
7786
7787 static void ironlake_init_pch_refclk(struct drm_device *dev)
7788 {
7789 struct drm_i915_private *dev_priv = dev->dev_private;
7790 struct intel_encoder *encoder;
7791 u32 val, final;
7792 bool has_lvds = false;
7793 bool has_cpu_edp = false;
7794 bool has_panel = false;
7795 bool has_ck505 = false;
7796 bool can_ssc = false;
7797
7798 /* We need to take the global config into account */
7799 for_each_intel_encoder(dev, encoder) {
7800 switch (encoder->type) {
7801 case INTEL_OUTPUT_LVDS:
7802 has_panel = true;
7803 has_lvds = true;
7804 break;
7805 case INTEL_OUTPUT_EDP:
7806 has_panel = true;
7807 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7808 has_cpu_edp = true;
7809 break;
7810 default:
7811 break;
7812 }
7813 }
7814
7815 if (HAS_PCH_IBX(dev)) {
7816 has_ck505 = dev_priv->vbt.display_clock_mode;
7817 can_ssc = has_ck505;
7818 } else {
7819 has_ck505 = false;
7820 can_ssc = true;
7821 }
7822
7823 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7824 has_panel, has_lvds, has_ck505);
7825
7826 /* Ironlake: try to setup display ref clock before DPLL
7827 * enabling. This is only under driver's control after
7828 * PCH B stepping, previous chipset stepping should be
7829 * ignoring this setting.
7830 */
7831 val = I915_READ(PCH_DREF_CONTROL);
7832
7833 /* As we must carefully and slowly disable/enable each source in turn,
7834 * compute the final state we want first and check if we need to
7835 * make any changes at all.
7836 */
7837 final = val;
7838 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7839 if (has_ck505)
7840 final |= DREF_NONSPREAD_CK505_ENABLE;
7841 else
7842 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7843
7844 final &= ~DREF_SSC_SOURCE_MASK;
7845 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7846 final &= ~DREF_SSC1_ENABLE;
7847
7848 if (has_panel) {
7849 final |= DREF_SSC_SOURCE_ENABLE;
7850
7851 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7852 final |= DREF_SSC1_ENABLE;
7853
7854 if (has_cpu_edp) {
7855 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7856 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7857 else
7858 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7859 } else
7860 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7861 } else {
7862 final |= DREF_SSC_SOURCE_DISABLE;
7863 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7864 }
7865
7866 if (final == val)
7867 return;
7868
7869 /* Always enable nonspread source */
7870 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7871
7872 if (has_ck505)
7873 val |= DREF_NONSPREAD_CK505_ENABLE;
7874 else
7875 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7876
7877 if (has_panel) {
7878 val &= ~DREF_SSC_SOURCE_MASK;
7879 val |= DREF_SSC_SOURCE_ENABLE;
7880
7881 /* SSC must be turned on before enabling the CPU output */
7882 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7883 DRM_DEBUG_KMS("Using SSC on panel\n");
7884 val |= DREF_SSC1_ENABLE;
7885 } else
7886 val &= ~DREF_SSC1_ENABLE;
7887
7888 /* Get SSC going before enabling the outputs */
7889 I915_WRITE(PCH_DREF_CONTROL, val);
7890 POSTING_READ(PCH_DREF_CONTROL);
7891 udelay(200);
7892
7893 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7894
7895 /* Enable CPU source on CPU attached eDP */
7896 if (has_cpu_edp) {
7897 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7898 DRM_DEBUG_KMS("Using SSC on eDP\n");
7899 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7900 } else
7901 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7902 } else
7903 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7904
7905 I915_WRITE(PCH_DREF_CONTROL, val);
7906 POSTING_READ(PCH_DREF_CONTROL);
7907 udelay(200);
7908 } else {
7909 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7910
7911 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7912
7913 /* Turn off CPU output */
7914 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7915
7916 I915_WRITE(PCH_DREF_CONTROL, val);
7917 POSTING_READ(PCH_DREF_CONTROL);
7918 udelay(200);
7919
7920 /* Turn off the SSC source */
7921 val &= ~DREF_SSC_SOURCE_MASK;
7922 val |= DREF_SSC_SOURCE_DISABLE;
7923
7924 /* Turn off SSC1 */
7925 val &= ~DREF_SSC1_ENABLE;
7926
7927 I915_WRITE(PCH_DREF_CONTROL, val);
7928 POSTING_READ(PCH_DREF_CONTROL);
7929 udelay(200);
7930 }
7931
7932 BUG_ON(val != final);
7933 }
7934
7935 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7936 {
7937 uint32_t tmp;
7938
7939 tmp = I915_READ(SOUTH_CHICKEN2);
7940 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7941 I915_WRITE(SOUTH_CHICKEN2, tmp);
7942
7943 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7944 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7945 DRM_ERROR("FDI mPHY reset assert timeout\n");
7946
7947 tmp = I915_READ(SOUTH_CHICKEN2);
7948 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7949 I915_WRITE(SOUTH_CHICKEN2, tmp);
7950
7951 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7952 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7953 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7954 }
7955
7956 /* WaMPhyProgramming:hsw */
7957 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7958 {
7959 uint32_t tmp;
7960
7961 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7962 tmp &= ~(0xFF << 24);
7963 tmp |= (0x12 << 24);
7964 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7965
7966 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7967 tmp |= (1 << 11);
7968 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7969
7970 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7971 tmp |= (1 << 11);
7972 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7973
7974 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7975 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7976 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7977
7978 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7979 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7980 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7981
7982 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7983 tmp &= ~(7 << 13);
7984 tmp |= (5 << 13);
7985 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7986
7987 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7988 tmp &= ~(7 << 13);
7989 tmp |= (5 << 13);
7990 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7991
7992 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7993 tmp &= ~0xFF;
7994 tmp |= 0x1C;
7995 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7996
7997 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7998 tmp &= ~0xFF;
7999 tmp |= 0x1C;
8000 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8001
8002 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8003 tmp &= ~(0xFF << 16);
8004 tmp |= (0x1C << 16);
8005 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8006
8007 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8008 tmp &= ~(0xFF << 16);
8009 tmp |= (0x1C << 16);
8010 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8011
8012 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8013 tmp |= (1 << 27);
8014 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8015
8016 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8017 tmp |= (1 << 27);
8018 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8019
8020 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8021 tmp &= ~(0xF << 28);
8022 tmp |= (4 << 28);
8023 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8024
8025 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8026 tmp &= ~(0xF << 28);
8027 tmp |= (4 << 28);
8028 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8029 }
8030
8031 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8032 * Programming" based on the parameters passed:
8033 * - Sequence to enable CLKOUT_DP
8034 * - Sequence to enable CLKOUT_DP without spread
8035 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8036 */
8037 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8038 bool with_fdi)
8039 {
8040 struct drm_i915_private *dev_priv = dev->dev_private;
8041 uint32_t reg, tmp;
8042
8043 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8044 with_spread = true;
8045 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8046 with_fdi, "LP PCH doesn't have FDI\n"))
8047 with_fdi = false;
8048
8049 mutex_lock(&dev_priv->dpio_lock);
8050
8051 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8052 tmp &= ~SBI_SSCCTL_DISABLE;
8053 tmp |= SBI_SSCCTL_PATHALT;
8054 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8055
8056 udelay(24);
8057
8058 if (with_spread) {
8059 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8060 tmp &= ~SBI_SSCCTL_PATHALT;
8061 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8062
8063 if (with_fdi) {
8064 lpt_reset_fdi_mphy(dev_priv);
8065 lpt_program_fdi_mphy(dev_priv);
8066 }
8067 }
8068
8069 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8070 SBI_GEN0 : SBI_DBUFF0;
8071 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8072 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8073 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8074
8075 mutex_unlock(&dev_priv->dpio_lock);
8076 }
8077
8078 /* Sequence to disable CLKOUT_DP */
8079 static void lpt_disable_clkout_dp(struct drm_device *dev)
8080 {
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082 uint32_t reg, tmp;
8083
8084 mutex_lock(&dev_priv->dpio_lock);
8085
8086 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8087 SBI_GEN0 : SBI_DBUFF0;
8088 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8089 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8090 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8091
8092 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8093 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8094 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8095 tmp |= SBI_SSCCTL_PATHALT;
8096 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8097 udelay(32);
8098 }
8099 tmp |= SBI_SSCCTL_DISABLE;
8100 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8101 }
8102
8103 mutex_unlock(&dev_priv->dpio_lock);
8104 }
8105
8106 static void lpt_init_pch_refclk(struct drm_device *dev)
8107 {
8108 struct intel_encoder *encoder;
8109 bool has_vga = false;
8110
8111 for_each_intel_encoder(dev, encoder) {
8112 switch (encoder->type) {
8113 case INTEL_OUTPUT_ANALOG:
8114 has_vga = true;
8115 break;
8116 default:
8117 break;
8118 }
8119 }
8120
8121 if (has_vga)
8122 lpt_enable_clkout_dp(dev, true, true);
8123 else
8124 lpt_disable_clkout_dp(dev);
8125 }
8126
8127 /*
8128 * Initialize reference clocks when the driver loads
8129 */
8130 void intel_init_pch_refclk(struct drm_device *dev)
8131 {
8132 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8133 ironlake_init_pch_refclk(dev);
8134 else if (HAS_PCH_LPT(dev))
8135 lpt_init_pch_refclk(dev);
8136 }
8137
8138 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8139 {
8140 struct drm_device *dev = crtc_state->base.crtc->dev;
8141 struct drm_i915_private *dev_priv = dev->dev_private;
8142 struct drm_atomic_state *state = crtc_state->base.state;
8143 struct drm_connector *connector;
8144 struct drm_connector_state *connector_state;
8145 struct intel_encoder *encoder;
8146 int num_connectors = 0, i;
8147 bool is_lvds = false;
8148
8149 for_each_connector_in_state(state, connector, connector_state, i) {
8150 if (connector_state->crtc != crtc_state->base.crtc)
8151 continue;
8152
8153 encoder = to_intel_encoder(connector_state->best_encoder);
8154
8155 switch (encoder->type) {
8156 case INTEL_OUTPUT_LVDS:
8157 is_lvds = true;
8158 break;
8159 default:
8160 break;
8161 }
8162 num_connectors++;
8163 }
8164
8165 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8166 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8167 dev_priv->vbt.lvds_ssc_freq);
8168 return dev_priv->vbt.lvds_ssc_freq;
8169 }
8170
8171 return 120000;
8172 }
8173
8174 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8175 {
8176 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8178 int pipe = intel_crtc->pipe;
8179 uint32_t val;
8180
8181 val = 0;
8182
8183 switch (intel_crtc->config->pipe_bpp) {
8184 case 18:
8185 val |= PIPECONF_6BPC;
8186 break;
8187 case 24:
8188 val |= PIPECONF_8BPC;
8189 break;
8190 case 30:
8191 val |= PIPECONF_10BPC;
8192 break;
8193 case 36:
8194 val |= PIPECONF_12BPC;
8195 break;
8196 default:
8197 /* Case prevented by intel_choose_pipe_bpp_dither. */
8198 BUG();
8199 }
8200
8201 if (intel_crtc->config->dither)
8202 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8203
8204 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8205 val |= PIPECONF_INTERLACED_ILK;
8206 else
8207 val |= PIPECONF_PROGRESSIVE;
8208
8209 if (intel_crtc->config->limited_color_range)
8210 val |= PIPECONF_COLOR_RANGE_SELECT;
8211
8212 I915_WRITE(PIPECONF(pipe), val);
8213 POSTING_READ(PIPECONF(pipe));
8214 }
8215
8216 /*
8217 * Set up the pipe CSC unit.
8218 *
8219 * Currently only full range RGB to limited range RGB conversion
8220 * is supported, but eventually this should handle various
8221 * RGB<->YCbCr scenarios as well.
8222 */
8223 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8224 {
8225 struct drm_device *dev = crtc->dev;
8226 struct drm_i915_private *dev_priv = dev->dev_private;
8227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8228 int pipe = intel_crtc->pipe;
8229 uint16_t coeff = 0x7800; /* 1.0 */
8230
8231 /*
8232 * TODO: Check what kind of values actually come out of the pipe
8233 * with these coeff/postoff values and adjust to get the best
8234 * accuracy. Perhaps we even need to take the bpc value into
8235 * consideration.
8236 */
8237
8238 if (intel_crtc->config->limited_color_range)
8239 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8240
8241 /*
8242 * GY/GU and RY/RU should be the other way around according
8243 * to BSpec, but reality doesn't agree. Just set them up in
8244 * a way that results in the correct picture.
8245 */
8246 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8247 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8248
8249 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8250 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8251
8252 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8253 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8254
8255 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8256 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8257 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8258
8259 if (INTEL_INFO(dev)->gen > 6) {
8260 uint16_t postoff = 0;
8261
8262 if (intel_crtc->config->limited_color_range)
8263 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8264
8265 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8266 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8267 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8268
8269 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8270 } else {
8271 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8272
8273 if (intel_crtc->config->limited_color_range)
8274 mode |= CSC_BLACK_SCREEN_OFFSET;
8275
8276 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8277 }
8278 }
8279
8280 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8281 {
8282 struct drm_device *dev = crtc->dev;
8283 struct drm_i915_private *dev_priv = dev->dev_private;
8284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8285 enum pipe pipe = intel_crtc->pipe;
8286 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8287 uint32_t val;
8288
8289 val = 0;
8290
8291 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8292 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8293
8294 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8295 val |= PIPECONF_INTERLACED_ILK;
8296 else
8297 val |= PIPECONF_PROGRESSIVE;
8298
8299 I915_WRITE(PIPECONF(cpu_transcoder), val);
8300 POSTING_READ(PIPECONF(cpu_transcoder));
8301
8302 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8303 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8304
8305 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8306 val = 0;
8307
8308 switch (intel_crtc->config->pipe_bpp) {
8309 case 18:
8310 val |= PIPEMISC_DITHER_6_BPC;
8311 break;
8312 case 24:
8313 val |= PIPEMISC_DITHER_8_BPC;
8314 break;
8315 case 30:
8316 val |= PIPEMISC_DITHER_10_BPC;
8317 break;
8318 case 36:
8319 val |= PIPEMISC_DITHER_12_BPC;
8320 break;
8321 default:
8322 /* Case prevented by pipe_config_set_bpp. */
8323 BUG();
8324 }
8325
8326 if (intel_crtc->config->dither)
8327 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8328
8329 I915_WRITE(PIPEMISC(pipe), val);
8330 }
8331 }
8332
8333 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8334 struct intel_crtc_state *crtc_state,
8335 intel_clock_t *clock,
8336 bool *has_reduced_clock,
8337 intel_clock_t *reduced_clock)
8338 {
8339 struct drm_device *dev = crtc->dev;
8340 struct drm_i915_private *dev_priv = dev->dev_private;
8341 int refclk;
8342 const intel_limit_t *limit;
8343 bool ret, is_lvds = false;
8344
8345 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8346
8347 refclk = ironlake_get_refclk(crtc_state);
8348
8349 /*
8350 * Returns a set of divisors for the desired target clock with the given
8351 * refclk, or FALSE. The returned values represent the clock equation:
8352 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8353 */
8354 limit = intel_limit(crtc_state, refclk);
8355 ret = dev_priv->display.find_dpll(limit, crtc_state,
8356 crtc_state->port_clock,
8357 refclk, NULL, clock);
8358 if (!ret)
8359 return false;
8360
8361 if (is_lvds && dev_priv->lvds_downclock_avail) {
8362 /*
8363 * Ensure we match the reduced clock's P to the target clock.
8364 * If the clocks don't match, we can't switch the display clock
8365 * by using the FP0/FP1. In such case we will disable the LVDS
8366 * downclock feature.
8367 */
8368 *has_reduced_clock =
8369 dev_priv->display.find_dpll(limit, crtc_state,
8370 dev_priv->lvds_downclock,
8371 refclk, clock,
8372 reduced_clock);
8373 }
8374
8375 return true;
8376 }
8377
8378 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8379 {
8380 /*
8381 * Account for spread spectrum to avoid
8382 * oversubscribing the link. Max center spread
8383 * is 2.5%; use 5% for safety's sake.
8384 */
8385 u32 bps = target_clock * bpp * 21 / 20;
8386 return DIV_ROUND_UP(bps, link_bw * 8);
8387 }
8388
8389 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8390 {
8391 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8392 }
8393
8394 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8395 struct intel_crtc_state *crtc_state,
8396 u32 *fp,
8397 intel_clock_t *reduced_clock, u32 *fp2)
8398 {
8399 struct drm_crtc *crtc = &intel_crtc->base;
8400 struct drm_device *dev = crtc->dev;
8401 struct drm_i915_private *dev_priv = dev->dev_private;
8402 struct drm_atomic_state *state = crtc_state->base.state;
8403 struct drm_connector *connector;
8404 struct drm_connector_state *connector_state;
8405 struct intel_encoder *encoder;
8406 uint32_t dpll;
8407 int factor, num_connectors = 0, i;
8408 bool is_lvds = false, is_sdvo = false;
8409
8410 for_each_connector_in_state(state, connector, connector_state, i) {
8411 if (connector_state->crtc != crtc_state->base.crtc)
8412 continue;
8413
8414 encoder = to_intel_encoder(connector_state->best_encoder);
8415
8416 switch (encoder->type) {
8417 case INTEL_OUTPUT_LVDS:
8418 is_lvds = true;
8419 break;
8420 case INTEL_OUTPUT_SDVO:
8421 case INTEL_OUTPUT_HDMI:
8422 is_sdvo = true;
8423 break;
8424 default:
8425 break;
8426 }
8427
8428 num_connectors++;
8429 }
8430
8431 /* Enable autotuning of the PLL clock (if permissible) */
8432 factor = 21;
8433 if (is_lvds) {
8434 if ((intel_panel_use_ssc(dev_priv) &&
8435 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8436 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8437 factor = 25;
8438 } else if (crtc_state->sdvo_tv_clock)
8439 factor = 20;
8440
8441 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8442 *fp |= FP_CB_TUNE;
8443
8444 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8445 *fp2 |= FP_CB_TUNE;
8446
8447 dpll = 0;
8448
8449 if (is_lvds)
8450 dpll |= DPLLB_MODE_LVDS;
8451 else
8452 dpll |= DPLLB_MODE_DAC_SERIAL;
8453
8454 dpll |= (crtc_state->pixel_multiplier - 1)
8455 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8456
8457 if (is_sdvo)
8458 dpll |= DPLL_SDVO_HIGH_SPEED;
8459 if (crtc_state->has_dp_encoder)
8460 dpll |= DPLL_SDVO_HIGH_SPEED;
8461
8462 /* compute bitmask from p1 value */
8463 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8464 /* also FPA1 */
8465 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8466
8467 switch (crtc_state->dpll.p2) {
8468 case 5:
8469 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8470 break;
8471 case 7:
8472 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8473 break;
8474 case 10:
8475 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8476 break;
8477 case 14:
8478 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8479 break;
8480 }
8481
8482 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8483 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8484 else
8485 dpll |= PLL_REF_INPUT_DREFCLK;
8486
8487 return dpll | DPLL_VCO_ENABLE;
8488 }
8489
8490 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8491 struct intel_crtc_state *crtc_state)
8492 {
8493 struct drm_device *dev = crtc->base.dev;
8494 intel_clock_t clock, reduced_clock;
8495 u32 dpll = 0, fp = 0, fp2 = 0;
8496 bool ok, has_reduced_clock = false;
8497 bool is_lvds = false;
8498 struct intel_shared_dpll *pll;
8499
8500 memset(&crtc_state->dpll_hw_state, 0,
8501 sizeof(crtc_state->dpll_hw_state));
8502
8503 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8504
8505 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8506 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8507
8508 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8509 &has_reduced_clock, &reduced_clock);
8510 if (!ok && !crtc_state->clock_set) {
8511 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8512 return -EINVAL;
8513 }
8514 /* Compat-code for transition, will disappear. */
8515 if (!crtc_state->clock_set) {
8516 crtc_state->dpll.n = clock.n;
8517 crtc_state->dpll.m1 = clock.m1;
8518 crtc_state->dpll.m2 = clock.m2;
8519 crtc_state->dpll.p1 = clock.p1;
8520 crtc_state->dpll.p2 = clock.p2;
8521 }
8522
8523 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8524 if (crtc_state->has_pch_encoder) {
8525 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8526 if (has_reduced_clock)
8527 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8528
8529 dpll = ironlake_compute_dpll(crtc, crtc_state,
8530 &fp, &reduced_clock,
8531 has_reduced_clock ? &fp2 : NULL);
8532
8533 crtc_state->dpll_hw_state.dpll = dpll;
8534 crtc_state->dpll_hw_state.fp0 = fp;
8535 if (has_reduced_clock)
8536 crtc_state->dpll_hw_state.fp1 = fp2;
8537 else
8538 crtc_state->dpll_hw_state.fp1 = fp;
8539
8540 pll = intel_get_shared_dpll(crtc, crtc_state);
8541 if (pll == NULL) {
8542 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8543 pipe_name(crtc->pipe));
8544 return -EINVAL;
8545 }
8546 }
8547
8548 if (is_lvds && has_reduced_clock)
8549 crtc->lowfreq_avail = true;
8550 else
8551 crtc->lowfreq_avail = false;
8552
8553 return 0;
8554 }
8555
8556 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8557 struct intel_link_m_n *m_n)
8558 {
8559 struct drm_device *dev = crtc->base.dev;
8560 struct drm_i915_private *dev_priv = dev->dev_private;
8561 enum pipe pipe = crtc->pipe;
8562
8563 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8564 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8565 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8566 & ~TU_SIZE_MASK;
8567 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8568 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8569 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8570 }
8571
8572 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8573 enum transcoder transcoder,
8574 struct intel_link_m_n *m_n,
8575 struct intel_link_m_n *m2_n2)
8576 {
8577 struct drm_device *dev = crtc->base.dev;
8578 struct drm_i915_private *dev_priv = dev->dev_private;
8579 enum pipe pipe = crtc->pipe;
8580
8581 if (INTEL_INFO(dev)->gen >= 5) {
8582 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8583 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8584 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8585 & ~TU_SIZE_MASK;
8586 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8587 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8588 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8589 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8590 * gen < 8) and if DRRS is supported (to make sure the
8591 * registers are not unnecessarily read).
8592 */
8593 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8594 crtc->config->has_drrs) {
8595 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8596 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8597 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8598 & ~TU_SIZE_MASK;
8599 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8600 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8601 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8602 }
8603 } else {
8604 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8605 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8606 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8607 & ~TU_SIZE_MASK;
8608 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8609 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8610 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8611 }
8612 }
8613
8614 void intel_dp_get_m_n(struct intel_crtc *crtc,
8615 struct intel_crtc_state *pipe_config)
8616 {
8617 if (pipe_config->has_pch_encoder)
8618 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8619 else
8620 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8621 &pipe_config->dp_m_n,
8622 &pipe_config->dp_m2_n2);
8623 }
8624
8625 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8626 struct intel_crtc_state *pipe_config)
8627 {
8628 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8629 &pipe_config->fdi_m_n, NULL);
8630 }
8631
8632 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8633 struct intel_crtc_state *pipe_config)
8634 {
8635 struct drm_device *dev = crtc->base.dev;
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8638 uint32_t ps_ctrl = 0;
8639 int id = -1;
8640 int i;
8641
8642 /* find scaler attached to this pipe */
8643 for (i = 0; i < crtc->num_scalers; i++) {
8644 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8645 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8646 id = i;
8647 pipe_config->pch_pfit.enabled = true;
8648 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8649 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8650 break;
8651 }
8652 }
8653
8654 scaler_state->scaler_id = id;
8655 if (id >= 0) {
8656 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8657 } else {
8658 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8659 }
8660 }
8661
8662 static void
8663 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8664 struct intel_initial_plane_config *plane_config)
8665 {
8666 struct drm_device *dev = crtc->base.dev;
8667 struct drm_i915_private *dev_priv = dev->dev_private;
8668 u32 val, base, offset, stride_mult, tiling;
8669 int pipe = crtc->pipe;
8670 int fourcc, pixel_format;
8671 unsigned int aligned_height;
8672 struct drm_framebuffer *fb;
8673 struct intel_framebuffer *intel_fb;
8674
8675 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8676 if (!intel_fb) {
8677 DRM_DEBUG_KMS("failed to alloc fb\n");
8678 return;
8679 }
8680
8681 fb = &intel_fb->base;
8682
8683 val = I915_READ(PLANE_CTL(pipe, 0));
8684 if (!(val & PLANE_CTL_ENABLE))
8685 goto error;
8686
8687 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8688 fourcc = skl_format_to_fourcc(pixel_format,
8689 val & PLANE_CTL_ORDER_RGBX,
8690 val & PLANE_CTL_ALPHA_MASK);
8691 fb->pixel_format = fourcc;
8692 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8693
8694 tiling = val & PLANE_CTL_TILED_MASK;
8695 switch (tiling) {
8696 case PLANE_CTL_TILED_LINEAR:
8697 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8698 break;
8699 case PLANE_CTL_TILED_X:
8700 plane_config->tiling = I915_TILING_X;
8701 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8702 break;
8703 case PLANE_CTL_TILED_Y:
8704 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8705 break;
8706 case PLANE_CTL_TILED_YF:
8707 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8708 break;
8709 default:
8710 MISSING_CASE(tiling);
8711 goto error;
8712 }
8713
8714 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8715 plane_config->base = base;
8716
8717 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8718
8719 val = I915_READ(PLANE_SIZE(pipe, 0));
8720 fb->height = ((val >> 16) & 0xfff) + 1;
8721 fb->width = ((val >> 0) & 0x1fff) + 1;
8722
8723 val = I915_READ(PLANE_STRIDE(pipe, 0));
8724 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8725 fb->pixel_format);
8726 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8727
8728 aligned_height = intel_fb_align_height(dev, fb->height,
8729 fb->pixel_format,
8730 fb->modifier[0]);
8731
8732 plane_config->size = fb->pitches[0] * aligned_height;
8733
8734 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8735 pipe_name(pipe), fb->width, fb->height,
8736 fb->bits_per_pixel, base, fb->pitches[0],
8737 plane_config->size);
8738
8739 plane_config->fb = intel_fb;
8740 return;
8741
8742 error:
8743 kfree(fb);
8744 }
8745
8746 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8747 struct intel_crtc_state *pipe_config)
8748 {
8749 struct drm_device *dev = crtc->base.dev;
8750 struct drm_i915_private *dev_priv = dev->dev_private;
8751 uint32_t tmp;
8752
8753 tmp = I915_READ(PF_CTL(crtc->pipe));
8754
8755 if (tmp & PF_ENABLE) {
8756 pipe_config->pch_pfit.enabled = true;
8757 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8758 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8759
8760 /* We currently do not free assignements of panel fitters on
8761 * ivb/hsw (since we don't use the higher upscaling modes which
8762 * differentiates them) so just WARN about this case for now. */
8763 if (IS_GEN7(dev)) {
8764 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8765 PF_PIPE_SEL_IVB(crtc->pipe));
8766 }
8767 }
8768 }
8769
8770 static void
8771 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8772 struct intel_initial_plane_config *plane_config)
8773 {
8774 struct drm_device *dev = crtc->base.dev;
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776 u32 val, base, offset;
8777 int pipe = crtc->pipe;
8778 int fourcc, pixel_format;
8779 unsigned int aligned_height;
8780 struct drm_framebuffer *fb;
8781 struct intel_framebuffer *intel_fb;
8782
8783 val = I915_READ(DSPCNTR(pipe));
8784 if (!(val & DISPLAY_PLANE_ENABLE))
8785 return;
8786
8787 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8788 if (!intel_fb) {
8789 DRM_DEBUG_KMS("failed to alloc fb\n");
8790 return;
8791 }
8792
8793 fb = &intel_fb->base;
8794
8795 if (INTEL_INFO(dev)->gen >= 4) {
8796 if (val & DISPPLANE_TILED) {
8797 plane_config->tiling = I915_TILING_X;
8798 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8799 }
8800 }
8801
8802 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8803 fourcc = i9xx_format_to_fourcc(pixel_format);
8804 fb->pixel_format = fourcc;
8805 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8806
8807 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8808 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8809 offset = I915_READ(DSPOFFSET(pipe));
8810 } else {
8811 if (plane_config->tiling)
8812 offset = I915_READ(DSPTILEOFF(pipe));
8813 else
8814 offset = I915_READ(DSPLINOFF(pipe));
8815 }
8816 plane_config->base = base;
8817
8818 val = I915_READ(PIPESRC(pipe));
8819 fb->width = ((val >> 16) & 0xfff) + 1;
8820 fb->height = ((val >> 0) & 0xfff) + 1;
8821
8822 val = I915_READ(DSPSTRIDE(pipe));
8823 fb->pitches[0] = val & 0xffffffc0;
8824
8825 aligned_height = intel_fb_align_height(dev, fb->height,
8826 fb->pixel_format,
8827 fb->modifier[0]);
8828
8829 plane_config->size = fb->pitches[0] * aligned_height;
8830
8831 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8832 pipe_name(pipe), fb->width, fb->height,
8833 fb->bits_per_pixel, base, fb->pitches[0],
8834 plane_config->size);
8835
8836 plane_config->fb = intel_fb;
8837 }
8838
8839 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8840 struct intel_crtc_state *pipe_config)
8841 {
8842 struct drm_device *dev = crtc->base.dev;
8843 struct drm_i915_private *dev_priv = dev->dev_private;
8844 uint32_t tmp;
8845
8846 if (!intel_display_power_is_enabled(dev_priv,
8847 POWER_DOMAIN_PIPE(crtc->pipe)))
8848 return false;
8849
8850 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8851 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8852
8853 tmp = I915_READ(PIPECONF(crtc->pipe));
8854 if (!(tmp & PIPECONF_ENABLE))
8855 return false;
8856
8857 switch (tmp & PIPECONF_BPC_MASK) {
8858 case PIPECONF_6BPC:
8859 pipe_config->pipe_bpp = 18;
8860 break;
8861 case PIPECONF_8BPC:
8862 pipe_config->pipe_bpp = 24;
8863 break;
8864 case PIPECONF_10BPC:
8865 pipe_config->pipe_bpp = 30;
8866 break;
8867 case PIPECONF_12BPC:
8868 pipe_config->pipe_bpp = 36;
8869 break;
8870 default:
8871 break;
8872 }
8873
8874 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8875 pipe_config->limited_color_range = true;
8876
8877 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8878 struct intel_shared_dpll *pll;
8879
8880 pipe_config->has_pch_encoder = true;
8881
8882 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8883 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8884 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8885
8886 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8887
8888 if (HAS_PCH_IBX(dev_priv->dev)) {
8889 pipe_config->shared_dpll =
8890 (enum intel_dpll_id) crtc->pipe;
8891 } else {
8892 tmp = I915_READ(PCH_DPLL_SEL);
8893 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8894 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8895 else
8896 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8897 }
8898
8899 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8900
8901 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8902 &pipe_config->dpll_hw_state));
8903
8904 tmp = pipe_config->dpll_hw_state.dpll;
8905 pipe_config->pixel_multiplier =
8906 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8907 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8908
8909 ironlake_pch_clock_get(crtc, pipe_config);
8910 } else {
8911 pipe_config->pixel_multiplier = 1;
8912 }
8913
8914 intel_get_pipe_timings(crtc, pipe_config);
8915
8916 ironlake_get_pfit_config(crtc, pipe_config);
8917
8918 return true;
8919 }
8920
8921 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8922 {
8923 struct drm_device *dev = dev_priv->dev;
8924 struct intel_crtc *crtc;
8925
8926 for_each_intel_crtc(dev, crtc)
8927 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8928 pipe_name(crtc->pipe));
8929
8930 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8931 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8932 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8933 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8934 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8935 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8936 "CPU PWM1 enabled\n");
8937 if (IS_HASWELL(dev))
8938 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8939 "CPU PWM2 enabled\n");
8940 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8941 "PCH PWM1 enabled\n");
8942 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8943 "Utility pin enabled\n");
8944 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8945
8946 /*
8947 * In theory we can still leave IRQs enabled, as long as only the HPD
8948 * interrupts remain enabled. We used to check for that, but since it's
8949 * gen-specific and since we only disable LCPLL after we fully disable
8950 * the interrupts, the check below should be enough.
8951 */
8952 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8953 }
8954
8955 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8956 {
8957 struct drm_device *dev = dev_priv->dev;
8958
8959 if (IS_HASWELL(dev))
8960 return I915_READ(D_COMP_HSW);
8961 else
8962 return I915_READ(D_COMP_BDW);
8963 }
8964
8965 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8966 {
8967 struct drm_device *dev = dev_priv->dev;
8968
8969 if (IS_HASWELL(dev)) {
8970 mutex_lock(&dev_priv->rps.hw_lock);
8971 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8972 val))
8973 DRM_ERROR("Failed to write to D_COMP\n");
8974 mutex_unlock(&dev_priv->rps.hw_lock);
8975 } else {
8976 I915_WRITE(D_COMP_BDW, val);
8977 POSTING_READ(D_COMP_BDW);
8978 }
8979 }
8980
8981 /*
8982 * This function implements pieces of two sequences from BSpec:
8983 * - Sequence for display software to disable LCPLL
8984 * - Sequence for display software to allow package C8+
8985 * The steps implemented here are just the steps that actually touch the LCPLL
8986 * register. Callers should take care of disabling all the display engine
8987 * functions, doing the mode unset, fixing interrupts, etc.
8988 */
8989 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8990 bool switch_to_fclk, bool allow_power_down)
8991 {
8992 uint32_t val;
8993
8994 assert_can_disable_lcpll(dev_priv);
8995
8996 val = I915_READ(LCPLL_CTL);
8997
8998 if (switch_to_fclk) {
8999 val |= LCPLL_CD_SOURCE_FCLK;
9000 I915_WRITE(LCPLL_CTL, val);
9001
9002 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9003 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9004 DRM_ERROR("Switching to FCLK failed\n");
9005
9006 val = I915_READ(LCPLL_CTL);
9007 }
9008
9009 val |= LCPLL_PLL_DISABLE;
9010 I915_WRITE(LCPLL_CTL, val);
9011 POSTING_READ(LCPLL_CTL);
9012
9013 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9014 DRM_ERROR("LCPLL still locked\n");
9015
9016 val = hsw_read_dcomp(dev_priv);
9017 val |= D_COMP_COMP_DISABLE;
9018 hsw_write_dcomp(dev_priv, val);
9019 ndelay(100);
9020
9021 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9022 1))
9023 DRM_ERROR("D_COMP RCOMP still in progress\n");
9024
9025 if (allow_power_down) {
9026 val = I915_READ(LCPLL_CTL);
9027 val |= LCPLL_POWER_DOWN_ALLOW;
9028 I915_WRITE(LCPLL_CTL, val);
9029 POSTING_READ(LCPLL_CTL);
9030 }
9031 }
9032
9033 /*
9034 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9035 * source.
9036 */
9037 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9038 {
9039 uint32_t val;
9040
9041 val = I915_READ(LCPLL_CTL);
9042
9043 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9044 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9045 return;
9046
9047 /*
9048 * Make sure we're not on PC8 state before disabling PC8, otherwise
9049 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9050 */
9051 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9052
9053 if (val & LCPLL_POWER_DOWN_ALLOW) {
9054 val &= ~LCPLL_POWER_DOWN_ALLOW;
9055 I915_WRITE(LCPLL_CTL, val);
9056 POSTING_READ(LCPLL_CTL);
9057 }
9058
9059 val = hsw_read_dcomp(dev_priv);
9060 val |= D_COMP_COMP_FORCE;
9061 val &= ~D_COMP_COMP_DISABLE;
9062 hsw_write_dcomp(dev_priv, val);
9063
9064 val = I915_READ(LCPLL_CTL);
9065 val &= ~LCPLL_PLL_DISABLE;
9066 I915_WRITE(LCPLL_CTL, val);
9067
9068 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9069 DRM_ERROR("LCPLL not locked yet\n");
9070
9071 if (val & LCPLL_CD_SOURCE_FCLK) {
9072 val = I915_READ(LCPLL_CTL);
9073 val &= ~LCPLL_CD_SOURCE_FCLK;
9074 I915_WRITE(LCPLL_CTL, val);
9075
9076 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9077 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9078 DRM_ERROR("Switching back to LCPLL failed\n");
9079 }
9080
9081 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9082 }
9083
9084 /*
9085 * Package states C8 and deeper are really deep PC states that can only be
9086 * reached when all the devices on the system allow it, so even if the graphics
9087 * device allows PC8+, it doesn't mean the system will actually get to these
9088 * states. Our driver only allows PC8+ when going into runtime PM.
9089 *
9090 * The requirements for PC8+ are that all the outputs are disabled, the power
9091 * well is disabled and most interrupts are disabled, and these are also
9092 * requirements for runtime PM. When these conditions are met, we manually do
9093 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9094 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9095 * hang the machine.
9096 *
9097 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9098 * the state of some registers, so when we come back from PC8+ we need to
9099 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9100 * need to take care of the registers kept by RC6. Notice that this happens even
9101 * if we don't put the device in PCI D3 state (which is what currently happens
9102 * because of the runtime PM support).
9103 *
9104 * For more, read "Display Sequences for Package C8" on the hardware
9105 * documentation.
9106 */
9107 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9108 {
9109 struct drm_device *dev = dev_priv->dev;
9110 uint32_t val;
9111
9112 DRM_DEBUG_KMS("Enabling package C8+\n");
9113
9114 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9115 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9116 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9117 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9118 }
9119
9120 lpt_disable_clkout_dp(dev);
9121 hsw_disable_lcpll(dev_priv, true, true);
9122 }
9123
9124 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9125 {
9126 struct drm_device *dev = dev_priv->dev;
9127 uint32_t val;
9128
9129 DRM_DEBUG_KMS("Disabling package C8+\n");
9130
9131 hsw_restore_lcpll(dev_priv);
9132 lpt_init_pch_refclk(dev);
9133
9134 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9135 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9136 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9137 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9138 }
9139
9140 intel_prepare_ddi(dev);
9141 }
9142
9143 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9144 {
9145 struct drm_device *dev = old_state->dev;
9146 struct drm_i915_private *dev_priv = dev->dev_private;
9147 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9148 int req_cdclk;
9149
9150 /* see the comment in valleyview_modeset_global_resources */
9151 if (WARN_ON(max_pixclk < 0))
9152 return;
9153
9154 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9155
9156 if (req_cdclk != dev_priv->cdclk_freq)
9157 broxton_set_cdclk(dev, req_cdclk);
9158 }
9159
9160 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9161 struct intel_crtc_state *crtc_state)
9162 {
9163 if (!intel_ddi_pll_select(crtc, crtc_state))
9164 return -EINVAL;
9165
9166 crtc->lowfreq_avail = false;
9167
9168 return 0;
9169 }
9170
9171 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9172 enum port port,
9173 struct intel_crtc_state *pipe_config)
9174 {
9175 switch (port) {
9176 case PORT_A:
9177 pipe_config->ddi_pll_sel = SKL_DPLL0;
9178 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9179 break;
9180 case PORT_B:
9181 pipe_config->ddi_pll_sel = SKL_DPLL1;
9182 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9183 break;
9184 case PORT_C:
9185 pipe_config->ddi_pll_sel = SKL_DPLL2;
9186 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9187 break;
9188 default:
9189 DRM_ERROR("Incorrect port type\n");
9190 }
9191 }
9192
9193 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9194 enum port port,
9195 struct intel_crtc_state *pipe_config)
9196 {
9197 u32 temp, dpll_ctl1;
9198
9199 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9200 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9201
9202 switch (pipe_config->ddi_pll_sel) {
9203 case SKL_DPLL0:
9204 /*
9205 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9206 * of the shared DPLL framework and thus needs to be read out
9207 * separately
9208 */
9209 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9210 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9211 break;
9212 case SKL_DPLL1:
9213 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9214 break;
9215 case SKL_DPLL2:
9216 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9217 break;
9218 case SKL_DPLL3:
9219 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9220 break;
9221 }
9222 }
9223
9224 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9225 enum port port,
9226 struct intel_crtc_state *pipe_config)
9227 {
9228 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9229
9230 switch (pipe_config->ddi_pll_sel) {
9231 case PORT_CLK_SEL_WRPLL1:
9232 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9233 break;
9234 case PORT_CLK_SEL_WRPLL2:
9235 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9236 break;
9237 }
9238 }
9239
9240 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9241 struct intel_crtc_state *pipe_config)
9242 {
9243 struct drm_device *dev = crtc->base.dev;
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245 struct intel_shared_dpll *pll;
9246 enum port port;
9247 uint32_t tmp;
9248
9249 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9250
9251 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9252
9253 if (IS_SKYLAKE(dev))
9254 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9255 else if (IS_BROXTON(dev))
9256 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9257 else
9258 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9259
9260 if (pipe_config->shared_dpll >= 0) {
9261 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9262
9263 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9264 &pipe_config->dpll_hw_state));
9265 }
9266
9267 /*
9268 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9269 * DDI E. So just check whether this pipe is wired to DDI E and whether
9270 * the PCH transcoder is on.
9271 */
9272 if (INTEL_INFO(dev)->gen < 9 &&
9273 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9274 pipe_config->has_pch_encoder = true;
9275
9276 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9277 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9278 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9279
9280 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9281 }
9282 }
9283
9284 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9285 struct intel_crtc_state *pipe_config)
9286 {
9287 struct drm_device *dev = crtc->base.dev;
9288 struct drm_i915_private *dev_priv = dev->dev_private;
9289 enum intel_display_power_domain pfit_domain;
9290 uint32_t tmp;
9291
9292 if (!intel_display_power_is_enabled(dev_priv,
9293 POWER_DOMAIN_PIPE(crtc->pipe)))
9294 return false;
9295
9296 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9297 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9298
9299 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9300 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9301 enum pipe trans_edp_pipe;
9302 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9303 default:
9304 WARN(1, "unknown pipe linked to edp transcoder\n");
9305 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9306 case TRANS_DDI_EDP_INPUT_A_ON:
9307 trans_edp_pipe = PIPE_A;
9308 break;
9309 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9310 trans_edp_pipe = PIPE_B;
9311 break;
9312 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9313 trans_edp_pipe = PIPE_C;
9314 break;
9315 }
9316
9317 if (trans_edp_pipe == crtc->pipe)
9318 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9319 }
9320
9321 if (!intel_display_power_is_enabled(dev_priv,
9322 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9323 return false;
9324
9325 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9326 if (!(tmp & PIPECONF_ENABLE))
9327 return false;
9328
9329 haswell_get_ddi_port_state(crtc, pipe_config);
9330
9331 intel_get_pipe_timings(crtc, pipe_config);
9332
9333 if (INTEL_INFO(dev)->gen >= 9) {
9334 skl_init_scalers(dev, crtc, pipe_config);
9335 }
9336
9337 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9338
9339 if (INTEL_INFO(dev)->gen >= 9) {
9340 pipe_config->scaler_state.scaler_id = -1;
9341 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9342 }
9343
9344 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9345 if (INTEL_INFO(dev)->gen == 9)
9346 skylake_get_pfit_config(crtc, pipe_config);
9347 else if (INTEL_INFO(dev)->gen < 9)
9348 ironlake_get_pfit_config(crtc, pipe_config);
9349 else
9350 MISSING_CASE(INTEL_INFO(dev)->gen);
9351 }
9352
9353 if (IS_HASWELL(dev))
9354 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9355 (I915_READ(IPS_CTL) & IPS_ENABLE);
9356
9357 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9358 pipe_config->pixel_multiplier =
9359 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9360 } else {
9361 pipe_config->pixel_multiplier = 1;
9362 }
9363
9364 return true;
9365 }
9366
9367 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9368 {
9369 struct drm_device *dev = crtc->dev;
9370 struct drm_i915_private *dev_priv = dev->dev_private;
9371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9372 uint32_t cntl = 0, size = 0;
9373
9374 if (base) {
9375 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9376 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9377 unsigned int stride = roundup_pow_of_two(width) * 4;
9378
9379 switch (stride) {
9380 default:
9381 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9382 width, stride);
9383 stride = 256;
9384 /* fallthrough */
9385 case 256:
9386 case 512:
9387 case 1024:
9388 case 2048:
9389 break;
9390 }
9391
9392 cntl |= CURSOR_ENABLE |
9393 CURSOR_GAMMA_ENABLE |
9394 CURSOR_FORMAT_ARGB |
9395 CURSOR_STRIDE(stride);
9396
9397 size = (height << 12) | width;
9398 }
9399
9400 if (intel_crtc->cursor_cntl != 0 &&
9401 (intel_crtc->cursor_base != base ||
9402 intel_crtc->cursor_size != size ||
9403 intel_crtc->cursor_cntl != cntl)) {
9404 /* On these chipsets we can only modify the base/size/stride
9405 * whilst the cursor is disabled.
9406 */
9407 I915_WRITE(_CURACNTR, 0);
9408 POSTING_READ(_CURACNTR);
9409 intel_crtc->cursor_cntl = 0;
9410 }
9411
9412 if (intel_crtc->cursor_base != base) {
9413 I915_WRITE(_CURABASE, base);
9414 intel_crtc->cursor_base = base;
9415 }
9416
9417 if (intel_crtc->cursor_size != size) {
9418 I915_WRITE(CURSIZE, size);
9419 intel_crtc->cursor_size = size;
9420 }
9421
9422 if (intel_crtc->cursor_cntl != cntl) {
9423 I915_WRITE(_CURACNTR, cntl);
9424 POSTING_READ(_CURACNTR);
9425 intel_crtc->cursor_cntl = cntl;
9426 }
9427 }
9428
9429 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9430 {
9431 struct drm_device *dev = crtc->dev;
9432 struct drm_i915_private *dev_priv = dev->dev_private;
9433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9434 int pipe = intel_crtc->pipe;
9435 uint32_t cntl;
9436
9437 cntl = 0;
9438 if (base) {
9439 cntl = MCURSOR_GAMMA_ENABLE;
9440 switch (intel_crtc->base.cursor->state->crtc_w) {
9441 case 64:
9442 cntl |= CURSOR_MODE_64_ARGB_AX;
9443 break;
9444 case 128:
9445 cntl |= CURSOR_MODE_128_ARGB_AX;
9446 break;
9447 case 256:
9448 cntl |= CURSOR_MODE_256_ARGB_AX;
9449 break;
9450 default:
9451 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9452 return;
9453 }
9454 cntl |= pipe << 28; /* Connect to correct pipe */
9455
9456 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9457 cntl |= CURSOR_PIPE_CSC_ENABLE;
9458 }
9459
9460 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9461 cntl |= CURSOR_ROTATE_180;
9462
9463 if (intel_crtc->cursor_cntl != cntl) {
9464 I915_WRITE(CURCNTR(pipe), cntl);
9465 POSTING_READ(CURCNTR(pipe));
9466 intel_crtc->cursor_cntl = cntl;
9467 }
9468
9469 /* and commit changes on next vblank */
9470 I915_WRITE(CURBASE(pipe), base);
9471 POSTING_READ(CURBASE(pipe));
9472
9473 intel_crtc->cursor_base = base;
9474 }
9475
9476 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9477 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9478 bool on)
9479 {
9480 struct drm_device *dev = crtc->dev;
9481 struct drm_i915_private *dev_priv = dev->dev_private;
9482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9483 int pipe = intel_crtc->pipe;
9484 int x = crtc->cursor_x;
9485 int y = crtc->cursor_y;
9486 u32 base = 0, pos = 0;
9487
9488 if (on)
9489 base = intel_crtc->cursor_addr;
9490
9491 if (x >= intel_crtc->config->pipe_src_w)
9492 base = 0;
9493
9494 if (y >= intel_crtc->config->pipe_src_h)
9495 base = 0;
9496
9497 if (x < 0) {
9498 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9499 base = 0;
9500
9501 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9502 x = -x;
9503 }
9504 pos |= x << CURSOR_X_SHIFT;
9505
9506 if (y < 0) {
9507 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9508 base = 0;
9509
9510 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9511 y = -y;
9512 }
9513 pos |= y << CURSOR_Y_SHIFT;
9514
9515 if (base == 0 && intel_crtc->cursor_base == 0)
9516 return;
9517
9518 I915_WRITE(CURPOS(pipe), pos);
9519
9520 /* ILK+ do this automagically */
9521 if (HAS_GMCH_DISPLAY(dev) &&
9522 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9523 base += (intel_crtc->base.cursor->state->crtc_h *
9524 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9525 }
9526
9527 if (IS_845G(dev) || IS_I865G(dev))
9528 i845_update_cursor(crtc, base);
9529 else
9530 i9xx_update_cursor(crtc, base);
9531 }
9532
9533 static bool cursor_size_ok(struct drm_device *dev,
9534 uint32_t width, uint32_t height)
9535 {
9536 if (width == 0 || height == 0)
9537 return false;
9538
9539 /*
9540 * 845g/865g are special in that they are only limited by
9541 * the width of their cursors, the height is arbitrary up to
9542 * the precision of the register. Everything else requires
9543 * square cursors, limited to a few power-of-two sizes.
9544 */
9545 if (IS_845G(dev) || IS_I865G(dev)) {
9546 if ((width & 63) != 0)
9547 return false;
9548
9549 if (width > (IS_845G(dev) ? 64 : 512))
9550 return false;
9551
9552 if (height > 1023)
9553 return false;
9554 } else {
9555 switch (width | height) {
9556 case 256:
9557 case 128:
9558 if (IS_GEN2(dev))
9559 return false;
9560 case 64:
9561 break;
9562 default:
9563 return false;
9564 }
9565 }
9566
9567 return true;
9568 }
9569
9570 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9571 u16 *blue, uint32_t start, uint32_t size)
9572 {
9573 int end = (start + size > 256) ? 256 : start + size, i;
9574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9575
9576 for (i = start; i < end; i++) {
9577 intel_crtc->lut_r[i] = red[i] >> 8;
9578 intel_crtc->lut_g[i] = green[i] >> 8;
9579 intel_crtc->lut_b[i] = blue[i] >> 8;
9580 }
9581
9582 intel_crtc_load_lut(crtc);
9583 }
9584
9585 /* VESA 640x480x72Hz mode to set on the pipe */
9586 static struct drm_display_mode load_detect_mode = {
9587 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9588 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9589 };
9590
9591 struct drm_framebuffer *
9592 __intel_framebuffer_create(struct drm_device *dev,
9593 struct drm_mode_fb_cmd2 *mode_cmd,
9594 struct drm_i915_gem_object *obj)
9595 {
9596 struct intel_framebuffer *intel_fb;
9597 int ret;
9598
9599 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9600 if (!intel_fb) {
9601 drm_gem_object_unreference(&obj->base);
9602 return ERR_PTR(-ENOMEM);
9603 }
9604
9605 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9606 if (ret)
9607 goto err;
9608
9609 return &intel_fb->base;
9610 err:
9611 drm_gem_object_unreference(&obj->base);
9612 kfree(intel_fb);
9613
9614 return ERR_PTR(ret);
9615 }
9616
9617 static struct drm_framebuffer *
9618 intel_framebuffer_create(struct drm_device *dev,
9619 struct drm_mode_fb_cmd2 *mode_cmd,
9620 struct drm_i915_gem_object *obj)
9621 {
9622 struct drm_framebuffer *fb;
9623 int ret;
9624
9625 ret = i915_mutex_lock_interruptible(dev);
9626 if (ret)
9627 return ERR_PTR(ret);
9628 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9629 mutex_unlock(&dev->struct_mutex);
9630
9631 return fb;
9632 }
9633
9634 static u32
9635 intel_framebuffer_pitch_for_width(int width, int bpp)
9636 {
9637 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9638 return ALIGN(pitch, 64);
9639 }
9640
9641 static u32
9642 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9643 {
9644 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9645 return PAGE_ALIGN(pitch * mode->vdisplay);
9646 }
9647
9648 static struct drm_framebuffer *
9649 intel_framebuffer_create_for_mode(struct drm_device *dev,
9650 struct drm_display_mode *mode,
9651 int depth, int bpp)
9652 {
9653 struct drm_i915_gem_object *obj;
9654 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9655
9656 obj = i915_gem_alloc_object(dev,
9657 intel_framebuffer_size_for_mode(mode, bpp));
9658 if (obj == NULL)
9659 return ERR_PTR(-ENOMEM);
9660
9661 mode_cmd.width = mode->hdisplay;
9662 mode_cmd.height = mode->vdisplay;
9663 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9664 bpp);
9665 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9666
9667 return intel_framebuffer_create(dev, &mode_cmd, obj);
9668 }
9669
9670 static struct drm_framebuffer *
9671 mode_fits_in_fbdev(struct drm_device *dev,
9672 struct drm_display_mode *mode)
9673 {
9674 #ifdef CONFIG_DRM_I915_FBDEV
9675 struct drm_i915_private *dev_priv = dev->dev_private;
9676 struct drm_i915_gem_object *obj;
9677 struct drm_framebuffer *fb;
9678
9679 if (!dev_priv->fbdev)
9680 return NULL;
9681
9682 if (!dev_priv->fbdev->fb)
9683 return NULL;
9684
9685 obj = dev_priv->fbdev->fb->obj;
9686 BUG_ON(!obj);
9687
9688 fb = &dev_priv->fbdev->fb->base;
9689 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9690 fb->bits_per_pixel))
9691 return NULL;
9692
9693 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9694 return NULL;
9695
9696 return fb;
9697 #else
9698 return NULL;
9699 #endif
9700 }
9701
9702 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9703 struct drm_crtc *crtc,
9704 struct drm_display_mode *mode,
9705 struct drm_framebuffer *fb,
9706 int x, int y)
9707 {
9708 struct drm_plane_state *plane_state;
9709 int hdisplay, vdisplay;
9710 int ret;
9711
9712 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9713 if (IS_ERR(plane_state))
9714 return PTR_ERR(plane_state);
9715
9716 if (mode)
9717 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9718 else
9719 hdisplay = vdisplay = 0;
9720
9721 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9722 if (ret)
9723 return ret;
9724 drm_atomic_set_fb_for_plane(plane_state, fb);
9725 plane_state->crtc_x = 0;
9726 plane_state->crtc_y = 0;
9727 plane_state->crtc_w = hdisplay;
9728 plane_state->crtc_h = vdisplay;
9729 plane_state->src_x = x << 16;
9730 plane_state->src_y = y << 16;
9731 plane_state->src_w = hdisplay << 16;
9732 plane_state->src_h = vdisplay << 16;
9733
9734 return 0;
9735 }
9736
9737 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9738 struct drm_display_mode *mode,
9739 struct intel_load_detect_pipe *old,
9740 struct drm_modeset_acquire_ctx *ctx)
9741 {
9742 struct intel_crtc *intel_crtc;
9743 struct intel_encoder *intel_encoder =
9744 intel_attached_encoder(connector);
9745 struct drm_crtc *possible_crtc;
9746 struct drm_encoder *encoder = &intel_encoder->base;
9747 struct drm_crtc *crtc = NULL;
9748 struct drm_device *dev = encoder->dev;
9749 struct drm_framebuffer *fb;
9750 struct drm_mode_config *config = &dev->mode_config;
9751 struct drm_atomic_state *state = NULL;
9752 struct drm_connector_state *connector_state;
9753 struct intel_crtc_state *crtc_state;
9754 int ret, i = -1;
9755
9756 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9757 connector->base.id, connector->name,
9758 encoder->base.id, encoder->name);
9759
9760 retry:
9761 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9762 if (ret)
9763 goto fail_unlock;
9764
9765 /*
9766 * Algorithm gets a little messy:
9767 *
9768 * - if the connector already has an assigned crtc, use it (but make
9769 * sure it's on first)
9770 *
9771 * - try to find the first unused crtc that can drive this connector,
9772 * and use that if we find one
9773 */
9774
9775 /* See if we already have a CRTC for this connector */
9776 if (encoder->crtc) {
9777 crtc = encoder->crtc;
9778
9779 ret = drm_modeset_lock(&crtc->mutex, ctx);
9780 if (ret)
9781 goto fail_unlock;
9782 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9783 if (ret)
9784 goto fail_unlock;
9785
9786 old->dpms_mode = connector->dpms;
9787 old->load_detect_temp = false;
9788
9789 /* Make sure the crtc and connector are running */
9790 if (connector->dpms != DRM_MODE_DPMS_ON)
9791 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9792
9793 return true;
9794 }
9795
9796 /* Find an unused one (if possible) */
9797 for_each_crtc(dev, possible_crtc) {
9798 i++;
9799 if (!(encoder->possible_crtcs & (1 << i)))
9800 continue;
9801 if (possible_crtc->state->enable)
9802 continue;
9803 /* This can occur when applying the pipe A quirk on resume. */
9804 if (to_intel_crtc(possible_crtc)->new_enabled)
9805 continue;
9806
9807 crtc = possible_crtc;
9808 break;
9809 }
9810
9811 /*
9812 * If we didn't find an unused CRTC, don't use any.
9813 */
9814 if (!crtc) {
9815 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9816 goto fail_unlock;
9817 }
9818
9819 ret = drm_modeset_lock(&crtc->mutex, ctx);
9820 if (ret)
9821 goto fail_unlock;
9822 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9823 if (ret)
9824 goto fail_unlock;
9825 intel_encoder->new_crtc = to_intel_crtc(crtc);
9826 to_intel_connector(connector)->new_encoder = intel_encoder;
9827
9828 intel_crtc = to_intel_crtc(crtc);
9829 intel_crtc->new_enabled = true;
9830 old->dpms_mode = connector->dpms;
9831 old->load_detect_temp = true;
9832 old->release_fb = NULL;
9833
9834 state = drm_atomic_state_alloc(dev);
9835 if (!state)
9836 return false;
9837
9838 state->acquire_ctx = ctx;
9839
9840 connector_state = drm_atomic_get_connector_state(state, connector);
9841 if (IS_ERR(connector_state)) {
9842 ret = PTR_ERR(connector_state);
9843 goto fail;
9844 }
9845
9846 connector_state->crtc = crtc;
9847 connector_state->best_encoder = &intel_encoder->base;
9848
9849 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9850 if (IS_ERR(crtc_state)) {
9851 ret = PTR_ERR(crtc_state);
9852 goto fail;
9853 }
9854
9855 crtc_state->base.active = crtc_state->base.enable = true;
9856
9857 if (!mode)
9858 mode = &load_detect_mode;
9859
9860 /* We need a framebuffer large enough to accommodate all accesses
9861 * that the plane may generate whilst we perform load detection.
9862 * We can not rely on the fbcon either being present (we get called
9863 * during its initialisation to detect all boot displays, or it may
9864 * not even exist) or that it is large enough to satisfy the
9865 * requested mode.
9866 */
9867 fb = mode_fits_in_fbdev(dev, mode);
9868 if (fb == NULL) {
9869 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9870 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9871 old->release_fb = fb;
9872 } else
9873 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9874 if (IS_ERR(fb)) {
9875 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9876 goto fail;
9877 }
9878
9879 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9880 if (ret)
9881 goto fail;
9882
9883 drm_mode_copy(&crtc_state->base.mode, mode);
9884
9885 if (intel_set_mode(crtc, state)) {
9886 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9887 if (old->release_fb)
9888 old->release_fb->funcs->destroy(old->release_fb);
9889 goto fail;
9890 }
9891 crtc->primary->crtc = crtc;
9892
9893 /* let the connector get through one full cycle before testing */
9894 intel_wait_for_vblank(dev, intel_crtc->pipe);
9895 return true;
9896
9897 fail:
9898 intel_crtc->new_enabled = crtc->state->enable;
9899 fail_unlock:
9900 drm_atomic_state_free(state);
9901 state = NULL;
9902
9903 if (ret == -EDEADLK) {
9904 drm_modeset_backoff(ctx);
9905 goto retry;
9906 }
9907
9908 return false;
9909 }
9910
9911 void intel_release_load_detect_pipe(struct drm_connector *connector,
9912 struct intel_load_detect_pipe *old,
9913 struct drm_modeset_acquire_ctx *ctx)
9914 {
9915 struct drm_device *dev = connector->dev;
9916 struct intel_encoder *intel_encoder =
9917 intel_attached_encoder(connector);
9918 struct drm_encoder *encoder = &intel_encoder->base;
9919 struct drm_crtc *crtc = encoder->crtc;
9920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9921 struct drm_atomic_state *state;
9922 struct drm_connector_state *connector_state;
9923 struct intel_crtc_state *crtc_state;
9924 int ret;
9925
9926 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9927 connector->base.id, connector->name,
9928 encoder->base.id, encoder->name);
9929
9930 if (old->load_detect_temp) {
9931 state = drm_atomic_state_alloc(dev);
9932 if (!state)
9933 goto fail;
9934
9935 state->acquire_ctx = ctx;
9936
9937 connector_state = drm_atomic_get_connector_state(state, connector);
9938 if (IS_ERR(connector_state))
9939 goto fail;
9940
9941 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9942 if (IS_ERR(crtc_state))
9943 goto fail;
9944
9945 to_intel_connector(connector)->new_encoder = NULL;
9946 intel_encoder->new_crtc = NULL;
9947 intel_crtc->new_enabled = false;
9948
9949 connector_state->best_encoder = NULL;
9950 connector_state->crtc = NULL;
9951
9952 crtc_state->base.enable = crtc_state->base.active = false;
9953
9954 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9955 0, 0);
9956 if (ret)
9957 goto fail;
9958
9959 ret = intel_set_mode(crtc, state);
9960 if (ret)
9961 goto fail;
9962
9963 if (old->release_fb) {
9964 drm_framebuffer_unregister_private(old->release_fb);
9965 drm_framebuffer_unreference(old->release_fb);
9966 }
9967
9968 return;
9969 }
9970
9971 /* Switch crtc and encoder back off if necessary */
9972 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9973 connector->funcs->dpms(connector, old->dpms_mode);
9974
9975 return;
9976 fail:
9977 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9978 drm_atomic_state_free(state);
9979 }
9980
9981 static int i9xx_pll_refclk(struct drm_device *dev,
9982 const struct intel_crtc_state *pipe_config)
9983 {
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 u32 dpll = pipe_config->dpll_hw_state.dpll;
9986
9987 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9988 return dev_priv->vbt.lvds_ssc_freq;
9989 else if (HAS_PCH_SPLIT(dev))
9990 return 120000;
9991 else if (!IS_GEN2(dev))
9992 return 96000;
9993 else
9994 return 48000;
9995 }
9996
9997 /* Returns the clock of the currently programmed mode of the given pipe. */
9998 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9999 struct intel_crtc_state *pipe_config)
10000 {
10001 struct drm_device *dev = crtc->base.dev;
10002 struct drm_i915_private *dev_priv = dev->dev_private;
10003 int pipe = pipe_config->cpu_transcoder;
10004 u32 dpll = pipe_config->dpll_hw_state.dpll;
10005 u32 fp;
10006 intel_clock_t clock;
10007 int refclk = i9xx_pll_refclk(dev, pipe_config);
10008
10009 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10010 fp = pipe_config->dpll_hw_state.fp0;
10011 else
10012 fp = pipe_config->dpll_hw_state.fp1;
10013
10014 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10015 if (IS_PINEVIEW(dev)) {
10016 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10017 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10018 } else {
10019 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10020 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10021 }
10022
10023 if (!IS_GEN2(dev)) {
10024 if (IS_PINEVIEW(dev))
10025 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10026 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10027 else
10028 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10029 DPLL_FPA01_P1_POST_DIV_SHIFT);
10030
10031 switch (dpll & DPLL_MODE_MASK) {
10032 case DPLLB_MODE_DAC_SERIAL:
10033 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10034 5 : 10;
10035 break;
10036 case DPLLB_MODE_LVDS:
10037 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10038 7 : 14;
10039 break;
10040 default:
10041 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10042 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10043 return;
10044 }
10045
10046 if (IS_PINEVIEW(dev))
10047 pineview_clock(refclk, &clock);
10048 else
10049 i9xx_clock(refclk, &clock);
10050 } else {
10051 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10052 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10053
10054 if (is_lvds) {
10055 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10056 DPLL_FPA01_P1_POST_DIV_SHIFT);
10057
10058 if (lvds & LVDS_CLKB_POWER_UP)
10059 clock.p2 = 7;
10060 else
10061 clock.p2 = 14;
10062 } else {
10063 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10064 clock.p1 = 2;
10065 else {
10066 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10067 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10068 }
10069 if (dpll & PLL_P2_DIVIDE_BY_4)
10070 clock.p2 = 4;
10071 else
10072 clock.p2 = 2;
10073 }
10074
10075 i9xx_clock(refclk, &clock);
10076 }
10077
10078 /*
10079 * This value includes pixel_multiplier. We will use
10080 * port_clock to compute adjusted_mode.crtc_clock in the
10081 * encoder's get_config() function.
10082 */
10083 pipe_config->port_clock = clock.dot;
10084 }
10085
10086 int intel_dotclock_calculate(int link_freq,
10087 const struct intel_link_m_n *m_n)
10088 {
10089 /*
10090 * The calculation for the data clock is:
10091 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10092 * But we want to avoid losing precison if possible, so:
10093 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10094 *
10095 * and the link clock is simpler:
10096 * link_clock = (m * link_clock) / n
10097 */
10098
10099 if (!m_n->link_n)
10100 return 0;
10101
10102 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10103 }
10104
10105 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10106 struct intel_crtc_state *pipe_config)
10107 {
10108 struct drm_device *dev = crtc->base.dev;
10109
10110 /* read out port_clock from the DPLL */
10111 i9xx_crtc_clock_get(crtc, pipe_config);
10112
10113 /*
10114 * This value does not include pixel_multiplier.
10115 * We will check that port_clock and adjusted_mode.crtc_clock
10116 * agree once we know their relationship in the encoder's
10117 * get_config() function.
10118 */
10119 pipe_config->base.adjusted_mode.crtc_clock =
10120 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10121 &pipe_config->fdi_m_n);
10122 }
10123
10124 /** Returns the currently programmed mode of the given pipe. */
10125 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10126 struct drm_crtc *crtc)
10127 {
10128 struct drm_i915_private *dev_priv = dev->dev_private;
10129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10130 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10131 struct drm_display_mode *mode;
10132 struct intel_crtc_state pipe_config;
10133 int htot = I915_READ(HTOTAL(cpu_transcoder));
10134 int hsync = I915_READ(HSYNC(cpu_transcoder));
10135 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10136 int vsync = I915_READ(VSYNC(cpu_transcoder));
10137 enum pipe pipe = intel_crtc->pipe;
10138
10139 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10140 if (!mode)
10141 return NULL;
10142
10143 /*
10144 * Construct a pipe_config sufficient for getting the clock info
10145 * back out of crtc_clock_get.
10146 *
10147 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10148 * to use a real value here instead.
10149 */
10150 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10151 pipe_config.pixel_multiplier = 1;
10152 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10153 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10154 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10155 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10156
10157 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10158 mode->hdisplay = (htot & 0xffff) + 1;
10159 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10160 mode->hsync_start = (hsync & 0xffff) + 1;
10161 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10162 mode->vdisplay = (vtot & 0xffff) + 1;
10163 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10164 mode->vsync_start = (vsync & 0xffff) + 1;
10165 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10166
10167 drm_mode_set_name(mode);
10168
10169 return mode;
10170 }
10171
10172 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10173 {
10174 struct drm_device *dev = crtc->dev;
10175 struct drm_i915_private *dev_priv = dev->dev_private;
10176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10177
10178 if (!HAS_GMCH_DISPLAY(dev))
10179 return;
10180
10181 if (!dev_priv->lvds_downclock_avail)
10182 return;
10183
10184 /*
10185 * Since this is called by a timer, we should never get here in
10186 * the manual case.
10187 */
10188 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10189 int pipe = intel_crtc->pipe;
10190 int dpll_reg = DPLL(pipe);
10191 int dpll;
10192
10193 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10194
10195 assert_panel_unlocked(dev_priv, pipe);
10196
10197 dpll = I915_READ(dpll_reg);
10198 dpll |= DISPLAY_RATE_SELECT_FPA1;
10199 I915_WRITE(dpll_reg, dpll);
10200 intel_wait_for_vblank(dev, pipe);
10201 dpll = I915_READ(dpll_reg);
10202 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10203 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10204 }
10205
10206 }
10207
10208 void intel_mark_busy(struct drm_device *dev)
10209 {
10210 struct drm_i915_private *dev_priv = dev->dev_private;
10211
10212 if (dev_priv->mm.busy)
10213 return;
10214
10215 intel_runtime_pm_get(dev_priv);
10216 i915_update_gfx_val(dev_priv);
10217 if (INTEL_INFO(dev)->gen >= 6)
10218 gen6_rps_busy(dev_priv);
10219 dev_priv->mm.busy = true;
10220 }
10221
10222 void intel_mark_idle(struct drm_device *dev)
10223 {
10224 struct drm_i915_private *dev_priv = dev->dev_private;
10225 struct drm_crtc *crtc;
10226
10227 if (!dev_priv->mm.busy)
10228 return;
10229
10230 dev_priv->mm.busy = false;
10231
10232 for_each_crtc(dev, crtc) {
10233 if (!crtc->primary->fb)
10234 continue;
10235
10236 intel_decrease_pllclock(crtc);
10237 }
10238
10239 if (INTEL_INFO(dev)->gen >= 6)
10240 gen6_rps_idle(dev->dev_private);
10241
10242 intel_runtime_pm_put(dev_priv);
10243 }
10244
10245 static void intel_crtc_destroy(struct drm_crtc *crtc)
10246 {
10247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10248 struct drm_device *dev = crtc->dev;
10249 struct intel_unpin_work *work;
10250
10251 spin_lock_irq(&dev->event_lock);
10252 work = intel_crtc->unpin_work;
10253 intel_crtc->unpin_work = NULL;
10254 spin_unlock_irq(&dev->event_lock);
10255
10256 if (work) {
10257 cancel_work_sync(&work->work);
10258 kfree(work);
10259 }
10260
10261 drm_crtc_cleanup(crtc);
10262
10263 kfree(intel_crtc);
10264 }
10265
10266 static void intel_unpin_work_fn(struct work_struct *__work)
10267 {
10268 struct intel_unpin_work *work =
10269 container_of(__work, struct intel_unpin_work, work);
10270 struct drm_device *dev = work->crtc->dev;
10271 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10272
10273 mutex_lock(&dev->struct_mutex);
10274 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10275 drm_gem_object_unreference(&work->pending_flip_obj->base);
10276
10277 intel_fbc_update(dev);
10278
10279 if (work->flip_queued_req)
10280 i915_gem_request_assign(&work->flip_queued_req, NULL);
10281 mutex_unlock(&dev->struct_mutex);
10282
10283 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10284 drm_framebuffer_unreference(work->old_fb);
10285
10286 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10287 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10288
10289 kfree(work);
10290 }
10291
10292 static void do_intel_finish_page_flip(struct drm_device *dev,
10293 struct drm_crtc *crtc)
10294 {
10295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10296 struct intel_unpin_work *work;
10297 unsigned long flags;
10298
10299 /* Ignore early vblank irqs */
10300 if (intel_crtc == NULL)
10301 return;
10302
10303 /*
10304 * This is called both by irq handlers and the reset code (to complete
10305 * lost pageflips) so needs the full irqsave spinlocks.
10306 */
10307 spin_lock_irqsave(&dev->event_lock, flags);
10308 work = intel_crtc->unpin_work;
10309
10310 /* Ensure we don't miss a work->pending update ... */
10311 smp_rmb();
10312
10313 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10314 spin_unlock_irqrestore(&dev->event_lock, flags);
10315 return;
10316 }
10317
10318 page_flip_completed(intel_crtc);
10319
10320 spin_unlock_irqrestore(&dev->event_lock, flags);
10321 }
10322
10323 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10324 {
10325 struct drm_i915_private *dev_priv = dev->dev_private;
10326 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10327
10328 do_intel_finish_page_flip(dev, crtc);
10329 }
10330
10331 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10332 {
10333 struct drm_i915_private *dev_priv = dev->dev_private;
10334 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10335
10336 do_intel_finish_page_flip(dev, crtc);
10337 }
10338
10339 /* Is 'a' after or equal to 'b'? */
10340 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10341 {
10342 return !((a - b) & 0x80000000);
10343 }
10344
10345 static bool page_flip_finished(struct intel_crtc *crtc)
10346 {
10347 struct drm_device *dev = crtc->base.dev;
10348 struct drm_i915_private *dev_priv = dev->dev_private;
10349
10350 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10351 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10352 return true;
10353
10354 /*
10355 * The relevant registers doen't exist on pre-ctg.
10356 * As the flip done interrupt doesn't trigger for mmio
10357 * flips on gmch platforms, a flip count check isn't
10358 * really needed there. But since ctg has the registers,
10359 * include it in the check anyway.
10360 */
10361 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10362 return true;
10363
10364 /*
10365 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10366 * used the same base address. In that case the mmio flip might
10367 * have completed, but the CS hasn't even executed the flip yet.
10368 *
10369 * A flip count check isn't enough as the CS might have updated
10370 * the base address just after start of vblank, but before we
10371 * managed to process the interrupt. This means we'd complete the
10372 * CS flip too soon.
10373 *
10374 * Combining both checks should get us a good enough result. It may
10375 * still happen that the CS flip has been executed, but has not
10376 * yet actually completed. But in case the base address is the same
10377 * anyway, we don't really care.
10378 */
10379 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10380 crtc->unpin_work->gtt_offset &&
10381 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10382 crtc->unpin_work->flip_count);
10383 }
10384
10385 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10386 {
10387 struct drm_i915_private *dev_priv = dev->dev_private;
10388 struct intel_crtc *intel_crtc =
10389 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10390 unsigned long flags;
10391
10392
10393 /*
10394 * This is called both by irq handlers and the reset code (to complete
10395 * lost pageflips) so needs the full irqsave spinlocks.
10396 *
10397 * NB: An MMIO update of the plane base pointer will also
10398 * generate a page-flip completion irq, i.e. every modeset
10399 * is also accompanied by a spurious intel_prepare_page_flip().
10400 */
10401 spin_lock_irqsave(&dev->event_lock, flags);
10402 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10403 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10404 spin_unlock_irqrestore(&dev->event_lock, flags);
10405 }
10406
10407 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10408 {
10409 /* Ensure that the work item is consistent when activating it ... */
10410 smp_wmb();
10411 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10412 /* and that it is marked active as soon as the irq could fire. */
10413 smp_wmb();
10414 }
10415
10416 static int intel_gen2_queue_flip(struct drm_device *dev,
10417 struct drm_crtc *crtc,
10418 struct drm_framebuffer *fb,
10419 struct drm_i915_gem_object *obj,
10420 struct intel_engine_cs *ring,
10421 uint32_t flags)
10422 {
10423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10424 u32 flip_mask;
10425 int ret;
10426
10427 ret = intel_ring_begin(ring, 6);
10428 if (ret)
10429 return ret;
10430
10431 /* Can't queue multiple flips, so wait for the previous
10432 * one to finish before executing the next.
10433 */
10434 if (intel_crtc->plane)
10435 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10436 else
10437 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10438 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10439 intel_ring_emit(ring, MI_NOOP);
10440 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10441 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10442 intel_ring_emit(ring, fb->pitches[0]);
10443 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10444 intel_ring_emit(ring, 0); /* aux display base address, unused */
10445
10446 intel_mark_page_flip_active(intel_crtc);
10447 __intel_ring_advance(ring);
10448 return 0;
10449 }
10450
10451 static int intel_gen3_queue_flip(struct drm_device *dev,
10452 struct drm_crtc *crtc,
10453 struct drm_framebuffer *fb,
10454 struct drm_i915_gem_object *obj,
10455 struct intel_engine_cs *ring,
10456 uint32_t flags)
10457 {
10458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10459 u32 flip_mask;
10460 int ret;
10461
10462 ret = intel_ring_begin(ring, 6);
10463 if (ret)
10464 return ret;
10465
10466 if (intel_crtc->plane)
10467 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10468 else
10469 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10470 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10471 intel_ring_emit(ring, MI_NOOP);
10472 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10473 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10474 intel_ring_emit(ring, fb->pitches[0]);
10475 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10476 intel_ring_emit(ring, MI_NOOP);
10477
10478 intel_mark_page_flip_active(intel_crtc);
10479 __intel_ring_advance(ring);
10480 return 0;
10481 }
10482
10483 static int intel_gen4_queue_flip(struct drm_device *dev,
10484 struct drm_crtc *crtc,
10485 struct drm_framebuffer *fb,
10486 struct drm_i915_gem_object *obj,
10487 struct intel_engine_cs *ring,
10488 uint32_t flags)
10489 {
10490 struct drm_i915_private *dev_priv = dev->dev_private;
10491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10492 uint32_t pf, pipesrc;
10493 int ret;
10494
10495 ret = intel_ring_begin(ring, 4);
10496 if (ret)
10497 return ret;
10498
10499 /* i965+ uses the linear or tiled offsets from the
10500 * Display Registers (which do not change across a page-flip)
10501 * so we need only reprogram the base address.
10502 */
10503 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10504 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10505 intel_ring_emit(ring, fb->pitches[0]);
10506 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10507 obj->tiling_mode);
10508
10509 /* XXX Enabling the panel-fitter across page-flip is so far
10510 * untested on non-native modes, so ignore it for now.
10511 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10512 */
10513 pf = 0;
10514 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10515 intel_ring_emit(ring, pf | pipesrc);
10516
10517 intel_mark_page_flip_active(intel_crtc);
10518 __intel_ring_advance(ring);
10519 return 0;
10520 }
10521
10522 static int intel_gen6_queue_flip(struct drm_device *dev,
10523 struct drm_crtc *crtc,
10524 struct drm_framebuffer *fb,
10525 struct drm_i915_gem_object *obj,
10526 struct intel_engine_cs *ring,
10527 uint32_t flags)
10528 {
10529 struct drm_i915_private *dev_priv = dev->dev_private;
10530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10531 uint32_t pf, pipesrc;
10532 int ret;
10533
10534 ret = intel_ring_begin(ring, 4);
10535 if (ret)
10536 return ret;
10537
10538 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10539 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10540 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10541 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10542
10543 /* Contrary to the suggestions in the documentation,
10544 * "Enable Panel Fitter" does not seem to be required when page
10545 * flipping with a non-native mode, and worse causes a normal
10546 * modeset to fail.
10547 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10548 */
10549 pf = 0;
10550 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10551 intel_ring_emit(ring, pf | pipesrc);
10552
10553 intel_mark_page_flip_active(intel_crtc);
10554 __intel_ring_advance(ring);
10555 return 0;
10556 }
10557
10558 static int intel_gen7_queue_flip(struct drm_device *dev,
10559 struct drm_crtc *crtc,
10560 struct drm_framebuffer *fb,
10561 struct drm_i915_gem_object *obj,
10562 struct intel_engine_cs *ring,
10563 uint32_t flags)
10564 {
10565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10566 uint32_t plane_bit = 0;
10567 int len, ret;
10568
10569 switch (intel_crtc->plane) {
10570 case PLANE_A:
10571 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10572 break;
10573 case PLANE_B:
10574 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10575 break;
10576 case PLANE_C:
10577 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10578 break;
10579 default:
10580 WARN_ONCE(1, "unknown plane in flip command\n");
10581 return -ENODEV;
10582 }
10583
10584 len = 4;
10585 if (ring->id == RCS) {
10586 len += 6;
10587 /*
10588 * On Gen 8, SRM is now taking an extra dword to accommodate
10589 * 48bits addresses, and we need a NOOP for the batch size to
10590 * stay even.
10591 */
10592 if (IS_GEN8(dev))
10593 len += 2;
10594 }
10595
10596 /*
10597 * BSpec MI_DISPLAY_FLIP for IVB:
10598 * "The full packet must be contained within the same cache line."
10599 *
10600 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10601 * cacheline, if we ever start emitting more commands before
10602 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10603 * then do the cacheline alignment, and finally emit the
10604 * MI_DISPLAY_FLIP.
10605 */
10606 ret = intel_ring_cacheline_align(ring);
10607 if (ret)
10608 return ret;
10609
10610 ret = intel_ring_begin(ring, len);
10611 if (ret)
10612 return ret;
10613
10614 /* Unmask the flip-done completion message. Note that the bspec says that
10615 * we should do this for both the BCS and RCS, and that we must not unmask
10616 * more than one flip event at any time (or ensure that one flip message
10617 * can be sent by waiting for flip-done prior to queueing new flips).
10618 * Experimentation says that BCS works despite DERRMR masking all
10619 * flip-done completion events and that unmasking all planes at once
10620 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10621 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10622 */
10623 if (ring->id == RCS) {
10624 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10625 intel_ring_emit(ring, DERRMR);
10626 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10627 DERRMR_PIPEB_PRI_FLIP_DONE |
10628 DERRMR_PIPEC_PRI_FLIP_DONE));
10629 if (IS_GEN8(dev))
10630 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10631 MI_SRM_LRM_GLOBAL_GTT);
10632 else
10633 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10634 MI_SRM_LRM_GLOBAL_GTT);
10635 intel_ring_emit(ring, DERRMR);
10636 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10637 if (IS_GEN8(dev)) {
10638 intel_ring_emit(ring, 0);
10639 intel_ring_emit(ring, MI_NOOP);
10640 }
10641 }
10642
10643 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10644 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10645 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10646 intel_ring_emit(ring, (MI_NOOP));
10647
10648 intel_mark_page_flip_active(intel_crtc);
10649 __intel_ring_advance(ring);
10650 return 0;
10651 }
10652
10653 static bool use_mmio_flip(struct intel_engine_cs *ring,
10654 struct drm_i915_gem_object *obj)
10655 {
10656 /*
10657 * This is not being used for older platforms, because
10658 * non-availability of flip done interrupt forces us to use
10659 * CS flips. Older platforms derive flip done using some clever
10660 * tricks involving the flip_pending status bits and vblank irqs.
10661 * So using MMIO flips there would disrupt this mechanism.
10662 */
10663
10664 if (ring == NULL)
10665 return true;
10666
10667 if (INTEL_INFO(ring->dev)->gen < 5)
10668 return false;
10669
10670 if (i915.use_mmio_flip < 0)
10671 return false;
10672 else if (i915.use_mmio_flip > 0)
10673 return true;
10674 else if (i915.enable_execlists)
10675 return true;
10676 else
10677 return ring != i915_gem_request_get_ring(obj->last_read_req);
10678 }
10679
10680 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10681 {
10682 struct drm_device *dev = intel_crtc->base.dev;
10683 struct drm_i915_private *dev_priv = dev->dev_private;
10684 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10685 const enum pipe pipe = intel_crtc->pipe;
10686 u32 ctl, stride;
10687
10688 ctl = I915_READ(PLANE_CTL(pipe, 0));
10689 ctl &= ~PLANE_CTL_TILED_MASK;
10690 switch (fb->modifier[0]) {
10691 case DRM_FORMAT_MOD_NONE:
10692 break;
10693 case I915_FORMAT_MOD_X_TILED:
10694 ctl |= PLANE_CTL_TILED_X;
10695 break;
10696 case I915_FORMAT_MOD_Y_TILED:
10697 ctl |= PLANE_CTL_TILED_Y;
10698 break;
10699 case I915_FORMAT_MOD_Yf_TILED:
10700 ctl |= PLANE_CTL_TILED_YF;
10701 break;
10702 default:
10703 MISSING_CASE(fb->modifier[0]);
10704 }
10705
10706 /*
10707 * The stride is either expressed as a multiple of 64 bytes chunks for
10708 * linear buffers or in number of tiles for tiled buffers.
10709 */
10710 stride = fb->pitches[0] /
10711 intel_fb_stride_alignment(dev, fb->modifier[0],
10712 fb->pixel_format);
10713
10714 /*
10715 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10716 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10717 */
10718 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10719 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10720
10721 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10722 POSTING_READ(PLANE_SURF(pipe, 0));
10723 }
10724
10725 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10726 {
10727 struct drm_device *dev = intel_crtc->base.dev;
10728 struct drm_i915_private *dev_priv = dev->dev_private;
10729 struct intel_framebuffer *intel_fb =
10730 to_intel_framebuffer(intel_crtc->base.primary->fb);
10731 struct drm_i915_gem_object *obj = intel_fb->obj;
10732 u32 dspcntr;
10733 u32 reg;
10734
10735 reg = DSPCNTR(intel_crtc->plane);
10736 dspcntr = I915_READ(reg);
10737
10738 if (obj->tiling_mode != I915_TILING_NONE)
10739 dspcntr |= DISPPLANE_TILED;
10740 else
10741 dspcntr &= ~DISPPLANE_TILED;
10742
10743 I915_WRITE(reg, dspcntr);
10744
10745 I915_WRITE(DSPSURF(intel_crtc->plane),
10746 intel_crtc->unpin_work->gtt_offset);
10747 POSTING_READ(DSPSURF(intel_crtc->plane));
10748
10749 }
10750
10751 /*
10752 * XXX: This is the temporary way to update the plane registers until we get
10753 * around to using the usual plane update functions for MMIO flips
10754 */
10755 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10756 {
10757 struct drm_device *dev = intel_crtc->base.dev;
10758 bool atomic_update;
10759 u32 start_vbl_count;
10760
10761 intel_mark_page_flip_active(intel_crtc);
10762
10763 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10764
10765 if (INTEL_INFO(dev)->gen >= 9)
10766 skl_do_mmio_flip(intel_crtc);
10767 else
10768 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10769 ilk_do_mmio_flip(intel_crtc);
10770
10771 if (atomic_update)
10772 intel_pipe_update_end(intel_crtc, start_vbl_count);
10773 }
10774
10775 static void intel_mmio_flip_work_func(struct work_struct *work)
10776 {
10777 struct intel_mmio_flip *mmio_flip =
10778 container_of(work, struct intel_mmio_flip, work);
10779
10780 if (mmio_flip->rq)
10781 WARN_ON(__i915_wait_request(mmio_flip->rq,
10782 mmio_flip->crtc->reset_counter,
10783 false, NULL, NULL));
10784
10785 intel_do_mmio_flip(mmio_flip->crtc);
10786
10787 i915_gem_request_unreference__unlocked(mmio_flip->rq);
10788 kfree(mmio_flip);
10789 }
10790
10791 static int intel_queue_mmio_flip(struct drm_device *dev,
10792 struct drm_crtc *crtc,
10793 struct drm_framebuffer *fb,
10794 struct drm_i915_gem_object *obj,
10795 struct intel_engine_cs *ring,
10796 uint32_t flags)
10797 {
10798 struct intel_mmio_flip *mmio_flip;
10799
10800 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10801 if (mmio_flip == NULL)
10802 return -ENOMEM;
10803
10804 mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10805 mmio_flip->crtc = to_intel_crtc(crtc);
10806
10807 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10808 schedule_work(&mmio_flip->work);
10809
10810 return 0;
10811 }
10812
10813 static int intel_default_queue_flip(struct drm_device *dev,
10814 struct drm_crtc *crtc,
10815 struct drm_framebuffer *fb,
10816 struct drm_i915_gem_object *obj,
10817 struct intel_engine_cs *ring,
10818 uint32_t flags)
10819 {
10820 return -ENODEV;
10821 }
10822
10823 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10824 struct drm_crtc *crtc)
10825 {
10826 struct drm_i915_private *dev_priv = dev->dev_private;
10827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10828 struct intel_unpin_work *work = intel_crtc->unpin_work;
10829 u32 addr;
10830
10831 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10832 return true;
10833
10834 if (!work->enable_stall_check)
10835 return false;
10836
10837 if (work->flip_ready_vblank == 0) {
10838 if (work->flip_queued_req &&
10839 !i915_gem_request_completed(work->flip_queued_req, true))
10840 return false;
10841
10842 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10843 }
10844
10845 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10846 return false;
10847
10848 /* Potential stall - if we see that the flip has happened,
10849 * assume a missed interrupt. */
10850 if (INTEL_INFO(dev)->gen >= 4)
10851 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10852 else
10853 addr = I915_READ(DSPADDR(intel_crtc->plane));
10854
10855 /* There is a potential issue here with a false positive after a flip
10856 * to the same address. We could address this by checking for a
10857 * non-incrementing frame counter.
10858 */
10859 return addr == work->gtt_offset;
10860 }
10861
10862 void intel_check_page_flip(struct drm_device *dev, int pipe)
10863 {
10864 struct drm_i915_private *dev_priv = dev->dev_private;
10865 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10867 struct intel_unpin_work *work;
10868
10869 WARN_ON(!in_interrupt());
10870
10871 if (crtc == NULL)
10872 return;
10873
10874 spin_lock(&dev->event_lock);
10875 work = intel_crtc->unpin_work;
10876 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10877 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10878 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10879 page_flip_completed(intel_crtc);
10880 work = NULL;
10881 }
10882 if (work != NULL &&
10883 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10884 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10885 spin_unlock(&dev->event_lock);
10886 }
10887
10888 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
10890 struct drm_pending_vblank_event *event,
10891 uint32_t page_flip_flags)
10892 {
10893 struct drm_device *dev = crtc->dev;
10894 struct drm_i915_private *dev_priv = dev->dev_private;
10895 struct drm_framebuffer *old_fb = crtc->primary->fb;
10896 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10898 struct drm_plane *primary = crtc->primary;
10899 enum pipe pipe = intel_crtc->pipe;
10900 struct intel_unpin_work *work;
10901 struct intel_engine_cs *ring;
10902 bool mmio_flip;
10903 int ret;
10904
10905 /*
10906 * drm_mode_page_flip_ioctl() should already catch this, but double
10907 * check to be safe. In the future we may enable pageflipping from
10908 * a disabled primary plane.
10909 */
10910 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10911 return -EBUSY;
10912
10913 /* Can't change pixel format via MI display flips. */
10914 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10915 return -EINVAL;
10916
10917 /*
10918 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10919 * Note that pitch changes could also affect these register.
10920 */
10921 if (INTEL_INFO(dev)->gen > 3 &&
10922 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10923 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10924 return -EINVAL;
10925
10926 if (i915_terminally_wedged(&dev_priv->gpu_error))
10927 goto out_hang;
10928
10929 work = kzalloc(sizeof(*work), GFP_KERNEL);
10930 if (work == NULL)
10931 return -ENOMEM;
10932
10933 work->event = event;
10934 work->crtc = crtc;
10935 work->old_fb = old_fb;
10936 INIT_WORK(&work->work, intel_unpin_work_fn);
10937
10938 ret = drm_crtc_vblank_get(crtc);
10939 if (ret)
10940 goto free_work;
10941
10942 /* We borrow the event spin lock for protecting unpin_work */
10943 spin_lock_irq(&dev->event_lock);
10944 if (intel_crtc->unpin_work) {
10945 /* Before declaring the flip queue wedged, check if
10946 * the hardware completed the operation behind our backs.
10947 */
10948 if (__intel_pageflip_stall_check(dev, crtc)) {
10949 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10950 page_flip_completed(intel_crtc);
10951 } else {
10952 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10953 spin_unlock_irq(&dev->event_lock);
10954
10955 drm_crtc_vblank_put(crtc);
10956 kfree(work);
10957 return -EBUSY;
10958 }
10959 }
10960 intel_crtc->unpin_work = work;
10961 spin_unlock_irq(&dev->event_lock);
10962
10963 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10964 flush_workqueue(dev_priv->wq);
10965
10966 /* Reference the objects for the scheduled work. */
10967 drm_framebuffer_reference(work->old_fb);
10968 drm_gem_object_reference(&obj->base);
10969
10970 crtc->primary->fb = fb;
10971 update_state_fb(crtc->primary);
10972
10973 work->pending_flip_obj = obj;
10974
10975 ret = i915_mutex_lock_interruptible(dev);
10976 if (ret)
10977 goto cleanup;
10978
10979 atomic_inc(&intel_crtc->unpin_work_count);
10980 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10981
10982 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10983 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10984
10985 if (IS_VALLEYVIEW(dev)) {
10986 ring = &dev_priv->ring[BCS];
10987 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10988 /* vlv: DISPLAY_FLIP fails to change tiling */
10989 ring = NULL;
10990 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10991 ring = &dev_priv->ring[BCS];
10992 } else if (INTEL_INFO(dev)->gen >= 7) {
10993 ring = i915_gem_request_get_ring(obj->last_read_req);
10994 if (ring == NULL || ring->id != RCS)
10995 ring = &dev_priv->ring[BCS];
10996 } else {
10997 ring = &dev_priv->ring[RCS];
10998 }
10999
11000 mmio_flip = use_mmio_flip(ring, obj);
11001
11002 /* When using CS flips, we want to emit semaphores between rings.
11003 * However, when using mmio flips we will create a task to do the
11004 * synchronisation, so all we want here is to pin the framebuffer
11005 * into the display plane and skip any waits.
11006 */
11007 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11008 crtc->primary->state,
11009 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11010 if (ret)
11011 goto cleanup_pending;
11012
11013 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11014 + intel_crtc->dspaddr_offset;
11015
11016 if (mmio_flip) {
11017 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11018 page_flip_flags);
11019 if (ret)
11020 goto cleanup_unpin;
11021
11022 i915_gem_request_assign(&work->flip_queued_req,
11023 obj->last_write_req);
11024 } else {
11025 if (obj->last_write_req) {
11026 ret = i915_gem_check_olr(obj->last_write_req);
11027 if (ret)
11028 goto cleanup_unpin;
11029 }
11030
11031 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11032 page_flip_flags);
11033 if (ret)
11034 goto cleanup_unpin;
11035
11036 i915_gem_request_assign(&work->flip_queued_req,
11037 intel_ring_get_request(ring));
11038 }
11039
11040 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11041 work->enable_stall_check = true;
11042
11043 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11044 INTEL_FRONTBUFFER_PRIMARY(pipe));
11045
11046 intel_fbc_disable(dev);
11047 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11048 mutex_unlock(&dev->struct_mutex);
11049
11050 trace_i915_flip_request(intel_crtc->plane, obj);
11051
11052 return 0;
11053
11054 cleanup_unpin:
11055 intel_unpin_fb_obj(fb, crtc->primary->state);
11056 cleanup_pending:
11057 atomic_dec(&intel_crtc->unpin_work_count);
11058 mutex_unlock(&dev->struct_mutex);
11059 cleanup:
11060 crtc->primary->fb = old_fb;
11061 update_state_fb(crtc->primary);
11062
11063 drm_gem_object_unreference_unlocked(&obj->base);
11064 drm_framebuffer_unreference(work->old_fb);
11065
11066 spin_lock_irq(&dev->event_lock);
11067 intel_crtc->unpin_work = NULL;
11068 spin_unlock_irq(&dev->event_lock);
11069
11070 drm_crtc_vblank_put(crtc);
11071 free_work:
11072 kfree(work);
11073
11074 if (ret == -EIO) {
11075 out_hang:
11076 ret = intel_plane_restore(primary);
11077 if (ret == 0 && event) {
11078 spin_lock_irq(&dev->event_lock);
11079 drm_send_vblank_event(dev, pipe, event);
11080 spin_unlock_irq(&dev->event_lock);
11081 }
11082 }
11083 return ret;
11084 }
11085
11086 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11087 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11088 .load_lut = intel_crtc_load_lut,
11089 .atomic_begin = intel_begin_crtc_commit,
11090 .atomic_flush = intel_finish_crtc_commit,
11091 };
11092
11093 /**
11094 * intel_modeset_update_staged_output_state
11095 *
11096 * Updates the staged output configuration state, e.g. after we've read out the
11097 * current hw state.
11098 */
11099 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11100 {
11101 struct intel_crtc *crtc;
11102 struct intel_encoder *encoder;
11103 struct intel_connector *connector;
11104
11105 for_each_intel_connector(dev, connector) {
11106 connector->new_encoder =
11107 to_intel_encoder(connector->base.encoder);
11108 }
11109
11110 for_each_intel_encoder(dev, encoder) {
11111 encoder->new_crtc =
11112 to_intel_crtc(encoder->base.crtc);
11113 }
11114
11115 for_each_intel_crtc(dev, crtc) {
11116 crtc->new_enabled = crtc->base.state->enable;
11117 }
11118 }
11119
11120 /* Transitional helper to copy current connector/encoder state to
11121 * connector->state. This is needed so that code that is partially
11122 * converted to atomic does the right thing.
11123 */
11124 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11125 {
11126 struct intel_connector *connector;
11127
11128 for_each_intel_connector(dev, connector) {
11129 if (connector->base.encoder) {
11130 connector->base.state->best_encoder =
11131 connector->base.encoder;
11132 connector->base.state->crtc =
11133 connector->base.encoder->crtc;
11134 } else {
11135 connector->base.state->best_encoder = NULL;
11136 connector->base.state->crtc = NULL;
11137 }
11138 }
11139 }
11140
11141 /* Fixup legacy state after an atomic state swap.
11142 */
11143 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11144 {
11145 struct intel_crtc *crtc;
11146 struct intel_encoder *encoder;
11147 struct intel_connector *connector;
11148
11149 for_each_intel_connector(state->dev, connector) {
11150 connector->base.encoder = connector->base.state->best_encoder;
11151 if (connector->base.encoder)
11152 connector->base.encoder->crtc =
11153 connector->base.state->crtc;
11154 }
11155
11156 /* Update crtc of disabled encoders */
11157 for_each_intel_encoder(state->dev, encoder) {
11158 int num_connectors = 0;
11159
11160 for_each_intel_connector(state->dev, connector)
11161 if (connector->base.encoder == &encoder->base)
11162 num_connectors++;
11163
11164 if (num_connectors == 0)
11165 encoder->base.crtc = NULL;
11166 }
11167
11168 for_each_intel_crtc(state->dev, crtc) {
11169 crtc->base.enabled = crtc->base.state->enable;
11170 crtc->config = to_intel_crtc_state(crtc->base.state);
11171 }
11172
11173 /* Copy the new configuration to the staged state, to keep the few
11174 * pieces of code that haven't been converted yet happy */
11175 intel_modeset_update_staged_output_state(state->dev);
11176 }
11177
11178 static void
11179 connected_sink_compute_bpp(struct intel_connector *connector,
11180 struct intel_crtc_state *pipe_config)
11181 {
11182 int bpp = pipe_config->pipe_bpp;
11183
11184 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11185 connector->base.base.id,
11186 connector->base.name);
11187
11188 /* Don't use an invalid EDID bpc value */
11189 if (connector->base.display_info.bpc &&
11190 connector->base.display_info.bpc * 3 < bpp) {
11191 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11192 bpp, connector->base.display_info.bpc*3);
11193 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11194 }
11195
11196 /* Clamp bpp to 8 on screens without EDID 1.4 */
11197 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11198 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11199 bpp);
11200 pipe_config->pipe_bpp = 24;
11201 }
11202 }
11203
11204 static int
11205 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11206 struct intel_crtc_state *pipe_config)
11207 {
11208 struct drm_device *dev = crtc->base.dev;
11209 struct drm_atomic_state *state;
11210 struct drm_connector *connector;
11211 struct drm_connector_state *connector_state;
11212 int bpp, i;
11213
11214 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11215 bpp = 10*3;
11216 else if (INTEL_INFO(dev)->gen >= 5)
11217 bpp = 12*3;
11218 else
11219 bpp = 8*3;
11220
11221
11222 pipe_config->pipe_bpp = bpp;
11223
11224 state = pipe_config->base.state;
11225
11226 /* Clamp display bpp to EDID value */
11227 for_each_connector_in_state(state, connector, connector_state, i) {
11228 if (connector_state->crtc != &crtc->base)
11229 continue;
11230
11231 connected_sink_compute_bpp(to_intel_connector(connector),
11232 pipe_config);
11233 }
11234
11235 return bpp;
11236 }
11237
11238 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11239 {
11240 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11241 "type: 0x%x flags: 0x%x\n",
11242 mode->crtc_clock,
11243 mode->crtc_hdisplay, mode->crtc_hsync_start,
11244 mode->crtc_hsync_end, mode->crtc_htotal,
11245 mode->crtc_vdisplay, mode->crtc_vsync_start,
11246 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11247 }
11248
11249 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11250 struct intel_crtc_state *pipe_config,
11251 const char *context)
11252 {
11253 struct drm_device *dev = crtc->base.dev;
11254 struct drm_plane *plane;
11255 struct intel_plane *intel_plane;
11256 struct intel_plane_state *state;
11257 struct drm_framebuffer *fb;
11258
11259 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11260 context, pipe_config, pipe_name(crtc->pipe));
11261
11262 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11263 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11264 pipe_config->pipe_bpp, pipe_config->dither);
11265 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11266 pipe_config->has_pch_encoder,
11267 pipe_config->fdi_lanes,
11268 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11269 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11270 pipe_config->fdi_m_n.tu);
11271 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11272 pipe_config->has_dp_encoder,
11273 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11274 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11275 pipe_config->dp_m_n.tu);
11276
11277 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11278 pipe_config->has_dp_encoder,
11279 pipe_config->dp_m2_n2.gmch_m,
11280 pipe_config->dp_m2_n2.gmch_n,
11281 pipe_config->dp_m2_n2.link_m,
11282 pipe_config->dp_m2_n2.link_n,
11283 pipe_config->dp_m2_n2.tu);
11284
11285 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11286 pipe_config->has_audio,
11287 pipe_config->has_infoframe);
11288
11289 DRM_DEBUG_KMS("requested mode:\n");
11290 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11291 DRM_DEBUG_KMS("adjusted mode:\n");
11292 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11293 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11294 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11295 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11296 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11297 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11298 crtc->num_scalers,
11299 pipe_config->scaler_state.scaler_users,
11300 pipe_config->scaler_state.scaler_id);
11301 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11302 pipe_config->gmch_pfit.control,
11303 pipe_config->gmch_pfit.pgm_ratios,
11304 pipe_config->gmch_pfit.lvds_border_bits);
11305 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11306 pipe_config->pch_pfit.pos,
11307 pipe_config->pch_pfit.size,
11308 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11309 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11310 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11311
11312 if (IS_BROXTON(dev)) {
11313 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11314 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11315 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11316 pipe_config->ddi_pll_sel,
11317 pipe_config->dpll_hw_state.ebb0,
11318 pipe_config->dpll_hw_state.pll0,
11319 pipe_config->dpll_hw_state.pll1,
11320 pipe_config->dpll_hw_state.pll2,
11321 pipe_config->dpll_hw_state.pll3,
11322 pipe_config->dpll_hw_state.pll6,
11323 pipe_config->dpll_hw_state.pll8,
11324 pipe_config->dpll_hw_state.pcsdw12);
11325 } else if (IS_SKYLAKE(dev)) {
11326 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11327 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11328 pipe_config->ddi_pll_sel,
11329 pipe_config->dpll_hw_state.ctrl1,
11330 pipe_config->dpll_hw_state.cfgcr1,
11331 pipe_config->dpll_hw_state.cfgcr2);
11332 } else if (HAS_DDI(dev)) {
11333 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11334 pipe_config->ddi_pll_sel,
11335 pipe_config->dpll_hw_state.wrpll);
11336 } else {
11337 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11338 "fp0: 0x%x, fp1: 0x%x\n",
11339 pipe_config->dpll_hw_state.dpll,
11340 pipe_config->dpll_hw_state.dpll_md,
11341 pipe_config->dpll_hw_state.fp0,
11342 pipe_config->dpll_hw_state.fp1);
11343 }
11344
11345 DRM_DEBUG_KMS("planes on this crtc\n");
11346 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11347 intel_plane = to_intel_plane(plane);
11348 if (intel_plane->pipe != crtc->pipe)
11349 continue;
11350
11351 state = to_intel_plane_state(plane->state);
11352 fb = state->base.fb;
11353 if (!fb) {
11354 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11355 "disabled, scaler_id = %d\n",
11356 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11357 plane->base.id, intel_plane->pipe,
11358 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11359 drm_plane_index(plane), state->scaler_id);
11360 continue;
11361 }
11362
11363 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11364 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11365 plane->base.id, intel_plane->pipe,
11366 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11367 drm_plane_index(plane));
11368 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11369 fb->base.id, fb->width, fb->height, fb->pixel_format);
11370 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11371 state->scaler_id,
11372 state->src.x1 >> 16, state->src.y1 >> 16,
11373 drm_rect_width(&state->src) >> 16,
11374 drm_rect_height(&state->src) >> 16,
11375 state->dst.x1, state->dst.y1,
11376 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11377 }
11378 }
11379
11380 static bool encoders_cloneable(const struct intel_encoder *a,
11381 const struct intel_encoder *b)
11382 {
11383 /* masks could be asymmetric, so check both ways */
11384 return a == b || (a->cloneable & (1 << b->type) &&
11385 b->cloneable & (1 << a->type));
11386 }
11387
11388 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11389 struct intel_crtc *crtc,
11390 struct intel_encoder *encoder)
11391 {
11392 struct intel_encoder *source_encoder;
11393 struct drm_connector *connector;
11394 struct drm_connector_state *connector_state;
11395 int i;
11396
11397 for_each_connector_in_state(state, connector, connector_state, i) {
11398 if (connector_state->crtc != &crtc->base)
11399 continue;
11400
11401 source_encoder =
11402 to_intel_encoder(connector_state->best_encoder);
11403 if (!encoders_cloneable(encoder, source_encoder))
11404 return false;
11405 }
11406
11407 return true;
11408 }
11409
11410 static bool check_encoder_cloning(struct drm_atomic_state *state,
11411 struct intel_crtc *crtc)
11412 {
11413 struct intel_encoder *encoder;
11414 struct drm_connector *connector;
11415 struct drm_connector_state *connector_state;
11416 int i;
11417
11418 for_each_connector_in_state(state, connector, connector_state, i) {
11419 if (connector_state->crtc != &crtc->base)
11420 continue;
11421
11422 encoder = to_intel_encoder(connector_state->best_encoder);
11423 if (!check_single_encoder_cloning(state, crtc, encoder))
11424 return false;
11425 }
11426
11427 return true;
11428 }
11429
11430 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11431 {
11432 struct drm_device *dev = state->dev;
11433 struct intel_encoder *encoder;
11434 struct drm_connector *connector;
11435 struct drm_connector_state *connector_state;
11436 unsigned int used_ports = 0;
11437 int i;
11438
11439 /*
11440 * Walk the connector list instead of the encoder
11441 * list to detect the problem on ddi platforms
11442 * where there's just one encoder per digital port.
11443 */
11444 for_each_connector_in_state(state, connector, connector_state, i) {
11445 if (!connector_state->best_encoder)
11446 continue;
11447
11448 encoder = to_intel_encoder(connector_state->best_encoder);
11449
11450 WARN_ON(!connector_state->crtc);
11451
11452 switch (encoder->type) {
11453 unsigned int port_mask;
11454 case INTEL_OUTPUT_UNKNOWN:
11455 if (WARN_ON(!HAS_DDI(dev)))
11456 break;
11457 case INTEL_OUTPUT_DISPLAYPORT:
11458 case INTEL_OUTPUT_HDMI:
11459 case INTEL_OUTPUT_EDP:
11460 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11461
11462 /* the same port mustn't appear more than once */
11463 if (used_ports & port_mask)
11464 return false;
11465
11466 used_ports |= port_mask;
11467 default:
11468 break;
11469 }
11470 }
11471
11472 return true;
11473 }
11474
11475 static void
11476 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11477 {
11478 struct drm_crtc_state tmp_state;
11479 struct intel_crtc_scaler_state scaler_state;
11480 struct intel_dpll_hw_state dpll_hw_state;
11481 enum intel_dpll_id shared_dpll;
11482 uint32_t ddi_pll_sel;
11483
11484 /* Clear only the intel specific part of the crtc state excluding scalers */
11485 tmp_state = crtc_state->base;
11486 scaler_state = crtc_state->scaler_state;
11487 shared_dpll = crtc_state->shared_dpll;
11488 dpll_hw_state = crtc_state->dpll_hw_state;
11489 ddi_pll_sel = crtc_state->ddi_pll_sel;
11490
11491 memset(crtc_state, 0, sizeof *crtc_state);
11492
11493 crtc_state->base = tmp_state;
11494 crtc_state->scaler_state = scaler_state;
11495 crtc_state->shared_dpll = shared_dpll;
11496 crtc_state->dpll_hw_state = dpll_hw_state;
11497 crtc_state->ddi_pll_sel = ddi_pll_sel;
11498 }
11499
11500 static int
11501 intel_modeset_pipe_config(struct drm_crtc *crtc,
11502 struct drm_atomic_state *state,
11503 struct intel_crtc_state *pipe_config)
11504 {
11505 struct intel_encoder *encoder;
11506 struct drm_connector *connector;
11507 struct drm_connector_state *connector_state;
11508 int base_bpp, ret = -EINVAL;
11509 int i;
11510 bool retry = true;
11511
11512 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11513 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11514 return -EINVAL;
11515 }
11516
11517 if (!check_digital_port_conflicts(state)) {
11518 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11519 return -EINVAL;
11520 }
11521
11522 clear_intel_crtc_state(pipe_config);
11523
11524 pipe_config->cpu_transcoder =
11525 (enum transcoder) to_intel_crtc(crtc)->pipe;
11526
11527 /*
11528 * Sanitize sync polarity flags based on requested ones. If neither
11529 * positive or negative polarity is requested, treat this as meaning
11530 * negative polarity.
11531 */
11532 if (!(pipe_config->base.adjusted_mode.flags &
11533 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11534 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11535
11536 if (!(pipe_config->base.adjusted_mode.flags &
11537 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11538 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11539
11540 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11541 * plane pixel format and any sink constraints into account. Returns the
11542 * source plane bpp so that dithering can be selected on mismatches
11543 * after encoders and crtc also have had their say. */
11544 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11545 pipe_config);
11546 if (base_bpp < 0)
11547 goto fail;
11548
11549 /*
11550 * Determine the real pipe dimensions. Note that stereo modes can
11551 * increase the actual pipe size due to the frame doubling and
11552 * insertion of additional space for blanks between the frame. This
11553 * is stored in the crtc timings. We use the requested mode to do this
11554 * computation to clearly distinguish it from the adjusted mode, which
11555 * can be changed by the connectors in the below retry loop.
11556 */
11557 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11558 &pipe_config->pipe_src_w,
11559 &pipe_config->pipe_src_h);
11560
11561 encoder_retry:
11562 /* Ensure the port clock defaults are reset when retrying. */
11563 pipe_config->port_clock = 0;
11564 pipe_config->pixel_multiplier = 1;
11565
11566 /* Fill in default crtc timings, allow encoders to overwrite them. */
11567 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11568 CRTC_STEREO_DOUBLE);
11569
11570 /* Pass our mode to the connectors and the CRTC to give them a chance to
11571 * adjust it according to limitations or connector properties, and also
11572 * a chance to reject the mode entirely.
11573 */
11574 for_each_connector_in_state(state, connector, connector_state, i) {
11575 if (connector_state->crtc != crtc)
11576 continue;
11577
11578 encoder = to_intel_encoder(connector_state->best_encoder);
11579
11580 if (!(encoder->compute_config(encoder, pipe_config))) {
11581 DRM_DEBUG_KMS("Encoder config failure\n");
11582 goto fail;
11583 }
11584 }
11585
11586 /* Set default port clock if not overwritten by the encoder. Needs to be
11587 * done afterwards in case the encoder adjusts the mode. */
11588 if (!pipe_config->port_clock)
11589 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11590 * pipe_config->pixel_multiplier;
11591
11592 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11593 if (ret < 0) {
11594 DRM_DEBUG_KMS("CRTC fixup failed\n");
11595 goto fail;
11596 }
11597
11598 if (ret == RETRY) {
11599 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11600 ret = -EINVAL;
11601 goto fail;
11602 }
11603
11604 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11605 retry = false;
11606 goto encoder_retry;
11607 }
11608
11609 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11610 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11611 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11612
11613 return 0;
11614 fail:
11615 return ret;
11616 }
11617
11618 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11619 {
11620 struct drm_encoder *encoder;
11621 struct drm_device *dev = crtc->dev;
11622
11623 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11624 if (encoder->crtc == crtc)
11625 return true;
11626
11627 return false;
11628 }
11629
11630 static bool
11631 needs_modeset(struct drm_crtc_state *state)
11632 {
11633 return state->mode_changed || state->active_changed;
11634 }
11635
11636 static void
11637 intel_modeset_update_state(struct drm_atomic_state *state)
11638 {
11639 struct drm_device *dev = state->dev;
11640 struct drm_i915_private *dev_priv = dev->dev_private;
11641 struct intel_encoder *intel_encoder;
11642 struct drm_crtc *crtc;
11643 struct drm_crtc_state *crtc_state;
11644 struct drm_connector *connector;
11645 int i;
11646
11647 intel_shared_dpll_commit(dev_priv);
11648
11649 for_each_intel_encoder(dev, intel_encoder) {
11650 if (!intel_encoder->base.crtc)
11651 continue;
11652
11653 for_each_crtc_in_state(state, crtc, crtc_state, i)
11654 if (crtc == intel_encoder->base.crtc)
11655 break;
11656
11657 if (crtc != intel_encoder->base.crtc)
11658 continue;
11659
11660 if (crtc_state->enable && needs_modeset(crtc_state))
11661 intel_encoder->connectors_active = false;
11662 }
11663
11664 drm_atomic_helper_swap_state(state->dev, state);
11665 intel_modeset_fixup_state(state);
11666
11667 /* Double check state. */
11668 for_each_crtc(dev, crtc) {
11669 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11670 }
11671
11672 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11673 if (!connector->encoder || !connector->encoder->crtc)
11674 continue;
11675
11676 for_each_crtc_in_state(state, crtc, crtc_state, i)
11677 if (crtc == connector->encoder->crtc)
11678 break;
11679
11680 if (crtc != connector->encoder->crtc)
11681 continue;
11682
11683 if (crtc->state->enable && needs_modeset(crtc->state)) {
11684 struct drm_property *dpms_property =
11685 dev->mode_config.dpms_property;
11686
11687 connector->dpms = DRM_MODE_DPMS_ON;
11688 drm_object_property_set_value(&connector->base,
11689 dpms_property,
11690 DRM_MODE_DPMS_ON);
11691
11692 intel_encoder = to_intel_encoder(connector->encoder);
11693 intel_encoder->connectors_active = true;
11694 }
11695 }
11696
11697 }
11698
11699 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11700 {
11701 int diff;
11702
11703 if (clock1 == clock2)
11704 return true;
11705
11706 if (!clock1 || !clock2)
11707 return false;
11708
11709 diff = abs(clock1 - clock2);
11710
11711 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11712 return true;
11713
11714 return false;
11715 }
11716
11717 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11718 list_for_each_entry((intel_crtc), \
11719 &(dev)->mode_config.crtc_list, \
11720 base.head) \
11721 if (mask & (1 <<(intel_crtc)->pipe))
11722
11723 static bool
11724 intel_pipe_config_compare(struct drm_device *dev,
11725 struct intel_crtc_state *current_config,
11726 struct intel_crtc_state *pipe_config)
11727 {
11728 #define PIPE_CONF_CHECK_X(name) \
11729 if (current_config->name != pipe_config->name) { \
11730 DRM_ERROR("mismatch in " #name " " \
11731 "(expected 0x%08x, found 0x%08x)\n", \
11732 current_config->name, \
11733 pipe_config->name); \
11734 return false; \
11735 }
11736
11737 #define PIPE_CONF_CHECK_I(name) \
11738 if (current_config->name != pipe_config->name) { \
11739 DRM_ERROR("mismatch in " #name " " \
11740 "(expected %i, found %i)\n", \
11741 current_config->name, \
11742 pipe_config->name); \
11743 return false; \
11744 }
11745
11746 /* This is required for BDW+ where there is only one set of registers for
11747 * switching between high and low RR.
11748 * This macro can be used whenever a comparison has to be made between one
11749 * hw state and multiple sw state variables.
11750 */
11751 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11752 if ((current_config->name != pipe_config->name) && \
11753 (current_config->alt_name != pipe_config->name)) { \
11754 DRM_ERROR("mismatch in " #name " " \
11755 "(expected %i or %i, found %i)\n", \
11756 current_config->name, \
11757 current_config->alt_name, \
11758 pipe_config->name); \
11759 return false; \
11760 }
11761
11762 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11763 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11764 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11765 "(expected %i, found %i)\n", \
11766 current_config->name & (mask), \
11767 pipe_config->name & (mask)); \
11768 return false; \
11769 }
11770
11771 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11772 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11773 DRM_ERROR("mismatch in " #name " " \
11774 "(expected %i, found %i)\n", \
11775 current_config->name, \
11776 pipe_config->name); \
11777 return false; \
11778 }
11779
11780 #define PIPE_CONF_QUIRK(quirk) \
11781 ((current_config->quirks | pipe_config->quirks) & (quirk))
11782
11783 PIPE_CONF_CHECK_I(cpu_transcoder);
11784
11785 PIPE_CONF_CHECK_I(has_pch_encoder);
11786 PIPE_CONF_CHECK_I(fdi_lanes);
11787 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11788 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11789 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11790 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11791 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11792
11793 PIPE_CONF_CHECK_I(has_dp_encoder);
11794
11795 if (INTEL_INFO(dev)->gen < 8) {
11796 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11797 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11798 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11799 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11800 PIPE_CONF_CHECK_I(dp_m_n.tu);
11801
11802 if (current_config->has_drrs) {
11803 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11804 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11805 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11806 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11807 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11808 }
11809 } else {
11810 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11811 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11812 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11813 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11814 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11815 }
11816
11817 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11818 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11819 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11820 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11821 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11822 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11823
11824 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11825 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11826 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11827 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11828 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11829 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11830
11831 PIPE_CONF_CHECK_I(pixel_multiplier);
11832 PIPE_CONF_CHECK_I(has_hdmi_sink);
11833 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11834 IS_VALLEYVIEW(dev))
11835 PIPE_CONF_CHECK_I(limited_color_range);
11836 PIPE_CONF_CHECK_I(has_infoframe);
11837
11838 PIPE_CONF_CHECK_I(has_audio);
11839
11840 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11841 DRM_MODE_FLAG_INTERLACE);
11842
11843 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11844 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11845 DRM_MODE_FLAG_PHSYNC);
11846 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11847 DRM_MODE_FLAG_NHSYNC);
11848 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11849 DRM_MODE_FLAG_PVSYNC);
11850 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11851 DRM_MODE_FLAG_NVSYNC);
11852 }
11853
11854 PIPE_CONF_CHECK_I(pipe_src_w);
11855 PIPE_CONF_CHECK_I(pipe_src_h);
11856
11857 /*
11858 * FIXME: BIOS likes to set up a cloned config with lvds+external
11859 * screen. Since we don't yet re-compute the pipe config when moving
11860 * just the lvds port away to another pipe the sw tracking won't match.
11861 *
11862 * Proper atomic modesets with recomputed global state will fix this.
11863 * Until then just don't check gmch state for inherited modes.
11864 */
11865 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11866 PIPE_CONF_CHECK_I(gmch_pfit.control);
11867 /* pfit ratios are autocomputed by the hw on gen4+ */
11868 if (INTEL_INFO(dev)->gen < 4)
11869 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11870 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11871 }
11872
11873 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11874 if (current_config->pch_pfit.enabled) {
11875 PIPE_CONF_CHECK_I(pch_pfit.pos);
11876 PIPE_CONF_CHECK_I(pch_pfit.size);
11877 }
11878
11879 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11880
11881 /* BDW+ don't expose a synchronous way to read the state */
11882 if (IS_HASWELL(dev))
11883 PIPE_CONF_CHECK_I(ips_enabled);
11884
11885 PIPE_CONF_CHECK_I(double_wide);
11886
11887 PIPE_CONF_CHECK_X(ddi_pll_sel);
11888
11889 PIPE_CONF_CHECK_I(shared_dpll);
11890 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11891 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11892 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11893 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11894 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11895 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11896 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11897 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11898
11899 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11900 PIPE_CONF_CHECK_I(pipe_bpp);
11901
11902 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11903 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11904
11905 #undef PIPE_CONF_CHECK_X
11906 #undef PIPE_CONF_CHECK_I
11907 #undef PIPE_CONF_CHECK_I_ALT
11908 #undef PIPE_CONF_CHECK_FLAGS
11909 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11910 #undef PIPE_CONF_QUIRK
11911
11912 return true;
11913 }
11914
11915 static void check_wm_state(struct drm_device *dev)
11916 {
11917 struct drm_i915_private *dev_priv = dev->dev_private;
11918 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11919 struct intel_crtc *intel_crtc;
11920 int plane;
11921
11922 if (INTEL_INFO(dev)->gen < 9)
11923 return;
11924
11925 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11926 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11927
11928 for_each_intel_crtc(dev, intel_crtc) {
11929 struct skl_ddb_entry *hw_entry, *sw_entry;
11930 const enum pipe pipe = intel_crtc->pipe;
11931
11932 if (!intel_crtc->active)
11933 continue;
11934
11935 /* planes */
11936 for_each_plane(dev_priv, pipe, plane) {
11937 hw_entry = &hw_ddb.plane[pipe][plane];
11938 sw_entry = &sw_ddb->plane[pipe][plane];
11939
11940 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11941 continue;
11942
11943 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11944 "(expected (%u,%u), found (%u,%u))\n",
11945 pipe_name(pipe), plane + 1,
11946 sw_entry->start, sw_entry->end,
11947 hw_entry->start, hw_entry->end);
11948 }
11949
11950 /* cursor */
11951 hw_entry = &hw_ddb.cursor[pipe];
11952 sw_entry = &sw_ddb->cursor[pipe];
11953
11954 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11955 continue;
11956
11957 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11958 "(expected (%u,%u), found (%u,%u))\n",
11959 pipe_name(pipe),
11960 sw_entry->start, sw_entry->end,
11961 hw_entry->start, hw_entry->end);
11962 }
11963 }
11964
11965 static void
11966 check_connector_state(struct drm_device *dev)
11967 {
11968 struct intel_connector *connector;
11969
11970 for_each_intel_connector(dev, connector) {
11971 /* This also checks the encoder/connector hw state with the
11972 * ->get_hw_state callbacks. */
11973 intel_connector_check_state(connector);
11974
11975 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11976 "connector's staged encoder doesn't match current encoder\n");
11977 }
11978 }
11979
11980 static void
11981 check_encoder_state(struct drm_device *dev)
11982 {
11983 struct intel_encoder *encoder;
11984 struct intel_connector *connector;
11985
11986 for_each_intel_encoder(dev, encoder) {
11987 bool enabled = false;
11988 bool active = false;
11989 enum pipe pipe, tracked_pipe;
11990
11991 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11992 encoder->base.base.id,
11993 encoder->base.name);
11994
11995 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11996 "encoder's stage crtc doesn't match current crtc\n");
11997 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11998 "encoder's active_connectors set, but no crtc\n");
11999
12000 for_each_intel_connector(dev, connector) {
12001 if (connector->base.encoder != &encoder->base)
12002 continue;
12003 enabled = true;
12004 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12005 active = true;
12006 }
12007 /*
12008 * for MST connectors if we unplug the connector is gone
12009 * away but the encoder is still connected to a crtc
12010 * until a modeset happens in response to the hotplug.
12011 */
12012 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12013 continue;
12014
12015 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12016 "encoder's enabled state mismatch "
12017 "(expected %i, found %i)\n",
12018 !!encoder->base.crtc, enabled);
12019 I915_STATE_WARN(active && !encoder->base.crtc,
12020 "active encoder with no crtc\n");
12021
12022 I915_STATE_WARN(encoder->connectors_active != active,
12023 "encoder's computed active state doesn't match tracked active state "
12024 "(expected %i, found %i)\n", active, encoder->connectors_active);
12025
12026 active = encoder->get_hw_state(encoder, &pipe);
12027 I915_STATE_WARN(active != encoder->connectors_active,
12028 "encoder's hw state doesn't match sw tracking "
12029 "(expected %i, found %i)\n",
12030 encoder->connectors_active, active);
12031
12032 if (!encoder->base.crtc)
12033 continue;
12034
12035 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12036 I915_STATE_WARN(active && pipe != tracked_pipe,
12037 "active encoder's pipe doesn't match"
12038 "(expected %i, found %i)\n",
12039 tracked_pipe, pipe);
12040
12041 }
12042 }
12043
12044 static void
12045 check_crtc_state(struct drm_device *dev)
12046 {
12047 struct drm_i915_private *dev_priv = dev->dev_private;
12048 struct intel_crtc *crtc;
12049 struct intel_encoder *encoder;
12050 struct intel_crtc_state pipe_config;
12051
12052 for_each_intel_crtc(dev, crtc) {
12053 bool enabled = false;
12054 bool active = false;
12055
12056 memset(&pipe_config, 0, sizeof(pipe_config));
12057
12058 DRM_DEBUG_KMS("[CRTC:%d]\n",
12059 crtc->base.base.id);
12060
12061 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12062 "active crtc, but not enabled in sw tracking\n");
12063
12064 for_each_intel_encoder(dev, encoder) {
12065 if (encoder->base.crtc != &crtc->base)
12066 continue;
12067 enabled = true;
12068 if (encoder->connectors_active)
12069 active = true;
12070 }
12071
12072 I915_STATE_WARN(active != crtc->active,
12073 "crtc's computed active state doesn't match tracked active state "
12074 "(expected %i, found %i)\n", active, crtc->active);
12075 I915_STATE_WARN(enabled != crtc->base.state->enable,
12076 "crtc's computed enabled state doesn't match tracked enabled state "
12077 "(expected %i, found %i)\n", enabled,
12078 crtc->base.state->enable);
12079
12080 active = dev_priv->display.get_pipe_config(crtc,
12081 &pipe_config);
12082
12083 /* hw state is inconsistent with the pipe quirk */
12084 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12085 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12086 active = crtc->active;
12087
12088 for_each_intel_encoder(dev, encoder) {
12089 enum pipe pipe;
12090 if (encoder->base.crtc != &crtc->base)
12091 continue;
12092 if (encoder->get_hw_state(encoder, &pipe))
12093 encoder->get_config(encoder, &pipe_config);
12094 }
12095
12096 I915_STATE_WARN(crtc->active != active,
12097 "crtc active state doesn't match with hw state "
12098 "(expected %i, found %i)\n", crtc->active, active);
12099
12100 if (active &&
12101 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12102 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12103 intel_dump_pipe_config(crtc, &pipe_config,
12104 "[hw state]");
12105 intel_dump_pipe_config(crtc, crtc->config,
12106 "[sw state]");
12107 }
12108 }
12109 }
12110
12111 static void
12112 check_shared_dpll_state(struct drm_device *dev)
12113 {
12114 struct drm_i915_private *dev_priv = dev->dev_private;
12115 struct intel_crtc *crtc;
12116 struct intel_dpll_hw_state dpll_hw_state;
12117 int i;
12118
12119 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12120 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12121 int enabled_crtcs = 0, active_crtcs = 0;
12122 bool active;
12123
12124 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12125
12126 DRM_DEBUG_KMS("%s\n", pll->name);
12127
12128 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12129
12130 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12131 "more active pll users than references: %i vs %i\n",
12132 pll->active, hweight32(pll->config.crtc_mask));
12133 I915_STATE_WARN(pll->active && !pll->on,
12134 "pll in active use but not on in sw tracking\n");
12135 I915_STATE_WARN(pll->on && !pll->active,
12136 "pll in on but not on in use in sw tracking\n");
12137 I915_STATE_WARN(pll->on != active,
12138 "pll on state mismatch (expected %i, found %i)\n",
12139 pll->on, active);
12140
12141 for_each_intel_crtc(dev, crtc) {
12142 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12143 enabled_crtcs++;
12144 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12145 active_crtcs++;
12146 }
12147 I915_STATE_WARN(pll->active != active_crtcs,
12148 "pll active crtcs mismatch (expected %i, found %i)\n",
12149 pll->active, active_crtcs);
12150 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12151 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12152 hweight32(pll->config.crtc_mask), enabled_crtcs);
12153
12154 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12155 sizeof(dpll_hw_state)),
12156 "pll hw state mismatch\n");
12157 }
12158 }
12159
12160 void
12161 intel_modeset_check_state(struct drm_device *dev)
12162 {
12163 check_wm_state(dev);
12164 check_connector_state(dev);
12165 check_encoder_state(dev);
12166 check_crtc_state(dev);
12167 check_shared_dpll_state(dev);
12168 }
12169
12170 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12171 int dotclock)
12172 {
12173 /*
12174 * FDI already provided one idea for the dotclock.
12175 * Yell if the encoder disagrees.
12176 */
12177 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12178 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12179 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12180 }
12181
12182 static void update_scanline_offset(struct intel_crtc *crtc)
12183 {
12184 struct drm_device *dev = crtc->base.dev;
12185
12186 /*
12187 * The scanline counter increments at the leading edge of hsync.
12188 *
12189 * On most platforms it starts counting from vtotal-1 on the
12190 * first active line. That means the scanline counter value is
12191 * always one less than what we would expect. Ie. just after
12192 * start of vblank, which also occurs at start of hsync (on the
12193 * last active line), the scanline counter will read vblank_start-1.
12194 *
12195 * On gen2 the scanline counter starts counting from 1 instead
12196 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12197 * to keep the value positive), instead of adding one.
12198 *
12199 * On HSW+ the behaviour of the scanline counter depends on the output
12200 * type. For DP ports it behaves like most other platforms, but on HDMI
12201 * there's an extra 1 line difference. So we need to add two instead of
12202 * one to the value.
12203 */
12204 if (IS_GEN2(dev)) {
12205 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12206 int vtotal;
12207
12208 vtotal = mode->crtc_vtotal;
12209 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12210 vtotal /= 2;
12211
12212 crtc->scanline_offset = vtotal - 1;
12213 } else if (HAS_DDI(dev) &&
12214 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12215 crtc->scanline_offset = 2;
12216 } else
12217 crtc->scanline_offset = 1;
12218 }
12219
12220 static struct intel_crtc_state *
12221 intel_modeset_compute_config(struct drm_crtc *crtc,
12222 struct drm_atomic_state *state)
12223 {
12224 struct intel_crtc_state *pipe_config;
12225 int ret = 0;
12226
12227 ret = drm_atomic_add_affected_connectors(state, crtc);
12228 if (ret)
12229 return ERR_PTR(ret);
12230
12231 ret = drm_atomic_helper_check_modeset(state->dev, state);
12232 if (ret)
12233 return ERR_PTR(ret);
12234
12235 /*
12236 * Note this needs changes when we start tracking multiple modes
12237 * and crtcs. At that point we'll need to compute the whole config
12238 * (i.e. one pipe_config for each crtc) rather than just the one
12239 * for this crtc.
12240 */
12241 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12242 if (IS_ERR(pipe_config))
12243 return pipe_config;
12244
12245 if (!pipe_config->base.enable)
12246 return pipe_config;
12247
12248 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12249 if (ret)
12250 return ERR_PTR(ret);
12251
12252 /* Check things that can only be changed through modeset */
12253 if (pipe_config->has_audio !=
12254 to_intel_crtc(crtc)->config->has_audio)
12255 pipe_config->base.mode_changed = true;
12256
12257 /*
12258 * Note we have an issue here with infoframes: current code
12259 * only updates them on the full mode set path per hw
12260 * requirements. So here we should be checking for any
12261 * required changes and forcing a mode set.
12262 */
12263
12264 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12265
12266 ret = drm_atomic_helper_check_planes(state->dev, state);
12267 if (ret)
12268 return ERR_PTR(ret);
12269
12270 return pipe_config;
12271 }
12272
12273 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12274 {
12275 struct drm_device *dev = state->dev;
12276 struct drm_i915_private *dev_priv = to_i915(dev);
12277 unsigned clear_pipes = 0;
12278 struct intel_crtc *intel_crtc;
12279 struct intel_crtc_state *intel_crtc_state;
12280 struct drm_crtc *crtc;
12281 struct drm_crtc_state *crtc_state;
12282 int ret = 0;
12283 int i;
12284
12285 if (!dev_priv->display.crtc_compute_clock)
12286 return 0;
12287
12288 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12289 intel_crtc = to_intel_crtc(crtc);
12290 intel_crtc_state = to_intel_crtc_state(crtc_state);
12291
12292 if (needs_modeset(crtc_state)) {
12293 clear_pipes |= 1 << intel_crtc->pipe;
12294 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12295 }
12296 }
12297
12298 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12299 if (ret)
12300 goto done;
12301
12302 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12303 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12304 continue;
12305
12306 intel_crtc = to_intel_crtc(crtc);
12307 intel_crtc_state = to_intel_crtc_state(crtc_state);
12308
12309 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12310 intel_crtc_state);
12311 if (ret) {
12312 intel_shared_dpll_abort_config(dev_priv);
12313 goto done;
12314 }
12315 }
12316
12317 done:
12318 return ret;
12319 }
12320
12321 /* Code that should eventually be part of atomic_check() */
12322 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12323 {
12324 struct drm_device *dev = state->dev;
12325 int ret;
12326
12327 /*
12328 * See if the config requires any additional preparation, e.g.
12329 * to adjust global state with pipes off. We need to do this
12330 * here so we can get the modeset_pipe updated config for the new
12331 * mode set on this crtc. For other crtcs we need to use the
12332 * adjusted_mode bits in the crtc directly.
12333 */
12334 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12335 ret = valleyview_modeset_global_pipes(state);
12336 if (ret)
12337 return ret;
12338 }
12339
12340 ret = __intel_set_mode_setup_plls(state);
12341 if (ret)
12342 return ret;
12343
12344 return 0;
12345 }
12346
12347 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12348 struct intel_crtc_state *pipe_config)
12349 {
12350 struct drm_device *dev = modeset_crtc->dev;
12351 struct drm_i915_private *dev_priv = dev->dev_private;
12352 struct drm_atomic_state *state = pipe_config->base.state;
12353 struct drm_crtc *crtc;
12354 struct drm_crtc_state *crtc_state;
12355 int ret = 0;
12356 int i;
12357
12358 ret = __intel_set_mode_checks(state);
12359 if (ret < 0)
12360 return ret;
12361
12362 ret = drm_atomic_helper_prepare_planes(dev, state);
12363 if (ret)
12364 return ret;
12365
12366 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12367 if (!needs_modeset(crtc_state))
12368 continue;
12369
12370 if (!crtc_state->enable) {
12371 intel_crtc_disable(crtc);
12372 } else if (crtc->state->enable) {
12373 intel_crtc_disable_planes(crtc);
12374 dev_priv->display.crtc_disable(crtc);
12375 }
12376 }
12377
12378 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12379 * to set it here already despite that we pass it down the callchain.
12380 *
12381 * Note we'll need to fix this up when we start tracking multiple
12382 * pipes; here we assume a single modeset_pipe and only track the
12383 * single crtc and mode.
12384 */
12385 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12386 modeset_crtc->mode = pipe_config->base.mode;
12387
12388 /*
12389 * Calculate and store various constants which
12390 * are later needed by vblank and swap-completion
12391 * timestamping. They are derived from true hwmode.
12392 */
12393 drm_calc_timestamping_constants(modeset_crtc,
12394 &pipe_config->base.adjusted_mode);
12395 }
12396
12397 /* Only after disabling all output pipelines that will be changed can we
12398 * update the the output configuration. */
12399 intel_modeset_update_state(state);
12400
12401 /* The state has been swaped above, so state actually contains the
12402 * old state now. */
12403
12404 modeset_update_crtc_power_domains(state);
12405
12406 drm_atomic_helper_commit_planes(dev, state);
12407
12408 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12409 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12410 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12411 continue;
12412
12413 update_scanline_offset(to_intel_crtc(crtc));
12414
12415 dev_priv->display.crtc_enable(crtc);
12416 intel_crtc_enable_planes(crtc);
12417 }
12418
12419 /* FIXME: add subpixel order */
12420
12421 drm_atomic_helper_cleanup_planes(dev, state);
12422
12423 drm_atomic_state_free(state);
12424
12425 return 0;
12426 }
12427
12428 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12429 struct intel_crtc_state *pipe_config)
12430 {
12431 int ret;
12432
12433 ret = __intel_set_mode(crtc, pipe_config);
12434
12435 if (ret == 0)
12436 intel_modeset_check_state(crtc->dev);
12437
12438 return ret;
12439 }
12440
12441 static int intel_set_mode(struct drm_crtc *crtc,
12442 struct drm_atomic_state *state)
12443 {
12444 struct intel_crtc_state *pipe_config;
12445 int ret = 0;
12446
12447 pipe_config = intel_modeset_compute_config(crtc, state);
12448 if (IS_ERR(pipe_config)) {
12449 ret = PTR_ERR(pipe_config);
12450 goto out;
12451 }
12452
12453 ret = intel_set_mode_with_config(crtc, pipe_config);
12454 if (ret)
12455 goto out;
12456
12457 out:
12458 return ret;
12459 }
12460
12461 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12462 {
12463 struct drm_device *dev = crtc->dev;
12464 struct drm_atomic_state *state;
12465 struct intel_crtc *intel_crtc;
12466 struct intel_encoder *encoder;
12467 struct intel_connector *connector;
12468 struct drm_connector_state *connector_state;
12469 struct intel_crtc_state *crtc_state;
12470 int ret;
12471
12472 state = drm_atomic_state_alloc(dev);
12473 if (!state) {
12474 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12475 crtc->base.id);
12476 return;
12477 }
12478
12479 state->acquire_ctx = dev->mode_config.acquire_ctx;
12480
12481 /* The force restore path in the HW readout code relies on the staged
12482 * config still keeping the user requested config while the actual
12483 * state has been overwritten by the configuration read from HW. We
12484 * need to copy the staged config to the atomic state, otherwise the
12485 * mode set will just reapply the state the HW is already in. */
12486 for_each_intel_encoder(dev, encoder) {
12487 if (&encoder->new_crtc->base != crtc)
12488 continue;
12489
12490 for_each_intel_connector(dev, connector) {
12491 if (connector->new_encoder != encoder)
12492 continue;
12493
12494 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12495 if (IS_ERR(connector_state)) {
12496 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12497 connector->base.base.id,
12498 connector->base.name,
12499 PTR_ERR(connector_state));
12500 continue;
12501 }
12502
12503 connector_state->crtc = crtc;
12504 connector_state->best_encoder = &encoder->base;
12505 }
12506 }
12507
12508 for_each_intel_crtc(dev, intel_crtc) {
12509 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12510 continue;
12511
12512 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12513 if (IS_ERR(crtc_state)) {
12514 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12515 intel_crtc->base.base.id,
12516 PTR_ERR(crtc_state));
12517 continue;
12518 }
12519
12520 crtc_state->base.active = crtc_state->base.enable =
12521 intel_crtc->new_enabled;
12522
12523 if (&intel_crtc->base == crtc)
12524 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12525 }
12526
12527 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12528 crtc->primary->fb, crtc->x, crtc->y);
12529
12530 ret = intel_set_mode(crtc, state);
12531 if (ret)
12532 drm_atomic_state_free(state);
12533 }
12534
12535 #undef for_each_intel_crtc_masked
12536
12537 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12538 struct drm_mode_set *set)
12539 {
12540 int ro;
12541
12542 for (ro = 0; ro < set->num_connectors; ro++)
12543 if (set->connectors[ro] == &connector->base)
12544 return true;
12545
12546 return false;
12547 }
12548
12549 static int
12550 intel_modeset_stage_output_state(struct drm_device *dev,
12551 struct drm_mode_set *set,
12552 struct drm_atomic_state *state)
12553 {
12554 struct intel_connector *connector;
12555 struct drm_connector *drm_connector;
12556 struct drm_connector_state *connector_state;
12557 struct drm_crtc *crtc;
12558 struct drm_crtc_state *crtc_state;
12559 int i, ret;
12560
12561 /* The upper layers ensure that we either disable a crtc or have a list
12562 * of connectors. For paranoia, double-check this. */
12563 WARN_ON(!set->fb && (set->num_connectors != 0));
12564 WARN_ON(set->fb && (set->num_connectors == 0));
12565
12566 for_each_intel_connector(dev, connector) {
12567 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12568
12569 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12570 continue;
12571
12572 connector_state =
12573 drm_atomic_get_connector_state(state, &connector->base);
12574 if (IS_ERR(connector_state))
12575 return PTR_ERR(connector_state);
12576
12577 if (in_mode_set) {
12578 int pipe = to_intel_crtc(set->crtc)->pipe;
12579 connector_state->best_encoder =
12580 &intel_find_encoder(connector, pipe)->base;
12581 }
12582
12583 if (connector->base.state->crtc != set->crtc)
12584 continue;
12585
12586 /* If we disable the crtc, disable all its connectors. Also, if
12587 * the connector is on the changing crtc but not on the new
12588 * connector list, disable it. */
12589 if (!set->fb || !in_mode_set) {
12590 connector_state->best_encoder = NULL;
12591
12592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12593 connector->base.base.id,
12594 connector->base.name);
12595 }
12596 }
12597 /* connector->new_encoder is now updated for all connectors. */
12598
12599 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12600 connector = to_intel_connector(drm_connector);
12601
12602 if (!connector_state->best_encoder) {
12603 ret = drm_atomic_set_crtc_for_connector(connector_state,
12604 NULL);
12605 if (ret)
12606 return ret;
12607
12608 continue;
12609 }
12610
12611 if (intel_connector_in_mode_set(connector, set)) {
12612 struct drm_crtc *crtc = connector->base.state->crtc;
12613
12614 /* If this connector was in a previous crtc, add it
12615 * to the state. We might need to disable it. */
12616 if (crtc) {
12617 crtc_state =
12618 drm_atomic_get_crtc_state(state, crtc);
12619 if (IS_ERR(crtc_state))
12620 return PTR_ERR(crtc_state);
12621 }
12622
12623 ret = drm_atomic_set_crtc_for_connector(connector_state,
12624 set->crtc);
12625 if (ret)
12626 return ret;
12627 }
12628
12629 /* Make sure the new CRTC will work with the encoder */
12630 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12631 connector_state->crtc)) {
12632 return -EINVAL;
12633 }
12634
12635 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12636 connector->base.base.id,
12637 connector->base.name,
12638 connector_state->crtc->base.id);
12639
12640 if (connector_state->best_encoder != &connector->encoder->base)
12641 connector->encoder =
12642 to_intel_encoder(connector_state->best_encoder);
12643 }
12644
12645 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12646 bool has_connectors;
12647
12648 ret = drm_atomic_add_affected_connectors(state, crtc);
12649 if (ret)
12650 return ret;
12651
12652 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12653 if (has_connectors != crtc_state->enable)
12654 crtc_state->enable =
12655 crtc_state->active = has_connectors;
12656 }
12657
12658 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12659 set->fb, set->x, set->y);
12660 if (ret)
12661 return ret;
12662
12663 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12664 if (IS_ERR(crtc_state))
12665 return PTR_ERR(crtc_state);
12666
12667 if (set->mode)
12668 drm_mode_copy(&crtc_state->mode, set->mode);
12669
12670 if (set->num_connectors)
12671 crtc_state->active = true;
12672
12673 return 0;
12674 }
12675
12676 static bool primary_plane_visible(struct drm_crtc *crtc)
12677 {
12678 struct intel_plane_state *plane_state =
12679 to_intel_plane_state(crtc->primary->state);
12680
12681 return plane_state->visible;
12682 }
12683
12684 static int intel_crtc_set_config(struct drm_mode_set *set)
12685 {
12686 struct drm_device *dev;
12687 struct drm_atomic_state *state = NULL;
12688 struct intel_crtc_state *pipe_config;
12689 bool primary_plane_was_visible;
12690 int ret;
12691
12692 BUG_ON(!set);
12693 BUG_ON(!set->crtc);
12694 BUG_ON(!set->crtc->helper_private);
12695
12696 /* Enforce sane interface api - has been abused by the fb helper. */
12697 BUG_ON(!set->mode && set->fb);
12698 BUG_ON(set->fb && set->num_connectors == 0);
12699
12700 if (set->fb) {
12701 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12702 set->crtc->base.id, set->fb->base.id,
12703 (int)set->num_connectors, set->x, set->y);
12704 } else {
12705 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12706 }
12707
12708 dev = set->crtc->dev;
12709
12710 state = drm_atomic_state_alloc(dev);
12711 if (!state)
12712 return -ENOMEM;
12713
12714 state->acquire_ctx = dev->mode_config.acquire_ctx;
12715
12716 ret = intel_modeset_stage_output_state(dev, set, state);
12717 if (ret)
12718 goto out;
12719
12720 pipe_config = intel_modeset_compute_config(set->crtc, state);
12721 if (IS_ERR(pipe_config)) {
12722 ret = PTR_ERR(pipe_config);
12723 goto out;
12724 }
12725
12726 intel_update_pipe_size(to_intel_crtc(set->crtc));
12727
12728 primary_plane_was_visible = primary_plane_visible(set->crtc);
12729
12730 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12731
12732 if (ret == 0 &&
12733 pipe_config->base.enable &&
12734 pipe_config->base.planes_changed &&
12735 !needs_modeset(&pipe_config->base)) {
12736 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12737
12738 /*
12739 * We need to make sure the primary plane is re-enabled if it
12740 * has previously been turned off.
12741 */
12742 if (ret == 0 && !primary_plane_was_visible &&
12743 primary_plane_visible(set->crtc)) {
12744 WARN_ON(!intel_crtc->active);
12745 intel_post_enable_primary(set->crtc);
12746 }
12747
12748 /*
12749 * In the fastboot case this may be our only check of the
12750 * state after boot. It would be better to only do it on
12751 * the first update, but we don't have a nice way of doing that
12752 * (and really, set_config isn't used much for high freq page
12753 * flipping, so increasing its cost here shouldn't be a big
12754 * deal).
12755 */
12756 if (i915.fastboot && ret == 0)
12757 intel_modeset_check_state(set->crtc->dev);
12758 }
12759
12760 if (ret) {
12761 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12762 set->crtc->base.id, ret);
12763 }
12764
12765 out:
12766 if (ret)
12767 drm_atomic_state_free(state);
12768 return ret;
12769 }
12770
12771 static const struct drm_crtc_funcs intel_crtc_funcs = {
12772 .gamma_set = intel_crtc_gamma_set,
12773 .set_config = intel_crtc_set_config,
12774 .destroy = intel_crtc_destroy,
12775 .page_flip = intel_crtc_page_flip,
12776 .atomic_duplicate_state = intel_crtc_duplicate_state,
12777 .atomic_destroy_state = intel_crtc_destroy_state,
12778 };
12779
12780 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12781 struct intel_shared_dpll *pll,
12782 struct intel_dpll_hw_state *hw_state)
12783 {
12784 uint32_t val;
12785
12786 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12787 return false;
12788
12789 val = I915_READ(PCH_DPLL(pll->id));
12790 hw_state->dpll = val;
12791 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12792 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12793
12794 return val & DPLL_VCO_ENABLE;
12795 }
12796
12797 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12798 struct intel_shared_dpll *pll)
12799 {
12800 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12801 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12802 }
12803
12804 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12805 struct intel_shared_dpll *pll)
12806 {
12807 /* PCH refclock must be enabled first */
12808 ibx_assert_pch_refclk_enabled(dev_priv);
12809
12810 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12811
12812 /* Wait for the clocks to stabilize. */
12813 POSTING_READ(PCH_DPLL(pll->id));
12814 udelay(150);
12815
12816 /* The pixel multiplier can only be updated once the
12817 * DPLL is enabled and the clocks are stable.
12818 *
12819 * So write it again.
12820 */
12821 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12822 POSTING_READ(PCH_DPLL(pll->id));
12823 udelay(200);
12824 }
12825
12826 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12827 struct intel_shared_dpll *pll)
12828 {
12829 struct drm_device *dev = dev_priv->dev;
12830 struct intel_crtc *crtc;
12831
12832 /* Make sure no transcoder isn't still depending on us. */
12833 for_each_intel_crtc(dev, crtc) {
12834 if (intel_crtc_to_shared_dpll(crtc) == pll)
12835 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12836 }
12837
12838 I915_WRITE(PCH_DPLL(pll->id), 0);
12839 POSTING_READ(PCH_DPLL(pll->id));
12840 udelay(200);
12841 }
12842
12843 static char *ibx_pch_dpll_names[] = {
12844 "PCH DPLL A",
12845 "PCH DPLL B",
12846 };
12847
12848 static void ibx_pch_dpll_init(struct drm_device *dev)
12849 {
12850 struct drm_i915_private *dev_priv = dev->dev_private;
12851 int i;
12852
12853 dev_priv->num_shared_dpll = 2;
12854
12855 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12856 dev_priv->shared_dplls[i].id = i;
12857 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12858 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12859 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12860 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12861 dev_priv->shared_dplls[i].get_hw_state =
12862 ibx_pch_dpll_get_hw_state;
12863 }
12864 }
12865
12866 static void intel_shared_dpll_init(struct drm_device *dev)
12867 {
12868 struct drm_i915_private *dev_priv = dev->dev_private;
12869
12870 if (HAS_DDI(dev))
12871 intel_ddi_pll_init(dev);
12872 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12873 ibx_pch_dpll_init(dev);
12874 else
12875 dev_priv->num_shared_dpll = 0;
12876
12877 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12878 }
12879
12880 /**
12881 * intel_wm_need_update - Check whether watermarks need updating
12882 * @plane: drm plane
12883 * @state: new plane state
12884 *
12885 * Check current plane state versus the new one to determine whether
12886 * watermarks need to be recalculated.
12887 *
12888 * Returns true or false.
12889 */
12890 bool intel_wm_need_update(struct drm_plane *plane,
12891 struct drm_plane_state *state)
12892 {
12893 /* Update watermarks on tiling changes. */
12894 if (!plane->state->fb || !state->fb ||
12895 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12896 plane->state->rotation != state->rotation)
12897 return true;
12898
12899 return false;
12900 }
12901
12902 /**
12903 * intel_prepare_plane_fb - Prepare fb for usage on plane
12904 * @plane: drm plane to prepare for
12905 * @fb: framebuffer to prepare for presentation
12906 *
12907 * Prepares a framebuffer for usage on a display plane. Generally this
12908 * involves pinning the underlying object and updating the frontbuffer tracking
12909 * bits. Some older platforms need special physical address handling for
12910 * cursor planes.
12911 *
12912 * Returns 0 on success, negative error code on failure.
12913 */
12914 int
12915 intel_prepare_plane_fb(struct drm_plane *plane,
12916 struct drm_framebuffer *fb,
12917 const struct drm_plane_state *new_state)
12918 {
12919 struct drm_device *dev = plane->dev;
12920 struct intel_plane *intel_plane = to_intel_plane(plane);
12921 enum pipe pipe = intel_plane->pipe;
12922 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12923 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12924 unsigned frontbuffer_bits = 0;
12925 int ret = 0;
12926
12927 if (!obj)
12928 return 0;
12929
12930 switch (plane->type) {
12931 case DRM_PLANE_TYPE_PRIMARY:
12932 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12933 break;
12934 case DRM_PLANE_TYPE_CURSOR:
12935 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12936 break;
12937 case DRM_PLANE_TYPE_OVERLAY:
12938 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12939 break;
12940 }
12941
12942 mutex_lock(&dev->struct_mutex);
12943
12944 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12945 INTEL_INFO(dev)->cursor_needs_physical) {
12946 int align = IS_I830(dev) ? 16 * 1024 : 256;
12947 ret = i915_gem_object_attach_phys(obj, align);
12948 if (ret)
12949 DRM_DEBUG_KMS("failed to attach phys object\n");
12950 } else {
12951 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12952 }
12953
12954 if (ret == 0)
12955 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12956
12957 mutex_unlock(&dev->struct_mutex);
12958
12959 return ret;
12960 }
12961
12962 /**
12963 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12964 * @plane: drm plane to clean up for
12965 * @fb: old framebuffer that was on plane
12966 *
12967 * Cleans up a framebuffer that has just been removed from a plane.
12968 */
12969 void
12970 intel_cleanup_plane_fb(struct drm_plane *plane,
12971 struct drm_framebuffer *fb,
12972 const struct drm_plane_state *old_state)
12973 {
12974 struct drm_device *dev = plane->dev;
12975 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12976
12977 if (WARN_ON(!obj))
12978 return;
12979
12980 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12981 !INTEL_INFO(dev)->cursor_needs_physical) {
12982 mutex_lock(&dev->struct_mutex);
12983 intel_unpin_fb_obj(fb, old_state);
12984 mutex_unlock(&dev->struct_mutex);
12985 }
12986 }
12987
12988 int
12989 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12990 {
12991 int max_scale;
12992 struct drm_device *dev;
12993 struct drm_i915_private *dev_priv;
12994 int crtc_clock, cdclk;
12995
12996 if (!intel_crtc || !crtc_state)
12997 return DRM_PLANE_HELPER_NO_SCALING;
12998
12999 dev = intel_crtc->base.dev;
13000 dev_priv = dev->dev_private;
13001 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13002 cdclk = dev_priv->display.get_display_clock_speed(dev);
13003
13004 if (!crtc_clock || !cdclk)
13005 return DRM_PLANE_HELPER_NO_SCALING;
13006
13007 /*
13008 * skl max scale is lower of:
13009 * close to 3 but not 3, -1 is for that purpose
13010 * or
13011 * cdclk/crtc_clock
13012 */
13013 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13014
13015 return max_scale;
13016 }
13017
13018 static int
13019 intel_check_primary_plane(struct drm_plane *plane,
13020 struct intel_plane_state *state)
13021 {
13022 struct drm_device *dev = plane->dev;
13023 struct drm_i915_private *dev_priv = dev->dev_private;
13024 struct drm_crtc *crtc = state->base.crtc;
13025 struct intel_crtc *intel_crtc;
13026 struct intel_crtc_state *crtc_state;
13027 struct drm_framebuffer *fb = state->base.fb;
13028 struct drm_rect *dest = &state->dst;
13029 struct drm_rect *src = &state->src;
13030 const struct drm_rect *clip = &state->clip;
13031 bool can_position = false;
13032 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13033 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13034 int ret;
13035
13036 crtc = crtc ? crtc : plane->crtc;
13037 intel_crtc = to_intel_crtc(crtc);
13038 crtc_state = state->base.state ?
13039 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13040
13041 if (INTEL_INFO(dev)->gen >= 9) {
13042 min_scale = 1;
13043 max_scale = skl_max_scale(intel_crtc, crtc_state);
13044 can_position = true;
13045 }
13046
13047 ret = drm_plane_helper_check_update(plane, crtc, fb,
13048 src, dest, clip,
13049 min_scale,
13050 max_scale,
13051 can_position, true,
13052 &state->visible);
13053 if (ret)
13054 return ret;
13055
13056 if (intel_crtc->active) {
13057 struct intel_plane_state *old_state =
13058 to_intel_plane_state(plane->state);
13059
13060 intel_crtc->atomic.wait_for_flips = true;
13061
13062 /*
13063 * FBC does not work on some platforms for rotated
13064 * planes, so disable it when rotation is not 0 and
13065 * update it when rotation is set back to 0.
13066 *
13067 * FIXME: This is redundant with the fbc update done in
13068 * the primary plane enable function except that that
13069 * one is done too late. We eventually need to unify
13070 * this.
13071 */
13072 if (state->visible &&
13073 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13074 dev_priv->fbc.crtc == intel_crtc &&
13075 state->base.rotation != BIT(DRM_ROTATE_0)) {
13076 intel_crtc->atomic.disable_fbc = true;
13077 }
13078
13079 if (state->visible && !old_state->visible) {
13080 /*
13081 * BDW signals flip done immediately if the plane
13082 * is disabled, even if the plane enable is already
13083 * armed to occur at the next vblank :(
13084 */
13085 if (IS_BROADWELL(dev))
13086 intel_crtc->atomic.wait_vblank = true;
13087 }
13088
13089 intel_crtc->atomic.fb_bits |=
13090 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13091
13092 intel_crtc->atomic.update_fbc = true;
13093
13094 if (intel_wm_need_update(plane, &state->base))
13095 intel_crtc->atomic.update_wm = true;
13096 }
13097
13098 if (INTEL_INFO(dev)->gen >= 9) {
13099 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13100 to_intel_plane(plane), state, 0);
13101 if (ret)
13102 return ret;
13103 }
13104
13105 return 0;
13106 }
13107
13108 static void
13109 intel_commit_primary_plane(struct drm_plane *plane,
13110 struct intel_plane_state *state)
13111 {
13112 struct drm_crtc *crtc = state->base.crtc;
13113 struct drm_framebuffer *fb = state->base.fb;
13114 struct drm_device *dev = plane->dev;
13115 struct drm_i915_private *dev_priv = dev->dev_private;
13116 struct intel_crtc *intel_crtc;
13117 struct drm_rect *src = &state->src;
13118
13119 crtc = crtc ? crtc : plane->crtc;
13120 intel_crtc = to_intel_crtc(crtc);
13121
13122 plane->fb = fb;
13123 crtc->x = src->x1 >> 16;
13124 crtc->y = src->y1 >> 16;
13125
13126 if (intel_crtc->active) {
13127 if (state->visible)
13128 /* FIXME: kill this fastboot hack */
13129 intel_update_pipe_size(intel_crtc);
13130
13131 dev_priv->display.update_primary_plane(crtc, plane->fb,
13132 crtc->x, crtc->y);
13133 }
13134 }
13135
13136 static void
13137 intel_disable_primary_plane(struct drm_plane *plane,
13138 struct drm_crtc *crtc,
13139 bool force)
13140 {
13141 struct drm_device *dev = plane->dev;
13142 struct drm_i915_private *dev_priv = dev->dev_private;
13143
13144 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13145 }
13146
13147 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13148 {
13149 struct drm_device *dev = crtc->dev;
13150 struct drm_i915_private *dev_priv = dev->dev_private;
13151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13152 struct intel_plane *intel_plane;
13153 struct drm_plane *p;
13154 unsigned fb_bits = 0;
13155
13156 /* Track fb's for any planes being disabled */
13157 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13158 intel_plane = to_intel_plane(p);
13159
13160 if (intel_crtc->atomic.disabled_planes &
13161 (1 << drm_plane_index(p))) {
13162 switch (p->type) {
13163 case DRM_PLANE_TYPE_PRIMARY:
13164 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13165 break;
13166 case DRM_PLANE_TYPE_CURSOR:
13167 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13168 break;
13169 case DRM_PLANE_TYPE_OVERLAY:
13170 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13171 break;
13172 }
13173
13174 mutex_lock(&dev->struct_mutex);
13175 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13176 mutex_unlock(&dev->struct_mutex);
13177 }
13178 }
13179
13180 if (intel_crtc->atomic.wait_for_flips)
13181 intel_crtc_wait_for_pending_flips(crtc);
13182
13183 if (intel_crtc->atomic.disable_fbc)
13184 intel_fbc_disable(dev);
13185
13186 if (intel_crtc->atomic.pre_disable_primary)
13187 intel_pre_disable_primary(crtc);
13188
13189 if (intel_crtc->atomic.update_wm)
13190 intel_update_watermarks(crtc);
13191
13192 intel_runtime_pm_get(dev_priv);
13193
13194 /* Perform vblank evasion around commit operation */
13195 if (intel_crtc->active)
13196 intel_crtc->atomic.evade =
13197 intel_pipe_update_start(intel_crtc,
13198 &intel_crtc->atomic.start_vbl_count);
13199 }
13200
13201 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13202 {
13203 struct drm_device *dev = crtc->dev;
13204 struct drm_i915_private *dev_priv = dev->dev_private;
13205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13206 struct drm_plane *p;
13207
13208 if (intel_crtc->atomic.evade)
13209 intel_pipe_update_end(intel_crtc,
13210 intel_crtc->atomic.start_vbl_count);
13211
13212 intel_runtime_pm_put(dev_priv);
13213
13214 if (intel_crtc->atomic.wait_vblank)
13215 intel_wait_for_vblank(dev, intel_crtc->pipe);
13216
13217 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13218
13219 if (intel_crtc->atomic.update_fbc) {
13220 mutex_lock(&dev->struct_mutex);
13221 intel_fbc_update(dev);
13222 mutex_unlock(&dev->struct_mutex);
13223 }
13224
13225 if (intel_crtc->atomic.post_enable_primary)
13226 intel_post_enable_primary(crtc);
13227
13228 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13229 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13230 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13231 false, false);
13232
13233 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13234 }
13235
13236 /**
13237 * intel_plane_destroy - destroy a plane
13238 * @plane: plane to destroy
13239 *
13240 * Common destruction function for all types of planes (primary, cursor,
13241 * sprite).
13242 */
13243 void intel_plane_destroy(struct drm_plane *plane)
13244 {
13245 struct intel_plane *intel_plane = to_intel_plane(plane);
13246 drm_plane_cleanup(plane);
13247 kfree(intel_plane);
13248 }
13249
13250 const struct drm_plane_funcs intel_plane_funcs = {
13251 .update_plane = drm_atomic_helper_update_plane,
13252 .disable_plane = drm_atomic_helper_disable_plane,
13253 .destroy = intel_plane_destroy,
13254 .set_property = drm_atomic_helper_plane_set_property,
13255 .atomic_get_property = intel_plane_atomic_get_property,
13256 .atomic_set_property = intel_plane_atomic_set_property,
13257 .atomic_duplicate_state = intel_plane_duplicate_state,
13258 .atomic_destroy_state = intel_plane_destroy_state,
13259
13260 };
13261
13262 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13263 int pipe)
13264 {
13265 struct intel_plane *primary;
13266 struct intel_plane_state *state;
13267 const uint32_t *intel_primary_formats;
13268 int num_formats;
13269
13270 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13271 if (primary == NULL)
13272 return NULL;
13273
13274 state = intel_create_plane_state(&primary->base);
13275 if (!state) {
13276 kfree(primary);
13277 return NULL;
13278 }
13279 primary->base.state = &state->base;
13280
13281 primary->can_scale = false;
13282 primary->max_downscale = 1;
13283 if (INTEL_INFO(dev)->gen >= 9) {
13284 primary->can_scale = true;
13285 state->scaler_id = -1;
13286 }
13287 primary->pipe = pipe;
13288 primary->plane = pipe;
13289 primary->check_plane = intel_check_primary_plane;
13290 primary->commit_plane = intel_commit_primary_plane;
13291 primary->disable_plane = intel_disable_primary_plane;
13292 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13293 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13294 primary->plane = !pipe;
13295
13296 if (INTEL_INFO(dev)->gen <= 3) {
13297 intel_primary_formats = i8xx_primary_formats;
13298 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13299 } else {
13300 intel_primary_formats = i965_primary_formats;
13301 num_formats = ARRAY_SIZE(i965_primary_formats);
13302 }
13303
13304 drm_universal_plane_init(dev, &primary->base, 0,
13305 &intel_plane_funcs,
13306 intel_primary_formats, num_formats,
13307 DRM_PLANE_TYPE_PRIMARY);
13308
13309 if (INTEL_INFO(dev)->gen >= 4)
13310 intel_create_rotation_property(dev, primary);
13311
13312 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13313
13314 return &primary->base;
13315 }
13316
13317 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13318 {
13319 if (!dev->mode_config.rotation_property) {
13320 unsigned long flags = BIT(DRM_ROTATE_0) |
13321 BIT(DRM_ROTATE_180);
13322
13323 if (INTEL_INFO(dev)->gen >= 9)
13324 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13325
13326 dev->mode_config.rotation_property =
13327 drm_mode_create_rotation_property(dev, flags);
13328 }
13329 if (dev->mode_config.rotation_property)
13330 drm_object_attach_property(&plane->base.base,
13331 dev->mode_config.rotation_property,
13332 plane->base.state->rotation);
13333 }
13334
13335 static int
13336 intel_check_cursor_plane(struct drm_plane *plane,
13337 struct intel_plane_state *state)
13338 {
13339 struct drm_crtc *crtc = state->base.crtc;
13340 struct drm_device *dev = plane->dev;
13341 struct drm_framebuffer *fb = state->base.fb;
13342 struct drm_rect *dest = &state->dst;
13343 struct drm_rect *src = &state->src;
13344 const struct drm_rect *clip = &state->clip;
13345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13346 struct intel_crtc *intel_crtc;
13347 unsigned stride;
13348 int ret;
13349
13350 crtc = crtc ? crtc : plane->crtc;
13351 intel_crtc = to_intel_crtc(crtc);
13352
13353 ret = drm_plane_helper_check_update(plane, crtc, fb,
13354 src, dest, clip,
13355 DRM_PLANE_HELPER_NO_SCALING,
13356 DRM_PLANE_HELPER_NO_SCALING,
13357 true, true, &state->visible);
13358 if (ret)
13359 return ret;
13360
13361
13362 /* if we want to turn off the cursor ignore width and height */
13363 if (!obj)
13364 goto finish;
13365
13366 /* Check for which cursor types we support */
13367 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13368 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13369 state->base.crtc_w, state->base.crtc_h);
13370 return -EINVAL;
13371 }
13372
13373 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13374 if (obj->base.size < stride * state->base.crtc_h) {
13375 DRM_DEBUG_KMS("buffer is too small\n");
13376 return -ENOMEM;
13377 }
13378
13379 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13380 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13381 ret = -EINVAL;
13382 }
13383
13384 finish:
13385 if (intel_crtc->active) {
13386 if (plane->state->crtc_w != state->base.crtc_w)
13387 intel_crtc->atomic.update_wm = true;
13388
13389 intel_crtc->atomic.fb_bits |=
13390 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13391 }
13392
13393 return ret;
13394 }
13395
13396 static void
13397 intel_disable_cursor_plane(struct drm_plane *plane,
13398 struct drm_crtc *crtc,
13399 bool force)
13400 {
13401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13402
13403 if (!force) {
13404 plane->fb = NULL;
13405 intel_crtc->cursor_bo = NULL;
13406 intel_crtc->cursor_addr = 0;
13407 }
13408
13409 intel_crtc_update_cursor(crtc, false);
13410 }
13411
13412 static void
13413 intel_commit_cursor_plane(struct drm_plane *plane,
13414 struct intel_plane_state *state)
13415 {
13416 struct drm_crtc *crtc = state->base.crtc;
13417 struct drm_device *dev = plane->dev;
13418 struct intel_crtc *intel_crtc;
13419 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13420 uint32_t addr;
13421
13422 crtc = crtc ? crtc : plane->crtc;
13423 intel_crtc = to_intel_crtc(crtc);
13424
13425 plane->fb = state->base.fb;
13426 crtc->cursor_x = state->base.crtc_x;
13427 crtc->cursor_y = state->base.crtc_y;
13428
13429 if (intel_crtc->cursor_bo == obj)
13430 goto update;
13431
13432 if (!obj)
13433 addr = 0;
13434 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13435 addr = i915_gem_obj_ggtt_offset(obj);
13436 else
13437 addr = obj->phys_handle->busaddr;
13438
13439 intel_crtc->cursor_addr = addr;
13440 intel_crtc->cursor_bo = obj;
13441 update:
13442
13443 if (intel_crtc->active)
13444 intel_crtc_update_cursor(crtc, state->visible);
13445 }
13446
13447 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13448 int pipe)
13449 {
13450 struct intel_plane *cursor;
13451 struct intel_plane_state *state;
13452
13453 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13454 if (cursor == NULL)
13455 return NULL;
13456
13457 state = intel_create_plane_state(&cursor->base);
13458 if (!state) {
13459 kfree(cursor);
13460 return NULL;
13461 }
13462 cursor->base.state = &state->base;
13463
13464 cursor->can_scale = false;
13465 cursor->max_downscale = 1;
13466 cursor->pipe = pipe;
13467 cursor->plane = pipe;
13468 cursor->check_plane = intel_check_cursor_plane;
13469 cursor->commit_plane = intel_commit_cursor_plane;
13470 cursor->disable_plane = intel_disable_cursor_plane;
13471
13472 drm_universal_plane_init(dev, &cursor->base, 0,
13473 &intel_plane_funcs,
13474 intel_cursor_formats,
13475 ARRAY_SIZE(intel_cursor_formats),
13476 DRM_PLANE_TYPE_CURSOR);
13477
13478 if (INTEL_INFO(dev)->gen >= 4) {
13479 if (!dev->mode_config.rotation_property)
13480 dev->mode_config.rotation_property =
13481 drm_mode_create_rotation_property(dev,
13482 BIT(DRM_ROTATE_0) |
13483 BIT(DRM_ROTATE_180));
13484 if (dev->mode_config.rotation_property)
13485 drm_object_attach_property(&cursor->base.base,
13486 dev->mode_config.rotation_property,
13487 state->base.rotation);
13488 }
13489
13490 if (INTEL_INFO(dev)->gen >=9)
13491 state->scaler_id = -1;
13492
13493 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13494
13495 return &cursor->base;
13496 }
13497
13498 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13499 struct intel_crtc_state *crtc_state)
13500 {
13501 int i;
13502 struct intel_scaler *intel_scaler;
13503 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13504
13505 for (i = 0; i < intel_crtc->num_scalers; i++) {
13506 intel_scaler = &scaler_state->scalers[i];
13507 intel_scaler->in_use = 0;
13508 intel_scaler->id = i;
13509
13510 intel_scaler->mode = PS_SCALER_MODE_DYN;
13511 }
13512
13513 scaler_state->scaler_id = -1;
13514 }
13515
13516 static void intel_crtc_init(struct drm_device *dev, int pipe)
13517 {
13518 struct drm_i915_private *dev_priv = dev->dev_private;
13519 struct intel_crtc *intel_crtc;
13520 struct intel_crtc_state *crtc_state = NULL;
13521 struct drm_plane *primary = NULL;
13522 struct drm_plane *cursor = NULL;
13523 int i, ret;
13524
13525 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13526 if (intel_crtc == NULL)
13527 return;
13528
13529 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13530 if (!crtc_state)
13531 goto fail;
13532 intel_crtc->config = crtc_state;
13533 intel_crtc->base.state = &crtc_state->base;
13534 crtc_state->base.crtc = &intel_crtc->base;
13535
13536 /* initialize shared scalers */
13537 if (INTEL_INFO(dev)->gen >= 9) {
13538 if (pipe == PIPE_C)
13539 intel_crtc->num_scalers = 1;
13540 else
13541 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13542
13543 skl_init_scalers(dev, intel_crtc, crtc_state);
13544 }
13545
13546 primary = intel_primary_plane_create(dev, pipe);
13547 if (!primary)
13548 goto fail;
13549
13550 cursor = intel_cursor_plane_create(dev, pipe);
13551 if (!cursor)
13552 goto fail;
13553
13554 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13555 cursor, &intel_crtc_funcs);
13556 if (ret)
13557 goto fail;
13558
13559 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13560 for (i = 0; i < 256; i++) {
13561 intel_crtc->lut_r[i] = i;
13562 intel_crtc->lut_g[i] = i;
13563 intel_crtc->lut_b[i] = i;
13564 }
13565
13566 /*
13567 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13568 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13569 */
13570 intel_crtc->pipe = pipe;
13571 intel_crtc->plane = pipe;
13572 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13573 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13574 intel_crtc->plane = !pipe;
13575 }
13576
13577 intel_crtc->cursor_base = ~0;
13578 intel_crtc->cursor_cntl = ~0;
13579 intel_crtc->cursor_size = ~0;
13580
13581 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13582 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13583 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13584 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13585
13586 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13587
13588 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13589 return;
13590
13591 fail:
13592 if (primary)
13593 drm_plane_cleanup(primary);
13594 if (cursor)
13595 drm_plane_cleanup(cursor);
13596 kfree(crtc_state);
13597 kfree(intel_crtc);
13598 }
13599
13600 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13601 {
13602 struct drm_encoder *encoder = connector->base.encoder;
13603 struct drm_device *dev = connector->base.dev;
13604
13605 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13606
13607 if (!encoder || WARN_ON(!encoder->crtc))
13608 return INVALID_PIPE;
13609
13610 return to_intel_crtc(encoder->crtc)->pipe;
13611 }
13612
13613 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13614 struct drm_file *file)
13615 {
13616 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13617 struct drm_crtc *drmmode_crtc;
13618 struct intel_crtc *crtc;
13619
13620 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13621
13622 if (!drmmode_crtc) {
13623 DRM_ERROR("no such CRTC id\n");
13624 return -ENOENT;
13625 }
13626
13627 crtc = to_intel_crtc(drmmode_crtc);
13628 pipe_from_crtc_id->pipe = crtc->pipe;
13629
13630 return 0;
13631 }
13632
13633 static int intel_encoder_clones(struct intel_encoder *encoder)
13634 {
13635 struct drm_device *dev = encoder->base.dev;
13636 struct intel_encoder *source_encoder;
13637 int index_mask = 0;
13638 int entry = 0;
13639
13640 for_each_intel_encoder(dev, source_encoder) {
13641 if (encoders_cloneable(encoder, source_encoder))
13642 index_mask |= (1 << entry);
13643
13644 entry++;
13645 }
13646
13647 return index_mask;
13648 }
13649
13650 static bool has_edp_a(struct drm_device *dev)
13651 {
13652 struct drm_i915_private *dev_priv = dev->dev_private;
13653
13654 if (!IS_MOBILE(dev))
13655 return false;
13656
13657 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13658 return false;
13659
13660 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13661 return false;
13662
13663 return true;
13664 }
13665
13666 static bool intel_crt_present(struct drm_device *dev)
13667 {
13668 struct drm_i915_private *dev_priv = dev->dev_private;
13669
13670 if (INTEL_INFO(dev)->gen >= 9)
13671 return false;
13672
13673 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13674 return false;
13675
13676 if (IS_CHERRYVIEW(dev))
13677 return false;
13678
13679 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13680 return false;
13681
13682 return true;
13683 }
13684
13685 static void intel_setup_outputs(struct drm_device *dev)
13686 {
13687 struct drm_i915_private *dev_priv = dev->dev_private;
13688 struct intel_encoder *encoder;
13689 bool dpd_is_edp = false;
13690
13691 intel_lvds_init(dev);
13692
13693 if (intel_crt_present(dev))
13694 intel_crt_init(dev);
13695
13696 if (IS_BROXTON(dev)) {
13697 /*
13698 * FIXME: Broxton doesn't support port detection via the
13699 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13700 * detect the ports.
13701 */
13702 intel_ddi_init(dev, PORT_A);
13703 intel_ddi_init(dev, PORT_B);
13704 intel_ddi_init(dev, PORT_C);
13705 } else if (HAS_DDI(dev)) {
13706 int found;
13707
13708 /*
13709 * Haswell uses DDI functions to detect digital outputs.
13710 * On SKL pre-D0 the strap isn't connected, so we assume
13711 * it's there.
13712 */
13713 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13714 /* WaIgnoreDDIAStrap: skl */
13715 if (found ||
13716 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13717 intel_ddi_init(dev, PORT_A);
13718
13719 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13720 * register */
13721 found = I915_READ(SFUSE_STRAP);
13722
13723 if (found & SFUSE_STRAP_DDIB_DETECTED)
13724 intel_ddi_init(dev, PORT_B);
13725 if (found & SFUSE_STRAP_DDIC_DETECTED)
13726 intel_ddi_init(dev, PORT_C);
13727 if (found & SFUSE_STRAP_DDID_DETECTED)
13728 intel_ddi_init(dev, PORT_D);
13729 } else if (HAS_PCH_SPLIT(dev)) {
13730 int found;
13731 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13732
13733 if (has_edp_a(dev))
13734 intel_dp_init(dev, DP_A, PORT_A);
13735
13736 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13737 /* PCH SDVOB multiplex with HDMIB */
13738 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13739 if (!found)
13740 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13741 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13742 intel_dp_init(dev, PCH_DP_B, PORT_B);
13743 }
13744
13745 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13746 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13747
13748 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13749 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13750
13751 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13752 intel_dp_init(dev, PCH_DP_C, PORT_C);
13753
13754 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13755 intel_dp_init(dev, PCH_DP_D, PORT_D);
13756 } else if (IS_VALLEYVIEW(dev)) {
13757 /*
13758 * The DP_DETECTED bit is the latched state of the DDC
13759 * SDA pin at boot. However since eDP doesn't require DDC
13760 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13761 * eDP ports may have been muxed to an alternate function.
13762 * Thus we can't rely on the DP_DETECTED bit alone to detect
13763 * eDP ports. Consult the VBT as well as DP_DETECTED to
13764 * detect eDP ports.
13765 */
13766 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13767 !intel_dp_is_edp(dev, PORT_B))
13768 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13769 PORT_B);
13770 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13771 intel_dp_is_edp(dev, PORT_B))
13772 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13773
13774 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13775 !intel_dp_is_edp(dev, PORT_C))
13776 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13777 PORT_C);
13778 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13779 intel_dp_is_edp(dev, PORT_C))
13780 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13781
13782 if (IS_CHERRYVIEW(dev)) {
13783 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13784 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13785 PORT_D);
13786 /* eDP not supported on port D, so don't check VBT */
13787 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13788 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13789 }
13790
13791 intel_dsi_init(dev);
13792 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13793 bool found = false;
13794
13795 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13796 DRM_DEBUG_KMS("probing SDVOB\n");
13797 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13798 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13799 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13800 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13801 }
13802
13803 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13804 intel_dp_init(dev, DP_B, PORT_B);
13805 }
13806
13807 /* Before G4X SDVOC doesn't have its own detect register */
13808
13809 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13810 DRM_DEBUG_KMS("probing SDVOC\n");
13811 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13812 }
13813
13814 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13815
13816 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13817 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13818 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13819 }
13820 if (SUPPORTS_INTEGRATED_DP(dev))
13821 intel_dp_init(dev, DP_C, PORT_C);
13822 }
13823
13824 if (SUPPORTS_INTEGRATED_DP(dev) &&
13825 (I915_READ(DP_D) & DP_DETECTED))
13826 intel_dp_init(dev, DP_D, PORT_D);
13827 } else if (IS_GEN2(dev))
13828 intel_dvo_init(dev);
13829
13830 if (SUPPORTS_TV(dev))
13831 intel_tv_init(dev);
13832
13833 intel_psr_init(dev);
13834
13835 for_each_intel_encoder(dev, encoder) {
13836 encoder->base.possible_crtcs = encoder->crtc_mask;
13837 encoder->base.possible_clones =
13838 intel_encoder_clones(encoder);
13839 }
13840
13841 intel_init_pch_refclk(dev);
13842
13843 drm_helper_move_panel_connectors_to_head(dev);
13844 }
13845
13846 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13847 {
13848 struct drm_device *dev = fb->dev;
13849 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13850
13851 drm_framebuffer_cleanup(fb);
13852 mutex_lock(&dev->struct_mutex);
13853 WARN_ON(!intel_fb->obj->framebuffer_references--);
13854 drm_gem_object_unreference(&intel_fb->obj->base);
13855 mutex_unlock(&dev->struct_mutex);
13856 kfree(intel_fb);
13857 }
13858
13859 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13860 struct drm_file *file,
13861 unsigned int *handle)
13862 {
13863 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13864 struct drm_i915_gem_object *obj = intel_fb->obj;
13865
13866 return drm_gem_handle_create(file, &obj->base, handle);
13867 }
13868
13869 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13870 .destroy = intel_user_framebuffer_destroy,
13871 .create_handle = intel_user_framebuffer_create_handle,
13872 };
13873
13874 static
13875 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13876 uint32_t pixel_format)
13877 {
13878 u32 gen = INTEL_INFO(dev)->gen;
13879
13880 if (gen >= 9) {
13881 /* "The stride in bytes must not exceed the of the size of 8K
13882 * pixels and 32K bytes."
13883 */
13884 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13885 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13886 return 32*1024;
13887 } else if (gen >= 4) {
13888 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13889 return 16*1024;
13890 else
13891 return 32*1024;
13892 } else if (gen >= 3) {
13893 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13894 return 8*1024;
13895 else
13896 return 16*1024;
13897 } else {
13898 /* XXX DSPC is limited to 4k tiled */
13899 return 8*1024;
13900 }
13901 }
13902
13903 static int intel_framebuffer_init(struct drm_device *dev,
13904 struct intel_framebuffer *intel_fb,
13905 struct drm_mode_fb_cmd2 *mode_cmd,
13906 struct drm_i915_gem_object *obj)
13907 {
13908 unsigned int aligned_height;
13909 int ret;
13910 u32 pitch_limit, stride_alignment;
13911
13912 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13913
13914 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13915 /* Enforce that fb modifier and tiling mode match, but only for
13916 * X-tiled. This is needed for FBC. */
13917 if (!!(obj->tiling_mode == I915_TILING_X) !=
13918 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13919 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13920 return -EINVAL;
13921 }
13922 } else {
13923 if (obj->tiling_mode == I915_TILING_X)
13924 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13925 else if (obj->tiling_mode == I915_TILING_Y) {
13926 DRM_DEBUG("No Y tiling for legacy addfb\n");
13927 return -EINVAL;
13928 }
13929 }
13930
13931 /* Passed in modifier sanity checking. */
13932 switch (mode_cmd->modifier[0]) {
13933 case I915_FORMAT_MOD_Y_TILED:
13934 case I915_FORMAT_MOD_Yf_TILED:
13935 if (INTEL_INFO(dev)->gen < 9) {
13936 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13937 mode_cmd->modifier[0]);
13938 return -EINVAL;
13939 }
13940 case DRM_FORMAT_MOD_NONE:
13941 case I915_FORMAT_MOD_X_TILED:
13942 break;
13943 default:
13944 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13945 mode_cmd->modifier[0]);
13946 return -EINVAL;
13947 }
13948
13949 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13950 mode_cmd->pixel_format);
13951 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13952 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13953 mode_cmd->pitches[0], stride_alignment);
13954 return -EINVAL;
13955 }
13956
13957 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13958 mode_cmd->pixel_format);
13959 if (mode_cmd->pitches[0] > pitch_limit) {
13960 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13961 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13962 "tiled" : "linear",
13963 mode_cmd->pitches[0], pitch_limit);
13964 return -EINVAL;
13965 }
13966
13967 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13968 mode_cmd->pitches[0] != obj->stride) {
13969 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13970 mode_cmd->pitches[0], obj->stride);
13971 return -EINVAL;
13972 }
13973
13974 /* Reject formats not supported by any plane early. */
13975 switch (mode_cmd->pixel_format) {
13976 case DRM_FORMAT_C8:
13977 case DRM_FORMAT_RGB565:
13978 case DRM_FORMAT_XRGB8888:
13979 case DRM_FORMAT_ARGB8888:
13980 break;
13981 case DRM_FORMAT_XRGB1555:
13982 if (INTEL_INFO(dev)->gen > 3) {
13983 DRM_DEBUG("unsupported pixel format: %s\n",
13984 drm_get_format_name(mode_cmd->pixel_format));
13985 return -EINVAL;
13986 }
13987 break;
13988 case DRM_FORMAT_XBGR8888:
13989 case DRM_FORMAT_ABGR8888:
13990 case DRM_FORMAT_XRGB2101010:
13991 case DRM_FORMAT_XBGR2101010:
13992 if (INTEL_INFO(dev)->gen < 4) {
13993 DRM_DEBUG("unsupported pixel format: %s\n",
13994 drm_get_format_name(mode_cmd->pixel_format));
13995 return -EINVAL;
13996 }
13997 break;
13998 case DRM_FORMAT_ABGR2101010:
13999 if (!IS_VALLEYVIEW(dev)) {
14000 DRM_DEBUG("unsupported pixel format: %s\n",
14001 drm_get_format_name(mode_cmd->pixel_format));
14002 return -EINVAL;
14003 }
14004 break;
14005 case DRM_FORMAT_YUYV:
14006 case DRM_FORMAT_UYVY:
14007 case DRM_FORMAT_YVYU:
14008 case DRM_FORMAT_VYUY:
14009 if (INTEL_INFO(dev)->gen < 5) {
14010 DRM_DEBUG("unsupported pixel format: %s\n",
14011 drm_get_format_name(mode_cmd->pixel_format));
14012 return -EINVAL;
14013 }
14014 break;
14015 default:
14016 DRM_DEBUG("unsupported pixel format: %s\n",
14017 drm_get_format_name(mode_cmd->pixel_format));
14018 return -EINVAL;
14019 }
14020
14021 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14022 if (mode_cmd->offsets[0] != 0)
14023 return -EINVAL;
14024
14025 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14026 mode_cmd->pixel_format,
14027 mode_cmd->modifier[0]);
14028 /* FIXME drm helper for size checks (especially planar formats)? */
14029 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14030 return -EINVAL;
14031
14032 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14033 intel_fb->obj = obj;
14034 intel_fb->obj->framebuffer_references++;
14035
14036 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14037 if (ret) {
14038 DRM_ERROR("framebuffer init failed %d\n", ret);
14039 return ret;
14040 }
14041
14042 return 0;
14043 }
14044
14045 static struct drm_framebuffer *
14046 intel_user_framebuffer_create(struct drm_device *dev,
14047 struct drm_file *filp,
14048 struct drm_mode_fb_cmd2 *mode_cmd)
14049 {
14050 struct drm_i915_gem_object *obj;
14051
14052 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14053 mode_cmd->handles[0]));
14054 if (&obj->base == NULL)
14055 return ERR_PTR(-ENOENT);
14056
14057 return intel_framebuffer_create(dev, mode_cmd, obj);
14058 }
14059
14060 #ifndef CONFIG_DRM_I915_FBDEV
14061 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14062 {
14063 }
14064 #endif
14065
14066 static const struct drm_mode_config_funcs intel_mode_funcs = {
14067 .fb_create = intel_user_framebuffer_create,
14068 .output_poll_changed = intel_fbdev_output_poll_changed,
14069 .atomic_check = intel_atomic_check,
14070 .atomic_commit = intel_atomic_commit,
14071 };
14072
14073 /* Set up chip specific display functions */
14074 static void intel_init_display(struct drm_device *dev)
14075 {
14076 struct drm_i915_private *dev_priv = dev->dev_private;
14077
14078 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14079 dev_priv->display.find_dpll = g4x_find_best_dpll;
14080 else if (IS_CHERRYVIEW(dev))
14081 dev_priv->display.find_dpll = chv_find_best_dpll;
14082 else if (IS_VALLEYVIEW(dev))
14083 dev_priv->display.find_dpll = vlv_find_best_dpll;
14084 else if (IS_PINEVIEW(dev))
14085 dev_priv->display.find_dpll = pnv_find_best_dpll;
14086 else
14087 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14088
14089 if (INTEL_INFO(dev)->gen >= 9) {
14090 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14091 dev_priv->display.get_initial_plane_config =
14092 skylake_get_initial_plane_config;
14093 dev_priv->display.crtc_compute_clock =
14094 haswell_crtc_compute_clock;
14095 dev_priv->display.crtc_enable = haswell_crtc_enable;
14096 dev_priv->display.crtc_disable = haswell_crtc_disable;
14097 dev_priv->display.off = ironlake_crtc_off;
14098 dev_priv->display.update_primary_plane =
14099 skylake_update_primary_plane;
14100 } else if (HAS_DDI(dev)) {
14101 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14102 dev_priv->display.get_initial_plane_config =
14103 ironlake_get_initial_plane_config;
14104 dev_priv->display.crtc_compute_clock =
14105 haswell_crtc_compute_clock;
14106 dev_priv->display.crtc_enable = haswell_crtc_enable;
14107 dev_priv->display.crtc_disable = haswell_crtc_disable;
14108 dev_priv->display.off = ironlake_crtc_off;
14109 dev_priv->display.update_primary_plane =
14110 ironlake_update_primary_plane;
14111 } else if (HAS_PCH_SPLIT(dev)) {
14112 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14113 dev_priv->display.get_initial_plane_config =
14114 ironlake_get_initial_plane_config;
14115 dev_priv->display.crtc_compute_clock =
14116 ironlake_crtc_compute_clock;
14117 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14118 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14119 dev_priv->display.off = ironlake_crtc_off;
14120 dev_priv->display.update_primary_plane =
14121 ironlake_update_primary_plane;
14122 } else if (IS_VALLEYVIEW(dev)) {
14123 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14124 dev_priv->display.get_initial_plane_config =
14125 i9xx_get_initial_plane_config;
14126 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14127 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14128 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14129 dev_priv->display.off = i9xx_crtc_off;
14130 dev_priv->display.update_primary_plane =
14131 i9xx_update_primary_plane;
14132 } else {
14133 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14134 dev_priv->display.get_initial_plane_config =
14135 i9xx_get_initial_plane_config;
14136 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14137 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14138 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14139 dev_priv->display.off = i9xx_crtc_off;
14140 dev_priv->display.update_primary_plane =
14141 i9xx_update_primary_plane;
14142 }
14143
14144 /* Returns the core display clock speed */
14145 if (IS_SKYLAKE(dev))
14146 dev_priv->display.get_display_clock_speed =
14147 skylake_get_display_clock_speed;
14148 else if (IS_BROADWELL(dev))
14149 dev_priv->display.get_display_clock_speed =
14150 broadwell_get_display_clock_speed;
14151 else if (IS_HASWELL(dev))
14152 dev_priv->display.get_display_clock_speed =
14153 haswell_get_display_clock_speed;
14154 else if (IS_VALLEYVIEW(dev))
14155 dev_priv->display.get_display_clock_speed =
14156 valleyview_get_display_clock_speed;
14157 else if (IS_GEN5(dev))
14158 dev_priv->display.get_display_clock_speed =
14159 ilk_get_display_clock_speed;
14160 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14161 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14162 dev_priv->display.get_display_clock_speed =
14163 i945_get_display_clock_speed;
14164 else if (IS_I915G(dev))
14165 dev_priv->display.get_display_clock_speed =
14166 i915_get_display_clock_speed;
14167 else if (IS_I945GM(dev) || IS_845G(dev))
14168 dev_priv->display.get_display_clock_speed =
14169 i9xx_misc_get_display_clock_speed;
14170 else if (IS_PINEVIEW(dev))
14171 dev_priv->display.get_display_clock_speed =
14172 pnv_get_display_clock_speed;
14173 else if (IS_I915GM(dev))
14174 dev_priv->display.get_display_clock_speed =
14175 i915gm_get_display_clock_speed;
14176 else if (IS_I865G(dev))
14177 dev_priv->display.get_display_clock_speed =
14178 i865_get_display_clock_speed;
14179 else if (IS_I85X(dev))
14180 dev_priv->display.get_display_clock_speed =
14181 i855_get_display_clock_speed;
14182 else /* 852, 830 */
14183 dev_priv->display.get_display_clock_speed =
14184 i830_get_display_clock_speed;
14185
14186 if (IS_GEN5(dev)) {
14187 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14188 } else if (IS_GEN6(dev)) {
14189 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14190 } else if (IS_IVYBRIDGE(dev)) {
14191 /* FIXME: detect B0+ stepping and use auto training */
14192 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14193 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14194 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14195 } else if (IS_VALLEYVIEW(dev)) {
14196 dev_priv->display.modeset_global_resources =
14197 valleyview_modeset_global_resources;
14198 } else if (IS_BROXTON(dev)) {
14199 dev_priv->display.modeset_global_resources =
14200 broxton_modeset_global_resources;
14201 }
14202
14203 switch (INTEL_INFO(dev)->gen) {
14204 case 2:
14205 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14206 break;
14207
14208 case 3:
14209 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14210 break;
14211
14212 case 4:
14213 case 5:
14214 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14215 break;
14216
14217 case 6:
14218 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14219 break;
14220 case 7:
14221 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14222 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14223 break;
14224 case 9:
14225 /* Drop through - unsupported since execlist only. */
14226 default:
14227 /* Default just returns -ENODEV to indicate unsupported */
14228 dev_priv->display.queue_flip = intel_default_queue_flip;
14229 }
14230
14231 intel_panel_init_backlight_funcs(dev);
14232
14233 mutex_init(&dev_priv->pps_mutex);
14234 }
14235
14236 /*
14237 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14238 * resume, or other times. This quirk makes sure that's the case for
14239 * affected systems.
14240 */
14241 static void quirk_pipea_force(struct drm_device *dev)
14242 {
14243 struct drm_i915_private *dev_priv = dev->dev_private;
14244
14245 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14246 DRM_INFO("applying pipe a force quirk\n");
14247 }
14248
14249 static void quirk_pipeb_force(struct drm_device *dev)
14250 {
14251 struct drm_i915_private *dev_priv = dev->dev_private;
14252
14253 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14254 DRM_INFO("applying pipe b force quirk\n");
14255 }
14256
14257 /*
14258 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14259 */
14260 static void quirk_ssc_force_disable(struct drm_device *dev)
14261 {
14262 struct drm_i915_private *dev_priv = dev->dev_private;
14263 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14264 DRM_INFO("applying lvds SSC disable quirk\n");
14265 }
14266
14267 /*
14268 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14269 * brightness value
14270 */
14271 static void quirk_invert_brightness(struct drm_device *dev)
14272 {
14273 struct drm_i915_private *dev_priv = dev->dev_private;
14274 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14275 DRM_INFO("applying inverted panel brightness quirk\n");
14276 }
14277
14278 /* Some VBT's incorrectly indicate no backlight is present */
14279 static void quirk_backlight_present(struct drm_device *dev)
14280 {
14281 struct drm_i915_private *dev_priv = dev->dev_private;
14282 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14283 DRM_INFO("applying backlight present quirk\n");
14284 }
14285
14286 struct intel_quirk {
14287 int device;
14288 int subsystem_vendor;
14289 int subsystem_device;
14290 void (*hook)(struct drm_device *dev);
14291 };
14292
14293 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14294 struct intel_dmi_quirk {
14295 void (*hook)(struct drm_device *dev);
14296 const struct dmi_system_id (*dmi_id_list)[];
14297 };
14298
14299 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14300 {
14301 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14302 return 1;
14303 }
14304
14305 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14306 {
14307 .dmi_id_list = &(const struct dmi_system_id[]) {
14308 {
14309 .callback = intel_dmi_reverse_brightness,
14310 .ident = "NCR Corporation",
14311 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14312 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14313 },
14314 },
14315 { } /* terminating entry */
14316 },
14317 .hook = quirk_invert_brightness,
14318 },
14319 };
14320
14321 static struct intel_quirk intel_quirks[] = {
14322 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14323 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14324
14325 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14326 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14327
14328 /* 830 needs to leave pipe A & dpll A up */
14329 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14330
14331 /* 830 needs to leave pipe B & dpll B up */
14332 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14333
14334 /* Lenovo U160 cannot use SSC on LVDS */
14335 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14336
14337 /* Sony Vaio Y cannot use SSC on LVDS */
14338 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14339
14340 /* Acer Aspire 5734Z must invert backlight brightness */
14341 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14342
14343 /* Acer/eMachines G725 */
14344 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14345
14346 /* Acer/eMachines e725 */
14347 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14348
14349 /* Acer/Packard Bell NCL20 */
14350 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14351
14352 /* Acer Aspire 4736Z */
14353 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14354
14355 /* Acer Aspire 5336 */
14356 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14357
14358 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14359 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14360
14361 /* Acer C720 Chromebook (Core i3 4005U) */
14362 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14363
14364 /* Apple Macbook 2,1 (Core 2 T7400) */
14365 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14366
14367 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14368 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14369
14370 /* HP Chromebook 14 (Celeron 2955U) */
14371 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14372
14373 /* Dell Chromebook 11 */
14374 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14375 };
14376
14377 static void intel_init_quirks(struct drm_device *dev)
14378 {
14379 struct pci_dev *d = dev->pdev;
14380 int i;
14381
14382 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14383 struct intel_quirk *q = &intel_quirks[i];
14384
14385 if (d->device == q->device &&
14386 (d->subsystem_vendor == q->subsystem_vendor ||
14387 q->subsystem_vendor == PCI_ANY_ID) &&
14388 (d->subsystem_device == q->subsystem_device ||
14389 q->subsystem_device == PCI_ANY_ID))
14390 q->hook(dev);
14391 }
14392 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14393 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14394 intel_dmi_quirks[i].hook(dev);
14395 }
14396 }
14397
14398 /* Disable the VGA plane that we never use */
14399 static void i915_disable_vga(struct drm_device *dev)
14400 {
14401 struct drm_i915_private *dev_priv = dev->dev_private;
14402 u8 sr1;
14403 u32 vga_reg = i915_vgacntrl_reg(dev);
14404
14405 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14406 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14407 outb(SR01, VGA_SR_INDEX);
14408 sr1 = inb(VGA_SR_DATA);
14409 outb(sr1 | 1<<5, VGA_SR_DATA);
14410 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14411 udelay(300);
14412
14413 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14414 POSTING_READ(vga_reg);
14415 }
14416
14417 void intel_modeset_init_hw(struct drm_device *dev)
14418 {
14419 intel_prepare_ddi(dev);
14420
14421 if (IS_VALLEYVIEW(dev))
14422 vlv_update_cdclk(dev);
14423
14424 intel_init_clock_gating(dev);
14425
14426 intel_enable_gt_powersave(dev);
14427 }
14428
14429 void intel_modeset_init(struct drm_device *dev)
14430 {
14431 struct drm_i915_private *dev_priv = dev->dev_private;
14432 int sprite, ret;
14433 enum pipe pipe;
14434 struct intel_crtc *crtc;
14435
14436 drm_mode_config_init(dev);
14437
14438 dev->mode_config.min_width = 0;
14439 dev->mode_config.min_height = 0;
14440
14441 dev->mode_config.preferred_depth = 24;
14442 dev->mode_config.prefer_shadow = 1;
14443
14444 dev->mode_config.allow_fb_modifiers = true;
14445
14446 dev->mode_config.funcs = &intel_mode_funcs;
14447
14448 intel_init_quirks(dev);
14449
14450 intel_init_pm(dev);
14451
14452 if (INTEL_INFO(dev)->num_pipes == 0)
14453 return;
14454
14455 intel_init_display(dev);
14456 intel_init_audio(dev);
14457
14458 if (IS_GEN2(dev)) {
14459 dev->mode_config.max_width = 2048;
14460 dev->mode_config.max_height = 2048;
14461 } else if (IS_GEN3(dev)) {
14462 dev->mode_config.max_width = 4096;
14463 dev->mode_config.max_height = 4096;
14464 } else {
14465 dev->mode_config.max_width = 8192;
14466 dev->mode_config.max_height = 8192;
14467 }
14468
14469 if (IS_845G(dev) || IS_I865G(dev)) {
14470 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14471 dev->mode_config.cursor_height = 1023;
14472 } else if (IS_GEN2(dev)) {
14473 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14474 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14475 } else {
14476 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14477 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14478 }
14479
14480 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14481
14482 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14483 INTEL_INFO(dev)->num_pipes,
14484 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14485
14486 for_each_pipe(dev_priv, pipe) {
14487 intel_crtc_init(dev, pipe);
14488 for_each_sprite(dev_priv, pipe, sprite) {
14489 ret = intel_plane_init(dev, pipe, sprite);
14490 if (ret)
14491 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14492 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14493 }
14494 }
14495
14496 intel_init_dpio(dev);
14497
14498 intel_shared_dpll_init(dev);
14499
14500 /* Just disable it once at startup */
14501 i915_disable_vga(dev);
14502 intel_setup_outputs(dev);
14503
14504 /* Just in case the BIOS is doing something questionable. */
14505 intel_fbc_disable(dev);
14506
14507 drm_modeset_lock_all(dev);
14508 intel_modeset_setup_hw_state(dev, false);
14509 drm_modeset_unlock_all(dev);
14510
14511 for_each_intel_crtc(dev, crtc) {
14512 if (!crtc->active)
14513 continue;
14514
14515 /*
14516 * Note that reserving the BIOS fb up front prevents us
14517 * from stuffing other stolen allocations like the ring
14518 * on top. This prevents some ugliness at boot time, and
14519 * can even allow for smooth boot transitions if the BIOS
14520 * fb is large enough for the active pipe configuration.
14521 */
14522 if (dev_priv->display.get_initial_plane_config) {
14523 dev_priv->display.get_initial_plane_config(crtc,
14524 &crtc->plane_config);
14525 /*
14526 * If the fb is shared between multiple heads, we'll
14527 * just get the first one.
14528 */
14529 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14530 }
14531 }
14532 }
14533
14534 static void intel_enable_pipe_a(struct drm_device *dev)
14535 {
14536 struct intel_connector *connector;
14537 struct drm_connector *crt = NULL;
14538 struct intel_load_detect_pipe load_detect_temp;
14539 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14540
14541 /* We can't just switch on the pipe A, we need to set things up with a
14542 * proper mode and output configuration. As a gross hack, enable pipe A
14543 * by enabling the load detect pipe once. */
14544 for_each_intel_connector(dev, connector) {
14545 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14546 crt = &connector->base;
14547 break;
14548 }
14549 }
14550
14551 if (!crt)
14552 return;
14553
14554 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14555 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14556 }
14557
14558 static bool
14559 intel_check_plane_mapping(struct intel_crtc *crtc)
14560 {
14561 struct drm_device *dev = crtc->base.dev;
14562 struct drm_i915_private *dev_priv = dev->dev_private;
14563 u32 reg, val;
14564
14565 if (INTEL_INFO(dev)->num_pipes == 1)
14566 return true;
14567
14568 reg = DSPCNTR(!crtc->plane);
14569 val = I915_READ(reg);
14570
14571 if ((val & DISPLAY_PLANE_ENABLE) &&
14572 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14573 return false;
14574
14575 return true;
14576 }
14577
14578 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14579 {
14580 struct drm_device *dev = crtc->base.dev;
14581 struct drm_i915_private *dev_priv = dev->dev_private;
14582 u32 reg;
14583
14584 /* Clear any frame start delays used for debugging left by the BIOS */
14585 reg = PIPECONF(crtc->config->cpu_transcoder);
14586 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14587
14588 /* restore vblank interrupts to correct state */
14589 drm_crtc_vblank_reset(&crtc->base);
14590 if (crtc->active) {
14591 update_scanline_offset(crtc);
14592 drm_crtc_vblank_on(&crtc->base);
14593 }
14594
14595 /* We need to sanitize the plane -> pipe mapping first because this will
14596 * disable the crtc (and hence change the state) if it is wrong. Note
14597 * that gen4+ has a fixed plane -> pipe mapping. */
14598 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14599 struct intel_connector *connector;
14600 bool plane;
14601
14602 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14603 crtc->base.base.id);
14604
14605 /* Pipe has the wrong plane attached and the plane is active.
14606 * Temporarily change the plane mapping and disable everything
14607 * ... */
14608 plane = crtc->plane;
14609 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14610 crtc->plane = !plane;
14611 intel_crtc_disable_planes(&crtc->base);
14612 dev_priv->display.crtc_disable(&crtc->base);
14613 crtc->plane = plane;
14614
14615 /* ... and break all links. */
14616 for_each_intel_connector(dev, connector) {
14617 if (connector->encoder->base.crtc != &crtc->base)
14618 continue;
14619
14620 connector->base.dpms = DRM_MODE_DPMS_OFF;
14621 connector->base.encoder = NULL;
14622 }
14623 /* multiple connectors may have the same encoder:
14624 * handle them and break crtc link separately */
14625 for_each_intel_connector(dev, connector)
14626 if (connector->encoder->base.crtc == &crtc->base) {
14627 connector->encoder->base.crtc = NULL;
14628 connector->encoder->connectors_active = false;
14629 }
14630
14631 WARN_ON(crtc->active);
14632 crtc->base.state->enable = false;
14633 crtc->base.state->active = false;
14634 crtc->base.enabled = false;
14635 }
14636
14637 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14638 crtc->pipe == PIPE_A && !crtc->active) {
14639 /* BIOS forgot to enable pipe A, this mostly happens after
14640 * resume. Force-enable the pipe to fix this, the update_dpms
14641 * call below we restore the pipe to the right state, but leave
14642 * the required bits on. */
14643 intel_enable_pipe_a(dev);
14644 }
14645
14646 /* Adjust the state of the output pipe according to whether we
14647 * have active connectors/encoders. */
14648 intel_crtc_update_dpms(&crtc->base);
14649
14650 if (crtc->active != crtc->base.state->enable) {
14651 struct intel_encoder *encoder;
14652
14653 /* This can happen either due to bugs in the get_hw_state
14654 * functions or because the pipe is force-enabled due to the
14655 * pipe A quirk. */
14656 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14657 crtc->base.base.id,
14658 crtc->base.state->enable ? "enabled" : "disabled",
14659 crtc->active ? "enabled" : "disabled");
14660
14661 crtc->base.state->enable = crtc->active;
14662 crtc->base.state->active = crtc->active;
14663 crtc->base.enabled = crtc->active;
14664
14665 /* Because we only establish the connector -> encoder ->
14666 * crtc links if something is active, this means the
14667 * crtc is now deactivated. Break the links. connector
14668 * -> encoder links are only establish when things are
14669 * actually up, hence no need to break them. */
14670 WARN_ON(crtc->active);
14671
14672 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14673 WARN_ON(encoder->connectors_active);
14674 encoder->base.crtc = NULL;
14675 }
14676 }
14677
14678 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14679 /*
14680 * We start out with underrun reporting disabled to avoid races.
14681 * For correct bookkeeping mark this on active crtcs.
14682 *
14683 * Also on gmch platforms we dont have any hardware bits to
14684 * disable the underrun reporting. Which means we need to start
14685 * out with underrun reporting disabled also on inactive pipes,
14686 * since otherwise we'll complain about the garbage we read when
14687 * e.g. coming up after runtime pm.
14688 *
14689 * No protection against concurrent access is required - at
14690 * worst a fifo underrun happens which also sets this to false.
14691 */
14692 crtc->cpu_fifo_underrun_disabled = true;
14693 crtc->pch_fifo_underrun_disabled = true;
14694 }
14695 }
14696
14697 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14698 {
14699 struct intel_connector *connector;
14700 struct drm_device *dev = encoder->base.dev;
14701
14702 /* We need to check both for a crtc link (meaning that the
14703 * encoder is active and trying to read from a pipe) and the
14704 * pipe itself being active. */
14705 bool has_active_crtc = encoder->base.crtc &&
14706 to_intel_crtc(encoder->base.crtc)->active;
14707
14708 if (encoder->connectors_active && !has_active_crtc) {
14709 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14710 encoder->base.base.id,
14711 encoder->base.name);
14712
14713 /* Connector is active, but has no active pipe. This is
14714 * fallout from our resume register restoring. Disable
14715 * the encoder manually again. */
14716 if (encoder->base.crtc) {
14717 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14718 encoder->base.base.id,
14719 encoder->base.name);
14720 encoder->disable(encoder);
14721 if (encoder->post_disable)
14722 encoder->post_disable(encoder);
14723 }
14724 encoder->base.crtc = NULL;
14725 encoder->connectors_active = false;
14726
14727 /* Inconsistent output/port/pipe state happens presumably due to
14728 * a bug in one of the get_hw_state functions. Or someplace else
14729 * in our code, like the register restore mess on resume. Clamp
14730 * things to off as a safer default. */
14731 for_each_intel_connector(dev, connector) {
14732 if (connector->encoder != encoder)
14733 continue;
14734 connector->base.dpms = DRM_MODE_DPMS_OFF;
14735 connector->base.encoder = NULL;
14736 }
14737 }
14738 /* Enabled encoders without active connectors will be fixed in
14739 * the crtc fixup. */
14740 }
14741
14742 void i915_redisable_vga_power_on(struct drm_device *dev)
14743 {
14744 struct drm_i915_private *dev_priv = dev->dev_private;
14745 u32 vga_reg = i915_vgacntrl_reg(dev);
14746
14747 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14748 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14749 i915_disable_vga(dev);
14750 }
14751 }
14752
14753 void i915_redisable_vga(struct drm_device *dev)
14754 {
14755 struct drm_i915_private *dev_priv = dev->dev_private;
14756
14757 /* This function can be called both from intel_modeset_setup_hw_state or
14758 * at a very early point in our resume sequence, where the power well
14759 * structures are not yet restored. Since this function is at a very
14760 * paranoid "someone might have enabled VGA while we were not looking"
14761 * level, just check if the power well is enabled instead of trying to
14762 * follow the "don't touch the power well if we don't need it" policy
14763 * the rest of the driver uses. */
14764 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14765 return;
14766
14767 i915_redisable_vga_power_on(dev);
14768 }
14769
14770 static bool primary_get_hw_state(struct intel_crtc *crtc)
14771 {
14772 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14773
14774 if (!crtc->active)
14775 return false;
14776
14777 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14778 }
14779
14780 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14781 {
14782 struct drm_i915_private *dev_priv = dev->dev_private;
14783 enum pipe pipe;
14784 struct intel_crtc *crtc;
14785 struct intel_encoder *encoder;
14786 struct intel_connector *connector;
14787 int i;
14788
14789 for_each_intel_crtc(dev, crtc) {
14790 struct drm_plane *primary = crtc->base.primary;
14791 struct intel_plane_state *plane_state;
14792
14793 memset(crtc->config, 0, sizeof(*crtc->config));
14794
14795 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14796
14797 crtc->active = dev_priv->display.get_pipe_config(crtc,
14798 crtc->config);
14799
14800 crtc->base.state->enable = crtc->active;
14801 crtc->base.state->active = crtc->active;
14802 crtc->base.enabled = crtc->active;
14803
14804 plane_state = to_intel_plane_state(primary->state);
14805 plane_state->visible = primary_get_hw_state(crtc);
14806
14807 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14808 crtc->base.base.id,
14809 crtc->active ? "enabled" : "disabled");
14810 }
14811
14812 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14813 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14814
14815 pll->on = pll->get_hw_state(dev_priv, pll,
14816 &pll->config.hw_state);
14817 pll->active = 0;
14818 pll->config.crtc_mask = 0;
14819 for_each_intel_crtc(dev, crtc) {
14820 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14821 pll->active++;
14822 pll->config.crtc_mask |= 1 << crtc->pipe;
14823 }
14824 }
14825
14826 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14827 pll->name, pll->config.crtc_mask, pll->on);
14828
14829 if (pll->config.crtc_mask)
14830 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14831 }
14832
14833 for_each_intel_encoder(dev, encoder) {
14834 pipe = 0;
14835
14836 if (encoder->get_hw_state(encoder, &pipe)) {
14837 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14838 encoder->base.crtc = &crtc->base;
14839 encoder->get_config(encoder, crtc->config);
14840 } else {
14841 encoder->base.crtc = NULL;
14842 }
14843
14844 encoder->connectors_active = false;
14845 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14846 encoder->base.base.id,
14847 encoder->base.name,
14848 encoder->base.crtc ? "enabled" : "disabled",
14849 pipe_name(pipe));
14850 }
14851
14852 for_each_intel_connector(dev, connector) {
14853 if (connector->get_hw_state(connector)) {
14854 connector->base.dpms = DRM_MODE_DPMS_ON;
14855 connector->encoder->connectors_active = true;
14856 connector->base.encoder = &connector->encoder->base;
14857 } else {
14858 connector->base.dpms = DRM_MODE_DPMS_OFF;
14859 connector->base.encoder = NULL;
14860 }
14861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14862 connector->base.base.id,
14863 connector->base.name,
14864 connector->base.encoder ? "enabled" : "disabled");
14865 }
14866 }
14867
14868 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14869 * and i915 state tracking structures. */
14870 void intel_modeset_setup_hw_state(struct drm_device *dev,
14871 bool force_restore)
14872 {
14873 struct drm_i915_private *dev_priv = dev->dev_private;
14874 enum pipe pipe;
14875 struct intel_crtc *crtc;
14876 struct intel_encoder *encoder;
14877 int i;
14878
14879 intel_modeset_readout_hw_state(dev);
14880
14881 /*
14882 * Now that we have the config, copy it to each CRTC struct
14883 * Note that this could go away if we move to using crtc_config
14884 * checking everywhere.
14885 */
14886 for_each_intel_crtc(dev, crtc) {
14887 if (crtc->active && i915.fastboot) {
14888 intel_mode_from_pipe_config(&crtc->base.mode,
14889 crtc->config);
14890 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14891 crtc->base.base.id);
14892 drm_mode_debug_printmodeline(&crtc->base.mode);
14893 }
14894 }
14895
14896 /* HW state is read out, now we need to sanitize this mess. */
14897 for_each_intel_encoder(dev, encoder) {
14898 intel_sanitize_encoder(encoder);
14899 }
14900
14901 for_each_pipe(dev_priv, pipe) {
14902 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14903 intel_sanitize_crtc(crtc);
14904 intel_dump_pipe_config(crtc, crtc->config,
14905 "[setup_hw_state]");
14906 }
14907
14908 intel_modeset_update_connector_atomic_state(dev);
14909
14910 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14911 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14912
14913 if (!pll->on || pll->active)
14914 continue;
14915
14916 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14917
14918 pll->disable(dev_priv, pll);
14919 pll->on = false;
14920 }
14921
14922 if (IS_GEN9(dev))
14923 skl_wm_get_hw_state(dev);
14924 else if (HAS_PCH_SPLIT(dev))
14925 ilk_wm_get_hw_state(dev);
14926
14927 if (force_restore) {
14928 i915_redisable_vga(dev);
14929
14930 /*
14931 * We need to use raw interfaces for restoring state to avoid
14932 * checking (bogus) intermediate states.
14933 */
14934 for_each_pipe(dev_priv, pipe) {
14935 struct drm_crtc *crtc =
14936 dev_priv->pipe_to_crtc_mapping[pipe];
14937
14938 intel_crtc_restore_mode(crtc);
14939 }
14940 } else {
14941 intel_modeset_update_staged_output_state(dev);
14942 }
14943
14944 intel_modeset_check_state(dev);
14945 }
14946
14947 void intel_modeset_gem_init(struct drm_device *dev)
14948 {
14949 struct drm_i915_private *dev_priv = dev->dev_private;
14950 struct drm_crtc *c;
14951 struct drm_i915_gem_object *obj;
14952 int ret;
14953
14954 mutex_lock(&dev->struct_mutex);
14955 intel_init_gt_powersave(dev);
14956 mutex_unlock(&dev->struct_mutex);
14957
14958 /*
14959 * There may be no VBT; and if the BIOS enabled SSC we can
14960 * just keep using it to avoid unnecessary flicker. Whereas if the
14961 * BIOS isn't using it, don't assume it will work even if the VBT
14962 * indicates as much.
14963 */
14964 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14965 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14966 DREF_SSC1_ENABLE);
14967
14968 intel_modeset_init_hw(dev);
14969
14970 intel_setup_overlay(dev);
14971
14972 /*
14973 * Make sure any fbs we allocated at startup are properly
14974 * pinned & fenced. When we do the allocation it's too early
14975 * for this.
14976 */
14977 for_each_crtc(dev, c) {
14978 obj = intel_fb_obj(c->primary->fb);
14979 if (obj == NULL)
14980 continue;
14981
14982 mutex_lock(&dev->struct_mutex);
14983 ret = intel_pin_and_fence_fb_obj(c->primary,
14984 c->primary->fb,
14985 c->primary->state,
14986 NULL);
14987 mutex_unlock(&dev->struct_mutex);
14988 if (ret) {
14989 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14990 to_intel_crtc(c)->pipe);
14991 drm_framebuffer_unreference(c->primary->fb);
14992 c->primary->fb = NULL;
14993 update_state_fb(c->primary);
14994 }
14995 }
14996
14997 intel_backlight_register(dev);
14998 }
14999
15000 void intel_connector_unregister(struct intel_connector *intel_connector)
15001 {
15002 struct drm_connector *connector = &intel_connector->base;
15003
15004 intel_panel_destroy_backlight(connector);
15005 drm_connector_unregister(connector);
15006 }
15007
15008 void intel_modeset_cleanup(struct drm_device *dev)
15009 {
15010 struct drm_i915_private *dev_priv = dev->dev_private;
15011 struct drm_connector *connector;
15012
15013 intel_disable_gt_powersave(dev);
15014
15015 intel_backlight_unregister(dev);
15016
15017 /*
15018 * Interrupts and polling as the first thing to avoid creating havoc.
15019 * Too much stuff here (turning of connectors, ...) would
15020 * experience fancy races otherwise.
15021 */
15022 intel_irq_uninstall(dev_priv);
15023
15024 /*
15025 * Due to the hpd irq storm handling the hotplug work can re-arm the
15026 * poll handlers. Hence disable polling after hpd handling is shut down.
15027 */
15028 drm_kms_helper_poll_fini(dev);
15029
15030 mutex_lock(&dev->struct_mutex);
15031
15032 intel_unregister_dsm_handler();
15033
15034 intel_fbc_disable(dev);
15035
15036 mutex_unlock(&dev->struct_mutex);
15037
15038 /* flush any delayed tasks or pending work */
15039 flush_scheduled_work();
15040
15041 /* destroy the backlight and sysfs files before encoders/connectors */
15042 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15043 struct intel_connector *intel_connector;
15044
15045 intel_connector = to_intel_connector(connector);
15046 intel_connector->unregister(intel_connector);
15047 }
15048
15049 drm_mode_config_cleanup(dev);
15050
15051 intel_cleanup_overlay(dev);
15052
15053 mutex_lock(&dev->struct_mutex);
15054 intel_cleanup_gt_powersave(dev);
15055 mutex_unlock(&dev->struct_mutex);
15056 }
15057
15058 /*
15059 * Return which encoder is currently attached for connector.
15060 */
15061 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15062 {
15063 return &intel_attached_encoder(connector)->base;
15064 }
15065
15066 void intel_connector_attach_encoder(struct intel_connector *connector,
15067 struct intel_encoder *encoder)
15068 {
15069 connector->encoder = encoder;
15070 drm_mode_connector_attach_encoder(&connector->base,
15071 &encoder->base);
15072 }
15073
15074 /*
15075 * set vga decode state - true == enable VGA decode
15076 */
15077 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15078 {
15079 struct drm_i915_private *dev_priv = dev->dev_private;
15080 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15081 u16 gmch_ctrl;
15082
15083 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15084 DRM_ERROR("failed to read control word\n");
15085 return -EIO;
15086 }
15087
15088 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15089 return 0;
15090
15091 if (state)
15092 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15093 else
15094 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15095
15096 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15097 DRM_ERROR("failed to write control word\n");
15098 return -EIO;
15099 }
15100
15101 return 0;
15102 }
15103
15104 struct intel_display_error_state {
15105
15106 u32 power_well_driver;
15107
15108 int num_transcoders;
15109
15110 struct intel_cursor_error_state {
15111 u32 control;
15112 u32 position;
15113 u32 base;
15114 u32 size;
15115 } cursor[I915_MAX_PIPES];
15116
15117 struct intel_pipe_error_state {
15118 bool power_domain_on;
15119 u32 source;
15120 u32 stat;
15121 } pipe[I915_MAX_PIPES];
15122
15123 struct intel_plane_error_state {
15124 u32 control;
15125 u32 stride;
15126 u32 size;
15127 u32 pos;
15128 u32 addr;
15129 u32 surface;
15130 u32 tile_offset;
15131 } plane[I915_MAX_PIPES];
15132
15133 struct intel_transcoder_error_state {
15134 bool power_domain_on;
15135 enum transcoder cpu_transcoder;
15136
15137 u32 conf;
15138
15139 u32 htotal;
15140 u32 hblank;
15141 u32 hsync;
15142 u32 vtotal;
15143 u32 vblank;
15144 u32 vsync;
15145 } transcoder[4];
15146 };
15147
15148 struct intel_display_error_state *
15149 intel_display_capture_error_state(struct drm_device *dev)
15150 {
15151 struct drm_i915_private *dev_priv = dev->dev_private;
15152 struct intel_display_error_state *error;
15153 int transcoders[] = {
15154 TRANSCODER_A,
15155 TRANSCODER_B,
15156 TRANSCODER_C,
15157 TRANSCODER_EDP,
15158 };
15159 int i;
15160
15161 if (INTEL_INFO(dev)->num_pipes == 0)
15162 return NULL;
15163
15164 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15165 if (error == NULL)
15166 return NULL;
15167
15168 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15169 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15170
15171 for_each_pipe(dev_priv, i) {
15172 error->pipe[i].power_domain_on =
15173 __intel_display_power_is_enabled(dev_priv,
15174 POWER_DOMAIN_PIPE(i));
15175 if (!error->pipe[i].power_domain_on)
15176 continue;
15177
15178 error->cursor[i].control = I915_READ(CURCNTR(i));
15179 error->cursor[i].position = I915_READ(CURPOS(i));
15180 error->cursor[i].base = I915_READ(CURBASE(i));
15181
15182 error->plane[i].control = I915_READ(DSPCNTR(i));
15183 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15184 if (INTEL_INFO(dev)->gen <= 3) {
15185 error->plane[i].size = I915_READ(DSPSIZE(i));
15186 error->plane[i].pos = I915_READ(DSPPOS(i));
15187 }
15188 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15189 error->plane[i].addr = I915_READ(DSPADDR(i));
15190 if (INTEL_INFO(dev)->gen >= 4) {
15191 error->plane[i].surface = I915_READ(DSPSURF(i));
15192 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15193 }
15194
15195 error->pipe[i].source = I915_READ(PIPESRC(i));
15196
15197 if (HAS_GMCH_DISPLAY(dev))
15198 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15199 }
15200
15201 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15202 if (HAS_DDI(dev_priv->dev))
15203 error->num_transcoders++; /* Account for eDP. */
15204
15205 for (i = 0; i < error->num_transcoders; i++) {
15206 enum transcoder cpu_transcoder = transcoders[i];
15207
15208 error->transcoder[i].power_domain_on =
15209 __intel_display_power_is_enabled(dev_priv,
15210 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15211 if (!error->transcoder[i].power_domain_on)
15212 continue;
15213
15214 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15215
15216 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15217 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15218 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15219 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15220 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15221 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15222 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15223 }
15224
15225 return error;
15226 }
15227
15228 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15229
15230 void
15231 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15232 struct drm_device *dev,
15233 struct intel_display_error_state *error)
15234 {
15235 struct drm_i915_private *dev_priv = dev->dev_private;
15236 int i;
15237
15238 if (!error)
15239 return;
15240
15241 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15242 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15243 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15244 error->power_well_driver);
15245 for_each_pipe(dev_priv, i) {
15246 err_printf(m, "Pipe [%d]:\n", i);
15247 err_printf(m, " Power: %s\n",
15248 error->pipe[i].power_domain_on ? "on" : "off");
15249 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15250 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15251
15252 err_printf(m, "Plane [%d]:\n", i);
15253 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15254 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15255 if (INTEL_INFO(dev)->gen <= 3) {
15256 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15257 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15258 }
15259 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15260 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15261 if (INTEL_INFO(dev)->gen >= 4) {
15262 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15263 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15264 }
15265
15266 err_printf(m, "Cursor [%d]:\n", i);
15267 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15268 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15269 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15270 }
15271
15272 for (i = 0; i < error->num_transcoders; i++) {
15273 err_printf(m, "CPU transcoder: %c\n",
15274 transcoder_name(error->transcoder[i].cpu_transcoder));
15275 err_printf(m, " Power: %s\n",
15276 error->transcoder[i].power_domain_on ? "on" : "off");
15277 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15278 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15279 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15280 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15281 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15282 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15283 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15284 }
15285 }
15286
15287 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15288 {
15289 struct intel_crtc *crtc;
15290
15291 for_each_intel_crtc(dev, crtc) {
15292 struct intel_unpin_work *work;
15293
15294 spin_lock_irq(&dev->event_lock);
15295
15296 work = crtc->unpin_work;
15297
15298 if (work && work->event &&
15299 work->event->base.file_priv == file) {
15300 kfree(work->event);
15301 work->event = NULL;
15302 }
15303
15304 spin_unlock_irq(&dev->event_lock);
15305 }
15306 }
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