2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2
[] = {
57 COMMON_PRIMARY_FORMATS
,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4
[] = {
64 COMMON_PRIMARY_FORMATS
, \
67 DRM_FORMAT_XRGB2101010
,
68 DRM_FORMAT_ARGB2101010
,
69 DRM_FORMAT_XBGR2101010
,
70 DRM_FORMAT_ABGR2101010
,
74 static const uint32_t intel_cursor_formats
[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
80 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
82 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
83 struct intel_crtc_state
*pipe_config
);
85 static int intel_set_mode(struct drm_crtc
*crtc
,
86 struct drm_atomic_state
*state
);
87 static int intel_framebuffer_init(struct drm_device
*dev
,
88 struct intel_framebuffer
*ifb
,
89 struct drm_mode_fb_cmd2
*mode_cmd
,
90 struct drm_i915_gem_object
*obj
);
91 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
92 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
94 struct intel_link_m_n
*m_n
,
95 struct intel_link_m_n
*m2_n2
);
96 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
97 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
98 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
99 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_state
*pipe_config
);
101 static void chv_prepare_pll(struct intel_crtc
*crtc
,
102 const struct intel_crtc_state
*pipe_config
);
103 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
104 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
105 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
106 struct intel_crtc_state
*crtc_state
);
107 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
109 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
);
110 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
);
112 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
114 if (!connector
->mst_port
)
115 return connector
->encoder
;
117 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
126 int p2_slow
, p2_fast
;
129 typedef struct intel_limit intel_limit_t
;
131 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
136 intel_pch_rawclk(struct drm_device
*dev
)
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
140 WARN_ON(!HAS_PCH_SPLIT(dev
));
142 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
145 static inline u32
/* units of 100MHz */
146 intel_fdi_link_freq(struct drm_device
*dev
)
149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
150 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
155 static const intel_limit_t intel_limits_i8xx_dac
= {
156 .dot
= { .min
= 25000, .max
= 350000 },
157 .vco
= { .min
= 908000, .max
= 1512000 },
158 .n
= { .min
= 2, .max
= 16 },
159 .m
= { .min
= 96, .max
= 140 },
160 .m1
= { .min
= 18, .max
= 26 },
161 .m2
= { .min
= 6, .max
= 16 },
162 .p
= { .min
= 4, .max
= 128 },
163 .p1
= { .min
= 2, .max
= 33 },
164 .p2
= { .dot_limit
= 165000,
165 .p2_slow
= 4, .p2_fast
= 2 },
168 static const intel_limit_t intel_limits_i8xx_dvo
= {
169 .dot
= { .min
= 25000, .max
= 350000 },
170 .vco
= { .min
= 908000, .max
= 1512000 },
171 .n
= { .min
= 2, .max
= 16 },
172 .m
= { .min
= 96, .max
= 140 },
173 .m1
= { .min
= 18, .max
= 26 },
174 .m2
= { .min
= 6, .max
= 16 },
175 .p
= { .min
= 4, .max
= 128 },
176 .p1
= { .min
= 2, .max
= 33 },
177 .p2
= { .dot_limit
= 165000,
178 .p2_slow
= 4, .p2_fast
= 4 },
181 static const intel_limit_t intel_limits_i8xx_lvds
= {
182 .dot
= { .min
= 25000, .max
= 350000 },
183 .vco
= { .min
= 908000, .max
= 1512000 },
184 .n
= { .min
= 2, .max
= 16 },
185 .m
= { .min
= 96, .max
= 140 },
186 .m1
= { .min
= 18, .max
= 26 },
187 .m2
= { .min
= 6, .max
= 16 },
188 .p
= { .min
= 4, .max
= 128 },
189 .p1
= { .min
= 1, .max
= 6 },
190 .p2
= { .dot_limit
= 165000,
191 .p2_slow
= 14, .p2_fast
= 7 },
194 static const intel_limit_t intel_limits_i9xx_sdvo
= {
195 .dot
= { .min
= 20000, .max
= 400000 },
196 .vco
= { .min
= 1400000, .max
= 2800000 },
197 .n
= { .min
= 1, .max
= 6 },
198 .m
= { .min
= 70, .max
= 120 },
199 .m1
= { .min
= 8, .max
= 18 },
200 .m2
= { .min
= 3, .max
= 7 },
201 .p
= { .min
= 5, .max
= 80 },
202 .p1
= { .min
= 1, .max
= 8 },
203 .p2
= { .dot_limit
= 200000,
204 .p2_slow
= 10, .p2_fast
= 5 },
207 static const intel_limit_t intel_limits_i9xx_lvds
= {
208 .dot
= { .min
= 20000, .max
= 400000 },
209 .vco
= { .min
= 1400000, .max
= 2800000 },
210 .n
= { .min
= 1, .max
= 6 },
211 .m
= { .min
= 70, .max
= 120 },
212 .m1
= { .min
= 8, .max
= 18 },
213 .m2
= { .min
= 3, .max
= 7 },
214 .p
= { .min
= 7, .max
= 98 },
215 .p1
= { .min
= 1, .max
= 8 },
216 .p2
= { .dot_limit
= 112000,
217 .p2_slow
= 14, .p2_fast
= 7 },
221 static const intel_limit_t intel_limits_g4x_sdvo
= {
222 .dot
= { .min
= 25000, .max
= 270000 },
223 .vco
= { .min
= 1750000, .max
= 3500000},
224 .n
= { .min
= 1, .max
= 4 },
225 .m
= { .min
= 104, .max
= 138 },
226 .m1
= { .min
= 17, .max
= 23 },
227 .m2
= { .min
= 5, .max
= 11 },
228 .p
= { .min
= 10, .max
= 30 },
229 .p1
= { .min
= 1, .max
= 3},
230 .p2
= { .dot_limit
= 270000,
236 static const intel_limit_t intel_limits_g4x_hdmi
= {
237 .dot
= { .min
= 22000, .max
= 400000 },
238 .vco
= { .min
= 1750000, .max
= 3500000},
239 .n
= { .min
= 1, .max
= 4 },
240 .m
= { .min
= 104, .max
= 138 },
241 .m1
= { .min
= 16, .max
= 23 },
242 .m2
= { .min
= 5, .max
= 11 },
243 .p
= { .min
= 5, .max
= 80 },
244 .p1
= { .min
= 1, .max
= 8},
245 .p2
= { .dot_limit
= 165000,
246 .p2_slow
= 10, .p2_fast
= 5 },
249 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
250 .dot
= { .min
= 20000, .max
= 115000 },
251 .vco
= { .min
= 1750000, .max
= 3500000 },
252 .n
= { .min
= 1, .max
= 3 },
253 .m
= { .min
= 104, .max
= 138 },
254 .m1
= { .min
= 17, .max
= 23 },
255 .m2
= { .min
= 5, .max
= 11 },
256 .p
= { .min
= 28, .max
= 112 },
257 .p1
= { .min
= 2, .max
= 8 },
258 .p2
= { .dot_limit
= 0,
259 .p2_slow
= 14, .p2_fast
= 14
263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
264 .dot
= { .min
= 80000, .max
= 224000 },
265 .vco
= { .min
= 1750000, .max
= 3500000 },
266 .n
= { .min
= 1, .max
= 3 },
267 .m
= { .min
= 104, .max
= 138 },
268 .m1
= { .min
= 17, .max
= 23 },
269 .m2
= { .min
= 5, .max
= 11 },
270 .p
= { .min
= 14, .max
= 42 },
271 .p1
= { .min
= 2, .max
= 6 },
272 .p2
= { .dot_limit
= 0,
273 .p2_slow
= 7, .p2_fast
= 7
277 static const intel_limit_t intel_limits_pineview_sdvo
= {
278 .dot
= { .min
= 20000, .max
= 400000},
279 .vco
= { .min
= 1700000, .max
= 3500000 },
280 /* Pineview's Ncounter is a ring counter */
281 .n
= { .min
= 3, .max
= 6 },
282 .m
= { .min
= 2, .max
= 256 },
283 /* Pineview only has one combined m divider, which we treat as m2. */
284 .m1
= { .min
= 0, .max
= 0 },
285 .m2
= { .min
= 0, .max
= 254 },
286 .p
= { .min
= 5, .max
= 80 },
287 .p1
= { .min
= 1, .max
= 8 },
288 .p2
= { .dot_limit
= 200000,
289 .p2_slow
= 10, .p2_fast
= 5 },
292 static const intel_limit_t intel_limits_pineview_lvds
= {
293 .dot
= { .min
= 20000, .max
= 400000 },
294 .vco
= { .min
= 1700000, .max
= 3500000 },
295 .n
= { .min
= 3, .max
= 6 },
296 .m
= { .min
= 2, .max
= 256 },
297 .m1
= { .min
= 0, .max
= 0 },
298 .m2
= { .min
= 0, .max
= 254 },
299 .p
= { .min
= 7, .max
= 112 },
300 .p1
= { .min
= 1, .max
= 8 },
301 .p2
= { .dot_limit
= 112000,
302 .p2_slow
= 14, .p2_fast
= 14 },
305 /* Ironlake / Sandybridge
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
310 static const intel_limit_t intel_limits_ironlake_dac
= {
311 .dot
= { .min
= 25000, .max
= 350000 },
312 .vco
= { .min
= 1760000, .max
= 3510000 },
313 .n
= { .min
= 1, .max
= 5 },
314 .m
= { .min
= 79, .max
= 127 },
315 .m1
= { .min
= 12, .max
= 22 },
316 .m2
= { .min
= 5, .max
= 9 },
317 .p
= { .min
= 5, .max
= 80 },
318 .p1
= { .min
= 1, .max
= 8 },
319 .p2
= { .dot_limit
= 225000,
320 .p2_slow
= 10, .p2_fast
= 5 },
323 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
324 .dot
= { .min
= 25000, .max
= 350000 },
325 .vco
= { .min
= 1760000, .max
= 3510000 },
326 .n
= { .min
= 1, .max
= 3 },
327 .m
= { .min
= 79, .max
= 118 },
328 .m1
= { .min
= 12, .max
= 22 },
329 .m2
= { .min
= 5, .max
= 9 },
330 .p
= { .min
= 28, .max
= 112 },
331 .p1
= { .min
= 2, .max
= 8 },
332 .p2
= { .dot_limit
= 225000,
333 .p2_slow
= 14, .p2_fast
= 14 },
336 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
337 .dot
= { .min
= 25000, .max
= 350000 },
338 .vco
= { .min
= 1760000, .max
= 3510000 },
339 .n
= { .min
= 1, .max
= 3 },
340 .m
= { .min
= 79, .max
= 127 },
341 .m1
= { .min
= 12, .max
= 22 },
342 .m2
= { .min
= 5, .max
= 9 },
343 .p
= { .min
= 14, .max
= 56 },
344 .p1
= { .min
= 2, .max
= 8 },
345 .p2
= { .dot_limit
= 225000,
346 .p2_slow
= 7, .p2_fast
= 7 },
349 /* LVDS 100mhz refclk limits. */
350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
351 .dot
= { .min
= 25000, .max
= 350000 },
352 .vco
= { .min
= 1760000, .max
= 3510000 },
353 .n
= { .min
= 1, .max
= 2 },
354 .m
= { .min
= 79, .max
= 126 },
355 .m1
= { .min
= 12, .max
= 22 },
356 .m2
= { .min
= 5, .max
= 9 },
357 .p
= { .min
= 28, .max
= 112 },
358 .p1
= { .min
= 2, .max
= 8 },
359 .p2
= { .dot_limit
= 225000,
360 .p2_slow
= 14, .p2_fast
= 14 },
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000 },
366 .n
= { .min
= 1, .max
= 3 },
367 .m
= { .min
= 79, .max
= 126 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 14, .max
= 42 },
371 .p1
= { .min
= 2, .max
= 6 },
372 .p2
= { .dot_limit
= 225000,
373 .p2_slow
= 7, .p2_fast
= 7 },
376 static const intel_limit_t intel_limits_vlv
= {
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
383 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
384 .vco
= { .min
= 4000000, .max
= 6000000 },
385 .n
= { .min
= 1, .max
= 7 },
386 .m1
= { .min
= 2, .max
= 3 },
387 .m2
= { .min
= 11, .max
= 156 },
388 .p1
= { .min
= 2, .max
= 3 },
389 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
392 static const intel_limit_t intel_limits_chv
= {
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
399 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
400 .vco
= { .min
= 4800000, .max
= 6480000 },
401 .n
= { .min
= 1, .max
= 1 },
402 .m1
= { .min
= 2, .max
= 2 },
403 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
404 .p1
= { .min
= 2, .max
= 4 },
405 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
408 static const intel_limit_t intel_limits_bxt
= {
409 /* FIXME: find real dot limits */
410 .dot
= { .min
= 0, .max
= INT_MAX
},
411 .vco
= { .min
= 4800000, .max
= 6480000 },
412 .n
= { .min
= 1, .max
= 1 },
413 .m1
= { .min
= 2, .max
= 2 },
414 /* FIXME: find real m2 limits */
415 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
416 .p1
= { .min
= 2, .max
= 4 },
417 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
420 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
422 clock
->m
= clock
->m1
* clock
->m2
;
423 clock
->p
= clock
->p1
* clock
->p2
;
424 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
426 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
427 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
431 * Returns whether any output on the specified pipe is of the specified type
433 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
435 struct drm_device
*dev
= crtc
->base
.dev
;
436 struct intel_encoder
*encoder
;
438 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
439 if (encoder
->type
== type
)
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
451 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
454 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
455 struct drm_connector
*connector
;
456 struct drm_connector_state
*connector_state
;
457 struct intel_encoder
*encoder
;
458 int i
, num_connectors
= 0;
460 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
461 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
466 encoder
= to_intel_encoder(connector_state
->best_encoder
);
467 if (encoder
->type
== type
)
471 WARN_ON(num_connectors
== 0);
476 static const intel_limit_t
*
477 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
479 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
480 const intel_limit_t
*limit
;
482 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
483 if (intel_is_dual_link_lvds(dev
)) {
484 if (refclk
== 100000)
485 limit
= &intel_limits_ironlake_dual_lvds_100m
;
487 limit
= &intel_limits_ironlake_dual_lvds
;
489 if (refclk
== 100000)
490 limit
= &intel_limits_ironlake_single_lvds_100m
;
492 limit
= &intel_limits_ironlake_single_lvds
;
495 limit
= &intel_limits_ironlake_dac
;
500 static const intel_limit_t
*
501 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
503 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
504 const intel_limit_t
*limit
;
506 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
507 if (intel_is_dual_link_lvds(dev
))
508 limit
= &intel_limits_g4x_dual_channel_lvds
;
510 limit
= &intel_limits_g4x_single_channel_lvds
;
511 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
512 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
513 limit
= &intel_limits_g4x_hdmi
;
514 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
515 limit
= &intel_limits_g4x_sdvo
;
516 } else /* The option is for other outputs */
517 limit
= &intel_limits_i9xx_sdvo
;
522 static const intel_limit_t
*
523 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
525 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
526 const intel_limit_t
*limit
;
529 limit
= &intel_limits_bxt
;
530 else if (HAS_PCH_SPLIT(dev
))
531 limit
= intel_ironlake_limit(crtc_state
, refclk
);
532 else if (IS_G4X(dev
)) {
533 limit
= intel_g4x_limit(crtc_state
);
534 } else if (IS_PINEVIEW(dev
)) {
535 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
536 limit
= &intel_limits_pineview_lvds
;
538 limit
= &intel_limits_pineview_sdvo
;
539 } else if (IS_CHERRYVIEW(dev
)) {
540 limit
= &intel_limits_chv
;
541 } else if (IS_VALLEYVIEW(dev
)) {
542 limit
= &intel_limits_vlv
;
543 } else if (!IS_GEN2(dev
)) {
544 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
545 limit
= &intel_limits_i9xx_lvds
;
547 limit
= &intel_limits_i9xx_sdvo
;
549 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
550 limit
= &intel_limits_i8xx_lvds
;
551 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
552 limit
= &intel_limits_i8xx_dvo
;
554 limit
= &intel_limits_i8xx_dac
;
559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
560 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
562 clock
->m
= clock
->m2
+ 2;
563 clock
->p
= clock
->p1
* clock
->p2
;
564 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
566 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
567 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
570 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
572 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
575 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
577 clock
->m
= i9xx_dpll_compute_m(clock
);
578 clock
->p
= clock
->p1
* clock
->p2
;
579 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
581 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
582 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
585 static void chv_clock(int refclk
, intel_clock_t
*clock
)
587 clock
->m
= clock
->m1
* clock
->m2
;
588 clock
->p
= clock
->p1
* clock
->p2
;
589 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
591 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
593 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
602 static bool intel_PLL_is_valid(struct drm_device
*dev
,
603 const intel_limit_t
*limit
,
604 const intel_clock_t
*clock
)
606 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
607 INTELPllInvalid("n out of range\n");
608 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
613 INTELPllInvalid("m1 out of range\n");
615 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
616 if (clock
->m1
<= clock
->m2
)
617 INTELPllInvalid("m1 <= m2\n");
619 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
620 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
621 INTELPllInvalid("p out of range\n");
622 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
623 INTELPllInvalid("m out of range\n");
626 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
627 INTELPllInvalid("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
631 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
632 INTELPllInvalid("dot out of range\n");
638 i9xx_find_best_dpll(const intel_limit_t
*limit
,
639 struct intel_crtc_state
*crtc_state
,
640 int target
, int refclk
, intel_clock_t
*match_clock
,
641 intel_clock_t
*best_clock
)
643 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
644 struct drm_device
*dev
= crtc
->base
.dev
;
648 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 clock
.p2
= limit
->p2
.p2_fast
;
657 clock
.p2
= limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 clock
.p2
= limit
->p2
.p2_slow
;
662 clock
.p2
= limit
->p2
.p2_fast
;
665 memset(best_clock
, 0, sizeof(*best_clock
));
667 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
669 for (clock
.m2
= limit
->m2
.min
;
670 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
671 if (clock
.m2
>= clock
.m1
)
673 for (clock
.n
= limit
->n
.min
;
674 clock
.n
<= limit
->n
.max
; clock
.n
++) {
675 for (clock
.p1
= limit
->p1
.min
;
676 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
679 i9xx_clock(refclk
, &clock
);
680 if (!intel_PLL_is_valid(dev
, limit
,
684 clock
.p
!= match_clock
->p
)
687 this_err
= abs(clock
.dot
- target
);
688 if (this_err
< err
) {
697 return (err
!= target
);
701 pnv_find_best_dpll(const intel_limit_t
*limit
,
702 struct intel_crtc_state
*crtc_state
,
703 int target
, int refclk
, intel_clock_t
*match_clock
,
704 intel_clock_t
*best_clock
)
706 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
707 struct drm_device
*dev
= crtc
->base
.dev
;
711 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
730 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
732 for (clock
.m2
= limit
->m2
.min
;
733 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
734 for (clock
.n
= limit
->n
.min
;
735 clock
.n
<= limit
->n
.max
; clock
.n
++) {
736 for (clock
.p1
= limit
->p1
.min
;
737 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
740 pineview_clock(refclk
, &clock
);
741 if (!intel_PLL_is_valid(dev
, limit
,
745 clock
.p
!= match_clock
->p
)
748 this_err
= abs(clock
.dot
- target
);
749 if (this_err
< err
) {
758 return (err
!= target
);
762 g4x_find_best_dpll(const intel_limit_t
*limit
,
763 struct intel_crtc_state
*crtc_state
,
764 int target
, int refclk
, intel_clock_t
*match_clock
,
765 intel_clock_t
*best_clock
)
767 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
768 struct drm_device
*dev
= crtc
->base
.dev
;
772 /* approximately equals target * 0.00585 */
773 int err_most
= (target
>> 8) + (target
>> 9);
776 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
777 if (intel_is_dual_link_lvds(dev
))
778 clock
.p2
= limit
->p2
.p2_fast
;
780 clock
.p2
= limit
->p2
.p2_slow
;
782 if (target
< limit
->p2
.dot_limit
)
783 clock
.p2
= limit
->p2
.p2_slow
;
785 clock
.p2
= limit
->p2
.p2_fast
;
788 memset(best_clock
, 0, sizeof(*best_clock
));
789 max_n
= limit
->n
.max
;
790 /* based on hardware requirement, prefer smaller n to precision */
791 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
792 /* based on hardware requirement, prefere larger m1,m2 */
793 for (clock
.m1
= limit
->m1
.max
;
794 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
795 for (clock
.m2
= limit
->m2
.max
;
796 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
797 for (clock
.p1
= limit
->p1
.max
;
798 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
801 i9xx_clock(refclk
, &clock
);
802 if (!intel_PLL_is_valid(dev
, limit
,
806 this_err
= abs(clock
.dot
- target
);
807 if (this_err
< err_most
) {
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
824 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
825 const intel_clock_t
*calculated_clock
,
826 const intel_clock_t
*best_clock
,
827 unsigned int best_error_ppm
,
828 unsigned int *error_ppm
)
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
834 if (IS_CHERRYVIEW(dev
)) {
837 return calculated_clock
->p
> best_clock
->p
;
840 if (WARN_ON_ONCE(!target_freq
))
843 *error_ppm
= div_u64(1000000ULL *
844 abs(target_freq
- calculated_clock
->dot
),
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
851 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
857 return *error_ppm
+ 10 < best_error_ppm
;
861 vlv_find_best_dpll(const intel_limit_t
*limit
,
862 struct intel_crtc_state
*crtc_state
,
863 int target
, int refclk
, intel_clock_t
*match_clock
,
864 intel_clock_t
*best_clock
)
866 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
867 struct drm_device
*dev
= crtc
->base
.dev
;
869 unsigned int bestppm
= 1000000;
870 /* min update 19.2 MHz */
871 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
874 target
*= 5; /* fast clock */
876 memset(best_clock
, 0, sizeof(*best_clock
));
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
880 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
881 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
882 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
883 clock
.p
= clock
.p1
* clock
.p2
;
884 /* based on hardware requirement, prefer bigger m1,m2 values */
885 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
888 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
891 vlv_clock(refclk
, &clock
);
893 if (!intel_PLL_is_valid(dev
, limit
,
897 if (!vlv_PLL_is_optimal(dev
, target
,
915 chv_find_best_dpll(const intel_limit_t
*limit
,
916 struct intel_crtc_state
*crtc_state
,
917 int target
, int refclk
, intel_clock_t
*match_clock
,
918 intel_clock_t
*best_clock
)
920 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
921 struct drm_device
*dev
= crtc
->base
.dev
;
922 unsigned int best_error_ppm
;
927 memset(best_clock
, 0, sizeof(*best_clock
));
928 best_error_ppm
= 1000000;
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
935 clock
.n
= 1, clock
.m1
= 2;
936 target
*= 5; /* fast clock */
938 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
939 for (clock
.p2
= limit
->p2
.p2_fast
;
940 clock
.p2
>= limit
->p2
.p2_slow
;
941 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
942 unsigned int error_ppm
;
944 clock
.p
= clock
.p1
* clock
.p2
;
946 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
947 clock
.n
) << 22, refclk
* clock
.m1
);
949 if (m2
> INT_MAX
/clock
.m1
)
954 chv_clock(refclk
, &clock
);
956 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
959 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
960 best_error_ppm
, &error_ppm
))
964 best_error_ppm
= error_ppm
;
972 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
973 intel_clock_t
*best_clock
)
975 int refclk
= i9xx_get_refclk(crtc_state
, 0);
977 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
978 target_clock
, refclk
, NULL
, best_clock
);
981 bool intel_crtc_active(struct drm_crtc
*crtc
)
983 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
988 * We can ditch the adjusted_mode.crtc_clock check as soon
989 * as Haswell has gained clock readout/fastboot support.
991 * We can ditch the crtc->primary->fb check as soon as we can
992 * properly reconstruct framebuffers.
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
998 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
999 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1002 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1005 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1006 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1008 return intel_crtc
->config
->cpu_transcoder
;
1011 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1014 u32 reg
= PIPEDSL(pipe
);
1019 line_mask
= DSL_LINEMASK_GEN2
;
1021 line_mask
= DSL_LINEMASK_GEN3
;
1023 line1
= I915_READ(reg
) & line_mask
;
1025 line2
= I915_READ(reg
) & line_mask
;
1027 return line1
== line2
;
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
1032 * @crtc: crtc whose pipe to wait for
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
1046 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1048 struct drm_device
*dev
= crtc
->base
.dev
;
1049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1050 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1051 enum pipe pipe
= crtc
->pipe
;
1053 if (INTEL_INFO(dev
)->gen
>= 4) {
1054 int reg
= PIPECONF(cpu_transcoder
);
1056 /* Wait for the Pipe State to go off */
1057 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1059 WARN(1, "pipe_off wait timed out\n");
1061 /* Wait for the display line to settle */
1062 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1063 WARN(1, "pipe_off wait timed out\n");
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1072 * Returns true if @port is connected, false otherwise.
1074 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1075 struct intel_digital_port
*port
)
1079 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1080 switch (port
->port
) {
1082 bit
= SDE_PORTB_HOTPLUG
;
1085 bit
= SDE_PORTC_HOTPLUG
;
1088 bit
= SDE_PORTD_HOTPLUG
;
1094 switch (port
->port
) {
1096 bit
= SDE_PORTB_HOTPLUG_CPT
;
1099 bit
= SDE_PORTC_HOTPLUG_CPT
;
1102 bit
= SDE_PORTD_HOTPLUG_CPT
;
1109 return I915_READ(SDEISR
) & bit
;
1112 static const char *state_string(bool enabled
)
1114 return enabled
? "on" : "off";
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1126 val
= I915_READ(reg
);
1127 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1128 I915_STATE_WARN(cur_state
!= state
,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state
), state_string(cur_state
));
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1139 mutex_lock(&dev_priv
->dpio_lock
);
1140 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1141 mutex_unlock(&dev_priv
->dpio_lock
);
1143 cur_state
= val
& DSI_PLL_VCO_EN
;
1144 I915_STATE_WARN(cur_state
!= state
,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state
), state_string(cur_state
));
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1151 struct intel_shared_dpll
*
1152 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1154 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1156 if (crtc
->config
->shared_dpll
< 0)
1159 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1163 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1164 struct intel_shared_dpll
*pll
,
1168 struct intel_dpll_hw_state hw_state
;
1171 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1174 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1175 I915_STATE_WARN(cur_state
!= state
,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll
->name
, state_string(state
), state_string(cur_state
));
1180 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1186 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1189 if (HAS_DDI(dev_priv
->dev
)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1192 val
= I915_READ(reg
);
1193 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1195 reg
= FDI_TX_CTL(pipe
);
1196 val
= I915_READ(reg
);
1197 cur_state
= !!(val
& FDI_TX_ENABLE
);
1199 I915_STATE_WARN(cur_state
!= state
,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state
), state_string(cur_state
));
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1206 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1207 enum pipe pipe
, bool state
)
1213 reg
= FDI_RX_CTL(pipe
);
1214 val
= I915_READ(reg
);
1215 cur_state
= !!(val
& FDI_RX_ENABLE
);
1216 I915_STATE_WARN(cur_state
!= state
,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state
), state_string(cur_state
));
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv
->dev
))
1237 reg
= FDI_TX_CTL(pipe
);
1238 val
= I915_READ(reg
);
1239 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1242 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1243 enum pipe pipe
, bool state
)
1249 reg
= FDI_RX_CTL(pipe
);
1250 val
= I915_READ(reg
);
1251 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1252 I915_STATE_WARN(cur_state
!= state
,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state
), state_string(cur_state
));
1257 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1260 struct drm_device
*dev
= dev_priv
->dev
;
1263 enum pipe panel_pipe
= PIPE_A
;
1266 if (WARN_ON(HAS_DDI(dev
)))
1269 if (HAS_PCH_SPLIT(dev
)) {
1272 pp_reg
= PCH_PP_CONTROL
;
1273 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1275 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1276 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1277 panel_pipe
= PIPE_B
;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev
)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1284 pp_reg
= PP_CONTROL
;
1285 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1286 panel_pipe
= PIPE_B
;
1289 val
= I915_READ(pp_reg
);
1290 if (!(val
& PANEL_POWER_ON
) ||
1291 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1294 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1295 "panel assertion failure, pipe %c regs locked\n",
1299 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1300 enum pipe pipe
, bool state
)
1302 struct drm_device
*dev
= dev_priv
->dev
;
1305 if (IS_845G(dev
) || IS_I865G(dev
))
1306 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1308 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1310 I915_STATE_WARN(cur_state
!= state
,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1317 void assert_pipe(struct drm_i915_private
*dev_priv
,
1318 enum pipe pipe
, bool state
)
1323 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1328 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1331 if (!intel_display_power_is_enabled(dev_priv
,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1335 reg
= PIPECONF(cpu_transcoder
);
1336 val
= I915_READ(reg
);
1337 cur_state
= !!(val
& PIPECONF_ENABLE
);
1340 I915_STATE_WARN(cur_state
!= state
,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1345 static void assert_plane(struct drm_i915_private
*dev_priv
,
1346 enum plane plane
, bool state
)
1352 reg
= DSPCNTR(plane
);
1353 val
= I915_READ(reg
);
1354 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1355 I915_STATE_WARN(cur_state
!= state
,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane
), state_string(state
), state_string(cur_state
));
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1363 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1366 struct drm_device
*dev
= dev_priv
->dev
;
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev
)->gen
>= 4) {
1373 reg
= DSPCNTR(pipe
);
1374 val
= I915_READ(reg
);
1375 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1376 "plane %c assertion failure, should be disabled but not\n",
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv
, i
) {
1384 val
= I915_READ(reg
);
1385 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1386 DISPPLANE_SEL_PIPE_SHIFT
;
1387 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i
), pipe_name(pipe
));
1393 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1396 struct drm_device
*dev
= dev_priv
->dev
;
1400 if (INTEL_INFO(dev
)->gen
>= 9) {
1401 for_each_sprite(dev_priv
, pipe
, sprite
) {
1402 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1403 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite
, pipe_name(pipe
));
1407 } else if (IS_VALLEYVIEW(dev
)) {
1408 for_each_sprite(dev_priv
, pipe
, sprite
) {
1409 reg
= SPCNTR(pipe
, sprite
);
1410 val
= I915_READ(reg
);
1411 I915_STATE_WARN(val
& SP_ENABLE
,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1415 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1417 val
= I915_READ(reg
);
1418 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe
), pipe_name(pipe
));
1421 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1422 reg
= DVSCNTR(pipe
);
1423 val
= I915_READ(reg
);
1424 I915_STATE_WARN(val
& DVS_ENABLE
,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe
), pipe_name(pipe
));
1430 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1433 drm_crtc_vblank_put(crtc
);
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1443 val
= I915_READ(PCH_DREF_CONTROL
);
1444 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1445 DREF_SUPERSPREAD_SOURCE_MASK
));
1446 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1456 reg
= PCH_TRANSCONF(pipe
);
1457 val
= I915_READ(reg
);
1458 enabled
= !!(val
& TRANS_ENABLE
);
1459 I915_STATE_WARN(enabled
,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1464 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1465 enum pipe pipe
, u32 port_sel
, u32 val
)
1467 if ((val
& DP_PORT_EN
) == 0)
1470 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1471 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1472 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1473 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1475 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1476 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1479 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1485 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1486 enum pipe pipe
, u32 val
)
1488 if ((val
& SDVO_ENABLE
) == 0)
1491 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1492 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1494 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1495 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1498 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1504 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1505 enum pipe pipe
, u32 val
)
1507 if ((val
& LVDS_PORT_EN
) == 0)
1510 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1511 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1514 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1520 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1521 enum pipe pipe
, u32 val
)
1523 if ((val
& ADPA_DAC_ENABLE
) == 0)
1525 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1526 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1529 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1535 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1536 enum pipe pipe
, int reg
, u32 port_sel
)
1538 u32 val
= I915_READ(reg
);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg
, pipe_name(pipe
));
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1544 && (val
& DP_PIPEB_SELECT
),
1545 "IBX PCH dp port still using transcoder B\n");
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1549 enum pipe pipe
, int reg
)
1551 u32 val
= I915_READ(reg
);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg
, pipe_name(pipe
));
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1557 && (val
& SDVO_PIPE_B_SELECT
),
1558 "IBX PCH hdmi port still using transcoder B\n");
1561 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1567 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1568 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1569 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1572 val
= I915_READ(reg
);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1578 val
= I915_READ(reg
);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1583 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1584 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1585 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1588 static void intel_init_dpio(struct drm_device
*dev
)
1590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1592 if (!IS_VALLEYVIEW(dev
))
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1600 if (IS_CHERRYVIEW(dev
)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1608 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1609 const struct intel_crtc_state
*pipe_config
)
1611 struct drm_device
*dev
= crtc
->base
.dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 int reg
= DPLL(crtc
->pipe
);
1614 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1616 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv
->dev
))
1623 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1625 I915_WRITE(reg
, dpll
);
1629 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1632 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1633 POSTING_READ(DPLL_MD(crtc
->pipe
));
1635 /* We do this three times for luck */
1636 I915_WRITE(reg
, dpll
);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg
, dpll
);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg
, dpll
);
1644 udelay(150); /* wait for warmup */
1647 static void chv_enable_pll(struct intel_crtc
*crtc
,
1648 const struct intel_crtc_state
*pipe_config
)
1650 struct drm_device
*dev
= crtc
->base
.dev
;
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1652 int pipe
= crtc
->pipe
;
1653 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1656 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1660 mutex_lock(&dev_priv
->dpio_lock
);
1662 /* Enable back the 10bit clock to display controller */
1663 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1664 tmp
|= DPIO_DCLKP_EN
;
1665 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1675 /* Check PLL is locked */
1676 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1677 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1679 /* not sure when this should be written */
1680 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1681 POSTING_READ(DPLL_MD(pipe
));
1683 mutex_unlock(&dev_priv
->dpio_lock
);
1686 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1688 struct intel_crtc
*crtc
;
1691 for_each_intel_crtc(dev
, crtc
)
1692 count
+= crtc
->active
&&
1693 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1698 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1700 struct drm_device
*dev
= crtc
->base
.dev
;
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1702 int reg
= DPLL(crtc
->pipe
);
1703 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1705 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1712 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1722 dpll
|= DPLL_DVO_2X_MODE
;
1723 I915_WRITE(DPLL(!crtc
->pipe
),
1724 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1727 /* Wait for the clocks to stabilize. */
1731 if (INTEL_INFO(dev
)->gen
>= 4) {
1732 I915_WRITE(DPLL_MD(crtc
->pipe
),
1733 crtc
->config
->dpll_hw_state
.dpll_md
);
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1738 * So write it again.
1740 I915_WRITE(reg
, dpll
);
1743 /* We do this three times for luck */
1744 I915_WRITE(reg
, dpll
);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg
, dpll
);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg
, dpll
);
1752 udelay(150); /* wait for warmup */
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1762 * Note! This is for pre-ILK only.
1764 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1766 struct drm_device
*dev
= crtc
->base
.dev
;
1767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1768 enum pipe pipe
= crtc
->pipe
;
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1772 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1773 intel_num_dvo_pipes(dev
) == 1) {
1774 I915_WRITE(DPLL(PIPE_B
),
1775 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1776 I915_WRITE(DPLL(PIPE_A
),
1777 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1782 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv
, pipe
);
1788 I915_WRITE(DPLL(pipe
), 0);
1789 POSTING_READ(DPLL(pipe
));
1792 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv
, pipe
);
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1804 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1805 I915_WRITE(DPLL(pipe
), val
);
1806 POSTING_READ(DPLL(pipe
));
1810 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1812 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv
, pipe
);
1818 /* Set PLL en = 0 */
1819 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1821 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1822 I915_WRITE(DPLL(pipe
), val
);
1823 POSTING_READ(DPLL(pipe
));
1825 mutex_lock(&dev_priv
->dpio_lock
);
1827 /* Disable 10bit clock to display controller */
1828 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1829 val
&= ~DPIO_DCLKP_EN
;
1830 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1832 /* disable left/right clock distribution */
1833 if (pipe
!= PIPE_B
) {
1834 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1835 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1836 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1838 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1839 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1840 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1843 mutex_unlock(&dev_priv
->dpio_lock
);
1846 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1847 struct intel_digital_port
*dport
,
1848 unsigned int expected_mask
)
1853 switch (dport
->port
) {
1855 port_mask
= DPLL_PORTB_READY_MASK
;
1859 port_mask
= DPLL_PORTC_READY_MASK
;
1861 expected_mask
<<= 4;
1864 port_mask
= DPLL_PORTD_READY_MASK
;
1865 dpll_reg
= DPIO_PHY_STATUS
;
1871 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1876 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1878 struct drm_device
*dev
= crtc
->base
.dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1880 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1882 if (WARN_ON(pll
== NULL
))
1885 WARN_ON(!pll
->config
.crtc_mask
);
1886 if (pll
->active
== 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1889 assert_shared_dpll_disabled(dev_priv
, pll
);
1891 pll
->mode_set(dev_priv
, pll
);
1896 * intel_enable_shared_dpll - enable PCH PLL
1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1903 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1905 struct drm_device
*dev
= crtc
->base
.dev
;
1906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1907 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1909 if (WARN_ON(pll
== NULL
))
1912 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1916 pll
->name
, pll
->active
, pll
->on
,
1917 crtc
->base
.base
.id
);
1919 if (pll
->active
++) {
1921 assert_shared_dpll_enabled(dev_priv
, pll
);
1926 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1928 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1929 pll
->enable(dev_priv
, pll
);
1933 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1935 struct drm_device
*dev
= crtc
->base
.dev
;
1936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1937 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1941 if (WARN_ON(pll
== NULL
))
1944 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll
->name
, pll
->active
, pll
->on
,
1949 crtc
->base
.base
.id
);
1951 if (WARN_ON(pll
->active
== 0)) {
1952 assert_shared_dpll_disabled(dev_priv
, pll
);
1956 assert_shared_dpll_enabled(dev_priv
, pll
);
1961 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1962 pll
->disable(dev_priv
, pll
);
1965 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1968 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1971 struct drm_device
*dev
= dev_priv
->dev
;
1972 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1974 uint32_t reg
, val
, pipeconf_val
;
1976 /* PCH only available on ILK+ */
1977 BUG_ON(!HAS_PCH_SPLIT(dev
));
1979 /* Make sure PCH DPLL is enabled */
1980 assert_shared_dpll_enabled(dev_priv
,
1981 intel_crtc_to_shared_dpll(intel_crtc
));
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv
, pipe
);
1985 assert_fdi_rx_enabled(dev_priv
, pipe
);
1987 if (HAS_PCH_CPT(dev
)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg
= TRANS_CHICKEN2(pipe
);
1991 val
= I915_READ(reg
);
1992 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1993 I915_WRITE(reg
, val
);
1996 reg
= PCH_TRANSCONF(pipe
);
1997 val
= I915_READ(reg
);
1998 pipeconf_val
= I915_READ(PIPECONF(pipe
));
2000 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2005 val
&= ~PIPECONF_BPC_MASK
;
2006 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2009 val
&= ~TRANS_INTERLACE_MASK
;
2010 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2011 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2012 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2013 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2015 val
|= TRANS_INTERLACED
;
2017 val
|= TRANS_PROGRESSIVE
;
2019 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2020 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2024 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2025 enum transcoder cpu_transcoder
)
2027 u32 val
, pipeconf_val
;
2029 /* PCH only available on ILK+ */
2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2032 /* FDI must be feeding us bits for PCH ports */
2033 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2034 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2036 /* Workaround: set timing override bit. */
2037 val
= I915_READ(_TRANSA_CHICKEN2
);
2038 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2039 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2042 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2044 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2045 PIPECONF_INTERLACED_ILK
)
2046 val
|= TRANS_INTERLACED
;
2048 val
|= TRANS_PROGRESSIVE
;
2050 I915_WRITE(LPT_TRANSCONF
, val
);
2051 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2052 DRM_ERROR("Failed to enable PCH transcoder\n");
2055 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2058 struct drm_device
*dev
= dev_priv
->dev
;
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv
, pipe
);
2063 assert_fdi_rx_disabled(dev_priv
, pipe
);
2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv
, pipe
);
2068 reg
= PCH_TRANSCONF(pipe
);
2069 val
= I915_READ(reg
);
2070 val
&= ~TRANS_ENABLE
;
2071 I915_WRITE(reg
, val
);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2076 if (!HAS_PCH_IBX(dev
)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg
= TRANS_CHICKEN2(pipe
);
2079 val
= I915_READ(reg
);
2080 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2081 I915_WRITE(reg
, val
);
2085 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2089 val
= I915_READ(LPT_TRANSCONF
);
2090 val
&= ~TRANS_ENABLE
;
2091 I915_WRITE(LPT_TRANSCONF
, val
);
2092 /* wait for PCH transcoder off, transcoder state */
2093 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2094 DRM_ERROR("Failed to disable PCH transcoder\n");
2096 /* Workaround: clear timing override bit. */
2097 val
= I915_READ(_TRANSA_CHICKEN2
);
2098 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2099 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2103 * intel_enable_pipe - enable a pipe, asserting requirements
2104 * @crtc: crtc responsible for the pipe
2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2109 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2111 struct drm_device
*dev
= crtc
->base
.dev
;
2112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2113 enum pipe pipe
= crtc
->pipe
;
2114 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2116 enum pipe pch_transcoder
;
2120 assert_planes_disabled(dev_priv
, pipe
);
2121 assert_cursor_disabled(dev_priv
, pipe
);
2122 assert_sprites_disabled(dev_priv
, pipe
);
2124 if (HAS_PCH_LPT(dev_priv
->dev
))
2125 pch_transcoder
= TRANSCODER_A
;
2127 pch_transcoder
= pipe
;
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2134 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2135 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2136 assert_dsi_pll_enabled(dev_priv
);
2138 assert_pll_enabled(dev_priv
, pipe
);
2140 if (crtc
->config
->has_pch_encoder
) {
2141 /* if driving the PCH, we need FDI enabled */
2142 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2143 assert_fdi_tx_pll_enabled(dev_priv
,
2144 (enum pipe
) cpu_transcoder
);
2146 /* FIXME: assert CPU port conditions for SNB+ */
2149 reg
= PIPECONF(cpu_transcoder
);
2150 val
= I915_READ(reg
);
2151 if (val
& PIPECONF_ENABLE
) {
2152 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2153 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2157 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2169 * Will wait until the pipe has shut down before returning.
2171 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2173 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2174 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2175 enum pipe pipe
= crtc
->pipe
;
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2183 assert_planes_disabled(dev_priv
, pipe
);
2184 assert_cursor_disabled(dev_priv
, pipe
);
2185 assert_sprites_disabled(dev_priv
, pipe
);
2187 reg
= PIPECONF(cpu_transcoder
);
2188 val
= I915_READ(reg
);
2189 if ((val
& PIPECONF_ENABLE
) == 0)
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2196 if (crtc
->config
->double_wide
)
2197 val
&= ~PIPECONF_DOUBLE_WIDE
;
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2201 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2202 val
&= ~PIPECONF_ENABLE
;
2204 I915_WRITE(reg
, val
);
2205 if ((val
& PIPECONF_ENABLE
) == 0)
2206 intel_wait_for_pipe_off(crtc
);
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2213 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2216 struct drm_device
*dev
= dev_priv
->dev
;
2217 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2219 I915_WRITE(reg
, I915_READ(reg
));
2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
2228 * Enable @plane on @crtc, making sure that the pipe is running first.
2230 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2231 struct drm_crtc
*crtc
)
2233 struct drm_device
*dev
= plane
->dev
;
2234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2238 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2239 to_intel_plane_state(plane
->state
)->visible
= true;
2241 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2245 static bool need_vtd_wa(struct drm_device
*dev
)
2247 #ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2255 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2256 uint64_t fb_format_modifier
)
2258 unsigned int tile_height
;
2259 uint32_t pixel_bytes
;
2261 switch (fb_format_modifier
) {
2262 case DRM_FORMAT_MOD_NONE
:
2265 case I915_FORMAT_MOD_X_TILED
:
2266 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2268 case I915_FORMAT_MOD_Y_TILED
:
2271 case I915_FORMAT_MOD_Yf_TILED
:
2272 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2273 switch (pixel_bytes
) {
2287 "128-bit pixels are not supported for display!");
2293 MISSING_CASE(fb_format_modifier
);
2302 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2303 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2305 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2306 fb_format_modifier
));
2310 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2311 const struct drm_plane_state
*plane_state
)
2313 struct intel_rotation_info
*info
= &view
->rotation_info
;
2315 *view
= i915_ggtt_view_normal
;
2320 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2323 *view
= i915_ggtt_view_rotated
;
2325 info
->height
= fb
->height
;
2326 info
->pixel_format
= fb
->pixel_format
;
2327 info
->pitch
= fb
->pitches
[0];
2328 info
->fb_modifier
= fb
->modifier
[0];
2334 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2335 struct drm_framebuffer
*fb
,
2336 const struct drm_plane_state
*plane_state
,
2337 struct intel_engine_cs
*pipelined
)
2339 struct drm_device
*dev
= fb
->dev
;
2340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2341 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2342 struct i915_ggtt_view view
;
2346 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2348 switch (fb
->modifier
[0]) {
2349 case DRM_FORMAT_MOD_NONE
:
2350 if (INTEL_INFO(dev
)->gen
>= 9)
2351 alignment
= 256 * 1024;
2352 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2353 alignment
= 128 * 1024;
2354 else if (INTEL_INFO(dev
)->gen
>= 4)
2355 alignment
= 4 * 1024;
2357 alignment
= 64 * 1024;
2359 case I915_FORMAT_MOD_X_TILED
:
2360 if (INTEL_INFO(dev
)->gen
>= 9)
2361 alignment
= 256 * 1024;
2363 /* pin() will align the object as required by fence */
2367 case I915_FORMAT_MOD_Y_TILED
:
2368 case I915_FORMAT_MOD_Yf_TILED
:
2369 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2372 alignment
= 1 * 1024 * 1024;
2375 MISSING_CASE(fb
->modifier
[0]);
2379 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2388 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2389 alignment
= 256 * 1024;
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2398 intel_runtime_pm_get(dev_priv
);
2400 dev_priv
->mm
.interruptible
= false;
2401 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2404 goto err_interruptible
;
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2411 ret
= i915_gem_object_get_fence(obj
);
2415 i915_gem_object_pin_fence(obj
);
2417 dev_priv
->mm
.interruptible
= true;
2418 intel_runtime_pm_put(dev_priv
);
2422 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2424 dev_priv
->mm
.interruptible
= true;
2425 intel_runtime_pm_put(dev_priv
);
2429 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2430 const struct drm_plane_state
*plane_state
)
2432 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2433 struct i915_ggtt_view view
;
2436 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2438 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2439 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2441 i915_gem_object_unpin_fence(obj
);
2442 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2445 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
2447 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2448 unsigned int tiling_mode
,
2452 if (tiling_mode
!= I915_TILING_NONE
) {
2453 unsigned int tile_rows
, tiles
;
2458 tiles
= *x
/ (512/cpp
);
2461 return tile_rows
* pitch
* 8 + tiles
* 4096;
2463 unsigned int offset
;
2465 offset
= *y
* pitch
+ *x
* cpp
;
2467 *x
= (offset
& 4095) / cpp
;
2468 return offset
& -4096;
2472 static int i9xx_format_to_fourcc(int format
)
2475 case DISPPLANE_8BPP
:
2476 return DRM_FORMAT_C8
;
2477 case DISPPLANE_BGRX555
:
2478 return DRM_FORMAT_XRGB1555
;
2479 case DISPPLANE_BGRX565
:
2480 return DRM_FORMAT_RGB565
;
2482 case DISPPLANE_BGRX888
:
2483 return DRM_FORMAT_XRGB8888
;
2484 case DISPPLANE_RGBX888
:
2485 return DRM_FORMAT_XBGR8888
;
2486 case DISPPLANE_BGRX101010
:
2487 return DRM_FORMAT_XRGB2101010
;
2488 case DISPPLANE_RGBX101010
:
2489 return DRM_FORMAT_XBGR2101010
;
2493 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2496 case PLANE_CTL_FORMAT_RGB_565
:
2497 return DRM_FORMAT_RGB565
;
2499 case PLANE_CTL_FORMAT_XRGB_8888
:
2502 return DRM_FORMAT_ABGR8888
;
2504 return DRM_FORMAT_XBGR8888
;
2507 return DRM_FORMAT_ARGB8888
;
2509 return DRM_FORMAT_XRGB8888
;
2511 case PLANE_CTL_FORMAT_XRGB_2101010
:
2513 return DRM_FORMAT_XBGR2101010
;
2515 return DRM_FORMAT_XRGB2101010
;
2520 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2521 struct intel_initial_plane_config
*plane_config
)
2523 struct drm_device
*dev
= crtc
->base
.dev
;
2524 struct drm_i915_gem_object
*obj
= NULL
;
2525 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2526 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2527 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2528 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2531 size_aligned
-= base_aligned
;
2533 if (plane_config
->size
== 0)
2536 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2543 obj
->tiling_mode
= plane_config
->tiling
;
2544 if (obj
->tiling_mode
== I915_TILING_X
)
2545 obj
->stride
= fb
->pitches
[0];
2547 mode_cmd
.pixel_format
= fb
->pixel_format
;
2548 mode_cmd
.width
= fb
->width
;
2549 mode_cmd
.height
= fb
->height
;
2550 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2551 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2552 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2554 mutex_lock(&dev
->struct_mutex
);
2555 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2557 DRM_DEBUG_KMS("intel fb init failed\n");
2560 mutex_unlock(&dev
->struct_mutex
);
2562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2566 drm_gem_object_unreference(&obj
->base
);
2567 mutex_unlock(&dev
->struct_mutex
);
2571 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 update_state_fb(struct drm_plane
*plane
)
2575 if (plane
->fb
== plane
->state
->fb
)
2578 if (plane
->state
->fb
)
2579 drm_framebuffer_unreference(plane
->state
->fb
);
2580 plane
->state
->fb
= plane
->fb
;
2581 if (plane
->state
->fb
)
2582 drm_framebuffer_reference(plane
->state
->fb
);
2586 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2587 struct intel_initial_plane_config
*plane_config
)
2589 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2592 struct intel_crtc
*i
;
2593 struct drm_i915_gem_object
*obj
;
2594 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2595 struct drm_framebuffer
*fb
;
2597 if (!plane_config
->fb
)
2600 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2601 fb
= &plane_config
->fb
->base
;
2605 kfree(plane_config
->fb
);
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2611 for_each_crtc(dev
, c
) {
2612 i
= to_intel_crtc(c
);
2614 if (c
== &intel_crtc
->base
)
2620 fb
= c
->primary
->fb
;
2624 obj
= intel_fb_obj(fb
);
2625 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2626 drm_framebuffer_reference(fb
);
2634 obj
= intel_fb_obj(fb
);
2635 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2636 dev_priv
->preserve_bios_swizzle
= true;
2639 primary
->state
->crtc
= &intel_crtc
->base
;
2640 primary
->crtc
= &intel_crtc
->base
;
2641 update_state_fb(primary
);
2642 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2645 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2646 struct drm_framebuffer
*fb
,
2649 struct drm_device
*dev
= crtc
->dev
;
2650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2651 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2652 struct drm_plane
*primary
= crtc
->primary
;
2653 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2654 struct drm_i915_gem_object
*obj
;
2655 int plane
= intel_crtc
->plane
;
2656 unsigned long linear_offset
;
2658 u32 reg
= DSPCNTR(plane
);
2661 if (!visible
|| !fb
) {
2663 if (INTEL_INFO(dev
)->gen
>= 4)
2664 I915_WRITE(DSPSURF(plane
), 0);
2666 I915_WRITE(DSPADDR(plane
), 0);
2671 obj
= intel_fb_obj(fb
);
2672 if (WARN_ON(obj
== NULL
))
2675 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2677 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2679 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2681 if (INTEL_INFO(dev
)->gen
< 4) {
2682 if (intel_crtc
->pipe
== PIPE_B
)
2683 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2688 I915_WRITE(DSPSIZE(plane
),
2689 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2690 (intel_crtc
->config
->pipe_src_w
- 1));
2691 I915_WRITE(DSPPOS(plane
), 0);
2692 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2693 I915_WRITE(PRIMSIZE(plane
),
2694 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2695 (intel_crtc
->config
->pipe_src_w
- 1));
2696 I915_WRITE(PRIMPOS(plane
), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2700 switch (fb
->pixel_format
) {
2702 dspcntr
|= DISPPLANE_8BPP
;
2704 case DRM_FORMAT_XRGB1555
:
2705 case DRM_FORMAT_ARGB1555
:
2706 dspcntr
|= DISPPLANE_BGRX555
;
2708 case DRM_FORMAT_RGB565
:
2709 dspcntr
|= DISPPLANE_BGRX565
;
2711 case DRM_FORMAT_XRGB8888
:
2712 case DRM_FORMAT_ARGB8888
:
2713 dspcntr
|= DISPPLANE_BGRX888
;
2715 case DRM_FORMAT_XBGR8888
:
2716 case DRM_FORMAT_ABGR8888
:
2717 dspcntr
|= DISPPLANE_RGBX888
;
2719 case DRM_FORMAT_XRGB2101010
:
2720 case DRM_FORMAT_ARGB2101010
:
2721 dspcntr
|= DISPPLANE_BGRX101010
;
2723 case DRM_FORMAT_XBGR2101010
:
2724 case DRM_FORMAT_ABGR2101010
:
2725 dspcntr
|= DISPPLANE_RGBX101010
;
2731 if (INTEL_INFO(dev
)->gen
>= 4 &&
2732 obj
->tiling_mode
!= I915_TILING_NONE
)
2733 dspcntr
|= DISPPLANE_TILED
;
2736 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2738 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2740 if (INTEL_INFO(dev
)->gen
>= 4) {
2741 intel_crtc
->dspaddr_offset
=
2742 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2745 linear_offset
-= intel_crtc
->dspaddr_offset
;
2747 intel_crtc
->dspaddr_offset
= linear_offset
;
2750 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2751 dspcntr
|= DISPPLANE_ROTATE_180
;
2753 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2754 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2759 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2760 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2763 I915_WRITE(reg
, dspcntr
);
2765 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2766 if (INTEL_INFO(dev
)->gen
>= 4) {
2767 I915_WRITE(DSPSURF(plane
),
2768 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2769 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2770 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2772 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2776 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2777 struct drm_framebuffer
*fb
,
2780 struct drm_device
*dev
= crtc
->dev
;
2781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2783 struct drm_plane
*primary
= crtc
->primary
;
2784 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2785 struct drm_i915_gem_object
*obj
;
2786 int plane
= intel_crtc
->plane
;
2787 unsigned long linear_offset
;
2789 u32 reg
= DSPCNTR(plane
);
2792 if (!visible
|| !fb
) {
2794 I915_WRITE(DSPSURF(plane
), 0);
2799 obj
= intel_fb_obj(fb
);
2800 if (WARN_ON(obj
== NULL
))
2803 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2805 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2807 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2809 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2810 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2812 switch (fb
->pixel_format
) {
2814 dspcntr
|= DISPPLANE_8BPP
;
2816 case DRM_FORMAT_RGB565
:
2817 dspcntr
|= DISPPLANE_BGRX565
;
2819 case DRM_FORMAT_XRGB8888
:
2820 case DRM_FORMAT_ARGB8888
:
2821 dspcntr
|= DISPPLANE_BGRX888
;
2823 case DRM_FORMAT_XBGR8888
:
2824 case DRM_FORMAT_ABGR8888
:
2825 dspcntr
|= DISPPLANE_RGBX888
;
2827 case DRM_FORMAT_XRGB2101010
:
2828 case DRM_FORMAT_ARGB2101010
:
2829 dspcntr
|= DISPPLANE_BGRX101010
;
2831 case DRM_FORMAT_XBGR2101010
:
2832 case DRM_FORMAT_ABGR2101010
:
2833 dspcntr
|= DISPPLANE_RGBX101010
;
2839 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2840 dspcntr
|= DISPPLANE_TILED
;
2842 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2843 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2845 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2846 intel_crtc
->dspaddr_offset
=
2847 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2850 linear_offset
-= intel_crtc
->dspaddr_offset
;
2851 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2852 dspcntr
|= DISPPLANE_ROTATE_180
;
2854 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2855 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2856 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2861 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2862 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2866 I915_WRITE(reg
, dspcntr
);
2868 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2869 I915_WRITE(DSPSURF(plane
),
2870 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2871 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2872 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2874 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2875 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2880 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2881 uint32_t pixel_format
)
2883 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2890 switch (fb_modifier
) {
2891 case DRM_FORMAT_MOD_NONE
:
2893 case I915_FORMAT_MOD_X_TILED
:
2894 if (INTEL_INFO(dev
)->gen
== 2)
2897 case I915_FORMAT_MOD_Y_TILED
:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2903 case I915_FORMAT_MOD_Yf_TILED
:
2904 if (bits_per_pixel
== 8)
2909 MISSING_CASE(fb_modifier
);
2914 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2915 struct drm_i915_gem_object
*obj
)
2917 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2919 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2920 view
= &i915_ggtt_view_rotated
;
2922 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2928 void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2930 struct drm_device
*dev
;
2931 struct drm_i915_private
*dev_priv
;
2932 struct intel_crtc_scaler_state
*scaler_state
;
2935 if (!intel_crtc
|| !intel_crtc
->config
)
2938 dev
= intel_crtc
->base
.dev
;
2939 dev_priv
= dev
->dev_private
;
2940 scaler_state
= &intel_crtc
->config
->scaler_state
;
2942 /* loop through and disable scalers that aren't in use */
2943 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2944 if (!scaler_state
->scalers
[i
].in_use
) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2954 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2958 switch (pixel_format
) {
2959 case DRM_FORMAT_RGB565
:
2960 format
= PLANE_CTL_FORMAT_RGB_565
;
2962 case DRM_FORMAT_XBGR8888
:
2963 format
= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2965 case DRM_FORMAT_XRGB8888
:
2966 format
= PLANE_CTL_FORMAT_XRGB_8888
;
2969 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2970 * to be already pre-multiplied. We need to add a knob (or a different
2971 * DRM_FORMAT) for user-space to configure that.
2973 case DRM_FORMAT_ABGR8888
:
2974 format
= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2977 case DRM_FORMAT_ARGB8888
:
2978 format
= PLANE_CTL_FORMAT_XRGB_8888
|
2979 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2981 case DRM_FORMAT_XRGB2101010
:
2982 format
= PLANE_CTL_FORMAT_XRGB_2101010
;
2984 case DRM_FORMAT_XBGR2101010
:
2985 format
= PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2987 case DRM_FORMAT_YUYV
:
2988 format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2990 case DRM_FORMAT_YVYU
:
2991 format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2993 case DRM_FORMAT_UYVY
:
2994 format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2996 case DRM_FORMAT_VYUY
:
2997 format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3006 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3008 u32 plane_ctl_tiling
= 0;
3010 switch (fb_modifier
) {
3011 case DRM_FORMAT_MOD_NONE
:
3013 case I915_FORMAT_MOD_X_TILED
:
3014 plane_ctl_tiling
= PLANE_CTL_TILED_X
;
3016 case I915_FORMAT_MOD_Y_TILED
:
3017 plane_ctl_tiling
= PLANE_CTL_TILED_Y
;
3019 case I915_FORMAT_MOD_Yf_TILED
:
3020 plane_ctl_tiling
= PLANE_CTL_TILED_YF
;
3023 MISSING_CASE(fb_modifier
);
3026 return plane_ctl_tiling
;
3029 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3031 u32 plane_ctl_rotation
= 0;
3034 case BIT(DRM_ROTATE_0
):
3036 case BIT(DRM_ROTATE_90
):
3037 plane_ctl_rotation
= PLANE_CTL_ROTATE_90
;
3039 case BIT(DRM_ROTATE_180
):
3040 plane_ctl_rotation
= PLANE_CTL_ROTATE_180
;
3042 case BIT(DRM_ROTATE_270
):
3043 plane_ctl_rotation
= PLANE_CTL_ROTATE_270
;
3046 MISSING_CASE(rotation
);
3049 return plane_ctl_rotation
;
3052 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3053 struct drm_framebuffer
*fb
,
3056 struct drm_device
*dev
= crtc
->dev
;
3057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3058 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3059 struct drm_plane
*plane
= crtc
->primary
;
3060 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3061 struct drm_i915_gem_object
*obj
;
3062 int pipe
= intel_crtc
->pipe
;
3063 u32 plane_ctl
, stride_div
, stride
;
3064 u32 tile_height
, plane_offset
, plane_size
;
3065 unsigned int rotation
;
3066 int x_offset
, y_offset
;
3067 unsigned long surf_addr
;
3068 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3069 struct intel_plane_state
*plane_state
;
3070 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3071 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3074 plane_state
= to_intel_plane_state(plane
->state
);
3076 if (!visible
|| !fb
) {
3077 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3078 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3079 POSTING_READ(PLANE_CTL(pipe
, 0));
3083 plane_ctl
= PLANE_CTL_ENABLE
|
3084 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3085 PLANE_CTL_PIPE_CSC_ENABLE
;
3087 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3088 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3089 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3091 rotation
= plane
->state
->rotation
;
3092 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3094 obj
= intel_fb_obj(fb
);
3095 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3097 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3100 * FIXME: intel_plane_state->src, dst aren't set when transitional
3101 * update_plane helpers are called from legacy paths.
3102 * Once full atomic crtc is available, below check can be avoided.
3104 if (drm_rect_width(&plane_state
->src
)) {
3105 scaler_id
= plane_state
->scaler_id
;
3106 src_x
= plane_state
->src
.x1
>> 16;
3107 src_y
= plane_state
->src
.y1
>> 16;
3108 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3109 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3110 dst_x
= plane_state
->dst
.x1
;
3111 dst_y
= plane_state
->dst
.y1
;
3112 dst_w
= drm_rect_width(&plane_state
->dst
);
3113 dst_h
= drm_rect_height(&plane_state
->dst
);
3115 WARN_ON(x
!= src_x
|| y
!= src_y
);
3117 src_w
= intel_crtc
->config
->pipe_src_w
;
3118 src_h
= intel_crtc
->config
->pipe_src_h
;
3121 if (intel_rotation_90_or_270(rotation
)) {
3122 /* stride = Surface height in tiles */
3123 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3125 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3126 x_offset
= stride
* tile_height
- y
- src_h
;
3128 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3130 stride
= fb
->pitches
[0] / stride_div
;
3133 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3135 plane_offset
= y_offset
<< 16 | x_offset
;
3137 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3138 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3139 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3140 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3142 if (scaler_id
>= 0) {
3143 uint32_t ps_ctrl
= 0;
3145 WARN_ON(!dst_w
|| !dst_h
);
3146 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3147 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3148 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3149 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3150 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3151 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3152 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3154 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3157 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3159 POSTING_READ(PLANE_SURF(pipe
, 0));
3162 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3164 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3165 int x
, int y
, enum mode_set_atomic state
)
3167 struct drm_device
*dev
= crtc
->dev
;
3168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3170 if (dev_priv
->display
.disable_fbc
)
3171 dev_priv
->display
.disable_fbc(dev
);
3173 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3178 static void intel_complete_page_flips(struct drm_device
*dev
)
3180 struct drm_crtc
*crtc
;
3182 for_each_crtc(dev
, crtc
) {
3183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3184 enum plane plane
= intel_crtc
->plane
;
3186 intel_prepare_page_flip(dev
, plane
);
3187 intel_finish_page_flip_plane(dev
, plane
);
3191 static void intel_update_primary_planes(struct drm_device
*dev
)
3193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3194 struct drm_crtc
*crtc
;
3196 for_each_crtc(dev
, crtc
) {
3197 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3199 drm_modeset_lock(&crtc
->mutex
, NULL
);
3201 * FIXME: Once we have proper support for primary planes (and
3202 * disabling them without disabling the entire crtc) allow again
3203 * a NULL crtc->primary->fb.
3205 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3206 dev_priv
->display
.update_primary_plane(crtc
,
3210 drm_modeset_unlock(&crtc
->mutex
);
3214 void intel_crtc_reset(struct intel_crtc
*crtc
)
3216 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3221 intel_crtc_disable_planes(&crtc
->base
);
3222 dev_priv
->display
.crtc_disable(&crtc
->base
);
3223 dev_priv
->display
.crtc_enable(&crtc
->base
);
3224 intel_crtc_enable_planes(&crtc
->base
);
3227 void intel_prepare_reset(struct drm_device
*dev
)
3229 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3230 struct intel_crtc
*crtc
;
3232 /* no reset support for gen2 */
3236 /* reset doesn't touch the display */
3237 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3240 drm_modeset_lock_all(dev
);
3243 * Disabling the crtcs gracefully seems nicer. Also the
3244 * g33 docs say we should at least disable all the planes.
3246 for_each_intel_crtc(dev
, crtc
) {
3250 intel_crtc_disable_planes(&crtc
->base
);
3251 dev_priv
->display
.crtc_disable(&crtc
->base
);
3255 void intel_finish_reset(struct drm_device
*dev
)
3257 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3260 * Flips in the rings will be nuked by the reset,
3261 * so complete all pending flips so that user space
3262 * will get its events and not get stuck.
3264 intel_complete_page_flips(dev
);
3266 /* no reset support for gen2 */
3270 /* reset doesn't touch the display */
3271 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3273 * Flips in the rings have been nuked by the reset,
3274 * so update the base address of all primary
3275 * planes to the the last fb to make sure we're
3276 * showing the correct fb after a reset.
3278 intel_update_primary_planes(dev
);
3283 * The display has been reset as well,
3284 * so need a full re-initialization.
3286 intel_runtime_pm_disable_interrupts(dev_priv
);
3287 intel_runtime_pm_enable_interrupts(dev_priv
);
3289 intel_modeset_init_hw(dev
);
3291 spin_lock_irq(&dev_priv
->irq_lock
);
3292 if (dev_priv
->display
.hpd_irq_setup
)
3293 dev_priv
->display
.hpd_irq_setup(dev
);
3294 spin_unlock_irq(&dev_priv
->irq_lock
);
3296 intel_modeset_setup_hw_state(dev
, true);
3298 intel_hpd_init(dev_priv
);
3300 drm_modeset_unlock_all(dev
);
3304 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3306 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3307 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3308 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3311 /* Big Hammer, we also need to ensure that any pending
3312 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3313 * current scanout is retired before unpinning the old
3314 * framebuffer. Note that we rely on userspace rendering
3315 * into the buffer attached to the pipe they are waiting
3316 * on. If not, userspace generates a GPU hang with IPEHR
3317 * point to the MI_WAIT_FOR_EVENT.
3319 * This should only fail upon a hung GPU, in which case we
3320 * can safely continue.
3322 dev_priv
->mm
.interruptible
= false;
3323 ret
= i915_gem_object_wait_rendering(obj
, true);
3324 dev_priv
->mm
.interruptible
= was_interruptible
;
3329 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3331 struct drm_device
*dev
= crtc
->dev
;
3332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3333 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3336 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3337 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3340 spin_lock_irq(&dev
->event_lock
);
3341 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3342 spin_unlock_irq(&dev
->event_lock
);
3347 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3349 struct drm_device
*dev
= crtc
->base
.dev
;
3350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3351 const struct drm_display_mode
*adjusted_mode
;
3357 * Update pipe size and adjust fitter if needed: the reason for this is
3358 * that in compute_mode_changes we check the native mode (not the pfit
3359 * mode) to see if we can flip rather than do a full mode set. In the
3360 * fastboot case, we'll flip, but if we don't update the pipesrc and
3361 * pfit state, we'll end up with a big fb scanned out into the wrong
3364 * To fix this properly, we need to hoist the checks up into
3365 * compute_mode_changes (or above), check the actual pfit state and
3366 * whether the platform allows pfit disable with pipe active, and only
3367 * then update the pipesrc and pfit state, even on the flip path.
3370 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3372 I915_WRITE(PIPESRC(crtc
->pipe
),
3373 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3374 (adjusted_mode
->crtc_vdisplay
- 1));
3375 if (!crtc
->config
->pch_pfit
.enabled
&&
3376 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3377 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3378 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3379 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3380 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3382 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3383 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3386 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3388 struct drm_device
*dev
= crtc
->dev
;
3389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3390 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3391 int pipe
= intel_crtc
->pipe
;
3394 /* enable normal train */
3395 reg
= FDI_TX_CTL(pipe
);
3396 temp
= I915_READ(reg
);
3397 if (IS_IVYBRIDGE(dev
)) {
3398 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3399 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3401 temp
&= ~FDI_LINK_TRAIN_NONE
;
3402 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3404 I915_WRITE(reg
, temp
);
3406 reg
= FDI_RX_CTL(pipe
);
3407 temp
= I915_READ(reg
);
3408 if (HAS_PCH_CPT(dev
)) {
3409 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3410 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3412 temp
&= ~FDI_LINK_TRAIN_NONE
;
3413 temp
|= FDI_LINK_TRAIN_NONE
;
3415 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3417 /* wait one idle pattern time */
3421 /* IVB wants error correction enabled */
3422 if (IS_IVYBRIDGE(dev
))
3423 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3424 FDI_FE_ERRC_ENABLE
);
3427 /* The FDI link training functions for ILK/Ibexpeak. */
3428 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3430 struct drm_device
*dev
= crtc
->dev
;
3431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3433 int pipe
= intel_crtc
->pipe
;
3434 u32 reg
, temp
, tries
;
3436 /* FDI needs bits from pipe first */
3437 assert_pipe_enabled(dev_priv
, pipe
);
3439 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3441 reg
= FDI_RX_IMR(pipe
);
3442 temp
= I915_READ(reg
);
3443 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3444 temp
&= ~FDI_RX_BIT_LOCK
;
3445 I915_WRITE(reg
, temp
);
3449 /* enable CPU FDI TX and PCH FDI RX */
3450 reg
= FDI_TX_CTL(pipe
);
3451 temp
= I915_READ(reg
);
3452 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3453 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3454 temp
&= ~FDI_LINK_TRAIN_NONE
;
3455 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3456 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3458 reg
= FDI_RX_CTL(pipe
);
3459 temp
= I915_READ(reg
);
3460 temp
&= ~FDI_LINK_TRAIN_NONE
;
3461 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3462 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3467 /* Ironlake workaround, enable clock pointer after FDI enable*/
3468 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3469 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3470 FDI_RX_PHASE_SYNC_POINTER_EN
);
3472 reg
= FDI_RX_IIR(pipe
);
3473 for (tries
= 0; tries
< 5; tries
++) {
3474 temp
= I915_READ(reg
);
3475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3477 if ((temp
& FDI_RX_BIT_LOCK
)) {
3478 DRM_DEBUG_KMS("FDI train 1 done.\n");
3479 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3484 DRM_ERROR("FDI train 1 fail!\n");
3487 reg
= FDI_TX_CTL(pipe
);
3488 temp
= I915_READ(reg
);
3489 temp
&= ~FDI_LINK_TRAIN_NONE
;
3490 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3491 I915_WRITE(reg
, temp
);
3493 reg
= FDI_RX_CTL(pipe
);
3494 temp
= I915_READ(reg
);
3495 temp
&= ~FDI_LINK_TRAIN_NONE
;
3496 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3497 I915_WRITE(reg
, temp
);
3502 reg
= FDI_RX_IIR(pipe
);
3503 for (tries
= 0; tries
< 5; tries
++) {
3504 temp
= I915_READ(reg
);
3505 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3507 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3508 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3509 DRM_DEBUG_KMS("FDI train 2 done.\n");
3514 DRM_ERROR("FDI train 2 fail!\n");
3516 DRM_DEBUG_KMS("FDI train done\n");
3520 static const int snb_b_fdi_train_param
[] = {
3521 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3522 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3523 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3524 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3527 /* The FDI link training functions for SNB/Cougarpoint. */
3528 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3530 struct drm_device
*dev
= crtc
->dev
;
3531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3532 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3533 int pipe
= intel_crtc
->pipe
;
3534 u32 reg
, temp
, i
, retry
;
3536 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3538 reg
= FDI_RX_IMR(pipe
);
3539 temp
= I915_READ(reg
);
3540 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3541 temp
&= ~FDI_RX_BIT_LOCK
;
3542 I915_WRITE(reg
, temp
);
3547 /* enable CPU FDI TX and PCH FDI RX */
3548 reg
= FDI_TX_CTL(pipe
);
3549 temp
= I915_READ(reg
);
3550 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3551 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3552 temp
&= ~FDI_LINK_TRAIN_NONE
;
3553 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3554 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3556 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3557 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3559 I915_WRITE(FDI_RX_MISC(pipe
),
3560 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3562 reg
= FDI_RX_CTL(pipe
);
3563 temp
= I915_READ(reg
);
3564 if (HAS_PCH_CPT(dev
)) {
3565 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3566 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3568 temp
&= ~FDI_LINK_TRAIN_NONE
;
3569 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3571 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3576 for (i
= 0; i
< 4; i
++) {
3577 reg
= FDI_TX_CTL(pipe
);
3578 temp
= I915_READ(reg
);
3579 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3580 temp
|= snb_b_fdi_train_param
[i
];
3581 I915_WRITE(reg
, temp
);
3586 for (retry
= 0; retry
< 5; retry
++) {
3587 reg
= FDI_RX_IIR(pipe
);
3588 temp
= I915_READ(reg
);
3589 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3590 if (temp
& FDI_RX_BIT_LOCK
) {
3591 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3592 DRM_DEBUG_KMS("FDI train 1 done.\n");
3601 DRM_ERROR("FDI train 1 fail!\n");
3604 reg
= FDI_TX_CTL(pipe
);
3605 temp
= I915_READ(reg
);
3606 temp
&= ~FDI_LINK_TRAIN_NONE
;
3607 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3609 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3611 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3613 I915_WRITE(reg
, temp
);
3615 reg
= FDI_RX_CTL(pipe
);
3616 temp
= I915_READ(reg
);
3617 if (HAS_PCH_CPT(dev
)) {
3618 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3619 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3621 temp
&= ~FDI_LINK_TRAIN_NONE
;
3622 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3624 I915_WRITE(reg
, temp
);
3629 for (i
= 0; i
< 4; i
++) {
3630 reg
= FDI_TX_CTL(pipe
);
3631 temp
= I915_READ(reg
);
3632 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3633 temp
|= snb_b_fdi_train_param
[i
];
3634 I915_WRITE(reg
, temp
);
3639 for (retry
= 0; retry
< 5; retry
++) {
3640 reg
= FDI_RX_IIR(pipe
);
3641 temp
= I915_READ(reg
);
3642 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3643 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3644 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3645 DRM_DEBUG_KMS("FDI train 2 done.\n");
3654 DRM_ERROR("FDI train 2 fail!\n");
3656 DRM_DEBUG_KMS("FDI train done.\n");
3659 /* Manual link training for Ivy Bridge A0 parts */
3660 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3662 struct drm_device
*dev
= crtc
->dev
;
3663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3664 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3665 int pipe
= intel_crtc
->pipe
;
3666 u32 reg
, temp
, i
, j
;
3668 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3670 reg
= FDI_RX_IMR(pipe
);
3671 temp
= I915_READ(reg
);
3672 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3673 temp
&= ~FDI_RX_BIT_LOCK
;
3674 I915_WRITE(reg
, temp
);
3679 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3680 I915_READ(FDI_RX_IIR(pipe
)));
3682 /* Try each vswing and preemphasis setting twice before moving on */
3683 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3684 /* disable first in case we need to retry */
3685 reg
= FDI_TX_CTL(pipe
);
3686 temp
= I915_READ(reg
);
3687 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3688 temp
&= ~FDI_TX_ENABLE
;
3689 I915_WRITE(reg
, temp
);
3691 reg
= FDI_RX_CTL(pipe
);
3692 temp
= I915_READ(reg
);
3693 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3694 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3695 temp
&= ~FDI_RX_ENABLE
;
3696 I915_WRITE(reg
, temp
);
3698 /* enable CPU FDI TX and PCH FDI RX */
3699 reg
= FDI_TX_CTL(pipe
);
3700 temp
= I915_READ(reg
);
3701 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3702 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3703 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3704 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3705 temp
|= snb_b_fdi_train_param
[j
/2];
3706 temp
|= FDI_COMPOSITE_SYNC
;
3707 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3709 I915_WRITE(FDI_RX_MISC(pipe
),
3710 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3712 reg
= FDI_RX_CTL(pipe
);
3713 temp
= I915_READ(reg
);
3714 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3715 temp
|= FDI_COMPOSITE_SYNC
;
3716 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3719 udelay(1); /* should be 0.5us */
3721 for (i
= 0; i
< 4; i
++) {
3722 reg
= FDI_RX_IIR(pipe
);
3723 temp
= I915_READ(reg
);
3724 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3726 if (temp
& FDI_RX_BIT_LOCK
||
3727 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3728 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3729 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3733 udelay(1); /* should be 0.5us */
3736 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3741 reg
= FDI_TX_CTL(pipe
);
3742 temp
= I915_READ(reg
);
3743 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3744 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3745 I915_WRITE(reg
, temp
);
3747 reg
= FDI_RX_CTL(pipe
);
3748 temp
= I915_READ(reg
);
3749 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3750 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3751 I915_WRITE(reg
, temp
);
3754 udelay(2); /* should be 1.5us */
3756 for (i
= 0; i
< 4; i
++) {
3757 reg
= FDI_RX_IIR(pipe
);
3758 temp
= I915_READ(reg
);
3759 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3761 if (temp
& FDI_RX_SYMBOL_LOCK
||
3762 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3763 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3764 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3768 udelay(2); /* should be 1.5us */
3771 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3775 DRM_DEBUG_KMS("FDI train done.\n");
3778 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3780 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 int pipe
= intel_crtc
->pipe
;
3786 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3787 reg
= FDI_RX_CTL(pipe
);
3788 temp
= I915_READ(reg
);
3789 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3790 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3791 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3792 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3797 /* Switch from Rawclk to PCDclk */
3798 temp
= I915_READ(reg
);
3799 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3804 /* Enable CPU FDI TX PLL, always on for Ironlake */
3805 reg
= FDI_TX_CTL(pipe
);
3806 temp
= I915_READ(reg
);
3807 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3808 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3815 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3817 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3819 int pipe
= intel_crtc
->pipe
;
3822 /* Switch from PCDclk to Rawclk */
3823 reg
= FDI_RX_CTL(pipe
);
3824 temp
= I915_READ(reg
);
3825 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3827 /* Disable CPU FDI TX PLL */
3828 reg
= FDI_TX_CTL(pipe
);
3829 temp
= I915_READ(reg
);
3830 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3835 reg
= FDI_RX_CTL(pipe
);
3836 temp
= I915_READ(reg
);
3837 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3839 /* Wait for the clocks to turn off. */
3844 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3846 struct drm_device
*dev
= crtc
->dev
;
3847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3849 int pipe
= intel_crtc
->pipe
;
3852 /* disable CPU FDI tx and PCH FDI rx */
3853 reg
= FDI_TX_CTL(pipe
);
3854 temp
= I915_READ(reg
);
3855 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3858 reg
= FDI_RX_CTL(pipe
);
3859 temp
= I915_READ(reg
);
3860 temp
&= ~(0x7 << 16);
3861 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3862 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3867 /* Ironlake workaround, disable clock pointer after downing FDI */
3868 if (HAS_PCH_IBX(dev
))
3869 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3871 /* still set train pattern 1 */
3872 reg
= FDI_TX_CTL(pipe
);
3873 temp
= I915_READ(reg
);
3874 temp
&= ~FDI_LINK_TRAIN_NONE
;
3875 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3876 I915_WRITE(reg
, temp
);
3878 reg
= FDI_RX_CTL(pipe
);
3879 temp
= I915_READ(reg
);
3880 if (HAS_PCH_CPT(dev
)) {
3881 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3882 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3884 temp
&= ~FDI_LINK_TRAIN_NONE
;
3885 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3887 /* BPC in FDI rx is consistent with that in PIPECONF */
3888 temp
&= ~(0x07 << 16);
3889 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3890 I915_WRITE(reg
, temp
);
3896 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3898 struct intel_crtc
*crtc
;
3900 /* Note that we don't need to be called with mode_config.lock here
3901 * as our list of CRTC objects is static for the lifetime of the
3902 * device and so cannot disappear as we iterate. Similarly, we can
3903 * happily treat the predicates as racy, atomic checks as userspace
3904 * cannot claim and pin a new fb without at least acquring the
3905 * struct_mutex and so serialising with us.
3907 for_each_intel_crtc(dev
, crtc
) {
3908 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3911 if (crtc
->unpin_work
)
3912 intel_wait_for_vblank(dev
, crtc
->pipe
);
3920 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3922 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3923 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3925 /* ensure that the unpin work is consistent wrt ->pending. */
3927 intel_crtc
->unpin_work
= NULL
;
3930 drm_send_vblank_event(intel_crtc
->base
.dev
,
3934 drm_crtc_vblank_put(&intel_crtc
->base
);
3936 wake_up_all(&dev_priv
->pending_flip_queue
);
3937 queue_work(dev_priv
->wq
, &work
->work
);
3939 trace_i915_flip_complete(intel_crtc
->plane
,
3940 work
->pending_flip_obj
);
3943 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3945 struct drm_device
*dev
= crtc
->dev
;
3946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3948 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3949 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3950 !intel_crtc_has_pending_flip(crtc
),
3952 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3954 spin_lock_irq(&dev
->event_lock
);
3955 if (intel_crtc
->unpin_work
) {
3956 WARN_ONCE(1, "Removing stuck page flip\n");
3957 page_flip_completed(intel_crtc
);
3959 spin_unlock_irq(&dev
->event_lock
);
3962 if (crtc
->primary
->fb
) {
3963 mutex_lock(&dev
->struct_mutex
);
3964 intel_finish_fb(crtc
->primary
->fb
);
3965 mutex_unlock(&dev
->struct_mutex
);
3969 /* Program iCLKIP clock to the desired frequency */
3970 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3972 struct drm_device
*dev
= crtc
->dev
;
3973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3974 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3975 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3978 mutex_lock(&dev_priv
->dpio_lock
);
3980 /* It is necessary to ungate the pixclk gate prior to programming
3981 * the divisors, and gate it back when it is done.
3983 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3985 /* Disable SSCCTL */
3986 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3987 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3991 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3992 if (clock
== 20000) {
3997 /* The iCLK virtual clock root frequency is in MHz,
3998 * but the adjusted_mode->crtc_clock in in KHz. To get the
3999 * divisors, it is necessary to divide one by another, so we
4000 * convert the virtual clock precision to KHz here for higher
4003 u32 iclk_virtual_root_freq
= 172800 * 1000;
4004 u32 iclk_pi_range
= 64;
4005 u32 desired_divisor
, msb_divisor_value
, pi_value
;
4007 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
4008 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
4009 pi_value
= desired_divisor
% iclk_pi_range
;
4012 divsel
= msb_divisor_value
- 2;
4013 phaseinc
= pi_value
;
4016 /* This should not happen with any sane values */
4017 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4018 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4019 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4020 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4022 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4029 /* Program SSCDIVINTPHASE6 */
4030 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4031 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4032 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4033 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4034 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4035 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4036 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4037 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4039 /* Program SSCAUXDIV */
4040 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4041 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4042 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4043 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4045 /* Enable modulator and associated divider */
4046 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4047 temp
&= ~SBI_SSCCTL_DISABLE
;
4048 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4050 /* Wait for initialization time */
4053 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4055 mutex_unlock(&dev_priv
->dpio_lock
);
4058 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4059 enum pipe pch_transcoder
)
4061 struct drm_device
*dev
= crtc
->base
.dev
;
4062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4063 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4065 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4066 I915_READ(HTOTAL(cpu_transcoder
)));
4067 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4068 I915_READ(HBLANK(cpu_transcoder
)));
4069 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4070 I915_READ(HSYNC(cpu_transcoder
)));
4072 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4073 I915_READ(VTOTAL(cpu_transcoder
)));
4074 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4075 I915_READ(VBLANK(cpu_transcoder
)));
4076 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4077 I915_READ(VSYNC(cpu_transcoder
)));
4078 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4079 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4082 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4087 temp
= I915_READ(SOUTH_CHICKEN1
);
4088 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4091 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4092 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4094 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4096 temp
|= FDI_BC_BIFURCATION_SELECT
;
4098 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4099 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4100 POSTING_READ(SOUTH_CHICKEN1
);
4103 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4105 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4107 switch (intel_crtc
->pipe
) {
4111 if (intel_crtc
->config
->fdi_lanes
> 2)
4112 cpt_set_fdi_bc_bifurcation(dev
, false);
4114 cpt_set_fdi_bc_bifurcation(dev
, true);
4118 cpt_set_fdi_bc_bifurcation(dev
, true);
4127 * Enable PCH resources required for PCH ports:
4129 * - FDI training & RX/TX
4130 * - update transcoder timings
4131 * - DP transcoding bits
4134 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4136 struct drm_device
*dev
= crtc
->dev
;
4137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4138 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4139 int pipe
= intel_crtc
->pipe
;
4142 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4144 if (IS_IVYBRIDGE(dev
))
4145 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4147 /* Write the TU size bits before fdi link training, so that error
4148 * detection works. */
4149 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4150 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4152 /* For PCH output, training FDI link */
4153 dev_priv
->display
.fdi_link_train(crtc
);
4155 /* We need to program the right clock selection before writing the pixel
4156 * mutliplier into the DPLL. */
4157 if (HAS_PCH_CPT(dev
)) {
4160 temp
= I915_READ(PCH_DPLL_SEL
);
4161 temp
|= TRANS_DPLL_ENABLE(pipe
);
4162 sel
= TRANS_DPLLB_SEL(pipe
);
4163 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4167 I915_WRITE(PCH_DPLL_SEL
, temp
);
4170 /* XXX: pch pll's can be enabled any time before we enable the PCH
4171 * transcoder, and we actually should do this to not upset any PCH
4172 * transcoder that already use the clock when we share it.
4174 * Note that enable_shared_dpll tries to do the right thing, but
4175 * get_shared_dpll unconditionally resets the pll - we need that to have
4176 * the right LVDS enable sequence. */
4177 intel_enable_shared_dpll(intel_crtc
);
4179 /* set transcoder timing, panel must allow it */
4180 assert_panel_unlocked(dev_priv
, pipe
);
4181 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4183 intel_fdi_normal_train(crtc
);
4185 /* For PCH DP, enable TRANS_DP_CTL */
4186 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4187 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4188 reg
= TRANS_DP_CTL(pipe
);
4189 temp
= I915_READ(reg
);
4190 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4191 TRANS_DP_SYNC_MASK
|
4193 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
4194 TRANS_DP_ENH_FRAMING
);
4195 temp
|= bpc
<< 9; /* same format but at 11:9 */
4197 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4198 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4199 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4200 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4202 switch (intel_trans_dp_port_sel(crtc
)) {
4204 temp
|= TRANS_DP_PORT_SEL_B
;
4207 temp
|= TRANS_DP_PORT_SEL_C
;
4210 temp
|= TRANS_DP_PORT_SEL_D
;
4216 I915_WRITE(reg
, temp
);
4219 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4222 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4224 struct drm_device
*dev
= crtc
->dev
;
4225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4226 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4227 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4229 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4231 lpt_program_iclkip(crtc
);
4233 /* Set transcoder timing. */
4234 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4236 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4239 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4241 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4246 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4247 WARN(1, "bad %s crtc mask\n", pll
->name
);
4251 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4252 if (pll
->config
.crtc_mask
== 0) {
4254 WARN_ON(pll
->active
);
4257 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4260 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4261 struct intel_crtc_state
*crtc_state
)
4263 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4264 struct intel_shared_dpll
*pll
;
4265 enum intel_dpll_id i
;
4267 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4268 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4269 i
= (enum intel_dpll_id
) crtc
->pipe
;
4270 pll
= &dev_priv
->shared_dplls
[i
];
4272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4273 crtc
->base
.base
.id
, pll
->name
);
4275 WARN_ON(pll
->new_config
->crtc_mask
);
4280 if (IS_BROXTON(dev_priv
->dev
)) {
4281 /* PLL is attached to port in bxt */
4282 struct intel_encoder
*encoder
;
4283 struct intel_digital_port
*intel_dig_port
;
4285 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4286 if (WARN_ON(!encoder
))
4289 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4290 /* 1:1 mapping between ports and PLLs */
4291 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4292 pll
= &dev_priv
->shared_dplls
[i
];
4293 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4294 crtc
->base
.base
.id
, pll
->name
);
4295 WARN_ON(pll
->new_config
->crtc_mask
);
4300 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4301 pll
= &dev_priv
->shared_dplls
[i
];
4303 /* Only want to check enabled timings first */
4304 if (pll
->new_config
->crtc_mask
== 0)
4307 if (memcmp(&crtc_state
->dpll_hw_state
,
4308 &pll
->new_config
->hw_state
,
4309 sizeof(pll
->new_config
->hw_state
)) == 0) {
4310 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4311 crtc
->base
.base
.id
, pll
->name
,
4312 pll
->new_config
->crtc_mask
,
4318 /* Ok no matching timings, maybe there's a free one? */
4319 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4320 pll
= &dev_priv
->shared_dplls
[i
];
4321 if (pll
->new_config
->crtc_mask
== 0) {
4322 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4323 crtc
->base
.base
.id
, pll
->name
);
4331 if (pll
->new_config
->crtc_mask
== 0)
4332 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4334 crtc_state
->shared_dpll
= i
;
4335 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4336 pipe_name(crtc
->pipe
));
4338 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4344 * intel_shared_dpll_start_config - start a new PLL staged config
4345 * @dev_priv: DRM device
4346 * @clear_pipes: mask of pipes that will have their PLLs freed
4348 * Starts a new PLL staged config, copying the current config but
4349 * releasing the references of pipes specified in clear_pipes.
4351 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4352 unsigned clear_pipes
)
4354 struct intel_shared_dpll
*pll
;
4355 enum intel_dpll_id i
;
4357 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4358 pll
= &dev_priv
->shared_dplls
[i
];
4360 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4362 if (!pll
->new_config
)
4365 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4372 pll
= &dev_priv
->shared_dplls
[i
];
4373 kfree(pll
->new_config
);
4374 pll
->new_config
= NULL
;
4380 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4382 struct intel_shared_dpll
*pll
;
4383 enum intel_dpll_id i
;
4385 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4386 pll
= &dev_priv
->shared_dplls
[i
];
4388 WARN_ON(pll
->new_config
== &pll
->config
);
4390 pll
->config
= *pll
->new_config
;
4391 kfree(pll
->new_config
);
4392 pll
->new_config
= NULL
;
4396 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4398 struct intel_shared_dpll
*pll
;
4399 enum intel_dpll_id i
;
4401 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4402 pll
= &dev_priv
->shared_dplls
[i
];
4404 WARN_ON(pll
->new_config
== &pll
->config
);
4406 kfree(pll
->new_config
);
4407 pll
->new_config
= NULL
;
4411 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4414 int dslreg
= PIPEDSL(pipe
);
4417 temp
= I915_READ(dslreg
);
4419 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4420 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4421 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4426 * skl_update_scaler_users - Stages update to crtc's scaler state
4428 * @crtc_state: crtc_state
4429 * @plane: plane (NULL indicates crtc is requesting update)
4430 * @plane_state: plane's state
4431 * @force_detach: request unconditional detachment of scaler
4433 * This function updates scaler state for requested plane or crtc.
4434 * To request scaler usage update for a plane, caller shall pass plane pointer.
4435 * To request scaler usage update for crtc, caller shall pass plane pointer
4439 * 0 - scaler_usage updated successfully
4440 * error - requested scaling cannot be supported or other error condition
4443 skl_update_scaler_users(
4444 struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
,
4445 struct intel_plane
*intel_plane
, struct intel_plane_state
*plane_state
,
4450 int src_w
, src_h
, dst_w
, dst_h
;
4452 struct drm_framebuffer
*fb
;
4453 struct intel_crtc_scaler_state
*scaler_state
;
4454 unsigned int rotation
;
4456 if (!intel_crtc
|| !crtc_state
)
4459 scaler_state
= &crtc_state
->scaler_state
;
4461 idx
= intel_plane
? drm_plane_index(&intel_plane
->base
) : SKL_CRTC_INDEX
;
4462 fb
= intel_plane
? plane_state
->base
.fb
: NULL
;
4465 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
4466 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
4467 dst_w
= drm_rect_width(&plane_state
->dst
);
4468 dst_h
= drm_rect_height(&plane_state
->dst
);
4469 scaler_id
= &plane_state
->scaler_id
;
4470 rotation
= plane_state
->base
.rotation
;
4472 struct drm_display_mode
*adjusted_mode
=
4473 &crtc_state
->base
.adjusted_mode
;
4474 src_w
= crtc_state
->pipe_src_w
;
4475 src_h
= crtc_state
->pipe_src_h
;
4476 dst_w
= adjusted_mode
->hdisplay
;
4477 dst_h
= adjusted_mode
->vdisplay
;
4478 scaler_id
= &scaler_state
->scaler_id
;
4479 rotation
= DRM_ROTATE_0
;
4482 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4483 (src_h
!= dst_w
|| src_w
!= dst_h
):
4484 (src_w
!= dst_w
|| src_h
!= dst_h
);
4487 * if plane is being disabled or scaler is no more required or force detach
4488 * - free scaler binded to this plane/crtc
4489 * - in order to do this, update crtc->scaler_usage
4491 * Here scaler state in crtc_state is set free so that
4492 * scaler can be assigned to other user. Actual register
4493 * update to free the scaler is done in plane/panel-fit programming.
4494 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4496 if (force_detach
|| !need_scaling
|| (intel_plane
&&
4497 (!fb
|| !plane_state
->visible
))) {
4498 if (*scaler_id
>= 0) {
4499 scaler_state
->scaler_users
&= ~(1 << idx
);
4500 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4502 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4503 "crtc_state = %p scaler_users = 0x%x\n",
4504 intel_crtc
->pipe
, *scaler_id
, intel_plane
? "PLANE" : "CRTC",
4505 intel_plane
? intel_plane
->base
.base
.id
:
4506 intel_crtc
->base
.base
.id
, crtc_state
,
4507 scaler_state
->scaler_users
);
4514 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4515 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4517 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4518 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4519 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4520 "size is out of scaler range\n",
4521 intel_plane
? "PLANE" : "CRTC",
4522 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4523 intel_crtc
->pipe
, idx
, src_w
, src_h
, dst_w
, dst_h
);
4527 /* check colorkey */
4528 if (intel_plane
&& intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4529 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4530 intel_plane
->base
.base
.id
);
4534 /* Check src format */
4536 switch (fb
->pixel_format
) {
4537 case DRM_FORMAT_RGB565
:
4538 case DRM_FORMAT_XBGR8888
:
4539 case DRM_FORMAT_XRGB8888
:
4540 case DRM_FORMAT_ABGR8888
:
4541 case DRM_FORMAT_ARGB8888
:
4542 case DRM_FORMAT_XRGB2101010
:
4543 case DRM_FORMAT_ARGB2101010
:
4544 case DRM_FORMAT_XBGR2101010
:
4545 case DRM_FORMAT_ABGR2101010
:
4546 case DRM_FORMAT_YUYV
:
4547 case DRM_FORMAT_YVYU
:
4548 case DRM_FORMAT_UYVY
:
4549 case DRM_FORMAT_VYUY
:
4552 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4553 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4558 /* mark this plane as a scaler user in crtc_state */
4559 scaler_state
->scaler_users
|= (1 << idx
);
4560 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4561 "crtc_state = %p scaler_users = 0x%x\n",
4562 intel_plane
? "PLANE" : "CRTC",
4563 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4564 src_w
, src_h
, dst_w
, dst_h
, crtc_state
, scaler_state
->scaler_users
);
4568 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4570 struct drm_device
*dev
= crtc
->base
.dev
;
4571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4572 int pipe
= crtc
->pipe
;
4573 struct intel_crtc_scaler_state
*scaler_state
=
4574 &crtc
->config
->scaler_state
;
4576 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4578 /* To update pfit, first update scaler state */
4579 skl_update_scaler_users(crtc
, crtc
->config
, NULL
, NULL
, !enable
);
4580 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4581 skl_detach_scalers(crtc
);
4585 if (crtc
->config
->pch_pfit
.enabled
) {
4588 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4589 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4593 id
= scaler_state
->scaler_id
;
4594 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4595 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4596 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4597 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4599 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4603 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4605 struct drm_device
*dev
= crtc
->base
.dev
;
4606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4607 int pipe
= crtc
->pipe
;
4609 if (crtc
->config
->pch_pfit
.enabled
) {
4610 /* Force use of hard-coded filter coefficients
4611 * as some pre-programmed values are broken,
4614 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4615 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4616 PF_PIPE_SEL_IVB(pipe
));
4618 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4619 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4620 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4624 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4626 struct drm_device
*dev
= crtc
->dev
;
4627 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4628 struct drm_plane
*plane
;
4629 struct intel_plane
*intel_plane
;
4631 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4632 intel_plane
= to_intel_plane(plane
);
4633 if (intel_plane
->pipe
== pipe
)
4634 intel_plane_restore(&intel_plane
->base
);
4638 void hsw_enable_ips(struct intel_crtc
*crtc
)
4640 struct drm_device
*dev
= crtc
->base
.dev
;
4641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4643 if (!crtc
->config
->ips_enabled
)
4646 /* We can only enable IPS after we enable a plane and wait for a vblank */
4647 intel_wait_for_vblank(dev
, crtc
->pipe
);
4649 assert_plane_enabled(dev_priv
, crtc
->plane
);
4650 if (IS_BROADWELL(dev
)) {
4651 mutex_lock(&dev_priv
->rps
.hw_lock
);
4652 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4653 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4654 /* Quoting Art Runyan: "its not safe to expect any particular
4655 * value in IPS_CTL bit 31 after enabling IPS through the
4656 * mailbox." Moreover, the mailbox may return a bogus state,
4657 * so we need to just enable it and continue on.
4660 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4661 /* The bit only becomes 1 in the next vblank, so this wait here
4662 * is essentially intel_wait_for_vblank. If we don't have this
4663 * and don't wait for vblanks until the end of crtc_enable, then
4664 * the HW state readout code will complain that the expected
4665 * IPS_CTL value is not the one we read. */
4666 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4667 DRM_ERROR("Timed out waiting for IPS enable\n");
4671 void hsw_disable_ips(struct intel_crtc
*crtc
)
4673 struct drm_device
*dev
= crtc
->base
.dev
;
4674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4676 if (!crtc
->config
->ips_enabled
)
4679 assert_plane_enabled(dev_priv
, crtc
->plane
);
4680 if (IS_BROADWELL(dev
)) {
4681 mutex_lock(&dev_priv
->rps
.hw_lock
);
4682 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4683 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4684 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4685 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4686 DRM_ERROR("Timed out waiting for IPS disable\n");
4688 I915_WRITE(IPS_CTL
, 0);
4689 POSTING_READ(IPS_CTL
);
4692 /* We need to wait for a vblank before we can disable the plane. */
4693 intel_wait_for_vblank(dev
, crtc
->pipe
);
4696 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4697 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4699 struct drm_device
*dev
= crtc
->dev
;
4700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4701 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4702 enum pipe pipe
= intel_crtc
->pipe
;
4703 int palreg
= PALETTE(pipe
);
4705 bool reenable_ips
= false;
4707 /* The clocks have to be on to load the palette. */
4708 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4711 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4712 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4713 assert_dsi_pll_enabled(dev_priv
);
4715 assert_pll_enabled(dev_priv
, pipe
);
4718 /* use legacy palette for Ironlake */
4719 if (!HAS_GMCH_DISPLAY(dev
))
4720 palreg
= LGC_PALETTE(pipe
);
4722 /* Workaround : Do not read or write the pipe palette/gamma data while
4723 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4725 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4726 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4727 GAMMA_MODE_MODE_SPLIT
)) {
4728 hsw_disable_ips(intel_crtc
);
4729 reenable_ips
= true;
4732 for (i
= 0; i
< 256; i
++) {
4733 I915_WRITE(palreg
+ 4 * i
,
4734 (intel_crtc
->lut_r
[i
] << 16) |
4735 (intel_crtc
->lut_g
[i
] << 8) |
4736 intel_crtc
->lut_b
[i
]);
4740 hsw_enable_ips(intel_crtc
);
4743 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4745 if (intel_crtc
->overlay
) {
4746 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4749 mutex_lock(&dev
->struct_mutex
);
4750 dev_priv
->mm
.interruptible
= false;
4751 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4752 dev_priv
->mm
.interruptible
= true;
4753 mutex_unlock(&dev
->struct_mutex
);
4756 /* Let userspace switch the overlay on again. In most cases userspace
4757 * has to recompute where to put it anyway.
4762 * intel_post_enable_primary - Perform operations after enabling primary plane
4763 * @crtc: the CRTC whose primary plane was just enabled
4765 * Performs potentially sleeping operations that must be done after the primary
4766 * plane is enabled, such as updating FBC and IPS. Note that this may be
4767 * called due to an explicit primary plane update, or due to an implicit
4768 * re-enable that is caused when a sprite plane is updated to no longer
4769 * completely hide the primary plane.
4772 intel_post_enable_primary(struct drm_crtc
*crtc
)
4774 struct drm_device
*dev
= crtc
->dev
;
4775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4776 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4777 int pipe
= intel_crtc
->pipe
;
4780 * BDW signals flip done immediately if the plane
4781 * is disabled, even if the plane enable is already
4782 * armed to occur at the next vblank :(
4784 if (IS_BROADWELL(dev
))
4785 intel_wait_for_vblank(dev
, pipe
);
4788 * FIXME IPS should be fine as long as one plane is
4789 * enabled, but in practice it seems to have problems
4790 * when going from primary only to sprite only and vice
4793 hsw_enable_ips(intel_crtc
);
4795 mutex_lock(&dev
->struct_mutex
);
4796 intel_fbc_update(dev
);
4797 mutex_unlock(&dev
->struct_mutex
);
4800 * Gen2 reports pipe underruns whenever all planes are disabled.
4801 * So don't enable underrun reporting before at least some planes
4803 * FIXME: Need to fix the logic to work when we turn off all planes
4804 * but leave the pipe running.
4807 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4809 /* Underruns don't raise interrupts, so check manually. */
4810 if (HAS_GMCH_DISPLAY(dev
))
4811 i9xx_check_fifo_underruns(dev_priv
);
4815 * intel_pre_disable_primary - Perform operations before disabling primary plane
4816 * @crtc: the CRTC whose primary plane is to be disabled
4818 * Performs potentially sleeping operations that must be done before the
4819 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4820 * be called due to an explicit primary plane update, or due to an implicit
4821 * disable that is caused when a sprite plane completely hides the primary
4825 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4827 struct drm_device
*dev
= crtc
->dev
;
4828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4830 int pipe
= intel_crtc
->pipe
;
4833 * Gen2 reports pipe underruns whenever all planes are disabled.
4834 * So diasble underrun reporting before all the planes get disabled.
4835 * FIXME: Need to fix the logic to work when we turn off all planes
4836 * but leave the pipe running.
4839 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4842 * Vblank time updates from the shadow to live plane control register
4843 * are blocked if the memory self-refresh mode is active at that
4844 * moment. So to make sure the plane gets truly disabled, disable
4845 * first the self-refresh mode. The self-refresh enable bit in turn
4846 * will be checked/applied by the HW only at the next frame start
4847 * event which is after the vblank start event, so we need to have a
4848 * wait-for-vblank between disabling the plane and the pipe.
4850 if (HAS_GMCH_DISPLAY(dev
))
4851 intel_set_memory_cxsr(dev_priv
, false);
4853 mutex_lock(&dev
->struct_mutex
);
4854 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4855 intel_fbc_disable(dev
);
4856 mutex_unlock(&dev
->struct_mutex
);
4859 * FIXME IPS should be fine as long as one plane is
4860 * enabled, but in practice it seems to have problems
4861 * when going from primary only to sprite only and vice
4864 hsw_disable_ips(intel_crtc
);
4867 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4869 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4870 intel_enable_sprite_planes(crtc
);
4871 intel_crtc_update_cursor(crtc
, true);
4873 intel_post_enable_primary(crtc
);
4876 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4878 struct drm_device
*dev
= crtc
->dev
;
4879 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4880 struct intel_plane
*intel_plane
;
4881 int pipe
= intel_crtc
->pipe
;
4883 intel_crtc_wait_for_pending_flips(crtc
);
4885 intel_pre_disable_primary(crtc
);
4887 intel_crtc_dpms_overlay_disable(intel_crtc
);
4888 for_each_intel_plane(dev
, intel_plane
) {
4889 if (intel_plane
->pipe
== pipe
) {
4890 struct drm_crtc
*from
= intel_plane
->base
.crtc
;
4892 intel_plane
->disable_plane(&intel_plane
->base
,
4893 from
?: crtc
, true);
4898 * FIXME: Once we grow proper nuclear flip support out of this we need
4899 * to compute the mask of flip planes precisely. For the time being
4900 * consider this a flip to a NULL plane.
4902 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4905 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4907 struct drm_device
*dev
= crtc
->dev
;
4908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4909 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4910 struct intel_encoder
*encoder
;
4911 int pipe
= intel_crtc
->pipe
;
4913 WARN_ON(!crtc
->state
->enable
);
4915 if (intel_crtc
->active
)
4918 if (intel_crtc
->config
->has_pch_encoder
)
4919 intel_prepare_shared_dpll(intel_crtc
);
4921 if (intel_crtc
->config
->has_dp_encoder
)
4922 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4924 intel_set_pipe_timings(intel_crtc
);
4926 if (intel_crtc
->config
->has_pch_encoder
) {
4927 intel_cpu_transcoder_set_m_n(intel_crtc
,
4928 &intel_crtc
->config
->fdi_m_n
, NULL
);
4931 ironlake_set_pipeconf(crtc
);
4933 intel_crtc
->active
= true;
4935 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4936 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4938 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4939 if (encoder
->pre_enable
)
4940 encoder
->pre_enable(encoder
);
4942 if (intel_crtc
->config
->has_pch_encoder
) {
4943 /* Note: FDI PLL enabling _must_ be done before we enable the
4944 * cpu pipes, hence this is separate from all the other fdi/pch
4946 ironlake_fdi_pll_enable(intel_crtc
);
4948 assert_fdi_tx_disabled(dev_priv
, pipe
);
4949 assert_fdi_rx_disabled(dev_priv
, pipe
);
4952 ironlake_pfit_enable(intel_crtc
);
4955 * On ILK+ LUT must be loaded before the pipe is running but with
4958 intel_crtc_load_lut(crtc
);
4960 intel_update_watermarks(crtc
);
4961 intel_enable_pipe(intel_crtc
);
4963 if (intel_crtc
->config
->has_pch_encoder
)
4964 ironlake_pch_enable(crtc
);
4966 assert_vblank_disabled(crtc
);
4967 drm_crtc_vblank_on(crtc
);
4969 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4970 encoder
->enable(encoder
);
4972 if (HAS_PCH_CPT(dev
))
4973 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4976 /* IPS only exists on ULT machines and is tied to pipe A. */
4977 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4979 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4983 * This implements the workaround described in the "notes" section of the mode
4984 * set sequence documentation. When going from no pipes or single pipe to
4985 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4986 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4988 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4990 struct drm_device
*dev
= crtc
->base
.dev
;
4991 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4993 /* We want to get the other_active_crtc only if there's only 1 other
4995 for_each_intel_crtc(dev
, crtc_it
) {
4996 if (!crtc_it
->active
|| crtc_it
== crtc
)
4999 if (other_active_crtc
)
5002 other_active_crtc
= crtc_it
;
5004 if (!other_active_crtc
)
5007 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
5008 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
5011 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
5013 struct drm_device
*dev
= crtc
->dev
;
5014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5016 struct intel_encoder
*encoder
;
5017 int pipe
= intel_crtc
->pipe
;
5019 WARN_ON(!crtc
->state
->enable
);
5021 if (intel_crtc
->active
)
5024 if (intel_crtc_to_shared_dpll(intel_crtc
))
5025 intel_enable_shared_dpll(intel_crtc
);
5027 if (intel_crtc
->config
->has_dp_encoder
)
5028 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5030 intel_set_pipe_timings(intel_crtc
);
5032 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
5033 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
5034 intel_crtc
->config
->pixel_multiplier
- 1);
5037 if (intel_crtc
->config
->has_pch_encoder
) {
5038 intel_cpu_transcoder_set_m_n(intel_crtc
,
5039 &intel_crtc
->config
->fdi_m_n
, NULL
);
5042 haswell_set_pipeconf(crtc
);
5044 intel_set_pipe_csc(crtc
);
5046 intel_crtc
->active
= true;
5048 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5049 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5050 if (encoder
->pre_enable
)
5051 encoder
->pre_enable(encoder
);
5053 if (intel_crtc
->config
->has_pch_encoder
) {
5054 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5056 dev_priv
->display
.fdi_link_train(crtc
);
5059 intel_ddi_enable_pipe_clock(intel_crtc
);
5061 if (INTEL_INFO(dev
)->gen
== 9)
5062 skylake_pfit_update(intel_crtc
, 1);
5063 else if (INTEL_INFO(dev
)->gen
< 9)
5064 ironlake_pfit_enable(intel_crtc
);
5066 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5069 * On ILK+ LUT must be loaded before the pipe is running but with
5072 intel_crtc_load_lut(crtc
);
5074 intel_ddi_set_pipe_settings(crtc
);
5075 intel_ddi_enable_transcoder_func(crtc
);
5077 intel_update_watermarks(crtc
);
5078 intel_enable_pipe(intel_crtc
);
5080 if (intel_crtc
->config
->has_pch_encoder
)
5081 lpt_pch_enable(crtc
);
5083 if (intel_crtc
->config
->dp_encoder_is_mst
)
5084 intel_ddi_set_vc_payload_alloc(crtc
, true);
5086 assert_vblank_disabled(crtc
);
5087 drm_crtc_vblank_on(crtc
);
5089 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5090 encoder
->enable(encoder
);
5091 intel_opregion_notify_encoder(encoder
, true);
5094 /* If we change the relative order between pipe/planes enabling, we need
5095 * to change the workaround. */
5096 haswell_mode_set_planes_workaround(intel_crtc
);
5099 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5101 struct drm_device
*dev
= crtc
->base
.dev
;
5102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5103 int pipe
= crtc
->pipe
;
5105 /* To avoid upsetting the power well on haswell only disable the pfit if
5106 * it's in use. The hw state code will make sure we get this right. */
5107 if (crtc
->config
->pch_pfit
.enabled
) {
5108 I915_WRITE(PF_CTL(pipe
), 0);
5109 I915_WRITE(PF_WIN_POS(pipe
), 0);
5110 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5114 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5116 struct drm_device
*dev
= crtc
->dev
;
5117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5119 struct intel_encoder
*encoder
;
5120 int pipe
= intel_crtc
->pipe
;
5123 if (!intel_crtc
->active
)
5126 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5127 encoder
->disable(encoder
);
5129 drm_crtc_vblank_off(crtc
);
5130 assert_vblank_disabled(crtc
);
5132 if (intel_crtc
->config
->has_pch_encoder
)
5133 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5135 intel_disable_pipe(intel_crtc
);
5137 ironlake_pfit_disable(intel_crtc
);
5139 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5140 if (encoder
->post_disable
)
5141 encoder
->post_disable(encoder
);
5143 if (intel_crtc
->config
->has_pch_encoder
) {
5144 ironlake_fdi_disable(crtc
);
5146 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5148 if (HAS_PCH_CPT(dev
)) {
5149 /* disable TRANS_DP_CTL */
5150 reg
= TRANS_DP_CTL(pipe
);
5151 temp
= I915_READ(reg
);
5152 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5153 TRANS_DP_PORT_SEL_MASK
);
5154 temp
|= TRANS_DP_PORT_SEL_NONE
;
5155 I915_WRITE(reg
, temp
);
5157 /* disable DPLL_SEL */
5158 temp
= I915_READ(PCH_DPLL_SEL
);
5159 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5160 I915_WRITE(PCH_DPLL_SEL
, temp
);
5163 /* disable PCH DPLL */
5164 intel_disable_shared_dpll(intel_crtc
);
5166 ironlake_fdi_pll_disable(intel_crtc
);
5169 intel_crtc
->active
= false;
5170 intel_update_watermarks(crtc
);
5172 mutex_lock(&dev
->struct_mutex
);
5173 intel_fbc_update(dev
);
5174 mutex_unlock(&dev
->struct_mutex
);
5177 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5179 struct drm_device
*dev
= crtc
->dev
;
5180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5181 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5182 struct intel_encoder
*encoder
;
5183 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5185 if (!intel_crtc
->active
)
5188 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5189 intel_opregion_notify_encoder(encoder
, false);
5190 encoder
->disable(encoder
);
5193 drm_crtc_vblank_off(crtc
);
5194 assert_vblank_disabled(crtc
);
5196 if (intel_crtc
->config
->has_pch_encoder
)
5197 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5199 intel_disable_pipe(intel_crtc
);
5201 if (intel_crtc
->config
->dp_encoder_is_mst
)
5202 intel_ddi_set_vc_payload_alloc(crtc
, false);
5204 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5206 if (INTEL_INFO(dev
)->gen
== 9)
5207 skylake_pfit_update(intel_crtc
, 0);
5208 else if (INTEL_INFO(dev
)->gen
< 9)
5209 ironlake_pfit_disable(intel_crtc
);
5211 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5213 intel_ddi_disable_pipe_clock(intel_crtc
);
5215 if (intel_crtc
->config
->has_pch_encoder
) {
5216 lpt_disable_pch_transcoder(dev_priv
);
5217 intel_ddi_fdi_disable(crtc
);
5220 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5221 if (encoder
->post_disable
)
5222 encoder
->post_disable(encoder
);
5224 intel_crtc
->active
= false;
5225 intel_update_watermarks(crtc
);
5227 mutex_lock(&dev
->struct_mutex
);
5228 intel_fbc_update(dev
);
5229 mutex_unlock(&dev
->struct_mutex
);
5231 if (intel_crtc_to_shared_dpll(intel_crtc
))
5232 intel_disable_shared_dpll(intel_crtc
);
5235 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
5237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5238 intel_put_shared_dpll(intel_crtc
);
5242 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5244 struct drm_device
*dev
= crtc
->base
.dev
;
5245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5246 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5248 if (!pipe_config
->gmch_pfit
.control
)
5252 * The panel fitter should only be adjusted whilst the pipe is disabled,
5253 * according to register description and PRM.
5255 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5256 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5258 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5259 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5261 /* Border color in case we don't scale up to the full screen. Black by
5262 * default, change to something else for debugging. */
5263 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5266 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5270 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5272 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5274 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5276 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5279 return POWER_DOMAIN_PORT_OTHER
;
5283 #define for_each_power_domain(domain, mask) \
5284 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5285 if ((1 << (domain)) & (mask))
5287 enum intel_display_power_domain
5288 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5290 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5291 struct intel_digital_port
*intel_dig_port
;
5293 switch (intel_encoder
->type
) {
5294 case INTEL_OUTPUT_UNKNOWN
:
5295 /* Only DDI platforms should ever use this output type */
5296 WARN_ON_ONCE(!HAS_DDI(dev
));
5297 case INTEL_OUTPUT_DISPLAYPORT
:
5298 case INTEL_OUTPUT_HDMI
:
5299 case INTEL_OUTPUT_EDP
:
5300 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5301 return port_to_power_domain(intel_dig_port
->port
);
5302 case INTEL_OUTPUT_DP_MST
:
5303 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5304 return port_to_power_domain(intel_dig_port
->port
);
5305 case INTEL_OUTPUT_ANALOG
:
5306 return POWER_DOMAIN_PORT_CRT
;
5307 case INTEL_OUTPUT_DSI
:
5308 return POWER_DOMAIN_PORT_DSI
;
5310 return POWER_DOMAIN_PORT_OTHER
;
5314 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5316 struct drm_device
*dev
= crtc
->dev
;
5317 struct intel_encoder
*intel_encoder
;
5318 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5319 enum pipe pipe
= intel_crtc
->pipe
;
5321 enum transcoder transcoder
;
5323 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5325 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5326 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5327 if (intel_crtc
->config
->pch_pfit
.enabled
||
5328 intel_crtc
->config
->pch_pfit
.force_thru
)
5329 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5331 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5332 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5337 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5339 struct drm_device
*dev
= state
->dev
;
5340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5341 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5342 struct intel_crtc
*crtc
;
5345 * First get all needed power domains, then put all unneeded, to avoid
5346 * any unnecessary toggling of the power wells.
5348 for_each_intel_crtc(dev
, crtc
) {
5349 enum intel_display_power_domain domain
;
5351 if (!crtc
->base
.state
->enable
)
5354 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5356 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5357 intel_display_power_get(dev_priv
, domain
);
5360 if (dev_priv
->display
.modeset_global_resources
)
5361 dev_priv
->display
.modeset_global_resources(state
);
5363 for_each_intel_crtc(dev
, crtc
) {
5364 enum intel_display_power_domain domain
;
5366 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5367 intel_display_power_put(dev_priv
, domain
);
5369 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5372 intel_display_set_init_power(dev_priv
, false);
5375 void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5380 uint32_t current_freq
;
5383 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5384 switch (frequency
) {
5386 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5387 ratio
= BXT_DE_PLL_RATIO(60);
5390 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5391 ratio
= BXT_DE_PLL_RATIO(60);
5394 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5395 ratio
= BXT_DE_PLL_RATIO(60);
5398 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5399 ratio
= BXT_DE_PLL_RATIO(60);
5402 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5403 ratio
= BXT_DE_PLL_RATIO(65);
5407 * Bypass frequency with DE PLL disabled. Init ratio, divider
5408 * to suppress GCC warning.
5414 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5419 mutex_lock(&dev_priv
->rps
.hw_lock
);
5420 /* Inform power controller of upcoming frequency change */
5421 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5423 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5426 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5431 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5432 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5433 current_freq
= current_freq
* 500 + 1000;
5436 * DE PLL has to be disabled when
5437 * - setting to 19.2MHz (bypass, PLL isn't used)
5438 * - before setting to 624MHz (PLL needs toggling)
5439 * - before setting to any frequency from 624MHz (PLL needs toggling)
5441 if (frequency
== 19200 || frequency
== 624000 ||
5442 current_freq
== 624000) {
5443 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5445 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5447 DRM_ERROR("timout waiting for DE PLL unlock\n");
5450 if (frequency
!= 19200) {
5453 val
= I915_READ(BXT_DE_PLL_CTL
);
5454 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5456 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5458 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5460 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5461 DRM_ERROR("timeout waiting for DE PLL lock\n");
5463 val
= I915_READ(CDCLK_CTL
);
5464 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5467 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5470 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5471 if (frequency
>= 500000)
5472 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5474 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5475 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5476 val
|= (frequency
- 1000) / 500;
5477 I915_WRITE(CDCLK_CTL
, val
);
5480 mutex_lock(&dev_priv
->rps
.hw_lock
);
5481 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5482 DIV_ROUND_UP(frequency
, 25000));
5483 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5486 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5491 dev_priv
->cdclk_freq
= frequency
;
5494 void broxton_init_cdclk(struct drm_device
*dev
)
5496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5500 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5501 * or else the reset will hang because there is no PCH to respond.
5502 * Move the handshake programming to initialization sequence.
5503 * Previously was left up to BIOS.
5505 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5506 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5507 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5509 /* Enable PG1 for cdclk */
5510 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5512 /* check if cd clock is enabled */
5513 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5514 DRM_DEBUG_KMS("Display already initialized\n");
5520 * - The initial CDCLK needs to be read from VBT.
5521 * Need to make this change after VBT has changes for BXT.
5522 * - check if setting the max (or any) cdclk freq is really necessary
5523 * here, it belongs to modeset time
5525 broxton_set_cdclk(dev
, 624000);
5527 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5528 POSTING_READ(DBUF_CTL
);
5532 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5533 DRM_ERROR("DBuf power enable timeout!\n");
5536 void broxton_uninit_cdclk(struct drm_device
*dev
)
5538 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5540 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5541 POSTING_READ(DBUF_CTL
);
5545 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5546 DRM_ERROR("DBuf power disable timeout!\n");
5548 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5549 broxton_set_cdclk(dev
, 19200);
5551 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5554 /* returns HPLL frequency in kHz */
5555 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5557 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5559 /* Obtain SKU information */
5560 mutex_lock(&dev_priv
->dpio_lock
);
5561 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5562 CCK_FUSE_HPLL_FREQ_MASK
;
5563 mutex_unlock(&dev_priv
->dpio_lock
);
5565 return vco_freq
[hpll_freq
] * 1000;
5568 static void vlv_update_cdclk(struct drm_device
*dev
)
5570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5572 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5573 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5574 dev_priv
->cdclk_freq
);
5577 * Program the gmbus_freq based on the cdclk frequency.
5578 * BSpec erroneously claims we should aim for 4MHz, but
5579 * in fact 1MHz is the correct frequency.
5581 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5584 /* Adjust CDclk dividers to allow high res or save power if possible */
5585 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5590 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5591 != dev_priv
->cdclk_freq
);
5593 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5595 else if (cdclk
== 266667)
5600 mutex_lock(&dev_priv
->rps
.hw_lock
);
5601 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5602 val
&= ~DSPFREQGUAR_MASK
;
5603 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5604 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5605 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5606 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5608 DRM_ERROR("timed out waiting for CDclk change\n");
5610 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5612 if (cdclk
== 400000) {
5615 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5617 mutex_lock(&dev_priv
->dpio_lock
);
5618 /* adjust cdclk divider */
5619 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5620 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5622 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5624 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5625 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5627 DRM_ERROR("timed out waiting for CDclk change\n");
5628 mutex_unlock(&dev_priv
->dpio_lock
);
5631 mutex_lock(&dev_priv
->dpio_lock
);
5632 /* adjust self-refresh exit latency value */
5633 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5637 * For high bandwidth configs, we set a higher latency in the bunit
5638 * so that the core display fetch happens in time to avoid underruns.
5640 if (cdclk
== 400000)
5641 val
|= 4500 / 250; /* 4.5 usec */
5643 val
|= 3000 / 250; /* 3.0 usec */
5644 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5645 mutex_unlock(&dev_priv
->dpio_lock
);
5647 vlv_update_cdclk(dev
);
5650 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5655 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5656 != dev_priv
->cdclk_freq
);
5665 MISSING_CASE(cdclk
);
5670 * Specs are full of misinformation, but testing on actual
5671 * hardware has shown that we just need to write the desired
5672 * CCK divider into the Punit register.
5674 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5676 mutex_lock(&dev_priv
->rps
.hw_lock
);
5677 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5678 val
&= ~DSPFREQGUAR_MASK_CHV
;
5679 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5680 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5681 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5682 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5684 DRM_ERROR("timed out waiting for CDclk change\n");
5686 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5688 vlv_update_cdclk(dev
);
5691 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5694 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5695 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5698 * Really only a few cases to deal with, as only 4 CDclks are supported:
5701 * 320/333MHz (depends on HPLL freq)
5703 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5704 * of the lower bin and adjust if needed.
5706 * We seem to get an unstable or solid color picture at 200MHz.
5707 * Not sure what's wrong. For now use 200MHz only when all pipes
5710 if (!IS_CHERRYVIEW(dev_priv
) &&
5711 max_pixclk
> freq_320
*limit
/100)
5713 else if (max_pixclk
> 266667*limit
/100)
5715 else if (max_pixclk
> 0)
5721 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5726 * - remove the guardband, it's not needed on BXT
5727 * - set 19.2MHz bypass frequency if there are no active pipes
5729 if (max_pixclk
> 576000*9/10)
5731 else if (max_pixclk
> 384000*9/10)
5733 else if (max_pixclk
> 288000*9/10)
5735 else if (max_pixclk
> 144000*9/10)
5741 /* Compute the max pixel clock for new configuration. Uses atomic state if
5742 * that's non-NULL, look at current state otherwise. */
5743 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5744 struct drm_atomic_state
*state
)
5746 struct intel_crtc
*intel_crtc
;
5747 struct intel_crtc_state
*crtc_state
;
5750 for_each_intel_crtc(dev
, intel_crtc
) {
5753 intel_atomic_get_crtc_state(state
, intel_crtc
);
5755 crtc_state
= intel_crtc
->config
;
5756 if (IS_ERR(crtc_state
))
5757 return PTR_ERR(crtc_state
);
5759 if (!crtc_state
->base
.enable
)
5762 max_pixclk
= max(max_pixclk
,
5763 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5769 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
)
5771 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5772 struct drm_crtc
*crtc
;
5773 struct drm_crtc_state
*crtc_state
;
5774 int max_pixclk
= intel_mode_max_pixclk(state
->dev
, state
);
5780 if (IS_VALLEYVIEW(dev_priv
))
5781 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5783 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
5785 if (cdclk
== dev_priv
->cdclk_freq
)
5788 /* add all active pipes to the state */
5789 for_each_crtc(state
->dev
, crtc
) {
5790 if (!crtc
->state
->enable
)
5793 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
5794 if (IS_ERR(crtc_state
))
5795 return PTR_ERR(crtc_state
);
5798 /* disable/enable all currently active pipes while we change cdclk */
5799 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
5800 if (crtc_state
->enable
)
5801 crtc_state
->mode_changed
= true;
5806 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5808 unsigned int credits
, default_credits
;
5810 if (IS_CHERRYVIEW(dev_priv
))
5811 default_credits
= PFI_CREDIT(12);
5813 default_credits
= PFI_CREDIT(8);
5815 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5816 /* CHV suggested value is 31 or 63 */
5817 if (IS_CHERRYVIEW(dev_priv
))
5818 credits
= PFI_CREDIT_31
;
5820 credits
= PFI_CREDIT(15);
5822 credits
= default_credits
;
5826 * WA - write default credits before re-programming
5827 * FIXME: should we also set the resend bit here?
5829 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5832 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5833 credits
| PFI_CREDIT_RESEND
);
5836 * FIXME is this guaranteed to clear
5837 * immediately or should we poll for it?
5839 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5842 static void valleyview_modeset_global_resources(struct drm_atomic_state
*old_state
)
5844 struct drm_device
*dev
= old_state
->dev
;
5845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5846 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
5849 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5851 if (WARN_ON(max_pixclk
< 0))
5854 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5856 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
5858 * FIXME: We can end up here with all power domains off, yet
5859 * with a CDCLK frequency other than the minimum. To account
5860 * for this take the PIPE-A power domain, which covers the HW
5861 * blocks needed for the following programming. This can be
5862 * removed once it's guaranteed that we get here either with
5863 * the minimum CDCLK set, or the required power domains
5866 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5868 if (IS_CHERRYVIEW(dev
))
5869 cherryview_set_cdclk(dev
, req_cdclk
);
5871 valleyview_set_cdclk(dev
, req_cdclk
);
5873 vlv_program_pfi_credits(dev_priv
);
5875 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5879 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5881 struct drm_device
*dev
= crtc
->dev
;
5882 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5883 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5884 struct intel_encoder
*encoder
;
5885 int pipe
= intel_crtc
->pipe
;
5888 WARN_ON(!crtc
->state
->enable
);
5890 if (intel_crtc
->active
)
5893 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5896 if (IS_CHERRYVIEW(dev
))
5897 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5899 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5902 if (intel_crtc
->config
->has_dp_encoder
)
5903 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5905 intel_set_pipe_timings(intel_crtc
);
5907 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5910 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5911 I915_WRITE(CHV_CANVAS(pipe
), 0);
5914 i9xx_set_pipeconf(intel_crtc
);
5916 intel_crtc
->active
= true;
5918 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5920 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5921 if (encoder
->pre_pll_enable
)
5922 encoder
->pre_pll_enable(encoder
);
5925 if (IS_CHERRYVIEW(dev
))
5926 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5928 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5931 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5932 if (encoder
->pre_enable
)
5933 encoder
->pre_enable(encoder
);
5935 i9xx_pfit_enable(intel_crtc
);
5937 intel_crtc_load_lut(crtc
);
5939 intel_update_watermarks(crtc
);
5940 intel_enable_pipe(intel_crtc
);
5942 assert_vblank_disabled(crtc
);
5943 drm_crtc_vblank_on(crtc
);
5945 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5946 encoder
->enable(encoder
);
5949 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5951 struct drm_device
*dev
= crtc
->base
.dev
;
5952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5954 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5955 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5958 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5960 struct drm_device
*dev
= crtc
->dev
;
5961 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5963 struct intel_encoder
*encoder
;
5964 int pipe
= intel_crtc
->pipe
;
5966 WARN_ON(!crtc
->state
->enable
);
5968 if (intel_crtc
->active
)
5971 i9xx_set_pll_dividers(intel_crtc
);
5973 if (intel_crtc
->config
->has_dp_encoder
)
5974 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5976 intel_set_pipe_timings(intel_crtc
);
5978 i9xx_set_pipeconf(intel_crtc
);
5980 intel_crtc
->active
= true;
5983 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5985 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5986 if (encoder
->pre_enable
)
5987 encoder
->pre_enable(encoder
);
5989 i9xx_enable_pll(intel_crtc
);
5991 i9xx_pfit_enable(intel_crtc
);
5993 intel_crtc_load_lut(crtc
);
5995 intel_update_watermarks(crtc
);
5996 intel_enable_pipe(intel_crtc
);
5998 assert_vblank_disabled(crtc
);
5999 drm_crtc_vblank_on(crtc
);
6001 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6002 encoder
->enable(encoder
);
6005 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6007 struct drm_device
*dev
= crtc
->base
.dev
;
6008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6010 if (!crtc
->config
->gmch_pfit
.control
)
6013 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6015 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6016 I915_READ(PFIT_CONTROL
));
6017 I915_WRITE(PFIT_CONTROL
, 0);
6020 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6022 struct drm_device
*dev
= crtc
->dev
;
6023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6024 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6025 struct intel_encoder
*encoder
;
6026 int pipe
= intel_crtc
->pipe
;
6028 if (!intel_crtc
->active
)
6032 * On gen2 planes are double buffered but the pipe isn't, so we must
6033 * wait for planes to fully turn off before disabling the pipe.
6034 * We also need to wait on all gmch platforms because of the
6035 * self-refresh mode constraint explained above.
6037 intel_wait_for_vblank(dev
, pipe
);
6039 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6040 encoder
->disable(encoder
);
6042 drm_crtc_vblank_off(crtc
);
6043 assert_vblank_disabled(crtc
);
6045 intel_disable_pipe(intel_crtc
);
6047 i9xx_pfit_disable(intel_crtc
);
6049 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6050 if (encoder
->post_disable
)
6051 encoder
->post_disable(encoder
);
6053 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6054 if (IS_CHERRYVIEW(dev
))
6055 chv_disable_pll(dev_priv
, pipe
);
6056 else if (IS_VALLEYVIEW(dev
))
6057 vlv_disable_pll(dev_priv
, pipe
);
6059 i9xx_disable_pll(intel_crtc
);
6063 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6065 intel_crtc
->active
= false;
6066 intel_update_watermarks(crtc
);
6068 mutex_lock(&dev
->struct_mutex
);
6069 intel_fbc_update(dev
);
6070 mutex_unlock(&dev
->struct_mutex
);
6073 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
6077 /* Master function to enable/disable CRTC and corresponding power wells */
6078 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6080 struct drm_device
*dev
= crtc
->dev
;
6081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6083 enum intel_display_power_domain domain
;
6084 unsigned long domains
;
6087 if (!intel_crtc
->active
) {
6088 domains
= get_crtc_power_domains(crtc
);
6089 for_each_power_domain(domain
, domains
)
6090 intel_display_power_get(dev_priv
, domain
);
6091 intel_crtc
->enabled_power_domains
= domains
;
6093 dev_priv
->display
.crtc_enable(crtc
);
6094 intel_crtc_enable_planes(crtc
);
6097 if (intel_crtc
->active
) {
6098 intel_crtc_disable_planes(crtc
);
6099 dev_priv
->display
.crtc_disable(crtc
);
6101 domains
= intel_crtc
->enabled_power_domains
;
6102 for_each_power_domain(domain
, domains
)
6103 intel_display_power_put(dev_priv
, domain
);
6104 intel_crtc
->enabled_power_domains
= 0;
6110 * Sets the power management mode of the pipe and plane.
6112 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6114 struct drm_device
*dev
= crtc
->dev
;
6115 struct intel_encoder
*intel_encoder
;
6116 bool enable
= false;
6118 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6119 enable
|= intel_encoder
->connectors_active
;
6121 intel_crtc_control(crtc
, enable
);
6123 crtc
->state
->active
= enable
;
6126 static void intel_crtc_disable(struct drm_crtc
*crtc
)
6128 struct drm_device
*dev
= crtc
->dev
;
6129 struct drm_connector
*connector
;
6130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6132 /* crtc should still be enabled when we disable it. */
6133 WARN_ON(!crtc
->state
->enable
);
6135 intel_crtc_disable_planes(crtc
);
6136 dev_priv
->display
.crtc_disable(crtc
);
6137 dev_priv
->display
.off(crtc
);
6139 drm_plane_helper_disable(crtc
->primary
);
6141 /* Update computed state. */
6142 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6143 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6146 if (connector
->encoder
->crtc
!= crtc
)
6149 connector
->dpms
= DRM_MODE_DPMS_OFF
;
6150 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
6154 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6156 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6158 drm_encoder_cleanup(encoder
);
6159 kfree(intel_encoder
);
6162 /* Simple dpms helper for encoders with just one connector, no cloning and only
6163 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6164 * state of the entire output pipe. */
6165 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6167 if (mode
== DRM_MODE_DPMS_ON
) {
6168 encoder
->connectors_active
= true;
6170 intel_crtc_update_dpms(encoder
->base
.crtc
);
6172 encoder
->connectors_active
= false;
6174 intel_crtc_update_dpms(encoder
->base
.crtc
);
6178 /* Cross check the actual hw state with our own modeset state tracking (and it's
6179 * internal consistency). */
6180 static void intel_connector_check_state(struct intel_connector
*connector
)
6182 if (connector
->get_hw_state(connector
)) {
6183 struct intel_encoder
*encoder
= connector
->encoder
;
6184 struct drm_crtc
*crtc
;
6185 bool encoder_enabled
;
6188 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6189 connector
->base
.base
.id
,
6190 connector
->base
.name
);
6192 /* there is no real hw state for MST connectors */
6193 if (connector
->mst_port
)
6196 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6197 "wrong connector dpms state\n");
6198 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6199 "active connector not linked to encoder\n");
6202 I915_STATE_WARN(!encoder
->connectors_active
,
6203 "encoder->connectors_active not set\n");
6205 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6206 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6207 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6210 crtc
= encoder
->base
.crtc
;
6212 I915_STATE_WARN(!crtc
->state
->enable
,
6213 "crtc not enabled\n");
6214 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6215 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6216 "encoder active on the wrong pipe\n");
6221 int intel_connector_init(struct intel_connector
*connector
)
6223 struct drm_connector_state
*connector_state
;
6225 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6226 if (!connector_state
)
6229 connector
->base
.state
= connector_state
;
6233 struct intel_connector
*intel_connector_alloc(void)
6235 struct intel_connector
*connector
;
6237 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6241 if (intel_connector_init(connector
) < 0) {
6249 /* Even simpler default implementation, if there's really no special case to
6251 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6253 /* All the simple cases only support two dpms states. */
6254 if (mode
!= DRM_MODE_DPMS_ON
)
6255 mode
= DRM_MODE_DPMS_OFF
;
6257 if (mode
== connector
->dpms
)
6260 connector
->dpms
= mode
;
6262 /* Only need to change hw state when actually enabled */
6263 if (connector
->encoder
)
6264 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6266 intel_modeset_check_state(connector
->dev
);
6269 /* Simple connector->get_hw_state implementation for encoders that support only
6270 * one connector and no cloning and hence the encoder state determines the state
6271 * of the connector. */
6272 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6275 struct intel_encoder
*encoder
= connector
->encoder
;
6277 return encoder
->get_hw_state(encoder
, &pipe
);
6280 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6282 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6283 return crtc_state
->fdi_lanes
;
6288 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6289 struct intel_crtc_state
*pipe_config
)
6291 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6292 struct intel_crtc
*other_crtc
;
6293 struct intel_crtc_state
*other_crtc_state
;
6295 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6296 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6297 if (pipe_config
->fdi_lanes
> 4) {
6298 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6299 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6303 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6304 if (pipe_config
->fdi_lanes
> 2) {
6305 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6306 pipe_config
->fdi_lanes
);
6313 if (INTEL_INFO(dev
)->num_pipes
== 2)
6316 /* Ivybridge 3 pipe is really complicated */
6321 if (pipe_config
->fdi_lanes
<= 2)
6324 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6326 intel_atomic_get_crtc_state(state
, other_crtc
);
6327 if (IS_ERR(other_crtc_state
))
6328 return PTR_ERR(other_crtc_state
);
6330 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6331 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6332 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6337 if (pipe_config
->fdi_lanes
> 2) {
6338 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6339 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6343 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6345 intel_atomic_get_crtc_state(state
, other_crtc
);
6346 if (IS_ERR(other_crtc_state
))
6347 return PTR_ERR(other_crtc_state
);
6349 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6350 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6360 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6361 struct intel_crtc_state
*pipe_config
)
6363 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6364 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6365 int lane
, link_bw
, fdi_dotclock
, ret
;
6366 bool needs_recompute
= false;
6369 /* FDI is a binary signal running at ~2.7GHz, encoding
6370 * each output octet as 10 bits. The actual frequency
6371 * is stored as a divider into a 100MHz clock, and the
6372 * mode pixel clock is stored in units of 1KHz.
6373 * Hence the bw of each lane in terms of the mode signal
6376 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6378 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6380 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6381 pipe_config
->pipe_bpp
);
6383 pipe_config
->fdi_lanes
= lane
;
6385 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6386 link_bw
, &pipe_config
->fdi_m_n
);
6388 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6389 intel_crtc
->pipe
, pipe_config
);
6390 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6391 pipe_config
->pipe_bpp
-= 2*3;
6392 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6393 pipe_config
->pipe_bpp
);
6394 needs_recompute
= true;
6395 pipe_config
->bw_constrained
= true;
6400 if (needs_recompute
)
6406 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6407 struct intel_crtc_state
*pipe_config
)
6409 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6410 hsw_crtc_supports_ips(crtc
) &&
6411 pipe_config
->pipe_bpp
<= 24;
6414 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6415 struct intel_crtc_state
*pipe_config
)
6417 struct drm_device
*dev
= crtc
->base
.dev
;
6418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6419 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6422 /* FIXME should check pixel clock limits on all platforms */
6423 if (INTEL_INFO(dev
)->gen
< 4) {
6425 dev_priv
->display
.get_display_clock_speed(dev
);
6428 * Enable pixel doubling when the dot clock
6429 * is > 90% of the (display) core speed.
6431 * GDG double wide on either pipe,
6432 * otherwise pipe A only.
6434 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6435 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6437 pipe_config
->double_wide
= true;
6440 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6445 * Pipe horizontal size must be even in:
6447 * - LVDS dual channel mode
6448 * - Double wide pipe
6450 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6451 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6452 pipe_config
->pipe_src_w
&= ~1;
6454 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6455 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6457 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6458 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6462 hsw_compute_ips_config(crtc
, pipe_config
);
6464 if (pipe_config
->has_pch_encoder
)
6465 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6467 /* FIXME: remove below call once atomic mode set is place and all crtc
6468 * related checks called from atomic_crtc_check function */
6470 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6471 crtc
, pipe_config
->base
.state
);
6472 ret
= intel_atomic_setup_scalers(dev
, crtc
, pipe_config
);
6477 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6479 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6480 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6481 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6484 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
6485 WARN(1, "LCPLL1 not enabled\n");
6486 return 24000; /* 24MHz is the cd freq with NSSC ref */
6489 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6492 linkrate
= (I915_READ(DPLL_CTRL1
) &
6493 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6495 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6496 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6498 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6499 case CDCLK_FREQ_450_432
:
6501 case CDCLK_FREQ_337_308
:
6503 case CDCLK_FREQ_675_617
:
6506 WARN(1, "Unknown cd freq selection\n");
6510 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6511 case CDCLK_FREQ_450_432
:
6513 case CDCLK_FREQ_337_308
:
6515 case CDCLK_FREQ_675_617
:
6518 WARN(1, "Unknown cd freq selection\n");
6522 /* error case, do as if DPLL0 isn't enabled */
6526 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6529 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6530 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6532 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6534 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6536 else if (freq
== LCPLL_CLK_FREQ_450
)
6538 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6540 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6546 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6549 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6550 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6552 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6554 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6556 else if (freq
== LCPLL_CLK_FREQ_450
)
6558 else if (IS_HSW_ULT(dev
))
6564 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6570 if (dev_priv
->hpll_freq
== 0)
6571 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6573 mutex_lock(&dev_priv
->dpio_lock
);
6574 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6575 mutex_unlock(&dev_priv
->dpio_lock
);
6577 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6579 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6580 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6581 "cdclk change in progress\n");
6583 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6586 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6591 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6596 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6601 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6606 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6610 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6612 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6613 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6615 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6617 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6619 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6622 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6623 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6625 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6630 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6634 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6636 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6639 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6640 case GC_DISPLAY_CLOCK_333_MHZ
:
6643 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6649 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6654 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6657 /* Assume that the hardware is in the high speed state. This
6658 * should be the default.
6660 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6661 case GC_CLOCK_133_200
:
6662 case GC_CLOCK_100_200
:
6664 case GC_CLOCK_166_250
:
6666 case GC_CLOCK_100_133
:
6670 /* Shouldn't happen */
6674 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6680 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6682 while (*num
> DATA_LINK_M_N_MASK
||
6683 *den
> DATA_LINK_M_N_MASK
) {
6689 static void compute_m_n(unsigned int m
, unsigned int n
,
6690 uint32_t *ret_m
, uint32_t *ret_n
)
6692 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6693 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6694 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6698 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6699 int pixel_clock
, int link_clock
,
6700 struct intel_link_m_n
*m_n
)
6704 compute_m_n(bits_per_pixel
* pixel_clock
,
6705 link_clock
* nlanes
* 8,
6706 &m_n
->gmch_m
, &m_n
->gmch_n
);
6708 compute_m_n(pixel_clock
, link_clock
,
6709 &m_n
->link_m
, &m_n
->link_n
);
6712 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6714 if (i915
.panel_use_ssc
>= 0)
6715 return i915
.panel_use_ssc
!= 0;
6716 return dev_priv
->vbt
.lvds_use_ssc
6717 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6720 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6723 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6727 WARN_ON(!crtc_state
->base
.state
);
6729 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
6731 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6732 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6733 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6734 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6735 } else if (!IS_GEN2(dev
)) {
6744 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6746 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6749 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6751 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6754 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6755 struct intel_crtc_state
*crtc_state
,
6756 intel_clock_t
*reduced_clock
)
6758 struct drm_device
*dev
= crtc
->base
.dev
;
6761 if (IS_PINEVIEW(dev
)) {
6762 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6764 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6766 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6768 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6771 crtc_state
->dpll_hw_state
.fp0
= fp
;
6773 crtc
->lowfreq_avail
= false;
6774 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6776 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6777 crtc
->lowfreq_avail
= true;
6779 crtc_state
->dpll_hw_state
.fp1
= fp
;
6783 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6789 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6790 * and set it to a reasonable value instead.
6792 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6793 reg_val
&= 0xffffff00;
6794 reg_val
|= 0x00000030;
6795 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6797 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6798 reg_val
&= 0x8cffffff;
6799 reg_val
= 0x8c000000;
6800 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6802 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6803 reg_val
&= 0xffffff00;
6804 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6806 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6807 reg_val
&= 0x00ffffff;
6808 reg_val
|= 0xb0000000;
6809 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6812 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6813 struct intel_link_m_n
*m_n
)
6815 struct drm_device
*dev
= crtc
->base
.dev
;
6816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6817 int pipe
= crtc
->pipe
;
6819 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6820 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6821 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6822 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6825 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6826 struct intel_link_m_n
*m_n
,
6827 struct intel_link_m_n
*m2_n2
)
6829 struct drm_device
*dev
= crtc
->base
.dev
;
6830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6831 int pipe
= crtc
->pipe
;
6832 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6834 if (INTEL_INFO(dev
)->gen
>= 5) {
6835 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6836 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6837 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6838 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6839 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6840 * for gen < 8) and if DRRS is supported (to make sure the
6841 * registers are not unnecessarily accessed).
6843 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
6844 crtc
->config
->has_drrs
) {
6845 I915_WRITE(PIPE_DATA_M2(transcoder
),
6846 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6847 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6848 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6849 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6852 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6853 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6854 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6855 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6859 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6861 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6864 dp_m_n
= &crtc
->config
->dp_m_n
;
6865 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6866 } else if (m_n
== M2_N2
) {
6869 * M2_N2 registers are not supported. Hence m2_n2 divider value
6870 * needs to be programmed into M1_N1.
6872 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6874 DRM_ERROR("Unsupported divider value\n");
6878 if (crtc
->config
->has_pch_encoder
)
6879 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6881 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6884 static void vlv_update_pll(struct intel_crtc
*crtc
,
6885 struct intel_crtc_state
*pipe_config
)
6890 * Enable DPIO clock input. We should never disable the reference
6891 * clock for pipe B, since VGA hotplug / manual detection depends
6894 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6895 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6896 /* We should never disable this, set it here for state tracking */
6897 if (crtc
->pipe
== PIPE_B
)
6898 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6899 dpll
|= DPLL_VCO_ENABLE
;
6900 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6902 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6903 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6904 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6907 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6908 const struct intel_crtc_state
*pipe_config
)
6910 struct drm_device
*dev
= crtc
->base
.dev
;
6911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6912 int pipe
= crtc
->pipe
;
6914 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6915 u32 coreclk
, reg_val
;
6917 mutex_lock(&dev_priv
->dpio_lock
);
6919 bestn
= pipe_config
->dpll
.n
;
6920 bestm1
= pipe_config
->dpll
.m1
;
6921 bestm2
= pipe_config
->dpll
.m2
;
6922 bestp1
= pipe_config
->dpll
.p1
;
6923 bestp2
= pipe_config
->dpll
.p2
;
6925 /* See eDP HDMI DPIO driver vbios notes doc */
6927 /* PLL B needs special handling */
6929 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6931 /* Set up Tx target for periodic Rcomp update */
6932 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6934 /* Disable target IRef on PLL */
6935 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6936 reg_val
&= 0x00ffffff;
6937 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6939 /* Disable fast lock */
6940 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6942 /* Set idtafcrecal before PLL is enabled */
6943 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6944 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6945 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6946 mdiv
|= (1 << DPIO_K_SHIFT
);
6949 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6950 * but we don't support that).
6951 * Note: don't use the DAC post divider as it seems unstable.
6953 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6954 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6956 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6957 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6959 /* Set HBR and RBR LPF coefficients */
6960 if (pipe_config
->port_clock
== 162000 ||
6961 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6962 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6963 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6966 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6969 if (pipe_config
->has_dp_encoder
) {
6970 /* Use SSC source */
6972 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6975 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6977 } else { /* HDMI or VGA */
6978 /* Use bend source */
6980 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6983 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6987 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6988 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6989 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6990 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6991 coreclk
|= 0x01000000;
6992 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6994 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6995 mutex_unlock(&dev_priv
->dpio_lock
);
6998 static void chv_update_pll(struct intel_crtc
*crtc
,
6999 struct intel_crtc_state
*pipe_config
)
7001 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
7002 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7004 if (crtc
->pipe
!= PIPE_A
)
7005 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7007 pipe_config
->dpll_hw_state
.dpll_md
=
7008 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7011 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7012 const struct intel_crtc_state
*pipe_config
)
7014 struct drm_device
*dev
= crtc
->base
.dev
;
7015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7016 int pipe
= crtc
->pipe
;
7017 int dpll_reg
= DPLL(crtc
->pipe
);
7018 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7019 u32 loopfilter
, tribuf_calcntr
;
7020 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7024 bestn
= pipe_config
->dpll
.n
;
7025 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7026 bestm1
= pipe_config
->dpll
.m1
;
7027 bestm2
= pipe_config
->dpll
.m2
>> 22;
7028 bestp1
= pipe_config
->dpll
.p1
;
7029 bestp2
= pipe_config
->dpll
.p2
;
7030 vco
= pipe_config
->dpll
.vco
;
7035 * Enable Refclk and SSC
7037 I915_WRITE(dpll_reg
,
7038 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7040 mutex_lock(&dev_priv
->dpio_lock
);
7042 /* p1 and p2 divider */
7043 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7044 5 << DPIO_CHV_S1_DIV_SHIFT
|
7045 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7046 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7047 1 << DPIO_CHV_K_DIV_SHIFT
);
7049 /* Feedback post-divider - m2 */
7050 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7052 /* Feedback refclk divider - n and m1 */
7053 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7054 DPIO_CHV_M1_DIV_BY_2
|
7055 1 << DPIO_CHV_N_DIV_SHIFT
);
7057 /* M2 fraction division */
7059 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7061 /* M2 fraction division enable */
7062 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7063 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7064 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7066 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7067 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7069 /* Program digital lock detect threshold */
7070 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7071 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7072 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7073 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7075 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7076 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7079 if (vco
== 5400000) {
7080 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7081 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7082 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7083 tribuf_calcntr
= 0x9;
7084 } else if (vco
<= 6200000) {
7085 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7086 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7087 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7088 tribuf_calcntr
= 0x9;
7089 } else if (vco
<= 6480000) {
7090 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7091 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7092 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7093 tribuf_calcntr
= 0x8;
7095 /* Not supported. Apply the same limits as in the max case */
7096 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7097 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7098 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7101 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7103 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7104 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7105 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7106 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7109 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7110 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7113 mutex_unlock(&dev_priv
->dpio_lock
);
7117 * vlv_force_pll_on - forcibly enable just the PLL
7118 * @dev_priv: i915 private structure
7119 * @pipe: pipe PLL to enable
7120 * @dpll: PLL configuration
7122 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7123 * in cases where we need the PLL enabled even when @pipe is not going to
7126 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7127 const struct dpll
*dpll
)
7129 struct intel_crtc
*crtc
=
7130 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7131 struct intel_crtc_state pipe_config
= {
7132 .base
.crtc
= &crtc
->base
,
7133 .pixel_multiplier
= 1,
7137 if (IS_CHERRYVIEW(dev
)) {
7138 chv_update_pll(crtc
, &pipe_config
);
7139 chv_prepare_pll(crtc
, &pipe_config
);
7140 chv_enable_pll(crtc
, &pipe_config
);
7142 vlv_update_pll(crtc
, &pipe_config
);
7143 vlv_prepare_pll(crtc
, &pipe_config
);
7144 vlv_enable_pll(crtc
, &pipe_config
);
7149 * vlv_force_pll_off - forcibly disable just the PLL
7150 * @dev_priv: i915 private structure
7151 * @pipe: pipe PLL to disable
7153 * Disable the PLL for @pipe. To be used in cases where we need
7154 * the PLL enabled even when @pipe is not going to be enabled.
7156 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7158 if (IS_CHERRYVIEW(dev
))
7159 chv_disable_pll(to_i915(dev
), pipe
);
7161 vlv_disable_pll(to_i915(dev
), pipe
);
7164 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7165 struct intel_crtc_state
*crtc_state
,
7166 intel_clock_t
*reduced_clock
,
7169 struct drm_device
*dev
= crtc
->base
.dev
;
7170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7173 struct dpll
*clock
= &crtc_state
->dpll
;
7175 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7177 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7178 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7180 dpll
= DPLL_VGA_MODE_DIS
;
7182 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7183 dpll
|= DPLLB_MODE_LVDS
;
7185 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7187 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7188 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7189 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7193 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7195 if (crtc_state
->has_dp_encoder
)
7196 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7198 /* compute bitmask from p1 value */
7199 if (IS_PINEVIEW(dev
))
7200 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7202 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7203 if (IS_G4X(dev
) && reduced_clock
)
7204 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7206 switch (clock
->p2
) {
7208 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7211 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7214 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7217 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7220 if (INTEL_INFO(dev
)->gen
>= 4)
7221 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7223 if (crtc_state
->sdvo_tv_clock
)
7224 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7225 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7226 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7227 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7229 dpll
|= PLL_REF_INPUT_DREFCLK
;
7231 dpll
|= DPLL_VCO_ENABLE
;
7232 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7234 if (INTEL_INFO(dev
)->gen
>= 4) {
7235 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7236 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7237 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7241 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7242 struct intel_crtc_state
*crtc_state
,
7243 intel_clock_t
*reduced_clock
,
7246 struct drm_device
*dev
= crtc
->base
.dev
;
7247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7249 struct dpll
*clock
= &crtc_state
->dpll
;
7251 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7253 dpll
= DPLL_VGA_MODE_DIS
;
7255 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7256 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7259 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7261 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7263 dpll
|= PLL_P2_DIVIDE_BY_4
;
7266 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7267 dpll
|= DPLL_DVO_2X_MODE
;
7269 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7270 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7271 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7273 dpll
|= PLL_REF_INPUT_DREFCLK
;
7275 dpll
|= DPLL_VCO_ENABLE
;
7276 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7279 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7281 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7283 enum pipe pipe
= intel_crtc
->pipe
;
7284 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7285 struct drm_display_mode
*adjusted_mode
=
7286 &intel_crtc
->config
->base
.adjusted_mode
;
7287 uint32_t crtc_vtotal
, crtc_vblank_end
;
7290 /* We need to be careful not to changed the adjusted mode, for otherwise
7291 * the hw state checker will get angry at the mismatch. */
7292 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7293 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7295 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7296 /* the chip adds 2 halflines automatically */
7298 crtc_vblank_end
-= 1;
7300 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7301 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7303 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7304 adjusted_mode
->crtc_htotal
/ 2;
7306 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7309 if (INTEL_INFO(dev
)->gen
> 3)
7310 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7312 I915_WRITE(HTOTAL(cpu_transcoder
),
7313 (adjusted_mode
->crtc_hdisplay
- 1) |
7314 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7315 I915_WRITE(HBLANK(cpu_transcoder
),
7316 (adjusted_mode
->crtc_hblank_start
- 1) |
7317 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7318 I915_WRITE(HSYNC(cpu_transcoder
),
7319 (adjusted_mode
->crtc_hsync_start
- 1) |
7320 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7322 I915_WRITE(VTOTAL(cpu_transcoder
),
7323 (adjusted_mode
->crtc_vdisplay
- 1) |
7324 ((crtc_vtotal
- 1) << 16));
7325 I915_WRITE(VBLANK(cpu_transcoder
),
7326 (adjusted_mode
->crtc_vblank_start
- 1) |
7327 ((crtc_vblank_end
- 1) << 16));
7328 I915_WRITE(VSYNC(cpu_transcoder
),
7329 (adjusted_mode
->crtc_vsync_start
- 1) |
7330 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7332 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7333 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7334 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7336 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7337 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7338 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7340 /* pipesrc controls the size that is scaled from, which should
7341 * always be the user's requested size.
7343 I915_WRITE(PIPESRC(pipe
),
7344 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7345 (intel_crtc
->config
->pipe_src_h
- 1));
7348 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7349 struct intel_crtc_state
*pipe_config
)
7351 struct drm_device
*dev
= crtc
->base
.dev
;
7352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7353 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7356 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7357 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7358 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7359 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7360 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7361 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7362 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7363 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7364 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7366 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7367 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7368 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7369 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7370 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7371 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7372 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7373 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7374 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7376 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7377 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7378 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7379 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7382 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7383 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7384 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7386 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7387 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7390 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7391 struct intel_crtc_state
*pipe_config
)
7393 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7394 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7395 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7396 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7398 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7399 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7400 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7401 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7403 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7405 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7406 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7409 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7411 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7417 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7418 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7419 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7421 if (intel_crtc
->config
->double_wide
)
7422 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7424 /* only g4x and later have fancy bpc/dither controls */
7425 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7426 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7427 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7428 pipeconf
|= PIPECONF_DITHER_EN
|
7429 PIPECONF_DITHER_TYPE_SP
;
7431 switch (intel_crtc
->config
->pipe_bpp
) {
7433 pipeconf
|= PIPECONF_6BPC
;
7436 pipeconf
|= PIPECONF_8BPC
;
7439 pipeconf
|= PIPECONF_10BPC
;
7442 /* Case prevented by intel_choose_pipe_bpp_dither. */
7447 if (HAS_PIPE_CXSR(dev
)) {
7448 if (intel_crtc
->lowfreq_avail
) {
7449 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7450 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7452 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7456 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7457 if (INTEL_INFO(dev
)->gen
< 4 ||
7458 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7459 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7461 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7463 pipeconf
|= PIPECONF_PROGRESSIVE
;
7465 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7466 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7468 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7469 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7472 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7473 struct intel_crtc_state
*crtc_state
)
7475 struct drm_device
*dev
= crtc
->base
.dev
;
7476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7477 int refclk
, num_connectors
= 0;
7478 intel_clock_t clock
, reduced_clock
;
7479 bool ok
, has_reduced_clock
= false;
7480 bool is_lvds
= false, is_dsi
= false;
7481 struct intel_encoder
*encoder
;
7482 const intel_limit_t
*limit
;
7483 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7484 struct drm_connector
*connector
;
7485 struct drm_connector_state
*connector_state
;
7488 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7489 if (connector_state
->crtc
!= &crtc
->base
)
7492 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7494 switch (encoder
->type
) {
7495 case INTEL_OUTPUT_LVDS
:
7498 case INTEL_OUTPUT_DSI
:
7511 if (!crtc_state
->clock_set
) {
7512 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7515 * Returns a set of divisors for the desired target clock with
7516 * the given refclk, or FALSE. The returned values represent
7517 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7520 limit
= intel_limit(crtc_state
, refclk
);
7521 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7522 crtc_state
->port_clock
,
7523 refclk
, NULL
, &clock
);
7525 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7529 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7531 * Ensure we match the reduced clock's P to the target
7532 * clock. If the clocks don't match, we can't switch
7533 * the display clock by using the FP0/FP1. In such case
7534 * we will disable the LVDS downclock feature.
7537 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7538 dev_priv
->lvds_downclock
,
7542 /* Compat-code for transition, will disappear. */
7543 crtc_state
->dpll
.n
= clock
.n
;
7544 crtc_state
->dpll
.m1
= clock
.m1
;
7545 crtc_state
->dpll
.m2
= clock
.m2
;
7546 crtc_state
->dpll
.p1
= clock
.p1
;
7547 crtc_state
->dpll
.p2
= clock
.p2
;
7551 i8xx_update_pll(crtc
, crtc_state
,
7552 has_reduced_clock
? &reduced_clock
: NULL
,
7554 } else if (IS_CHERRYVIEW(dev
)) {
7555 chv_update_pll(crtc
, crtc_state
);
7556 } else if (IS_VALLEYVIEW(dev
)) {
7557 vlv_update_pll(crtc
, crtc_state
);
7559 i9xx_update_pll(crtc
, crtc_state
,
7560 has_reduced_clock
? &reduced_clock
: NULL
,
7567 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7568 struct intel_crtc_state
*pipe_config
)
7570 struct drm_device
*dev
= crtc
->base
.dev
;
7571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7574 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7577 tmp
= I915_READ(PFIT_CONTROL
);
7578 if (!(tmp
& PFIT_ENABLE
))
7581 /* Check whether the pfit is attached to our pipe. */
7582 if (INTEL_INFO(dev
)->gen
< 4) {
7583 if (crtc
->pipe
!= PIPE_B
)
7586 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7590 pipe_config
->gmch_pfit
.control
= tmp
;
7591 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7592 if (INTEL_INFO(dev
)->gen
< 5)
7593 pipe_config
->gmch_pfit
.lvds_border_bits
=
7594 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7597 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7598 struct intel_crtc_state
*pipe_config
)
7600 struct drm_device
*dev
= crtc
->base
.dev
;
7601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7602 int pipe
= pipe_config
->cpu_transcoder
;
7603 intel_clock_t clock
;
7605 int refclk
= 100000;
7607 /* In case of MIPI DPLL will not even be used */
7608 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7611 mutex_lock(&dev_priv
->dpio_lock
);
7612 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7613 mutex_unlock(&dev_priv
->dpio_lock
);
7615 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7616 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7617 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7618 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7619 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7621 vlv_clock(refclk
, &clock
);
7623 /* clock.dot is the fast clock */
7624 pipe_config
->port_clock
= clock
.dot
/ 5;
7628 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7629 struct intel_initial_plane_config
*plane_config
)
7631 struct drm_device
*dev
= crtc
->base
.dev
;
7632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7633 u32 val
, base
, offset
;
7634 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7635 int fourcc
, pixel_format
;
7636 unsigned int aligned_height
;
7637 struct drm_framebuffer
*fb
;
7638 struct intel_framebuffer
*intel_fb
;
7640 val
= I915_READ(DSPCNTR(plane
));
7641 if (!(val
& DISPLAY_PLANE_ENABLE
))
7644 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7646 DRM_DEBUG_KMS("failed to alloc fb\n");
7650 fb
= &intel_fb
->base
;
7652 if (INTEL_INFO(dev
)->gen
>= 4) {
7653 if (val
& DISPPLANE_TILED
) {
7654 plane_config
->tiling
= I915_TILING_X
;
7655 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7659 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7660 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7661 fb
->pixel_format
= fourcc
;
7662 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7664 if (INTEL_INFO(dev
)->gen
>= 4) {
7665 if (plane_config
->tiling
)
7666 offset
= I915_READ(DSPTILEOFF(plane
));
7668 offset
= I915_READ(DSPLINOFF(plane
));
7669 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7671 base
= I915_READ(DSPADDR(plane
));
7673 plane_config
->base
= base
;
7675 val
= I915_READ(PIPESRC(pipe
));
7676 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7677 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7679 val
= I915_READ(DSPSTRIDE(pipe
));
7680 fb
->pitches
[0] = val
& 0xffffffc0;
7682 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7686 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7688 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7689 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7690 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7691 plane_config
->size
);
7693 plane_config
->fb
= intel_fb
;
7696 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7697 struct intel_crtc_state
*pipe_config
)
7699 struct drm_device
*dev
= crtc
->base
.dev
;
7700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7701 int pipe
= pipe_config
->cpu_transcoder
;
7702 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7703 intel_clock_t clock
;
7704 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7705 int refclk
= 100000;
7707 mutex_lock(&dev_priv
->dpio_lock
);
7708 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7709 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7710 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7711 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7712 mutex_unlock(&dev_priv
->dpio_lock
);
7714 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7715 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7716 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7717 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7718 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7720 chv_clock(refclk
, &clock
);
7722 /* clock.dot is the fast clock */
7723 pipe_config
->port_clock
= clock
.dot
/ 5;
7726 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7727 struct intel_crtc_state
*pipe_config
)
7729 struct drm_device
*dev
= crtc
->base
.dev
;
7730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7733 if (!intel_display_power_is_enabled(dev_priv
,
7734 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7737 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7738 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7740 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7741 if (!(tmp
& PIPECONF_ENABLE
))
7744 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7745 switch (tmp
& PIPECONF_BPC_MASK
) {
7747 pipe_config
->pipe_bpp
= 18;
7750 pipe_config
->pipe_bpp
= 24;
7752 case PIPECONF_10BPC
:
7753 pipe_config
->pipe_bpp
= 30;
7760 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7761 pipe_config
->limited_color_range
= true;
7763 if (INTEL_INFO(dev
)->gen
< 4)
7764 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7766 intel_get_pipe_timings(crtc
, pipe_config
);
7768 i9xx_get_pfit_config(crtc
, pipe_config
);
7770 if (INTEL_INFO(dev
)->gen
>= 4) {
7771 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7772 pipe_config
->pixel_multiplier
=
7773 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7774 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7775 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7776 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7777 tmp
= I915_READ(DPLL(crtc
->pipe
));
7778 pipe_config
->pixel_multiplier
=
7779 ((tmp
& SDVO_MULTIPLIER_MASK
)
7780 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7782 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7783 * port and will be fixed up in the encoder->get_config
7785 pipe_config
->pixel_multiplier
= 1;
7787 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7788 if (!IS_VALLEYVIEW(dev
)) {
7790 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7791 * on 830. Filter it out here so that we don't
7792 * report errors due to that.
7795 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7797 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7798 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7800 /* Mask out read-only status bits. */
7801 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7802 DPLL_PORTC_READY_MASK
|
7803 DPLL_PORTB_READY_MASK
);
7806 if (IS_CHERRYVIEW(dev
))
7807 chv_crtc_clock_get(crtc
, pipe_config
);
7808 else if (IS_VALLEYVIEW(dev
))
7809 vlv_crtc_clock_get(crtc
, pipe_config
);
7811 i9xx_crtc_clock_get(crtc
, pipe_config
);
7816 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7819 struct intel_encoder
*encoder
;
7821 bool has_lvds
= false;
7822 bool has_cpu_edp
= false;
7823 bool has_panel
= false;
7824 bool has_ck505
= false;
7825 bool can_ssc
= false;
7827 /* We need to take the global config into account */
7828 for_each_intel_encoder(dev
, encoder
) {
7829 switch (encoder
->type
) {
7830 case INTEL_OUTPUT_LVDS
:
7834 case INTEL_OUTPUT_EDP
:
7836 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7844 if (HAS_PCH_IBX(dev
)) {
7845 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7846 can_ssc
= has_ck505
;
7852 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7853 has_panel
, has_lvds
, has_ck505
);
7855 /* Ironlake: try to setup display ref clock before DPLL
7856 * enabling. This is only under driver's control after
7857 * PCH B stepping, previous chipset stepping should be
7858 * ignoring this setting.
7860 val
= I915_READ(PCH_DREF_CONTROL
);
7862 /* As we must carefully and slowly disable/enable each source in turn,
7863 * compute the final state we want first and check if we need to
7864 * make any changes at all.
7867 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7869 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7871 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7873 final
&= ~DREF_SSC_SOURCE_MASK
;
7874 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7875 final
&= ~DREF_SSC1_ENABLE
;
7878 final
|= DREF_SSC_SOURCE_ENABLE
;
7880 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7881 final
|= DREF_SSC1_ENABLE
;
7884 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7885 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7887 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7889 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7891 final
|= DREF_SSC_SOURCE_DISABLE
;
7892 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7898 /* Always enable nonspread source */
7899 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7902 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7904 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7907 val
&= ~DREF_SSC_SOURCE_MASK
;
7908 val
|= DREF_SSC_SOURCE_ENABLE
;
7910 /* SSC must be turned on before enabling the CPU output */
7911 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7912 DRM_DEBUG_KMS("Using SSC on panel\n");
7913 val
|= DREF_SSC1_ENABLE
;
7915 val
&= ~DREF_SSC1_ENABLE
;
7917 /* Get SSC going before enabling the outputs */
7918 I915_WRITE(PCH_DREF_CONTROL
, val
);
7919 POSTING_READ(PCH_DREF_CONTROL
);
7922 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7924 /* Enable CPU source on CPU attached eDP */
7926 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7927 DRM_DEBUG_KMS("Using SSC on eDP\n");
7928 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7930 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7932 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7934 I915_WRITE(PCH_DREF_CONTROL
, val
);
7935 POSTING_READ(PCH_DREF_CONTROL
);
7938 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7940 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7942 /* Turn off CPU output */
7943 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7945 I915_WRITE(PCH_DREF_CONTROL
, val
);
7946 POSTING_READ(PCH_DREF_CONTROL
);
7949 /* Turn off the SSC source */
7950 val
&= ~DREF_SSC_SOURCE_MASK
;
7951 val
|= DREF_SSC_SOURCE_DISABLE
;
7954 val
&= ~DREF_SSC1_ENABLE
;
7956 I915_WRITE(PCH_DREF_CONTROL
, val
);
7957 POSTING_READ(PCH_DREF_CONTROL
);
7961 BUG_ON(val
!= final
);
7964 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7968 tmp
= I915_READ(SOUTH_CHICKEN2
);
7969 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7970 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7972 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7973 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7974 DRM_ERROR("FDI mPHY reset assert timeout\n");
7976 tmp
= I915_READ(SOUTH_CHICKEN2
);
7977 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7978 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7980 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7981 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7982 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7985 /* WaMPhyProgramming:hsw */
7986 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7990 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7991 tmp
&= ~(0xFF << 24);
7992 tmp
|= (0x12 << 24);
7993 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7995 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7997 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7999 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8001 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8003 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8004 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8005 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8007 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8008 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8009 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8011 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8014 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8016 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8019 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8021 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8024 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8026 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8029 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8031 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8032 tmp
&= ~(0xFF << 16);
8033 tmp
|= (0x1C << 16);
8034 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8036 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8037 tmp
&= ~(0xFF << 16);
8038 tmp
|= (0x1C << 16);
8039 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8041 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8043 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8045 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8047 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8049 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8050 tmp
&= ~(0xF << 28);
8052 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8054 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8055 tmp
&= ~(0xF << 28);
8057 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8060 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8061 * Programming" based on the parameters passed:
8062 * - Sequence to enable CLKOUT_DP
8063 * - Sequence to enable CLKOUT_DP without spread
8064 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8066 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8072 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8074 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8075 with_fdi
, "LP PCH doesn't have FDI\n"))
8078 mutex_lock(&dev_priv
->dpio_lock
);
8080 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8081 tmp
&= ~SBI_SSCCTL_DISABLE
;
8082 tmp
|= SBI_SSCCTL_PATHALT
;
8083 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8088 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8089 tmp
&= ~SBI_SSCCTL_PATHALT
;
8090 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8093 lpt_reset_fdi_mphy(dev_priv
);
8094 lpt_program_fdi_mphy(dev_priv
);
8098 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8099 SBI_GEN0
: SBI_DBUFF0
;
8100 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8101 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8102 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8104 mutex_unlock(&dev_priv
->dpio_lock
);
8107 /* Sequence to disable CLKOUT_DP */
8108 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8113 mutex_lock(&dev_priv
->dpio_lock
);
8115 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8116 SBI_GEN0
: SBI_DBUFF0
;
8117 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8118 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8119 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8121 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8122 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8123 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8124 tmp
|= SBI_SSCCTL_PATHALT
;
8125 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8128 tmp
|= SBI_SSCCTL_DISABLE
;
8129 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8132 mutex_unlock(&dev_priv
->dpio_lock
);
8135 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8137 struct intel_encoder
*encoder
;
8138 bool has_vga
= false;
8140 for_each_intel_encoder(dev
, encoder
) {
8141 switch (encoder
->type
) {
8142 case INTEL_OUTPUT_ANALOG
:
8151 lpt_enable_clkout_dp(dev
, true, true);
8153 lpt_disable_clkout_dp(dev
);
8157 * Initialize reference clocks when the driver loads
8159 void intel_init_pch_refclk(struct drm_device
*dev
)
8161 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8162 ironlake_init_pch_refclk(dev
);
8163 else if (HAS_PCH_LPT(dev
))
8164 lpt_init_pch_refclk(dev
);
8167 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8169 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8171 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8172 struct drm_connector
*connector
;
8173 struct drm_connector_state
*connector_state
;
8174 struct intel_encoder
*encoder
;
8175 int num_connectors
= 0, i
;
8176 bool is_lvds
= false;
8178 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8179 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8182 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8184 switch (encoder
->type
) {
8185 case INTEL_OUTPUT_LVDS
:
8194 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8195 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8196 dev_priv
->vbt
.lvds_ssc_freq
);
8197 return dev_priv
->vbt
.lvds_ssc_freq
;
8203 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8205 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8207 int pipe
= intel_crtc
->pipe
;
8212 switch (intel_crtc
->config
->pipe_bpp
) {
8214 val
|= PIPECONF_6BPC
;
8217 val
|= PIPECONF_8BPC
;
8220 val
|= PIPECONF_10BPC
;
8223 val
|= PIPECONF_12BPC
;
8226 /* Case prevented by intel_choose_pipe_bpp_dither. */
8230 if (intel_crtc
->config
->dither
)
8231 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8233 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8234 val
|= PIPECONF_INTERLACED_ILK
;
8236 val
|= PIPECONF_PROGRESSIVE
;
8238 if (intel_crtc
->config
->limited_color_range
)
8239 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8241 I915_WRITE(PIPECONF(pipe
), val
);
8242 POSTING_READ(PIPECONF(pipe
));
8246 * Set up the pipe CSC unit.
8248 * Currently only full range RGB to limited range RGB conversion
8249 * is supported, but eventually this should handle various
8250 * RGB<->YCbCr scenarios as well.
8252 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8254 struct drm_device
*dev
= crtc
->dev
;
8255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8257 int pipe
= intel_crtc
->pipe
;
8258 uint16_t coeff
= 0x7800; /* 1.0 */
8261 * TODO: Check what kind of values actually come out of the pipe
8262 * with these coeff/postoff values and adjust to get the best
8263 * accuracy. Perhaps we even need to take the bpc value into
8267 if (intel_crtc
->config
->limited_color_range
)
8268 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8271 * GY/GU and RY/RU should be the other way around according
8272 * to BSpec, but reality doesn't agree. Just set them up in
8273 * a way that results in the correct picture.
8275 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8276 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8278 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8279 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8281 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8282 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8284 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8285 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8286 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8288 if (INTEL_INFO(dev
)->gen
> 6) {
8289 uint16_t postoff
= 0;
8291 if (intel_crtc
->config
->limited_color_range
)
8292 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8294 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8295 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8296 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8298 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8300 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8302 if (intel_crtc
->config
->limited_color_range
)
8303 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8305 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8309 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8311 struct drm_device
*dev
= crtc
->dev
;
8312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8314 enum pipe pipe
= intel_crtc
->pipe
;
8315 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8320 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8321 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8323 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8324 val
|= PIPECONF_INTERLACED_ILK
;
8326 val
|= PIPECONF_PROGRESSIVE
;
8328 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8329 POSTING_READ(PIPECONF(cpu_transcoder
));
8331 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8332 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8334 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8337 switch (intel_crtc
->config
->pipe_bpp
) {
8339 val
|= PIPEMISC_DITHER_6_BPC
;
8342 val
|= PIPEMISC_DITHER_8_BPC
;
8345 val
|= PIPEMISC_DITHER_10_BPC
;
8348 val
|= PIPEMISC_DITHER_12_BPC
;
8351 /* Case prevented by pipe_config_set_bpp. */
8355 if (intel_crtc
->config
->dither
)
8356 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8358 I915_WRITE(PIPEMISC(pipe
), val
);
8362 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8363 struct intel_crtc_state
*crtc_state
,
8364 intel_clock_t
*clock
,
8365 bool *has_reduced_clock
,
8366 intel_clock_t
*reduced_clock
)
8368 struct drm_device
*dev
= crtc
->dev
;
8369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8371 const intel_limit_t
*limit
;
8372 bool ret
, is_lvds
= false;
8374 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8376 refclk
= ironlake_get_refclk(crtc_state
);
8379 * Returns a set of divisors for the desired target clock with the given
8380 * refclk, or FALSE. The returned values represent the clock equation:
8381 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8383 limit
= intel_limit(crtc_state
, refclk
);
8384 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8385 crtc_state
->port_clock
,
8386 refclk
, NULL
, clock
);
8390 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8392 * Ensure we match the reduced clock's P to the target clock.
8393 * If the clocks don't match, we can't switch the display clock
8394 * by using the FP0/FP1. In such case we will disable the LVDS
8395 * downclock feature.
8397 *has_reduced_clock
=
8398 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8399 dev_priv
->lvds_downclock
,
8407 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8410 * Account for spread spectrum to avoid
8411 * oversubscribing the link. Max center spread
8412 * is 2.5%; use 5% for safety's sake.
8414 u32 bps
= target_clock
* bpp
* 21 / 20;
8415 return DIV_ROUND_UP(bps
, link_bw
* 8);
8418 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8420 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8423 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8424 struct intel_crtc_state
*crtc_state
,
8426 intel_clock_t
*reduced_clock
, u32
*fp2
)
8428 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8429 struct drm_device
*dev
= crtc
->dev
;
8430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8431 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8432 struct drm_connector
*connector
;
8433 struct drm_connector_state
*connector_state
;
8434 struct intel_encoder
*encoder
;
8436 int factor
, num_connectors
= 0, i
;
8437 bool is_lvds
= false, is_sdvo
= false;
8439 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8440 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8443 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8445 switch (encoder
->type
) {
8446 case INTEL_OUTPUT_LVDS
:
8449 case INTEL_OUTPUT_SDVO
:
8450 case INTEL_OUTPUT_HDMI
:
8460 /* Enable autotuning of the PLL clock (if permissible) */
8463 if ((intel_panel_use_ssc(dev_priv
) &&
8464 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8465 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8467 } else if (crtc_state
->sdvo_tv_clock
)
8470 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8473 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8479 dpll
|= DPLLB_MODE_LVDS
;
8481 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8483 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8484 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8487 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8488 if (crtc_state
->has_dp_encoder
)
8489 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8491 /* compute bitmask from p1 value */
8492 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8494 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8496 switch (crtc_state
->dpll
.p2
) {
8498 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8501 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8504 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8507 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8511 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8512 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8514 dpll
|= PLL_REF_INPUT_DREFCLK
;
8516 return dpll
| DPLL_VCO_ENABLE
;
8519 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8520 struct intel_crtc_state
*crtc_state
)
8522 struct drm_device
*dev
= crtc
->base
.dev
;
8523 intel_clock_t clock
, reduced_clock
;
8524 u32 dpll
= 0, fp
= 0, fp2
= 0;
8525 bool ok
, has_reduced_clock
= false;
8526 bool is_lvds
= false;
8527 struct intel_shared_dpll
*pll
;
8529 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8531 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8532 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8534 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8535 &has_reduced_clock
, &reduced_clock
);
8536 if (!ok
&& !crtc_state
->clock_set
) {
8537 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8540 /* Compat-code for transition, will disappear. */
8541 if (!crtc_state
->clock_set
) {
8542 crtc_state
->dpll
.n
= clock
.n
;
8543 crtc_state
->dpll
.m1
= clock
.m1
;
8544 crtc_state
->dpll
.m2
= clock
.m2
;
8545 crtc_state
->dpll
.p1
= clock
.p1
;
8546 crtc_state
->dpll
.p2
= clock
.p2
;
8549 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8550 if (crtc_state
->has_pch_encoder
) {
8551 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8552 if (has_reduced_clock
)
8553 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8555 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8556 &fp
, &reduced_clock
,
8557 has_reduced_clock
? &fp2
: NULL
);
8559 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8560 crtc_state
->dpll_hw_state
.fp0
= fp
;
8561 if (has_reduced_clock
)
8562 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8564 crtc_state
->dpll_hw_state
.fp1
= fp
;
8566 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8568 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8569 pipe_name(crtc
->pipe
));
8574 if (is_lvds
&& has_reduced_clock
)
8575 crtc
->lowfreq_avail
= true;
8577 crtc
->lowfreq_avail
= false;
8582 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8583 struct intel_link_m_n
*m_n
)
8585 struct drm_device
*dev
= crtc
->base
.dev
;
8586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8587 enum pipe pipe
= crtc
->pipe
;
8589 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8590 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8591 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8593 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8594 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8595 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8598 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8599 enum transcoder transcoder
,
8600 struct intel_link_m_n
*m_n
,
8601 struct intel_link_m_n
*m2_n2
)
8603 struct drm_device
*dev
= crtc
->base
.dev
;
8604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8605 enum pipe pipe
= crtc
->pipe
;
8607 if (INTEL_INFO(dev
)->gen
>= 5) {
8608 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8609 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8610 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8612 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8613 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8614 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8615 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8616 * gen < 8) and if DRRS is supported (to make sure the
8617 * registers are not unnecessarily read).
8619 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8620 crtc
->config
->has_drrs
) {
8621 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8622 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8623 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8625 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8626 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8627 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8630 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8631 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8632 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8634 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8635 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8636 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8640 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8641 struct intel_crtc_state
*pipe_config
)
8643 if (pipe_config
->has_pch_encoder
)
8644 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8646 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8647 &pipe_config
->dp_m_n
,
8648 &pipe_config
->dp_m2_n2
);
8651 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8652 struct intel_crtc_state
*pipe_config
)
8654 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8655 &pipe_config
->fdi_m_n
, NULL
);
8658 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8659 struct intel_crtc_state
*pipe_config
)
8661 struct drm_device
*dev
= crtc
->base
.dev
;
8662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8663 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8664 uint32_t ps_ctrl
= 0;
8668 /* find scaler attached to this pipe */
8669 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8670 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8671 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8673 pipe_config
->pch_pfit
.enabled
= true;
8674 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8675 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8680 scaler_state
->scaler_id
= id
;
8682 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8684 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8689 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8690 struct intel_initial_plane_config
*plane_config
)
8692 struct drm_device
*dev
= crtc
->base
.dev
;
8693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8694 u32 val
, base
, offset
, stride_mult
, tiling
;
8695 int pipe
= crtc
->pipe
;
8696 int fourcc
, pixel_format
;
8697 unsigned int aligned_height
;
8698 struct drm_framebuffer
*fb
;
8699 struct intel_framebuffer
*intel_fb
;
8701 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8703 DRM_DEBUG_KMS("failed to alloc fb\n");
8707 fb
= &intel_fb
->base
;
8709 val
= I915_READ(PLANE_CTL(pipe
, 0));
8710 if (!(val
& PLANE_CTL_ENABLE
))
8713 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8714 fourcc
= skl_format_to_fourcc(pixel_format
,
8715 val
& PLANE_CTL_ORDER_RGBX
,
8716 val
& PLANE_CTL_ALPHA_MASK
);
8717 fb
->pixel_format
= fourcc
;
8718 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8720 tiling
= val
& PLANE_CTL_TILED_MASK
;
8722 case PLANE_CTL_TILED_LINEAR
:
8723 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8725 case PLANE_CTL_TILED_X
:
8726 plane_config
->tiling
= I915_TILING_X
;
8727 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8729 case PLANE_CTL_TILED_Y
:
8730 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8732 case PLANE_CTL_TILED_YF
:
8733 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8736 MISSING_CASE(tiling
);
8740 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8741 plane_config
->base
= base
;
8743 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8745 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8746 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8747 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8749 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8750 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8752 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8754 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8758 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8760 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8761 pipe_name(pipe
), fb
->width
, fb
->height
,
8762 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8763 plane_config
->size
);
8765 plane_config
->fb
= intel_fb
;
8772 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8773 struct intel_crtc_state
*pipe_config
)
8775 struct drm_device
*dev
= crtc
->base
.dev
;
8776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8779 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8781 if (tmp
& PF_ENABLE
) {
8782 pipe_config
->pch_pfit
.enabled
= true;
8783 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8784 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8786 /* We currently do not free assignements of panel fitters on
8787 * ivb/hsw (since we don't use the higher upscaling modes which
8788 * differentiates them) so just WARN about this case for now. */
8790 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8791 PF_PIPE_SEL_IVB(crtc
->pipe
));
8797 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8798 struct intel_initial_plane_config
*plane_config
)
8800 struct drm_device
*dev
= crtc
->base
.dev
;
8801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8802 u32 val
, base
, offset
;
8803 int pipe
= crtc
->pipe
;
8804 int fourcc
, pixel_format
;
8805 unsigned int aligned_height
;
8806 struct drm_framebuffer
*fb
;
8807 struct intel_framebuffer
*intel_fb
;
8809 val
= I915_READ(DSPCNTR(pipe
));
8810 if (!(val
& DISPLAY_PLANE_ENABLE
))
8813 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8815 DRM_DEBUG_KMS("failed to alloc fb\n");
8819 fb
= &intel_fb
->base
;
8821 if (INTEL_INFO(dev
)->gen
>= 4) {
8822 if (val
& DISPPLANE_TILED
) {
8823 plane_config
->tiling
= I915_TILING_X
;
8824 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8828 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8829 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8830 fb
->pixel_format
= fourcc
;
8831 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8833 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8834 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
8835 offset
= I915_READ(DSPOFFSET(pipe
));
8837 if (plane_config
->tiling
)
8838 offset
= I915_READ(DSPTILEOFF(pipe
));
8840 offset
= I915_READ(DSPLINOFF(pipe
));
8842 plane_config
->base
= base
;
8844 val
= I915_READ(PIPESRC(pipe
));
8845 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8846 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8848 val
= I915_READ(DSPSTRIDE(pipe
));
8849 fb
->pitches
[0] = val
& 0xffffffc0;
8851 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8855 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8857 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8858 pipe_name(pipe
), fb
->width
, fb
->height
,
8859 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8860 plane_config
->size
);
8862 plane_config
->fb
= intel_fb
;
8865 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8866 struct intel_crtc_state
*pipe_config
)
8868 struct drm_device
*dev
= crtc
->base
.dev
;
8869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8872 if (!intel_display_power_is_enabled(dev_priv
,
8873 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8876 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8877 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8879 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8880 if (!(tmp
& PIPECONF_ENABLE
))
8883 switch (tmp
& PIPECONF_BPC_MASK
) {
8885 pipe_config
->pipe_bpp
= 18;
8888 pipe_config
->pipe_bpp
= 24;
8890 case PIPECONF_10BPC
:
8891 pipe_config
->pipe_bpp
= 30;
8893 case PIPECONF_12BPC
:
8894 pipe_config
->pipe_bpp
= 36;
8900 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8901 pipe_config
->limited_color_range
= true;
8903 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8904 struct intel_shared_dpll
*pll
;
8906 pipe_config
->has_pch_encoder
= true;
8908 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8909 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8910 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8912 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8914 if (HAS_PCH_IBX(dev_priv
->dev
)) {
8915 pipe_config
->shared_dpll
=
8916 (enum intel_dpll_id
) crtc
->pipe
;
8918 tmp
= I915_READ(PCH_DPLL_SEL
);
8919 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8920 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
8922 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
8925 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8927 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8928 &pipe_config
->dpll_hw_state
));
8930 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8931 pipe_config
->pixel_multiplier
=
8932 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8933 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8935 ironlake_pch_clock_get(crtc
, pipe_config
);
8937 pipe_config
->pixel_multiplier
= 1;
8940 intel_get_pipe_timings(crtc
, pipe_config
);
8942 ironlake_get_pfit_config(crtc
, pipe_config
);
8947 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8949 struct drm_device
*dev
= dev_priv
->dev
;
8950 struct intel_crtc
*crtc
;
8952 for_each_intel_crtc(dev
, crtc
)
8953 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8954 pipe_name(crtc
->pipe
));
8956 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8957 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8958 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8959 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8960 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8961 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8962 "CPU PWM1 enabled\n");
8963 if (IS_HASWELL(dev
))
8964 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8965 "CPU PWM2 enabled\n");
8966 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8967 "PCH PWM1 enabled\n");
8968 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8969 "Utility pin enabled\n");
8970 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8973 * In theory we can still leave IRQs enabled, as long as only the HPD
8974 * interrupts remain enabled. We used to check for that, but since it's
8975 * gen-specific and since we only disable LCPLL after we fully disable
8976 * the interrupts, the check below should be enough.
8978 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8981 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8983 struct drm_device
*dev
= dev_priv
->dev
;
8985 if (IS_HASWELL(dev
))
8986 return I915_READ(D_COMP_HSW
);
8988 return I915_READ(D_COMP_BDW
);
8991 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8993 struct drm_device
*dev
= dev_priv
->dev
;
8995 if (IS_HASWELL(dev
)) {
8996 mutex_lock(&dev_priv
->rps
.hw_lock
);
8997 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8999 DRM_ERROR("Failed to write to D_COMP\n");
9000 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9002 I915_WRITE(D_COMP_BDW
, val
);
9003 POSTING_READ(D_COMP_BDW
);
9008 * This function implements pieces of two sequences from BSpec:
9009 * - Sequence for display software to disable LCPLL
9010 * - Sequence for display software to allow package C8+
9011 * The steps implemented here are just the steps that actually touch the LCPLL
9012 * register. Callers should take care of disabling all the display engine
9013 * functions, doing the mode unset, fixing interrupts, etc.
9015 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9016 bool switch_to_fclk
, bool allow_power_down
)
9020 assert_can_disable_lcpll(dev_priv
);
9022 val
= I915_READ(LCPLL_CTL
);
9024 if (switch_to_fclk
) {
9025 val
|= LCPLL_CD_SOURCE_FCLK
;
9026 I915_WRITE(LCPLL_CTL
, val
);
9028 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9029 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9030 DRM_ERROR("Switching to FCLK failed\n");
9032 val
= I915_READ(LCPLL_CTL
);
9035 val
|= LCPLL_PLL_DISABLE
;
9036 I915_WRITE(LCPLL_CTL
, val
);
9037 POSTING_READ(LCPLL_CTL
);
9039 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9040 DRM_ERROR("LCPLL still locked\n");
9042 val
= hsw_read_dcomp(dev_priv
);
9043 val
|= D_COMP_COMP_DISABLE
;
9044 hsw_write_dcomp(dev_priv
, val
);
9047 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9049 DRM_ERROR("D_COMP RCOMP still in progress\n");
9051 if (allow_power_down
) {
9052 val
= I915_READ(LCPLL_CTL
);
9053 val
|= LCPLL_POWER_DOWN_ALLOW
;
9054 I915_WRITE(LCPLL_CTL
, val
);
9055 POSTING_READ(LCPLL_CTL
);
9060 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9063 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9067 val
= I915_READ(LCPLL_CTL
);
9069 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9070 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9074 * Make sure we're not on PC8 state before disabling PC8, otherwise
9075 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9077 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9079 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9080 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9081 I915_WRITE(LCPLL_CTL
, val
);
9082 POSTING_READ(LCPLL_CTL
);
9085 val
= hsw_read_dcomp(dev_priv
);
9086 val
|= D_COMP_COMP_FORCE
;
9087 val
&= ~D_COMP_COMP_DISABLE
;
9088 hsw_write_dcomp(dev_priv
, val
);
9090 val
= I915_READ(LCPLL_CTL
);
9091 val
&= ~LCPLL_PLL_DISABLE
;
9092 I915_WRITE(LCPLL_CTL
, val
);
9094 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9095 DRM_ERROR("LCPLL not locked yet\n");
9097 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9098 val
= I915_READ(LCPLL_CTL
);
9099 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9100 I915_WRITE(LCPLL_CTL
, val
);
9102 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9103 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9104 DRM_ERROR("Switching back to LCPLL failed\n");
9107 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9111 * Package states C8 and deeper are really deep PC states that can only be
9112 * reached when all the devices on the system allow it, so even if the graphics
9113 * device allows PC8+, it doesn't mean the system will actually get to these
9114 * states. Our driver only allows PC8+ when going into runtime PM.
9116 * The requirements for PC8+ are that all the outputs are disabled, the power
9117 * well is disabled and most interrupts are disabled, and these are also
9118 * requirements for runtime PM. When these conditions are met, we manually do
9119 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9120 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9123 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9124 * the state of some registers, so when we come back from PC8+ we need to
9125 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9126 * need to take care of the registers kept by RC6. Notice that this happens even
9127 * if we don't put the device in PCI D3 state (which is what currently happens
9128 * because of the runtime PM support).
9130 * For more, read "Display Sequences for Package C8" on the hardware
9133 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9135 struct drm_device
*dev
= dev_priv
->dev
;
9138 DRM_DEBUG_KMS("Enabling package C8+\n");
9140 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9141 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9142 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9143 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9146 lpt_disable_clkout_dp(dev
);
9147 hsw_disable_lcpll(dev_priv
, true, true);
9150 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9152 struct drm_device
*dev
= dev_priv
->dev
;
9155 DRM_DEBUG_KMS("Disabling package C8+\n");
9157 hsw_restore_lcpll(dev_priv
);
9158 lpt_init_pch_refclk(dev
);
9160 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9161 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9162 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9163 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9166 intel_prepare_ddi(dev
);
9169 static void broxton_modeset_global_resources(struct drm_atomic_state
*old_state
)
9171 struct drm_device
*dev
= old_state
->dev
;
9172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9173 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
9176 /* see the comment in valleyview_modeset_global_resources */
9177 if (WARN_ON(max_pixclk
< 0))
9180 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9182 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9183 broxton_set_cdclk(dev
, req_cdclk
);
9186 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9187 struct intel_crtc_state
*crtc_state
)
9189 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9192 crtc
->lowfreq_avail
= false;
9197 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9199 struct intel_crtc_state
*pipe_config
)
9203 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9204 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9207 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9208 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9211 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9212 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9215 DRM_ERROR("Incorrect port type\n");
9219 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9221 struct intel_crtc_state
*pipe_config
)
9223 u32 temp
, dpll_ctl1
;
9225 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9226 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9228 switch (pipe_config
->ddi_pll_sel
) {
9231 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9232 * of the shared DPLL framework and thus needs to be read out
9235 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9236 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9239 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9242 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9245 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9250 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9252 struct intel_crtc_state
*pipe_config
)
9254 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9256 switch (pipe_config
->ddi_pll_sel
) {
9257 case PORT_CLK_SEL_WRPLL1
:
9258 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9260 case PORT_CLK_SEL_WRPLL2
:
9261 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9266 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9267 struct intel_crtc_state
*pipe_config
)
9269 struct drm_device
*dev
= crtc
->base
.dev
;
9270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9271 struct intel_shared_dpll
*pll
;
9275 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9277 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9279 if (IS_SKYLAKE(dev
))
9280 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9281 else if (IS_BROXTON(dev
))
9282 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9284 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9286 if (pipe_config
->shared_dpll
>= 0) {
9287 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9289 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9290 &pipe_config
->dpll_hw_state
));
9294 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9295 * DDI E. So just check whether this pipe is wired to DDI E and whether
9296 * the PCH transcoder is on.
9298 if (INTEL_INFO(dev
)->gen
< 9 &&
9299 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9300 pipe_config
->has_pch_encoder
= true;
9302 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9303 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9304 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9306 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9310 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9311 struct intel_crtc_state
*pipe_config
)
9313 struct drm_device
*dev
= crtc
->base
.dev
;
9314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9315 enum intel_display_power_domain pfit_domain
;
9318 if (!intel_display_power_is_enabled(dev_priv
,
9319 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9322 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9323 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9325 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9326 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9327 enum pipe trans_edp_pipe
;
9328 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9330 WARN(1, "unknown pipe linked to edp transcoder\n");
9331 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9332 case TRANS_DDI_EDP_INPUT_A_ON
:
9333 trans_edp_pipe
= PIPE_A
;
9335 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9336 trans_edp_pipe
= PIPE_B
;
9338 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9339 trans_edp_pipe
= PIPE_C
;
9343 if (trans_edp_pipe
== crtc
->pipe
)
9344 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9347 if (!intel_display_power_is_enabled(dev_priv
,
9348 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9351 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9352 if (!(tmp
& PIPECONF_ENABLE
))
9355 haswell_get_ddi_port_state(crtc
, pipe_config
);
9357 intel_get_pipe_timings(crtc
, pipe_config
);
9359 if (INTEL_INFO(dev
)->gen
>= 9) {
9360 skl_init_scalers(dev
, crtc
, pipe_config
);
9363 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9365 if (INTEL_INFO(dev
)->gen
>= 9) {
9366 pipe_config
->scaler_state
.scaler_id
= -1;
9367 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9370 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9371 if (INTEL_INFO(dev
)->gen
== 9)
9372 skylake_get_pfit_config(crtc
, pipe_config
);
9373 else if (INTEL_INFO(dev
)->gen
< 9)
9374 ironlake_get_pfit_config(crtc
, pipe_config
);
9376 MISSING_CASE(INTEL_INFO(dev
)->gen
);
9379 if (IS_HASWELL(dev
))
9380 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9381 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9383 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9384 pipe_config
->pixel_multiplier
=
9385 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9387 pipe_config
->pixel_multiplier
= 1;
9393 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9395 struct drm_device
*dev
= crtc
->dev
;
9396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9398 uint32_t cntl
= 0, size
= 0;
9401 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9402 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9403 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9407 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9418 cntl
|= CURSOR_ENABLE
|
9419 CURSOR_GAMMA_ENABLE
|
9420 CURSOR_FORMAT_ARGB
|
9421 CURSOR_STRIDE(stride
);
9423 size
= (height
<< 12) | width
;
9426 if (intel_crtc
->cursor_cntl
!= 0 &&
9427 (intel_crtc
->cursor_base
!= base
||
9428 intel_crtc
->cursor_size
!= size
||
9429 intel_crtc
->cursor_cntl
!= cntl
)) {
9430 /* On these chipsets we can only modify the base/size/stride
9431 * whilst the cursor is disabled.
9433 I915_WRITE(_CURACNTR
, 0);
9434 POSTING_READ(_CURACNTR
);
9435 intel_crtc
->cursor_cntl
= 0;
9438 if (intel_crtc
->cursor_base
!= base
) {
9439 I915_WRITE(_CURABASE
, base
);
9440 intel_crtc
->cursor_base
= base
;
9443 if (intel_crtc
->cursor_size
!= size
) {
9444 I915_WRITE(CURSIZE
, size
);
9445 intel_crtc
->cursor_size
= size
;
9448 if (intel_crtc
->cursor_cntl
!= cntl
) {
9449 I915_WRITE(_CURACNTR
, cntl
);
9450 POSTING_READ(_CURACNTR
);
9451 intel_crtc
->cursor_cntl
= cntl
;
9455 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9457 struct drm_device
*dev
= crtc
->dev
;
9458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9459 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9460 int pipe
= intel_crtc
->pipe
;
9465 cntl
= MCURSOR_GAMMA_ENABLE
;
9466 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9468 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9471 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9474 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9477 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9480 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9482 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9483 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9486 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9487 cntl
|= CURSOR_ROTATE_180
;
9489 if (intel_crtc
->cursor_cntl
!= cntl
) {
9490 I915_WRITE(CURCNTR(pipe
), cntl
);
9491 POSTING_READ(CURCNTR(pipe
));
9492 intel_crtc
->cursor_cntl
= cntl
;
9495 /* and commit changes on next vblank */
9496 I915_WRITE(CURBASE(pipe
), base
);
9497 POSTING_READ(CURBASE(pipe
));
9499 intel_crtc
->cursor_base
= base
;
9502 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9503 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9506 struct drm_device
*dev
= crtc
->dev
;
9507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9508 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9509 int pipe
= intel_crtc
->pipe
;
9510 int x
= crtc
->cursor_x
;
9511 int y
= crtc
->cursor_y
;
9512 u32 base
= 0, pos
= 0;
9515 base
= intel_crtc
->cursor_addr
;
9517 if (x
>= intel_crtc
->config
->pipe_src_w
)
9520 if (y
>= intel_crtc
->config
->pipe_src_h
)
9524 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
9527 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9530 pos
|= x
<< CURSOR_X_SHIFT
;
9533 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
9536 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9539 pos
|= y
<< CURSOR_Y_SHIFT
;
9541 if (base
== 0 && intel_crtc
->cursor_base
== 0)
9544 I915_WRITE(CURPOS(pipe
), pos
);
9546 /* ILK+ do this automagically */
9547 if (HAS_GMCH_DISPLAY(dev
) &&
9548 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
9549 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
9550 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
9553 if (IS_845G(dev
) || IS_I865G(dev
))
9554 i845_update_cursor(crtc
, base
);
9556 i9xx_update_cursor(crtc
, base
);
9559 static bool cursor_size_ok(struct drm_device
*dev
,
9560 uint32_t width
, uint32_t height
)
9562 if (width
== 0 || height
== 0)
9566 * 845g/865g are special in that they are only limited by
9567 * the width of their cursors, the height is arbitrary up to
9568 * the precision of the register. Everything else requires
9569 * square cursors, limited to a few power-of-two sizes.
9571 if (IS_845G(dev
) || IS_I865G(dev
)) {
9572 if ((width
& 63) != 0)
9575 if (width
> (IS_845G(dev
) ? 64 : 512))
9581 switch (width
| height
) {
9596 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
9597 u16
*blue
, uint32_t start
, uint32_t size
)
9599 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
9600 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9602 for (i
= start
; i
< end
; i
++) {
9603 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
9604 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
9605 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
9608 intel_crtc_load_lut(crtc
);
9611 /* VESA 640x480x72Hz mode to set on the pipe */
9612 static struct drm_display_mode load_detect_mode
= {
9613 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9614 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9617 struct drm_framebuffer
*
9618 __intel_framebuffer_create(struct drm_device
*dev
,
9619 struct drm_mode_fb_cmd2
*mode_cmd
,
9620 struct drm_i915_gem_object
*obj
)
9622 struct intel_framebuffer
*intel_fb
;
9625 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9627 drm_gem_object_unreference(&obj
->base
);
9628 return ERR_PTR(-ENOMEM
);
9631 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
9635 return &intel_fb
->base
;
9637 drm_gem_object_unreference(&obj
->base
);
9640 return ERR_PTR(ret
);
9643 static struct drm_framebuffer
*
9644 intel_framebuffer_create(struct drm_device
*dev
,
9645 struct drm_mode_fb_cmd2
*mode_cmd
,
9646 struct drm_i915_gem_object
*obj
)
9648 struct drm_framebuffer
*fb
;
9651 ret
= i915_mutex_lock_interruptible(dev
);
9653 return ERR_PTR(ret
);
9654 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
9655 mutex_unlock(&dev
->struct_mutex
);
9661 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9663 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9664 return ALIGN(pitch
, 64);
9668 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9670 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9671 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9674 static struct drm_framebuffer
*
9675 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9676 struct drm_display_mode
*mode
,
9679 struct drm_i915_gem_object
*obj
;
9680 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9682 obj
= i915_gem_alloc_object(dev
,
9683 intel_framebuffer_size_for_mode(mode
, bpp
));
9685 return ERR_PTR(-ENOMEM
);
9687 mode_cmd
.width
= mode
->hdisplay
;
9688 mode_cmd
.height
= mode
->vdisplay
;
9689 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9691 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9693 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9696 static struct drm_framebuffer
*
9697 mode_fits_in_fbdev(struct drm_device
*dev
,
9698 struct drm_display_mode
*mode
)
9700 #ifdef CONFIG_DRM_I915_FBDEV
9701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9702 struct drm_i915_gem_object
*obj
;
9703 struct drm_framebuffer
*fb
;
9705 if (!dev_priv
->fbdev
)
9708 if (!dev_priv
->fbdev
->fb
)
9711 obj
= dev_priv
->fbdev
->fb
->obj
;
9714 fb
= &dev_priv
->fbdev
->fb
->base
;
9715 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9716 fb
->bits_per_pixel
))
9719 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9728 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
9729 struct drm_crtc
*crtc
,
9730 struct drm_display_mode
*mode
,
9731 struct drm_framebuffer
*fb
,
9734 struct drm_plane_state
*plane_state
;
9735 int hdisplay
, vdisplay
;
9738 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
9739 if (IS_ERR(plane_state
))
9740 return PTR_ERR(plane_state
);
9743 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
9745 hdisplay
= vdisplay
= 0;
9747 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
9750 drm_atomic_set_fb_for_plane(plane_state
, fb
);
9751 plane_state
->crtc_x
= 0;
9752 plane_state
->crtc_y
= 0;
9753 plane_state
->crtc_w
= hdisplay
;
9754 plane_state
->crtc_h
= vdisplay
;
9755 plane_state
->src_x
= x
<< 16;
9756 plane_state
->src_y
= y
<< 16;
9757 plane_state
->src_w
= hdisplay
<< 16;
9758 plane_state
->src_h
= vdisplay
<< 16;
9763 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9764 struct drm_display_mode
*mode
,
9765 struct intel_load_detect_pipe
*old
,
9766 struct drm_modeset_acquire_ctx
*ctx
)
9768 struct intel_crtc
*intel_crtc
;
9769 struct intel_encoder
*intel_encoder
=
9770 intel_attached_encoder(connector
);
9771 struct drm_crtc
*possible_crtc
;
9772 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9773 struct drm_crtc
*crtc
= NULL
;
9774 struct drm_device
*dev
= encoder
->dev
;
9775 struct drm_framebuffer
*fb
;
9776 struct drm_mode_config
*config
= &dev
->mode_config
;
9777 struct drm_atomic_state
*state
= NULL
;
9778 struct drm_connector_state
*connector_state
;
9779 struct intel_crtc_state
*crtc_state
;
9782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9783 connector
->base
.id
, connector
->name
,
9784 encoder
->base
.id
, encoder
->name
);
9787 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9792 * Algorithm gets a little messy:
9794 * - if the connector already has an assigned crtc, use it (but make
9795 * sure it's on first)
9797 * - try to find the first unused crtc that can drive this connector,
9798 * and use that if we find one
9801 /* See if we already have a CRTC for this connector */
9802 if (encoder
->crtc
) {
9803 crtc
= encoder
->crtc
;
9805 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9808 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9812 old
->dpms_mode
= connector
->dpms
;
9813 old
->load_detect_temp
= false;
9815 /* Make sure the crtc and connector are running */
9816 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9817 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9822 /* Find an unused one (if possible) */
9823 for_each_crtc(dev
, possible_crtc
) {
9825 if (!(encoder
->possible_crtcs
& (1 << i
)))
9827 if (possible_crtc
->state
->enable
)
9829 /* This can occur when applying the pipe A quirk on resume. */
9830 if (to_intel_crtc(possible_crtc
)->new_enabled
)
9833 crtc
= possible_crtc
;
9838 * If we didn't find an unused CRTC, don't use any.
9841 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9845 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9848 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9851 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
9852 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
9854 intel_crtc
= to_intel_crtc(crtc
);
9855 intel_crtc
->new_enabled
= true;
9856 old
->dpms_mode
= connector
->dpms
;
9857 old
->load_detect_temp
= true;
9858 old
->release_fb
= NULL
;
9860 state
= drm_atomic_state_alloc(dev
);
9864 state
->acquire_ctx
= ctx
;
9866 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9867 if (IS_ERR(connector_state
)) {
9868 ret
= PTR_ERR(connector_state
);
9872 connector_state
->crtc
= crtc
;
9873 connector_state
->best_encoder
= &intel_encoder
->base
;
9875 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9876 if (IS_ERR(crtc_state
)) {
9877 ret
= PTR_ERR(crtc_state
);
9881 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
9884 mode
= &load_detect_mode
;
9886 /* We need a framebuffer large enough to accommodate all accesses
9887 * that the plane may generate whilst we perform load detection.
9888 * We can not rely on the fbcon either being present (we get called
9889 * during its initialisation to detect all boot displays, or it may
9890 * not even exist) or that it is large enough to satisfy the
9893 fb
= mode_fits_in_fbdev(dev
, mode
);
9895 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9896 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9897 old
->release_fb
= fb
;
9899 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9901 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9905 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
9909 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
9911 if (intel_set_mode(crtc
, state
)) {
9912 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9913 if (old
->release_fb
)
9914 old
->release_fb
->funcs
->destroy(old
->release_fb
);
9917 crtc
->primary
->crtc
= crtc
;
9919 /* let the connector get through one full cycle before testing */
9920 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
9924 intel_crtc
->new_enabled
= crtc
->state
->enable
;
9926 drm_atomic_state_free(state
);
9929 if (ret
== -EDEADLK
) {
9930 drm_modeset_backoff(ctx
);
9937 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9938 struct intel_load_detect_pipe
*old
,
9939 struct drm_modeset_acquire_ctx
*ctx
)
9941 struct drm_device
*dev
= connector
->dev
;
9942 struct intel_encoder
*intel_encoder
=
9943 intel_attached_encoder(connector
);
9944 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9945 struct drm_crtc
*crtc
= encoder
->crtc
;
9946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9947 struct drm_atomic_state
*state
;
9948 struct drm_connector_state
*connector_state
;
9949 struct intel_crtc_state
*crtc_state
;
9952 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9953 connector
->base
.id
, connector
->name
,
9954 encoder
->base
.id
, encoder
->name
);
9956 if (old
->load_detect_temp
) {
9957 state
= drm_atomic_state_alloc(dev
);
9961 state
->acquire_ctx
= ctx
;
9963 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9964 if (IS_ERR(connector_state
))
9967 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9968 if (IS_ERR(crtc_state
))
9971 to_intel_connector(connector
)->new_encoder
= NULL
;
9972 intel_encoder
->new_crtc
= NULL
;
9973 intel_crtc
->new_enabled
= false;
9975 connector_state
->best_encoder
= NULL
;
9976 connector_state
->crtc
= NULL
;
9978 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
9980 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
9985 ret
= intel_set_mode(crtc
, state
);
9989 if (old
->release_fb
) {
9990 drm_framebuffer_unregister_private(old
->release_fb
);
9991 drm_framebuffer_unreference(old
->release_fb
);
9997 /* Switch crtc and encoder back off if necessary */
9998 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
9999 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10003 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10004 drm_atomic_state_free(state
);
10007 static int i9xx_pll_refclk(struct drm_device
*dev
,
10008 const struct intel_crtc_state
*pipe_config
)
10010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10011 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10013 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10014 return dev_priv
->vbt
.lvds_ssc_freq
;
10015 else if (HAS_PCH_SPLIT(dev
))
10017 else if (!IS_GEN2(dev
))
10023 /* Returns the clock of the currently programmed mode of the given pipe. */
10024 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10025 struct intel_crtc_state
*pipe_config
)
10027 struct drm_device
*dev
= crtc
->base
.dev
;
10028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10029 int pipe
= pipe_config
->cpu_transcoder
;
10030 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10032 intel_clock_t clock
;
10033 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10035 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10036 fp
= pipe_config
->dpll_hw_state
.fp0
;
10038 fp
= pipe_config
->dpll_hw_state
.fp1
;
10040 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10041 if (IS_PINEVIEW(dev
)) {
10042 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10043 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10045 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10046 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10049 if (!IS_GEN2(dev
)) {
10050 if (IS_PINEVIEW(dev
))
10051 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10052 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10054 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10055 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10057 switch (dpll
& DPLL_MODE_MASK
) {
10058 case DPLLB_MODE_DAC_SERIAL
:
10059 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10062 case DPLLB_MODE_LVDS
:
10063 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10067 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10068 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10072 if (IS_PINEVIEW(dev
))
10073 pineview_clock(refclk
, &clock
);
10075 i9xx_clock(refclk
, &clock
);
10077 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10078 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10081 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10082 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10084 if (lvds
& LVDS_CLKB_POWER_UP
)
10089 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10092 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10093 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10095 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10101 i9xx_clock(refclk
, &clock
);
10105 * This value includes pixel_multiplier. We will use
10106 * port_clock to compute adjusted_mode.crtc_clock in the
10107 * encoder's get_config() function.
10109 pipe_config
->port_clock
= clock
.dot
;
10112 int intel_dotclock_calculate(int link_freq
,
10113 const struct intel_link_m_n
*m_n
)
10116 * The calculation for the data clock is:
10117 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10118 * But we want to avoid losing precison if possible, so:
10119 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10121 * and the link clock is simpler:
10122 * link_clock = (m * link_clock) / n
10128 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10131 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10132 struct intel_crtc_state
*pipe_config
)
10134 struct drm_device
*dev
= crtc
->base
.dev
;
10136 /* read out port_clock from the DPLL */
10137 i9xx_crtc_clock_get(crtc
, pipe_config
);
10140 * This value does not include pixel_multiplier.
10141 * We will check that port_clock and adjusted_mode.crtc_clock
10142 * agree once we know their relationship in the encoder's
10143 * get_config() function.
10145 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10146 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10147 &pipe_config
->fdi_m_n
);
10150 /** Returns the currently programmed mode of the given pipe. */
10151 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10152 struct drm_crtc
*crtc
)
10154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10156 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10157 struct drm_display_mode
*mode
;
10158 struct intel_crtc_state pipe_config
;
10159 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10160 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10161 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10162 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10163 enum pipe pipe
= intel_crtc
->pipe
;
10165 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10170 * Construct a pipe_config sufficient for getting the clock info
10171 * back out of crtc_clock_get.
10173 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10174 * to use a real value here instead.
10176 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10177 pipe_config
.pixel_multiplier
= 1;
10178 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10179 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10180 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10181 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10183 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10184 mode
->hdisplay
= (htot
& 0xffff) + 1;
10185 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10186 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10187 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10188 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10189 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10190 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10191 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10193 drm_mode_set_name(mode
);
10198 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10200 struct drm_device
*dev
= crtc
->dev
;
10201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10204 if (!HAS_GMCH_DISPLAY(dev
))
10207 if (!dev_priv
->lvds_downclock_avail
)
10211 * Since this is called by a timer, we should never get here in
10214 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10215 int pipe
= intel_crtc
->pipe
;
10216 int dpll_reg
= DPLL(pipe
);
10219 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10221 assert_panel_unlocked(dev_priv
, pipe
);
10223 dpll
= I915_READ(dpll_reg
);
10224 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10225 I915_WRITE(dpll_reg
, dpll
);
10226 intel_wait_for_vblank(dev
, pipe
);
10227 dpll
= I915_READ(dpll_reg
);
10228 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10229 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10234 void intel_mark_busy(struct drm_device
*dev
)
10236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10238 if (dev_priv
->mm
.busy
)
10241 intel_runtime_pm_get(dev_priv
);
10242 i915_update_gfx_val(dev_priv
);
10243 if (INTEL_INFO(dev
)->gen
>= 6)
10244 gen6_rps_busy(dev_priv
);
10245 dev_priv
->mm
.busy
= true;
10248 void intel_mark_idle(struct drm_device
*dev
)
10250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10251 struct drm_crtc
*crtc
;
10253 if (!dev_priv
->mm
.busy
)
10256 dev_priv
->mm
.busy
= false;
10258 for_each_crtc(dev
, crtc
) {
10259 if (!crtc
->primary
->fb
)
10262 intel_decrease_pllclock(crtc
);
10265 if (INTEL_INFO(dev
)->gen
>= 6)
10266 gen6_rps_idle(dev
->dev_private
);
10268 intel_runtime_pm_put(dev_priv
);
10271 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10273 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10274 struct drm_device
*dev
= crtc
->dev
;
10275 struct intel_unpin_work
*work
;
10277 spin_lock_irq(&dev
->event_lock
);
10278 work
= intel_crtc
->unpin_work
;
10279 intel_crtc
->unpin_work
= NULL
;
10280 spin_unlock_irq(&dev
->event_lock
);
10283 cancel_work_sync(&work
->work
);
10287 drm_crtc_cleanup(crtc
);
10292 static void intel_unpin_work_fn(struct work_struct
*__work
)
10294 struct intel_unpin_work
*work
=
10295 container_of(__work
, struct intel_unpin_work
, work
);
10296 struct drm_device
*dev
= work
->crtc
->dev
;
10297 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10299 mutex_lock(&dev
->struct_mutex
);
10300 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10301 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10303 intel_fbc_update(dev
);
10305 if (work
->flip_queued_req
)
10306 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10307 mutex_unlock(&dev
->struct_mutex
);
10309 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10310 drm_framebuffer_unreference(work
->old_fb
);
10312 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10313 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10318 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10319 struct drm_crtc
*crtc
)
10321 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10322 struct intel_unpin_work
*work
;
10323 unsigned long flags
;
10325 /* Ignore early vblank irqs */
10326 if (intel_crtc
== NULL
)
10330 * This is called both by irq handlers and the reset code (to complete
10331 * lost pageflips) so needs the full irqsave spinlocks.
10333 spin_lock_irqsave(&dev
->event_lock
, flags
);
10334 work
= intel_crtc
->unpin_work
;
10336 /* Ensure we don't miss a work->pending update ... */
10339 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10340 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10344 page_flip_completed(intel_crtc
);
10346 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10349 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10352 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10354 do_intel_finish_page_flip(dev
, crtc
);
10357 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10360 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10362 do_intel_finish_page_flip(dev
, crtc
);
10365 /* Is 'a' after or equal to 'b'? */
10366 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10368 return !((a
- b
) & 0x80000000);
10371 static bool page_flip_finished(struct intel_crtc
*crtc
)
10373 struct drm_device
*dev
= crtc
->base
.dev
;
10374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10376 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10377 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10381 * The relevant registers doen't exist on pre-ctg.
10382 * As the flip done interrupt doesn't trigger for mmio
10383 * flips on gmch platforms, a flip count check isn't
10384 * really needed there. But since ctg has the registers,
10385 * include it in the check anyway.
10387 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10391 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10392 * used the same base address. In that case the mmio flip might
10393 * have completed, but the CS hasn't even executed the flip yet.
10395 * A flip count check isn't enough as the CS might have updated
10396 * the base address just after start of vblank, but before we
10397 * managed to process the interrupt. This means we'd complete the
10398 * CS flip too soon.
10400 * Combining both checks should get us a good enough result. It may
10401 * still happen that the CS flip has been executed, but has not
10402 * yet actually completed. But in case the base address is the same
10403 * anyway, we don't really care.
10405 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10406 crtc
->unpin_work
->gtt_offset
&&
10407 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10408 crtc
->unpin_work
->flip_count
);
10411 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10414 struct intel_crtc
*intel_crtc
=
10415 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10416 unsigned long flags
;
10420 * This is called both by irq handlers and the reset code (to complete
10421 * lost pageflips) so needs the full irqsave spinlocks.
10423 * NB: An MMIO update of the plane base pointer will also
10424 * generate a page-flip completion irq, i.e. every modeset
10425 * is also accompanied by a spurious intel_prepare_page_flip().
10427 spin_lock_irqsave(&dev
->event_lock
, flags
);
10428 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10429 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10430 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10433 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10435 /* Ensure that the work item is consistent when activating it ... */
10437 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10438 /* and that it is marked active as soon as the irq could fire. */
10442 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10443 struct drm_crtc
*crtc
,
10444 struct drm_framebuffer
*fb
,
10445 struct drm_i915_gem_object
*obj
,
10446 struct intel_engine_cs
*ring
,
10449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10453 ret
= intel_ring_begin(ring
, 6);
10457 /* Can't queue multiple flips, so wait for the previous
10458 * one to finish before executing the next.
10460 if (intel_crtc
->plane
)
10461 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10463 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10464 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10465 intel_ring_emit(ring
, MI_NOOP
);
10466 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10467 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10468 intel_ring_emit(ring
, fb
->pitches
[0]);
10469 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10470 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10472 intel_mark_page_flip_active(intel_crtc
);
10473 __intel_ring_advance(ring
);
10477 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10478 struct drm_crtc
*crtc
,
10479 struct drm_framebuffer
*fb
,
10480 struct drm_i915_gem_object
*obj
,
10481 struct intel_engine_cs
*ring
,
10484 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10488 ret
= intel_ring_begin(ring
, 6);
10492 if (intel_crtc
->plane
)
10493 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10495 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10496 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10497 intel_ring_emit(ring
, MI_NOOP
);
10498 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10499 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10500 intel_ring_emit(ring
, fb
->pitches
[0]);
10501 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10502 intel_ring_emit(ring
, MI_NOOP
);
10504 intel_mark_page_flip_active(intel_crtc
);
10505 __intel_ring_advance(ring
);
10509 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10510 struct drm_crtc
*crtc
,
10511 struct drm_framebuffer
*fb
,
10512 struct drm_i915_gem_object
*obj
,
10513 struct intel_engine_cs
*ring
,
10516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10517 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10518 uint32_t pf
, pipesrc
;
10521 ret
= intel_ring_begin(ring
, 4);
10525 /* i965+ uses the linear or tiled offsets from the
10526 * Display Registers (which do not change across a page-flip)
10527 * so we need only reprogram the base address.
10529 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10530 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10531 intel_ring_emit(ring
, fb
->pitches
[0]);
10532 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10535 /* XXX Enabling the panel-fitter across page-flip is so far
10536 * untested on non-native modes, so ignore it for now.
10537 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10540 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10541 intel_ring_emit(ring
, pf
| pipesrc
);
10543 intel_mark_page_flip_active(intel_crtc
);
10544 __intel_ring_advance(ring
);
10548 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10549 struct drm_crtc
*crtc
,
10550 struct drm_framebuffer
*fb
,
10551 struct drm_i915_gem_object
*obj
,
10552 struct intel_engine_cs
*ring
,
10555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10557 uint32_t pf
, pipesrc
;
10560 ret
= intel_ring_begin(ring
, 4);
10564 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10565 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10566 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10567 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10569 /* Contrary to the suggestions in the documentation,
10570 * "Enable Panel Fitter" does not seem to be required when page
10571 * flipping with a non-native mode, and worse causes a normal
10573 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10576 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10577 intel_ring_emit(ring
, pf
| pipesrc
);
10579 intel_mark_page_flip_active(intel_crtc
);
10580 __intel_ring_advance(ring
);
10584 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10585 struct drm_crtc
*crtc
,
10586 struct drm_framebuffer
*fb
,
10587 struct drm_i915_gem_object
*obj
,
10588 struct intel_engine_cs
*ring
,
10591 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10592 uint32_t plane_bit
= 0;
10595 switch (intel_crtc
->plane
) {
10597 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
10600 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
10603 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
10606 WARN_ONCE(1, "unknown plane in flip command\n");
10611 if (ring
->id
== RCS
) {
10614 * On Gen 8, SRM is now taking an extra dword to accommodate
10615 * 48bits addresses, and we need a NOOP for the batch size to
10623 * BSpec MI_DISPLAY_FLIP for IVB:
10624 * "The full packet must be contained within the same cache line."
10626 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10627 * cacheline, if we ever start emitting more commands before
10628 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10629 * then do the cacheline alignment, and finally emit the
10632 ret
= intel_ring_cacheline_align(ring
);
10636 ret
= intel_ring_begin(ring
, len
);
10640 /* Unmask the flip-done completion message. Note that the bspec says that
10641 * we should do this for both the BCS and RCS, and that we must not unmask
10642 * more than one flip event at any time (or ensure that one flip message
10643 * can be sent by waiting for flip-done prior to queueing new flips).
10644 * Experimentation says that BCS works despite DERRMR masking all
10645 * flip-done completion events and that unmasking all planes at once
10646 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10647 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10649 if (ring
->id
== RCS
) {
10650 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
10651 intel_ring_emit(ring
, DERRMR
);
10652 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
10653 DERRMR_PIPEB_PRI_FLIP_DONE
|
10654 DERRMR_PIPEC_PRI_FLIP_DONE
));
10656 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
10657 MI_SRM_LRM_GLOBAL_GTT
);
10659 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
10660 MI_SRM_LRM_GLOBAL_GTT
);
10661 intel_ring_emit(ring
, DERRMR
);
10662 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
10663 if (IS_GEN8(dev
)) {
10664 intel_ring_emit(ring
, 0);
10665 intel_ring_emit(ring
, MI_NOOP
);
10669 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
10670 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
10671 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10672 intel_ring_emit(ring
, (MI_NOOP
));
10674 intel_mark_page_flip_active(intel_crtc
);
10675 __intel_ring_advance(ring
);
10679 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
10680 struct drm_i915_gem_object
*obj
)
10683 * This is not being used for older platforms, because
10684 * non-availability of flip done interrupt forces us to use
10685 * CS flips. Older platforms derive flip done using some clever
10686 * tricks involving the flip_pending status bits and vblank irqs.
10687 * So using MMIO flips there would disrupt this mechanism.
10693 if (INTEL_INFO(ring
->dev
)->gen
< 5)
10696 if (i915
.use_mmio_flip
< 0)
10698 else if (i915
.use_mmio_flip
> 0)
10700 else if (i915
.enable_execlists
)
10703 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
10706 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10708 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10710 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
10711 const enum pipe pipe
= intel_crtc
->pipe
;
10714 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10715 ctl
&= ~PLANE_CTL_TILED_MASK
;
10716 switch (fb
->modifier
[0]) {
10717 case DRM_FORMAT_MOD_NONE
:
10719 case I915_FORMAT_MOD_X_TILED
:
10720 ctl
|= PLANE_CTL_TILED_X
;
10722 case I915_FORMAT_MOD_Y_TILED
:
10723 ctl
|= PLANE_CTL_TILED_Y
;
10725 case I915_FORMAT_MOD_Yf_TILED
:
10726 ctl
|= PLANE_CTL_TILED_YF
;
10729 MISSING_CASE(fb
->modifier
[0]);
10733 * The stride is either expressed as a multiple of 64 bytes chunks for
10734 * linear buffers or in number of tiles for tiled buffers.
10736 stride
= fb
->pitches
[0] /
10737 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
10741 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10742 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10744 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10745 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10747 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10748 POSTING_READ(PLANE_SURF(pipe
, 0));
10751 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10753 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10755 struct intel_framebuffer
*intel_fb
=
10756 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10757 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10761 reg
= DSPCNTR(intel_crtc
->plane
);
10762 dspcntr
= I915_READ(reg
);
10764 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10765 dspcntr
|= DISPPLANE_TILED
;
10767 dspcntr
&= ~DISPPLANE_TILED
;
10769 I915_WRITE(reg
, dspcntr
);
10771 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10772 intel_crtc
->unpin_work
->gtt_offset
);
10773 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10778 * XXX: This is the temporary way to update the plane registers until we get
10779 * around to using the usual plane update functions for MMIO flips
10781 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10783 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10784 bool atomic_update
;
10785 u32 start_vbl_count
;
10787 intel_mark_page_flip_active(intel_crtc
);
10789 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10791 if (INTEL_INFO(dev
)->gen
>= 9)
10792 skl_do_mmio_flip(intel_crtc
);
10794 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10795 ilk_do_mmio_flip(intel_crtc
);
10798 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10801 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10803 struct intel_mmio_flip
*mmio_flip
=
10804 container_of(work
, struct intel_mmio_flip
, work
);
10807 WARN_ON(__i915_wait_request(mmio_flip
->rq
,
10808 mmio_flip
->crtc
->reset_counter
,
10809 false, NULL
, NULL
));
10811 intel_do_mmio_flip(mmio_flip
->crtc
);
10813 i915_gem_request_unreference__unlocked(mmio_flip
->rq
);
10817 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10818 struct drm_crtc
*crtc
,
10819 struct drm_framebuffer
*fb
,
10820 struct drm_i915_gem_object
*obj
,
10821 struct intel_engine_cs
*ring
,
10824 struct intel_mmio_flip
*mmio_flip
;
10826 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
10827 if (mmio_flip
== NULL
)
10830 mmio_flip
->rq
= i915_gem_request_reference(obj
->last_write_req
);
10831 mmio_flip
->crtc
= to_intel_crtc(crtc
);
10833 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
10834 schedule_work(&mmio_flip
->work
);
10839 static int intel_default_queue_flip(struct drm_device
*dev
,
10840 struct drm_crtc
*crtc
,
10841 struct drm_framebuffer
*fb
,
10842 struct drm_i915_gem_object
*obj
,
10843 struct intel_engine_cs
*ring
,
10849 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
10850 struct drm_crtc
*crtc
)
10852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10854 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
10857 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
10860 if (!work
->enable_stall_check
)
10863 if (work
->flip_ready_vblank
== 0) {
10864 if (work
->flip_queued_req
&&
10865 !i915_gem_request_completed(work
->flip_queued_req
, true))
10868 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
10871 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
10874 /* Potential stall - if we see that the flip has happened,
10875 * assume a missed interrupt. */
10876 if (INTEL_INFO(dev
)->gen
>= 4)
10877 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
10879 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
10881 /* There is a potential issue here with a false positive after a flip
10882 * to the same address. We could address this by checking for a
10883 * non-incrementing frame counter.
10885 return addr
== work
->gtt_offset
;
10888 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
10890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10891 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10892 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10893 struct intel_unpin_work
*work
;
10895 WARN_ON(!in_interrupt());
10900 spin_lock(&dev
->event_lock
);
10901 work
= intel_crtc
->unpin_work
;
10902 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
10903 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10904 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
10905 page_flip_completed(intel_crtc
);
10908 if (work
!= NULL
&&
10909 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
10910 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
10911 spin_unlock(&dev
->event_lock
);
10914 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
10915 struct drm_framebuffer
*fb
,
10916 struct drm_pending_vblank_event
*event
,
10917 uint32_t page_flip_flags
)
10919 struct drm_device
*dev
= crtc
->dev
;
10920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10921 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10922 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10923 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10924 struct drm_plane
*primary
= crtc
->primary
;
10925 enum pipe pipe
= intel_crtc
->pipe
;
10926 struct intel_unpin_work
*work
;
10927 struct intel_engine_cs
*ring
;
10932 * drm_mode_page_flip_ioctl() should already catch this, but double
10933 * check to be safe. In the future we may enable pageflipping from
10934 * a disabled primary plane.
10936 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
10939 /* Can't change pixel format via MI display flips. */
10940 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
10944 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10945 * Note that pitch changes could also affect these register.
10947 if (INTEL_INFO(dev
)->gen
> 3 &&
10948 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
10949 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
10952 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10955 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10959 work
->event
= event
;
10961 work
->old_fb
= old_fb
;
10962 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10964 ret
= drm_crtc_vblank_get(crtc
);
10968 /* We borrow the event spin lock for protecting unpin_work */
10969 spin_lock_irq(&dev
->event_lock
);
10970 if (intel_crtc
->unpin_work
) {
10971 /* Before declaring the flip queue wedged, check if
10972 * the hardware completed the operation behind our backs.
10974 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10975 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10976 page_flip_completed(intel_crtc
);
10978 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10979 spin_unlock_irq(&dev
->event_lock
);
10981 drm_crtc_vblank_put(crtc
);
10986 intel_crtc
->unpin_work
= work
;
10987 spin_unlock_irq(&dev
->event_lock
);
10989 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10990 flush_workqueue(dev_priv
->wq
);
10992 /* Reference the objects for the scheduled work. */
10993 drm_framebuffer_reference(work
->old_fb
);
10994 drm_gem_object_reference(&obj
->base
);
10996 crtc
->primary
->fb
= fb
;
10997 update_state_fb(crtc
->primary
);
10999 work
->pending_flip_obj
= obj
;
11001 ret
= i915_mutex_lock_interruptible(dev
);
11005 atomic_inc(&intel_crtc
->unpin_work_count
);
11006 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11008 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11009 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
11011 if (IS_VALLEYVIEW(dev
)) {
11012 ring
= &dev_priv
->ring
[BCS
];
11013 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11014 /* vlv: DISPLAY_FLIP fails to change tiling */
11016 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11017 ring
= &dev_priv
->ring
[BCS
];
11018 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11019 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
11020 if (ring
== NULL
|| ring
->id
!= RCS
)
11021 ring
= &dev_priv
->ring
[BCS
];
11023 ring
= &dev_priv
->ring
[RCS
];
11026 mmio_flip
= use_mmio_flip(ring
, obj
);
11028 /* When using CS flips, we want to emit semaphores between rings.
11029 * However, when using mmio flips we will create a task to do the
11030 * synchronisation, so all we want here is to pin the framebuffer
11031 * into the display plane and skip any waits.
11033 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11034 crtc
->primary
->state
,
11035 mmio_flip
? i915_gem_request_get_ring(obj
->last_read_req
) : ring
);
11037 goto cleanup_pending
;
11039 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
11040 + intel_crtc
->dspaddr_offset
;
11043 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11046 goto cleanup_unpin
;
11048 i915_gem_request_assign(&work
->flip_queued_req
,
11049 obj
->last_write_req
);
11051 if (obj
->last_write_req
) {
11052 ret
= i915_gem_check_olr(obj
->last_write_req
);
11054 goto cleanup_unpin
;
11057 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
11060 goto cleanup_unpin
;
11062 i915_gem_request_assign(&work
->flip_queued_req
,
11063 intel_ring_get_request(ring
));
11066 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11067 work
->enable_stall_check
= true;
11069 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11070 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11072 intel_fbc_disable(dev
);
11073 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11074 mutex_unlock(&dev
->struct_mutex
);
11076 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11081 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11083 atomic_dec(&intel_crtc
->unpin_work_count
);
11084 mutex_unlock(&dev
->struct_mutex
);
11086 crtc
->primary
->fb
= old_fb
;
11087 update_state_fb(crtc
->primary
);
11089 drm_gem_object_unreference_unlocked(&obj
->base
);
11090 drm_framebuffer_unreference(work
->old_fb
);
11092 spin_lock_irq(&dev
->event_lock
);
11093 intel_crtc
->unpin_work
= NULL
;
11094 spin_unlock_irq(&dev
->event_lock
);
11096 drm_crtc_vblank_put(crtc
);
11102 ret
= intel_plane_restore(primary
);
11103 if (ret
== 0 && event
) {
11104 spin_lock_irq(&dev
->event_lock
);
11105 drm_send_vblank_event(dev
, pipe
, event
);
11106 spin_unlock_irq(&dev
->event_lock
);
11112 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11113 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11114 .load_lut
= intel_crtc_load_lut
,
11115 .atomic_begin
= intel_begin_crtc_commit
,
11116 .atomic_flush
= intel_finish_crtc_commit
,
11120 * intel_modeset_update_staged_output_state
11122 * Updates the staged output configuration state, e.g. after we've read out the
11123 * current hw state.
11125 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11127 struct intel_crtc
*crtc
;
11128 struct intel_encoder
*encoder
;
11129 struct intel_connector
*connector
;
11131 for_each_intel_connector(dev
, connector
) {
11132 connector
->new_encoder
=
11133 to_intel_encoder(connector
->base
.encoder
);
11136 for_each_intel_encoder(dev
, encoder
) {
11137 encoder
->new_crtc
=
11138 to_intel_crtc(encoder
->base
.crtc
);
11141 for_each_intel_crtc(dev
, crtc
) {
11142 crtc
->new_enabled
= crtc
->base
.state
->enable
;
11146 /* Transitional helper to copy current connector/encoder state to
11147 * connector->state. This is needed so that code that is partially
11148 * converted to atomic does the right thing.
11150 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11152 struct intel_connector
*connector
;
11154 for_each_intel_connector(dev
, connector
) {
11155 if (connector
->base
.encoder
) {
11156 connector
->base
.state
->best_encoder
=
11157 connector
->base
.encoder
;
11158 connector
->base
.state
->crtc
=
11159 connector
->base
.encoder
->crtc
;
11161 connector
->base
.state
->best_encoder
= NULL
;
11162 connector
->base
.state
->crtc
= NULL
;
11167 /* Fixup legacy state after an atomic state swap.
11169 static void intel_modeset_fixup_state(struct drm_atomic_state
*state
)
11171 struct intel_crtc
*crtc
;
11172 struct intel_encoder
*encoder
;
11173 struct intel_connector
*connector
;
11175 for_each_intel_connector(state
->dev
, connector
) {
11176 connector
->base
.encoder
= connector
->base
.state
->best_encoder
;
11177 if (connector
->base
.encoder
)
11178 connector
->base
.encoder
->crtc
=
11179 connector
->base
.state
->crtc
;
11182 /* Update crtc of disabled encoders */
11183 for_each_intel_encoder(state
->dev
, encoder
) {
11184 int num_connectors
= 0;
11186 for_each_intel_connector(state
->dev
, connector
)
11187 if (connector
->base
.encoder
== &encoder
->base
)
11190 if (num_connectors
== 0)
11191 encoder
->base
.crtc
= NULL
;
11194 for_each_intel_crtc(state
->dev
, crtc
) {
11195 crtc
->base
.enabled
= crtc
->base
.state
->enable
;
11196 crtc
->config
= to_intel_crtc_state(crtc
->base
.state
);
11199 /* Copy the new configuration to the staged state, to keep the few
11200 * pieces of code that haven't been converted yet happy */
11201 intel_modeset_update_staged_output_state(state
->dev
);
11205 connected_sink_compute_bpp(struct intel_connector
*connector
,
11206 struct intel_crtc_state
*pipe_config
)
11208 int bpp
= pipe_config
->pipe_bpp
;
11210 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11211 connector
->base
.base
.id
,
11212 connector
->base
.name
);
11214 /* Don't use an invalid EDID bpc value */
11215 if (connector
->base
.display_info
.bpc
&&
11216 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11217 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11218 bpp
, connector
->base
.display_info
.bpc
*3);
11219 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11222 /* Clamp bpp to 8 on screens without EDID 1.4 */
11223 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11224 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11226 pipe_config
->pipe_bpp
= 24;
11231 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11232 struct intel_crtc_state
*pipe_config
)
11234 struct drm_device
*dev
= crtc
->base
.dev
;
11235 struct drm_atomic_state
*state
;
11236 struct drm_connector
*connector
;
11237 struct drm_connector_state
*connector_state
;
11240 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11242 else if (INTEL_INFO(dev
)->gen
>= 5)
11248 pipe_config
->pipe_bpp
= bpp
;
11250 state
= pipe_config
->base
.state
;
11252 /* Clamp display bpp to EDID value */
11253 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11254 if (connector_state
->crtc
!= &crtc
->base
)
11257 connected_sink_compute_bpp(to_intel_connector(connector
),
11264 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11266 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11267 "type: 0x%x flags: 0x%x\n",
11269 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11270 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11271 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11272 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11275 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11276 struct intel_crtc_state
*pipe_config
,
11277 const char *context
)
11279 struct drm_device
*dev
= crtc
->base
.dev
;
11280 struct drm_plane
*plane
;
11281 struct intel_plane
*intel_plane
;
11282 struct intel_plane_state
*state
;
11283 struct drm_framebuffer
*fb
;
11285 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11286 context
, pipe_config
, pipe_name(crtc
->pipe
));
11288 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11289 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11290 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11291 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11292 pipe_config
->has_pch_encoder
,
11293 pipe_config
->fdi_lanes
,
11294 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11295 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11296 pipe_config
->fdi_m_n
.tu
);
11297 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11298 pipe_config
->has_dp_encoder
,
11299 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11300 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11301 pipe_config
->dp_m_n
.tu
);
11303 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11304 pipe_config
->has_dp_encoder
,
11305 pipe_config
->dp_m2_n2
.gmch_m
,
11306 pipe_config
->dp_m2_n2
.gmch_n
,
11307 pipe_config
->dp_m2_n2
.link_m
,
11308 pipe_config
->dp_m2_n2
.link_n
,
11309 pipe_config
->dp_m2_n2
.tu
);
11311 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11312 pipe_config
->has_audio
,
11313 pipe_config
->has_infoframe
);
11315 DRM_DEBUG_KMS("requested mode:\n");
11316 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11317 DRM_DEBUG_KMS("adjusted mode:\n");
11318 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11319 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11320 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11321 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11322 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11323 DRM_DEBUG_KMS("num_scalers: %d\n", crtc
->num_scalers
);
11324 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config
->scaler_state
.scaler_users
);
11325 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config
->scaler_state
.scaler_id
);
11326 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11327 pipe_config
->gmch_pfit
.control
,
11328 pipe_config
->gmch_pfit
.pgm_ratios
,
11329 pipe_config
->gmch_pfit
.lvds_border_bits
);
11330 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11331 pipe_config
->pch_pfit
.pos
,
11332 pipe_config
->pch_pfit
.size
,
11333 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11334 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11335 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11337 DRM_DEBUG_KMS("planes on this crtc\n");
11338 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11339 intel_plane
= to_intel_plane(plane
);
11340 if (intel_plane
->pipe
!= crtc
->pipe
)
11343 state
= to_intel_plane_state(plane
->state
);
11344 fb
= state
->base
.fb
;
11346 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11347 "disabled, scaler_id = %d\n",
11348 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11349 plane
->base
.id
, intel_plane
->pipe
,
11350 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
11351 drm_plane_index(plane
), state
->scaler_id
);
11355 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11356 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11357 plane
->base
.id
, intel_plane
->pipe
,
11358 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
11359 drm_plane_index(plane
));
11360 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11361 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
11362 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11364 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
11365 drm_rect_width(&state
->src
) >> 16,
11366 drm_rect_height(&state
->src
) >> 16,
11367 state
->dst
.x1
, state
->dst
.y1
,
11368 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
11372 static bool encoders_cloneable(const struct intel_encoder
*a
,
11373 const struct intel_encoder
*b
)
11375 /* masks could be asymmetric, so check both ways */
11376 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11377 b
->cloneable
& (1 << a
->type
));
11380 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11381 struct intel_crtc
*crtc
,
11382 struct intel_encoder
*encoder
)
11384 struct intel_encoder
*source_encoder
;
11385 struct drm_connector
*connector
;
11386 struct drm_connector_state
*connector_state
;
11389 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11390 if (connector_state
->crtc
!= &crtc
->base
)
11394 to_intel_encoder(connector_state
->best_encoder
);
11395 if (!encoders_cloneable(encoder
, source_encoder
))
11402 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11403 struct intel_crtc
*crtc
)
11405 struct intel_encoder
*encoder
;
11406 struct drm_connector
*connector
;
11407 struct drm_connector_state
*connector_state
;
11410 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11411 if (connector_state
->crtc
!= &crtc
->base
)
11414 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11415 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11422 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11424 struct drm_device
*dev
= state
->dev
;
11425 struct intel_encoder
*encoder
;
11426 struct drm_connector
*connector
;
11427 struct drm_connector_state
*connector_state
;
11428 unsigned int used_ports
= 0;
11432 * Walk the connector list instead of the encoder
11433 * list to detect the problem on ddi platforms
11434 * where there's just one encoder per digital port.
11436 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11437 if (!connector_state
->best_encoder
)
11440 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11442 WARN_ON(!connector_state
->crtc
);
11444 switch (encoder
->type
) {
11445 unsigned int port_mask
;
11446 case INTEL_OUTPUT_UNKNOWN
:
11447 if (WARN_ON(!HAS_DDI(dev
)))
11449 case INTEL_OUTPUT_DISPLAYPORT
:
11450 case INTEL_OUTPUT_HDMI
:
11451 case INTEL_OUTPUT_EDP
:
11452 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
11454 /* the same port mustn't appear more than once */
11455 if (used_ports
& port_mask
)
11458 used_ports
|= port_mask
;
11468 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11470 struct drm_crtc_state tmp_state
;
11471 struct intel_crtc_scaler_state scaler_state
;
11472 struct intel_dpll_hw_state dpll_hw_state
;
11473 enum intel_dpll_id shared_dpll
;
11475 /* Clear only the intel specific part of the crtc state excluding scalers */
11476 tmp_state
= crtc_state
->base
;
11477 scaler_state
= crtc_state
->scaler_state
;
11478 shared_dpll
= crtc_state
->shared_dpll
;
11479 dpll_hw_state
= crtc_state
->dpll_hw_state
;
11481 memset(crtc_state
, 0, sizeof *crtc_state
);
11483 crtc_state
->base
= tmp_state
;
11484 crtc_state
->scaler_state
= scaler_state
;
11485 crtc_state
->shared_dpll
= shared_dpll
;
11486 crtc_state
->dpll_hw_state
= dpll_hw_state
;
11490 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11491 struct drm_atomic_state
*state
,
11492 struct intel_crtc_state
*pipe_config
)
11494 struct intel_encoder
*encoder
;
11495 struct drm_connector
*connector
;
11496 struct drm_connector_state
*connector_state
;
11497 int base_bpp
, ret
= -EINVAL
;
11501 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
11502 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11506 if (!check_digital_port_conflicts(state
)) {
11507 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11511 clear_intel_crtc_state(pipe_config
);
11513 pipe_config
->cpu_transcoder
=
11514 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11517 * Sanitize sync polarity flags based on requested ones. If neither
11518 * positive or negative polarity is requested, treat this as meaning
11519 * negative polarity.
11521 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11522 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11523 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11525 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11526 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11527 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11529 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11530 * plane pixel format and any sink constraints into account. Returns the
11531 * source plane bpp so that dithering can be selected on mismatches
11532 * after encoders and crtc also have had their say. */
11533 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11539 * Determine the real pipe dimensions. Note that stereo modes can
11540 * increase the actual pipe size due to the frame doubling and
11541 * insertion of additional space for blanks between the frame. This
11542 * is stored in the crtc timings. We use the requested mode to do this
11543 * computation to clearly distinguish it from the adjusted mode, which
11544 * can be changed by the connectors in the below retry loop.
11546 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
11547 &pipe_config
->pipe_src_w
,
11548 &pipe_config
->pipe_src_h
);
11551 /* Ensure the port clock defaults are reset when retrying. */
11552 pipe_config
->port_clock
= 0;
11553 pipe_config
->pixel_multiplier
= 1;
11555 /* Fill in default crtc timings, allow encoders to overwrite them. */
11556 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11557 CRTC_STEREO_DOUBLE
);
11559 /* Pass our mode to the connectors and the CRTC to give them a chance to
11560 * adjust it according to limitations or connector properties, and also
11561 * a chance to reject the mode entirely.
11563 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11564 if (connector_state
->crtc
!= crtc
)
11567 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11569 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
11570 DRM_DEBUG_KMS("Encoder config failure\n");
11575 /* Set default port clock if not overwritten by the encoder. Needs to be
11576 * done afterwards in case the encoder adjusts the mode. */
11577 if (!pipe_config
->port_clock
)
11578 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11579 * pipe_config
->pixel_multiplier
;
11581 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11583 DRM_DEBUG_KMS("CRTC fixup failed\n");
11587 if (ret
== RETRY
) {
11588 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
11593 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11595 goto encoder_retry
;
11598 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
11599 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11600 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11607 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
11609 struct drm_encoder
*encoder
;
11610 struct drm_device
*dev
= crtc
->dev
;
11612 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
11613 if (encoder
->crtc
== crtc
)
11620 needs_modeset(struct drm_crtc_state
*state
)
11622 return state
->mode_changed
|| state
->active_changed
;
11626 intel_modeset_update_state(struct drm_atomic_state
*state
)
11628 struct drm_device
*dev
= state
->dev
;
11629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11630 struct intel_encoder
*intel_encoder
;
11631 struct drm_crtc
*crtc
;
11632 struct drm_crtc_state
*crtc_state
;
11633 struct drm_connector
*connector
;
11636 intel_shared_dpll_commit(dev_priv
);
11638 for_each_intel_encoder(dev
, intel_encoder
) {
11639 if (!intel_encoder
->base
.crtc
)
11642 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11643 if (crtc
== intel_encoder
->base
.crtc
)
11646 if (crtc
!= intel_encoder
->base
.crtc
)
11649 if (crtc_state
->enable
&& needs_modeset(crtc_state
))
11650 intel_encoder
->connectors_active
= false;
11653 drm_atomic_helper_swap_state(state
->dev
, state
);
11654 intel_modeset_fixup_state(state
);
11656 /* Double check state. */
11657 for_each_crtc(dev
, crtc
) {
11658 WARN_ON(crtc
->state
->enable
!= intel_crtc_in_use(crtc
));
11661 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11662 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
11665 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11666 if (crtc
== connector
->encoder
->crtc
)
11669 if (crtc
!= connector
->encoder
->crtc
)
11672 if (crtc
->state
->enable
&& needs_modeset(crtc
->state
)) {
11673 struct drm_property
*dpms_property
=
11674 dev
->mode_config
.dpms_property
;
11676 connector
->dpms
= DRM_MODE_DPMS_ON
;
11677 drm_object_property_set_value(&connector
->base
,
11681 intel_encoder
= to_intel_encoder(connector
->encoder
);
11682 intel_encoder
->connectors_active
= true;
11688 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11692 if (clock1
== clock2
)
11695 if (!clock1
|| !clock2
)
11698 diff
= abs(clock1
- clock2
);
11700 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11706 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11707 list_for_each_entry((intel_crtc), \
11708 &(dev)->mode_config.crtc_list, \
11710 if (mask & (1 <<(intel_crtc)->pipe))
11713 intel_pipe_config_compare(struct drm_device
*dev
,
11714 struct intel_crtc_state
*current_config
,
11715 struct intel_crtc_state
*pipe_config
)
11717 #define PIPE_CONF_CHECK_X(name) \
11718 if (current_config->name != pipe_config->name) { \
11719 DRM_ERROR("mismatch in " #name " " \
11720 "(expected 0x%08x, found 0x%08x)\n", \
11721 current_config->name, \
11722 pipe_config->name); \
11726 #define PIPE_CONF_CHECK_I(name) \
11727 if (current_config->name != pipe_config->name) { \
11728 DRM_ERROR("mismatch in " #name " " \
11729 "(expected %i, found %i)\n", \
11730 current_config->name, \
11731 pipe_config->name); \
11735 /* This is required for BDW+ where there is only one set of registers for
11736 * switching between high and low RR.
11737 * This macro can be used whenever a comparison has to be made between one
11738 * hw state and multiple sw state variables.
11740 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11741 if ((current_config->name != pipe_config->name) && \
11742 (current_config->alt_name != pipe_config->name)) { \
11743 DRM_ERROR("mismatch in " #name " " \
11744 "(expected %i or %i, found %i)\n", \
11745 current_config->name, \
11746 current_config->alt_name, \
11747 pipe_config->name); \
11751 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11752 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11753 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11754 "(expected %i, found %i)\n", \
11755 current_config->name & (mask), \
11756 pipe_config->name & (mask)); \
11760 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11761 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11762 DRM_ERROR("mismatch in " #name " " \
11763 "(expected %i, found %i)\n", \
11764 current_config->name, \
11765 pipe_config->name); \
11769 #define PIPE_CONF_QUIRK(quirk) \
11770 ((current_config->quirks | pipe_config->quirks) & (quirk))
11772 PIPE_CONF_CHECK_I(cpu_transcoder
);
11774 PIPE_CONF_CHECK_I(has_pch_encoder
);
11775 PIPE_CONF_CHECK_I(fdi_lanes
);
11776 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11777 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11778 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11779 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
11780 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
11782 PIPE_CONF_CHECK_I(has_dp_encoder
);
11784 if (INTEL_INFO(dev
)->gen
< 8) {
11785 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
11786 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
11787 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
11788 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
11789 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
11791 if (current_config
->has_drrs
) {
11792 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
11793 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
11794 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
11795 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
11796 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
11799 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
11800 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
11801 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
11802 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
11803 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
11806 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11807 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11808 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11809 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11810 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11811 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11813 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11814 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11815 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11816 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11817 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11818 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11820 PIPE_CONF_CHECK_I(pixel_multiplier
);
11821 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11822 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
11823 IS_VALLEYVIEW(dev
))
11824 PIPE_CONF_CHECK_I(limited_color_range
);
11825 PIPE_CONF_CHECK_I(has_infoframe
);
11827 PIPE_CONF_CHECK_I(has_audio
);
11829 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11830 DRM_MODE_FLAG_INTERLACE
);
11832 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11833 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11834 DRM_MODE_FLAG_PHSYNC
);
11835 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11836 DRM_MODE_FLAG_NHSYNC
);
11837 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11838 DRM_MODE_FLAG_PVSYNC
);
11839 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11840 DRM_MODE_FLAG_NVSYNC
);
11843 PIPE_CONF_CHECK_I(pipe_src_w
);
11844 PIPE_CONF_CHECK_I(pipe_src_h
);
11847 * FIXME: BIOS likes to set up a cloned config with lvds+external
11848 * screen. Since we don't yet re-compute the pipe config when moving
11849 * just the lvds port away to another pipe the sw tracking won't match.
11851 * Proper atomic modesets with recomputed global state will fix this.
11852 * Until then just don't check gmch state for inherited modes.
11854 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
11855 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
11856 /* pfit ratios are autocomputed by the hw on gen4+ */
11857 if (INTEL_INFO(dev
)->gen
< 4)
11858 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
11859 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
11862 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11863 if (current_config
->pch_pfit
.enabled
) {
11864 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
11865 PIPE_CONF_CHECK_I(pch_pfit
.size
);
11868 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
11870 /* BDW+ don't expose a synchronous way to read the state */
11871 if (IS_HASWELL(dev
))
11872 PIPE_CONF_CHECK_I(ips_enabled
);
11874 PIPE_CONF_CHECK_I(double_wide
);
11876 PIPE_CONF_CHECK_X(ddi_pll_sel
);
11878 PIPE_CONF_CHECK_I(shared_dpll
);
11879 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11880 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11881 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11882 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11883 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11884 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11885 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11886 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11888 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
11889 PIPE_CONF_CHECK_I(pipe_bpp
);
11891 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11892 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11894 #undef PIPE_CONF_CHECK_X
11895 #undef PIPE_CONF_CHECK_I
11896 #undef PIPE_CONF_CHECK_I_ALT
11897 #undef PIPE_CONF_CHECK_FLAGS
11898 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11899 #undef PIPE_CONF_QUIRK
11904 static void check_wm_state(struct drm_device
*dev
)
11906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11907 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11908 struct intel_crtc
*intel_crtc
;
11911 if (INTEL_INFO(dev
)->gen
< 9)
11914 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11915 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11917 for_each_intel_crtc(dev
, intel_crtc
) {
11918 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
11919 const enum pipe pipe
= intel_crtc
->pipe
;
11921 if (!intel_crtc
->active
)
11925 for_each_plane(dev_priv
, pipe
, plane
) {
11926 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
11927 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
11929 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11932 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11933 "(expected (%u,%u), found (%u,%u))\n",
11934 pipe_name(pipe
), plane
+ 1,
11935 sw_entry
->start
, sw_entry
->end
,
11936 hw_entry
->start
, hw_entry
->end
);
11940 hw_entry
= &hw_ddb
.cursor
[pipe
];
11941 sw_entry
= &sw_ddb
->cursor
[pipe
];
11943 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11946 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11947 "(expected (%u,%u), found (%u,%u))\n",
11949 sw_entry
->start
, sw_entry
->end
,
11950 hw_entry
->start
, hw_entry
->end
);
11955 check_connector_state(struct drm_device
*dev
)
11957 struct intel_connector
*connector
;
11959 for_each_intel_connector(dev
, connector
) {
11960 /* This also checks the encoder/connector hw state with the
11961 * ->get_hw_state callbacks. */
11962 intel_connector_check_state(connector
);
11964 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
11965 "connector's staged encoder doesn't match current encoder\n");
11970 check_encoder_state(struct drm_device
*dev
)
11972 struct intel_encoder
*encoder
;
11973 struct intel_connector
*connector
;
11975 for_each_intel_encoder(dev
, encoder
) {
11976 bool enabled
= false;
11977 bool active
= false;
11978 enum pipe pipe
, tracked_pipe
;
11980 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11981 encoder
->base
.base
.id
,
11982 encoder
->base
.name
);
11984 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
11985 "encoder's stage crtc doesn't match current crtc\n");
11986 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
11987 "encoder's active_connectors set, but no crtc\n");
11989 for_each_intel_connector(dev
, connector
) {
11990 if (connector
->base
.encoder
!= &encoder
->base
)
11993 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
11997 * for MST connectors if we unplug the connector is gone
11998 * away but the encoder is still connected to a crtc
11999 * until a modeset happens in response to the hotplug.
12001 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
12004 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12005 "encoder's enabled state mismatch "
12006 "(expected %i, found %i)\n",
12007 !!encoder
->base
.crtc
, enabled
);
12008 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
12009 "active encoder with no crtc\n");
12011 I915_STATE_WARN(encoder
->connectors_active
!= active
,
12012 "encoder's computed active state doesn't match tracked active state "
12013 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
12015 active
= encoder
->get_hw_state(encoder
, &pipe
);
12016 I915_STATE_WARN(active
!= encoder
->connectors_active
,
12017 "encoder's hw state doesn't match sw tracking "
12018 "(expected %i, found %i)\n",
12019 encoder
->connectors_active
, active
);
12021 if (!encoder
->base
.crtc
)
12024 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
12025 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
12026 "active encoder's pipe doesn't match"
12027 "(expected %i, found %i)\n",
12028 tracked_pipe
, pipe
);
12034 check_crtc_state(struct drm_device
*dev
)
12036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12037 struct intel_crtc
*crtc
;
12038 struct intel_encoder
*encoder
;
12039 struct intel_crtc_state pipe_config
;
12041 for_each_intel_crtc(dev
, crtc
) {
12042 bool enabled
= false;
12043 bool active
= false;
12045 memset(&pipe_config
, 0, sizeof(pipe_config
));
12047 DRM_DEBUG_KMS("[CRTC:%d]\n",
12048 crtc
->base
.base
.id
);
12050 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
12051 "active crtc, but not enabled in sw tracking\n");
12053 for_each_intel_encoder(dev
, encoder
) {
12054 if (encoder
->base
.crtc
!= &crtc
->base
)
12057 if (encoder
->connectors_active
)
12061 I915_STATE_WARN(active
!= crtc
->active
,
12062 "crtc's computed active state doesn't match tracked active state "
12063 "(expected %i, found %i)\n", active
, crtc
->active
);
12064 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
12065 "crtc's computed enabled state doesn't match tracked enabled state "
12066 "(expected %i, found %i)\n", enabled
,
12067 crtc
->base
.state
->enable
);
12069 active
= dev_priv
->display
.get_pipe_config(crtc
,
12072 /* hw state is inconsistent with the pipe quirk */
12073 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12074 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12075 active
= crtc
->active
;
12077 for_each_intel_encoder(dev
, encoder
) {
12079 if (encoder
->base
.crtc
!= &crtc
->base
)
12081 if (encoder
->get_hw_state(encoder
, &pipe
))
12082 encoder
->get_config(encoder
, &pipe_config
);
12085 I915_STATE_WARN(crtc
->active
!= active
,
12086 "crtc active state doesn't match with hw state "
12087 "(expected %i, found %i)\n", crtc
->active
, active
);
12090 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12091 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12092 intel_dump_pipe_config(crtc
, &pipe_config
,
12094 intel_dump_pipe_config(crtc
, crtc
->config
,
12101 check_shared_dpll_state(struct drm_device
*dev
)
12103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12104 struct intel_crtc
*crtc
;
12105 struct intel_dpll_hw_state dpll_hw_state
;
12108 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12109 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12110 int enabled_crtcs
= 0, active_crtcs
= 0;
12113 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12115 DRM_DEBUG_KMS("%s\n", pll
->name
);
12117 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12119 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12120 "more active pll users than references: %i vs %i\n",
12121 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12122 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12123 "pll in active use but not on in sw tracking\n");
12124 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12125 "pll in on but not on in use in sw tracking\n");
12126 I915_STATE_WARN(pll
->on
!= active
,
12127 "pll on state mismatch (expected %i, found %i)\n",
12130 for_each_intel_crtc(dev
, crtc
) {
12131 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12133 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12136 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12137 "pll active crtcs mismatch (expected %i, found %i)\n",
12138 pll
->active
, active_crtcs
);
12139 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12140 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12141 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12143 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12144 sizeof(dpll_hw_state
)),
12145 "pll hw state mismatch\n");
12150 intel_modeset_check_state(struct drm_device
*dev
)
12152 check_wm_state(dev
);
12153 check_connector_state(dev
);
12154 check_encoder_state(dev
);
12155 check_crtc_state(dev
);
12156 check_shared_dpll_state(dev
);
12159 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12163 * FDI already provided one idea for the dotclock.
12164 * Yell if the encoder disagrees.
12166 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12167 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12168 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12171 static void update_scanline_offset(struct intel_crtc
*crtc
)
12173 struct drm_device
*dev
= crtc
->base
.dev
;
12176 * The scanline counter increments at the leading edge of hsync.
12178 * On most platforms it starts counting from vtotal-1 on the
12179 * first active line. That means the scanline counter value is
12180 * always one less than what we would expect. Ie. just after
12181 * start of vblank, which also occurs at start of hsync (on the
12182 * last active line), the scanline counter will read vblank_start-1.
12184 * On gen2 the scanline counter starts counting from 1 instead
12185 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12186 * to keep the value positive), instead of adding one.
12188 * On HSW+ the behaviour of the scanline counter depends on the output
12189 * type. For DP ports it behaves like most other platforms, but on HDMI
12190 * there's an extra 1 line difference. So we need to add two instead of
12191 * one to the value.
12193 if (IS_GEN2(dev
)) {
12194 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12197 vtotal
= mode
->crtc_vtotal
;
12198 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12201 crtc
->scanline_offset
= vtotal
- 1;
12202 } else if (HAS_DDI(dev
) &&
12203 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12204 crtc
->scanline_offset
= 2;
12206 crtc
->scanline_offset
= 1;
12209 static struct intel_crtc_state
*
12210 intel_modeset_compute_config(struct drm_crtc
*crtc
,
12211 struct drm_atomic_state
*state
)
12213 struct intel_crtc_state
*pipe_config
;
12216 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12218 return ERR_PTR(ret
);
12220 ret
= drm_atomic_helper_check_modeset(state
->dev
, state
);
12222 return ERR_PTR(ret
);
12225 * Note this needs changes when we start tracking multiple modes
12226 * and crtcs. At that point we'll need to compute the whole config
12227 * (i.e. one pipe_config for each crtc) rather than just the one
12230 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
12231 if (IS_ERR(pipe_config
))
12232 return pipe_config
;
12234 if (!pipe_config
->base
.enable
)
12235 return pipe_config
;
12237 ret
= intel_modeset_pipe_config(crtc
, state
, pipe_config
);
12239 return ERR_PTR(ret
);
12241 /* Check things that can only be changed through modeset */
12242 if (pipe_config
->has_audio
!=
12243 to_intel_crtc(crtc
)->config
->has_audio
)
12244 pipe_config
->base
.mode_changed
= true;
12247 * Note we have an issue here with infoframes: current code
12248 * only updates them on the full mode set path per hw
12249 * requirements. So here we should be checking for any
12250 * required changes and forcing a mode set.
12253 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,"[modeset]");
12255 ret
= drm_atomic_helper_check_planes(state
->dev
, state
);
12257 return ERR_PTR(ret
);
12259 return pipe_config
;
12262 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
)
12264 struct drm_device
*dev
= state
->dev
;
12265 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12266 unsigned clear_pipes
= 0;
12267 struct intel_crtc
*intel_crtc
;
12268 struct intel_crtc_state
*intel_crtc_state
;
12269 struct drm_crtc
*crtc
;
12270 struct drm_crtc_state
*crtc_state
;
12274 if (!dev_priv
->display
.crtc_compute_clock
)
12277 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12278 intel_crtc
= to_intel_crtc(crtc
);
12279 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12281 if (needs_modeset(crtc_state
)) {
12282 clear_pipes
|= 1 << intel_crtc
->pipe
;
12283 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12284 memset(&intel_crtc_state
->dpll_hw_state
, 0,
12285 sizeof(intel_crtc_state
->dpll_hw_state
));
12289 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
12293 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12294 if (!needs_modeset(crtc_state
) || !crtc_state
->enable
)
12297 intel_crtc
= to_intel_crtc(crtc
);
12298 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12300 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12303 intel_shared_dpll_abort_config(dev_priv
);
12312 /* Code that should eventually be part of atomic_check() */
12313 static int __intel_set_mode_checks(struct drm_atomic_state
*state
)
12315 struct drm_device
*dev
= state
->dev
;
12319 * See if the config requires any additional preparation, e.g.
12320 * to adjust global state with pipes off. We need to do this
12321 * here so we can get the modeset_pipe updated config for the new
12322 * mode set on this crtc. For other crtcs we need to use the
12323 * adjusted_mode bits in the crtc directly.
12325 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
12326 ret
= valleyview_modeset_global_pipes(state
);
12331 ret
= __intel_set_mode_setup_plls(state
);
12338 static int __intel_set_mode(struct drm_crtc
*modeset_crtc
,
12339 struct intel_crtc_state
*pipe_config
)
12341 struct drm_device
*dev
= modeset_crtc
->dev
;
12342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12343 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12344 struct drm_crtc
*crtc
;
12345 struct drm_crtc_state
*crtc_state
;
12349 ret
= __intel_set_mode_checks(state
);
12353 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
12357 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12358 if (!needs_modeset(crtc_state
))
12361 if (!crtc_state
->enable
) {
12362 intel_crtc_disable(crtc
);
12363 } else if (crtc
->state
->enable
) {
12364 intel_crtc_disable_planes(crtc
);
12365 dev_priv
->display
.crtc_disable(crtc
);
12369 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12370 * to set it here already despite that we pass it down the callchain.
12372 * Note we'll need to fix this up when we start tracking multiple
12373 * pipes; here we assume a single modeset_pipe and only track the
12374 * single crtc and mode.
12376 if (pipe_config
->base
.enable
&& needs_modeset(&pipe_config
->base
)) {
12377 modeset_crtc
->mode
= pipe_config
->base
.mode
;
12380 * Calculate and store various constants which
12381 * are later needed by vblank and swap-completion
12382 * timestamping. They are derived from true hwmode.
12384 drm_calc_timestamping_constants(modeset_crtc
,
12385 &pipe_config
->base
.adjusted_mode
);
12388 /* Only after disabling all output pipelines that will be changed can we
12389 * update the the output configuration. */
12390 intel_modeset_update_state(state
);
12392 /* The state has been swaped above, so state actually contains the
12393 * old state now. */
12395 modeset_update_crtc_power_domains(state
);
12397 drm_atomic_helper_commit_planes(dev
, state
);
12399 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12400 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12401 if (!needs_modeset(crtc
->state
) || !crtc
->state
->enable
)
12404 update_scanline_offset(to_intel_crtc(crtc
));
12406 dev_priv
->display
.crtc_enable(crtc
);
12407 intel_crtc_enable_planes(crtc
);
12410 /* FIXME: add subpixel order */
12412 drm_atomic_helper_cleanup_planes(dev
, state
);
12414 drm_atomic_state_free(state
);
12419 static int intel_set_mode_with_config(struct drm_crtc
*crtc
,
12420 struct intel_crtc_state
*pipe_config
)
12424 ret
= __intel_set_mode(crtc
, pipe_config
);
12427 intel_modeset_check_state(crtc
->dev
);
12432 static int intel_set_mode(struct drm_crtc
*crtc
,
12433 struct drm_atomic_state
*state
)
12435 struct intel_crtc_state
*pipe_config
;
12438 pipe_config
= intel_modeset_compute_config(crtc
, state
);
12439 if (IS_ERR(pipe_config
)) {
12440 ret
= PTR_ERR(pipe_config
);
12444 ret
= intel_set_mode_with_config(crtc
, pipe_config
);
12452 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
12454 struct drm_device
*dev
= crtc
->dev
;
12455 struct drm_atomic_state
*state
;
12456 struct intel_crtc
*intel_crtc
;
12457 struct intel_encoder
*encoder
;
12458 struct intel_connector
*connector
;
12459 struct drm_connector_state
*connector_state
;
12460 struct intel_crtc_state
*crtc_state
;
12463 state
= drm_atomic_state_alloc(dev
);
12465 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12470 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12472 /* The force restore path in the HW readout code relies on the staged
12473 * config still keeping the user requested config while the actual
12474 * state has been overwritten by the configuration read from HW. We
12475 * need to copy the staged config to the atomic state, otherwise the
12476 * mode set will just reapply the state the HW is already in. */
12477 for_each_intel_encoder(dev
, encoder
) {
12478 if (&encoder
->new_crtc
->base
!= crtc
)
12481 for_each_intel_connector(dev
, connector
) {
12482 if (connector
->new_encoder
!= encoder
)
12485 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
12486 if (IS_ERR(connector_state
)) {
12487 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12488 connector
->base
.base
.id
,
12489 connector
->base
.name
,
12490 PTR_ERR(connector_state
));
12494 connector_state
->crtc
= crtc
;
12495 connector_state
->best_encoder
= &encoder
->base
;
12499 for_each_intel_crtc(dev
, intel_crtc
) {
12500 if (intel_crtc
->new_enabled
== intel_crtc
->base
.enabled
)
12503 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12504 if (IS_ERR(crtc_state
)) {
12505 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12506 intel_crtc
->base
.base
.id
,
12507 PTR_ERR(crtc_state
));
12511 crtc_state
->base
.active
= crtc_state
->base
.enable
=
12512 intel_crtc
->new_enabled
;
12514 if (&intel_crtc
->base
== crtc
)
12515 drm_mode_copy(&crtc_state
->base
.mode
, &crtc
->mode
);
12518 intel_modeset_setup_plane_state(state
, crtc
, &crtc
->mode
,
12519 crtc
->primary
->fb
, crtc
->x
, crtc
->y
);
12521 ret
= intel_set_mode(crtc
, state
);
12523 drm_atomic_state_free(state
);
12526 #undef for_each_intel_crtc_masked
12528 static bool intel_connector_in_mode_set(struct intel_connector
*connector
,
12529 struct drm_mode_set
*set
)
12533 for (ro
= 0; ro
< set
->num_connectors
; ro
++)
12534 if (set
->connectors
[ro
] == &connector
->base
)
12541 intel_modeset_stage_output_state(struct drm_device
*dev
,
12542 struct drm_mode_set
*set
,
12543 struct drm_atomic_state
*state
)
12545 struct intel_connector
*connector
;
12546 struct drm_connector
*drm_connector
;
12547 struct drm_connector_state
*connector_state
;
12548 struct drm_crtc
*crtc
;
12549 struct drm_crtc_state
*crtc_state
;
12552 /* The upper layers ensure that we either disable a crtc or have a list
12553 * of connectors. For paranoia, double-check this. */
12554 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
12555 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
12557 for_each_intel_connector(dev
, connector
) {
12558 bool in_mode_set
= intel_connector_in_mode_set(connector
, set
);
12560 if (!in_mode_set
&& connector
->base
.state
->crtc
!= set
->crtc
)
12564 drm_atomic_get_connector_state(state
, &connector
->base
);
12565 if (IS_ERR(connector_state
))
12566 return PTR_ERR(connector_state
);
12569 int pipe
= to_intel_crtc(set
->crtc
)->pipe
;
12570 connector_state
->best_encoder
=
12571 &intel_find_encoder(connector
, pipe
)->base
;
12574 if (connector
->base
.state
->crtc
!= set
->crtc
)
12577 /* If we disable the crtc, disable all its connectors. Also, if
12578 * the connector is on the changing crtc but not on the new
12579 * connector list, disable it. */
12580 if (!set
->fb
|| !in_mode_set
) {
12581 connector_state
->best_encoder
= NULL
;
12583 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12584 connector
->base
.base
.id
,
12585 connector
->base
.name
);
12588 /* connector->new_encoder is now updated for all connectors. */
12590 for_each_connector_in_state(state
, drm_connector
, connector_state
, i
) {
12591 connector
= to_intel_connector(drm_connector
);
12593 if (!connector_state
->best_encoder
) {
12594 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
12602 if (intel_connector_in_mode_set(connector
, set
)) {
12603 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
12605 /* If this connector was in a previous crtc, add it
12606 * to the state. We might need to disable it. */
12609 drm_atomic_get_crtc_state(state
, crtc
);
12610 if (IS_ERR(crtc_state
))
12611 return PTR_ERR(crtc_state
);
12614 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
12620 /* Make sure the new CRTC will work with the encoder */
12621 if (!drm_encoder_crtc_ok(connector_state
->best_encoder
,
12622 connector_state
->crtc
)) {
12626 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12627 connector
->base
.base
.id
,
12628 connector
->base
.name
,
12629 connector_state
->crtc
->base
.id
);
12631 if (connector_state
->best_encoder
!= &connector
->encoder
->base
)
12632 connector
->encoder
=
12633 to_intel_encoder(connector_state
->best_encoder
);
12636 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12637 bool has_connectors
;
12639 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12643 has_connectors
= !!drm_atomic_connectors_for_crtc(state
, crtc
);
12644 if (has_connectors
!= crtc_state
->enable
)
12645 crtc_state
->enable
=
12646 crtc_state
->active
= has_connectors
;
12649 ret
= intel_modeset_setup_plane_state(state
, set
->crtc
, set
->mode
,
12650 set
->fb
, set
->x
, set
->y
);
12654 crtc_state
= drm_atomic_get_crtc_state(state
, set
->crtc
);
12655 if (IS_ERR(crtc_state
))
12656 return PTR_ERR(crtc_state
);
12659 drm_mode_copy(&crtc_state
->mode
, set
->mode
);
12661 if (set
->num_connectors
)
12662 crtc_state
->active
= true;
12667 static bool primary_plane_visible(struct drm_crtc
*crtc
)
12669 struct intel_plane_state
*plane_state
=
12670 to_intel_plane_state(crtc
->primary
->state
);
12672 return plane_state
->visible
;
12675 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12677 struct drm_device
*dev
;
12678 struct drm_atomic_state
*state
= NULL
;
12679 struct intel_crtc_state
*pipe_config
;
12680 bool primary_plane_was_visible
;
12684 BUG_ON(!set
->crtc
);
12685 BUG_ON(!set
->crtc
->helper_private
);
12687 /* Enforce sane interface api - has been abused by the fb helper. */
12688 BUG_ON(!set
->mode
&& set
->fb
);
12689 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12692 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12693 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12694 (int)set
->num_connectors
, set
->x
, set
->y
);
12696 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12699 dev
= set
->crtc
->dev
;
12701 state
= drm_atomic_state_alloc(dev
);
12705 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12707 ret
= intel_modeset_stage_output_state(dev
, set
, state
);
12711 pipe_config
= intel_modeset_compute_config(set
->crtc
, state
);
12712 if (IS_ERR(pipe_config
)) {
12713 ret
= PTR_ERR(pipe_config
);
12717 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12719 primary_plane_was_visible
= primary_plane_visible(set
->crtc
);
12721 ret
= intel_set_mode_with_config(set
->crtc
, pipe_config
);
12724 pipe_config
->base
.enable
&&
12725 pipe_config
->base
.planes_changed
&&
12726 !needs_modeset(&pipe_config
->base
)) {
12727 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12730 * We need to make sure the primary plane is re-enabled if it
12731 * has previously been turned off.
12733 if (ret
== 0 && !primary_plane_was_visible
&&
12734 primary_plane_visible(set
->crtc
)) {
12735 WARN_ON(!intel_crtc
->active
);
12736 intel_post_enable_primary(set
->crtc
);
12740 * In the fastboot case this may be our only check of the
12741 * state after boot. It would be better to only do it on
12742 * the first update, but we don't have a nice way of doing that
12743 * (and really, set_config isn't used much for high freq page
12744 * flipping, so increasing its cost here shouldn't be a big
12747 if (i915
.fastboot
&& ret
== 0)
12748 intel_modeset_check_state(set
->crtc
->dev
);
12752 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12753 set
->crtc
->base
.id
, ret
);
12758 drm_atomic_state_free(state
);
12762 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12763 .gamma_set
= intel_crtc_gamma_set
,
12764 .set_config
= intel_crtc_set_config
,
12765 .destroy
= intel_crtc_destroy
,
12766 .page_flip
= intel_crtc_page_flip
,
12767 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12768 .atomic_destroy_state
= intel_crtc_destroy_state
,
12771 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
12772 struct intel_shared_dpll
*pll
,
12773 struct intel_dpll_hw_state
*hw_state
)
12777 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
12780 val
= I915_READ(PCH_DPLL(pll
->id
));
12781 hw_state
->dpll
= val
;
12782 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
12783 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
12785 return val
& DPLL_VCO_ENABLE
;
12788 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
12789 struct intel_shared_dpll
*pll
)
12791 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
12792 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
12795 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
12796 struct intel_shared_dpll
*pll
)
12798 /* PCH refclock must be enabled first */
12799 ibx_assert_pch_refclk_enabled(dev_priv
);
12801 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12803 /* Wait for the clocks to stabilize. */
12804 POSTING_READ(PCH_DPLL(pll
->id
));
12807 /* The pixel multiplier can only be updated once the
12808 * DPLL is enabled and the clocks are stable.
12810 * So write it again.
12812 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12813 POSTING_READ(PCH_DPLL(pll
->id
));
12817 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
12818 struct intel_shared_dpll
*pll
)
12820 struct drm_device
*dev
= dev_priv
->dev
;
12821 struct intel_crtc
*crtc
;
12823 /* Make sure no transcoder isn't still depending on us. */
12824 for_each_intel_crtc(dev
, crtc
) {
12825 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
12826 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
12829 I915_WRITE(PCH_DPLL(pll
->id
), 0);
12830 POSTING_READ(PCH_DPLL(pll
->id
));
12834 static char *ibx_pch_dpll_names
[] = {
12839 static void ibx_pch_dpll_init(struct drm_device
*dev
)
12841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12844 dev_priv
->num_shared_dpll
= 2;
12846 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12847 dev_priv
->shared_dplls
[i
].id
= i
;
12848 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
12849 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
12850 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
12851 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
12852 dev_priv
->shared_dplls
[i
].get_hw_state
=
12853 ibx_pch_dpll_get_hw_state
;
12857 static void intel_shared_dpll_init(struct drm_device
*dev
)
12859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12862 intel_ddi_pll_init(dev
);
12863 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
12864 ibx_pch_dpll_init(dev
);
12866 dev_priv
->num_shared_dpll
= 0;
12868 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
12872 * intel_wm_need_update - Check whether watermarks need updating
12873 * @plane: drm plane
12874 * @state: new plane state
12876 * Check current plane state versus the new one to determine whether
12877 * watermarks need to be recalculated.
12879 * Returns true or false.
12881 bool intel_wm_need_update(struct drm_plane
*plane
,
12882 struct drm_plane_state
*state
)
12884 /* Update watermarks on tiling changes. */
12885 if (!plane
->state
->fb
|| !state
->fb
||
12886 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
12887 plane
->state
->rotation
!= state
->rotation
)
12894 * intel_prepare_plane_fb - Prepare fb for usage on plane
12895 * @plane: drm plane to prepare for
12896 * @fb: framebuffer to prepare for presentation
12898 * Prepares a framebuffer for usage on a display plane. Generally this
12899 * involves pinning the underlying object and updating the frontbuffer tracking
12900 * bits. Some older platforms need special physical address handling for
12903 * Returns 0 on success, negative error code on failure.
12906 intel_prepare_plane_fb(struct drm_plane
*plane
,
12907 struct drm_framebuffer
*fb
,
12908 const struct drm_plane_state
*new_state
)
12910 struct drm_device
*dev
= plane
->dev
;
12911 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12912 enum pipe pipe
= intel_plane
->pipe
;
12913 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12914 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
12915 unsigned frontbuffer_bits
= 0;
12921 switch (plane
->type
) {
12922 case DRM_PLANE_TYPE_PRIMARY
:
12923 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
12925 case DRM_PLANE_TYPE_CURSOR
:
12926 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
12928 case DRM_PLANE_TYPE_OVERLAY
:
12929 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
12933 mutex_lock(&dev
->struct_mutex
);
12935 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
12936 INTEL_INFO(dev
)->cursor_needs_physical
) {
12937 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
12938 ret
= i915_gem_object_attach_phys(obj
, align
);
12940 DRM_DEBUG_KMS("failed to attach phys object\n");
12942 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
12946 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
12948 mutex_unlock(&dev
->struct_mutex
);
12954 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12955 * @plane: drm plane to clean up for
12956 * @fb: old framebuffer that was on plane
12958 * Cleans up a framebuffer that has just been removed from a plane.
12961 intel_cleanup_plane_fb(struct drm_plane
*plane
,
12962 struct drm_framebuffer
*fb
,
12963 const struct drm_plane_state
*old_state
)
12965 struct drm_device
*dev
= plane
->dev
;
12966 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12971 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
12972 !INTEL_INFO(dev
)->cursor_needs_physical
) {
12973 mutex_lock(&dev
->struct_mutex
);
12974 intel_unpin_fb_obj(fb
, old_state
);
12975 mutex_unlock(&dev
->struct_mutex
);
12980 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
12983 struct drm_device
*dev
;
12984 struct drm_i915_private
*dev_priv
;
12985 int crtc_clock
, cdclk
;
12987 if (!intel_crtc
|| !crtc_state
)
12988 return DRM_PLANE_HELPER_NO_SCALING
;
12990 dev
= intel_crtc
->base
.dev
;
12991 dev_priv
= dev
->dev_private
;
12992 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
12993 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
12995 if (!crtc_clock
|| !cdclk
)
12996 return DRM_PLANE_HELPER_NO_SCALING
;
12999 * skl max scale is lower of:
13000 * close to 3 but not 3, -1 is for that purpose
13004 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13010 intel_check_primary_plane(struct drm_plane
*plane
,
13011 struct intel_plane_state
*state
)
13013 struct drm_device
*dev
= plane
->dev
;
13014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13015 struct drm_crtc
*crtc
= state
->base
.crtc
;
13016 struct intel_crtc
*intel_crtc
;
13017 struct intel_crtc_state
*crtc_state
;
13018 struct drm_framebuffer
*fb
= state
->base
.fb
;
13019 struct drm_rect
*dest
= &state
->dst
;
13020 struct drm_rect
*src
= &state
->src
;
13021 const struct drm_rect
*clip
= &state
->clip
;
13022 bool can_position
= false;
13023 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13024 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13027 crtc
= crtc
? crtc
: plane
->crtc
;
13028 intel_crtc
= to_intel_crtc(crtc
);
13029 crtc_state
= state
->base
.state
?
13030 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
13032 if (INTEL_INFO(dev
)->gen
>= 9) {
13034 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
13035 can_position
= true;
13038 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13042 can_position
, true,
13047 if (intel_crtc
->active
) {
13048 struct intel_plane_state
*old_state
=
13049 to_intel_plane_state(plane
->state
);
13051 intel_crtc
->atomic
.wait_for_flips
= true;
13054 * FBC does not work on some platforms for rotated
13055 * planes, so disable it when rotation is not 0 and
13056 * update it when rotation is set back to 0.
13058 * FIXME: This is redundant with the fbc update done in
13059 * the primary plane enable function except that that
13060 * one is done too late. We eventually need to unify
13063 if (state
->visible
&&
13064 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
13065 dev_priv
->fbc
.crtc
== intel_crtc
&&
13066 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
13067 intel_crtc
->atomic
.disable_fbc
= true;
13070 if (state
->visible
&& !old_state
->visible
) {
13072 * BDW signals flip done immediately if the plane
13073 * is disabled, even if the plane enable is already
13074 * armed to occur at the next vblank :(
13076 if (IS_BROADWELL(dev
))
13077 intel_crtc
->atomic
.wait_vblank
= true;
13080 intel_crtc
->atomic
.fb_bits
|=
13081 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
13083 intel_crtc
->atomic
.update_fbc
= true;
13085 if (intel_wm_need_update(plane
, &state
->base
))
13086 intel_crtc
->atomic
.update_wm
= true;
13089 if (INTEL_INFO(dev
)->gen
>= 9) {
13090 ret
= skl_update_scaler_users(intel_crtc
, crtc_state
,
13091 to_intel_plane(plane
), state
, 0);
13100 intel_commit_primary_plane(struct drm_plane
*plane
,
13101 struct intel_plane_state
*state
)
13103 struct drm_crtc
*crtc
= state
->base
.crtc
;
13104 struct drm_framebuffer
*fb
= state
->base
.fb
;
13105 struct drm_device
*dev
= plane
->dev
;
13106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13107 struct intel_crtc
*intel_crtc
;
13108 struct drm_rect
*src
= &state
->src
;
13110 crtc
= crtc
? crtc
: plane
->crtc
;
13111 intel_crtc
= to_intel_crtc(crtc
);
13114 crtc
->x
= src
->x1
>> 16;
13115 crtc
->y
= src
->y1
>> 16;
13117 if (intel_crtc
->active
) {
13118 if (state
->visible
)
13119 /* FIXME: kill this fastboot hack */
13120 intel_update_pipe_size(intel_crtc
);
13122 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
13128 intel_disable_primary_plane(struct drm_plane
*plane
,
13129 struct drm_crtc
*crtc
,
13132 struct drm_device
*dev
= plane
->dev
;
13133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13135 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13138 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13140 struct drm_device
*dev
= crtc
->dev
;
13141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13143 struct intel_plane
*intel_plane
;
13144 struct drm_plane
*p
;
13145 unsigned fb_bits
= 0;
13147 /* Track fb's for any planes being disabled */
13148 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
13149 intel_plane
= to_intel_plane(p
);
13151 if (intel_crtc
->atomic
.disabled_planes
&
13152 (1 << drm_plane_index(p
))) {
13154 case DRM_PLANE_TYPE_PRIMARY
:
13155 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
13157 case DRM_PLANE_TYPE_CURSOR
:
13158 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
13160 case DRM_PLANE_TYPE_OVERLAY
:
13161 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
13165 mutex_lock(&dev
->struct_mutex
);
13166 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
13167 mutex_unlock(&dev
->struct_mutex
);
13171 if (intel_crtc
->atomic
.wait_for_flips
)
13172 intel_crtc_wait_for_pending_flips(crtc
);
13174 if (intel_crtc
->atomic
.disable_fbc
)
13175 intel_fbc_disable(dev
);
13177 if (intel_crtc
->atomic
.pre_disable_primary
)
13178 intel_pre_disable_primary(crtc
);
13180 if (intel_crtc
->atomic
.update_wm
)
13181 intel_update_watermarks(crtc
);
13183 intel_runtime_pm_get(dev_priv
);
13185 /* Perform vblank evasion around commit operation */
13186 if (intel_crtc
->active
)
13187 intel_crtc
->atomic
.evade
=
13188 intel_pipe_update_start(intel_crtc
,
13189 &intel_crtc
->atomic
.start_vbl_count
);
13192 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13194 struct drm_device
*dev
= crtc
->dev
;
13195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13197 struct drm_plane
*p
;
13199 if (intel_crtc
->atomic
.evade
)
13200 intel_pipe_update_end(intel_crtc
,
13201 intel_crtc
->atomic
.start_vbl_count
);
13203 intel_runtime_pm_put(dev_priv
);
13205 if (intel_crtc
->atomic
.wait_vblank
)
13206 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
13208 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
13210 if (intel_crtc
->atomic
.update_fbc
) {
13211 mutex_lock(&dev
->struct_mutex
);
13212 intel_fbc_update(dev
);
13213 mutex_unlock(&dev
->struct_mutex
);
13216 if (intel_crtc
->atomic
.post_enable_primary
)
13217 intel_post_enable_primary(crtc
);
13219 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
13220 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
13221 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
13224 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
13228 * intel_plane_destroy - destroy a plane
13229 * @plane: plane to destroy
13231 * Common destruction function for all types of planes (primary, cursor,
13234 void intel_plane_destroy(struct drm_plane
*plane
)
13236 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13237 drm_plane_cleanup(plane
);
13238 kfree(intel_plane
);
13241 const struct drm_plane_funcs intel_plane_funcs
= {
13242 .update_plane
= drm_atomic_helper_update_plane
,
13243 .disable_plane
= drm_atomic_helper_disable_plane
,
13244 .destroy
= intel_plane_destroy
,
13245 .set_property
= drm_atomic_helper_plane_set_property
,
13246 .atomic_get_property
= intel_plane_atomic_get_property
,
13247 .atomic_set_property
= intel_plane_atomic_set_property
,
13248 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13249 .atomic_destroy_state
= intel_plane_destroy_state
,
13253 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13256 struct intel_plane
*primary
;
13257 struct intel_plane_state
*state
;
13258 const uint32_t *intel_primary_formats
;
13261 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13262 if (primary
== NULL
)
13265 state
= intel_create_plane_state(&primary
->base
);
13270 primary
->base
.state
= &state
->base
;
13272 primary
->can_scale
= false;
13273 primary
->max_downscale
= 1;
13274 if (INTEL_INFO(dev
)->gen
>= 9) {
13275 primary
->can_scale
= true;
13276 state
->scaler_id
= -1;
13278 primary
->pipe
= pipe
;
13279 primary
->plane
= pipe
;
13280 primary
->check_plane
= intel_check_primary_plane
;
13281 primary
->commit_plane
= intel_commit_primary_plane
;
13282 primary
->disable_plane
= intel_disable_primary_plane
;
13283 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13284 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13285 primary
->plane
= !pipe
;
13287 if (INTEL_INFO(dev
)->gen
<= 3) {
13288 intel_primary_formats
= intel_primary_formats_gen2
;
13289 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
13291 intel_primary_formats
= intel_primary_formats_gen4
;
13292 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
13295 drm_universal_plane_init(dev
, &primary
->base
, 0,
13296 &intel_plane_funcs
,
13297 intel_primary_formats
, num_formats
,
13298 DRM_PLANE_TYPE_PRIMARY
);
13300 if (INTEL_INFO(dev
)->gen
>= 4)
13301 intel_create_rotation_property(dev
, primary
);
13303 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13305 return &primary
->base
;
13308 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13310 if (!dev
->mode_config
.rotation_property
) {
13311 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13312 BIT(DRM_ROTATE_180
);
13314 if (INTEL_INFO(dev
)->gen
>= 9)
13315 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13317 dev
->mode_config
.rotation_property
=
13318 drm_mode_create_rotation_property(dev
, flags
);
13320 if (dev
->mode_config
.rotation_property
)
13321 drm_object_attach_property(&plane
->base
.base
,
13322 dev
->mode_config
.rotation_property
,
13323 plane
->base
.state
->rotation
);
13327 intel_check_cursor_plane(struct drm_plane
*plane
,
13328 struct intel_plane_state
*state
)
13330 struct drm_crtc
*crtc
= state
->base
.crtc
;
13331 struct drm_device
*dev
= plane
->dev
;
13332 struct drm_framebuffer
*fb
= state
->base
.fb
;
13333 struct drm_rect
*dest
= &state
->dst
;
13334 struct drm_rect
*src
= &state
->src
;
13335 const struct drm_rect
*clip
= &state
->clip
;
13336 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13337 struct intel_crtc
*intel_crtc
;
13341 crtc
= crtc
? crtc
: plane
->crtc
;
13342 intel_crtc
= to_intel_crtc(crtc
);
13344 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13346 DRM_PLANE_HELPER_NO_SCALING
,
13347 DRM_PLANE_HELPER_NO_SCALING
,
13348 true, true, &state
->visible
);
13353 /* if we want to turn off the cursor ignore width and height */
13357 /* Check for which cursor types we support */
13358 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13359 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13360 state
->base
.crtc_w
, state
->base
.crtc_h
);
13364 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13365 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13366 DRM_DEBUG_KMS("buffer is too small\n");
13370 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13371 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13376 if (intel_crtc
->active
) {
13377 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
13378 intel_crtc
->atomic
.update_wm
= true;
13380 intel_crtc
->atomic
.fb_bits
|=
13381 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
13388 intel_disable_cursor_plane(struct drm_plane
*plane
,
13389 struct drm_crtc
*crtc
,
13392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13396 intel_crtc
->cursor_bo
= NULL
;
13397 intel_crtc
->cursor_addr
= 0;
13400 intel_crtc_update_cursor(crtc
, false);
13404 intel_commit_cursor_plane(struct drm_plane
*plane
,
13405 struct intel_plane_state
*state
)
13407 struct drm_crtc
*crtc
= state
->base
.crtc
;
13408 struct drm_device
*dev
= plane
->dev
;
13409 struct intel_crtc
*intel_crtc
;
13410 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13413 crtc
= crtc
? crtc
: plane
->crtc
;
13414 intel_crtc
= to_intel_crtc(crtc
);
13416 plane
->fb
= state
->base
.fb
;
13417 crtc
->cursor_x
= state
->base
.crtc_x
;
13418 crtc
->cursor_y
= state
->base
.crtc_y
;
13420 if (intel_crtc
->cursor_bo
== obj
)
13425 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13426 addr
= i915_gem_obj_ggtt_offset(obj
);
13428 addr
= obj
->phys_handle
->busaddr
;
13430 intel_crtc
->cursor_addr
= addr
;
13431 intel_crtc
->cursor_bo
= obj
;
13434 if (intel_crtc
->active
)
13435 intel_crtc_update_cursor(crtc
, state
->visible
);
13438 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13441 struct intel_plane
*cursor
;
13442 struct intel_plane_state
*state
;
13444 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13445 if (cursor
== NULL
)
13448 state
= intel_create_plane_state(&cursor
->base
);
13453 cursor
->base
.state
= &state
->base
;
13455 cursor
->can_scale
= false;
13456 cursor
->max_downscale
= 1;
13457 cursor
->pipe
= pipe
;
13458 cursor
->plane
= pipe
;
13459 cursor
->check_plane
= intel_check_cursor_plane
;
13460 cursor
->commit_plane
= intel_commit_cursor_plane
;
13461 cursor
->disable_plane
= intel_disable_cursor_plane
;
13463 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13464 &intel_plane_funcs
,
13465 intel_cursor_formats
,
13466 ARRAY_SIZE(intel_cursor_formats
),
13467 DRM_PLANE_TYPE_CURSOR
);
13469 if (INTEL_INFO(dev
)->gen
>= 4) {
13470 if (!dev
->mode_config
.rotation_property
)
13471 dev
->mode_config
.rotation_property
=
13472 drm_mode_create_rotation_property(dev
,
13473 BIT(DRM_ROTATE_0
) |
13474 BIT(DRM_ROTATE_180
));
13475 if (dev
->mode_config
.rotation_property
)
13476 drm_object_attach_property(&cursor
->base
.base
,
13477 dev
->mode_config
.rotation_property
,
13478 state
->base
.rotation
);
13481 if (INTEL_INFO(dev
)->gen
>=9)
13482 state
->scaler_id
= -1;
13484 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13486 return &cursor
->base
;
13489 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13490 struct intel_crtc_state
*crtc_state
)
13493 struct intel_scaler
*intel_scaler
;
13494 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13496 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13497 intel_scaler
= &scaler_state
->scalers
[i
];
13498 intel_scaler
->in_use
= 0;
13499 intel_scaler
->id
= i
;
13501 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13504 scaler_state
->scaler_id
= -1;
13507 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13510 struct intel_crtc
*intel_crtc
;
13511 struct intel_crtc_state
*crtc_state
= NULL
;
13512 struct drm_plane
*primary
= NULL
;
13513 struct drm_plane
*cursor
= NULL
;
13516 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13517 if (intel_crtc
== NULL
)
13520 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13523 intel_crtc
->config
= crtc_state
;
13524 intel_crtc
->base
.state
= &crtc_state
->base
;
13525 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13527 /* initialize shared scalers */
13528 if (INTEL_INFO(dev
)->gen
>= 9) {
13529 if (pipe
== PIPE_C
)
13530 intel_crtc
->num_scalers
= 1;
13532 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13534 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13537 primary
= intel_primary_plane_create(dev
, pipe
);
13541 cursor
= intel_cursor_plane_create(dev
, pipe
);
13545 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13546 cursor
, &intel_crtc_funcs
);
13550 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13551 for (i
= 0; i
< 256; i
++) {
13552 intel_crtc
->lut_r
[i
] = i
;
13553 intel_crtc
->lut_g
[i
] = i
;
13554 intel_crtc
->lut_b
[i
] = i
;
13558 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13559 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13561 intel_crtc
->pipe
= pipe
;
13562 intel_crtc
->plane
= pipe
;
13563 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13564 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13565 intel_crtc
->plane
= !pipe
;
13568 intel_crtc
->cursor_base
= ~0;
13569 intel_crtc
->cursor_cntl
= ~0;
13570 intel_crtc
->cursor_size
= ~0;
13572 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13573 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13574 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13575 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13577 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13579 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13584 drm_plane_cleanup(primary
);
13586 drm_plane_cleanup(cursor
);
13591 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13593 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13594 struct drm_device
*dev
= connector
->base
.dev
;
13596 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13598 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13599 return INVALID_PIPE
;
13601 return to_intel_crtc(encoder
->crtc
)->pipe
;
13604 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13605 struct drm_file
*file
)
13607 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13608 struct drm_crtc
*drmmode_crtc
;
13609 struct intel_crtc
*crtc
;
13611 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13613 if (!drmmode_crtc
) {
13614 DRM_ERROR("no such CRTC id\n");
13618 crtc
= to_intel_crtc(drmmode_crtc
);
13619 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13624 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13626 struct drm_device
*dev
= encoder
->base
.dev
;
13627 struct intel_encoder
*source_encoder
;
13628 int index_mask
= 0;
13631 for_each_intel_encoder(dev
, source_encoder
) {
13632 if (encoders_cloneable(encoder
, source_encoder
))
13633 index_mask
|= (1 << entry
);
13641 static bool has_edp_a(struct drm_device
*dev
)
13643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13645 if (!IS_MOBILE(dev
))
13648 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13651 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13657 static bool intel_crt_present(struct drm_device
*dev
)
13659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13661 if (INTEL_INFO(dev
)->gen
>= 9)
13664 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13667 if (IS_CHERRYVIEW(dev
))
13670 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13676 static void intel_setup_outputs(struct drm_device
*dev
)
13678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13679 struct intel_encoder
*encoder
;
13680 bool dpd_is_edp
= false;
13682 intel_lvds_init(dev
);
13684 if (intel_crt_present(dev
))
13685 intel_crt_init(dev
);
13687 if (IS_BROXTON(dev
)) {
13689 * FIXME: Broxton doesn't support port detection via the
13690 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13691 * detect the ports.
13693 intel_ddi_init(dev
, PORT_A
);
13694 intel_ddi_init(dev
, PORT_B
);
13695 intel_ddi_init(dev
, PORT_C
);
13696 } else if (HAS_DDI(dev
)) {
13700 * Haswell uses DDI functions to detect digital outputs.
13701 * On SKL pre-D0 the strap isn't connected, so we assume
13704 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13705 /* WaIgnoreDDIAStrap: skl */
13707 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13708 intel_ddi_init(dev
, PORT_A
);
13710 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13712 found
= I915_READ(SFUSE_STRAP
);
13714 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13715 intel_ddi_init(dev
, PORT_B
);
13716 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13717 intel_ddi_init(dev
, PORT_C
);
13718 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13719 intel_ddi_init(dev
, PORT_D
);
13720 } else if (HAS_PCH_SPLIT(dev
)) {
13722 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13724 if (has_edp_a(dev
))
13725 intel_dp_init(dev
, DP_A
, PORT_A
);
13727 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13728 /* PCH SDVOB multiplex with HDMIB */
13729 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13731 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13732 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13733 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13736 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13737 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13739 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13740 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13742 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13743 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13745 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13746 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13747 } else if (IS_VALLEYVIEW(dev
)) {
13749 * The DP_DETECTED bit is the latched state of the DDC
13750 * SDA pin at boot. However since eDP doesn't require DDC
13751 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13752 * eDP ports may have been muxed to an alternate function.
13753 * Thus we can't rely on the DP_DETECTED bit alone to detect
13754 * eDP ports. Consult the VBT as well as DP_DETECTED to
13755 * detect eDP ports.
13757 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13758 !intel_dp_is_edp(dev
, PORT_B
))
13759 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13761 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13762 intel_dp_is_edp(dev
, PORT_B
))
13763 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13765 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13766 !intel_dp_is_edp(dev
, PORT_C
))
13767 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13769 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13770 intel_dp_is_edp(dev
, PORT_C
))
13771 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13773 if (IS_CHERRYVIEW(dev
)) {
13774 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13775 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
13777 /* eDP not supported on port D, so don't check VBT */
13778 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
13779 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
13782 intel_dsi_init(dev
);
13783 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
13784 bool found
= false;
13786 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13787 DRM_DEBUG_KMS("probing SDVOB\n");
13788 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
13789 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
13790 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13791 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
13794 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
13795 intel_dp_init(dev
, DP_B
, PORT_B
);
13798 /* Before G4X SDVOC doesn't have its own detect register */
13800 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13801 DRM_DEBUG_KMS("probing SDVOC\n");
13802 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
13805 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
13807 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
13808 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13809 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
13811 if (SUPPORTS_INTEGRATED_DP(dev
))
13812 intel_dp_init(dev
, DP_C
, PORT_C
);
13815 if (SUPPORTS_INTEGRATED_DP(dev
) &&
13816 (I915_READ(DP_D
) & DP_DETECTED
))
13817 intel_dp_init(dev
, DP_D
, PORT_D
);
13818 } else if (IS_GEN2(dev
))
13819 intel_dvo_init(dev
);
13821 if (SUPPORTS_TV(dev
))
13822 intel_tv_init(dev
);
13824 intel_psr_init(dev
);
13826 for_each_intel_encoder(dev
, encoder
) {
13827 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
13828 encoder
->base
.possible_clones
=
13829 intel_encoder_clones(encoder
);
13832 intel_init_pch_refclk(dev
);
13834 drm_helper_move_panel_connectors_to_head(dev
);
13837 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
13839 struct drm_device
*dev
= fb
->dev
;
13840 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13842 drm_framebuffer_cleanup(fb
);
13843 mutex_lock(&dev
->struct_mutex
);
13844 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
13845 drm_gem_object_unreference(&intel_fb
->obj
->base
);
13846 mutex_unlock(&dev
->struct_mutex
);
13850 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
13851 struct drm_file
*file
,
13852 unsigned int *handle
)
13854 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13855 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
13857 return drm_gem_handle_create(file
, &obj
->base
, handle
);
13860 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
13861 .destroy
= intel_user_framebuffer_destroy
,
13862 .create_handle
= intel_user_framebuffer_create_handle
,
13866 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
13867 uint32_t pixel_format
)
13869 u32 gen
= INTEL_INFO(dev
)->gen
;
13872 /* "The stride in bytes must not exceed the of the size of 8K
13873 * pixels and 32K bytes."
13875 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
13876 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
13878 } else if (gen
>= 4) {
13879 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13883 } else if (gen
>= 3) {
13884 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13889 /* XXX DSPC is limited to 4k tiled */
13894 static int intel_framebuffer_init(struct drm_device
*dev
,
13895 struct intel_framebuffer
*intel_fb
,
13896 struct drm_mode_fb_cmd2
*mode_cmd
,
13897 struct drm_i915_gem_object
*obj
)
13899 unsigned int aligned_height
;
13901 u32 pitch_limit
, stride_alignment
;
13903 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
13905 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
13906 /* Enforce that fb modifier and tiling mode match, but only for
13907 * X-tiled. This is needed for FBC. */
13908 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
13909 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
13910 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13914 if (obj
->tiling_mode
== I915_TILING_X
)
13915 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
13916 else if (obj
->tiling_mode
== I915_TILING_Y
) {
13917 DRM_DEBUG("No Y tiling for legacy addfb\n");
13922 /* Passed in modifier sanity checking. */
13923 switch (mode_cmd
->modifier
[0]) {
13924 case I915_FORMAT_MOD_Y_TILED
:
13925 case I915_FORMAT_MOD_Yf_TILED
:
13926 if (INTEL_INFO(dev
)->gen
< 9) {
13927 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13928 mode_cmd
->modifier
[0]);
13931 case DRM_FORMAT_MOD_NONE
:
13932 case I915_FORMAT_MOD_X_TILED
:
13935 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13936 mode_cmd
->modifier
[0]);
13940 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
13941 mode_cmd
->pixel_format
);
13942 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
13943 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13944 mode_cmd
->pitches
[0], stride_alignment
);
13948 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
13949 mode_cmd
->pixel_format
);
13950 if (mode_cmd
->pitches
[0] > pitch_limit
) {
13951 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13952 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
13953 "tiled" : "linear",
13954 mode_cmd
->pitches
[0], pitch_limit
);
13958 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
13959 mode_cmd
->pitches
[0] != obj
->stride
) {
13960 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13961 mode_cmd
->pitches
[0], obj
->stride
);
13965 /* Reject formats not supported by any plane early. */
13966 switch (mode_cmd
->pixel_format
) {
13967 case DRM_FORMAT_C8
:
13968 case DRM_FORMAT_RGB565
:
13969 case DRM_FORMAT_XRGB8888
:
13970 case DRM_FORMAT_ARGB8888
:
13972 case DRM_FORMAT_XRGB1555
:
13973 case DRM_FORMAT_ARGB1555
:
13974 if (INTEL_INFO(dev
)->gen
> 3) {
13975 DRM_DEBUG("unsupported pixel format: %s\n",
13976 drm_get_format_name(mode_cmd
->pixel_format
));
13980 case DRM_FORMAT_XBGR8888
:
13981 case DRM_FORMAT_ABGR8888
:
13982 case DRM_FORMAT_XRGB2101010
:
13983 case DRM_FORMAT_ARGB2101010
:
13984 case DRM_FORMAT_XBGR2101010
:
13985 case DRM_FORMAT_ABGR2101010
:
13986 if (INTEL_INFO(dev
)->gen
< 4) {
13987 DRM_DEBUG("unsupported pixel format: %s\n",
13988 drm_get_format_name(mode_cmd
->pixel_format
));
13992 case DRM_FORMAT_YUYV
:
13993 case DRM_FORMAT_UYVY
:
13994 case DRM_FORMAT_YVYU
:
13995 case DRM_FORMAT_VYUY
:
13996 if (INTEL_INFO(dev
)->gen
< 5) {
13997 DRM_DEBUG("unsupported pixel format: %s\n",
13998 drm_get_format_name(mode_cmd
->pixel_format
));
14003 DRM_DEBUG("unsupported pixel format: %s\n",
14004 drm_get_format_name(mode_cmd
->pixel_format
));
14008 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14009 if (mode_cmd
->offsets
[0] != 0)
14012 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14013 mode_cmd
->pixel_format
,
14014 mode_cmd
->modifier
[0]);
14015 /* FIXME drm helper for size checks (especially planar formats)? */
14016 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14019 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14020 intel_fb
->obj
= obj
;
14021 intel_fb
->obj
->framebuffer_references
++;
14023 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14025 DRM_ERROR("framebuffer init failed %d\n", ret
);
14032 static struct drm_framebuffer
*
14033 intel_user_framebuffer_create(struct drm_device
*dev
,
14034 struct drm_file
*filp
,
14035 struct drm_mode_fb_cmd2
*mode_cmd
)
14037 struct drm_i915_gem_object
*obj
;
14039 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14040 mode_cmd
->handles
[0]));
14041 if (&obj
->base
== NULL
)
14042 return ERR_PTR(-ENOENT
);
14044 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14047 #ifndef CONFIG_DRM_I915_FBDEV
14048 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14053 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14054 .fb_create
= intel_user_framebuffer_create
,
14055 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14056 .atomic_check
= intel_atomic_check
,
14057 .atomic_commit
= intel_atomic_commit
,
14060 /* Set up chip specific display functions */
14061 static void intel_init_display(struct drm_device
*dev
)
14063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14065 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14066 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14067 else if (IS_CHERRYVIEW(dev
))
14068 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14069 else if (IS_VALLEYVIEW(dev
))
14070 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14071 else if (IS_PINEVIEW(dev
))
14072 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14074 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14076 if (INTEL_INFO(dev
)->gen
>= 9) {
14077 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14078 dev_priv
->display
.get_initial_plane_config
=
14079 skylake_get_initial_plane_config
;
14080 dev_priv
->display
.crtc_compute_clock
=
14081 haswell_crtc_compute_clock
;
14082 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14083 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14084 dev_priv
->display
.off
= ironlake_crtc_off
;
14085 dev_priv
->display
.update_primary_plane
=
14086 skylake_update_primary_plane
;
14087 } else if (HAS_DDI(dev
)) {
14088 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14089 dev_priv
->display
.get_initial_plane_config
=
14090 ironlake_get_initial_plane_config
;
14091 dev_priv
->display
.crtc_compute_clock
=
14092 haswell_crtc_compute_clock
;
14093 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14094 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14095 dev_priv
->display
.off
= ironlake_crtc_off
;
14096 dev_priv
->display
.update_primary_plane
=
14097 ironlake_update_primary_plane
;
14098 } else if (HAS_PCH_SPLIT(dev
)) {
14099 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14100 dev_priv
->display
.get_initial_plane_config
=
14101 ironlake_get_initial_plane_config
;
14102 dev_priv
->display
.crtc_compute_clock
=
14103 ironlake_crtc_compute_clock
;
14104 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14105 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14106 dev_priv
->display
.off
= ironlake_crtc_off
;
14107 dev_priv
->display
.update_primary_plane
=
14108 ironlake_update_primary_plane
;
14109 } else if (IS_VALLEYVIEW(dev
)) {
14110 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14111 dev_priv
->display
.get_initial_plane_config
=
14112 i9xx_get_initial_plane_config
;
14113 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14114 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14115 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14116 dev_priv
->display
.off
= i9xx_crtc_off
;
14117 dev_priv
->display
.update_primary_plane
=
14118 i9xx_update_primary_plane
;
14120 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14121 dev_priv
->display
.get_initial_plane_config
=
14122 i9xx_get_initial_plane_config
;
14123 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14124 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14125 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14126 dev_priv
->display
.off
= i9xx_crtc_off
;
14127 dev_priv
->display
.update_primary_plane
=
14128 i9xx_update_primary_plane
;
14131 /* Returns the core display clock speed */
14132 if (IS_SKYLAKE(dev
))
14133 dev_priv
->display
.get_display_clock_speed
=
14134 skylake_get_display_clock_speed
;
14135 else if (IS_BROADWELL(dev
))
14136 dev_priv
->display
.get_display_clock_speed
=
14137 broadwell_get_display_clock_speed
;
14138 else if (IS_HASWELL(dev
))
14139 dev_priv
->display
.get_display_clock_speed
=
14140 haswell_get_display_clock_speed
;
14141 else if (IS_VALLEYVIEW(dev
))
14142 dev_priv
->display
.get_display_clock_speed
=
14143 valleyview_get_display_clock_speed
;
14144 else if (IS_GEN5(dev
))
14145 dev_priv
->display
.get_display_clock_speed
=
14146 ilk_get_display_clock_speed
;
14147 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14148 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
14149 dev_priv
->display
.get_display_clock_speed
=
14150 i945_get_display_clock_speed
;
14151 else if (IS_I915G(dev
))
14152 dev_priv
->display
.get_display_clock_speed
=
14153 i915_get_display_clock_speed
;
14154 else if (IS_I945GM(dev
) || IS_845G(dev
))
14155 dev_priv
->display
.get_display_clock_speed
=
14156 i9xx_misc_get_display_clock_speed
;
14157 else if (IS_PINEVIEW(dev
))
14158 dev_priv
->display
.get_display_clock_speed
=
14159 pnv_get_display_clock_speed
;
14160 else if (IS_I915GM(dev
))
14161 dev_priv
->display
.get_display_clock_speed
=
14162 i915gm_get_display_clock_speed
;
14163 else if (IS_I865G(dev
))
14164 dev_priv
->display
.get_display_clock_speed
=
14165 i865_get_display_clock_speed
;
14166 else if (IS_I85X(dev
))
14167 dev_priv
->display
.get_display_clock_speed
=
14168 i855_get_display_clock_speed
;
14169 else /* 852, 830 */
14170 dev_priv
->display
.get_display_clock_speed
=
14171 i830_get_display_clock_speed
;
14173 if (IS_GEN5(dev
)) {
14174 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14175 } else if (IS_GEN6(dev
)) {
14176 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14177 } else if (IS_IVYBRIDGE(dev
)) {
14178 /* FIXME: detect B0+ stepping and use auto training */
14179 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14180 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14181 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14182 } else if (IS_VALLEYVIEW(dev
)) {
14183 dev_priv
->display
.modeset_global_resources
=
14184 valleyview_modeset_global_resources
;
14185 } else if (IS_BROXTON(dev
)) {
14186 dev_priv
->display
.modeset_global_resources
=
14187 broxton_modeset_global_resources
;
14190 switch (INTEL_INFO(dev
)->gen
) {
14192 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14196 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14201 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14205 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14208 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14209 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14212 /* Drop through - unsupported since execlist only. */
14214 /* Default just returns -ENODEV to indicate unsupported */
14215 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14218 intel_panel_init_backlight_funcs(dev
);
14220 mutex_init(&dev_priv
->pps_mutex
);
14224 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14225 * resume, or other times. This quirk makes sure that's the case for
14226 * affected systems.
14228 static void quirk_pipea_force(struct drm_device
*dev
)
14230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14232 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14233 DRM_INFO("applying pipe a force quirk\n");
14236 static void quirk_pipeb_force(struct drm_device
*dev
)
14238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14240 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14241 DRM_INFO("applying pipe b force quirk\n");
14245 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14247 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14250 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14251 DRM_INFO("applying lvds SSC disable quirk\n");
14255 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14258 static void quirk_invert_brightness(struct drm_device
*dev
)
14260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14261 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14262 DRM_INFO("applying inverted panel brightness quirk\n");
14265 /* Some VBT's incorrectly indicate no backlight is present */
14266 static void quirk_backlight_present(struct drm_device
*dev
)
14268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14269 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14270 DRM_INFO("applying backlight present quirk\n");
14273 struct intel_quirk
{
14275 int subsystem_vendor
;
14276 int subsystem_device
;
14277 void (*hook
)(struct drm_device
*dev
);
14280 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14281 struct intel_dmi_quirk
{
14282 void (*hook
)(struct drm_device
*dev
);
14283 const struct dmi_system_id (*dmi_id_list
)[];
14286 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14288 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14292 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14294 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14296 .callback
= intel_dmi_reverse_brightness
,
14297 .ident
= "NCR Corporation",
14298 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14299 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14302 { } /* terminating entry */
14304 .hook
= quirk_invert_brightness
,
14308 static struct intel_quirk intel_quirks
[] = {
14309 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14310 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14312 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14313 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14315 /* 830 needs to leave pipe A & dpll A up */
14316 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14318 /* 830 needs to leave pipe B & dpll B up */
14319 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14321 /* Lenovo U160 cannot use SSC on LVDS */
14322 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14324 /* Sony Vaio Y cannot use SSC on LVDS */
14325 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14327 /* Acer Aspire 5734Z must invert backlight brightness */
14328 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14330 /* Acer/eMachines G725 */
14331 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14333 /* Acer/eMachines e725 */
14334 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14336 /* Acer/Packard Bell NCL20 */
14337 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14339 /* Acer Aspire 4736Z */
14340 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14342 /* Acer Aspire 5336 */
14343 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14345 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14346 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14348 /* Acer C720 Chromebook (Core i3 4005U) */
14349 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14351 /* Apple Macbook 2,1 (Core 2 T7400) */
14352 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14354 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14355 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14357 /* HP Chromebook 14 (Celeron 2955U) */
14358 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14360 /* Dell Chromebook 11 */
14361 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14364 static void intel_init_quirks(struct drm_device
*dev
)
14366 struct pci_dev
*d
= dev
->pdev
;
14369 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14370 struct intel_quirk
*q
= &intel_quirks
[i
];
14372 if (d
->device
== q
->device
&&
14373 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14374 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14375 (d
->subsystem_device
== q
->subsystem_device
||
14376 q
->subsystem_device
== PCI_ANY_ID
))
14379 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14380 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14381 intel_dmi_quirks
[i
].hook(dev
);
14385 /* Disable the VGA plane that we never use */
14386 static void i915_disable_vga(struct drm_device
*dev
)
14388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14390 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14392 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14393 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14394 outb(SR01
, VGA_SR_INDEX
);
14395 sr1
= inb(VGA_SR_DATA
);
14396 outb(sr1
| 1<<5, VGA_SR_DATA
);
14397 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14400 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14401 POSTING_READ(vga_reg
);
14404 void intel_modeset_init_hw(struct drm_device
*dev
)
14406 intel_prepare_ddi(dev
);
14408 if (IS_VALLEYVIEW(dev
))
14409 vlv_update_cdclk(dev
);
14411 intel_init_clock_gating(dev
);
14413 intel_enable_gt_powersave(dev
);
14416 void intel_modeset_init(struct drm_device
*dev
)
14418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14421 struct intel_crtc
*crtc
;
14423 drm_mode_config_init(dev
);
14425 dev
->mode_config
.min_width
= 0;
14426 dev
->mode_config
.min_height
= 0;
14428 dev
->mode_config
.preferred_depth
= 24;
14429 dev
->mode_config
.prefer_shadow
= 1;
14431 dev
->mode_config
.allow_fb_modifiers
= true;
14433 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14435 intel_init_quirks(dev
);
14437 intel_init_pm(dev
);
14439 if (INTEL_INFO(dev
)->num_pipes
== 0)
14442 intel_init_display(dev
);
14443 intel_init_audio(dev
);
14445 if (IS_GEN2(dev
)) {
14446 dev
->mode_config
.max_width
= 2048;
14447 dev
->mode_config
.max_height
= 2048;
14448 } else if (IS_GEN3(dev
)) {
14449 dev
->mode_config
.max_width
= 4096;
14450 dev
->mode_config
.max_height
= 4096;
14452 dev
->mode_config
.max_width
= 8192;
14453 dev
->mode_config
.max_height
= 8192;
14456 if (IS_845G(dev
) || IS_I865G(dev
)) {
14457 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14458 dev
->mode_config
.cursor_height
= 1023;
14459 } else if (IS_GEN2(dev
)) {
14460 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14461 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14463 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14464 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14467 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14469 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14470 INTEL_INFO(dev
)->num_pipes
,
14471 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14473 for_each_pipe(dev_priv
, pipe
) {
14474 intel_crtc_init(dev
, pipe
);
14475 for_each_sprite(dev_priv
, pipe
, sprite
) {
14476 ret
= intel_plane_init(dev
, pipe
, sprite
);
14478 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14479 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14483 intel_init_dpio(dev
);
14485 intel_shared_dpll_init(dev
);
14487 /* Just disable it once at startup */
14488 i915_disable_vga(dev
);
14489 intel_setup_outputs(dev
);
14491 /* Just in case the BIOS is doing something questionable. */
14492 intel_fbc_disable(dev
);
14494 drm_modeset_lock_all(dev
);
14495 intel_modeset_setup_hw_state(dev
, false);
14496 drm_modeset_unlock_all(dev
);
14498 for_each_intel_crtc(dev
, crtc
) {
14503 * Note that reserving the BIOS fb up front prevents us
14504 * from stuffing other stolen allocations like the ring
14505 * on top. This prevents some ugliness at boot time, and
14506 * can even allow for smooth boot transitions if the BIOS
14507 * fb is large enough for the active pipe configuration.
14509 if (dev_priv
->display
.get_initial_plane_config
) {
14510 dev_priv
->display
.get_initial_plane_config(crtc
,
14511 &crtc
->plane_config
);
14513 * If the fb is shared between multiple heads, we'll
14514 * just get the first one.
14516 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
14521 static void intel_enable_pipe_a(struct drm_device
*dev
)
14523 struct intel_connector
*connector
;
14524 struct drm_connector
*crt
= NULL
;
14525 struct intel_load_detect_pipe load_detect_temp
;
14526 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14528 /* We can't just switch on the pipe A, we need to set things up with a
14529 * proper mode and output configuration. As a gross hack, enable pipe A
14530 * by enabling the load detect pipe once. */
14531 for_each_intel_connector(dev
, connector
) {
14532 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14533 crt
= &connector
->base
;
14541 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14542 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14546 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14548 struct drm_device
*dev
= crtc
->base
.dev
;
14549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14552 if (INTEL_INFO(dev
)->num_pipes
== 1)
14555 reg
= DSPCNTR(!crtc
->plane
);
14556 val
= I915_READ(reg
);
14558 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14559 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14565 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14567 struct drm_device
*dev
= crtc
->base
.dev
;
14568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14571 /* Clear any frame start delays used for debugging left by the BIOS */
14572 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14573 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14575 /* restore vblank interrupts to correct state */
14576 drm_crtc_vblank_reset(&crtc
->base
);
14577 if (crtc
->active
) {
14578 update_scanline_offset(crtc
);
14579 drm_crtc_vblank_on(&crtc
->base
);
14582 /* We need to sanitize the plane -> pipe mapping first because this will
14583 * disable the crtc (and hence change the state) if it is wrong. Note
14584 * that gen4+ has a fixed plane -> pipe mapping. */
14585 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14586 struct intel_connector
*connector
;
14589 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14590 crtc
->base
.base
.id
);
14592 /* Pipe has the wrong plane attached and the plane is active.
14593 * Temporarily change the plane mapping and disable everything
14595 plane
= crtc
->plane
;
14596 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
14597 crtc
->plane
= !plane
;
14598 intel_crtc_disable_planes(&crtc
->base
);
14599 dev_priv
->display
.crtc_disable(&crtc
->base
);
14600 crtc
->plane
= plane
;
14602 /* ... and break all links. */
14603 for_each_intel_connector(dev
, connector
) {
14604 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14607 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14608 connector
->base
.encoder
= NULL
;
14610 /* multiple connectors may have the same encoder:
14611 * handle them and break crtc link separately */
14612 for_each_intel_connector(dev
, connector
)
14613 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14614 connector
->encoder
->base
.crtc
= NULL
;
14615 connector
->encoder
->connectors_active
= false;
14618 WARN_ON(crtc
->active
);
14619 crtc
->base
.state
->enable
= false;
14620 crtc
->base
.state
->active
= false;
14621 crtc
->base
.enabled
= false;
14624 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14625 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14626 /* BIOS forgot to enable pipe A, this mostly happens after
14627 * resume. Force-enable the pipe to fix this, the update_dpms
14628 * call below we restore the pipe to the right state, but leave
14629 * the required bits on. */
14630 intel_enable_pipe_a(dev
);
14633 /* Adjust the state of the output pipe according to whether we
14634 * have active connectors/encoders. */
14635 intel_crtc_update_dpms(&crtc
->base
);
14637 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14638 struct intel_encoder
*encoder
;
14640 /* This can happen either due to bugs in the get_hw_state
14641 * functions or because the pipe is force-enabled due to the
14643 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14644 crtc
->base
.base
.id
,
14645 crtc
->base
.state
->enable
? "enabled" : "disabled",
14646 crtc
->active
? "enabled" : "disabled");
14648 crtc
->base
.state
->enable
= crtc
->active
;
14649 crtc
->base
.state
->active
= crtc
->active
;
14650 crtc
->base
.enabled
= crtc
->active
;
14652 /* Because we only establish the connector -> encoder ->
14653 * crtc links if something is active, this means the
14654 * crtc is now deactivated. Break the links. connector
14655 * -> encoder links are only establish when things are
14656 * actually up, hence no need to break them. */
14657 WARN_ON(crtc
->active
);
14659 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14660 WARN_ON(encoder
->connectors_active
);
14661 encoder
->base
.crtc
= NULL
;
14665 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14667 * We start out with underrun reporting disabled to avoid races.
14668 * For correct bookkeeping mark this on active crtcs.
14670 * Also on gmch platforms we dont have any hardware bits to
14671 * disable the underrun reporting. Which means we need to start
14672 * out with underrun reporting disabled also on inactive pipes,
14673 * since otherwise we'll complain about the garbage we read when
14674 * e.g. coming up after runtime pm.
14676 * No protection against concurrent access is required - at
14677 * worst a fifo underrun happens which also sets this to false.
14679 crtc
->cpu_fifo_underrun_disabled
= true;
14680 crtc
->pch_fifo_underrun_disabled
= true;
14684 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14686 struct intel_connector
*connector
;
14687 struct drm_device
*dev
= encoder
->base
.dev
;
14689 /* We need to check both for a crtc link (meaning that the
14690 * encoder is active and trying to read from a pipe) and the
14691 * pipe itself being active. */
14692 bool has_active_crtc
= encoder
->base
.crtc
&&
14693 to_intel_crtc(encoder
->base
.crtc
)->active
;
14695 if (encoder
->connectors_active
&& !has_active_crtc
) {
14696 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14697 encoder
->base
.base
.id
,
14698 encoder
->base
.name
);
14700 /* Connector is active, but has no active pipe. This is
14701 * fallout from our resume register restoring. Disable
14702 * the encoder manually again. */
14703 if (encoder
->base
.crtc
) {
14704 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14705 encoder
->base
.base
.id
,
14706 encoder
->base
.name
);
14707 encoder
->disable(encoder
);
14708 if (encoder
->post_disable
)
14709 encoder
->post_disable(encoder
);
14711 encoder
->base
.crtc
= NULL
;
14712 encoder
->connectors_active
= false;
14714 /* Inconsistent output/port/pipe state happens presumably due to
14715 * a bug in one of the get_hw_state functions. Or someplace else
14716 * in our code, like the register restore mess on resume. Clamp
14717 * things to off as a safer default. */
14718 for_each_intel_connector(dev
, connector
) {
14719 if (connector
->encoder
!= encoder
)
14721 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14722 connector
->base
.encoder
= NULL
;
14725 /* Enabled encoders without active connectors will be fixed in
14726 * the crtc fixup. */
14729 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14732 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14734 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14735 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14736 i915_disable_vga(dev
);
14740 void i915_redisable_vga(struct drm_device
*dev
)
14742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14744 /* This function can be called both from intel_modeset_setup_hw_state or
14745 * at a very early point in our resume sequence, where the power well
14746 * structures are not yet restored. Since this function is at a very
14747 * paranoid "someone might have enabled VGA while we were not looking"
14748 * level, just check if the power well is enabled instead of trying to
14749 * follow the "don't touch the power well if we don't need it" policy
14750 * the rest of the driver uses. */
14751 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14754 i915_redisable_vga_power_on(dev
);
14757 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14759 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14764 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
14767 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14771 struct intel_crtc
*crtc
;
14772 struct intel_encoder
*encoder
;
14773 struct intel_connector
*connector
;
14776 for_each_intel_crtc(dev
, crtc
) {
14777 struct drm_plane
*primary
= crtc
->base
.primary
;
14778 struct intel_plane_state
*plane_state
;
14780 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
14782 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
14784 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
14787 crtc
->base
.state
->enable
= crtc
->active
;
14788 crtc
->base
.state
->active
= crtc
->active
;
14789 crtc
->base
.enabled
= crtc
->active
;
14791 plane_state
= to_intel_plane_state(primary
->state
);
14792 plane_state
->visible
= primary_get_hw_state(crtc
);
14794 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14795 crtc
->base
.base
.id
,
14796 crtc
->active
? "enabled" : "disabled");
14799 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14800 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14802 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
14803 &pll
->config
.hw_state
);
14805 pll
->config
.crtc_mask
= 0;
14806 for_each_intel_crtc(dev
, crtc
) {
14807 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
14809 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
14813 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14814 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
14816 if (pll
->config
.crtc_mask
)
14817 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
14820 for_each_intel_encoder(dev
, encoder
) {
14823 if (encoder
->get_hw_state(encoder
, &pipe
)) {
14824 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14825 encoder
->base
.crtc
= &crtc
->base
;
14826 encoder
->get_config(encoder
, crtc
->config
);
14828 encoder
->base
.crtc
= NULL
;
14831 encoder
->connectors_active
= false;
14832 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14833 encoder
->base
.base
.id
,
14834 encoder
->base
.name
,
14835 encoder
->base
.crtc
? "enabled" : "disabled",
14839 for_each_intel_connector(dev
, connector
) {
14840 if (connector
->get_hw_state(connector
)) {
14841 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
14842 connector
->encoder
->connectors_active
= true;
14843 connector
->base
.encoder
= &connector
->encoder
->base
;
14845 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14846 connector
->base
.encoder
= NULL
;
14848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14849 connector
->base
.base
.id
,
14850 connector
->base
.name
,
14851 connector
->base
.encoder
? "enabled" : "disabled");
14855 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14856 * and i915 state tracking structures. */
14857 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
14858 bool force_restore
)
14860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14862 struct intel_crtc
*crtc
;
14863 struct intel_encoder
*encoder
;
14866 intel_modeset_readout_hw_state(dev
);
14869 * Now that we have the config, copy it to each CRTC struct
14870 * Note that this could go away if we move to using crtc_config
14871 * checking everywhere.
14873 for_each_intel_crtc(dev
, crtc
) {
14874 if (crtc
->active
&& i915
.fastboot
) {
14875 intel_mode_from_pipe_config(&crtc
->base
.mode
,
14877 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14878 crtc
->base
.base
.id
);
14879 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
14883 /* HW state is read out, now we need to sanitize this mess. */
14884 for_each_intel_encoder(dev
, encoder
) {
14885 intel_sanitize_encoder(encoder
);
14888 for_each_pipe(dev_priv
, pipe
) {
14889 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14890 intel_sanitize_crtc(crtc
);
14891 intel_dump_pipe_config(crtc
, crtc
->config
,
14892 "[setup_hw_state]");
14895 intel_modeset_update_connector_atomic_state(dev
);
14897 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14898 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14900 if (!pll
->on
|| pll
->active
)
14903 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
14905 pll
->disable(dev_priv
, pll
);
14910 skl_wm_get_hw_state(dev
);
14911 else if (HAS_PCH_SPLIT(dev
))
14912 ilk_wm_get_hw_state(dev
);
14914 if (force_restore
) {
14915 i915_redisable_vga(dev
);
14918 * We need to use raw interfaces for restoring state to avoid
14919 * checking (bogus) intermediate states.
14921 for_each_pipe(dev_priv
, pipe
) {
14922 struct drm_crtc
*crtc
=
14923 dev_priv
->pipe_to_crtc_mapping
[pipe
];
14925 intel_crtc_restore_mode(crtc
);
14928 intel_modeset_update_staged_output_state(dev
);
14931 intel_modeset_check_state(dev
);
14934 void intel_modeset_gem_init(struct drm_device
*dev
)
14936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14937 struct drm_crtc
*c
;
14938 struct drm_i915_gem_object
*obj
;
14941 mutex_lock(&dev
->struct_mutex
);
14942 intel_init_gt_powersave(dev
);
14943 mutex_unlock(&dev
->struct_mutex
);
14946 * There may be no VBT; and if the BIOS enabled SSC we can
14947 * just keep using it to avoid unnecessary flicker. Whereas if the
14948 * BIOS isn't using it, don't assume it will work even if the VBT
14949 * indicates as much.
14951 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
14952 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14955 intel_modeset_init_hw(dev
);
14957 intel_setup_overlay(dev
);
14960 * Make sure any fbs we allocated at startup are properly
14961 * pinned & fenced. When we do the allocation it's too early
14964 for_each_crtc(dev
, c
) {
14965 obj
= intel_fb_obj(c
->primary
->fb
);
14969 mutex_lock(&dev
->struct_mutex
);
14970 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
14974 mutex_unlock(&dev
->struct_mutex
);
14976 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14977 to_intel_crtc(c
)->pipe
);
14978 drm_framebuffer_unreference(c
->primary
->fb
);
14979 c
->primary
->fb
= NULL
;
14980 update_state_fb(c
->primary
);
14984 intel_backlight_register(dev
);
14987 void intel_connector_unregister(struct intel_connector
*intel_connector
)
14989 struct drm_connector
*connector
= &intel_connector
->base
;
14991 intel_panel_destroy_backlight(connector
);
14992 drm_connector_unregister(connector
);
14995 void intel_modeset_cleanup(struct drm_device
*dev
)
14997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14998 struct drm_connector
*connector
;
15000 intel_disable_gt_powersave(dev
);
15002 intel_backlight_unregister(dev
);
15005 * Interrupts and polling as the first thing to avoid creating havoc.
15006 * Too much stuff here (turning of connectors, ...) would
15007 * experience fancy races otherwise.
15009 intel_irq_uninstall(dev_priv
);
15012 * Due to the hpd irq storm handling the hotplug work can re-arm the
15013 * poll handlers. Hence disable polling after hpd handling is shut down.
15015 drm_kms_helper_poll_fini(dev
);
15017 mutex_lock(&dev
->struct_mutex
);
15019 intel_unregister_dsm_handler();
15021 intel_fbc_disable(dev
);
15023 mutex_unlock(&dev
->struct_mutex
);
15025 /* flush any delayed tasks or pending work */
15026 flush_scheduled_work();
15028 /* destroy the backlight and sysfs files before encoders/connectors */
15029 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15030 struct intel_connector
*intel_connector
;
15032 intel_connector
= to_intel_connector(connector
);
15033 intel_connector
->unregister(intel_connector
);
15036 drm_mode_config_cleanup(dev
);
15038 intel_cleanup_overlay(dev
);
15040 mutex_lock(&dev
->struct_mutex
);
15041 intel_cleanup_gt_powersave(dev
);
15042 mutex_unlock(&dev
->struct_mutex
);
15046 * Return which encoder is currently attached for connector.
15048 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15050 return &intel_attached_encoder(connector
)->base
;
15053 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15054 struct intel_encoder
*encoder
)
15056 connector
->encoder
= encoder
;
15057 drm_mode_connector_attach_encoder(&connector
->base
,
15062 * set vga decode state - true == enable VGA decode
15064 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15067 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15070 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15071 DRM_ERROR("failed to read control word\n");
15075 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15079 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15081 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15083 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15084 DRM_ERROR("failed to write control word\n");
15091 struct intel_display_error_state
{
15093 u32 power_well_driver
;
15095 int num_transcoders
;
15097 struct intel_cursor_error_state
{
15102 } cursor
[I915_MAX_PIPES
];
15104 struct intel_pipe_error_state
{
15105 bool power_domain_on
;
15108 } pipe
[I915_MAX_PIPES
];
15110 struct intel_plane_error_state
{
15118 } plane
[I915_MAX_PIPES
];
15120 struct intel_transcoder_error_state
{
15121 bool power_domain_on
;
15122 enum transcoder cpu_transcoder
;
15135 struct intel_display_error_state
*
15136 intel_display_capture_error_state(struct drm_device
*dev
)
15138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15139 struct intel_display_error_state
*error
;
15140 int transcoders
[] = {
15148 if (INTEL_INFO(dev
)->num_pipes
== 0)
15151 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15155 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15156 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15158 for_each_pipe(dev_priv
, i
) {
15159 error
->pipe
[i
].power_domain_on
=
15160 __intel_display_power_is_enabled(dev_priv
,
15161 POWER_DOMAIN_PIPE(i
));
15162 if (!error
->pipe
[i
].power_domain_on
)
15165 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15166 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15167 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15169 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15170 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15171 if (INTEL_INFO(dev
)->gen
<= 3) {
15172 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15173 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15175 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15176 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15177 if (INTEL_INFO(dev
)->gen
>= 4) {
15178 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15179 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15182 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15184 if (HAS_GMCH_DISPLAY(dev
))
15185 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15188 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15189 if (HAS_DDI(dev_priv
->dev
))
15190 error
->num_transcoders
++; /* Account for eDP. */
15192 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15193 enum transcoder cpu_transcoder
= transcoders
[i
];
15195 error
->transcoder
[i
].power_domain_on
=
15196 __intel_display_power_is_enabled(dev_priv
,
15197 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15198 if (!error
->transcoder
[i
].power_domain_on
)
15201 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15203 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15204 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15205 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15206 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15207 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15208 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15209 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15215 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15218 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15219 struct drm_device
*dev
,
15220 struct intel_display_error_state
*error
)
15222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15228 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15229 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15230 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15231 error
->power_well_driver
);
15232 for_each_pipe(dev_priv
, i
) {
15233 err_printf(m
, "Pipe [%d]:\n", i
);
15234 err_printf(m
, " Power: %s\n",
15235 error
->pipe
[i
].power_domain_on
? "on" : "off");
15236 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15237 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15239 err_printf(m
, "Plane [%d]:\n", i
);
15240 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15241 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15242 if (INTEL_INFO(dev
)->gen
<= 3) {
15243 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15244 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15246 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15247 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15248 if (INTEL_INFO(dev
)->gen
>= 4) {
15249 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15250 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15253 err_printf(m
, "Cursor [%d]:\n", i
);
15254 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15255 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15256 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15259 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15260 err_printf(m
, "CPU transcoder: %c\n",
15261 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15262 err_printf(m
, " Power: %s\n",
15263 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15264 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15265 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15266 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15267 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15268 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15269 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15270 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15274 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15276 struct intel_crtc
*crtc
;
15278 for_each_intel_crtc(dev
, crtc
) {
15279 struct intel_unpin_work
*work
;
15281 spin_lock_irq(&dev
->event_lock
);
15283 work
= crtc
->unpin_work
;
15285 if (work
&& work
->event
&&
15286 work
->event
->base
.file_priv
== file
) {
15287 kfree(work
->event
);
15288 work
->event
= NULL
;
15291 spin_unlock_irq(&dev
->event_lock
);