2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats
[] = {
62 DRM_FORMAT_XRGB2101010
,
63 DRM_FORMAT_XBGR2101010
,
66 static const uint32_t skl_primary_formats
[] = {
73 DRM_FORMAT_XRGB2101010
,
74 DRM_FORMAT_XBGR2101010
,
78 static const uint32_t intel_cursor_formats
[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
84 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
85 struct intel_crtc_state
*pipe_config
);
86 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
87 struct intel_crtc_state
*pipe_config
);
89 static int intel_set_mode(struct drm_crtc
*crtc
,
90 struct drm_atomic_state
*state
);
91 static int intel_framebuffer_init(struct drm_device
*dev
,
92 struct intel_framebuffer
*ifb
,
93 struct drm_mode_fb_cmd2
*mode_cmd
,
94 struct drm_i915_gem_object
*obj
);
95 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
96 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
98 struct intel_link_m_n
*m_n
,
99 struct intel_link_m_n
*m2_n2
);
100 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
101 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
102 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
103 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
104 const struct intel_crtc_state
*pipe_config
);
105 static void chv_prepare_pll(struct intel_crtc
*crtc
,
106 const struct intel_crtc_state
*pipe_config
);
107 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
108 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
109 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
110 struct intel_crtc_state
*crtc_state
);
111 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
113 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
);
114 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
);
116 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
118 if (!connector
->mst_port
)
119 return connector
->encoder
;
121 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
130 int p2_slow
, p2_fast
;
133 typedef struct intel_limit intel_limit_t
;
135 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
140 intel_pch_rawclk(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 WARN_ON(!HAS_PCH_SPLIT(dev
));
146 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
149 static inline u32
/* units of 100MHz */
150 intel_fdi_link_freq(struct drm_device
*dev
)
153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
154 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
159 static const intel_limit_t intel_limits_i8xx_dac
= {
160 .dot
= { .min
= 25000, .max
= 350000 },
161 .vco
= { .min
= 908000, .max
= 1512000 },
162 .n
= { .min
= 2, .max
= 16 },
163 .m
= { .min
= 96, .max
= 140 },
164 .m1
= { .min
= 18, .max
= 26 },
165 .m2
= { .min
= 6, .max
= 16 },
166 .p
= { .min
= 4, .max
= 128 },
167 .p1
= { .min
= 2, .max
= 33 },
168 .p2
= { .dot_limit
= 165000,
169 .p2_slow
= 4, .p2_fast
= 2 },
172 static const intel_limit_t intel_limits_i8xx_dvo
= {
173 .dot
= { .min
= 25000, .max
= 350000 },
174 .vco
= { .min
= 908000, .max
= 1512000 },
175 .n
= { .min
= 2, .max
= 16 },
176 .m
= { .min
= 96, .max
= 140 },
177 .m1
= { .min
= 18, .max
= 26 },
178 .m2
= { .min
= 6, .max
= 16 },
179 .p
= { .min
= 4, .max
= 128 },
180 .p1
= { .min
= 2, .max
= 33 },
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 4, .p2_fast
= 4 },
185 static const intel_limit_t intel_limits_i8xx_lvds
= {
186 .dot
= { .min
= 25000, .max
= 350000 },
187 .vco
= { .min
= 908000, .max
= 1512000 },
188 .n
= { .min
= 2, .max
= 16 },
189 .m
= { .min
= 96, .max
= 140 },
190 .m1
= { .min
= 18, .max
= 26 },
191 .m2
= { .min
= 6, .max
= 16 },
192 .p
= { .min
= 4, .max
= 128 },
193 .p1
= { .min
= 1, .max
= 6 },
194 .p2
= { .dot_limit
= 165000,
195 .p2_slow
= 14, .p2_fast
= 7 },
198 static const intel_limit_t intel_limits_i9xx_sdvo
= {
199 .dot
= { .min
= 20000, .max
= 400000 },
200 .vco
= { .min
= 1400000, .max
= 2800000 },
201 .n
= { .min
= 1, .max
= 6 },
202 .m
= { .min
= 70, .max
= 120 },
203 .m1
= { .min
= 8, .max
= 18 },
204 .m2
= { .min
= 3, .max
= 7 },
205 .p
= { .min
= 5, .max
= 80 },
206 .p1
= { .min
= 1, .max
= 8 },
207 .p2
= { .dot_limit
= 200000,
208 .p2_slow
= 10, .p2_fast
= 5 },
211 static const intel_limit_t intel_limits_i9xx_lvds
= {
212 .dot
= { .min
= 20000, .max
= 400000 },
213 .vco
= { .min
= 1400000, .max
= 2800000 },
214 .n
= { .min
= 1, .max
= 6 },
215 .m
= { .min
= 70, .max
= 120 },
216 .m1
= { .min
= 8, .max
= 18 },
217 .m2
= { .min
= 3, .max
= 7 },
218 .p
= { .min
= 7, .max
= 98 },
219 .p1
= { .min
= 1, .max
= 8 },
220 .p2
= { .dot_limit
= 112000,
221 .p2_slow
= 14, .p2_fast
= 7 },
225 static const intel_limit_t intel_limits_g4x_sdvo
= {
226 .dot
= { .min
= 25000, .max
= 270000 },
227 .vco
= { .min
= 1750000, .max
= 3500000},
228 .n
= { .min
= 1, .max
= 4 },
229 .m
= { .min
= 104, .max
= 138 },
230 .m1
= { .min
= 17, .max
= 23 },
231 .m2
= { .min
= 5, .max
= 11 },
232 .p
= { .min
= 10, .max
= 30 },
233 .p1
= { .min
= 1, .max
= 3},
234 .p2
= { .dot_limit
= 270000,
240 static const intel_limit_t intel_limits_g4x_hdmi
= {
241 .dot
= { .min
= 22000, .max
= 400000 },
242 .vco
= { .min
= 1750000, .max
= 3500000},
243 .n
= { .min
= 1, .max
= 4 },
244 .m
= { .min
= 104, .max
= 138 },
245 .m1
= { .min
= 16, .max
= 23 },
246 .m2
= { .min
= 5, .max
= 11 },
247 .p
= { .min
= 5, .max
= 80 },
248 .p1
= { .min
= 1, .max
= 8},
249 .p2
= { .dot_limit
= 165000,
250 .p2_slow
= 10, .p2_fast
= 5 },
253 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
254 .dot
= { .min
= 20000, .max
= 115000 },
255 .vco
= { .min
= 1750000, .max
= 3500000 },
256 .n
= { .min
= 1, .max
= 3 },
257 .m
= { .min
= 104, .max
= 138 },
258 .m1
= { .min
= 17, .max
= 23 },
259 .m2
= { .min
= 5, .max
= 11 },
260 .p
= { .min
= 28, .max
= 112 },
261 .p1
= { .min
= 2, .max
= 8 },
262 .p2
= { .dot_limit
= 0,
263 .p2_slow
= 14, .p2_fast
= 14
267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
268 .dot
= { .min
= 80000, .max
= 224000 },
269 .vco
= { .min
= 1750000, .max
= 3500000 },
270 .n
= { .min
= 1, .max
= 3 },
271 .m
= { .min
= 104, .max
= 138 },
272 .m1
= { .min
= 17, .max
= 23 },
273 .m2
= { .min
= 5, .max
= 11 },
274 .p
= { .min
= 14, .max
= 42 },
275 .p1
= { .min
= 2, .max
= 6 },
276 .p2
= { .dot_limit
= 0,
277 .p2_slow
= 7, .p2_fast
= 7
281 static const intel_limit_t intel_limits_pineview_sdvo
= {
282 .dot
= { .min
= 20000, .max
= 400000},
283 .vco
= { .min
= 1700000, .max
= 3500000 },
284 /* Pineview's Ncounter is a ring counter */
285 .n
= { .min
= 3, .max
= 6 },
286 .m
= { .min
= 2, .max
= 256 },
287 /* Pineview only has one combined m divider, which we treat as m2. */
288 .m1
= { .min
= 0, .max
= 0 },
289 .m2
= { .min
= 0, .max
= 254 },
290 .p
= { .min
= 5, .max
= 80 },
291 .p1
= { .min
= 1, .max
= 8 },
292 .p2
= { .dot_limit
= 200000,
293 .p2_slow
= 10, .p2_fast
= 5 },
296 static const intel_limit_t intel_limits_pineview_lvds
= {
297 .dot
= { .min
= 20000, .max
= 400000 },
298 .vco
= { .min
= 1700000, .max
= 3500000 },
299 .n
= { .min
= 3, .max
= 6 },
300 .m
= { .min
= 2, .max
= 256 },
301 .m1
= { .min
= 0, .max
= 0 },
302 .m2
= { .min
= 0, .max
= 254 },
303 .p
= { .min
= 7, .max
= 112 },
304 .p1
= { .min
= 1, .max
= 8 },
305 .p2
= { .dot_limit
= 112000,
306 .p2_slow
= 14, .p2_fast
= 14 },
309 /* Ironlake / Sandybridge
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
314 static const intel_limit_t intel_limits_ironlake_dac
= {
315 .dot
= { .min
= 25000, .max
= 350000 },
316 .vco
= { .min
= 1760000, .max
= 3510000 },
317 .n
= { .min
= 1, .max
= 5 },
318 .m
= { .min
= 79, .max
= 127 },
319 .m1
= { .min
= 12, .max
= 22 },
320 .m2
= { .min
= 5, .max
= 9 },
321 .p
= { .min
= 5, .max
= 80 },
322 .p1
= { .min
= 1, .max
= 8 },
323 .p2
= { .dot_limit
= 225000,
324 .p2_slow
= 10, .p2_fast
= 5 },
327 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
328 .dot
= { .min
= 25000, .max
= 350000 },
329 .vco
= { .min
= 1760000, .max
= 3510000 },
330 .n
= { .min
= 1, .max
= 3 },
331 .m
= { .min
= 79, .max
= 118 },
332 .m1
= { .min
= 12, .max
= 22 },
333 .m2
= { .min
= 5, .max
= 9 },
334 .p
= { .min
= 28, .max
= 112 },
335 .p1
= { .min
= 2, .max
= 8 },
336 .p2
= { .dot_limit
= 225000,
337 .p2_slow
= 14, .p2_fast
= 14 },
340 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
341 .dot
= { .min
= 25000, .max
= 350000 },
342 .vco
= { .min
= 1760000, .max
= 3510000 },
343 .n
= { .min
= 1, .max
= 3 },
344 .m
= { .min
= 79, .max
= 127 },
345 .m1
= { .min
= 12, .max
= 22 },
346 .m2
= { .min
= 5, .max
= 9 },
347 .p
= { .min
= 14, .max
= 56 },
348 .p1
= { .min
= 2, .max
= 8 },
349 .p2
= { .dot_limit
= 225000,
350 .p2_slow
= 7, .p2_fast
= 7 },
353 /* LVDS 100mhz refclk limits. */
354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
355 .dot
= { .min
= 25000, .max
= 350000 },
356 .vco
= { .min
= 1760000, .max
= 3510000 },
357 .n
= { .min
= 1, .max
= 2 },
358 .m
= { .min
= 79, .max
= 126 },
359 .m1
= { .min
= 12, .max
= 22 },
360 .m2
= { .min
= 5, .max
= 9 },
361 .p
= { .min
= 28, .max
= 112 },
362 .p1
= { .min
= 2, .max
= 8 },
363 .p2
= { .dot_limit
= 225000,
364 .p2_slow
= 14, .p2_fast
= 14 },
367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
368 .dot
= { .min
= 25000, .max
= 350000 },
369 .vco
= { .min
= 1760000, .max
= 3510000 },
370 .n
= { .min
= 1, .max
= 3 },
371 .m
= { .min
= 79, .max
= 126 },
372 .m1
= { .min
= 12, .max
= 22 },
373 .m2
= { .min
= 5, .max
= 9 },
374 .p
= { .min
= 14, .max
= 42 },
375 .p1
= { .min
= 2, .max
= 6 },
376 .p2
= { .dot_limit
= 225000,
377 .p2_slow
= 7, .p2_fast
= 7 },
380 static const intel_limit_t intel_limits_vlv
= {
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
387 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
388 .vco
= { .min
= 4000000, .max
= 6000000 },
389 .n
= { .min
= 1, .max
= 7 },
390 .m1
= { .min
= 2, .max
= 3 },
391 .m2
= { .min
= 11, .max
= 156 },
392 .p1
= { .min
= 2, .max
= 3 },
393 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
396 static const intel_limit_t intel_limits_chv
= {
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
403 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
404 .vco
= { .min
= 4800000, .max
= 6480000 },
405 .n
= { .min
= 1, .max
= 1 },
406 .m1
= { .min
= 2, .max
= 2 },
407 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
408 .p1
= { .min
= 2, .max
= 4 },
409 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
412 static const intel_limit_t intel_limits_bxt
= {
413 /* FIXME: find real dot limits */
414 .dot
= { .min
= 0, .max
= INT_MAX
},
415 .vco
= { .min
= 4800000, .max
= 6480000 },
416 .n
= { .min
= 1, .max
= 1 },
417 .m1
= { .min
= 2, .max
= 2 },
418 /* FIXME: find real m2 limits */
419 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
420 .p1
= { .min
= 2, .max
= 4 },
421 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
424 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
426 clock
->m
= clock
->m1
* clock
->m2
;
427 clock
->p
= clock
->p1
* clock
->p2
;
428 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
430 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
431 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
435 * Returns whether any output on the specified pipe is of the specified type
437 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
439 struct drm_device
*dev
= crtc
->base
.dev
;
440 struct intel_encoder
*encoder
;
442 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
443 if (encoder
->type
== type
)
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
455 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
458 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
459 struct drm_connector
*connector
;
460 struct drm_connector_state
*connector_state
;
461 struct intel_encoder
*encoder
;
462 int i
, num_connectors
= 0;
464 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
465 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
470 encoder
= to_intel_encoder(connector_state
->best_encoder
);
471 if (encoder
->type
== type
)
475 WARN_ON(num_connectors
== 0);
480 static const intel_limit_t
*
481 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
483 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
484 const intel_limit_t
*limit
;
486 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
487 if (intel_is_dual_link_lvds(dev
)) {
488 if (refclk
== 100000)
489 limit
= &intel_limits_ironlake_dual_lvds_100m
;
491 limit
= &intel_limits_ironlake_dual_lvds
;
493 if (refclk
== 100000)
494 limit
= &intel_limits_ironlake_single_lvds_100m
;
496 limit
= &intel_limits_ironlake_single_lvds
;
499 limit
= &intel_limits_ironlake_dac
;
504 static const intel_limit_t
*
505 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
507 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
508 const intel_limit_t
*limit
;
510 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
511 if (intel_is_dual_link_lvds(dev
))
512 limit
= &intel_limits_g4x_dual_channel_lvds
;
514 limit
= &intel_limits_g4x_single_channel_lvds
;
515 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
516 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
517 limit
= &intel_limits_g4x_hdmi
;
518 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
519 limit
= &intel_limits_g4x_sdvo
;
520 } else /* The option is for other outputs */
521 limit
= &intel_limits_i9xx_sdvo
;
526 static const intel_limit_t
*
527 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
529 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
530 const intel_limit_t
*limit
;
533 limit
= &intel_limits_bxt
;
534 else if (HAS_PCH_SPLIT(dev
))
535 limit
= intel_ironlake_limit(crtc_state
, refclk
);
536 else if (IS_G4X(dev
)) {
537 limit
= intel_g4x_limit(crtc_state
);
538 } else if (IS_PINEVIEW(dev
)) {
539 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
540 limit
= &intel_limits_pineview_lvds
;
542 limit
= &intel_limits_pineview_sdvo
;
543 } else if (IS_CHERRYVIEW(dev
)) {
544 limit
= &intel_limits_chv
;
545 } else if (IS_VALLEYVIEW(dev
)) {
546 limit
= &intel_limits_vlv
;
547 } else if (!IS_GEN2(dev
)) {
548 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
549 limit
= &intel_limits_i9xx_lvds
;
551 limit
= &intel_limits_i9xx_sdvo
;
553 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
554 limit
= &intel_limits_i8xx_lvds
;
555 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
556 limit
= &intel_limits_i8xx_dvo
;
558 limit
= &intel_limits_i8xx_dac
;
563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
564 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
566 clock
->m
= clock
->m2
+ 2;
567 clock
->p
= clock
->p1
* clock
->p2
;
568 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
570 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
571 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
574 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
576 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
579 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
581 clock
->m
= i9xx_dpll_compute_m(clock
);
582 clock
->p
= clock
->p1
* clock
->p2
;
583 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
585 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
586 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
589 static void chv_clock(int refclk
, intel_clock_t
*clock
)
591 clock
->m
= clock
->m1
* clock
->m2
;
592 clock
->p
= clock
->p1
* clock
->p2
;
593 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
595 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
597 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
600 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
606 static bool intel_PLL_is_valid(struct drm_device
*dev
,
607 const intel_limit_t
*limit
,
608 const intel_clock_t
*clock
)
610 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
611 INTELPllInvalid("n out of range\n");
612 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
613 INTELPllInvalid("p1 out of range\n");
614 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
615 INTELPllInvalid("m2 out of range\n");
616 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
617 INTELPllInvalid("m1 out of range\n");
619 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
620 if (clock
->m1
<= clock
->m2
)
621 INTELPllInvalid("m1 <= m2\n");
623 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
624 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
625 INTELPllInvalid("p out of range\n");
626 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
627 INTELPllInvalid("m out of range\n");
630 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
635 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
636 INTELPllInvalid("dot out of range\n");
642 i9xx_find_best_dpll(const intel_limit_t
*limit
,
643 struct intel_crtc_state
*crtc_state
,
644 int target
, int refclk
, intel_clock_t
*match_clock
,
645 intel_clock_t
*best_clock
)
647 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
648 struct drm_device
*dev
= crtc
->base
.dev
;
652 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
658 if (intel_is_dual_link_lvds(dev
))
659 clock
.p2
= limit
->p2
.p2_fast
;
661 clock
.p2
= limit
->p2
.p2_slow
;
663 if (target
< limit
->p2
.dot_limit
)
664 clock
.p2
= limit
->p2
.p2_slow
;
666 clock
.p2
= limit
->p2
.p2_fast
;
669 memset(best_clock
, 0, sizeof(*best_clock
));
671 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
673 for (clock
.m2
= limit
->m2
.min
;
674 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
675 if (clock
.m2
>= clock
.m1
)
677 for (clock
.n
= limit
->n
.min
;
678 clock
.n
<= limit
->n
.max
; clock
.n
++) {
679 for (clock
.p1
= limit
->p1
.min
;
680 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
683 i9xx_clock(refclk
, &clock
);
684 if (!intel_PLL_is_valid(dev
, limit
,
688 clock
.p
!= match_clock
->p
)
691 this_err
= abs(clock
.dot
- target
);
692 if (this_err
< err
) {
701 return (err
!= target
);
705 pnv_find_best_dpll(const intel_limit_t
*limit
,
706 struct intel_crtc_state
*crtc_state
,
707 int target
, int refclk
, intel_clock_t
*match_clock
,
708 intel_clock_t
*best_clock
)
710 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
711 struct drm_device
*dev
= crtc
->base
.dev
;
715 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
734 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
736 for (clock
.m2
= limit
->m2
.min
;
737 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
738 for (clock
.n
= limit
->n
.min
;
739 clock
.n
<= limit
->n
.max
; clock
.n
++) {
740 for (clock
.p1
= limit
->p1
.min
;
741 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
744 pineview_clock(refclk
, &clock
);
745 if (!intel_PLL_is_valid(dev
, limit
,
749 clock
.p
!= match_clock
->p
)
752 this_err
= abs(clock
.dot
- target
);
753 if (this_err
< err
) {
762 return (err
!= target
);
766 g4x_find_best_dpll(const intel_limit_t
*limit
,
767 struct intel_crtc_state
*crtc_state
,
768 int target
, int refclk
, intel_clock_t
*match_clock
,
769 intel_clock_t
*best_clock
)
771 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
772 struct drm_device
*dev
= crtc
->base
.dev
;
776 /* approximately equals target * 0.00585 */
777 int err_most
= (target
>> 8) + (target
>> 9);
780 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
781 if (intel_is_dual_link_lvds(dev
))
782 clock
.p2
= limit
->p2
.p2_fast
;
784 clock
.p2
= limit
->p2
.p2_slow
;
786 if (target
< limit
->p2
.dot_limit
)
787 clock
.p2
= limit
->p2
.p2_slow
;
789 clock
.p2
= limit
->p2
.p2_fast
;
792 memset(best_clock
, 0, sizeof(*best_clock
));
793 max_n
= limit
->n
.max
;
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
796 /* based on hardware requirement, prefere larger m1,m2 */
797 for (clock
.m1
= limit
->m1
.max
;
798 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
799 for (clock
.m2
= limit
->m2
.max
;
800 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
801 for (clock
.p1
= limit
->p1
.max
;
802 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
805 i9xx_clock(refclk
, &clock
);
806 if (!intel_PLL_is_valid(dev
, limit
,
810 this_err
= abs(clock
.dot
- target
);
811 if (this_err
< err_most
) {
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
828 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
829 const intel_clock_t
*calculated_clock
,
830 const intel_clock_t
*best_clock
,
831 unsigned int best_error_ppm
,
832 unsigned int *error_ppm
)
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
838 if (IS_CHERRYVIEW(dev
)) {
841 return calculated_clock
->p
> best_clock
->p
;
844 if (WARN_ON_ONCE(!target_freq
))
847 *error_ppm
= div_u64(1000000ULL *
848 abs(target_freq
- calculated_clock
->dot
),
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
855 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
861 return *error_ppm
+ 10 < best_error_ppm
;
865 vlv_find_best_dpll(const intel_limit_t
*limit
,
866 struct intel_crtc_state
*crtc_state
,
867 int target
, int refclk
, intel_clock_t
*match_clock
,
868 intel_clock_t
*best_clock
)
870 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
871 struct drm_device
*dev
= crtc
->base
.dev
;
873 unsigned int bestppm
= 1000000;
874 /* min update 19.2 MHz */
875 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
878 target
*= 5; /* fast clock */
880 memset(best_clock
, 0, sizeof(*best_clock
));
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
884 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
885 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
886 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
887 clock
.p
= clock
.p1
* clock
.p2
;
888 /* based on hardware requirement, prefer bigger m1,m2 values */
889 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
892 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
895 vlv_clock(refclk
, &clock
);
897 if (!intel_PLL_is_valid(dev
, limit
,
901 if (!vlv_PLL_is_optimal(dev
, target
,
919 chv_find_best_dpll(const intel_limit_t
*limit
,
920 struct intel_crtc_state
*crtc_state
,
921 int target
, int refclk
, intel_clock_t
*match_clock
,
922 intel_clock_t
*best_clock
)
924 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
925 struct drm_device
*dev
= crtc
->base
.dev
;
926 unsigned int best_error_ppm
;
931 memset(best_clock
, 0, sizeof(*best_clock
));
932 best_error_ppm
= 1000000;
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
939 clock
.n
= 1, clock
.m1
= 2;
940 target
*= 5; /* fast clock */
942 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
943 for (clock
.p2
= limit
->p2
.p2_fast
;
944 clock
.p2
>= limit
->p2
.p2_slow
;
945 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
946 unsigned int error_ppm
;
948 clock
.p
= clock
.p1
* clock
.p2
;
950 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
951 clock
.n
) << 22, refclk
* clock
.m1
);
953 if (m2
> INT_MAX
/clock
.m1
)
958 chv_clock(refclk
, &clock
);
960 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
963 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
964 best_error_ppm
, &error_ppm
))
968 best_error_ppm
= error_ppm
;
976 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
977 intel_clock_t
*best_clock
)
979 int refclk
= i9xx_get_refclk(crtc_state
, 0);
981 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
982 target_clock
, refclk
, NULL
, best_clock
);
985 bool intel_crtc_active(struct drm_crtc
*crtc
)
987 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
992 * We can ditch the adjusted_mode.crtc_clock check as soon
993 * as Haswell has gained clock readout/fastboot support.
995 * We can ditch the crtc->primary->fb check as soon as we can
996 * properly reconstruct framebuffers.
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1002 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1003 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1006 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1009 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1012 return intel_crtc
->config
->cpu_transcoder
;
1015 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1018 u32 reg
= PIPEDSL(pipe
);
1023 line_mask
= DSL_LINEMASK_GEN2
;
1025 line_mask
= DSL_LINEMASK_GEN3
;
1027 line1
= I915_READ(reg
) & line_mask
;
1029 line2
= I915_READ(reg
) & line_mask
;
1031 return line1
== line2
;
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
1036 * @crtc: crtc whose pipe to wait for
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
1050 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1052 struct drm_device
*dev
= crtc
->base
.dev
;
1053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1054 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1055 enum pipe pipe
= crtc
->pipe
;
1057 if (INTEL_INFO(dev
)->gen
>= 4) {
1058 int reg
= PIPECONF(cpu_transcoder
);
1060 /* Wait for the Pipe State to go off */
1061 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1063 WARN(1, "pipe_off wait timed out\n");
1065 /* Wait for the display line to settle */
1066 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1067 WARN(1, "pipe_off wait timed out\n");
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1076 * Returns true if @port is connected, false otherwise.
1078 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1079 struct intel_digital_port
*port
)
1083 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1084 switch (port
->port
) {
1086 bit
= SDE_PORTB_HOTPLUG
;
1089 bit
= SDE_PORTC_HOTPLUG
;
1092 bit
= SDE_PORTD_HOTPLUG
;
1098 switch (port
->port
) {
1100 bit
= SDE_PORTB_HOTPLUG_CPT
;
1103 bit
= SDE_PORTC_HOTPLUG_CPT
;
1106 bit
= SDE_PORTD_HOTPLUG_CPT
;
1113 return I915_READ(SDEISR
) & bit
;
1116 static const char *state_string(bool enabled
)
1118 return enabled
? "on" : "off";
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private
*dev_priv
,
1123 enum pipe pipe
, bool state
)
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1132 I915_STATE_WARN(cur_state
!= state
,
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state
), state_string(cur_state
));
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1143 mutex_lock(&dev_priv
->sb_lock
);
1144 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1145 mutex_unlock(&dev_priv
->sb_lock
);
1147 cur_state
= val
& DSI_PLL_VCO_EN
;
1148 I915_STATE_WARN(cur_state
!= state
,
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state
), state_string(cur_state
));
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155 struct intel_shared_dpll
*
1156 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1158 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1160 if (crtc
->config
->shared_dpll
< 0)
1163 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1167 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1168 struct intel_shared_dpll
*pll
,
1172 struct intel_dpll_hw_state hw_state
;
1175 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1178 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1179 I915_STATE_WARN(cur_state
!= state
,
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll
->name
, state_string(state
), state_string(cur_state
));
1184 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1185 enum pipe pipe
, bool state
)
1190 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1193 if (HAS_DDI(dev_priv
->dev
)) {
1194 /* DDI does not have a specific FDI_TX register */
1195 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1196 val
= I915_READ(reg
);
1197 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1199 reg
= FDI_TX_CTL(pipe
);
1200 val
= I915_READ(reg
);
1201 cur_state
= !!(val
& FDI_TX_ENABLE
);
1203 I915_STATE_WARN(cur_state
!= state
,
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state
), state_string(cur_state
));
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1211 enum pipe pipe
, bool state
)
1217 reg
= FDI_RX_CTL(pipe
);
1218 val
= I915_READ(reg
);
1219 cur_state
= !!(val
& FDI_RX_ENABLE
);
1220 I915_STATE_WARN(cur_state
!= state
,
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state
), state_string(cur_state
));
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1233 /* ILK FDI PLL is always enabled */
1234 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238 if (HAS_DDI(dev_priv
->dev
))
1241 reg
= FDI_TX_CTL(pipe
);
1242 val
= I915_READ(reg
);
1243 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1246 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1247 enum pipe pipe
, bool state
)
1253 reg
= FDI_RX_CTL(pipe
);
1254 val
= I915_READ(reg
);
1255 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1256 I915_STATE_WARN(cur_state
!= state
,
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state
), state_string(cur_state
));
1261 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1264 struct drm_device
*dev
= dev_priv
->dev
;
1267 enum pipe panel_pipe
= PIPE_A
;
1270 if (WARN_ON(HAS_DDI(dev
)))
1273 if (HAS_PCH_SPLIT(dev
)) {
1276 pp_reg
= PCH_PP_CONTROL
;
1277 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1279 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1280 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1281 panel_pipe
= PIPE_B
;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev
)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1288 pp_reg
= PP_CONTROL
;
1289 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1290 panel_pipe
= PIPE_B
;
1293 val
= I915_READ(pp_reg
);
1294 if (!(val
& PANEL_POWER_ON
) ||
1295 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1298 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1299 "panel assertion failure, pipe %c regs locked\n",
1303 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1304 enum pipe pipe
, bool state
)
1306 struct drm_device
*dev
= dev_priv
->dev
;
1309 if (IS_845G(dev
) || IS_I865G(dev
))
1310 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1312 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1314 I915_STATE_WARN(cur_state
!= state
,
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321 void assert_pipe(struct drm_i915_private
*dev_priv
,
1322 enum pipe pipe
, bool state
)
1327 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1332 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1335 if (!intel_display_power_is_enabled(dev_priv
,
1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1339 reg
= PIPECONF(cpu_transcoder
);
1340 val
= I915_READ(reg
);
1341 cur_state
= !!(val
& PIPECONF_ENABLE
);
1344 I915_STATE_WARN(cur_state
!= state
,
1345 "pipe %c assertion failure (expected %s, current %s)\n",
1346 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1349 static void assert_plane(struct drm_i915_private
*dev_priv
,
1350 enum plane plane
, bool state
)
1356 reg
= DSPCNTR(plane
);
1357 val
= I915_READ(reg
);
1358 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1359 I915_STATE_WARN(cur_state
!= state
,
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane
), state_string(state
), state_string(cur_state
));
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1370 struct drm_device
*dev
= dev_priv
->dev
;
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev
)->gen
>= 4) {
1377 reg
= DSPCNTR(pipe
);
1378 val
= I915_READ(reg
);
1379 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1380 "plane %c assertion failure, should be disabled but not\n",
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv
, i
) {
1388 val
= I915_READ(reg
);
1389 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1390 DISPPLANE_SEL_PIPE_SHIFT
;
1391 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i
), pipe_name(pipe
));
1397 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1400 struct drm_device
*dev
= dev_priv
->dev
;
1404 if (INTEL_INFO(dev
)->gen
>= 9) {
1405 for_each_sprite(dev_priv
, pipe
, sprite
) {
1406 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1407 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite
, pipe_name(pipe
));
1411 } else if (IS_VALLEYVIEW(dev
)) {
1412 for_each_sprite(dev_priv
, pipe
, sprite
) {
1413 reg
= SPCNTR(pipe
, sprite
);
1414 val
= I915_READ(reg
);
1415 I915_STATE_WARN(val
& SP_ENABLE
,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1419 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1421 val
= I915_READ(reg
);
1422 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424 plane_name(pipe
), pipe_name(pipe
));
1425 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1426 reg
= DVSCNTR(pipe
);
1427 val
= I915_READ(reg
);
1428 I915_STATE_WARN(val
& DVS_ENABLE
,
1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430 plane_name(pipe
), pipe_name(pipe
));
1434 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1437 drm_crtc_vblank_put(crtc
);
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1447 val
= I915_READ(PCH_DREF_CONTROL
);
1448 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1449 DREF_SUPERSPREAD_SOURCE_MASK
));
1450 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1460 reg
= PCH_TRANSCONF(pipe
);
1461 val
= I915_READ(reg
);
1462 enabled
= !!(val
& TRANS_ENABLE
);
1463 I915_STATE_WARN(enabled
,
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1468 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1469 enum pipe pipe
, u32 port_sel
, u32 val
)
1471 if ((val
& DP_PORT_EN
) == 0)
1474 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1475 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1476 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1477 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1479 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1480 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1483 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1489 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1490 enum pipe pipe
, u32 val
)
1492 if ((val
& SDVO_ENABLE
) == 0)
1495 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1496 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1498 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1499 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1502 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1508 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1509 enum pipe pipe
, u32 val
)
1511 if ((val
& LVDS_PORT_EN
) == 0)
1514 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1515 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1518 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1524 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1525 enum pipe pipe
, u32 val
)
1527 if ((val
& ADPA_DAC_ENABLE
) == 0)
1529 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1530 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1533 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1539 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1540 enum pipe pipe
, int reg
, u32 port_sel
)
1542 u32 val
= I915_READ(reg
);
1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545 reg
, pipe_name(pipe
));
1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1548 && (val
& DP_PIPEB_SELECT
),
1549 "IBX PCH dp port still using transcoder B\n");
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1553 enum pipe pipe
, int reg
)
1555 u32 val
= I915_READ(reg
);
1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558 reg
, pipe_name(pipe
));
1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1561 && (val
& SDVO_PIPE_B_SELECT
),
1562 "IBX PCH hdmi port still using transcoder B\n");
1565 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1571 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1572 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1573 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1576 val
= I915_READ(reg
);
1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
1582 val
= I915_READ(reg
);
1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1587 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1588 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1589 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1592 static void intel_init_dpio(struct drm_device
*dev
)
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1596 if (!IS_VALLEYVIEW(dev
))
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 if (IS_CHERRYVIEW(dev
)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1612 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1613 const struct intel_crtc_state
*pipe_config
)
1615 struct drm_device
*dev
= crtc
->base
.dev
;
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1617 int reg
= DPLL(crtc
->pipe
);
1618 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1620 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1625 /* PLL is protected by panel, make sure we can write it */
1626 if (IS_MOBILE(dev_priv
->dev
))
1627 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1629 I915_WRITE(reg
, dpll
);
1633 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1636 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1637 POSTING_READ(DPLL_MD(crtc
->pipe
));
1639 /* We do this three times for luck */
1640 I915_WRITE(reg
, dpll
);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1651 static void chv_enable_pll(struct intel_crtc
*crtc
,
1652 const struct intel_crtc_state
*pipe_config
)
1654 struct drm_device
*dev
= crtc
->base
.dev
;
1655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1656 int pipe
= crtc
->pipe
;
1657 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1660 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1664 mutex_lock(&dev_priv
->sb_lock
);
1666 /* Enable back the 10bit clock to display controller */
1667 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1668 tmp
|= DPIO_DCLKP_EN
;
1669 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1677 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1679 /* Check PLL is locked */
1680 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1681 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1683 /* not sure when this should be written */
1684 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1685 POSTING_READ(DPLL_MD(pipe
));
1687 mutex_unlock(&dev_priv
->sb_lock
);
1690 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1692 struct intel_crtc
*crtc
;
1695 for_each_intel_crtc(dev
, crtc
)
1696 count
+= crtc
->active
&&
1697 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1702 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1704 struct drm_device
*dev
= crtc
->base
.dev
;
1705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1706 int reg
= DPLL(crtc
->pipe
);
1707 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1709 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1711 /* No really, not for ILK+ */
1712 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1714 /* PLL is protected by panel, make sure we can write it */
1715 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1716 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1726 dpll
|= DPLL_DVO_2X_MODE
;
1727 I915_WRITE(DPLL(!crtc
->pipe
),
1728 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1731 /* Wait for the clocks to stabilize. */
1735 if (INTEL_INFO(dev
)->gen
>= 4) {
1736 I915_WRITE(DPLL_MD(crtc
->pipe
),
1737 crtc
->config
->dpll_hw_state
.dpll_md
);
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1742 * So write it again.
1744 I915_WRITE(reg
, dpll
);
1747 /* We do this three times for luck */
1748 I915_WRITE(reg
, dpll
);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg
, dpll
);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg
, dpll
);
1756 udelay(150); /* wait for warmup */
1760 * i9xx_disable_pll - disable a PLL
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 * Note! This is for pre-ILK only.
1768 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1770 struct drm_device
*dev
= crtc
->base
.dev
;
1771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1772 enum pipe pipe
= crtc
->pipe
;
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1776 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1777 intel_num_dvo_pipes(dev
) == 1) {
1778 I915_WRITE(DPLL(PIPE_B
),
1779 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1780 I915_WRITE(DPLL(PIPE_A
),
1781 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1786 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv
, pipe
);
1792 I915_WRITE(DPLL(pipe
), 0);
1793 POSTING_READ(DPLL(pipe
));
1796 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv
, pipe
);
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1808 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1809 I915_WRITE(DPLL(pipe
), val
);
1810 POSTING_READ(DPLL(pipe
));
1814 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1816 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv
, pipe
);
1822 /* Set PLL en = 0 */
1823 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1825 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1826 I915_WRITE(DPLL(pipe
), val
);
1827 POSTING_READ(DPLL(pipe
));
1829 mutex_lock(&dev_priv
->sb_lock
);
1831 /* Disable 10bit clock to display controller */
1832 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1833 val
&= ~DPIO_DCLKP_EN
;
1834 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1836 /* disable left/right clock distribution */
1837 if (pipe
!= PIPE_B
) {
1838 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1839 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1840 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1842 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1843 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1844 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1847 mutex_unlock(&dev_priv
->sb_lock
);
1850 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1851 struct intel_digital_port
*dport
,
1852 unsigned int expected_mask
)
1857 switch (dport
->port
) {
1859 port_mask
= DPLL_PORTB_READY_MASK
;
1863 port_mask
= DPLL_PORTC_READY_MASK
;
1865 expected_mask
<<= 4;
1868 port_mask
= DPLL_PORTD_READY_MASK
;
1869 dpll_reg
= DPIO_PHY_STATUS
;
1875 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1880 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1882 struct drm_device
*dev
= crtc
->base
.dev
;
1883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1884 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1886 if (WARN_ON(pll
== NULL
))
1889 WARN_ON(!pll
->config
.crtc_mask
);
1890 if (pll
->active
== 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1893 assert_shared_dpll_disabled(dev_priv
, pll
);
1895 pll
->mode_set(dev_priv
, pll
);
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1907 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1909 struct drm_device
*dev
= crtc
->base
.dev
;
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1911 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1913 if (WARN_ON(pll
== NULL
))
1916 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll
->name
, pll
->active
, pll
->on
,
1921 crtc
->base
.base
.id
);
1923 if (pll
->active
++) {
1925 assert_shared_dpll_enabled(dev_priv
, pll
);
1930 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1932 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1933 pll
->enable(dev_priv
, pll
);
1937 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1939 struct drm_device
*dev
= crtc
->base
.dev
;
1940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1941 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1943 /* PCH only available on ILK+ */
1944 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1945 if (WARN_ON(pll
== NULL
))
1948 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll
->name
, pll
->active
, pll
->on
,
1953 crtc
->base
.base
.id
);
1955 if (WARN_ON(pll
->active
== 0)) {
1956 assert_shared_dpll_disabled(dev_priv
, pll
);
1960 assert_shared_dpll_enabled(dev_priv
, pll
);
1965 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1966 pll
->disable(dev_priv
, pll
);
1969 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1975 struct drm_device
*dev
= dev_priv
->dev
;
1976 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1977 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1978 uint32_t reg
, val
, pipeconf_val
;
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev
));
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv
,
1985 intel_crtc_to_shared_dpll(intel_crtc
));
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv
, pipe
);
1989 assert_fdi_rx_enabled(dev_priv
, pipe
);
1991 if (HAS_PCH_CPT(dev
)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg
= TRANS_CHICKEN2(pipe
);
1995 val
= I915_READ(reg
);
1996 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1997 I915_WRITE(reg
, val
);
2000 reg
= PCH_TRANSCONF(pipe
);
2001 val
= I915_READ(reg
);
2002 pipeconf_val
= I915_READ(PIPECONF(pipe
));
2004 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2009 val
&= ~PIPECONF_BPC_MASK
;
2010 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2013 val
&= ~TRANS_INTERLACE_MASK
;
2014 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2015 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2016 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2017 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2019 val
|= TRANS_INTERLACED
;
2021 val
|= TRANS_PROGRESSIVE
;
2023 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2024 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2029 enum transcoder cpu_transcoder
)
2031 u32 val
, pipeconf_val
;
2033 /* PCH only available on ILK+ */
2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2036 /* FDI must be feeding us bits for PCH ports */
2037 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2038 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2040 /* Workaround: set timing override bit. */
2041 val
= I915_READ(_TRANSA_CHICKEN2
);
2042 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2043 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2046 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2048 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2049 PIPECONF_INTERLACED_ILK
)
2050 val
|= TRANS_INTERLACED
;
2052 val
|= TRANS_PROGRESSIVE
;
2054 I915_WRITE(LPT_TRANSCONF
, val
);
2055 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2056 DRM_ERROR("Failed to enable PCH transcoder\n");
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2062 struct drm_device
*dev
= dev_priv
->dev
;
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv
, pipe
);
2067 assert_fdi_rx_disabled(dev_priv
, pipe
);
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv
, pipe
);
2072 reg
= PCH_TRANSCONF(pipe
);
2073 val
= I915_READ(reg
);
2074 val
&= ~TRANS_ENABLE
;
2075 I915_WRITE(reg
, val
);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2080 if (!HAS_PCH_IBX(dev
)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg
= TRANS_CHICKEN2(pipe
);
2083 val
= I915_READ(reg
);
2084 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2085 I915_WRITE(reg
, val
);
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2093 val
= I915_READ(LPT_TRANSCONF
);
2094 val
&= ~TRANS_ENABLE
;
2095 I915_WRITE(LPT_TRANSCONF
, val
);
2096 /* wait for PCH transcoder off, transcoder state */
2097 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2098 DRM_ERROR("Failed to disable PCH transcoder\n");
2100 /* Workaround: clear timing override bit. */
2101 val
= I915_READ(_TRANSA_CHICKEN2
);
2102 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2103 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2107 * intel_enable_pipe - enable a pipe, asserting requirements
2108 * @crtc: crtc responsible for the pipe
2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2115 struct drm_device
*dev
= crtc
->base
.dev
;
2116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2117 enum pipe pipe
= crtc
->pipe
;
2118 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2120 enum pipe pch_transcoder
;
2124 assert_planes_disabled(dev_priv
, pipe
);
2125 assert_cursor_disabled(dev_priv
, pipe
);
2126 assert_sprites_disabled(dev_priv
, pipe
);
2128 if (HAS_PCH_LPT(dev_priv
->dev
))
2129 pch_transcoder
= TRANSCODER_A
;
2131 pch_transcoder
= pipe
;
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2138 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2139 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2140 assert_dsi_pll_enabled(dev_priv
);
2142 assert_pll_enabled(dev_priv
, pipe
);
2144 if (crtc
->config
->has_pch_encoder
) {
2145 /* if driving the PCH, we need FDI enabled */
2146 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2147 assert_fdi_tx_pll_enabled(dev_priv
,
2148 (enum pipe
) cpu_transcoder
);
2150 /* FIXME: assert CPU port conditions for SNB+ */
2153 reg
= PIPECONF(cpu_transcoder
);
2154 val
= I915_READ(reg
);
2155 if (val
& PIPECONF_ENABLE
) {
2156 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2157 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2161 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2166 * intel_disable_pipe - disable a pipe, asserting requirements
2167 * @crtc: crtc whose pipes is to be disabled
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
2173 * Will wait until the pipe has shut down before returning.
2175 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2177 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2178 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2179 enum pipe pipe
= crtc
->pipe
;
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2187 assert_planes_disabled(dev_priv
, pipe
);
2188 assert_cursor_disabled(dev_priv
, pipe
);
2189 assert_sprites_disabled(dev_priv
, pipe
);
2191 reg
= PIPECONF(cpu_transcoder
);
2192 val
= I915_READ(reg
);
2193 if ((val
& PIPECONF_ENABLE
) == 0)
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2200 if (crtc
->config
->double_wide
)
2201 val
&= ~PIPECONF_DOUBLE_WIDE
;
2203 /* Don't disable pipe or pipe PLLs if needed */
2204 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2205 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2206 val
&= ~PIPECONF_ENABLE
;
2208 I915_WRITE(reg
, val
);
2209 if ((val
& PIPECONF_ENABLE
) == 0)
2210 intel_wait_for_pipe_off(crtc
);
2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
2218 * Enable @plane on @crtc, making sure that the pipe is running first.
2220 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2221 struct drm_crtc
*crtc
)
2223 struct drm_device
*dev
= plane
->dev
;
2224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2228 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2229 to_intel_plane_state(plane
->state
)->visible
= true;
2231 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2235 static bool need_vtd_wa(struct drm_device
*dev
)
2237 #ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2245 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2246 uint64_t fb_format_modifier
)
2248 unsigned int tile_height
;
2249 uint32_t pixel_bytes
;
2251 switch (fb_format_modifier
) {
2252 case DRM_FORMAT_MOD_NONE
:
2255 case I915_FORMAT_MOD_X_TILED
:
2256 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2258 case I915_FORMAT_MOD_Y_TILED
:
2261 case I915_FORMAT_MOD_Yf_TILED
:
2262 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2263 switch (pixel_bytes
) {
2277 "128-bit pixels are not supported for display!");
2283 MISSING_CASE(fb_format_modifier
);
2292 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2293 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2295 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2296 fb_format_modifier
));
2300 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2301 const struct drm_plane_state
*plane_state
)
2303 struct intel_rotation_info
*info
= &view
->rotation_info
;
2305 *view
= i915_ggtt_view_normal
;
2310 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2313 *view
= i915_ggtt_view_rotated
;
2315 info
->height
= fb
->height
;
2316 info
->pixel_format
= fb
->pixel_format
;
2317 info
->pitch
= fb
->pitches
[0];
2318 info
->fb_modifier
= fb
->modifier
[0];
2324 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2325 struct drm_framebuffer
*fb
,
2326 const struct drm_plane_state
*plane_state
,
2327 struct intel_engine_cs
*pipelined
)
2329 struct drm_device
*dev
= fb
->dev
;
2330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2331 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2332 struct i915_ggtt_view view
;
2336 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2338 switch (fb
->modifier
[0]) {
2339 case DRM_FORMAT_MOD_NONE
:
2340 if (INTEL_INFO(dev
)->gen
>= 9)
2341 alignment
= 256 * 1024;
2342 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2343 alignment
= 128 * 1024;
2344 else if (INTEL_INFO(dev
)->gen
>= 4)
2345 alignment
= 4 * 1024;
2347 alignment
= 64 * 1024;
2349 case I915_FORMAT_MOD_X_TILED
:
2350 if (INTEL_INFO(dev
)->gen
>= 9)
2351 alignment
= 256 * 1024;
2353 /* pin() will align the object as required by fence */
2357 case I915_FORMAT_MOD_Y_TILED
:
2358 case I915_FORMAT_MOD_Yf_TILED
:
2359 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2362 alignment
= 1 * 1024 * 1024;
2365 MISSING_CASE(fb
->modifier
[0]);
2369 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2378 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2379 alignment
= 256 * 1024;
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2388 intel_runtime_pm_get(dev_priv
);
2390 dev_priv
->mm
.interruptible
= false;
2391 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2394 goto err_interruptible
;
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2401 ret
= i915_gem_object_get_fence(obj
);
2405 i915_gem_object_pin_fence(obj
);
2407 dev_priv
->mm
.interruptible
= true;
2408 intel_runtime_pm_put(dev_priv
);
2412 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2414 dev_priv
->mm
.interruptible
= true;
2415 intel_runtime_pm_put(dev_priv
);
2419 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2420 const struct drm_plane_state
*plane_state
)
2422 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2423 struct i915_ggtt_view view
;
2426 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2428 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2429 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2431 i915_gem_object_unpin_fence(obj
);
2432 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2435 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
2437 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2438 unsigned int tiling_mode
,
2442 if (tiling_mode
!= I915_TILING_NONE
) {
2443 unsigned int tile_rows
, tiles
;
2448 tiles
= *x
/ (512/cpp
);
2451 return tile_rows
* pitch
* 8 + tiles
* 4096;
2453 unsigned int offset
;
2455 offset
= *y
* pitch
+ *x
* cpp
;
2457 *x
= (offset
& 4095) / cpp
;
2458 return offset
& -4096;
2462 static int i9xx_format_to_fourcc(int format
)
2465 case DISPPLANE_8BPP
:
2466 return DRM_FORMAT_C8
;
2467 case DISPPLANE_BGRX555
:
2468 return DRM_FORMAT_XRGB1555
;
2469 case DISPPLANE_BGRX565
:
2470 return DRM_FORMAT_RGB565
;
2472 case DISPPLANE_BGRX888
:
2473 return DRM_FORMAT_XRGB8888
;
2474 case DISPPLANE_RGBX888
:
2475 return DRM_FORMAT_XBGR8888
;
2476 case DISPPLANE_BGRX101010
:
2477 return DRM_FORMAT_XRGB2101010
;
2478 case DISPPLANE_RGBX101010
:
2479 return DRM_FORMAT_XBGR2101010
;
2483 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2486 case PLANE_CTL_FORMAT_RGB_565
:
2487 return DRM_FORMAT_RGB565
;
2489 case PLANE_CTL_FORMAT_XRGB_8888
:
2492 return DRM_FORMAT_ABGR8888
;
2494 return DRM_FORMAT_XBGR8888
;
2497 return DRM_FORMAT_ARGB8888
;
2499 return DRM_FORMAT_XRGB8888
;
2501 case PLANE_CTL_FORMAT_XRGB_2101010
:
2503 return DRM_FORMAT_XBGR2101010
;
2505 return DRM_FORMAT_XRGB2101010
;
2510 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2511 struct intel_initial_plane_config
*plane_config
)
2513 struct drm_device
*dev
= crtc
->base
.dev
;
2514 struct drm_i915_gem_object
*obj
= NULL
;
2515 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2516 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2517 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2518 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2521 size_aligned
-= base_aligned
;
2523 if (plane_config
->size
== 0)
2526 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2533 obj
->tiling_mode
= plane_config
->tiling
;
2534 if (obj
->tiling_mode
== I915_TILING_X
)
2535 obj
->stride
= fb
->pitches
[0];
2537 mode_cmd
.pixel_format
= fb
->pixel_format
;
2538 mode_cmd
.width
= fb
->width
;
2539 mode_cmd
.height
= fb
->height
;
2540 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2541 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2542 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2544 mutex_lock(&dev
->struct_mutex
);
2545 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2550 mutex_unlock(&dev
->struct_mutex
);
2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2556 drm_gem_object_unreference(&obj
->base
);
2557 mutex_unlock(&dev
->struct_mutex
);
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 update_state_fb(struct drm_plane
*plane
)
2565 if (plane
->fb
== plane
->state
->fb
)
2568 if (plane
->state
->fb
)
2569 drm_framebuffer_unreference(plane
->state
->fb
);
2570 plane
->state
->fb
= plane
->fb
;
2571 if (plane
->state
->fb
)
2572 drm_framebuffer_reference(plane
->state
->fb
);
2576 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2577 struct intel_initial_plane_config
*plane_config
)
2579 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2582 struct intel_crtc
*i
;
2583 struct drm_i915_gem_object
*obj
;
2584 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2585 struct drm_framebuffer
*fb
;
2587 if (!plane_config
->fb
)
2590 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2591 fb
= &plane_config
->fb
->base
;
2595 kfree(plane_config
->fb
);
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2601 for_each_crtc(dev
, c
) {
2602 i
= to_intel_crtc(c
);
2604 if (c
== &intel_crtc
->base
)
2610 fb
= c
->primary
->fb
;
2614 obj
= intel_fb_obj(fb
);
2615 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2616 drm_framebuffer_reference(fb
);
2624 obj
= intel_fb_obj(fb
);
2625 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2626 dev_priv
->preserve_bios_swizzle
= true;
2629 primary
->state
->crtc
= &intel_crtc
->base
;
2630 primary
->crtc
= &intel_crtc
->base
;
2631 update_state_fb(primary
);
2632 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2635 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2636 struct drm_framebuffer
*fb
,
2639 struct drm_device
*dev
= crtc
->dev
;
2640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2642 struct drm_plane
*primary
= crtc
->primary
;
2643 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2644 struct drm_i915_gem_object
*obj
;
2645 int plane
= intel_crtc
->plane
;
2646 unsigned long linear_offset
;
2648 u32 reg
= DSPCNTR(plane
);
2651 if (!visible
|| !fb
) {
2653 if (INTEL_INFO(dev
)->gen
>= 4)
2654 I915_WRITE(DSPSURF(plane
), 0);
2656 I915_WRITE(DSPADDR(plane
), 0);
2661 obj
= intel_fb_obj(fb
);
2662 if (WARN_ON(obj
== NULL
))
2665 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2667 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2669 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2671 if (INTEL_INFO(dev
)->gen
< 4) {
2672 if (intel_crtc
->pipe
== PIPE_B
)
2673 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2678 I915_WRITE(DSPSIZE(plane
),
2679 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2680 (intel_crtc
->config
->pipe_src_w
- 1));
2681 I915_WRITE(DSPPOS(plane
), 0);
2682 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2683 I915_WRITE(PRIMSIZE(plane
),
2684 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2685 (intel_crtc
->config
->pipe_src_w
- 1));
2686 I915_WRITE(PRIMPOS(plane
), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2690 switch (fb
->pixel_format
) {
2692 dspcntr
|= DISPPLANE_8BPP
;
2694 case DRM_FORMAT_XRGB1555
:
2695 dspcntr
|= DISPPLANE_BGRX555
;
2697 case DRM_FORMAT_RGB565
:
2698 dspcntr
|= DISPPLANE_BGRX565
;
2700 case DRM_FORMAT_XRGB8888
:
2701 dspcntr
|= DISPPLANE_BGRX888
;
2703 case DRM_FORMAT_XBGR8888
:
2704 dspcntr
|= DISPPLANE_RGBX888
;
2706 case DRM_FORMAT_XRGB2101010
:
2707 dspcntr
|= DISPPLANE_BGRX101010
;
2709 case DRM_FORMAT_XBGR2101010
:
2710 dspcntr
|= DISPPLANE_RGBX101010
;
2716 if (INTEL_INFO(dev
)->gen
>= 4 &&
2717 obj
->tiling_mode
!= I915_TILING_NONE
)
2718 dspcntr
|= DISPPLANE_TILED
;
2721 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2723 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2725 if (INTEL_INFO(dev
)->gen
>= 4) {
2726 intel_crtc
->dspaddr_offset
=
2727 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2730 linear_offset
-= intel_crtc
->dspaddr_offset
;
2732 intel_crtc
->dspaddr_offset
= linear_offset
;
2735 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2736 dspcntr
|= DISPPLANE_ROTATE_180
;
2738 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2739 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2744 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2745 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2748 I915_WRITE(reg
, dspcntr
);
2750 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2751 if (INTEL_INFO(dev
)->gen
>= 4) {
2752 I915_WRITE(DSPSURF(plane
),
2753 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2754 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2755 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2757 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2761 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2762 struct drm_framebuffer
*fb
,
2765 struct drm_device
*dev
= crtc
->dev
;
2766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2768 struct drm_plane
*primary
= crtc
->primary
;
2769 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2770 struct drm_i915_gem_object
*obj
;
2771 int plane
= intel_crtc
->plane
;
2772 unsigned long linear_offset
;
2774 u32 reg
= DSPCNTR(plane
);
2777 if (!visible
|| !fb
) {
2779 I915_WRITE(DSPSURF(plane
), 0);
2784 obj
= intel_fb_obj(fb
);
2785 if (WARN_ON(obj
== NULL
))
2788 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2790 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2792 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2794 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2795 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2797 switch (fb
->pixel_format
) {
2799 dspcntr
|= DISPPLANE_8BPP
;
2801 case DRM_FORMAT_RGB565
:
2802 dspcntr
|= DISPPLANE_BGRX565
;
2804 case DRM_FORMAT_XRGB8888
:
2805 dspcntr
|= DISPPLANE_BGRX888
;
2807 case DRM_FORMAT_XBGR8888
:
2808 dspcntr
|= DISPPLANE_RGBX888
;
2810 case DRM_FORMAT_XRGB2101010
:
2811 dspcntr
|= DISPPLANE_BGRX101010
;
2813 case DRM_FORMAT_XBGR2101010
:
2814 dspcntr
|= DISPPLANE_RGBX101010
;
2820 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2821 dspcntr
|= DISPPLANE_TILED
;
2823 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2824 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2826 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2827 intel_crtc
->dspaddr_offset
=
2828 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2831 linear_offset
-= intel_crtc
->dspaddr_offset
;
2832 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2833 dspcntr
|= DISPPLANE_ROTATE_180
;
2835 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2836 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2837 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2842 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2843 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2847 I915_WRITE(reg
, dspcntr
);
2849 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2850 I915_WRITE(DSPSURF(plane
),
2851 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2852 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2853 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2855 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2856 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2861 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2862 uint32_t pixel_format
)
2864 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2871 switch (fb_modifier
) {
2872 case DRM_FORMAT_MOD_NONE
:
2874 case I915_FORMAT_MOD_X_TILED
:
2875 if (INTEL_INFO(dev
)->gen
== 2)
2878 case I915_FORMAT_MOD_Y_TILED
:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2884 case I915_FORMAT_MOD_Yf_TILED
:
2885 if (bits_per_pixel
== 8)
2890 MISSING_CASE(fb_modifier
);
2895 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2896 struct drm_i915_gem_object
*obj
)
2898 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2900 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2901 view
= &i915_ggtt_view_rotated
;
2903 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2909 void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2911 struct drm_device
*dev
;
2912 struct drm_i915_private
*dev_priv
;
2913 struct intel_crtc_scaler_state
*scaler_state
;
2916 if (!intel_crtc
|| !intel_crtc
->config
)
2919 dev
= intel_crtc
->base
.dev
;
2920 dev_priv
= dev
->dev_private
;
2921 scaler_state
= &intel_crtc
->config
->scaler_state
;
2923 /* loop through and disable scalers that aren't in use */
2924 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2925 if (!scaler_state
->scalers
[i
].in_use
) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2935 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2937 switch (pixel_format
) {
2939 return PLANE_CTL_FORMAT_INDEXED
;
2940 case DRM_FORMAT_RGB565
:
2941 return PLANE_CTL_FORMAT_RGB_565
;
2942 case DRM_FORMAT_XBGR8888
:
2943 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2944 case DRM_FORMAT_XRGB8888
:
2945 return PLANE_CTL_FORMAT_XRGB_8888
;
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2951 case DRM_FORMAT_ABGR8888
:
2952 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2954 case DRM_FORMAT_ARGB8888
:
2955 return PLANE_CTL_FORMAT_XRGB_8888
|
2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2957 case DRM_FORMAT_XRGB2101010
:
2958 return PLANE_CTL_FORMAT_XRGB_2101010
;
2959 case DRM_FORMAT_XBGR2101010
:
2960 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2961 case DRM_FORMAT_YUYV
:
2962 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2963 case DRM_FORMAT_YVYU
:
2964 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2965 case DRM_FORMAT_UYVY
:
2966 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2967 case DRM_FORMAT_VYUY
:
2968 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2970 MISSING_CASE(pixel_format
);
2976 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2978 switch (fb_modifier
) {
2979 case DRM_FORMAT_MOD_NONE
:
2981 case I915_FORMAT_MOD_X_TILED
:
2982 return PLANE_CTL_TILED_X
;
2983 case I915_FORMAT_MOD_Y_TILED
:
2984 return PLANE_CTL_TILED_Y
;
2985 case I915_FORMAT_MOD_Yf_TILED
:
2986 return PLANE_CTL_TILED_YF
;
2988 MISSING_CASE(fb_modifier
);
2994 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2997 case BIT(DRM_ROTATE_0
):
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3003 case BIT(DRM_ROTATE_90
):
3004 return PLANE_CTL_ROTATE_270
;
3005 case BIT(DRM_ROTATE_180
):
3006 return PLANE_CTL_ROTATE_180
;
3007 case BIT(DRM_ROTATE_270
):
3008 return PLANE_CTL_ROTATE_90
;
3010 MISSING_CASE(rotation
);
3016 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3017 struct drm_framebuffer
*fb
,
3020 struct drm_device
*dev
= crtc
->dev
;
3021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3022 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3023 struct drm_plane
*plane
= crtc
->primary
;
3024 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3025 struct drm_i915_gem_object
*obj
;
3026 int pipe
= intel_crtc
->pipe
;
3027 u32 plane_ctl
, stride_div
, stride
;
3028 u32 tile_height
, plane_offset
, plane_size
;
3029 unsigned int rotation
;
3030 int x_offset
, y_offset
;
3031 unsigned long surf_addr
;
3032 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3033 struct intel_plane_state
*plane_state
;
3034 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3035 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3038 plane_state
= to_intel_plane_state(plane
->state
);
3040 if (!visible
|| !fb
) {
3041 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe
, 0));
3047 plane_ctl
= PLANE_CTL_ENABLE
|
3048 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3049 PLANE_CTL_PIPE_CSC_ENABLE
;
3051 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3052 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3053 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3055 rotation
= plane
->state
->rotation
;
3056 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3058 obj
= intel_fb_obj(fb
);
3059 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3061 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3068 if (drm_rect_width(&plane_state
->src
)) {
3069 scaler_id
= plane_state
->scaler_id
;
3070 src_x
= plane_state
->src
.x1
>> 16;
3071 src_y
= plane_state
->src
.y1
>> 16;
3072 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3073 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3074 dst_x
= plane_state
->dst
.x1
;
3075 dst_y
= plane_state
->dst
.y1
;
3076 dst_w
= drm_rect_width(&plane_state
->dst
);
3077 dst_h
= drm_rect_height(&plane_state
->dst
);
3079 WARN_ON(x
!= src_x
|| y
!= src_y
);
3081 src_w
= intel_crtc
->config
->pipe_src_w
;
3082 src_h
= intel_crtc
->config
->pipe_src_h
;
3085 if (intel_rotation_90_or_270(rotation
)) {
3086 /* stride = Surface height in tiles */
3087 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3089 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3090 x_offset
= stride
* tile_height
- y
- src_h
;
3092 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3094 stride
= fb
->pitches
[0] / stride_div
;
3097 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3099 plane_offset
= y_offset
<< 16 | x_offset
;
3101 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3102 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3103 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3104 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3106 if (scaler_id
>= 0) {
3107 uint32_t ps_ctrl
= 0;
3109 WARN_ON(!dst_w
|| !dst_h
);
3110 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3111 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3112 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3116 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3118 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3121 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3123 POSTING_READ(PLANE_SURF(pipe
, 0));
3126 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3128 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3129 int x
, int y
, enum mode_set_atomic state
)
3131 struct drm_device
*dev
= crtc
->dev
;
3132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3134 if (dev_priv
->display
.disable_fbc
)
3135 dev_priv
->display
.disable_fbc(dev
);
3137 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3142 static void intel_complete_page_flips(struct drm_device
*dev
)
3144 struct drm_crtc
*crtc
;
3146 for_each_crtc(dev
, crtc
) {
3147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3148 enum plane plane
= intel_crtc
->plane
;
3150 intel_prepare_page_flip(dev
, plane
);
3151 intel_finish_page_flip_plane(dev
, plane
);
3155 static void intel_update_primary_planes(struct drm_device
*dev
)
3157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3158 struct drm_crtc
*crtc
;
3160 for_each_crtc(dev
, crtc
) {
3161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3163 drm_modeset_lock(&crtc
->mutex
, NULL
);
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
3167 * a NULL crtc->primary->fb.
3169 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3170 dev_priv
->display
.update_primary_plane(crtc
,
3174 drm_modeset_unlock(&crtc
->mutex
);
3178 void intel_crtc_reset(struct intel_crtc
*crtc
)
3180 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3185 intel_crtc_disable_planes(&crtc
->base
);
3186 dev_priv
->display
.crtc_disable(&crtc
->base
);
3187 dev_priv
->display
.crtc_enable(&crtc
->base
);
3188 intel_crtc_enable_planes(&crtc
->base
);
3191 void intel_prepare_reset(struct drm_device
*dev
)
3193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3194 struct intel_crtc
*crtc
;
3196 /* no reset support for gen2 */
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3204 drm_modeset_lock_all(dev
);
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3210 for_each_intel_crtc(dev
, crtc
) {
3214 intel_crtc_disable_planes(&crtc
->base
);
3215 dev_priv
->display
.crtc_disable(&crtc
->base
);
3219 void intel_finish_reset(struct drm_device
*dev
)
3221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3228 intel_complete_page_flips(dev
);
3230 /* no reset support for gen2 */
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3242 intel_update_primary_planes(dev
);
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3250 intel_runtime_pm_disable_interrupts(dev_priv
);
3251 intel_runtime_pm_enable_interrupts(dev_priv
);
3253 intel_modeset_init_hw(dev
);
3255 spin_lock_irq(&dev_priv
->irq_lock
);
3256 if (dev_priv
->display
.hpd_irq_setup
)
3257 dev_priv
->display
.hpd_irq_setup(dev
);
3258 spin_unlock_irq(&dev_priv
->irq_lock
);
3260 intel_modeset_setup_hw_state(dev
, true);
3262 intel_hpd_init(dev_priv
);
3264 drm_modeset_unlock_all(dev
);
3268 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3270 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3271 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3272 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3286 dev_priv
->mm
.interruptible
= false;
3287 ret
= i915_gem_object_wait_rendering(obj
, true);
3288 dev_priv
->mm
.interruptible
= was_interruptible
;
3293 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3295 struct drm_device
*dev
= crtc
->dev
;
3296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3300 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3301 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3304 spin_lock_irq(&dev
->event_lock
);
3305 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3306 spin_unlock_irq(&dev
->event_lock
);
3311 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3313 struct drm_device
*dev
= crtc
->base
.dev
;
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3315 const struct drm_display_mode
*adjusted_mode
;
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3334 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3336 I915_WRITE(PIPESRC(crtc
->pipe
),
3337 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3338 (adjusted_mode
->crtc_vdisplay
- 1));
3339 if (!crtc
->config
->pch_pfit
.enabled
&&
3340 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3341 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3342 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3343 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3346 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3347 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3350 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3352 struct drm_device
*dev
= crtc
->dev
;
3353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3354 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3355 int pipe
= intel_crtc
->pipe
;
3358 /* enable normal train */
3359 reg
= FDI_TX_CTL(pipe
);
3360 temp
= I915_READ(reg
);
3361 if (IS_IVYBRIDGE(dev
)) {
3362 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3363 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3365 temp
&= ~FDI_LINK_TRAIN_NONE
;
3366 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3368 I915_WRITE(reg
, temp
);
3370 reg
= FDI_RX_CTL(pipe
);
3371 temp
= I915_READ(reg
);
3372 if (HAS_PCH_CPT(dev
)) {
3373 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3374 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3376 temp
&= ~FDI_LINK_TRAIN_NONE
;
3377 temp
|= FDI_LINK_TRAIN_NONE
;
3379 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3381 /* wait one idle pattern time */
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev
))
3387 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3388 FDI_FE_ERRC_ENABLE
);
3391 /* The FDI link training functions for ILK/Ibexpeak. */
3392 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3394 struct drm_device
*dev
= crtc
->dev
;
3395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3396 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3397 int pipe
= intel_crtc
->pipe
;
3398 u32 reg
, temp
, tries
;
3400 /* FDI needs bits from pipe first */
3401 assert_pipe_enabled(dev_priv
, pipe
);
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3405 reg
= FDI_RX_IMR(pipe
);
3406 temp
= I915_READ(reg
);
3407 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3408 temp
&= ~FDI_RX_BIT_LOCK
;
3409 I915_WRITE(reg
, temp
);
3413 /* enable CPU FDI TX and PCH FDI RX */
3414 reg
= FDI_TX_CTL(pipe
);
3415 temp
= I915_READ(reg
);
3416 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3417 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3418 temp
&= ~FDI_LINK_TRAIN_NONE
;
3419 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3420 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3422 reg
= FDI_RX_CTL(pipe
);
3423 temp
= I915_READ(reg
);
3424 temp
&= ~FDI_LINK_TRAIN_NONE
;
3425 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3426 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
3432 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3434 FDI_RX_PHASE_SYNC_POINTER_EN
);
3436 reg
= FDI_RX_IIR(pipe
);
3437 for (tries
= 0; tries
< 5; tries
++) {
3438 temp
= I915_READ(reg
);
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3441 if ((temp
& FDI_RX_BIT_LOCK
)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
3443 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3448 DRM_ERROR("FDI train 1 fail!\n");
3451 reg
= FDI_TX_CTL(pipe
);
3452 temp
= I915_READ(reg
);
3453 temp
&= ~FDI_LINK_TRAIN_NONE
;
3454 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3455 I915_WRITE(reg
, temp
);
3457 reg
= FDI_RX_CTL(pipe
);
3458 temp
= I915_READ(reg
);
3459 temp
&= ~FDI_LINK_TRAIN_NONE
;
3460 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3461 I915_WRITE(reg
, temp
);
3466 reg
= FDI_RX_IIR(pipe
);
3467 for (tries
= 0; tries
< 5; tries
++) {
3468 temp
= I915_READ(reg
);
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3471 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3472 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3478 DRM_ERROR("FDI train 2 fail!\n");
3480 DRM_DEBUG_KMS("FDI train done\n");
3484 static const int snb_b_fdi_train_param
[] = {
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3494 struct drm_device
*dev
= crtc
->dev
;
3495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3497 int pipe
= intel_crtc
->pipe
;
3498 u32 reg
, temp
, i
, retry
;
3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502 reg
= FDI_RX_IMR(pipe
);
3503 temp
= I915_READ(reg
);
3504 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3505 temp
&= ~FDI_RX_BIT_LOCK
;
3506 I915_WRITE(reg
, temp
);
3511 /* enable CPU FDI TX and PCH FDI RX */
3512 reg
= FDI_TX_CTL(pipe
);
3513 temp
= I915_READ(reg
);
3514 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3515 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3516 temp
&= ~FDI_LINK_TRAIN_NONE
;
3517 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3518 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3520 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3521 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3523 I915_WRITE(FDI_RX_MISC(pipe
),
3524 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3526 reg
= FDI_RX_CTL(pipe
);
3527 temp
= I915_READ(reg
);
3528 if (HAS_PCH_CPT(dev
)) {
3529 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3530 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3532 temp
&= ~FDI_LINK_TRAIN_NONE
;
3533 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3535 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3540 for (i
= 0; i
< 4; i
++) {
3541 reg
= FDI_TX_CTL(pipe
);
3542 temp
= I915_READ(reg
);
3543 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3544 temp
|= snb_b_fdi_train_param
[i
];
3545 I915_WRITE(reg
, temp
);
3550 for (retry
= 0; retry
< 5; retry
++) {
3551 reg
= FDI_RX_IIR(pipe
);
3552 temp
= I915_READ(reg
);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3554 if (temp
& FDI_RX_BIT_LOCK
) {
3555 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3565 DRM_ERROR("FDI train 1 fail!\n");
3568 reg
= FDI_TX_CTL(pipe
);
3569 temp
= I915_READ(reg
);
3570 temp
&= ~FDI_LINK_TRAIN_NONE
;
3571 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3573 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3575 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3577 I915_WRITE(reg
, temp
);
3579 reg
= FDI_RX_CTL(pipe
);
3580 temp
= I915_READ(reg
);
3581 if (HAS_PCH_CPT(dev
)) {
3582 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3583 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3585 temp
&= ~FDI_LINK_TRAIN_NONE
;
3586 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3588 I915_WRITE(reg
, temp
);
3593 for (i
= 0; i
< 4; i
++) {
3594 reg
= FDI_TX_CTL(pipe
);
3595 temp
= I915_READ(reg
);
3596 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3597 temp
|= snb_b_fdi_train_param
[i
];
3598 I915_WRITE(reg
, temp
);
3603 for (retry
= 0; retry
< 5; retry
++) {
3604 reg
= FDI_RX_IIR(pipe
);
3605 temp
= I915_READ(reg
);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3607 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3608 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3618 DRM_ERROR("FDI train 2 fail!\n");
3620 DRM_DEBUG_KMS("FDI train done.\n");
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3626 struct drm_device
*dev
= crtc
->dev
;
3627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3629 int pipe
= intel_crtc
->pipe
;
3630 u32 reg
, temp
, i
, j
;
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634 reg
= FDI_RX_IMR(pipe
);
3635 temp
= I915_READ(reg
);
3636 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3637 temp
&= ~FDI_RX_BIT_LOCK
;
3638 I915_WRITE(reg
, temp
);
3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe
)));
3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3648 /* disable first in case we need to retry */
3649 reg
= FDI_TX_CTL(pipe
);
3650 temp
= I915_READ(reg
);
3651 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3652 temp
&= ~FDI_TX_ENABLE
;
3653 I915_WRITE(reg
, temp
);
3655 reg
= FDI_RX_CTL(pipe
);
3656 temp
= I915_READ(reg
);
3657 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3658 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3659 temp
&= ~FDI_RX_ENABLE
;
3660 I915_WRITE(reg
, temp
);
3662 /* enable CPU FDI TX and PCH FDI RX */
3663 reg
= FDI_TX_CTL(pipe
);
3664 temp
= I915_READ(reg
);
3665 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3666 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3667 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3668 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3669 temp
|= snb_b_fdi_train_param
[j
/2];
3670 temp
|= FDI_COMPOSITE_SYNC
;
3671 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3673 I915_WRITE(FDI_RX_MISC(pipe
),
3674 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3676 reg
= FDI_RX_CTL(pipe
);
3677 temp
= I915_READ(reg
);
3678 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3679 temp
|= FDI_COMPOSITE_SYNC
;
3680 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3683 udelay(1); /* should be 0.5us */
3685 for (i
= 0; i
< 4; i
++) {
3686 reg
= FDI_RX_IIR(pipe
);
3687 temp
= I915_READ(reg
);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3690 if (temp
& FDI_RX_BIT_LOCK
||
3691 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3692 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3697 udelay(1); /* should be 0.5us */
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3705 reg
= FDI_TX_CTL(pipe
);
3706 temp
= I915_READ(reg
);
3707 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3708 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3709 I915_WRITE(reg
, temp
);
3711 reg
= FDI_RX_CTL(pipe
);
3712 temp
= I915_READ(reg
);
3713 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3714 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3715 I915_WRITE(reg
, temp
);
3718 udelay(2); /* should be 1.5us */
3720 for (i
= 0; i
< 4; i
++) {
3721 reg
= FDI_RX_IIR(pipe
);
3722 temp
= I915_READ(reg
);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3725 if (temp
& FDI_RX_SYMBOL_LOCK
||
3726 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3727 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3732 udelay(2); /* should be 1.5us */
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3739 DRM_DEBUG_KMS("FDI train done.\n");
3742 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3744 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3746 int pipe
= intel_crtc
->pipe
;
3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3751 reg
= FDI_RX_CTL(pipe
);
3752 temp
= I915_READ(reg
);
3753 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3754 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3755 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3756 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3761 /* Switch from Rawclk to PCDclk */
3762 temp
= I915_READ(reg
);
3763 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg
= FDI_TX_CTL(pipe
);
3770 temp
= I915_READ(reg
);
3771 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3772 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3779 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3781 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3783 int pipe
= intel_crtc
->pipe
;
3786 /* Switch from PCDclk to Rawclk */
3787 reg
= FDI_RX_CTL(pipe
);
3788 temp
= I915_READ(reg
);
3789 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3791 /* Disable CPU FDI TX PLL */
3792 reg
= FDI_TX_CTL(pipe
);
3793 temp
= I915_READ(reg
);
3794 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3799 reg
= FDI_RX_CTL(pipe
);
3800 temp
= I915_READ(reg
);
3801 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3803 /* Wait for the clocks to turn off. */
3808 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3810 struct drm_device
*dev
= crtc
->dev
;
3811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3812 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3813 int pipe
= intel_crtc
->pipe
;
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg
= FDI_TX_CTL(pipe
);
3818 temp
= I915_READ(reg
);
3819 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3822 reg
= FDI_RX_CTL(pipe
);
3823 temp
= I915_READ(reg
);
3824 temp
&= ~(0x7 << 16);
3825 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3826 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
3832 if (HAS_PCH_IBX(dev
))
3833 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3835 /* still set train pattern 1 */
3836 reg
= FDI_TX_CTL(pipe
);
3837 temp
= I915_READ(reg
);
3838 temp
&= ~FDI_LINK_TRAIN_NONE
;
3839 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3840 I915_WRITE(reg
, temp
);
3842 reg
= FDI_RX_CTL(pipe
);
3843 temp
= I915_READ(reg
);
3844 if (HAS_PCH_CPT(dev
)) {
3845 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3846 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3848 temp
&= ~FDI_LINK_TRAIN_NONE
;
3849 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp
&= ~(0x07 << 16);
3853 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3854 I915_WRITE(reg
, temp
);
3860 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3862 struct intel_crtc
*crtc
;
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3871 for_each_intel_crtc(dev
, crtc
) {
3872 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3875 if (crtc
->unpin_work
)
3876 intel_wait_for_vblank(dev
, crtc
->pipe
);
3884 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3886 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3887 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3891 intel_crtc
->unpin_work
= NULL
;
3894 drm_send_vblank_event(intel_crtc
->base
.dev
,
3898 drm_crtc_vblank_put(&intel_crtc
->base
);
3900 wake_up_all(&dev_priv
->pending_flip_queue
);
3901 queue_work(dev_priv
->wq
, &work
->work
);
3903 trace_i915_flip_complete(intel_crtc
->plane
,
3904 work
->pending_flip_obj
);
3907 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3909 struct drm_device
*dev
= crtc
->dev
;
3910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3912 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3913 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3914 !intel_crtc_has_pending_flip(crtc
),
3916 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3918 spin_lock_irq(&dev
->event_lock
);
3919 if (intel_crtc
->unpin_work
) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc
);
3923 spin_unlock_irq(&dev
->event_lock
);
3926 if (crtc
->primary
->fb
) {
3927 mutex_lock(&dev
->struct_mutex
);
3928 intel_finish_fb(crtc
->primary
->fb
);
3929 mutex_unlock(&dev
->struct_mutex
);
3933 /* Program iCLKIP clock to the desired frequency */
3934 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3936 struct drm_device
*dev
= crtc
->dev
;
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3938 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3939 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3942 mutex_lock(&dev_priv
->sb_lock
);
3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3947 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3951 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3956 if (clock
== 20000) {
3961 /* The iCLK virtual clock root frequency is in MHz,
3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
3964 * convert the virtual clock precision to KHz here for higher
3967 u32 iclk_virtual_root_freq
= 172800 * 1000;
3968 u32 iclk_pi_range
= 64;
3969 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3971 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3972 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3973 pi_value
= desired_divisor
% iclk_pi_range
;
3976 divsel
= msb_divisor_value
- 2;
3977 phaseinc
= pi_value
;
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3993 /* Program SSCDIVINTPHASE6 */
3994 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3995 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3996 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3997 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3998 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3999 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4000 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4001 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4003 /* Program SSCAUXDIV */
4004 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4005 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4007 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4009 /* Enable modulator and associated divider */
4010 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4011 temp
&= ~SBI_SSCCTL_DISABLE
;
4012 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4014 /* Wait for initialization time */
4017 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4019 mutex_unlock(&dev_priv
->sb_lock
);
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4023 enum pipe pch_transcoder
)
4025 struct drm_device
*dev
= crtc
->base
.dev
;
4026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4027 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4030 I915_READ(HTOTAL(cpu_transcoder
)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4032 I915_READ(HBLANK(cpu_transcoder
)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4034 I915_READ(HSYNC(cpu_transcoder
)));
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4037 I915_READ(VTOTAL(cpu_transcoder
)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4039 I915_READ(VBLANK(cpu_transcoder
)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4041 I915_READ(VSYNC(cpu_transcoder
)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4051 temp
= I915_READ(SOUTH_CHICKEN1
);
4052 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4058 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4060 temp
|= FDI_BC_BIFURCATION_SELECT
;
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4063 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4064 POSTING_READ(SOUTH_CHICKEN1
);
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4069 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4071 switch (intel_crtc
->pipe
) {
4075 if (intel_crtc
->config
->fdi_lanes
> 2)
4076 cpt_set_fdi_bc_bifurcation(dev
, false);
4078 cpt_set_fdi_bc_bifurcation(dev
, true);
4082 cpt_set_fdi_bc_bifurcation(dev
, true);
4091 * Enable PCH resources required for PCH ports:
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4098 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4100 struct drm_device
*dev
= crtc
->dev
;
4101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4102 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4103 int pipe
= intel_crtc
->pipe
;
4106 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4108 if (IS_IVYBRIDGE(dev
))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4114 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4116 /* For PCH output, training FDI link */
4117 dev_priv
->display
.fdi_link_train(crtc
);
4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
4121 if (HAS_PCH_CPT(dev
)) {
4124 temp
= I915_READ(PCH_DPLL_SEL
);
4125 temp
|= TRANS_DPLL_ENABLE(pipe
);
4126 sel
= TRANS_DPLLB_SEL(pipe
);
4127 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4131 I915_WRITE(PCH_DPLL_SEL
, temp
);
4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
4141 intel_enable_shared_dpll(intel_crtc
);
4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv
, pipe
);
4145 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4147 intel_fdi_normal_train(crtc
);
4149 /* For PCH DP, enable TRANS_DP_CTL */
4150 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4151 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4152 reg
= TRANS_DP_CTL(pipe
);
4153 temp
= I915_READ(reg
);
4154 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4155 TRANS_DP_SYNC_MASK
|
4157 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4158 temp
|= bpc
<< 9; /* same format but at 11:9 */
4160 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4161 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4162 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4163 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4165 switch (intel_trans_dp_port_sel(crtc
)) {
4167 temp
|= TRANS_DP_PORT_SEL_B
;
4170 temp
|= TRANS_DP_PORT_SEL_C
;
4173 temp
|= TRANS_DP_PORT_SEL_D
;
4179 I915_WRITE(reg
, temp
);
4182 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4185 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4187 struct drm_device
*dev
= crtc
->dev
;
4188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4190 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4192 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4194 lpt_program_iclkip(crtc
);
4196 /* Set transcoder timing. */
4197 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4199 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4202 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4204 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4209 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4210 WARN(1, "bad %s crtc mask\n", pll
->name
);
4214 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4215 if (pll
->config
.crtc_mask
== 0) {
4217 WARN_ON(pll
->active
);
4220 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4223 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4224 struct intel_crtc_state
*crtc_state
)
4226 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4227 struct intel_shared_dpll
*pll
;
4228 enum intel_dpll_id i
;
4230 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4232 i
= (enum intel_dpll_id
) crtc
->pipe
;
4233 pll
= &dev_priv
->shared_dplls
[i
];
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc
->base
.base
.id
, pll
->name
);
4238 WARN_ON(pll
->new_config
->crtc_mask
);
4243 if (IS_BROXTON(dev_priv
->dev
)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder
*encoder
;
4246 struct intel_digital_port
*intel_dig_port
;
4248 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4249 if (WARN_ON(!encoder
))
4252 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4253 /* 1:1 mapping between ports and PLLs */
4254 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4255 pll
= &dev_priv
->shared_dplls
[i
];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc
->base
.base
.id
, pll
->name
);
4258 WARN_ON(pll
->new_config
->crtc_mask
);
4263 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4264 pll
= &dev_priv
->shared_dplls
[i
];
4266 /* Only want to check enabled timings first */
4267 if (pll
->new_config
->crtc_mask
== 0)
4270 if (memcmp(&crtc_state
->dpll_hw_state
,
4271 &pll
->new_config
->hw_state
,
4272 sizeof(pll
->new_config
->hw_state
)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4274 crtc
->base
.base
.id
, pll
->name
,
4275 pll
->new_config
->crtc_mask
,
4281 /* Ok no matching timings, maybe there's a free one? */
4282 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4283 pll
= &dev_priv
->shared_dplls
[i
];
4284 if (pll
->new_config
->crtc_mask
== 0) {
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc
->base
.base
.id
, pll
->name
);
4294 if (pll
->new_config
->crtc_mask
== 0)
4295 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4297 crtc_state
->shared_dpll
= i
;
4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4299 pipe_name(crtc
->pipe
));
4301 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4314 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4315 unsigned clear_pipes
)
4317 struct intel_shared_dpll
*pll
;
4318 enum intel_dpll_id i
;
4320 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4321 pll
= &dev_priv
->shared_dplls
[i
];
4323 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4325 if (!pll
->new_config
)
4328 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4335 pll
= &dev_priv
->shared_dplls
[i
];
4336 kfree(pll
->new_config
);
4337 pll
->new_config
= NULL
;
4343 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4345 struct intel_shared_dpll
*pll
;
4346 enum intel_dpll_id i
;
4348 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4349 pll
= &dev_priv
->shared_dplls
[i
];
4351 WARN_ON(pll
->new_config
== &pll
->config
);
4353 pll
->config
= *pll
->new_config
;
4354 kfree(pll
->new_config
);
4355 pll
->new_config
= NULL
;
4359 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4361 struct intel_shared_dpll
*pll
;
4362 enum intel_dpll_id i
;
4364 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4365 pll
= &dev_priv
->shared_dplls
[i
];
4367 WARN_ON(pll
->new_config
== &pll
->config
);
4369 kfree(pll
->new_config
);
4370 pll
->new_config
= NULL
;
4374 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4377 int dslreg
= PIPEDSL(pipe
);
4380 temp
= I915_READ(dslreg
);
4382 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4383 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4406 skl_update_scaler_users(
4407 struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
,
4408 struct intel_plane
*intel_plane
, struct intel_plane_state
*plane_state
,
4413 int src_w
, src_h
, dst_w
, dst_h
;
4415 struct drm_framebuffer
*fb
;
4416 struct intel_crtc_scaler_state
*scaler_state
;
4417 unsigned int rotation
;
4419 if (!intel_crtc
|| !crtc_state
)
4422 scaler_state
= &crtc_state
->scaler_state
;
4424 idx
= intel_plane
? drm_plane_index(&intel_plane
->base
) : SKL_CRTC_INDEX
;
4425 fb
= intel_plane
? plane_state
->base
.fb
: NULL
;
4428 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
4429 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
4430 dst_w
= drm_rect_width(&plane_state
->dst
);
4431 dst_h
= drm_rect_height(&plane_state
->dst
);
4432 scaler_id
= &plane_state
->scaler_id
;
4433 rotation
= plane_state
->base
.rotation
;
4435 struct drm_display_mode
*adjusted_mode
=
4436 &crtc_state
->base
.adjusted_mode
;
4437 src_w
= crtc_state
->pipe_src_w
;
4438 src_h
= crtc_state
->pipe_src_h
;
4439 dst_w
= adjusted_mode
->hdisplay
;
4440 dst_h
= adjusted_mode
->vdisplay
;
4441 scaler_id
= &scaler_state
->scaler_id
;
4442 rotation
= DRM_ROTATE_0
;
4445 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4446 (src_h
!= dst_w
|| src_w
!= dst_h
):
4447 (src_w
!= dst_w
|| src_h
!= dst_h
);
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4459 if (force_detach
|| !need_scaling
|| (intel_plane
&&
4460 (!fb
|| !plane_state
->visible
))) {
4461 if (*scaler_id
>= 0) {
4462 scaler_state
->scaler_users
&= ~(1 << idx
);
4463 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc
->pipe
, *scaler_id
, intel_plane
? "PLANE" : "CRTC",
4468 intel_plane
? intel_plane
->base
.base
.id
:
4469 intel_crtc
->base
.base
.id
, crtc_state
,
4470 scaler_state
->scaler_users
);
4477 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4478 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4480 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4481 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane
? "PLANE" : "CRTC",
4485 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4486 intel_crtc
->pipe
, idx
, src_w
, src_h
, dst_w
, dst_h
);
4490 /* check colorkey */
4491 if (WARN_ON(intel_plane
&&
4492 intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane
->base
.base
.id
, src_w
, src_h
, dst_w
, dst_h
);
4498 /* Check src format */
4500 switch (fb
->pixel_format
) {
4501 case DRM_FORMAT_RGB565
:
4502 case DRM_FORMAT_XBGR8888
:
4503 case DRM_FORMAT_XRGB8888
:
4504 case DRM_FORMAT_ABGR8888
:
4505 case DRM_FORMAT_ARGB8888
:
4506 case DRM_FORMAT_XRGB2101010
:
4507 case DRM_FORMAT_XBGR2101010
:
4508 case DRM_FORMAT_YUYV
:
4509 case DRM_FORMAT_YVYU
:
4510 case DRM_FORMAT_UYVY
:
4511 case DRM_FORMAT_VYUY
:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state
->scaler_users
|= (1 << idx
);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane
? "PLANE" : "CRTC",
4525 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4526 src_w
, src_h
, dst_w
, dst_h
, crtc_state
, scaler_state
->scaler_users
);
4530 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4532 struct drm_device
*dev
= crtc
->base
.dev
;
4533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4534 int pipe
= crtc
->pipe
;
4535 struct intel_crtc_scaler_state
*scaler_state
=
4536 &crtc
->config
->scaler_state
;
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc
, crtc
->config
, NULL
, NULL
, !enable
);
4542 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4543 skl_detach_scalers(crtc
);
4547 if (crtc
->config
->pch_pfit
.enabled
) {
4550 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4555 id
= scaler_state
->scaler_id
;
4556 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4557 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4565 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4567 struct drm_device
*dev
= crtc
->base
.dev
;
4568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 int pipe
= crtc
->pipe
;
4571 if (crtc
->config
->pch_pfit
.enabled
) {
4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4576 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4577 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4578 PF_PIPE_SEL_IVB(pipe
));
4580 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4581 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4582 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4586 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4588 struct drm_device
*dev
= crtc
->dev
;
4589 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4590 struct drm_plane
*plane
;
4591 struct intel_plane
*intel_plane
;
4593 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4594 intel_plane
= to_intel_plane(plane
);
4595 if (intel_plane
->pipe
== pipe
)
4596 intel_plane_restore(&intel_plane
->base
);
4600 void hsw_enable_ips(struct intel_crtc
*crtc
)
4602 struct drm_device
*dev
= crtc
->base
.dev
;
4603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4605 if (!crtc
->config
->ips_enabled
)
4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev
, crtc
->pipe
);
4611 assert_plane_enabled(dev_priv
, crtc
->plane
);
4612 if (IS_BROADWELL(dev
)) {
4613 mutex_lock(&dev_priv
->rps
.hw_lock
);
4614 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4615 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
4622 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4633 void hsw_disable_ips(struct intel_crtc
*crtc
)
4635 struct drm_device
*dev
= crtc
->base
.dev
;
4636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4638 if (!crtc
->config
->ips_enabled
)
4641 assert_plane_enabled(dev_priv
, crtc
->plane
);
4642 if (IS_BROADWELL(dev
)) {
4643 mutex_lock(&dev_priv
->rps
.hw_lock
);
4644 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4645 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
4650 I915_WRITE(IPS_CTL
, 0);
4651 POSTING_READ(IPS_CTL
);
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev
, crtc
->pipe
);
4658 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4659 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4661 struct drm_device
*dev
= crtc
->dev
;
4662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4664 enum pipe pipe
= intel_crtc
->pipe
;
4665 int palreg
= PALETTE(pipe
);
4667 bool reenable_ips
= false;
4669 /* The clocks have to be on to load the palette. */
4670 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4673 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4674 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4675 assert_dsi_pll_enabled(dev_priv
);
4677 assert_pll_enabled(dev_priv
, pipe
);
4680 /* use legacy palette for Ironlake */
4681 if (!HAS_GMCH_DISPLAY(dev
))
4682 palreg
= LGC_PALETTE(pipe
);
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4687 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4688 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4689 GAMMA_MODE_MODE_SPLIT
)) {
4690 hsw_disable_ips(intel_crtc
);
4691 reenable_ips
= true;
4694 for (i
= 0; i
< 256; i
++) {
4695 I915_WRITE(palreg
+ 4 * i
,
4696 (intel_crtc
->lut_r
[i
] << 16) |
4697 (intel_crtc
->lut_g
[i
] << 8) |
4698 intel_crtc
->lut_b
[i
]);
4702 hsw_enable_ips(intel_crtc
);
4705 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4707 if (intel_crtc
->overlay
) {
4708 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4711 mutex_lock(&dev
->struct_mutex
);
4712 dev_priv
->mm
.interruptible
= false;
4713 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4714 dev_priv
->mm
.interruptible
= true;
4715 mutex_unlock(&dev
->struct_mutex
);
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4734 intel_post_enable_primary(struct drm_crtc
*crtc
)
4736 struct drm_device
*dev
= crtc
->dev
;
4737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4739 int pipe
= intel_crtc
->pipe
;
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4746 if (IS_BROADWELL(dev
))
4747 intel_wait_for_vblank(dev
, pipe
);
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4755 hsw_enable_ips(intel_crtc
);
4757 mutex_lock(&dev
->struct_mutex
);
4758 intel_fbc_update(dev
);
4759 mutex_unlock(&dev
->struct_mutex
);
4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev
))
4773 i9xx_check_fifo_underruns(dev_priv
);
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4787 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4789 struct drm_device
*dev
= crtc
->dev
;
4790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4792 int pipe
= intel_crtc
->pipe
;
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4812 if (HAS_GMCH_DISPLAY(dev
))
4813 intel_set_memory_cxsr(dev_priv
, false);
4815 mutex_lock(&dev
->struct_mutex
);
4816 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4817 intel_fbc_disable(dev
);
4818 mutex_unlock(&dev
->struct_mutex
);
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4826 hsw_disable_ips(intel_crtc
);
4829 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4831 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4832 intel_enable_sprite_planes(crtc
);
4833 intel_crtc_update_cursor(crtc
, true);
4835 intel_post_enable_primary(crtc
);
4838 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4840 struct drm_device
*dev
= crtc
->dev
;
4841 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4842 struct intel_plane
*intel_plane
;
4843 int pipe
= intel_crtc
->pipe
;
4845 intel_crtc_wait_for_pending_flips(crtc
);
4847 intel_pre_disable_primary(crtc
);
4849 intel_crtc_dpms_overlay_disable(intel_crtc
);
4850 for_each_intel_plane(dev
, intel_plane
) {
4851 if (intel_plane
->pipe
== pipe
) {
4852 struct drm_crtc
*from
= intel_plane
->base
.crtc
;
4854 intel_plane
->disable_plane(&intel_plane
->base
,
4855 from
?: crtc
, true);
4860 * FIXME: Once we grow proper nuclear flip support out of this we need
4861 * to compute the mask of flip planes precisely. For the time being
4862 * consider this a flip to a NULL plane.
4864 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4867 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4869 struct drm_device
*dev
= crtc
->dev
;
4870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4872 struct intel_encoder
*encoder
;
4873 int pipe
= intel_crtc
->pipe
;
4875 WARN_ON(!crtc
->state
->enable
);
4877 if (intel_crtc
->active
)
4880 if (intel_crtc
->config
->has_pch_encoder
)
4881 intel_prepare_shared_dpll(intel_crtc
);
4883 if (intel_crtc
->config
->has_dp_encoder
)
4884 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4886 intel_set_pipe_timings(intel_crtc
);
4888 if (intel_crtc
->config
->has_pch_encoder
) {
4889 intel_cpu_transcoder_set_m_n(intel_crtc
,
4890 &intel_crtc
->config
->fdi_m_n
, NULL
);
4893 ironlake_set_pipeconf(crtc
);
4895 intel_crtc
->active
= true;
4897 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4898 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4900 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4901 if (encoder
->pre_enable
)
4902 encoder
->pre_enable(encoder
);
4904 if (intel_crtc
->config
->has_pch_encoder
) {
4905 /* Note: FDI PLL enabling _must_ be done before we enable the
4906 * cpu pipes, hence this is separate from all the other fdi/pch
4908 ironlake_fdi_pll_enable(intel_crtc
);
4910 assert_fdi_tx_disabled(dev_priv
, pipe
);
4911 assert_fdi_rx_disabled(dev_priv
, pipe
);
4914 ironlake_pfit_enable(intel_crtc
);
4917 * On ILK+ LUT must be loaded before the pipe is running but with
4920 intel_crtc_load_lut(crtc
);
4922 intel_update_watermarks(crtc
);
4923 intel_enable_pipe(intel_crtc
);
4925 if (intel_crtc
->config
->has_pch_encoder
)
4926 ironlake_pch_enable(crtc
);
4928 assert_vblank_disabled(crtc
);
4929 drm_crtc_vblank_on(crtc
);
4931 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4932 encoder
->enable(encoder
);
4934 if (HAS_PCH_CPT(dev
))
4935 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4938 /* IPS only exists on ULT machines and is tied to pipe A. */
4939 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4941 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4945 * This implements the workaround described in the "notes" section of the mode
4946 * set sequence documentation. When going from no pipes or single pipe to
4947 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4948 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4950 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4952 struct drm_device
*dev
= crtc
->base
.dev
;
4953 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4955 /* We want to get the other_active_crtc only if there's only 1 other
4957 for_each_intel_crtc(dev
, crtc_it
) {
4958 if (!crtc_it
->active
|| crtc_it
== crtc
)
4961 if (other_active_crtc
)
4964 other_active_crtc
= crtc_it
;
4966 if (!other_active_crtc
)
4969 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4970 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4973 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4975 struct drm_device
*dev
= crtc
->dev
;
4976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4977 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4978 struct intel_encoder
*encoder
;
4979 int pipe
= intel_crtc
->pipe
;
4981 WARN_ON(!crtc
->state
->enable
);
4983 if (intel_crtc
->active
)
4986 if (intel_crtc_to_shared_dpll(intel_crtc
))
4987 intel_enable_shared_dpll(intel_crtc
);
4989 if (intel_crtc
->config
->has_dp_encoder
)
4990 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4992 intel_set_pipe_timings(intel_crtc
);
4994 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4995 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4996 intel_crtc
->config
->pixel_multiplier
- 1);
4999 if (intel_crtc
->config
->has_pch_encoder
) {
5000 intel_cpu_transcoder_set_m_n(intel_crtc
,
5001 &intel_crtc
->config
->fdi_m_n
, NULL
);
5004 haswell_set_pipeconf(crtc
);
5006 intel_set_pipe_csc(crtc
);
5008 intel_crtc
->active
= true;
5010 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5011 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5012 if (encoder
->pre_enable
)
5013 encoder
->pre_enable(encoder
);
5015 if (intel_crtc
->config
->has_pch_encoder
) {
5016 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5018 dev_priv
->display
.fdi_link_train(crtc
);
5021 intel_ddi_enable_pipe_clock(intel_crtc
);
5023 if (INTEL_INFO(dev
)->gen
== 9)
5024 skylake_pfit_update(intel_crtc
, 1);
5025 else if (INTEL_INFO(dev
)->gen
< 9)
5026 ironlake_pfit_enable(intel_crtc
);
5028 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5031 * On ILK+ LUT must be loaded before the pipe is running but with
5034 intel_crtc_load_lut(crtc
);
5036 intel_ddi_set_pipe_settings(crtc
);
5037 intel_ddi_enable_transcoder_func(crtc
);
5039 intel_update_watermarks(crtc
);
5040 intel_enable_pipe(intel_crtc
);
5042 if (intel_crtc
->config
->has_pch_encoder
)
5043 lpt_pch_enable(crtc
);
5045 if (intel_crtc
->config
->dp_encoder_is_mst
)
5046 intel_ddi_set_vc_payload_alloc(crtc
, true);
5048 assert_vblank_disabled(crtc
);
5049 drm_crtc_vblank_on(crtc
);
5051 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5052 encoder
->enable(encoder
);
5053 intel_opregion_notify_encoder(encoder
, true);
5056 /* If we change the relative order between pipe/planes enabling, we need
5057 * to change the workaround. */
5058 haswell_mode_set_planes_workaround(intel_crtc
);
5061 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5063 struct drm_device
*dev
= crtc
->base
.dev
;
5064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5065 int pipe
= crtc
->pipe
;
5067 /* To avoid upsetting the power well on haswell only disable the pfit if
5068 * it's in use. The hw state code will make sure we get this right. */
5069 if (crtc
->config
->pch_pfit
.enabled
) {
5070 I915_WRITE(PF_CTL(pipe
), 0);
5071 I915_WRITE(PF_WIN_POS(pipe
), 0);
5072 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5076 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5078 struct drm_device
*dev
= crtc
->dev
;
5079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5080 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5081 struct intel_encoder
*encoder
;
5082 int pipe
= intel_crtc
->pipe
;
5085 if (!intel_crtc
->active
)
5088 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5089 encoder
->disable(encoder
);
5091 drm_crtc_vblank_off(crtc
);
5092 assert_vblank_disabled(crtc
);
5094 if (intel_crtc
->config
->has_pch_encoder
)
5095 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5097 intel_disable_pipe(intel_crtc
);
5099 ironlake_pfit_disable(intel_crtc
);
5101 if (intel_crtc
->config
->has_pch_encoder
)
5102 ironlake_fdi_disable(crtc
);
5104 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5105 if (encoder
->post_disable
)
5106 encoder
->post_disable(encoder
);
5108 if (intel_crtc
->config
->has_pch_encoder
) {
5109 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5111 if (HAS_PCH_CPT(dev
)) {
5112 /* disable TRANS_DP_CTL */
5113 reg
= TRANS_DP_CTL(pipe
);
5114 temp
= I915_READ(reg
);
5115 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5116 TRANS_DP_PORT_SEL_MASK
);
5117 temp
|= TRANS_DP_PORT_SEL_NONE
;
5118 I915_WRITE(reg
, temp
);
5120 /* disable DPLL_SEL */
5121 temp
= I915_READ(PCH_DPLL_SEL
);
5122 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5123 I915_WRITE(PCH_DPLL_SEL
, temp
);
5126 /* disable PCH DPLL */
5127 intel_disable_shared_dpll(intel_crtc
);
5129 ironlake_fdi_pll_disable(intel_crtc
);
5132 intel_crtc
->active
= false;
5133 intel_update_watermarks(crtc
);
5135 mutex_lock(&dev
->struct_mutex
);
5136 intel_fbc_update(dev
);
5137 mutex_unlock(&dev
->struct_mutex
);
5140 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5142 struct drm_device
*dev
= crtc
->dev
;
5143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5144 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5145 struct intel_encoder
*encoder
;
5146 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5148 if (!intel_crtc
->active
)
5151 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5152 intel_opregion_notify_encoder(encoder
, false);
5153 encoder
->disable(encoder
);
5156 drm_crtc_vblank_off(crtc
);
5157 assert_vblank_disabled(crtc
);
5159 if (intel_crtc
->config
->has_pch_encoder
)
5160 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5162 intel_disable_pipe(intel_crtc
);
5164 if (intel_crtc
->config
->dp_encoder_is_mst
)
5165 intel_ddi_set_vc_payload_alloc(crtc
, false);
5167 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5169 if (INTEL_INFO(dev
)->gen
== 9)
5170 skylake_pfit_update(intel_crtc
, 0);
5171 else if (INTEL_INFO(dev
)->gen
< 9)
5172 ironlake_pfit_disable(intel_crtc
);
5174 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5176 intel_ddi_disable_pipe_clock(intel_crtc
);
5178 if (intel_crtc
->config
->has_pch_encoder
) {
5179 lpt_disable_pch_transcoder(dev_priv
);
5180 intel_ddi_fdi_disable(crtc
);
5183 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5184 if (encoder
->post_disable
)
5185 encoder
->post_disable(encoder
);
5187 intel_crtc
->active
= false;
5188 intel_update_watermarks(crtc
);
5190 mutex_lock(&dev
->struct_mutex
);
5191 intel_fbc_update(dev
);
5192 mutex_unlock(&dev
->struct_mutex
);
5194 if (intel_crtc_to_shared_dpll(intel_crtc
))
5195 intel_disable_shared_dpll(intel_crtc
);
5198 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
5200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5201 intel_put_shared_dpll(intel_crtc
);
5205 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5207 struct drm_device
*dev
= crtc
->base
.dev
;
5208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5209 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5211 if (!pipe_config
->gmch_pfit
.control
)
5215 * The panel fitter should only be adjusted whilst the pipe is disabled,
5216 * according to register description and PRM.
5218 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5219 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5221 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5222 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5224 /* Border color in case we don't scale up to the full screen. Black by
5225 * default, change to something else for debugging. */
5226 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5229 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5233 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5235 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5237 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5239 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5242 return POWER_DOMAIN_PORT_OTHER
;
5246 #define for_each_power_domain(domain, mask) \
5247 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5248 if ((1 << (domain)) & (mask))
5250 enum intel_display_power_domain
5251 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5253 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5254 struct intel_digital_port
*intel_dig_port
;
5256 switch (intel_encoder
->type
) {
5257 case INTEL_OUTPUT_UNKNOWN
:
5258 /* Only DDI platforms should ever use this output type */
5259 WARN_ON_ONCE(!HAS_DDI(dev
));
5260 case INTEL_OUTPUT_DISPLAYPORT
:
5261 case INTEL_OUTPUT_HDMI
:
5262 case INTEL_OUTPUT_EDP
:
5263 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5264 return port_to_power_domain(intel_dig_port
->port
);
5265 case INTEL_OUTPUT_DP_MST
:
5266 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5267 return port_to_power_domain(intel_dig_port
->port
);
5268 case INTEL_OUTPUT_ANALOG
:
5269 return POWER_DOMAIN_PORT_CRT
;
5270 case INTEL_OUTPUT_DSI
:
5271 return POWER_DOMAIN_PORT_DSI
;
5273 return POWER_DOMAIN_PORT_OTHER
;
5277 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5279 struct drm_device
*dev
= crtc
->dev
;
5280 struct intel_encoder
*intel_encoder
;
5281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5282 enum pipe pipe
= intel_crtc
->pipe
;
5284 enum transcoder transcoder
;
5286 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5288 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5289 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5290 if (intel_crtc
->config
->pch_pfit
.enabled
||
5291 intel_crtc
->config
->pch_pfit
.force_thru
)
5292 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5294 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5295 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5300 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5302 struct drm_device
*dev
= state
->dev
;
5303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5304 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5305 struct intel_crtc
*crtc
;
5308 * First get all needed power domains, then put all unneeded, to avoid
5309 * any unnecessary toggling of the power wells.
5311 for_each_intel_crtc(dev
, crtc
) {
5312 enum intel_display_power_domain domain
;
5314 if (!crtc
->base
.state
->enable
)
5317 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5319 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5320 intel_display_power_get(dev_priv
, domain
);
5323 if (dev_priv
->display
.modeset_global_resources
)
5324 dev_priv
->display
.modeset_global_resources(state
);
5326 for_each_intel_crtc(dev
, crtc
) {
5327 enum intel_display_power_domain domain
;
5329 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5330 intel_display_power_put(dev_priv
, domain
);
5332 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5335 intel_display_set_init_power(dev_priv
, false);
5338 void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5343 uint32_t current_freq
;
5346 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5347 switch (frequency
) {
5349 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5350 ratio
= BXT_DE_PLL_RATIO(60);
5353 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5354 ratio
= BXT_DE_PLL_RATIO(60);
5357 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5358 ratio
= BXT_DE_PLL_RATIO(60);
5361 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5362 ratio
= BXT_DE_PLL_RATIO(60);
5365 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5366 ratio
= BXT_DE_PLL_RATIO(65);
5370 * Bypass frequency with DE PLL disabled. Init ratio, divider
5371 * to suppress GCC warning.
5377 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5382 mutex_lock(&dev_priv
->rps
.hw_lock
);
5383 /* Inform power controller of upcoming frequency change */
5384 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5386 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5389 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5394 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5395 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5396 current_freq
= current_freq
* 500 + 1000;
5399 * DE PLL has to be disabled when
5400 * - setting to 19.2MHz (bypass, PLL isn't used)
5401 * - before setting to 624MHz (PLL needs toggling)
5402 * - before setting to any frequency from 624MHz (PLL needs toggling)
5404 if (frequency
== 19200 || frequency
== 624000 ||
5405 current_freq
== 624000) {
5406 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5408 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5410 DRM_ERROR("timout waiting for DE PLL unlock\n");
5413 if (frequency
!= 19200) {
5416 val
= I915_READ(BXT_DE_PLL_CTL
);
5417 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5419 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5421 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5423 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5424 DRM_ERROR("timeout waiting for DE PLL lock\n");
5426 val
= I915_READ(CDCLK_CTL
);
5427 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5430 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5433 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5434 if (frequency
>= 500000)
5435 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5437 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5438 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5439 val
|= (frequency
- 1000) / 500;
5440 I915_WRITE(CDCLK_CTL
, val
);
5443 mutex_lock(&dev_priv
->rps
.hw_lock
);
5444 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5445 DIV_ROUND_UP(frequency
, 25000));
5446 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5449 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5454 dev_priv
->cdclk_freq
= frequency
;
5457 void broxton_init_cdclk(struct drm_device
*dev
)
5459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5463 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5464 * or else the reset will hang because there is no PCH to respond.
5465 * Move the handshake programming to initialization sequence.
5466 * Previously was left up to BIOS.
5468 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5469 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5470 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5472 /* Enable PG1 for cdclk */
5473 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5475 /* check if cd clock is enabled */
5476 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5477 DRM_DEBUG_KMS("Display already initialized\n");
5483 * - The initial CDCLK needs to be read from VBT.
5484 * Need to make this change after VBT has changes for BXT.
5485 * - check if setting the max (or any) cdclk freq is really necessary
5486 * here, it belongs to modeset time
5488 broxton_set_cdclk(dev
, 624000);
5490 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5491 POSTING_READ(DBUF_CTL
);
5495 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5496 DRM_ERROR("DBuf power enable timeout!\n");
5499 void broxton_uninit_cdclk(struct drm_device
*dev
)
5501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5503 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5504 POSTING_READ(DBUF_CTL
);
5508 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5509 DRM_ERROR("DBuf power disable timeout!\n");
5511 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5512 broxton_set_cdclk(dev
, 19200);
5514 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5517 static const struct skl_cdclk_entry
{
5520 } skl_cdclk_frequencies
[] = {
5521 { .freq
= 308570, .vco
= 8640 },
5522 { .freq
= 337500, .vco
= 8100 },
5523 { .freq
= 432000, .vco
= 8640 },
5524 { .freq
= 450000, .vco
= 8100 },
5525 { .freq
= 540000, .vco
= 8100 },
5526 { .freq
= 617140, .vco
= 8640 },
5527 { .freq
= 675000, .vco
= 8100 },
5530 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5532 return (freq
- 1000) / 500;
5535 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5539 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5540 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5542 if (e
->freq
== freq
)
5550 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5552 unsigned int min_freq
;
5555 /* select the minimum CDCLK before enabling DPLL 0 */
5556 val
= I915_READ(CDCLK_CTL
);
5557 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5558 val
|= CDCLK_FREQ_337_308
;
5560 if (required_vco
== 8640)
5565 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5567 I915_WRITE(CDCLK_CTL
, val
);
5568 POSTING_READ(CDCLK_CTL
);
5571 * We always enable DPLL0 with the lowest link rate possible, but still
5572 * taking into account the VCO required to operate the eDP panel at the
5573 * desired frequency. The usual DP link rates operate with a VCO of
5574 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5575 * The modeset code is responsible for the selection of the exact link
5576 * rate later on, with the constraint of choosing a frequency that
5577 * works with required_vco.
5579 val
= I915_READ(DPLL_CTRL1
);
5581 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5582 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5583 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5584 if (required_vco
== 8640)
5585 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5588 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5591 I915_WRITE(DPLL_CTRL1
, val
);
5592 POSTING_READ(DPLL_CTRL1
);
5594 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5596 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5597 DRM_ERROR("DPLL0 not locked\n");
5600 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5605 /* inform PCU we want to change CDCLK */
5606 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5607 mutex_lock(&dev_priv
->rps
.hw_lock
);
5608 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5609 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5611 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5614 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5618 for (i
= 0; i
< 15; i
++) {
5619 if (skl_cdclk_pcu_ready(dev_priv
))
5627 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5629 u32 freq_select
, pcu_ack
;
5631 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5633 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5634 DRM_ERROR("failed to inform PCU about cdclk change\n");
5642 freq_select
= CDCLK_FREQ_450_432
;
5646 freq_select
= CDCLK_FREQ_540
;
5652 freq_select
= CDCLK_FREQ_337_308
;
5657 freq_select
= CDCLK_FREQ_675_617
;
5662 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5663 POSTING_READ(CDCLK_CTL
);
5665 /* inform PCU of the change */
5666 mutex_lock(&dev_priv
->rps
.hw_lock
);
5667 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5668 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5671 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5673 /* disable DBUF power */
5674 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5675 POSTING_READ(DBUF_CTL
);
5679 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5680 DRM_ERROR("DBuf power disable timeout\n");
5683 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5684 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5685 DRM_ERROR("Couldn't disable DPLL0\n");
5687 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5690 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5693 unsigned int required_vco
;
5695 /* enable PCH reset handshake */
5696 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5697 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
5699 /* enable PG1 and Misc I/O */
5700 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5702 /* DPLL0 already enabed !? */
5703 if (I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
) {
5704 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5709 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5710 skl_dpll0_enable(dev_priv
, required_vco
);
5712 /* set CDCLK to the frequency the BIOS chose */
5713 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5715 /* enable DBUF power */
5716 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5717 POSTING_READ(DBUF_CTL
);
5721 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5722 DRM_ERROR("DBuf power enable timeout\n");
5725 /* returns HPLL frequency in kHz */
5726 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5728 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5730 /* Obtain SKU information */
5731 mutex_lock(&dev_priv
->sb_lock
);
5732 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5733 CCK_FUSE_HPLL_FREQ_MASK
;
5734 mutex_unlock(&dev_priv
->sb_lock
);
5736 return vco_freq
[hpll_freq
] * 1000;
5739 static void vlv_update_cdclk(struct drm_device
*dev
)
5741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5743 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5744 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5745 dev_priv
->cdclk_freq
);
5748 * Program the gmbus_freq based on the cdclk frequency.
5749 * BSpec erroneously claims we should aim for 4MHz, but
5750 * in fact 1MHz is the correct frequency.
5752 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5755 /* Adjust CDclk dividers to allow high res or save power if possible */
5756 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5761 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5762 != dev_priv
->cdclk_freq
);
5764 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5766 else if (cdclk
== 266667)
5771 mutex_lock(&dev_priv
->rps
.hw_lock
);
5772 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5773 val
&= ~DSPFREQGUAR_MASK
;
5774 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5775 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5776 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5777 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5779 DRM_ERROR("timed out waiting for CDclk change\n");
5781 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5783 if (cdclk
== 400000) {
5786 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5788 mutex_lock(&dev_priv
->sb_lock
);
5789 /* adjust cdclk divider */
5790 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5791 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5793 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5795 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5796 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5798 DRM_ERROR("timed out waiting for CDclk change\n");
5799 mutex_unlock(&dev_priv
->sb_lock
);
5802 mutex_lock(&dev_priv
->sb_lock
);
5803 /* adjust self-refresh exit latency value */
5804 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5808 * For high bandwidth configs, we set a higher latency in the bunit
5809 * so that the core display fetch happens in time to avoid underruns.
5811 if (cdclk
== 400000)
5812 val
|= 4500 / 250; /* 4.5 usec */
5814 val
|= 3000 / 250; /* 3.0 usec */
5815 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5816 mutex_unlock(&dev_priv
->sb_lock
);
5818 vlv_update_cdclk(dev
);
5821 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5826 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5827 != dev_priv
->cdclk_freq
);
5836 MISSING_CASE(cdclk
);
5841 * Specs are full of misinformation, but testing on actual
5842 * hardware has shown that we just need to write the desired
5843 * CCK divider into the Punit register.
5845 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5847 mutex_lock(&dev_priv
->rps
.hw_lock
);
5848 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5849 val
&= ~DSPFREQGUAR_MASK_CHV
;
5850 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5851 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5852 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5853 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5855 DRM_ERROR("timed out waiting for CDclk change\n");
5857 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5859 vlv_update_cdclk(dev
);
5862 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5865 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5866 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5869 * Really only a few cases to deal with, as only 4 CDclks are supported:
5872 * 320/333MHz (depends on HPLL freq)
5874 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5875 * of the lower bin and adjust if needed.
5877 * We seem to get an unstable or solid color picture at 200MHz.
5878 * Not sure what's wrong. For now use 200MHz only when all pipes
5881 if (!IS_CHERRYVIEW(dev_priv
) &&
5882 max_pixclk
> freq_320
*limit
/100)
5884 else if (max_pixclk
> 266667*limit
/100)
5886 else if (max_pixclk
> 0)
5892 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5897 * - remove the guardband, it's not needed on BXT
5898 * - set 19.2MHz bypass frequency if there are no active pipes
5900 if (max_pixclk
> 576000*9/10)
5902 else if (max_pixclk
> 384000*9/10)
5904 else if (max_pixclk
> 288000*9/10)
5906 else if (max_pixclk
> 144000*9/10)
5912 /* Compute the max pixel clock for new configuration. Uses atomic state if
5913 * that's non-NULL, look at current state otherwise. */
5914 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5915 struct drm_atomic_state
*state
)
5917 struct intel_crtc
*intel_crtc
;
5918 struct intel_crtc_state
*crtc_state
;
5921 for_each_intel_crtc(dev
, intel_crtc
) {
5924 intel_atomic_get_crtc_state(state
, intel_crtc
);
5926 crtc_state
= intel_crtc
->config
;
5927 if (IS_ERR(crtc_state
))
5928 return PTR_ERR(crtc_state
);
5930 if (!crtc_state
->base
.enable
)
5933 max_pixclk
= max(max_pixclk
,
5934 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5940 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
)
5942 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5943 struct drm_crtc
*crtc
;
5944 struct drm_crtc_state
*crtc_state
;
5945 int max_pixclk
= intel_mode_max_pixclk(state
->dev
, state
);
5951 if (IS_VALLEYVIEW(dev_priv
))
5952 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5954 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
5956 if (cdclk
== dev_priv
->cdclk_freq
)
5959 /* add all active pipes to the state */
5960 for_each_crtc(state
->dev
, crtc
) {
5961 if (!crtc
->state
->enable
)
5964 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
5965 if (IS_ERR(crtc_state
))
5966 return PTR_ERR(crtc_state
);
5969 /* disable/enable all currently active pipes while we change cdclk */
5970 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
5971 if (crtc_state
->enable
)
5972 crtc_state
->mode_changed
= true;
5977 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5979 unsigned int credits
, default_credits
;
5981 if (IS_CHERRYVIEW(dev_priv
))
5982 default_credits
= PFI_CREDIT(12);
5984 default_credits
= PFI_CREDIT(8);
5986 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5987 /* CHV suggested value is 31 or 63 */
5988 if (IS_CHERRYVIEW(dev_priv
))
5989 credits
= PFI_CREDIT_31
;
5991 credits
= PFI_CREDIT(15);
5993 credits
= default_credits
;
5997 * WA - write default credits before re-programming
5998 * FIXME: should we also set the resend bit here?
6000 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6003 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6004 credits
| PFI_CREDIT_RESEND
);
6007 * FIXME is this guaranteed to clear
6008 * immediately or should we poll for it?
6010 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6013 static void valleyview_modeset_global_resources(struct drm_atomic_state
*old_state
)
6015 struct drm_device
*dev
= old_state
->dev
;
6016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6017 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
6020 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6022 if (WARN_ON(max_pixclk
< 0))
6025 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6027 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
6029 * FIXME: We can end up here with all power domains off, yet
6030 * with a CDCLK frequency other than the minimum. To account
6031 * for this take the PIPE-A power domain, which covers the HW
6032 * blocks needed for the following programming. This can be
6033 * removed once it's guaranteed that we get here either with
6034 * the minimum CDCLK set, or the required power domains
6037 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6039 if (IS_CHERRYVIEW(dev
))
6040 cherryview_set_cdclk(dev
, req_cdclk
);
6042 valleyview_set_cdclk(dev
, req_cdclk
);
6044 vlv_program_pfi_credits(dev_priv
);
6046 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6050 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6052 struct drm_device
*dev
= crtc
->dev
;
6053 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6055 struct intel_encoder
*encoder
;
6056 int pipe
= intel_crtc
->pipe
;
6059 WARN_ON(!crtc
->state
->enable
);
6061 if (intel_crtc
->active
)
6064 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
6067 if (IS_CHERRYVIEW(dev
))
6068 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6070 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6073 if (intel_crtc
->config
->has_dp_encoder
)
6074 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6076 intel_set_pipe_timings(intel_crtc
);
6078 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6081 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6082 I915_WRITE(CHV_CANVAS(pipe
), 0);
6085 i9xx_set_pipeconf(intel_crtc
);
6087 intel_crtc
->active
= true;
6089 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6091 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6092 if (encoder
->pre_pll_enable
)
6093 encoder
->pre_pll_enable(encoder
);
6096 if (IS_CHERRYVIEW(dev
))
6097 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6099 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6102 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6103 if (encoder
->pre_enable
)
6104 encoder
->pre_enable(encoder
);
6106 i9xx_pfit_enable(intel_crtc
);
6108 intel_crtc_load_lut(crtc
);
6110 intel_update_watermarks(crtc
);
6111 intel_enable_pipe(intel_crtc
);
6113 assert_vblank_disabled(crtc
);
6114 drm_crtc_vblank_on(crtc
);
6116 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6117 encoder
->enable(encoder
);
6120 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6122 struct drm_device
*dev
= crtc
->base
.dev
;
6123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6125 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6126 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6129 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6131 struct drm_device
*dev
= crtc
->dev
;
6132 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6134 struct intel_encoder
*encoder
;
6135 int pipe
= intel_crtc
->pipe
;
6137 WARN_ON(!crtc
->state
->enable
);
6139 if (intel_crtc
->active
)
6142 i9xx_set_pll_dividers(intel_crtc
);
6144 if (intel_crtc
->config
->has_dp_encoder
)
6145 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6147 intel_set_pipe_timings(intel_crtc
);
6149 i9xx_set_pipeconf(intel_crtc
);
6151 intel_crtc
->active
= true;
6154 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6156 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6157 if (encoder
->pre_enable
)
6158 encoder
->pre_enable(encoder
);
6160 i9xx_enable_pll(intel_crtc
);
6162 i9xx_pfit_enable(intel_crtc
);
6164 intel_crtc_load_lut(crtc
);
6166 intel_update_watermarks(crtc
);
6167 intel_enable_pipe(intel_crtc
);
6169 assert_vblank_disabled(crtc
);
6170 drm_crtc_vblank_on(crtc
);
6172 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6173 encoder
->enable(encoder
);
6176 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6178 struct drm_device
*dev
= crtc
->base
.dev
;
6179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6181 if (!crtc
->config
->gmch_pfit
.control
)
6184 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6186 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6187 I915_READ(PFIT_CONTROL
));
6188 I915_WRITE(PFIT_CONTROL
, 0);
6191 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6193 struct drm_device
*dev
= crtc
->dev
;
6194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6196 struct intel_encoder
*encoder
;
6197 int pipe
= intel_crtc
->pipe
;
6199 if (!intel_crtc
->active
)
6203 * On gen2 planes are double buffered but the pipe isn't, so we must
6204 * wait for planes to fully turn off before disabling the pipe.
6205 * We also need to wait on all gmch platforms because of the
6206 * self-refresh mode constraint explained above.
6208 intel_wait_for_vblank(dev
, pipe
);
6210 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6211 encoder
->disable(encoder
);
6213 drm_crtc_vblank_off(crtc
);
6214 assert_vblank_disabled(crtc
);
6216 intel_disable_pipe(intel_crtc
);
6218 i9xx_pfit_disable(intel_crtc
);
6220 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6221 if (encoder
->post_disable
)
6222 encoder
->post_disable(encoder
);
6224 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6225 if (IS_CHERRYVIEW(dev
))
6226 chv_disable_pll(dev_priv
, pipe
);
6227 else if (IS_VALLEYVIEW(dev
))
6228 vlv_disable_pll(dev_priv
, pipe
);
6230 i9xx_disable_pll(intel_crtc
);
6234 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6236 intel_crtc
->active
= false;
6237 intel_update_watermarks(crtc
);
6239 mutex_lock(&dev
->struct_mutex
);
6240 intel_fbc_update(dev
);
6241 mutex_unlock(&dev
->struct_mutex
);
6244 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
6248 /* Master function to enable/disable CRTC and corresponding power wells */
6249 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6251 struct drm_device
*dev
= crtc
->dev
;
6252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6253 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6254 enum intel_display_power_domain domain
;
6255 unsigned long domains
;
6258 if (!intel_crtc
->active
) {
6259 domains
= get_crtc_power_domains(crtc
);
6260 for_each_power_domain(domain
, domains
)
6261 intel_display_power_get(dev_priv
, domain
);
6262 intel_crtc
->enabled_power_domains
= domains
;
6264 dev_priv
->display
.crtc_enable(crtc
);
6265 intel_crtc_enable_planes(crtc
);
6268 if (intel_crtc
->active
) {
6269 intel_crtc_disable_planes(crtc
);
6270 dev_priv
->display
.crtc_disable(crtc
);
6272 domains
= intel_crtc
->enabled_power_domains
;
6273 for_each_power_domain(domain
, domains
)
6274 intel_display_power_put(dev_priv
, domain
);
6275 intel_crtc
->enabled_power_domains
= 0;
6281 * Sets the power management mode of the pipe and plane.
6283 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6285 struct drm_device
*dev
= crtc
->dev
;
6286 struct intel_encoder
*intel_encoder
;
6287 bool enable
= false;
6289 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6290 enable
|= intel_encoder
->connectors_active
;
6292 intel_crtc_control(crtc
, enable
);
6294 crtc
->state
->active
= enable
;
6297 static void intel_crtc_disable(struct drm_crtc
*crtc
)
6299 struct drm_device
*dev
= crtc
->dev
;
6300 struct drm_connector
*connector
;
6301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6303 /* crtc should still be enabled when we disable it. */
6304 WARN_ON(!crtc
->state
->enable
);
6306 intel_crtc_disable_planes(crtc
);
6307 dev_priv
->display
.crtc_disable(crtc
);
6308 dev_priv
->display
.off(crtc
);
6310 drm_plane_helper_disable(crtc
->primary
);
6312 /* Update computed state. */
6313 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6314 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6317 if (connector
->encoder
->crtc
!= crtc
)
6320 connector
->dpms
= DRM_MODE_DPMS_OFF
;
6321 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
6325 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6327 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6329 drm_encoder_cleanup(encoder
);
6330 kfree(intel_encoder
);
6333 /* Simple dpms helper for encoders with just one connector, no cloning and only
6334 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6335 * state of the entire output pipe. */
6336 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6338 if (mode
== DRM_MODE_DPMS_ON
) {
6339 encoder
->connectors_active
= true;
6341 intel_crtc_update_dpms(encoder
->base
.crtc
);
6343 encoder
->connectors_active
= false;
6345 intel_crtc_update_dpms(encoder
->base
.crtc
);
6349 /* Cross check the actual hw state with our own modeset state tracking (and it's
6350 * internal consistency). */
6351 static void intel_connector_check_state(struct intel_connector
*connector
)
6353 if (connector
->get_hw_state(connector
)) {
6354 struct intel_encoder
*encoder
= connector
->encoder
;
6355 struct drm_crtc
*crtc
;
6356 bool encoder_enabled
;
6359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6360 connector
->base
.base
.id
,
6361 connector
->base
.name
);
6363 /* there is no real hw state for MST connectors */
6364 if (connector
->mst_port
)
6367 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6368 "wrong connector dpms state\n");
6369 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6370 "active connector not linked to encoder\n");
6373 I915_STATE_WARN(!encoder
->connectors_active
,
6374 "encoder->connectors_active not set\n");
6376 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6377 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6378 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6381 crtc
= encoder
->base
.crtc
;
6383 I915_STATE_WARN(!crtc
->state
->enable
,
6384 "crtc not enabled\n");
6385 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6386 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6387 "encoder active on the wrong pipe\n");
6392 int intel_connector_init(struct intel_connector
*connector
)
6394 struct drm_connector_state
*connector_state
;
6396 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6397 if (!connector_state
)
6400 connector
->base
.state
= connector_state
;
6404 struct intel_connector
*intel_connector_alloc(void)
6406 struct intel_connector
*connector
;
6408 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6412 if (intel_connector_init(connector
) < 0) {
6420 /* Even simpler default implementation, if there's really no special case to
6422 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6424 /* All the simple cases only support two dpms states. */
6425 if (mode
!= DRM_MODE_DPMS_ON
)
6426 mode
= DRM_MODE_DPMS_OFF
;
6428 if (mode
== connector
->dpms
)
6431 connector
->dpms
= mode
;
6433 /* Only need to change hw state when actually enabled */
6434 if (connector
->encoder
)
6435 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6437 intel_modeset_check_state(connector
->dev
);
6440 /* Simple connector->get_hw_state implementation for encoders that support only
6441 * one connector and no cloning and hence the encoder state determines the state
6442 * of the connector. */
6443 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6446 struct intel_encoder
*encoder
= connector
->encoder
;
6448 return encoder
->get_hw_state(encoder
, &pipe
);
6451 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6453 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6454 return crtc_state
->fdi_lanes
;
6459 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6460 struct intel_crtc_state
*pipe_config
)
6462 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6463 struct intel_crtc
*other_crtc
;
6464 struct intel_crtc_state
*other_crtc_state
;
6466 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6467 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6468 if (pipe_config
->fdi_lanes
> 4) {
6469 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6470 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6474 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6475 if (pipe_config
->fdi_lanes
> 2) {
6476 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6477 pipe_config
->fdi_lanes
);
6484 if (INTEL_INFO(dev
)->num_pipes
== 2)
6487 /* Ivybridge 3 pipe is really complicated */
6492 if (pipe_config
->fdi_lanes
<= 2)
6495 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6497 intel_atomic_get_crtc_state(state
, other_crtc
);
6498 if (IS_ERR(other_crtc_state
))
6499 return PTR_ERR(other_crtc_state
);
6501 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6502 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6503 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6508 if (pipe_config
->fdi_lanes
> 2) {
6509 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6510 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6514 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6516 intel_atomic_get_crtc_state(state
, other_crtc
);
6517 if (IS_ERR(other_crtc_state
))
6518 return PTR_ERR(other_crtc_state
);
6520 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6521 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6531 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6532 struct intel_crtc_state
*pipe_config
)
6534 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6535 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6536 int lane
, link_bw
, fdi_dotclock
, ret
;
6537 bool needs_recompute
= false;
6540 /* FDI is a binary signal running at ~2.7GHz, encoding
6541 * each output octet as 10 bits. The actual frequency
6542 * is stored as a divider into a 100MHz clock, and the
6543 * mode pixel clock is stored in units of 1KHz.
6544 * Hence the bw of each lane in terms of the mode signal
6547 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6549 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6551 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6552 pipe_config
->pipe_bpp
);
6554 pipe_config
->fdi_lanes
= lane
;
6556 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6557 link_bw
, &pipe_config
->fdi_m_n
);
6559 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6560 intel_crtc
->pipe
, pipe_config
);
6561 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6562 pipe_config
->pipe_bpp
-= 2*3;
6563 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6564 pipe_config
->pipe_bpp
);
6565 needs_recompute
= true;
6566 pipe_config
->bw_constrained
= true;
6571 if (needs_recompute
)
6577 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6578 struct intel_crtc_state
*pipe_config
)
6580 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6581 hsw_crtc_supports_ips(crtc
) &&
6582 pipe_config
->pipe_bpp
<= 24;
6585 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6586 struct intel_crtc_state
*pipe_config
)
6588 struct drm_device
*dev
= crtc
->base
.dev
;
6589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6590 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6593 /* FIXME should check pixel clock limits on all platforms */
6594 if (INTEL_INFO(dev
)->gen
< 4) {
6596 dev_priv
->display
.get_display_clock_speed(dev
);
6599 * Enable pixel doubling when the dot clock
6600 * is > 90% of the (display) core speed.
6602 * GDG double wide on either pipe,
6603 * otherwise pipe A only.
6605 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6606 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6608 pipe_config
->double_wide
= true;
6611 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6616 * Pipe horizontal size must be even in:
6618 * - LVDS dual channel mode
6619 * - Double wide pipe
6621 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6622 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6623 pipe_config
->pipe_src_w
&= ~1;
6625 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6626 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6628 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6629 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6633 hsw_compute_ips_config(crtc
, pipe_config
);
6635 if (pipe_config
->has_pch_encoder
)
6636 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6638 /* FIXME: remove below call once atomic mode set is place and all crtc
6639 * related checks called from atomic_crtc_check function */
6641 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6642 crtc
, pipe_config
->base
.state
);
6643 ret
= intel_atomic_setup_scalers(dev
, crtc
, pipe_config
);
6648 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6650 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6651 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6652 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6655 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
6656 WARN(1, "LCPLL1 not enabled\n");
6657 return 24000; /* 24MHz is the cd freq with NSSC ref */
6660 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6663 linkrate
= (I915_READ(DPLL_CTRL1
) &
6664 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6666 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6667 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6669 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6670 case CDCLK_FREQ_450_432
:
6672 case CDCLK_FREQ_337_308
:
6674 case CDCLK_FREQ_675_617
:
6677 WARN(1, "Unknown cd freq selection\n");
6681 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6682 case CDCLK_FREQ_450_432
:
6684 case CDCLK_FREQ_337_308
:
6686 case CDCLK_FREQ_675_617
:
6689 WARN(1, "Unknown cd freq selection\n");
6693 /* error case, do as if DPLL0 isn't enabled */
6697 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6700 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6701 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6703 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6705 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6707 else if (freq
== LCPLL_CLK_FREQ_450
)
6709 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6711 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6717 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6720 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6721 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6723 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6725 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6727 else if (freq
== LCPLL_CLK_FREQ_450
)
6729 else if (IS_HSW_ULT(dev
))
6735 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6741 if (dev_priv
->hpll_freq
== 0)
6742 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6744 mutex_lock(&dev_priv
->sb_lock
);
6745 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6746 mutex_unlock(&dev_priv
->sb_lock
);
6748 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6750 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6751 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6752 "cdclk change in progress\n");
6754 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6757 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6762 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6767 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6772 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6777 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6781 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6783 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6784 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6786 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6788 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6790 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6793 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6794 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6796 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6801 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6805 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6807 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6810 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6811 case GC_DISPLAY_CLOCK_333_MHZ
:
6814 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6820 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6825 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6828 /* Assume that the hardware is in the high speed state. This
6829 * should be the default.
6831 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6832 case GC_CLOCK_133_200
:
6833 case GC_CLOCK_100_200
:
6835 case GC_CLOCK_166_250
:
6837 case GC_CLOCK_100_133
:
6841 /* Shouldn't happen */
6845 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6851 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6853 while (*num
> DATA_LINK_M_N_MASK
||
6854 *den
> DATA_LINK_M_N_MASK
) {
6860 static void compute_m_n(unsigned int m
, unsigned int n
,
6861 uint32_t *ret_m
, uint32_t *ret_n
)
6863 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6864 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6865 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6869 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6870 int pixel_clock
, int link_clock
,
6871 struct intel_link_m_n
*m_n
)
6875 compute_m_n(bits_per_pixel
* pixel_clock
,
6876 link_clock
* nlanes
* 8,
6877 &m_n
->gmch_m
, &m_n
->gmch_n
);
6879 compute_m_n(pixel_clock
, link_clock
,
6880 &m_n
->link_m
, &m_n
->link_n
);
6883 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6885 if (i915
.panel_use_ssc
>= 0)
6886 return i915
.panel_use_ssc
!= 0;
6887 return dev_priv
->vbt
.lvds_use_ssc
6888 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6891 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6894 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6898 WARN_ON(!crtc_state
->base
.state
);
6900 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
6902 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6903 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6904 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6905 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6906 } else if (!IS_GEN2(dev
)) {
6915 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6917 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6920 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6922 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6925 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6926 struct intel_crtc_state
*crtc_state
,
6927 intel_clock_t
*reduced_clock
)
6929 struct drm_device
*dev
= crtc
->base
.dev
;
6932 if (IS_PINEVIEW(dev
)) {
6933 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6935 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6937 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6939 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6942 crtc_state
->dpll_hw_state
.fp0
= fp
;
6944 crtc
->lowfreq_avail
= false;
6945 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6947 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6948 crtc
->lowfreq_avail
= true;
6950 crtc_state
->dpll_hw_state
.fp1
= fp
;
6954 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6960 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6961 * and set it to a reasonable value instead.
6963 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6964 reg_val
&= 0xffffff00;
6965 reg_val
|= 0x00000030;
6966 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6968 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6969 reg_val
&= 0x8cffffff;
6970 reg_val
= 0x8c000000;
6971 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6973 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6974 reg_val
&= 0xffffff00;
6975 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6977 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6978 reg_val
&= 0x00ffffff;
6979 reg_val
|= 0xb0000000;
6980 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6983 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6984 struct intel_link_m_n
*m_n
)
6986 struct drm_device
*dev
= crtc
->base
.dev
;
6987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6988 int pipe
= crtc
->pipe
;
6990 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6991 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6992 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6993 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6996 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6997 struct intel_link_m_n
*m_n
,
6998 struct intel_link_m_n
*m2_n2
)
7000 struct drm_device
*dev
= crtc
->base
.dev
;
7001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7002 int pipe
= crtc
->pipe
;
7003 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7005 if (INTEL_INFO(dev
)->gen
>= 5) {
7006 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7007 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7008 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7009 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7010 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7011 * for gen < 8) and if DRRS is supported (to make sure the
7012 * registers are not unnecessarily accessed).
7014 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7015 crtc
->config
->has_drrs
) {
7016 I915_WRITE(PIPE_DATA_M2(transcoder
),
7017 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7018 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7019 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7020 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7023 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7024 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7025 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7026 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7030 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7032 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7035 dp_m_n
= &crtc
->config
->dp_m_n
;
7036 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7037 } else if (m_n
== M2_N2
) {
7040 * M2_N2 registers are not supported. Hence m2_n2 divider value
7041 * needs to be programmed into M1_N1.
7043 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7045 DRM_ERROR("Unsupported divider value\n");
7049 if (crtc
->config
->has_pch_encoder
)
7050 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7052 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7055 static void vlv_update_pll(struct intel_crtc
*crtc
,
7056 struct intel_crtc_state
*pipe_config
)
7061 * Enable DPIO clock input. We should never disable the reference
7062 * clock for pipe B, since VGA hotplug / manual detection depends
7065 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
7066 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
7067 /* We should never disable this, set it here for state tracking */
7068 if (crtc
->pipe
== PIPE_B
)
7069 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7070 dpll
|= DPLL_VCO_ENABLE
;
7071 pipe_config
->dpll_hw_state
.dpll
= dpll
;
7073 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
7074 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7075 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
7078 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7079 const struct intel_crtc_state
*pipe_config
)
7081 struct drm_device
*dev
= crtc
->base
.dev
;
7082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7083 int pipe
= crtc
->pipe
;
7085 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7086 u32 coreclk
, reg_val
;
7088 mutex_lock(&dev_priv
->sb_lock
);
7090 bestn
= pipe_config
->dpll
.n
;
7091 bestm1
= pipe_config
->dpll
.m1
;
7092 bestm2
= pipe_config
->dpll
.m2
;
7093 bestp1
= pipe_config
->dpll
.p1
;
7094 bestp2
= pipe_config
->dpll
.p2
;
7096 /* See eDP HDMI DPIO driver vbios notes doc */
7098 /* PLL B needs special handling */
7100 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7102 /* Set up Tx target for periodic Rcomp update */
7103 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7105 /* Disable target IRef on PLL */
7106 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7107 reg_val
&= 0x00ffffff;
7108 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7110 /* Disable fast lock */
7111 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7113 /* Set idtafcrecal before PLL is enabled */
7114 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7115 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7116 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7117 mdiv
|= (1 << DPIO_K_SHIFT
);
7120 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7121 * but we don't support that).
7122 * Note: don't use the DAC post divider as it seems unstable.
7124 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7125 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7127 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7128 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7130 /* Set HBR and RBR LPF coefficients */
7131 if (pipe_config
->port_clock
== 162000 ||
7132 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7133 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7134 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7137 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7140 if (pipe_config
->has_dp_encoder
) {
7141 /* Use SSC source */
7143 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7146 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7148 } else { /* HDMI or VGA */
7149 /* Use bend source */
7151 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7154 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7158 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7159 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7160 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7161 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7162 coreclk
|= 0x01000000;
7163 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7165 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7166 mutex_unlock(&dev_priv
->sb_lock
);
7169 static void chv_update_pll(struct intel_crtc
*crtc
,
7170 struct intel_crtc_state
*pipe_config
)
7172 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
7173 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7175 if (crtc
->pipe
!= PIPE_A
)
7176 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7178 pipe_config
->dpll_hw_state
.dpll_md
=
7179 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7182 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7183 const struct intel_crtc_state
*pipe_config
)
7185 struct drm_device
*dev
= crtc
->base
.dev
;
7186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7187 int pipe
= crtc
->pipe
;
7188 int dpll_reg
= DPLL(crtc
->pipe
);
7189 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7190 u32 loopfilter
, tribuf_calcntr
;
7191 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7195 bestn
= pipe_config
->dpll
.n
;
7196 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7197 bestm1
= pipe_config
->dpll
.m1
;
7198 bestm2
= pipe_config
->dpll
.m2
>> 22;
7199 bestp1
= pipe_config
->dpll
.p1
;
7200 bestp2
= pipe_config
->dpll
.p2
;
7201 vco
= pipe_config
->dpll
.vco
;
7206 * Enable Refclk and SSC
7208 I915_WRITE(dpll_reg
,
7209 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7211 mutex_lock(&dev_priv
->sb_lock
);
7213 /* p1 and p2 divider */
7214 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7215 5 << DPIO_CHV_S1_DIV_SHIFT
|
7216 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7217 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7218 1 << DPIO_CHV_K_DIV_SHIFT
);
7220 /* Feedback post-divider - m2 */
7221 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7223 /* Feedback refclk divider - n and m1 */
7224 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7225 DPIO_CHV_M1_DIV_BY_2
|
7226 1 << DPIO_CHV_N_DIV_SHIFT
);
7228 /* M2 fraction division */
7230 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7232 /* M2 fraction division enable */
7233 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7234 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7235 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7237 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7238 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7240 /* Program digital lock detect threshold */
7241 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7242 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7243 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7244 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7246 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7247 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7250 if (vco
== 5400000) {
7251 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7252 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7253 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7254 tribuf_calcntr
= 0x9;
7255 } else if (vco
<= 6200000) {
7256 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7257 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7258 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7259 tribuf_calcntr
= 0x9;
7260 } else if (vco
<= 6480000) {
7261 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7262 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7263 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7264 tribuf_calcntr
= 0x8;
7266 /* Not supported. Apply the same limits as in the max case */
7267 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7268 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7269 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7272 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7274 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7275 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7276 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7277 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7280 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7281 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7284 mutex_unlock(&dev_priv
->sb_lock
);
7288 * vlv_force_pll_on - forcibly enable just the PLL
7289 * @dev_priv: i915 private structure
7290 * @pipe: pipe PLL to enable
7291 * @dpll: PLL configuration
7293 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7294 * in cases where we need the PLL enabled even when @pipe is not going to
7297 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7298 const struct dpll
*dpll
)
7300 struct intel_crtc
*crtc
=
7301 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7302 struct intel_crtc_state pipe_config
= {
7303 .base
.crtc
= &crtc
->base
,
7304 .pixel_multiplier
= 1,
7308 if (IS_CHERRYVIEW(dev
)) {
7309 chv_update_pll(crtc
, &pipe_config
);
7310 chv_prepare_pll(crtc
, &pipe_config
);
7311 chv_enable_pll(crtc
, &pipe_config
);
7313 vlv_update_pll(crtc
, &pipe_config
);
7314 vlv_prepare_pll(crtc
, &pipe_config
);
7315 vlv_enable_pll(crtc
, &pipe_config
);
7320 * vlv_force_pll_off - forcibly disable just the PLL
7321 * @dev_priv: i915 private structure
7322 * @pipe: pipe PLL to disable
7324 * Disable the PLL for @pipe. To be used in cases where we need
7325 * the PLL enabled even when @pipe is not going to be enabled.
7327 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7329 if (IS_CHERRYVIEW(dev
))
7330 chv_disable_pll(to_i915(dev
), pipe
);
7332 vlv_disable_pll(to_i915(dev
), pipe
);
7335 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7336 struct intel_crtc_state
*crtc_state
,
7337 intel_clock_t
*reduced_clock
,
7340 struct drm_device
*dev
= crtc
->base
.dev
;
7341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7344 struct dpll
*clock
= &crtc_state
->dpll
;
7346 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7348 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7349 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7351 dpll
= DPLL_VGA_MODE_DIS
;
7353 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7354 dpll
|= DPLLB_MODE_LVDS
;
7356 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7358 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7359 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7360 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7364 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7366 if (crtc_state
->has_dp_encoder
)
7367 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7369 /* compute bitmask from p1 value */
7370 if (IS_PINEVIEW(dev
))
7371 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7373 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7374 if (IS_G4X(dev
) && reduced_clock
)
7375 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7377 switch (clock
->p2
) {
7379 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7382 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7385 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7388 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7391 if (INTEL_INFO(dev
)->gen
>= 4)
7392 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7394 if (crtc_state
->sdvo_tv_clock
)
7395 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7396 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7397 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7398 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7400 dpll
|= PLL_REF_INPUT_DREFCLK
;
7402 dpll
|= DPLL_VCO_ENABLE
;
7403 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7405 if (INTEL_INFO(dev
)->gen
>= 4) {
7406 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7407 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7408 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7412 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7413 struct intel_crtc_state
*crtc_state
,
7414 intel_clock_t
*reduced_clock
,
7417 struct drm_device
*dev
= crtc
->base
.dev
;
7418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7420 struct dpll
*clock
= &crtc_state
->dpll
;
7422 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7424 dpll
= DPLL_VGA_MODE_DIS
;
7426 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7427 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7430 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7432 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7434 dpll
|= PLL_P2_DIVIDE_BY_4
;
7437 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7438 dpll
|= DPLL_DVO_2X_MODE
;
7440 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7441 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7442 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7444 dpll
|= PLL_REF_INPUT_DREFCLK
;
7446 dpll
|= DPLL_VCO_ENABLE
;
7447 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7450 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7452 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7454 enum pipe pipe
= intel_crtc
->pipe
;
7455 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7456 struct drm_display_mode
*adjusted_mode
=
7457 &intel_crtc
->config
->base
.adjusted_mode
;
7458 uint32_t crtc_vtotal
, crtc_vblank_end
;
7461 /* We need to be careful not to changed the adjusted mode, for otherwise
7462 * the hw state checker will get angry at the mismatch. */
7463 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7464 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7466 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7467 /* the chip adds 2 halflines automatically */
7469 crtc_vblank_end
-= 1;
7471 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7472 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7474 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7475 adjusted_mode
->crtc_htotal
/ 2;
7477 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7480 if (INTEL_INFO(dev
)->gen
> 3)
7481 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7483 I915_WRITE(HTOTAL(cpu_transcoder
),
7484 (adjusted_mode
->crtc_hdisplay
- 1) |
7485 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7486 I915_WRITE(HBLANK(cpu_transcoder
),
7487 (adjusted_mode
->crtc_hblank_start
- 1) |
7488 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7489 I915_WRITE(HSYNC(cpu_transcoder
),
7490 (adjusted_mode
->crtc_hsync_start
- 1) |
7491 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7493 I915_WRITE(VTOTAL(cpu_transcoder
),
7494 (adjusted_mode
->crtc_vdisplay
- 1) |
7495 ((crtc_vtotal
- 1) << 16));
7496 I915_WRITE(VBLANK(cpu_transcoder
),
7497 (adjusted_mode
->crtc_vblank_start
- 1) |
7498 ((crtc_vblank_end
- 1) << 16));
7499 I915_WRITE(VSYNC(cpu_transcoder
),
7500 (adjusted_mode
->crtc_vsync_start
- 1) |
7501 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7503 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7504 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7505 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7507 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7508 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7509 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7511 /* pipesrc controls the size that is scaled from, which should
7512 * always be the user's requested size.
7514 I915_WRITE(PIPESRC(pipe
),
7515 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7516 (intel_crtc
->config
->pipe_src_h
- 1));
7519 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7520 struct intel_crtc_state
*pipe_config
)
7522 struct drm_device
*dev
= crtc
->base
.dev
;
7523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7524 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7527 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7528 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7529 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7530 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7531 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7532 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7533 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7534 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7535 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7537 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7538 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7539 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7540 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7541 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7542 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7543 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7544 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7545 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7547 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7548 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7549 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7550 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7553 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7554 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7555 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7557 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7558 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7561 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7562 struct intel_crtc_state
*pipe_config
)
7564 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7565 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7566 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7567 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7569 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7570 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7571 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7572 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7574 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7576 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7577 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7580 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7582 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7588 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7589 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7590 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7592 if (intel_crtc
->config
->double_wide
)
7593 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7595 /* only g4x and later have fancy bpc/dither controls */
7596 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7597 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7598 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7599 pipeconf
|= PIPECONF_DITHER_EN
|
7600 PIPECONF_DITHER_TYPE_SP
;
7602 switch (intel_crtc
->config
->pipe_bpp
) {
7604 pipeconf
|= PIPECONF_6BPC
;
7607 pipeconf
|= PIPECONF_8BPC
;
7610 pipeconf
|= PIPECONF_10BPC
;
7613 /* Case prevented by intel_choose_pipe_bpp_dither. */
7618 if (HAS_PIPE_CXSR(dev
)) {
7619 if (intel_crtc
->lowfreq_avail
) {
7620 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7621 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7623 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7627 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7628 if (INTEL_INFO(dev
)->gen
< 4 ||
7629 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7630 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7632 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7634 pipeconf
|= PIPECONF_PROGRESSIVE
;
7636 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7637 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7639 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7640 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7643 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7644 struct intel_crtc_state
*crtc_state
)
7646 struct drm_device
*dev
= crtc
->base
.dev
;
7647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7648 int refclk
, num_connectors
= 0;
7649 intel_clock_t clock
, reduced_clock
;
7650 bool ok
, has_reduced_clock
= false;
7651 bool is_lvds
= false, is_dsi
= false;
7652 struct intel_encoder
*encoder
;
7653 const intel_limit_t
*limit
;
7654 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7655 struct drm_connector
*connector
;
7656 struct drm_connector_state
*connector_state
;
7659 memset(&crtc_state
->dpll_hw_state
, 0,
7660 sizeof(crtc_state
->dpll_hw_state
));
7662 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7663 if (connector_state
->crtc
!= &crtc
->base
)
7666 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7668 switch (encoder
->type
) {
7669 case INTEL_OUTPUT_LVDS
:
7672 case INTEL_OUTPUT_DSI
:
7685 if (!crtc_state
->clock_set
) {
7686 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7689 * Returns a set of divisors for the desired target clock with
7690 * the given refclk, or FALSE. The returned values represent
7691 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7694 limit
= intel_limit(crtc_state
, refclk
);
7695 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7696 crtc_state
->port_clock
,
7697 refclk
, NULL
, &clock
);
7699 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7703 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7705 * Ensure we match the reduced clock's P to the target
7706 * clock. If the clocks don't match, we can't switch
7707 * the display clock by using the FP0/FP1. In such case
7708 * we will disable the LVDS downclock feature.
7711 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7712 dev_priv
->lvds_downclock
,
7716 /* Compat-code for transition, will disappear. */
7717 crtc_state
->dpll
.n
= clock
.n
;
7718 crtc_state
->dpll
.m1
= clock
.m1
;
7719 crtc_state
->dpll
.m2
= clock
.m2
;
7720 crtc_state
->dpll
.p1
= clock
.p1
;
7721 crtc_state
->dpll
.p2
= clock
.p2
;
7725 i8xx_update_pll(crtc
, crtc_state
,
7726 has_reduced_clock
? &reduced_clock
: NULL
,
7728 } else if (IS_CHERRYVIEW(dev
)) {
7729 chv_update_pll(crtc
, crtc_state
);
7730 } else if (IS_VALLEYVIEW(dev
)) {
7731 vlv_update_pll(crtc
, crtc_state
);
7733 i9xx_update_pll(crtc
, crtc_state
,
7734 has_reduced_clock
? &reduced_clock
: NULL
,
7741 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7742 struct intel_crtc_state
*pipe_config
)
7744 struct drm_device
*dev
= crtc
->base
.dev
;
7745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7748 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7751 tmp
= I915_READ(PFIT_CONTROL
);
7752 if (!(tmp
& PFIT_ENABLE
))
7755 /* Check whether the pfit is attached to our pipe. */
7756 if (INTEL_INFO(dev
)->gen
< 4) {
7757 if (crtc
->pipe
!= PIPE_B
)
7760 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7764 pipe_config
->gmch_pfit
.control
= tmp
;
7765 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7766 if (INTEL_INFO(dev
)->gen
< 5)
7767 pipe_config
->gmch_pfit
.lvds_border_bits
=
7768 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7771 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7772 struct intel_crtc_state
*pipe_config
)
7774 struct drm_device
*dev
= crtc
->base
.dev
;
7775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7776 int pipe
= pipe_config
->cpu_transcoder
;
7777 intel_clock_t clock
;
7779 int refclk
= 100000;
7781 /* In case of MIPI DPLL will not even be used */
7782 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7785 mutex_lock(&dev_priv
->sb_lock
);
7786 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7787 mutex_unlock(&dev_priv
->sb_lock
);
7789 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7790 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7791 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7792 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7793 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7795 vlv_clock(refclk
, &clock
);
7797 /* clock.dot is the fast clock */
7798 pipe_config
->port_clock
= clock
.dot
/ 5;
7802 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7803 struct intel_initial_plane_config
*plane_config
)
7805 struct drm_device
*dev
= crtc
->base
.dev
;
7806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7807 u32 val
, base
, offset
;
7808 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7809 int fourcc
, pixel_format
;
7810 unsigned int aligned_height
;
7811 struct drm_framebuffer
*fb
;
7812 struct intel_framebuffer
*intel_fb
;
7814 val
= I915_READ(DSPCNTR(plane
));
7815 if (!(val
& DISPLAY_PLANE_ENABLE
))
7818 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7820 DRM_DEBUG_KMS("failed to alloc fb\n");
7824 fb
= &intel_fb
->base
;
7826 if (INTEL_INFO(dev
)->gen
>= 4) {
7827 if (val
& DISPPLANE_TILED
) {
7828 plane_config
->tiling
= I915_TILING_X
;
7829 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7833 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7834 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7835 fb
->pixel_format
= fourcc
;
7836 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7838 if (INTEL_INFO(dev
)->gen
>= 4) {
7839 if (plane_config
->tiling
)
7840 offset
= I915_READ(DSPTILEOFF(plane
));
7842 offset
= I915_READ(DSPLINOFF(plane
));
7843 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7845 base
= I915_READ(DSPADDR(plane
));
7847 plane_config
->base
= base
;
7849 val
= I915_READ(PIPESRC(pipe
));
7850 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7851 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7853 val
= I915_READ(DSPSTRIDE(pipe
));
7854 fb
->pitches
[0] = val
& 0xffffffc0;
7856 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7860 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7862 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7863 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7864 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7865 plane_config
->size
);
7867 plane_config
->fb
= intel_fb
;
7870 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7871 struct intel_crtc_state
*pipe_config
)
7873 struct drm_device
*dev
= crtc
->base
.dev
;
7874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7875 int pipe
= pipe_config
->cpu_transcoder
;
7876 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7877 intel_clock_t clock
;
7878 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7879 int refclk
= 100000;
7881 mutex_lock(&dev_priv
->sb_lock
);
7882 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7883 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7884 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7885 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7886 mutex_unlock(&dev_priv
->sb_lock
);
7888 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7889 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7890 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7891 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7892 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7894 chv_clock(refclk
, &clock
);
7896 /* clock.dot is the fast clock */
7897 pipe_config
->port_clock
= clock
.dot
/ 5;
7900 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7901 struct intel_crtc_state
*pipe_config
)
7903 struct drm_device
*dev
= crtc
->base
.dev
;
7904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7907 if (!intel_display_power_is_enabled(dev_priv
,
7908 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7911 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7912 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7914 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7915 if (!(tmp
& PIPECONF_ENABLE
))
7918 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7919 switch (tmp
& PIPECONF_BPC_MASK
) {
7921 pipe_config
->pipe_bpp
= 18;
7924 pipe_config
->pipe_bpp
= 24;
7926 case PIPECONF_10BPC
:
7927 pipe_config
->pipe_bpp
= 30;
7934 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7935 pipe_config
->limited_color_range
= true;
7937 if (INTEL_INFO(dev
)->gen
< 4)
7938 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7940 intel_get_pipe_timings(crtc
, pipe_config
);
7942 i9xx_get_pfit_config(crtc
, pipe_config
);
7944 if (INTEL_INFO(dev
)->gen
>= 4) {
7945 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7946 pipe_config
->pixel_multiplier
=
7947 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7948 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7949 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7950 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7951 tmp
= I915_READ(DPLL(crtc
->pipe
));
7952 pipe_config
->pixel_multiplier
=
7953 ((tmp
& SDVO_MULTIPLIER_MASK
)
7954 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7956 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7957 * port and will be fixed up in the encoder->get_config
7959 pipe_config
->pixel_multiplier
= 1;
7961 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7962 if (!IS_VALLEYVIEW(dev
)) {
7964 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7965 * on 830. Filter it out here so that we don't
7966 * report errors due to that.
7969 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7971 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7972 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7974 /* Mask out read-only status bits. */
7975 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7976 DPLL_PORTC_READY_MASK
|
7977 DPLL_PORTB_READY_MASK
);
7980 if (IS_CHERRYVIEW(dev
))
7981 chv_crtc_clock_get(crtc
, pipe_config
);
7982 else if (IS_VALLEYVIEW(dev
))
7983 vlv_crtc_clock_get(crtc
, pipe_config
);
7985 i9xx_crtc_clock_get(crtc
, pipe_config
);
7990 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7993 struct intel_encoder
*encoder
;
7995 bool has_lvds
= false;
7996 bool has_cpu_edp
= false;
7997 bool has_panel
= false;
7998 bool has_ck505
= false;
7999 bool can_ssc
= false;
8001 /* We need to take the global config into account */
8002 for_each_intel_encoder(dev
, encoder
) {
8003 switch (encoder
->type
) {
8004 case INTEL_OUTPUT_LVDS
:
8008 case INTEL_OUTPUT_EDP
:
8010 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8018 if (HAS_PCH_IBX(dev
)) {
8019 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8020 can_ssc
= has_ck505
;
8026 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8027 has_panel
, has_lvds
, has_ck505
);
8029 /* Ironlake: try to setup display ref clock before DPLL
8030 * enabling. This is only under driver's control after
8031 * PCH B stepping, previous chipset stepping should be
8032 * ignoring this setting.
8034 val
= I915_READ(PCH_DREF_CONTROL
);
8036 /* As we must carefully and slowly disable/enable each source in turn,
8037 * compute the final state we want first and check if we need to
8038 * make any changes at all.
8041 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8043 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8045 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8047 final
&= ~DREF_SSC_SOURCE_MASK
;
8048 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8049 final
&= ~DREF_SSC1_ENABLE
;
8052 final
|= DREF_SSC_SOURCE_ENABLE
;
8054 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8055 final
|= DREF_SSC1_ENABLE
;
8058 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8059 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8061 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8063 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8065 final
|= DREF_SSC_SOURCE_DISABLE
;
8066 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8072 /* Always enable nonspread source */
8073 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8076 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8078 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8081 val
&= ~DREF_SSC_SOURCE_MASK
;
8082 val
|= DREF_SSC_SOURCE_ENABLE
;
8084 /* SSC must be turned on before enabling the CPU output */
8085 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8086 DRM_DEBUG_KMS("Using SSC on panel\n");
8087 val
|= DREF_SSC1_ENABLE
;
8089 val
&= ~DREF_SSC1_ENABLE
;
8091 /* Get SSC going before enabling the outputs */
8092 I915_WRITE(PCH_DREF_CONTROL
, val
);
8093 POSTING_READ(PCH_DREF_CONTROL
);
8096 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8098 /* Enable CPU source on CPU attached eDP */
8100 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8101 DRM_DEBUG_KMS("Using SSC on eDP\n");
8102 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8104 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8106 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8108 I915_WRITE(PCH_DREF_CONTROL
, val
);
8109 POSTING_READ(PCH_DREF_CONTROL
);
8112 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8114 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8116 /* Turn off CPU output */
8117 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8119 I915_WRITE(PCH_DREF_CONTROL
, val
);
8120 POSTING_READ(PCH_DREF_CONTROL
);
8123 /* Turn off the SSC source */
8124 val
&= ~DREF_SSC_SOURCE_MASK
;
8125 val
|= DREF_SSC_SOURCE_DISABLE
;
8128 val
&= ~DREF_SSC1_ENABLE
;
8130 I915_WRITE(PCH_DREF_CONTROL
, val
);
8131 POSTING_READ(PCH_DREF_CONTROL
);
8135 BUG_ON(val
!= final
);
8138 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8142 tmp
= I915_READ(SOUTH_CHICKEN2
);
8143 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8144 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8146 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8147 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8148 DRM_ERROR("FDI mPHY reset assert timeout\n");
8150 tmp
= I915_READ(SOUTH_CHICKEN2
);
8151 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8152 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8154 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8155 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8156 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8159 /* WaMPhyProgramming:hsw */
8160 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8164 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8165 tmp
&= ~(0xFF << 24);
8166 tmp
|= (0x12 << 24);
8167 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8169 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8171 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8173 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8175 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8177 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8178 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8179 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8181 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8182 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8183 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8185 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8188 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8190 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8193 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8195 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8198 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8200 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8203 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8205 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8206 tmp
&= ~(0xFF << 16);
8207 tmp
|= (0x1C << 16);
8208 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8210 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8211 tmp
&= ~(0xFF << 16);
8212 tmp
|= (0x1C << 16);
8213 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8215 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8217 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8219 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8221 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8223 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8224 tmp
&= ~(0xF << 28);
8226 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8228 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8229 tmp
&= ~(0xF << 28);
8231 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8234 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8235 * Programming" based on the parameters passed:
8236 * - Sequence to enable CLKOUT_DP
8237 * - Sequence to enable CLKOUT_DP without spread
8238 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8240 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8246 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8248 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8249 with_fdi
, "LP PCH doesn't have FDI\n"))
8252 mutex_lock(&dev_priv
->sb_lock
);
8254 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8255 tmp
&= ~SBI_SSCCTL_DISABLE
;
8256 tmp
|= SBI_SSCCTL_PATHALT
;
8257 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8262 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8263 tmp
&= ~SBI_SSCCTL_PATHALT
;
8264 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8267 lpt_reset_fdi_mphy(dev_priv
);
8268 lpt_program_fdi_mphy(dev_priv
);
8272 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8273 SBI_GEN0
: SBI_DBUFF0
;
8274 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8275 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8276 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8278 mutex_unlock(&dev_priv
->sb_lock
);
8281 /* Sequence to disable CLKOUT_DP */
8282 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8287 mutex_lock(&dev_priv
->sb_lock
);
8289 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8290 SBI_GEN0
: SBI_DBUFF0
;
8291 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8292 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8293 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8295 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8296 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8297 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8298 tmp
|= SBI_SSCCTL_PATHALT
;
8299 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8302 tmp
|= SBI_SSCCTL_DISABLE
;
8303 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8306 mutex_unlock(&dev_priv
->sb_lock
);
8309 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8311 struct intel_encoder
*encoder
;
8312 bool has_vga
= false;
8314 for_each_intel_encoder(dev
, encoder
) {
8315 switch (encoder
->type
) {
8316 case INTEL_OUTPUT_ANALOG
:
8325 lpt_enable_clkout_dp(dev
, true, true);
8327 lpt_disable_clkout_dp(dev
);
8331 * Initialize reference clocks when the driver loads
8333 void intel_init_pch_refclk(struct drm_device
*dev
)
8335 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8336 ironlake_init_pch_refclk(dev
);
8337 else if (HAS_PCH_LPT(dev
))
8338 lpt_init_pch_refclk(dev
);
8341 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8343 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8345 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8346 struct drm_connector
*connector
;
8347 struct drm_connector_state
*connector_state
;
8348 struct intel_encoder
*encoder
;
8349 int num_connectors
= 0, i
;
8350 bool is_lvds
= false;
8352 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8353 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8356 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8358 switch (encoder
->type
) {
8359 case INTEL_OUTPUT_LVDS
:
8368 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8369 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8370 dev_priv
->vbt
.lvds_ssc_freq
);
8371 return dev_priv
->vbt
.lvds_ssc_freq
;
8377 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8379 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8380 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8381 int pipe
= intel_crtc
->pipe
;
8386 switch (intel_crtc
->config
->pipe_bpp
) {
8388 val
|= PIPECONF_6BPC
;
8391 val
|= PIPECONF_8BPC
;
8394 val
|= PIPECONF_10BPC
;
8397 val
|= PIPECONF_12BPC
;
8400 /* Case prevented by intel_choose_pipe_bpp_dither. */
8404 if (intel_crtc
->config
->dither
)
8405 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8407 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8408 val
|= PIPECONF_INTERLACED_ILK
;
8410 val
|= PIPECONF_PROGRESSIVE
;
8412 if (intel_crtc
->config
->limited_color_range
)
8413 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8415 I915_WRITE(PIPECONF(pipe
), val
);
8416 POSTING_READ(PIPECONF(pipe
));
8420 * Set up the pipe CSC unit.
8422 * Currently only full range RGB to limited range RGB conversion
8423 * is supported, but eventually this should handle various
8424 * RGB<->YCbCr scenarios as well.
8426 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8428 struct drm_device
*dev
= crtc
->dev
;
8429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8430 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8431 int pipe
= intel_crtc
->pipe
;
8432 uint16_t coeff
= 0x7800; /* 1.0 */
8435 * TODO: Check what kind of values actually come out of the pipe
8436 * with these coeff/postoff values and adjust to get the best
8437 * accuracy. Perhaps we even need to take the bpc value into
8441 if (intel_crtc
->config
->limited_color_range
)
8442 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8445 * GY/GU and RY/RU should be the other way around according
8446 * to BSpec, but reality doesn't agree. Just set them up in
8447 * a way that results in the correct picture.
8449 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8450 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8452 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8453 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8455 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8456 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8458 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8459 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8460 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8462 if (INTEL_INFO(dev
)->gen
> 6) {
8463 uint16_t postoff
= 0;
8465 if (intel_crtc
->config
->limited_color_range
)
8466 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8468 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8469 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8470 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8472 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8474 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8476 if (intel_crtc
->config
->limited_color_range
)
8477 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8479 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8483 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8485 struct drm_device
*dev
= crtc
->dev
;
8486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8488 enum pipe pipe
= intel_crtc
->pipe
;
8489 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8494 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8495 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8497 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8498 val
|= PIPECONF_INTERLACED_ILK
;
8500 val
|= PIPECONF_PROGRESSIVE
;
8502 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8503 POSTING_READ(PIPECONF(cpu_transcoder
));
8505 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8506 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8508 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8511 switch (intel_crtc
->config
->pipe_bpp
) {
8513 val
|= PIPEMISC_DITHER_6_BPC
;
8516 val
|= PIPEMISC_DITHER_8_BPC
;
8519 val
|= PIPEMISC_DITHER_10_BPC
;
8522 val
|= PIPEMISC_DITHER_12_BPC
;
8525 /* Case prevented by pipe_config_set_bpp. */
8529 if (intel_crtc
->config
->dither
)
8530 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8532 I915_WRITE(PIPEMISC(pipe
), val
);
8536 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8537 struct intel_crtc_state
*crtc_state
,
8538 intel_clock_t
*clock
,
8539 bool *has_reduced_clock
,
8540 intel_clock_t
*reduced_clock
)
8542 struct drm_device
*dev
= crtc
->dev
;
8543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8545 const intel_limit_t
*limit
;
8546 bool ret
, is_lvds
= false;
8548 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8550 refclk
= ironlake_get_refclk(crtc_state
);
8553 * Returns a set of divisors for the desired target clock with the given
8554 * refclk, or FALSE. The returned values represent the clock equation:
8555 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8557 limit
= intel_limit(crtc_state
, refclk
);
8558 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8559 crtc_state
->port_clock
,
8560 refclk
, NULL
, clock
);
8564 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8566 * Ensure we match the reduced clock's P to the target clock.
8567 * If the clocks don't match, we can't switch the display clock
8568 * by using the FP0/FP1. In such case we will disable the LVDS
8569 * downclock feature.
8571 *has_reduced_clock
=
8572 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8573 dev_priv
->lvds_downclock
,
8581 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8584 * Account for spread spectrum to avoid
8585 * oversubscribing the link. Max center spread
8586 * is 2.5%; use 5% for safety's sake.
8588 u32 bps
= target_clock
* bpp
* 21 / 20;
8589 return DIV_ROUND_UP(bps
, link_bw
* 8);
8592 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8594 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8597 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8598 struct intel_crtc_state
*crtc_state
,
8600 intel_clock_t
*reduced_clock
, u32
*fp2
)
8602 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8603 struct drm_device
*dev
= crtc
->dev
;
8604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8605 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8606 struct drm_connector
*connector
;
8607 struct drm_connector_state
*connector_state
;
8608 struct intel_encoder
*encoder
;
8610 int factor
, num_connectors
= 0, i
;
8611 bool is_lvds
= false, is_sdvo
= false;
8613 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8614 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8617 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8619 switch (encoder
->type
) {
8620 case INTEL_OUTPUT_LVDS
:
8623 case INTEL_OUTPUT_SDVO
:
8624 case INTEL_OUTPUT_HDMI
:
8634 /* Enable autotuning of the PLL clock (if permissible) */
8637 if ((intel_panel_use_ssc(dev_priv
) &&
8638 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8639 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8641 } else if (crtc_state
->sdvo_tv_clock
)
8644 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8647 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8653 dpll
|= DPLLB_MODE_LVDS
;
8655 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8657 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8658 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8661 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8662 if (crtc_state
->has_dp_encoder
)
8663 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8665 /* compute bitmask from p1 value */
8666 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8668 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8670 switch (crtc_state
->dpll
.p2
) {
8672 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8675 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8678 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8681 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8685 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8686 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8688 dpll
|= PLL_REF_INPUT_DREFCLK
;
8690 return dpll
| DPLL_VCO_ENABLE
;
8693 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8694 struct intel_crtc_state
*crtc_state
)
8696 struct drm_device
*dev
= crtc
->base
.dev
;
8697 intel_clock_t clock
, reduced_clock
;
8698 u32 dpll
= 0, fp
= 0, fp2
= 0;
8699 bool ok
, has_reduced_clock
= false;
8700 bool is_lvds
= false;
8701 struct intel_shared_dpll
*pll
;
8703 memset(&crtc_state
->dpll_hw_state
, 0,
8704 sizeof(crtc_state
->dpll_hw_state
));
8706 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8708 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8709 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8711 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8712 &has_reduced_clock
, &reduced_clock
);
8713 if (!ok
&& !crtc_state
->clock_set
) {
8714 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8717 /* Compat-code for transition, will disappear. */
8718 if (!crtc_state
->clock_set
) {
8719 crtc_state
->dpll
.n
= clock
.n
;
8720 crtc_state
->dpll
.m1
= clock
.m1
;
8721 crtc_state
->dpll
.m2
= clock
.m2
;
8722 crtc_state
->dpll
.p1
= clock
.p1
;
8723 crtc_state
->dpll
.p2
= clock
.p2
;
8726 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8727 if (crtc_state
->has_pch_encoder
) {
8728 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8729 if (has_reduced_clock
)
8730 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8732 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8733 &fp
, &reduced_clock
,
8734 has_reduced_clock
? &fp2
: NULL
);
8736 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8737 crtc_state
->dpll_hw_state
.fp0
= fp
;
8738 if (has_reduced_clock
)
8739 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8741 crtc_state
->dpll_hw_state
.fp1
= fp
;
8743 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8745 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8746 pipe_name(crtc
->pipe
));
8751 if (is_lvds
&& has_reduced_clock
)
8752 crtc
->lowfreq_avail
= true;
8754 crtc
->lowfreq_avail
= false;
8759 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8760 struct intel_link_m_n
*m_n
)
8762 struct drm_device
*dev
= crtc
->base
.dev
;
8763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8764 enum pipe pipe
= crtc
->pipe
;
8766 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8767 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8768 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8770 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8771 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8772 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8775 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8776 enum transcoder transcoder
,
8777 struct intel_link_m_n
*m_n
,
8778 struct intel_link_m_n
*m2_n2
)
8780 struct drm_device
*dev
= crtc
->base
.dev
;
8781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8782 enum pipe pipe
= crtc
->pipe
;
8784 if (INTEL_INFO(dev
)->gen
>= 5) {
8785 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8786 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8787 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8789 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8790 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8791 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8792 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8793 * gen < 8) and if DRRS is supported (to make sure the
8794 * registers are not unnecessarily read).
8796 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8797 crtc
->config
->has_drrs
) {
8798 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8799 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8800 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8802 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8803 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8804 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8807 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8808 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8809 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8811 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8812 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8813 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8817 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8818 struct intel_crtc_state
*pipe_config
)
8820 if (pipe_config
->has_pch_encoder
)
8821 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8823 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8824 &pipe_config
->dp_m_n
,
8825 &pipe_config
->dp_m2_n2
);
8828 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8829 struct intel_crtc_state
*pipe_config
)
8831 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8832 &pipe_config
->fdi_m_n
, NULL
);
8835 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8836 struct intel_crtc_state
*pipe_config
)
8838 struct drm_device
*dev
= crtc
->base
.dev
;
8839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8840 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8841 uint32_t ps_ctrl
= 0;
8845 /* find scaler attached to this pipe */
8846 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8847 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8848 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8850 pipe_config
->pch_pfit
.enabled
= true;
8851 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8852 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8857 scaler_state
->scaler_id
= id
;
8859 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8861 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8866 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8867 struct intel_initial_plane_config
*plane_config
)
8869 struct drm_device
*dev
= crtc
->base
.dev
;
8870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8871 u32 val
, base
, offset
, stride_mult
, tiling
;
8872 int pipe
= crtc
->pipe
;
8873 int fourcc
, pixel_format
;
8874 unsigned int aligned_height
;
8875 struct drm_framebuffer
*fb
;
8876 struct intel_framebuffer
*intel_fb
;
8878 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8880 DRM_DEBUG_KMS("failed to alloc fb\n");
8884 fb
= &intel_fb
->base
;
8886 val
= I915_READ(PLANE_CTL(pipe
, 0));
8887 if (!(val
& PLANE_CTL_ENABLE
))
8890 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8891 fourcc
= skl_format_to_fourcc(pixel_format
,
8892 val
& PLANE_CTL_ORDER_RGBX
,
8893 val
& PLANE_CTL_ALPHA_MASK
);
8894 fb
->pixel_format
= fourcc
;
8895 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8897 tiling
= val
& PLANE_CTL_TILED_MASK
;
8899 case PLANE_CTL_TILED_LINEAR
:
8900 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8902 case PLANE_CTL_TILED_X
:
8903 plane_config
->tiling
= I915_TILING_X
;
8904 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8906 case PLANE_CTL_TILED_Y
:
8907 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8909 case PLANE_CTL_TILED_YF
:
8910 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8913 MISSING_CASE(tiling
);
8917 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8918 plane_config
->base
= base
;
8920 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8922 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8923 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8924 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8926 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8927 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8929 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8931 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8935 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8937 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8938 pipe_name(pipe
), fb
->width
, fb
->height
,
8939 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8940 plane_config
->size
);
8942 plane_config
->fb
= intel_fb
;
8949 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8950 struct intel_crtc_state
*pipe_config
)
8952 struct drm_device
*dev
= crtc
->base
.dev
;
8953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8956 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8958 if (tmp
& PF_ENABLE
) {
8959 pipe_config
->pch_pfit
.enabled
= true;
8960 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8961 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8963 /* We currently do not free assignements of panel fitters on
8964 * ivb/hsw (since we don't use the higher upscaling modes which
8965 * differentiates them) so just WARN about this case for now. */
8967 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8968 PF_PIPE_SEL_IVB(crtc
->pipe
));
8974 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8975 struct intel_initial_plane_config
*plane_config
)
8977 struct drm_device
*dev
= crtc
->base
.dev
;
8978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8979 u32 val
, base
, offset
;
8980 int pipe
= crtc
->pipe
;
8981 int fourcc
, pixel_format
;
8982 unsigned int aligned_height
;
8983 struct drm_framebuffer
*fb
;
8984 struct intel_framebuffer
*intel_fb
;
8986 val
= I915_READ(DSPCNTR(pipe
));
8987 if (!(val
& DISPLAY_PLANE_ENABLE
))
8990 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8992 DRM_DEBUG_KMS("failed to alloc fb\n");
8996 fb
= &intel_fb
->base
;
8998 if (INTEL_INFO(dev
)->gen
>= 4) {
8999 if (val
& DISPPLANE_TILED
) {
9000 plane_config
->tiling
= I915_TILING_X
;
9001 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9005 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9006 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9007 fb
->pixel_format
= fourcc
;
9008 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9010 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9011 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9012 offset
= I915_READ(DSPOFFSET(pipe
));
9014 if (plane_config
->tiling
)
9015 offset
= I915_READ(DSPTILEOFF(pipe
));
9017 offset
= I915_READ(DSPLINOFF(pipe
));
9019 plane_config
->base
= base
;
9021 val
= I915_READ(PIPESRC(pipe
));
9022 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9023 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9025 val
= I915_READ(DSPSTRIDE(pipe
));
9026 fb
->pitches
[0] = val
& 0xffffffc0;
9028 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9032 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9034 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9035 pipe_name(pipe
), fb
->width
, fb
->height
,
9036 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9037 plane_config
->size
);
9039 plane_config
->fb
= intel_fb
;
9042 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9043 struct intel_crtc_state
*pipe_config
)
9045 struct drm_device
*dev
= crtc
->base
.dev
;
9046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9049 if (!intel_display_power_is_enabled(dev_priv
,
9050 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9053 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9054 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9056 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9057 if (!(tmp
& PIPECONF_ENABLE
))
9060 switch (tmp
& PIPECONF_BPC_MASK
) {
9062 pipe_config
->pipe_bpp
= 18;
9065 pipe_config
->pipe_bpp
= 24;
9067 case PIPECONF_10BPC
:
9068 pipe_config
->pipe_bpp
= 30;
9070 case PIPECONF_12BPC
:
9071 pipe_config
->pipe_bpp
= 36;
9077 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9078 pipe_config
->limited_color_range
= true;
9080 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9081 struct intel_shared_dpll
*pll
;
9083 pipe_config
->has_pch_encoder
= true;
9085 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9086 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9087 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9089 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9091 if (HAS_PCH_IBX(dev_priv
->dev
)) {
9092 pipe_config
->shared_dpll
=
9093 (enum intel_dpll_id
) crtc
->pipe
;
9095 tmp
= I915_READ(PCH_DPLL_SEL
);
9096 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9097 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
9099 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
9102 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9104 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9105 &pipe_config
->dpll_hw_state
));
9107 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9108 pipe_config
->pixel_multiplier
=
9109 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9110 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9112 ironlake_pch_clock_get(crtc
, pipe_config
);
9114 pipe_config
->pixel_multiplier
= 1;
9117 intel_get_pipe_timings(crtc
, pipe_config
);
9119 ironlake_get_pfit_config(crtc
, pipe_config
);
9124 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9126 struct drm_device
*dev
= dev_priv
->dev
;
9127 struct intel_crtc
*crtc
;
9129 for_each_intel_crtc(dev
, crtc
)
9130 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9131 pipe_name(crtc
->pipe
));
9133 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9134 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9135 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9136 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9137 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9138 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9139 "CPU PWM1 enabled\n");
9140 if (IS_HASWELL(dev
))
9141 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9142 "CPU PWM2 enabled\n");
9143 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9144 "PCH PWM1 enabled\n");
9145 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9146 "Utility pin enabled\n");
9147 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9150 * In theory we can still leave IRQs enabled, as long as only the HPD
9151 * interrupts remain enabled. We used to check for that, but since it's
9152 * gen-specific and since we only disable LCPLL after we fully disable
9153 * the interrupts, the check below should be enough.
9155 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9158 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9160 struct drm_device
*dev
= dev_priv
->dev
;
9162 if (IS_HASWELL(dev
))
9163 return I915_READ(D_COMP_HSW
);
9165 return I915_READ(D_COMP_BDW
);
9168 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9170 struct drm_device
*dev
= dev_priv
->dev
;
9172 if (IS_HASWELL(dev
)) {
9173 mutex_lock(&dev_priv
->rps
.hw_lock
);
9174 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9176 DRM_ERROR("Failed to write to D_COMP\n");
9177 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9179 I915_WRITE(D_COMP_BDW
, val
);
9180 POSTING_READ(D_COMP_BDW
);
9185 * This function implements pieces of two sequences from BSpec:
9186 * - Sequence for display software to disable LCPLL
9187 * - Sequence for display software to allow package C8+
9188 * The steps implemented here are just the steps that actually touch the LCPLL
9189 * register. Callers should take care of disabling all the display engine
9190 * functions, doing the mode unset, fixing interrupts, etc.
9192 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9193 bool switch_to_fclk
, bool allow_power_down
)
9197 assert_can_disable_lcpll(dev_priv
);
9199 val
= I915_READ(LCPLL_CTL
);
9201 if (switch_to_fclk
) {
9202 val
|= LCPLL_CD_SOURCE_FCLK
;
9203 I915_WRITE(LCPLL_CTL
, val
);
9205 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9206 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9207 DRM_ERROR("Switching to FCLK failed\n");
9209 val
= I915_READ(LCPLL_CTL
);
9212 val
|= LCPLL_PLL_DISABLE
;
9213 I915_WRITE(LCPLL_CTL
, val
);
9214 POSTING_READ(LCPLL_CTL
);
9216 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9217 DRM_ERROR("LCPLL still locked\n");
9219 val
= hsw_read_dcomp(dev_priv
);
9220 val
|= D_COMP_COMP_DISABLE
;
9221 hsw_write_dcomp(dev_priv
, val
);
9224 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9226 DRM_ERROR("D_COMP RCOMP still in progress\n");
9228 if (allow_power_down
) {
9229 val
= I915_READ(LCPLL_CTL
);
9230 val
|= LCPLL_POWER_DOWN_ALLOW
;
9231 I915_WRITE(LCPLL_CTL
, val
);
9232 POSTING_READ(LCPLL_CTL
);
9237 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9240 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9244 val
= I915_READ(LCPLL_CTL
);
9246 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9247 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9251 * Make sure we're not on PC8 state before disabling PC8, otherwise
9252 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9254 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9256 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9257 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9258 I915_WRITE(LCPLL_CTL
, val
);
9259 POSTING_READ(LCPLL_CTL
);
9262 val
= hsw_read_dcomp(dev_priv
);
9263 val
|= D_COMP_COMP_FORCE
;
9264 val
&= ~D_COMP_COMP_DISABLE
;
9265 hsw_write_dcomp(dev_priv
, val
);
9267 val
= I915_READ(LCPLL_CTL
);
9268 val
&= ~LCPLL_PLL_DISABLE
;
9269 I915_WRITE(LCPLL_CTL
, val
);
9271 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9272 DRM_ERROR("LCPLL not locked yet\n");
9274 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9275 val
= I915_READ(LCPLL_CTL
);
9276 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9277 I915_WRITE(LCPLL_CTL
, val
);
9279 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9280 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9281 DRM_ERROR("Switching back to LCPLL failed\n");
9284 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9288 * Package states C8 and deeper are really deep PC states that can only be
9289 * reached when all the devices on the system allow it, so even if the graphics
9290 * device allows PC8+, it doesn't mean the system will actually get to these
9291 * states. Our driver only allows PC8+ when going into runtime PM.
9293 * The requirements for PC8+ are that all the outputs are disabled, the power
9294 * well is disabled and most interrupts are disabled, and these are also
9295 * requirements for runtime PM. When these conditions are met, we manually do
9296 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9297 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9300 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9301 * the state of some registers, so when we come back from PC8+ we need to
9302 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9303 * need to take care of the registers kept by RC6. Notice that this happens even
9304 * if we don't put the device in PCI D3 state (which is what currently happens
9305 * because of the runtime PM support).
9307 * For more, read "Display Sequences for Package C8" on the hardware
9310 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9312 struct drm_device
*dev
= dev_priv
->dev
;
9315 DRM_DEBUG_KMS("Enabling package C8+\n");
9317 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9318 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9319 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9320 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9323 lpt_disable_clkout_dp(dev
);
9324 hsw_disable_lcpll(dev_priv
, true, true);
9327 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9329 struct drm_device
*dev
= dev_priv
->dev
;
9332 DRM_DEBUG_KMS("Disabling package C8+\n");
9334 hsw_restore_lcpll(dev_priv
);
9335 lpt_init_pch_refclk(dev
);
9337 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9338 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9339 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9340 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9343 intel_prepare_ddi(dev
);
9346 static void broxton_modeset_global_resources(struct drm_atomic_state
*old_state
)
9348 struct drm_device
*dev
= old_state
->dev
;
9349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9350 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
9353 /* see the comment in valleyview_modeset_global_resources */
9354 if (WARN_ON(max_pixclk
< 0))
9357 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9359 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9360 broxton_set_cdclk(dev
, req_cdclk
);
9363 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9364 struct intel_crtc_state
*crtc_state
)
9366 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9369 crtc
->lowfreq_avail
= false;
9374 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9376 struct intel_crtc_state
*pipe_config
)
9380 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9381 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9384 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9385 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9388 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9389 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9392 DRM_ERROR("Incorrect port type\n");
9396 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9398 struct intel_crtc_state
*pipe_config
)
9400 u32 temp
, dpll_ctl1
;
9402 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9403 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9405 switch (pipe_config
->ddi_pll_sel
) {
9408 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9409 * of the shared DPLL framework and thus needs to be read out
9412 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9413 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9416 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9419 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9422 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9427 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9429 struct intel_crtc_state
*pipe_config
)
9431 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9433 switch (pipe_config
->ddi_pll_sel
) {
9434 case PORT_CLK_SEL_WRPLL1
:
9435 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9437 case PORT_CLK_SEL_WRPLL2
:
9438 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9443 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9444 struct intel_crtc_state
*pipe_config
)
9446 struct drm_device
*dev
= crtc
->base
.dev
;
9447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9448 struct intel_shared_dpll
*pll
;
9452 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9454 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9456 if (IS_SKYLAKE(dev
))
9457 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9458 else if (IS_BROXTON(dev
))
9459 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9461 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9463 if (pipe_config
->shared_dpll
>= 0) {
9464 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9466 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9467 &pipe_config
->dpll_hw_state
));
9471 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9472 * DDI E. So just check whether this pipe is wired to DDI E and whether
9473 * the PCH transcoder is on.
9475 if (INTEL_INFO(dev
)->gen
< 9 &&
9476 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9477 pipe_config
->has_pch_encoder
= true;
9479 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9480 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9481 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9483 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9487 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9488 struct intel_crtc_state
*pipe_config
)
9490 struct drm_device
*dev
= crtc
->base
.dev
;
9491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9492 enum intel_display_power_domain pfit_domain
;
9495 if (!intel_display_power_is_enabled(dev_priv
,
9496 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9499 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9500 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9502 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9503 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9504 enum pipe trans_edp_pipe
;
9505 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9507 WARN(1, "unknown pipe linked to edp transcoder\n");
9508 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9509 case TRANS_DDI_EDP_INPUT_A_ON
:
9510 trans_edp_pipe
= PIPE_A
;
9512 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9513 trans_edp_pipe
= PIPE_B
;
9515 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9516 trans_edp_pipe
= PIPE_C
;
9520 if (trans_edp_pipe
== crtc
->pipe
)
9521 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9524 if (!intel_display_power_is_enabled(dev_priv
,
9525 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9528 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9529 if (!(tmp
& PIPECONF_ENABLE
))
9532 haswell_get_ddi_port_state(crtc
, pipe_config
);
9534 intel_get_pipe_timings(crtc
, pipe_config
);
9536 if (INTEL_INFO(dev
)->gen
>= 9) {
9537 skl_init_scalers(dev
, crtc
, pipe_config
);
9540 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9542 if (INTEL_INFO(dev
)->gen
>= 9) {
9543 pipe_config
->scaler_state
.scaler_id
= -1;
9544 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9547 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9548 if (INTEL_INFO(dev
)->gen
== 9)
9549 skylake_get_pfit_config(crtc
, pipe_config
);
9550 else if (INTEL_INFO(dev
)->gen
< 9)
9551 ironlake_get_pfit_config(crtc
, pipe_config
);
9553 MISSING_CASE(INTEL_INFO(dev
)->gen
);
9556 if (IS_HASWELL(dev
))
9557 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9558 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9560 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9561 pipe_config
->pixel_multiplier
=
9562 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9564 pipe_config
->pixel_multiplier
= 1;
9570 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9572 struct drm_device
*dev
= crtc
->dev
;
9573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9574 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9575 uint32_t cntl
= 0, size
= 0;
9578 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9579 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9580 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9584 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9595 cntl
|= CURSOR_ENABLE
|
9596 CURSOR_GAMMA_ENABLE
|
9597 CURSOR_FORMAT_ARGB
|
9598 CURSOR_STRIDE(stride
);
9600 size
= (height
<< 12) | width
;
9603 if (intel_crtc
->cursor_cntl
!= 0 &&
9604 (intel_crtc
->cursor_base
!= base
||
9605 intel_crtc
->cursor_size
!= size
||
9606 intel_crtc
->cursor_cntl
!= cntl
)) {
9607 /* On these chipsets we can only modify the base/size/stride
9608 * whilst the cursor is disabled.
9610 I915_WRITE(_CURACNTR
, 0);
9611 POSTING_READ(_CURACNTR
);
9612 intel_crtc
->cursor_cntl
= 0;
9615 if (intel_crtc
->cursor_base
!= base
) {
9616 I915_WRITE(_CURABASE
, base
);
9617 intel_crtc
->cursor_base
= base
;
9620 if (intel_crtc
->cursor_size
!= size
) {
9621 I915_WRITE(CURSIZE
, size
);
9622 intel_crtc
->cursor_size
= size
;
9625 if (intel_crtc
->cursor_cntl
!= cntl
) {
9626 I915_WRITE(_CURACNTR
, cntl
);
9627 POSTING_READ(_CURACNTR
);
9628 intel_crtc
->cursor_cntl
= cntl
;
9632 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9634 struct drm_device
*dev
= crtc
->dev
;
9635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9636 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9637 int pipe
= intel_crtc
->pipe
;
9642 cntl
= MCURSOR_GAMMA_ENABLE
;
9643 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9645 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9648 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9651 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9654 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9657 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9659 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9660 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9663 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9664 cntl
|= CURSOR_ROTATE_180
;
9666 if (intel_crtc
->cursor_cntl
!= cntl
) {
9667 I915_WRITE(CURCNTR(pipe
), cntl
);
9668 POSTING_READ(CURCNTR(pipe
));
9669 intel_crtc
->cursor_cntl
= cntl
;
9672 /* and commit changes on next vblank */
9673 I915_WRITE(CURBASE(pipe
), base
);
9674 POSTING_READ(CURBASE(pipe
));
9676 intel_crtc
->cursor_base
= base
;
9679 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9680 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9683 struct drm_device
*dev
= crtc
->dev
;
9684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9685 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9686 int pipe
= intel_crtc
->pipe
;
9687 int x
= crtc
->cursor_x
;
9688 int y
= crtc
->cursor_y
;
9689 u32 base
= 0, pos
= 0;
9692 base
= intel_crtc
->cursor_addr
;
9694 if (x
>= intel_crtc
->config
->pipe_src_w
)
9697 if (y
>= intel_crtc
->config
->pipe_src_h
)
9701 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
9704 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9707 pos
|= x
<< CURSOR_X_SHIFT
;
9710 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
9713 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9716 pos
|= y
<< CURSOR_Y_SHIFT
;
9718 if (base
== 0 && intel_crtc
->cursor_base
== 0)
9721 I915_WRITE(CURPOS(pipe
), pos
);
9723 /* ILK+ do this automagically */
9724 if (HAS_GMCH_DISPLAY(dev
) &&
9725 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
9726 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
9727 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
9730 if (IS_845G(dev
) || IS_I865G(dev
))
9731 i845_update_cursor(crtc
, base
);
9733 i9xx_update_cursor(crtc
, base
);
9736 static bool cursor_size_ok(struct drm_device
*dev
,
9737 uint32_t width
, uint32_t height
)
9739 if (width
== 0 || height
== 0)
9743 * 845g/865g are special in that they are only limited by
9744 * the width of their cursors, the height is arbitrary up to
9745 * the precision of the register. Everything else requires
9746 * square cursors, limited to a few power-of-two sizes.
9748 if (IS_845G(dev
) || IS_I865G(dev
)) {
9749 if ((width
& 63) != 0)
9752 if (width
> (IS_845G(dev
) ? 64 : 512))
9758 switch (width
| height
) {
9773 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
9774 u16
*blue
, uint32_t start
, uint32_t size
)
9776 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
9777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9779 for (i
= start
; i
< end
; i
++) {
9780 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
9781 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
9782 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
9785 intel_crtc_load_lut(crtc
);
9788 /* VESA 640x480x72Hz mode to set on the pipe */
9789 static struct drm_display_mode load_detect_mode
= {
9790 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9791 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9794 struct drm_framebuffer
*
9795 __intel_framebuffer_create(struct drm_device
*dev
,
9796 struct drm_mode_fb_cmd2
*mode_cmd
,
9797 struct drm_i915_gem_object
*obj
)
9799 struct intel_framebuffer
*intel_fb
;
9802 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9804 drm_gem_object_unreference(&obj
->base
);
9805 return ERR_PTR(-ENOMEM
);
9808 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
9812 return &intel_fb
->base
;
9814 drm_gem_object_unreference(&obj
->base
);
9817 return ERR_PTR(ret
);
9820 static struct drm_framebuffer
*
9821 intel_framebuffer_create(struct drm_device
*dev
,
9822 struct drm_mode_fb_cmd2
*mode_cmd
,
9823 struct drm_i915_gem_object
*obj
)
9825 struct drm_framebuffer
*fb
;
9828 ret
= i915_mutex_lock_interruptible(dev
);
9830 return ERR_PTR(ret
);
9831 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
9832 mutex_unlock(&dev
->struct_mutex
);
9838 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9840 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9841 return ALIGN(pitch
, 64);
9845 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9847 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9848 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9851 static struct drm_framebuffer
*
9852 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9853 struct drm_display_mode
*mode
,
9856 struct drm_i915_gem_object
*obj
;
9857 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9859 obj
= i915_gem_alloc_object(dev
,
9860 intel_framebuffer_size_for_mode(mode
, bpp
));
9862 return ERR_PTR(-ENOMEM
);
9864 mode_cmd
.width
= mode
->hdisplay
;
9865 mode_cmd
.height
= mode
->vdisplay
;
9866 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9868 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9870 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9873 static struct drm_framebuffer
*
9874 mode_fits_in_fbdev(struct drm_device
*dev
,
9875 struct drm_display_mode
*mode
)
9877 #ifdef CONFIG_DRM_I915_FBDEV
9878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9879 struct drm_i915_gem_object
*obj
;
9880 struct drm_framebuffer
*fb
;
9882 if (!dev_priv
->fbdev
)
9885 if (!dev_priv
->fbdev
->fb
)
9888 obj
= dev_priv
->fbdev
->fb
->obj
;
9891 fb
= &dev_priv
->fbdev
->fb
->base
;
9892 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9893 fb
->bits_per_pixel
))
9896 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9905 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
9906 struct drm_crtc
*crtc
,
9907 struct drm_display_mode
*mode
,
9908 struct drm_framebuffer
*fb
,
9911 struct drm_plane_state
*plane_state
;
9912 int hdisplay
, vdisplay
;
9915 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
9916 if (IS_ERR(plane_state
))
9917 return PTR_ERR(plane_state
);
9920 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
9922 hdisplay
= vdisplay
= 0;
9924 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
9927 drm_atomic_set_fb_for_plane(plane_state
, fb
);
9928 plane_state
->crtc_x
= 0;
9929 plane_state
->crtc_y
= 0;
9930 plane_state
->crtc_w
= hdisplay
;
9931 plane_state
->crtc_h
= vdisplay
;
9932 plane_state
->src_x
= x
<< 16;
9933 plane_state
->src_y
= y
<< 16;
9934 plane_state
->src_w
= hdisplay
<< 16;
9935 plane_state
->src_h
= vdisplay
<< 16;
9940 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9941 struct drm_display_mode
*mode
,
9942 struct intel_load_detect_pipe
*old
,
9943 struct drm_modeset_acquire_ctx
*ctx
)
9945 struct intel_crtc
*intel_crtc
;
9946 struct intel_encoder
*intel_encoder
=
9947 intel_attached_encoder(connector
);
9948 struct drm_crtc
*possible_crtc
;
9949 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9950 struct drm_crtc
*crtc
= NULL
;
9951 struct drm_device
*dev
= encoder
->dev
;
9952 struct drm_framebuffer
*fb
;
9953 struct drm_mode_config
*config
= &dev
->mode_config
;
9954 struct drm_atomic_state
*state
= NULL
;
9955 struct drm_connector_state
*connector_state
;
9956 struct intel_crtc_state
*crtc_state
;
9959 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9960 connector
->base
.id
, connector
->name
,
9961 encoder
->base
.id
, encoder
->name
);
9964 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9969 * Algorithm gets a little messy:
9971 * - if the connector already has an assigned crtc, use it (but make
9972 * sure it's on first)
9974 * - try to find the first unused crtc that can drive this connector,
9975 * and use that if we find one
9978 /* See if we already have a CRTC for this connector */
9979 if (encoder
->crtc
) {
9980 crtc
= encoder
->crtc
;
9982 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9985 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9989 old
->dpms_mode
= connector
->dpms
;
9990 old
->load_detect_temp
= false;
9992 /* Make sure the crtc and connector are running */
9993 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9994 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9999 /* Find an unused one (if possible) */
10000 for_each_crtc(dev
, possible_crtc
) {
10002 if (!(encoder
->possible_crtcs
& (1 << i
)))
10004 if (possible_crtc
->state
->enable
)
10006 /* This can occur when applying the pipe A quirk on resume. */
10007 if (to_intel_crtc(possible_crtc
)->new_enabled
)
10010 crtc
= possible_crtc
;
10015 * If we didn't find an unused CRTC, don't use any.
10018 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10022 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10025 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10028 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
10029 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
10031 intel_crtc
= to_intel_crtc(crtc
);
10032 intel_crtc
->new_enabled
= true;
10033 old
->dpms_mode
= connector
->dpms
;
10034 old
->load_detect_temp
= true;
10035 old
->release_fb
= NULL
;
10037 state
= drm_atomic_state_alloc(dev
);
10041 state
->acquire_ctx
= ctx
;
10043 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10044 if (IS_ERR(connector_state
)) {
10045 ret
= PTR_ERR(connector_state
);
10049 connector_state
->crtc
= crtc
;
10050 connector_state
->best_encoder
= &intel_encoder
->base
;
10052 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10053 if (IS_ERR(crtc_state
)) {
10054 ret
= PTR_ERR(crtc_state
);
10058 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10061 mode
= &load_detect_mode
;
10063 /* We need a framebuffer large enough to accommodate all accesses
10064 * that the plane may generate whilst we perform load detection.
10065 * We can not rely on the fbcon either being present (we get called
10066 * during its initialisation to detect all boot displays, or it may
10067 * not even exist) or that it is large enough to satisfy the
10070 fb
= mode_fits_in_fbdev(dev
, mode
);
10072 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10073 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10074 old
->release_fb
= fb
;
10076 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10078 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10082 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10086 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
10088 if (intel_set_mode(crtc
, state
)) {
10089 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10090 if (old
->release_fb
)
10091 old
->release_fb
->funcs
->destroy(old
->release_fb
);
10094 crtc
->primary
->crtc
= crtc
;
10096 /* let the connector get through one full cycle before testing */
10097 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10101 intel_crtc
->new_enabled
= crtc
->state
->enable
;
10103 drm_atomic_state_free(state
);
10106 if (ret
== -EDEADLK
) {
10107 drm_modeset_backoff(ctx
);
10114 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10115 struct intel_load_detect_pipe
*old
,
10116 struct drm_modeset_acquire_ctx
*ctx
)
10118 struct drm_device
*dev
= connector
->dev
;
10119 struct intel_encoder
*intel_encoder
=
10120 intel_attached_encoder(connector
);
10121 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10122 struct drm_crtc
*crtc
= encoder
->crtc
;
10123 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10124 struct drm_atomic_state
*state
;
10125 struct drm_connector_state
*connector_state
;
10126 struct intel_crtc_state
*crtc_state
;
10129 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10130 connector
->base
.id
, connector
->name
,
10131 encoder
->base
.id
, encoder
->name
);
10133 if (old
->load_detect_temp
) {
10134 state
= drm_atomic_state_alloc(dev
);
10138 state
->acquire_ctx
= ctx
;
10140 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10141 if (IS_ERR(connector_state
))
10144 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10145 if (IS_ERR(crtc_state
))
10148 to_intel_connector(connector
)->new_encoder
= NULL
;
10149 intel_encoder
->new_crtc
= NULL
;
10150 intel_crtc
->new_enabled
= false;
10152 connector_state
->best_encoder
= NULL
;
10153 connector_state
->crtc
= NULL
;
10155 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
10157 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
10162 ret
= intel_set_mode(crtc
, state
);
10166 if (old
->release_fb
) {
10167 drm_framebuffer_unregister_private(old
->release_fb
);
10168 drm_framebuffer_unreference(old
->release_fb
);
10174 /* Switch crtc and encoder back off if necessary */
10175 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
10176 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10180 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10181 drm_atomic_state_free(state
);
10184 static int i9xx_pll_refclk(struct drm_device
*dev
,
10185 const struct intel_crtc_state
*pipe_config
)
10187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10188 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10190 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10191 return dev_priv
->vbt
.lvds_ssc_freq
;
10192 else if (HAS_PCH_SPLIT(dev
))
10194 else if (!IS_GEN2(dev
))
10200 /* Returns the clock of the currently programmed mode of the given pipe. */
10201 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10202 struct intel_crtc_state
*pipe_config
)
10204 struct drm_device
*dev
= crtc
->base
.dev
;
10205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10206 int pipe
= pipe_config
->cpu_transcoder
;
10207 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10209 intel_clock_t clock
;
10210 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10212 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10213 fp
= pipe_config
->dpll_hw_state
.fp0
;
10215 fp
= pipe_config
->dpll_hw_state
.fp1
;
10217 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10218 if (IS_PINEVIEW(dev
)) {
10219 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10220 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10222 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10223 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10226 if (!IS_GEN2(dev
)) {
10227 if (IS_PINEVIEW(dev
))
10228 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10229 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10231 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10232 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10234 switch (dpll
& DPLL_MODE_MASK
) {
10235 case DPLLB_MODE_DAC_SERIAL
:
10236 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10239 case DPLLB_MODE_LVDS
:
10240 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10244 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10245 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10249 if (IS_PINEVIEW(dev
))
10250 pineview_clock(refclk
, &clock
);
10252 i9xx_clock(refclk
, &clock
);
10254 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10255 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10258 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10259 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10261 if (lvds
& LVDS_CLKB_POWER_UP
)
10266 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10269 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10270 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10272 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10278 i9xx_clock(refclk
, &clock
);
10282 * This value includes pixel_multiplier. We will use
10283 * port_clock to compute adjusted_mode.crtc_clock in the
10284 * encoder's get_config() function.
10286 pipe_config
->port_clock
= clock
.dot
;
10289 int intel_dotclock_calculate(int link_freq
,
10290 const struct intel_link_m_n
*m_n
)
10293 * The calculation for the data clock is:
10294 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10295 * But we want to avoid losing precison if possible, so:
10296 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10298 * and the link clock is simpler:
10299 * link_clock = (m * link_clock) / n
10305 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10308 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10309 struct intel_crtc_state
*pipe_config
)
10311 struct drm_device
*dev
= crtc
->base
.dev
;
10313 /* read out port_clock from the DPLL */
10314 i9xx_crtc_clock_get(crtc
, pipe_config
);
10317 * This value does not include pixel_multiplier.
10318 * We will check that port_clock and adjusted_mode.crtc_clock
10319 * agree once we know their relationship in the encoder's
10320 * get_config() function.
10322 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10323 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10324 &pipe_config
->fdi_m_n
);
10327 /** Returns the currently programmed mode of the given pipe. */
10328 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10329 struct drm_crtc
*crtc
)
10331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10333 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10334 struct drm_display_mode
*mode
;
10335 struct intel_crtc_state pipe_config
;
10336 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10337 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10338 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10339 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10340 enum pipe pipe
= intel_crtc
->pipe
;
10342 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10347 * Construct a pipe_config sufficient for getting the clock info
10348 * back out of crtc_clock_get.
10350 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10351 * to use a real value here instead.
10353 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10354 pipe_config
.pixel_multiplier
= 1;
10355 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10356 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10357 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10358 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10360 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10361 mode
->hdisplay
= (htot
& 0xffff) + 1;
10362 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10363 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10364 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10365 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10366 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10367 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10368 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10370 drm_mode_set_name(mode
);
10375 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10377 struct drm_device
*dev
= crtc
->dev
;
10378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10379 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10381 if (!HAS_GMCH_DISPLAY(dev
))
10384 if (!dev_priv
->lvds_downclock_avail
)
10388 * Since this is called by a timer, we should never get here in
10391 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10392 int pipe
= intel_crtc
->pipe
;
10393 int dpll_reg
= DPLL(pipe
);
10396 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10398 assert_panel_unlocked(dev_priv
, pipe
);
10400 dpll
= I915_READ(dpll_reg
);
10401 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10402 I915_WRITE(dpll_reg
, dpll
);
10403 intel_wait_for_vblank(dev
, pipe
);
10404 dpll
= I915_READ(dpll_reg
);
10405 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10406 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10411 void intel_mark_busy(struct drm_device
*dev
)
10413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10415 if (dev_priv
->mm
.busy
)
10418 intel_runtime_pm_get(dev_priv
);
10419 i915_update_gfx_val(dev_priv
);
10420 if (INTEL_INFO(dev
)->gen
>= 6)
10421 gen6_rps_busy(dev_priv
);
10422 dev_priv
->mm
.busy
= true;
10425 void intel_mark_idle(struct drm_device
*dev
)
10427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10428 struct drm_crtc
*crtc
;
10430 if (!dev_priv
->mm
.busy
)
10433 dev_priv
->mm
.busy
= false;
10435 for_each_crtc(dev
, crtc
) {
10436 if (!crtc
->primary
->fb
)
10439 intel_decrease_pllclock(crtc
);
10442 if (INTEL_INFO(dev
)->gen
>= 6)
10443 gen6_rps_idle(dev
->dev_private
);
10445 intel_runtime_pm_put(dev_priv
);
10448 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10450 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10451 struct drm_device
*dev
= crtc
->dev
;
10452 struct intel_unpin_work
*work
;
10454 spin_lock_irq(&dev
->event_lock
);
10455 work
= intel_crtc
->unpin_work
;
10456 intel_crtc
->unpin_work
= NULL
;
10457 spin_unlock_irq(&dev
->event_lock
);
10460 cancel_work_sync(&work
->work
);
10464 drm_crtc_cleanup(crtc
);
10469 static void intel_unpin_work_fn(struct work_struct
*__work
)
10471 struct intel_unpin_work
*work
=
10472 container_of(__work
, struct intel_unpin_work
, work
);
10473 struct drm_device
*dev
= work
->crtc
->dev
;
10474 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10476 mutex_lock(&dev
->struct_mutex
);
10477 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10478 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10480 intel_fbc_update(dev
);
10482 if (work
->flip_queued_req
)
10483 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10484 mutex_unlock(&dev
->struct_mutex
);
10486 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10487 drm_framebuffer_unreference(work
->old_fb
);
10489 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10490 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10495 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10496 struct drm_crtc
*crtc
)
10498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10499 struct intel_unpin_work
*work
;
10500 unsigned long flags
;
10502 /* Ignore early vblank irqs */
10503 if (intel_crtc
== NULL
)
10507 * This is called both by irq handlers and the reset code (to complete
10508 * lost pageflips) so needs the full irqsave spinlocks.
10510 spin_lock_irqsave(&dev
->event_lock
, flags
);
10511 work
= intel_crtc
->unpin_work
;
10513 /* Ensure we don't miss a work->pending update ... */
10516 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10517 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10521 page_flip_completed(intel_crtc
);
10523 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10526 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10529 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10531 do_intel_finish_page_flip(dev
, crtc
);
10534 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10537 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10539 do_intel_finish_page_flip(dev
, crtc
);
10542 /* Is 'a' after or equal to 'b'? */
10543 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10545 return !((a
- b
) & 0x80000000);
10548 static bool page_flip_finished(struct intel_crtc
*crtc
)
10550 struct drm_device
*dev
= crtc
->base
.dev
;
10551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10553 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10554 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10558 * The relevant registers doen't exist on pre-ctg.
10559 * As the flip done interrupt doesn't trigger for mmio
10560 * flips on gmch platforms, a flip count check isn't
10561 * really needed there. But since ctg has the registers,
10562 * include it in the check anyway.
10564 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10568 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10569 * used the same base address. In that case the mmio flip might
10570 * have completed, but the CS hasn't even executed the flip yet.
10572 * A flip count check isn't enough as the CS might have updated
10573 * the base address just after start of vblank, but before we
10574 * managed to process the interrupt. This means we'd complete the
10575 * CS flip too soon.
10577 * Combining both checks should get us a good enough result. It may
10578 * still happen that the CS flip has been executed, but has not
10579 * yet actually completed. But in case the base address is the same
10580 * anyway, we don't really care.
10582 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10583 crtc
->unpin_work
->gtt_offset
&&
10584 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10585 crtc
->unpin_work
->flip_count
);
10588 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10591 struct intel_crtc
*intel_crtc
=
10592 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10593 unsigned long flags
;
10597 * This is called both by irq handlers and the reset code (to complete
10598 * lost pageflips) so needs the full irqsave spinlocks.
10600 * NB: An MMIO update of the plane base pointer will also
10601 * generate a page-flip completion irq, i.e. every modeset
10602 * is also accompanied by a spurious intel_prepare_page_flip().
10604 spin_lock_irqsave(&dev
->event_lock
, flags
);
10605 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10606 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10607 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10610 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10612 /* Ensure that the work item is consistent when activating it ... */
10614 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10615 /* and that it is marked active as soon as the irq could fire. */
10619 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10620 struct drm_crtc
*crtc
,
10621 struct drm_framebuffer
*fb
,
10622 struct drm_i915_gem_object
*obj
,
10623 struct intel_engine_cs
*ring
,
10626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10630 ret
= intel_ring_begin(ring
, 6);
10634 /* Can't queue multiple flips, so wait for the previous
10635 * one to finish before executing the next.
10637 if (intel_crtc
->plane
)
10638 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10640 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10641 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10642 intel_ring_emit(ring
, MI_NOOP
);
10643 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10644 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10645 intel_ring_emit(ring
, fb
->pitches
[0]);
10646 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10647 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10649 intel_mark_page_flip_active(intel_crtc
);
10650 __intel_ring_advance(ring
);
10654 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10655 struct drm_crtc
*crtc
,
10656 struct drm_framebuffer
*fb
,
10657 struct drm_i915_gem_object
*obj
,
10658 struct intel_engine_cs
*ring
,
10661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10665 ret
= intel_ring_begin(ring
, 6);
10669 if (intel_crtc
->plane
)
10670 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10672 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10673 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10674 intel_ring_emit(ring
, MI_NOOP
);
10675 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10676 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10677 intel_ring_emit(ring
, fb
->pitches
[0]);
10678 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10679 intel_ring_emit(ring
, MI_NOOP
);
10681 intel_mark_page_flip_active(intel_crtc
);
10682 __intel_ring_advance(ring
);
10686 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10687 struct drm_crtc
*crtc
,
10688 struct drm_framebuffer
*fb
,
10689 struct drm_i915_gem_object
*obj
,
10690 struct intel_engine_cs
*ring
,
10693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10694 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10695 uint32_t pf
, pipesrc
;
10698 ret
= intel_ring_begin(ring
, 4);
10702 /* i965+ uses the linear or tiled offsets from the
10703 * Display Registers (which do not change across a page-flip)
10704 * so we need only reprogram the base address.
10706 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10707 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10708 intel_ring_emit(ring
, fb
->pitches
[0]);
10709 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10712 /* XXX Enabling the panel-fitter across page-flip is so far
10713 * untested on non-native modes, so ignore it for now.
10714 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10717 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10718 intel_ring_emit(ring
, pf
| pipesrc
);
10720 intel_mark_page_flip_active(intel_crtc
);
10721 __intel_ring_advance(ring
);
10725 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10726 struct drm_crtc
*crtc
,
10727 struct drm_framebuffer
*fb
,
10728 struct drm_i915_gem_object
*obj
,
10729 struct intel_engine_cs
*ring
,
10732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10734 uint32_t pf
, pipesrc
;
10737 ret
= intel_ring_begin(ring
, 4);
10741 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10742 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10743 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10744 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10746 /* Contrary to the suggestions in the documentation,
10747 * "Enable Panel Fitter" does not seem to be required when page
10748 * flipping with a non-native mode, and worse causes a normal
10750 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10753 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10754 intel_ring_emit(ring
, pf
| pipesrc
);
10756 intel_mark_page_flip_active(intel_crtc
);
10757 __intel_ring_advance(ring
);
10761 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10762 struct drm_crtc
*crtc
,
10763 struct drm_framebuffer
*fb
,
10764 struct drm_i915_gem_object
*obj
,
10765 struct intel_engine_cs
*ring
,
10768 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10769 uint32_t plane_bit
= 0;
10772 switch (intel_crtc
->plane
) {
10774 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
10777 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
10780 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
10783 WARN_ONCE(1, "unknown plane in flip command\n");
10788 if (ring
->id
== RCS
) {
10791 * On Gen 8, SRM is now taking an extra dword to accommodate
10792 * 48bits addresses, and we need a NOOP for the batch size to
10800 * BSpec MI_DISPLAY_FLIP for IVB:
10801 * "The full packet must be contained within the same cache line."
10803 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10804 * cacheline, if we ever start emitting more commands before
10805 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10806 * then do the cacheline alignment, and finally emit the
10809 ret
= intel_ring_cacheline_align(ring
);
10813 ret
= intel_ring_begin(ring
, len
);
10817 /* Unmask the flip-done completion message. Note that the bspec says that
10818 * we should do this for both the BCS and RCS, and that we must not unmask
10819 * more than one flip event at any time (or ensure that one flip message
10820 * can be sent by waiting for flip-done prior to queueing new flips).
10821 * Experimentation says that BCS works despite DERRMR masking all
10822 * flip-done completion events and that unmasking all planes at once
10823 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10824 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10826 if (ring
->id
== RCS
) {
10827 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
10828 intel_ring_emit(ring
, DERRMR
);
10829 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
10830 DERRMR_PIPEB_PRI_FLIP_DONE
|
10831 DERRMR_PIPEC_PRI_FLIP_DONE
));
10833 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
10834 MI_SRM_LRM_GLOBAL_GTT
);
10836 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
10837 MI_SRM_LRM_GLOBAL_GTT
);
10838 intel_ring_emit(ring
, DERRMR
);
10839 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
10840 if (IS_GEN8(dev
)) {
10841 intel_ring_emit(ring
, 0);
10842 intel_ring_emit(ring
, MI_NOOP
);
10846 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
10847 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
10848 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10849 intel_ring_emit(ring
, (MI_NOOP
));
10851 intel_mark_page_flip_active(intel_crtc
);
10852 __intel_ring_advance(ring
);
10856 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
10857 struct drm_i915_gem_object
*obj
)
10860 * This is not being used for older platforms, because
10861 * non-availability of flip done interrupt forces us to use
10862 * CS flips. Older platforms derive flip done using some clever
10863 * tricks involving the flip_pending status bits and vblank irqs.
10864 * So using MMIO flips there would disrupt this mechanism.
10870 if (INTEL_INFO(ring
->dev
)->gen
< 5)
10873 if (i915
.use_mmio_flip
< 0)
10875 else if (i915
.use_mmio_flip
> 0)
10877 else if (i915
.enable_execlists
)
10880 return ring
!= i915_gem_request_get_ring(obj
->last_write_req
);
10883 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10885 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10887 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
10888 const enum pipe pipe
= intel_crtc
->pipe
;
10891 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10892 ctl
&= ~PLANE_CTL_TILED_MASK
;
10893 switch (fb
->modifier
[0]) {
10894 case DRM_FORMAT_MOD_NONE
:
10896 case I915_FORMAT_MOD_X_TILED
:
10897 ctl
|= PLANE_CTL_TILED_X
;
10899 case I915_FORMAT_MOD_Y_TILED
:
10900 ctl
|= PLANE_CTL_TILED_Y
;
10902 case I915_FORMAT_MOD_Yf_TILED
:
10903 ctl
|= PLANE_CTL_TILED_YF
;
10906 MISSING_CASE(fb
->modifier
[0]);
10910 * The stride is either expressed as a multiple of 64 bytes chunks for
10911 * linear buffers or in number of tiles for tiled buffers.
10913 stride
= fb
->pitches
[0] /
10914 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
10918 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10919 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10921 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10922 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10924 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10925 POSTING_READ(PLANE_SURF(pipe
, 0));
10928 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10930 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10932 struct intel_framebuffer
*intel_fb
=
10933 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10934 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10938 reg
= DSPCNTR(intel_crtc
->plane
);
10939 dspcntr
= I915_READ(reg
);
10941 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10942 dspcntr
|= DISPPLANE_TILED
;
10944 dspcntr
&= ~DISPPLANE_TILED
;
10946 I915_WRITE(reg
, dspcntr
);
10948 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10949 intel_crtc
->unpin_work
->gtt_offset
);
10950 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10955 * XXX: This is the temporary way to update the plane registers until we get
10956 * around to using the usual plane update functions for MMIO flips
10958 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10960 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10961 bool atomic_update
;
10962 u32 start_vbl_count
;
10964 intel_mark_page_flip_active(intel_crtc
);
10966 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10968 if (INTEL_INFO(dev
)->gen
>= 9)
10969 skl_do_mmio_flip(intel_crtc
);
10971 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10972 ilk_do_mmio_flip(intel_crtc
);
10975 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10978 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10980 struct intel_mmio_flip
*mmio_flip
=
10981 container_of(work
, struct intel_mmio_flip
, work
);
10983 if (mmio_flip
->req
)
10984 WARN_ON(__i915_wait_request(mmio_flip
->req
,
10985 mmio_flip
->crtc
->reset_counter
,
10987 &mmio_flip
->i915
->rps
.mmioflips
));
10989 intel_do_mmio_flip(mmio_flip
->crtc
);
10991 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
10995 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10996 struct drm_crtc
*crtc
,
10997 struct drm_framebuffer
*fb
,
10998 struct drm_i915_gem_object
*obj
,
10999 struct intel_engine_cs
*ring
,
11002 struct intel_mmio_flip
*mmio_flip
;
11004 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11005 if (mmio_flip
== NULL
)
11008 mmio_flip
->i915
= to_i915(dev
);
11009 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11010 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11012 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11013 schedule_work(&mmio_flip
->work
);
11018 static int intel_default_queue_flip(struct drm_device
*dev
,
11019 struct drm_crtc
*crtc
,
11020 struct drm_framebuffer
*fb
,
11021 struct drm_i915_gem_object
*obj
,
11022 struct intel_engine_cs
*ring
,
11028 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11029 struct drm_crtc
*crtc
)
11031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11032 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11033 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11036 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11039 if (!work
->enable_stall_check
)
11042 if (work
->flip_ready_vblank
== 0) {
11043 if (work
->flip_queued_req
&&
11044 !i915_gem_request_completed(work
->flip_queued_req
, true))
11047 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11050 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11053 /* Potential stall - if we see that the flip has happened,
11054 * assume a missed interrupt. */
11055 if (INTEL_INFO(dev
)->gen
>= 4)
11056 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11058 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11060 /* There is a potential issue here with a false positive after a flip
11061 * to the same address. We could address this by checking for a
11062 * non-incrementing frame counter.
11064 return addr
== work
->gtt_offset
;
11067 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11070 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11071 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11072 struct intel_unpin_work
*work
;
11074 WARN_ON(!in_interrupt());
11079 spin_lock(&dev
->event_lock
);
11080 work
= intel_crtc
->unpin_work
;
11081 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11082 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11083 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11084 page_flip_completed(intel_crtc
);
11087 if (work
!= NULL
&&
11088 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11089 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11090 spin_unlock(&dev
->event_lock
);
11093 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11094 struct drm_framebuffer
*fb
,
11095 struct drm_pending_vblank_event
*event
,
11096 uint32_t page_flip_flags
)
11098 struct drm_device
*dev
= crtc
->dev
;
11099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11100 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11101 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11102 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11103 struct drm_plane
*primary
= crtc
->primary
;
11104 enum pipe pipe
= intel_crtc
->pipe
;
11105 struct intel_unpin_work
*work
;
11106 struct intel_engine_cs
*ring
;
11111 * drm_mode_page_flip_ioctl() should already catch this, but double
11112 * check to be safe. In the future we may enable pageflipping from
11113 * a disabled primary plane.
11115 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11118 /* Can't change pixel format via MI display flips. */
11119 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11123 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11124 * Note that pitch changes could also affect these register.
11126 if (INTEL_INFO(dev
)->gen
> 3 &&
11127 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11128 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11131 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11134 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11138 work
->event
= event
;
11140 work
->old_fb
= old_fb
;
11141 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11143 ret
= drm_crtc_vblank_get(crtc
);
11147 /* We borrow the event spin lock for protecting unpin_work */
11148 spin_lock_irq(&dev
->event_lock
);
11149 if (intel_crtc
->unpin_work
) {
11150 /* Before declaring the flip queue wedged, check if
11151 * the hardware completed the operation behind our backs.
11153 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11154 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11155 page_flip_completed(intel_crtc
);
11157 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11158 spin_unlock_irq(&dev
->event_lock
);
11160 drm_crtc_vblank_put(crtc
);
11165 intel_crtc
->unpin_work
= work
;
11166 spin_unlock_irq(&dev
->event_lock
);
11168 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11169 flush_workqueue(dev_priv
->wq
);
11171 /* Reference the objects for the scheduled work. */
11172 drm_framebuffer_reference(work
->old_fb
);
11173 drm_gem_object_reference(&obj
->base
);
11175 crtc
->primary
->fb
= fb
;
11176 update_state_fb(crtc
->primary
);
11178 work
->pending_flip_obj
= obj
;
11180 ret
= i915_mutex_lock_interruptible(dev
);
11184 atomic_inc(&intel_crtc
->unpin_work_count
);
11185 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11187 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11188 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
11190 if (IS_VALLEYVIEW(dev
)) {
11191 ring
= &dev_priv
->ring
[BCS
];
11192 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11193 /* vlv: DISPLAY_FLIP fails to change tiling */
11195 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11196 ring
= &dev_priv
->ring
[BCS
];
11197 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11198 ring
= i915_gem_request_get_ring(obj
->last_write_req
);
11199 if (ring
== NULL
|| ring
->id
!= RCS
)
11200 ring
= &dev_priv
->ring
[BCS
];
11202 ring
= &dev_priv
->ring
[RCS
];
11205 mmio_flip
= use_mmio_flip(ring
, obj
);
11207 /* When using CS flips, we want to emit semaphores between rings.
11208 * However, when using mmio flips we will create a task to do the
11209 * synchronisation, so all we want here is to pin the framebuffer
11210 * into the display plane and skip any waits.
11212 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11213 crtc
->primary
->state
,
11214 mmio_flip
? i915_gem_request_get_ring(obj
->last_write_req
) : ring
);
11216 goto cleanup_pending
;
11218 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
11219 + intel_crtc
->dspaddr_offset
;
11222 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11225 goto cleanup_unpin
;
11227 i915_gem_request_assign(&work
->flip_queued_req
,
11228 obj
->last_write_req
);
11230 if (obj
->last_write_req
) {
11231 ret
= i915_gem_check_olr(obj
->last_write_req
);
11233 goto cleanup_unpin
;
11236 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
11239 goto cleanup_unpin
;
11241 i915_gem_request_assign(&work
->flip_queued_req
,
11242 intel_ring_get_request(ring
));
11245 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11246 work
->enable_stall_check
= true;
11248 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11249 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11251 intel_fbc_disable(dev
);
11252 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11253 mutex_unlock(&dev
->struct_mutex
);
11255 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11260 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11262 atomic_dec(&intel_crtc
->unpin_work_count
);
11263 mutex_unlock(&dev
->struct_mutex
);
11265 crtc
->primary
->fb
= old_fb
;
11266 update_state_fb(crtc
->primary
);
11268 drm_gem_object_unreference_unlocked(&obj
->base
);
11269 drm_framebuffer_unreference(work
->old_fb
);
11271 spin_lock_irq(&dev
->event_lock
);
11272 intel_crtc
->unpin_work
= NULL
;
11273 spin_unlock_irq(&dev
->event_lock
);
11275 drm_crtc_vblank_put(crtc
);
11281 ret
= intel_plane_restore(primary
);
11282 if (ret
== 0 && event
) {
11283 spin_lock_irq(&dev
->event_lock
);
11284 drm_send_vblank_event(dev
, pipe
, event
);
11285 spin_unlock_irq(&dev
->event_lock
);
11291 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11292 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11293 .load_lut
= intel_crtc_load_lut
,
11294 .atomic_begin
= intel_begin_crtc_commit
,
11295 .atomic_flush
= intel_finish_crtc_commit
,
11299 * intel_modeset_update_staged_output_state
11301 * Updates the staged output configuration state, e.g. after we've read out the
11302 * current hw state.
11304 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11306 struct intel_crtc
*crtc
;
11307 struct intel_encoder
*encoder
;
11308 struct intel_connector
*connector
;
11310 for_each_intel_connector(dev
, connector
) {
11311 connector
->new_encoder
=
11312 to_intel_encoder(connector
->base
.encoder
);
11315 for_each_intel_encoder(dev
, encoder
) {
11316 encoder
->new_crtc
=
11317 to_intel_crtc(encoder
->base
.crtc
);
11320 for_each_intel_crtc(dev
, crtc
) {
11321 crtc
->new_enabled
= crtc
->base
.state
->enable
;
11325 /* Transitional helper to copy current connector/encoder state to
11326 * connector->state. This is needed so that code that is partially
11327 * converted to atomic does the right thing.
11329 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11331 struct intel_connector
*connector
;
11333 for_each_intel_connector(dev
, connector
) {
11334 if (connector
->base
.encoder
) {
11335 connector
->base
.state
->best_encoder
=
11336 connector
->base
.encoder
;
11337 connector
->base
.state
->crtc
=
11338 connector
->base
.encoder
->crtc
;
11340 connector
->base
.state
->best_encoder
= NULL
;
11341 connector
->base
.state
->crtc
= NULL
;
11346 /* Fixup legacy state after an atomic state swap.
11348 static void intel_modeset_fixup_state(struct drm_atomic_state
*state
)
11350 struct intel_crtc
*crtc
;
11351 struct intel_encoder
*encoder
;
11352 struct intel_connector
*connector
;
11354 for_each_intel_connector(state
->dev
, connector
) {
11355 connector
->base
.encoder
= connector
->base
.state
->best_encoder
;
11356 if (connector
->base
.encoder
)
11357 connector
->base
.encoder
->crtc
=
11358 connector
->base
.state
->crtc
;
11361 /* Update crtc of disabled encoders */
11362 for_each_intel_encoder(state
->dev
, encoder
) {
11363 int num_connectors
= 0;
11365 for_each_intel_connector(state
->dev
, connector
)
11366 if (connector
->base
.encoder
== &encoder
->base
)
11369 if (num_connectors
== 0)
11370 encoder
->base
.crtc
= NULL
;
11373 for_each_intel_crtc(state
->dev
, crtc
) {
11374 crtc
->base
.enabled
= crtc
->base
.state
->enable
;
11375 crtc
->config
= to_intel_crtc_state(crtc
->base
.state
);
11378 /* Copy the new configuration to the staged state, to keep the few
11379 * pieces of code that haven't been converted yet happy */
11380 intel_modeset_update_staged_output_state(state
->dev
);
11384 connected_sink_compute_bpp(struct intel_connector
*connector
,
11385 struct intel_crtc_state
*pipe_config
)
11387 int bpp
= pipe_config
->pipe_bpp
;
11389 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11390 connector
->base
.base
.id
,
11391 connector
->base
.name
);
11393 /* Don't use an invalid EDID bpc value */
11394 if (connector
->base
.display_info
.bpc
&&
11395 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11396 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11397 bpp
, connector
->base
.display_info
.bpc
*3);
11398 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11401 /* Clamp bpp to 8 on screens without EDID 1.4 */
11402 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11403 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11405 pipe_config
->pipe_bpp
= 24;
11410 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11411 struct intel_crtc_state
*pipe_config
)
11413 struct drm_device
*dev
= crtc
->base
.dev
;
11414 struct drm_atomic_state
*state
;
11415 struct drm_connector
*connector
;
11416 struct drm_connector_state
*connector_state
;
11419 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11421 else if (INTEL_INFO(dev
)->gen
>= 5)
11427 pipe_config
->pipe_bpp
= bpp
;
11429 state
= pipe_config
->base
.state
;
11431 /* Clamp display bpp to EDID value */
11432 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11433 if (connector_state
->crtc
!= &crtc
->base
)
11436 connected_sink_compute_bpp(to_intel_connector(connector
),
11443 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11445 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11446 "type: 0x%x flags: 0x%x\n",
11448 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11449 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11450 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11451 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11454 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11455 struct intel_crtc_state
*pipe_config
,
11456 const char *context
)
11458 struct drm_device
*dev
= crtc
->base
.dev
;
11459 struct drm_plane
*plane
;
11460 struct intel_plane
*intel_plane
;
11461 struct intel_plane_state
*state
;
11462 struct drm_framebuffer
*fb
;
11464 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11465 context
, pipe_config
, pipe_name(crtc
->pipe
));
11467 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11468 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11469 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11470 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11471 pipe_config
->has_pch_encoder
,
11472 pipe_config
->fdi_lanes
,
11473 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11474 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11475 pipe_config
->fdi_m_n
.tu
);
11476 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11477 pipe_config
->has_dp_encoder
,
11478 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11479 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11480 pipe_config
->dp_m_n
.tu
);
11482 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11483 pipe_config
->has_dp_encoder
,
11484 pipe_config
->dp_m2_n2
.gmch_m
,
11485 pipe_config
->dp_m2_n2
.gmch_n
,
11486 pipe_config
->dp_m2_n2
.link_m
,
11487 pipe_config
->dp_m2_n2
.link_n
,
11488 pipe_config
->dp_m2_n2
.tu
);
11490 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11491 pipe_config
->has_audio
,
11492 pipe_config
->has_infoframe
);
11494 DRM_DEBUG_KMS("requested mode:\n");
11495 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11496 DRM_DEBUG_KMS("adjusted mode:\n");
11497 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11498 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11499 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11500 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11501 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11502 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11504 pipe_config
->scaler_state
.scaler_users
,
11505 pipe_config
->scaler_state
.scaler_id
);
11506 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11507 pipe_config
->gmch_pfit
.control
,
11508 pipe_config
->gmch_pfit
.pgm_ratios
,
11509 pipe_config
->gmch_pfit
.lvds_border_bits
);
11510 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11511 pipe_config
->pch_pfit
.pos
,
11512 pipe_config
->pch_pfit
.size
,
11513 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11514 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11515 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11517 if (IS_BROXTON(dev
)) {
11518 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11519 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11520 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11521 pipe_config
->ddi_pll_sel
,
11522 pipe_config
->dpll_hw_state
.ebb0
,
11523 pipe_config
->dpll_hw_state
.pll0
,
11524 pipe_config
->dpll_hw_state
.pll1
,
11525 pipe_config
->dpll_hw_state
.pll2
,
11526 pipe_config
->dpll_hw_state
.pll3
,
11527 pipe_config
->dpll_hw_state
.pll6
,
11528 pipe_config
->dpll_hw_state
.pll8
,
11529 pipe_config
->dpll_hw_state
.pcsdw12
);
11530 } else if (IS_SKYLAKE(dev
)) {
11531 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11532 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11533 pipe_config
->ddi_pll_sel
,
11534 pipe_config
->dpll_hw_state
.ctrl1
,
11535 pipe_config
->dpll_hw_state
.cfgcr1
,
11536 pipe_config
->dpll_hw_state
.cfgcr2
);
11537 } else if (HAS_DDI(dev
)) {
11538 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11539 pipe_config
->ddi_pll_sel
,
11540 pipe_config
->dpll_hw_state
.wrpll
);
11542 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11543 "fp0: 0x%x, fp1: 0x%x\n",
11544 pipe_config
->dpll_hw_state
.dpll
,
11545 pipe_config
->dpll_hw_state
.dpll_md
,
11546 pipe_config
->dpll_hw_state
.fp0
,
11547 pipe_config
->dpll_hw_state
.fp1
);
11550 DRM_DEBUG_KMS("planes on this crtc\n");
11551 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11552 intel_plane
= to_intel_plane(plane
);
11553 if (intel_plane
->pipe
!= crtc
->pipe
)
11556 state
= to_intel_plane_state(plane
->state
);
11557 fb
= state
->base
.fb
;
11559 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11560 "disabled, scaler_id = %d\n",
11561 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11562 plane
->base
.id
, intel_plane
->pipe
,
11563 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
11564 drm_plane_index(plane
), state
->scaler_id
);
11568 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11569 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11570 plane
->base
.id
, intel_plane
->pipe
,
11571 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
11572 drm_plane_index(plane
));
11573 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11574 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
11575 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11577 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
11578 drm_rect_width(&state
->src
) >> 16,
11579 drm_rect_height(&state
->src
) >> 16,
11580 state
->dst
.x1
, state
->dst
.y1
,
11581 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
11585 static bool encoders_cloneable(const struct intel_encoder
*a
,
11586 const struct intel_encoder
*b
)
11588 /* masks could be asymmetric, so check both ways */
11589 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11590 b
->cloneable
& (1 << a
->type
));
11593 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11594 struct intel_crtc
*crtc
,
11595 struct intel_encoder
*encoder
)
11597 struct intel_encoder
*source_encoder
;
11598 struct drm_connector
*connector
;
11599 struct drm_connector_state
*connector_state
;
11602 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11603 if (connector_state
->crtc
!= &crtc
->base
)
11607 to_intel_encoder(connector_state
->best_encoder
);
11608 if (!encoders_cloneable(encoder
, source_encoder
))
11615 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11616 struct intel_crtc
*crtc
)
11618 struct intel_encoder
*encoder
;
11619 struct drm_connector
*connector
;
11620 struct drm_connector_state
*connector_state
;
11623 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11624 if (connector_state
->crtc
!= &crtc
->base
)
11627 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11628 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11635 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11637 struct drm_device
*dev
= state
->dev
;
11638 struct intel_encoder
*encoder
;
11639 struct drm_connector
*connector
;
11640 struct drm_connector_state
*connector_state
;
11641 unsigned int used_ports
= 0;
11645 * Walk the connector list instead of the encoder
11646 * list to detect the problem on ddi platforms
11647 * where there's just one encoder per digital port.
11649 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11650 if (!connector_state
->best_encoder
)
11653 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11655 WARN_ON(!connector_state
->crtc
);
11657 switch (encoder
->type
) {
11658 unsigned int port_mask
;
11659 case INTEL_OUTPUT_UNKNOWN
:
11660 if (WARN_ON(!HAS_DDI(dev
)))
11662 case INTEL_OUTPUT_DISPLAYPORT
:
11663 case INTEL_OUTPUT_HDMI
:
11664 case INTEL_OUTPUT_EDP
:
11665 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
11667 /* the same port mustn't appear more than once */
11668 if (used_ports
& port_mask
)
11671 used_ports
|= port_mask
;
11681 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11683 struct drm_crtc_state tmp_state
;
11684 struct intel_crtc_scaler_state scaler_state
;
11685 struct intel_dpll_hw_state dpll_hw_state
;
11686 enum intel_dpll_id shared_dpll
;
11687 uint32_t ddi_pll_sel
;
11689 /* FIXME: before the switch to atomic started, a new pipe_config was
11690 * kzalloc'd. Code that depends on any field being zero should be
11691 * fixed, so that the crtc_state can be safely duplicated. For now,
11692 * only fields that are know to not cause problems are preserved. */
11694 tmp_state
= crtc_state
->base
;
11695 scaler_state
= crtc_state
->scaler_state
;
11696 shared_dpll
= crtc_state
->shared_dpll
;
11697 dpll_hw_state
= crtc_state
->dpll_hw_state
;
11698 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
11700 memset(crtc_state
, 0, sizeof *crtc_state
);
11702 crtc_state
->base
= tmp_state
;
11703 crtc_state
->scaler_state
= scaler_state
;
11704 crtc_state
->shared_dpll
= shared_dpll
;
11705 crtc_state
->dpll_hw_state
= dpll_hw_state
;
11706 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
11710 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11711 struct drm_atomic_state
*state
,
11712 struct intel_crtc_state
*pipe_config
)
11714 struct intel_encoder
*encoder
;
11715 struct drm_connector
*connector
;
11716 struct drm_connector_state
*connector_state
;
11717 int base_bpp
, ret
= -EINVAL
;
11721 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
11722 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11726 if (!check_digital_port_conflicts(state
)) {
11727 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11731 clear_intel_crtc_state(pipe_config
);
11733 pipe_config
->cpu_transcoder
=
11734 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11737 * Sanitize sync polarity flags based on requested ones. If neither
11738 * positive or negative polarity is requested, treat this as meaning
11739 * negative polarity.
11741 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11742 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11743 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11745 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11746 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11747 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11749 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11750 * plane pixel format and any sink constraints into account. Returns the
11751 * source plane bpp so that dithering can be selected on mismatches
11752 * after encoders and crtc also have had their say. */
11753 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11759 * Determine the real pipe dimensions. Note that stereo modes can
11760 * increase the actual pipe size due to the frame doubling and
11761 * insertion of additional space for blanks between the frame. This
11762 * is stored in the crtc timings. We use the requested mode to do this
11763 * computation to clearly distinguish it from the adjusted mode, which
11764 * can be changed by the connectors in the below retry loop.
11766 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
11767 &pipe_config
->pipe_src_w
,
11768 &pipe_config
->pipe_src_h
);
11771 /* Ensure the port clock defaults are reset when retrying. */
11772 pipe_config
->port_clock
= 0;
11773 pipe_config
->pixel_multiplier
= 1;
11775 /* Fill in default crtc timings, allow encoders to overwrite them. */
11776 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11777 CRTC_STEREO_DOUBLE
);
11779 /* Pass our mode to the connectors and the CRTC to give them a chance to
11780 * adjust it according to limitations or connector properties, and also
11781 * a chance to reject the mode entirely.
11783 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11784 if (connector_state
->crtc
!= crtc
)
11787 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11789 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
11790 DRM_DEBUG_KMS("Encoder config failure\n");
11795 /* Set default port clock if not overwritten by the encoder. Needs to be
11796 * done afterwards in case the encoder adjusts the mode. */
11797 if (!pipe_config
->port_clock
)
11798 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11799 * pipe_config
->pixel_multiplier
;
11801 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11803 DRM_DEBUG_KMS("CRTC fixup failed\n");
11807 if (ret
== RETRY
) {
11808 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
11813 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11815 goto encoder_retry
;
11818 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
11819 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11820 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11827 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
11829 struct drm_encoder
*encoder
;
11830 struct drm_device
*dev
= crtc
->dev
;
11832 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
11833 if (encoder
->crtc
== crtc
)
11840 needs_modeset(struct drm_crtc_state
*state
)
11842 return state
->mode_changed
|| state
->active_changed
;
11846 intel_modeset_update_state(struct drm_atomic_state
*state
)
11848 struct drm_device
*dev
= state
->dev
;
11849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11850 struct intel_encoder
*intel_encoder
;
11851 struct drm_crtc
*crtc
;
11852 struct drm_crtc_state
*crtc_state
;
11853 struct drm_connector
*connector
;
11856 intel_shared_dpll_commit(dev_priv
);
11858 for_each_intel_encoder(dev
, intel_encoder
) {
11859 if (!intel_encoder
->base
.crtc
)
11862 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11863 if (crtc
== intel_encoder
->base
.crtc
)
11866 if (crtc
!= intel_encoder
->base
.crtc
)
11869 if (crtc_state
->enable
&& needs_modeset(crtc_state
))
11870 intel_encoder
->connectors_active
= false;
11873 drm_atomic_helper_swap_state(state
->dev
, state
);
11874 intel_modeset_fixup_state(state
);
11876 /* Double check state. */
11877 for_each_crtc(dev
, crtc
) {
11878 WARN_ON(crtc
->state
->enable
!= intel_crtc_in_use(crtc
));
11881 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11882 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
11885 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11886 if (crtc
== connector
->encoder
->crtc
)
11889 if (crtc
!= connector
->encoder
->crtc
)
11892 if (crtc
->state
->enable
&& needs_modeset(crtc
->state
)) {
11893 struct drm_property
*dpms_property
=
11894 dev
->mode_config
.dpms_property
;
11896 connector
->dpms
= DRM_MODE_DPMS_ON
;
11897 drm_object_property_set_value(&connector
->base
,
11901 intel_encoder
= to_intel_encoder(connector
->encoder
);
11902 intel_encoder
->connectors_active
= true;
11908 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11912 if (clock1
== clock2
)
11915 if (!clock1
|| !clock2
)
11918 diff
= abs(clock1
- clock2
);
11920 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11926 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11927 list_for_each_entry((intel_crtc), \
11928 &(dev)->mode_config.crtc_list, \
11930 if (mask & (1 <<(intel_crtc)->pipe))
11933 intel_pipe_config_compare(struct drm_device
*dev
,
11934 struct intel_crtc_state
*current_config
,
11935 struct intel_crtc_state
*pipe_config
)
11937 #define PIPE_CONF_CHECK_X(name) \
11938 if (current_config->name != pipe_config->name) { \
11939 DRM_ERROR("mismatch in " #name " " \
11940 "(expected 0x%08x, found 0x%08x)\n", \
11941 current_config->name, \
11942 pipe_config->name); \
11946 #define PIPE_CONF_CHECK_I(name) \
11947 if (current_config->name != pipe_config->name) { \
11948 DRM_ERROR("mismatch in " #name " " \
11949 "(expected %i, found %i)\n", \
11950 current_config->name, \
11951 pipe_config->name); \
11955 /* This is required for BDW+ where there is only one set of registers for
11956 * switching between high and low RR.
11957 * This macro can be used whenever a comparison has to be made between one
11958 * hw state and multiple sw state variables.
11960 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11961 if ((current_config->name != pipe_config->name) && \
11962 (current_config->alt_name != pipe_config->name)) { \
11963 DRM_ERROR("mismatch in " #name " " \
11964 "(expected %i or %i, found %i)\n", \
11965 current_config->name, \
11966 current_config->alt_name, \
11967 pipe_config->name); \
11971 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11972 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11973 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11974 "(expected %i, found %i)\n", \
11975 current_config->name & (mask), \
11976 pipe_config->name & (mask)); \
11980 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11981 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11982 DRM_ERROR("mismatch in " #name " " \
11983 "(expected %i, found %i)\n", \
11984 current_config->name, \
11985 pipe_config->name); \
11989 #define PIPE_CONF_QUIRK(quirk) \
11990 ((current_config->quirks | pipe_config->quirks) & (quirk))
11992 PIPE_CONF_CHECK_I(cpu_transcoder
);
11994 PIPE_CONF_CHECK_I(has_pch_encoder
);
11995 PIPE_CONF_CHECK_I(fdi_lanes
);
11996 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11997 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11998 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11999 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
12000 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
12002 PIPE_CONF_CHECK_I(has_dp_encoder
);
12004 if (INTEL_INFO(dev
)->gen
< 8) {
12005 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
12006 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
12007 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
12008 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
12009 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
12011 if (current_config
->has_drrs
) {
12012 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
12013 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
12014 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
12015 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
12016 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
12019 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
12020 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
12021 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
12022 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
12023 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
12026 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12027 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12028 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12029 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12030 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12031 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12033 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12034 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12035 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12036 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12037 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12038 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12040 PIPE_CONF_CHECK_I(pixel_multiplier
);
12041 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12042 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12043 IS_VALLEYVIEW(dev
))
12044 PIPE_CONF_CHECK_I(limited_color_range
);
12045 PIPE_CONF_CHECK_I(has_infoframe
);
12047 PIPE_CONF_CHECK_I(has_audio
);
12049 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12050 DRM_MODE_FLAG_INTERLACE
);
12052 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12053 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12054 DRM_MODE_FLAG_PHSYNC
);
12055 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12056 DRM_MODE_FLAG_NHSYNC
);
12057 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12058 DRM_MODE_FLAG_PVSYNC
);
12059 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12060 DRM_MODE_FLAG_NVSYNC
);
12063 PIPE_CONF_CHECK_I(pipe_src_w
);
12064 PIPE_CONF_CHECK_I(pipe_src_h
);
12067 * FIXME: BIOS likes to set up a cloned config with lvds+external
12068 * screen. Since we don't yet re-compute the pipe config when moving
12069 * just the lvds port away to another pipe the sw tracking won't match.
12071 * Proper atomic modesets with recomputed global state will fix this.
12072 * Until then just don't check gmch state for inherited modes.
12074 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
12075 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
12076 /* pfit ratios are autocomputed by the hw on gen4+ */
12077 if (INTEL_INFO(dev
)->gen
< 4)
12078 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
12079 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
12082 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12083 if (current_config
->pch_pfit
.enabled
) {
12084 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
12085 PIPE_CONF_CHECK_I(pch_pfit
.size
);
12088 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12090 /* BDW+ don't expose a synchronous way to read the state */
12091 if (IS_HASWELL(dev
))
12092 PIPE_CONF_CHECK_I(ips_enabled
);
12094 PIPE_CONF_CHECK_I(double_wide
);
12096 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12098 PIPE_CONF_CHECK_I(shared_dpll
);
12099 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12100 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12101 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12102 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12103 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12104 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12105 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12106 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12108 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12109 PIPE_CONF_CHECK_I(pipe_bpp
);
12111 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12112 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12114 #undef PIPE_CONF_CHECK_X
12115 #undef PIPE_CONF_CHECK_I
12116 #undef PIPE_CONF_CHECK_I_ALT
12117 #undef PIPE_CONF_CHECK_FLAGS
12118 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12119 #undef PIPE_CONF_QUIRK
12124 static void check_wm_state(struct drm_device
*dev
)
12126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12127 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12128 struct intel_crtc
*intel_crtc
;
12131 if (INTEL_INFO(dev
)->gen
< 9)
12134 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12135 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12137 for_each_intel_crtc(dev
, intel_crtc
) {
12138 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12139 const enum pipe pipe
= intel_crtc
->pipe
;
12141 if (!intel_crtc
->active
)
12145 for_each_plane(dev_priv
, pipe
, plane
) {
12146 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12147 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12149 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12152 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12153 "(expected (%u,%u), found (%u,%u))\n",
12154 pipe_name(pipe
), plane
+ 1,
12155 sw_entry
->start
, sw_entry
->end
,
12156 hw_entry
->start
, hw_entry
->end
);
12160 hw_entry
= &hw_ddb
.cursor
[pipe
];
12161 sw_entry
= &sw_ddb
->cursor
[pipe
];
12163 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12166 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12167 "(expected (%u,%u), found (%u,%u))\n",
12169 sw_entry
->start
, sw_entry
->end
,
12170 hw_entry
->start
, hw_entry
->end
);
12175 check_connector_state(struct drm_device
*dev
)
12177 struct intel_connector
*connector
;
12179 for_each_intel_connector(dev
, connector
) {
12180 /* This also checks the encoder/connector hw state with the
12181 * ->get_hw_state callbacks. */
12182 intel_connector_check_state(connector
);
12184 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
12185 "connector's staged encoder doesn't match current encoder\n");
12190 check_encoder_state(struct drm_device
*dev
)
12192 struct intel_encoder
*encoder
;
12193 struct intel_connector
*connector
;
12195 for_each_intel_encoder(dev
, encoder
) {
12196 bool enabled
= false;
12197 bool active
= false;
12198 enum pipe pipe
, tracked_pipe
;
12200 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12201 encoder
->base
.base
.id
,
12202 encoder
->base
.name
);
12204 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
12205 "encoder's stage crtc doesn't match current crtc\n");
12206 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
12207 "encoder's active_connectors set, but no crtc\n");
12209 for_each_intel_connector(dev
, connector
) {
12210 if (connector
->base
.encoder
!= &encoder
->base
)
12213 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
12217 * for MST connectors if we unplug the connector is gone
12218 * away but the encoder is still connected to a crtc
12219 * until a modeset happens in response to the hotplug.
12221 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
12224 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12225 "encoder's enabled state mismatch "
12226 "(expected %i, found %i)\n",
12227 !!encoder
->base
.crtc
, enabled
);
12228 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
12229 "active encoder with no crtc\n");
12231 I915_STATE_WARN(encoder
->connectors_active
!= active
,
12232 "encoder's computed active state doesn't match tracked active state "
12233 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
12235 active
= encoder
->get_hw_state(encoder
, &pipe
);
12236 I915_STATE_WARN(active
!= encoder
->connectors_active
,
12237 "encoder's hw state doesn't match sw tracking "
12238 "(expected %i, found %i)\n",
12239 encoder
->connectors_active
, active
);
12241 if (!encoder
->base
.crtc
)
12244 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
12245 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
12246 "active encoder's pipe doesn't match"
12247 "(expected %i, found %i)\n",
12248 tracked_pipe
, pipe
);
12254 check_crtc_state(struct drm_device
*dev
)
12256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12257 struct intel_crtc
*crtc
;
12258 struct intel_encoder
*encoder
;
12259 struct intel_crtc_state pipe_config
;
12261 for_each_intel_crtc(dev
, crtc
) {
12262 bool enabled
= false;
12263 bool active
= false;
12265 memset(&pipe_config
, 0, sizeof(pipe_config
));
12267 DRM_DEBUG_KMS("[CRTC:%d]\n",
12268 crtc
->base
.base
.id
);
12270 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
12271 "active crtc, but not enabled in sw tracking\n");
12273 for_each_intel_encoder(dev
, encoder
) {
12274 if (encoder
->base
.crtc
!= &crtc
->base
)
12277 if (encoder
->connectors_active
)
12281 I915_STATE_WARN(active
!= crtc
->active
,
12282 "crtc's computed active state doesn't match tracked active state "
12283 "(expected %i, found %i)\n", active
, crtc
->active
);
12284 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
12285 "crtc's computed enabled state doesn't match tracked enabled state "
12286 "(expected %i, found %i)\n", enabled
,
12287 crtc
->base
.state
->enable
);
12289 active
= dev_priv
->display
.get_pipe_config(crtc
,
12292 /* hw state is inconsistent with the pipe quirk */
12293 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12294 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12295 active
= crtc
->active
;
12297 for_each_intel_encoder(dev
, encoder
) {
12299 if (encoder
->base
.crtc
!= &crtc
->base
)
12301 if (encoder
->get_hw_state(encoder
, &pipe
))
12302 encoder
->get_config(encoder
, &pipe_config
);
12305 I915_STATE_WARN(crtc
->active
!= active
,
12306 "crtc active state doesn't match with hw state "
12307 "(expected %i, found %i)\n", crtc
->active
, active
);
12310 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12311 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12312 intel_dump_pipe_config(crtc
, &pipe_config
,
12314 intel_dump_pipe_config(crtc
, crtc
->config
,
12321 check_shared_dpll_state(struct drm_device
*dev
)
12323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12324 struct intel_crtc
*crtc
;
12325 struct intel_dpll_hw_state dpll_hw_state
;
12328 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12329 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12330 int enabled_crtcs
= 0, active_crtcs
= 0;
12333 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12335 DRM_DEBUG_KMS("%s\n", pll
->name
);
12337 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12339 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12340 "more active pll users than references: %i vs %i\n",
12341 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12342 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12343 "pll in active use but not on in sw tracking\n");
12344 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12345 "pll in on but not on in use in sw tracking\n");
12346 I915_STATE_WARN(pll
->on
!= active
,
12347 "pll on state mismatch (expected %i, found %i)\n",
12350 for_each_intel_crtc(dev
, crtc
) {
12351 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12353 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12356 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12357 "pll active crtcs mismatch (expected %i, found %i)\n",
12358 pll
->active
, active_crtcs
);
12359 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12360 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12361 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12363 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12364 sizeof(dpll_hw_state
)),
12365 "pll hw state mismatch\n");
12370 intel_modeset_check_state(struct drm_device
*dev
)
12372 check_wm_state(dev
);
12373 check_connector_state(dev
);
12374 check_encoder_state(dev
);
12375 check_crtc_state(dev
);
12376 check_shared_dpll_state(dev
);
12379 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12383 * FDI already provided one idea for the dotclock.
12384 * Yell if the encoder disagrees.
12386 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12387 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12388 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12391 static void update_scanline_offset(struct intel_crtc
*crtc
)
12393 struct drm_device
*dev
= crtc
->base
.dev
;
12396 * The scanline counter increments at the leading edge of hsync.
12398 * On most platforms it starts counting from vtotal-1 on the
12399 * first active line. That means the scanline counter value is
12400 * always one less than what we would expect. Ie. just after
12401 * start of vblank, which also occurs at start of hsync (on the
12402 * last active line), the scanline counter will read vblank_start-1.
12404 * On gen2 the scanline counter starts counting from 1 instead
12405 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12406 * to keep the value positive), instead of adding one.
12408 * On HSW+ the behaviour of the scanline counter depends on the output
12409 * type. For DP ports it behaves like most other platforms, but on HDMI
12410 * there's an extra 1 line difference. So we need to add two instead of
12411 * one to the value.
12413 if (IS_GEN2(dev
)) {
12414 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12417 vtotal
= mode
->crtc_vtotal
;
12418 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12421 crtc
->scanline_offset
= vtotal
- 1;
12422 } else if (HAS_DDI(dev
) &&
12423 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12424 crtc
->scanline_offset
= 2;
12426 crtc
->scanline_offset
= 1;
12429 static struct intel_crtc_state
*
12430 intel_modeset_compute_config(struct drm_crtc
*crtc
,
12431 struct drm_atomic_state
*state
)
12433 struct intel_crtc_state
*pipe_config
;
12436 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12438 return ERR_PTR(ret
);
12440 ret
= drm_atomic_helper_check_modeset(state
->dev
, state
);
12442 return ERR_PTR(ret
);
12445 * Note this needs changes when we start tracking multiple modes
12446 * and crtcs. At that point we'll need to compute the whole config
12447 * (i.e. one pipe_config for each crtc) rather than just the one
12450 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
12451 if (IS_ERR(pipe_config
))
12452 return pipe_config
;
12454 if (!pipe_config
->base
.enable
)
12455 return pipe_config
;
12457 ret
= intel_modeset_pipe_config(crtc
, state
, pipe_config
);
12459 return ERR_PTR(ret
);
12461 /* Check things that can only be changed through modeset */
12462 if (pipe_config
->has_audio
!=
12463 to_intel_crtc(crtc
)->config
->has_audio
)
12464 pipe_config
->base
.mode_changed
= true;
12467 * Note we have an issue here with infoframes: current code
12468 * only updates them on the full mode set path per hw
12469 * requirements. So here we should be checking for any
12470 * required changes and forcing a mode set.
12473 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,"[modeset]");
12475 ret
= drm_atomic_helper_check_planes(state
->dev
, state
);
12477 return ERR_PTR(ret
);
12479 return pipe_config
;
12482 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
)
12484 struct drm_device
*dev
= state
->dev
;
12485 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12486 unsigned clear_pipes
= 0;
12487 struct intel_crtc
*intel_crtc
;
12488 struct intel_crtc_state
*intel_crtc_state
;
12489 struct drm_crtc
*crtc
;
12490 struct drm_crtc_state
*crtc_state
;
12494 if (!dev_priv
->display
.crtc_compute_clock
)
12497 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12498 intel_crtc
= to_intel_crtc(crtc
);
12499 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12501 if (needs_modeset(crtc_state
)) {
12502 clear_pipes
|= 1 << intel_crtc
->pipe
;
12503 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12507 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
12511 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12512 if (!needs_modeset(crtc_state
) || !crtc_state
->enable
)
12515 intel_crtc
= to_intel_crtc(crtc
);
12516 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12518 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12521 intel_shared_dpll_abort_config(dev_priv
);
12530 /* Code that should eventually be part of atomic_check() */
12531 static int __intel_set_mode_checks(struct drm_atomic_state
*state
)
12533 struct drm_device
*dev
= state
->dev
;
12537 * See if the config requires any additional preparation, e.g.
12538 * to adjust global state with pipes off. We need to do this
12539 * here so we can get the modeset_pipe updated config for the new
12540 * mode set on this crtc. For other crtcs we need to use the
12541 * adjusted_mode bits in the crtc directly.
12543 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
12544 ret
= valleyview_modeset_global_pipes(state
);
12549 ret
= __intel_set_mode_setup_plls(state
);
12556 static int __intel_set_mode(struct drm_crtc
*modeset_crtc
,
12557 struct intel_crtc_state
*pipe_config
)
12559 struct drm_device
*dev
= modeset_crtc
->dev
;
12560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12561 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12562 struct drm_crtc
*crtc
;
12563 struct drm_crtc_state
*crtc_state
;
12567 ret
= __intel_set_mode_checks(state
);
12571 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
12575 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12576 if (!needs_modeset(crtc_state
))
12579 if (!crtc_state
->enable
) {
12580 intel_crtc_disable(crtc
);
12581 } else if (crtc
->state
->enable
) {
12582 intel_crtc_disable_planes(crtc
);
12583 dev_priv
->display
.crtc_disable(crtc
);
12587 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12588 * to set it here already despite that we pass it down the callchain.
12590 * Note we'll need to fix this up when we start tracking multiple
12591 * pipes; here we assume a single modeset_pipe and only track the
12592 * single crtc and mode.
12594 if (pipe_config
->base
.enable
&& needs_modeset(&pipe_config
->base
)) {
12595 modeset_crtc
->mode
= pipe_config
->base
.mode
;
12598 * Calculate and store various constants which
12599 * are later needed by vblank and swap-completion
12600 * timestamping. They are derived from true hwmode.
12602 drm_calc_timestamping_constants(modeset_crtc
,
12603 &pipe_config
->base
.adjusted_mode
);
12606 /* Only after disabling all output pipelines that will be changed can we
12607 * update the the output configuration. */
12608 intel_modeset_update_state(state
);
12610 /* The state has been swaped above, so state actually contains the
12611 * old state now. */
12613 modeset_update_crtc_power_domains(state
);
12615 drm_atomic_helper_commit_planes(dev
, state
);
12617 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12618 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12619 if (!needs_modeset(crtc
->state
) || !crtc
->state
->enable
)
12622 update_scanline_offset(to_intel_crtc(crtc
));
12624 dev_priv
->display
.crtc_enable(crtc
);
12625 intel_crtc_enable_planes(crtc
);
12628 /* FIXME: add subpixel order */
12630 drm_atomic_helper_cleanup_planes(dev
, state
);
12632 drm_atomic_state_free(state
);
12637 static int intel_set_mode_with_config(struct drm_crtc
*crtc
,
12638 struct intel_crtc_state
*pipe_config
)
12642 ret
= __intel_set_mode(crtc
, pipe_config
);
12645 intel_modeset_check_state(crtc
->dev
);
12650 static int intel_set_mode(struct drm_crtc
*crtc
,
12651 struct drm_atomic_state
*state
)
12653 struct intel_crtc_state
*pipe_config
;
12656 pipe_config
= intel_modeset_compute_config(crtc
, state
);
12657 if (IS_ERR(pipe_config
)) {
12658 ret
= PTR_ERR(pipe_config
);
12662 ret
= intel_set_mode_with_config(crtc
, pipe_config
);
12670 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
12672 struct drm_device
*dev
= crtc
->dev
;
12673 struct drm_atomic_state
*state
;
12674 struct intel_crtc
*intel_crtc
;
12675 struct intel_encoder
*encoder
;
12676 struct intel_connector
*connector
;
12677 struct drm_connector_state
*connector_state
;
12678 struct intel_crtc_state
*crtc_state
;
12681 state
= drm_atomic_state_alloc(dev
);
12683 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12688 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12690 /* The force restore path in the HW readout code relies on the staged
12691 * config still keeping the user requested config while the actual
12692 * state has been overwritten by the configuration read from HW. We
12693 * need to copy the staged config to the atomic state, otherwise the
12694 * mode set will just reapply the state the HW is already in. */
12695 for_each_intel_encoder(dev
, encoder
) {
12696 if (&encoder
->new_crtc
->base
!= crtc
)
12699 for_each_intel_connector(dev
, connector
) {
12700 if (connector
->new_encoder
!= encoder
)
12703 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
12704 if (IS_ERR(connector_state
)) {
12705 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12706 connector
->base
.base
.id
,
12707 connector
->base
.name
,
12708 PTR_ERR(connector_state
));
12712 connector_state
->crtc
= crtc
;
12713 connector_state
->best_encoder
= &encoder
->base
;
12717 for_each_intel_crtc(dev
, intel_crtc
) {
12718 if (intel_crtc
->new_enabled
== intel_crtc
->base
.enabled
)
12721 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12722 if (IS_ERR(crtc_state
)) {
12723 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12724 intel_crtc
->base
.base
.id
,
12725 PTR_ERR(crtc_state
));
12729 crtc_state
->base
.active
= crtc_state
->base
.enable
=
12730 intel_crtc
->new_enabled
;
12732 if (&intel_crtc
->base
== crtc
)
12733 drm_mode_copy(&crtc_state
->base
.mode
, &crtc
->mode
);
12736 intel_modeset_setup_plane_state(state
, crtc
, &crtc
->mode
,
12737 crtc
->primary
->fb
, crtc
->x
, crtc
->y
);
12739 ret
= intel_set_mode(crtc
, state
);
12741 drm_atomic_state_free(state
);
12744 #undef for_each_intel_crtc_masked
12746 static bool intel_connector_in_mode_set(struct intel_connector
*connector
,
12747 struct drm_mode_set
*set
)
12751 for (ro
= 0; ro
< set
->num_connectors
; ro
++)
12752 if (set
->connectors
[ro
] == &connector
->base
)
12759 intel_modeset_stage_output_state(struct drm_device
*dev
,
12760 struct drm_mode_set
*set
,
12761 struct drm_atomic_state
*state
)
12763 struct intel_connector
*connector
;
12764 struct drm_connector
*drm_connector
;
12765 struct drm_connector_state
*connector_state
;
12766 struct drm_crtc
*crtc
;
12767 struct drm_crtc_state
*crtc_state
;
12770 /* The upper layers ensure that we either disable a crtc or have a list
12771 * of connectors. For paranoia, double-check this. */
12772 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
12773 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
12775 for_each_intel_connector(dev
, connector
) {
12776 bool in_mode_set
= intel_connector_in_mode_set(connector
, set
);
12778 if (!in_mode_set
&& connector
->base
.state
->crtc
!= set
->crtc
)
12782 drm_atomic_get_connector_state(state
, &connector
->base
);
12783 if (IS_ERR(connector_state
))
12784 return PTR_ERR(connector_state
);
12787 int pipe
= to_intel_crtc(set
->crtc
)->pipe
;
12788 connector_state
->best_encoder
=
12789 &intel_find_encoder(connector
, pipe
)->base
;
12792 if (connector
->base
.state
->crtc
!= set
->crtc
)
12795 /* If we disable the crtc, disable all its connectors. Also, if
12796 * the connector is on the changing crtc but not on the new
12797 * connector list, disable it. */
12798 if (!set
->fb
|| !in_mode_set
) {
12799 connector_state
->best_encoder
= NULL
;
12801 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12802 connector
->base
.base
.id
,
12803 connector
->base
.name
);
12806 /* connector->new_encoder is now updated for all connectors. */
12808 for_each_connector_in_state(state
, drm_connector
, connector_state
, i
) {
12809 connector
= to_intel_connector(drm_connector
);
12811 if (!connector_state
->best_encoder
) {
12812 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
12820 if (intel_connector_in_mode_set(connector
, set
)) {
12821 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
12823 /* If this connector was in a previous crtc, add it
12824 * to the state. We might need to disable it. */
12827 drm_atomic_get_crtc_state(state
, crtc
);
12828 if (IS_ERR(crtc_state
))
12829 return PTR_ERR(crtc_state
);
12832 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
12838 /* Make sure the new CRTC will work with the encoder */
12839 if (!drm_encoder_crtc_ok(connector_state
->best_encoder
,
12840 connector_state
->crtc
)) {
12844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12845 connector
->base
.base
.id
,
12846 connector
->base
.name
,
12847 connector_state
->crtc
->base
.id
);
12849 if (connector_state
->best_encoder
!= &connector
->encoder
->base
)
12850 connector
->encoder
=
12851 to_intel_encoder(connector_state
->best_encoder
);
12854 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12855 bool has_connectors
;
12857 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12861 has_connectors
= !!drm_atomic_connectors_for_crtc(state
, crtc
);
12862 if (has_connectors
!= crtc_state
->enable
)
12863 crtc_state
->enable
=
12864 crtc_state
->active
= has_connectors
;
12867 ret
= intel_modeset_setup_plane_state(state
, set
->crtc
, set
->mode
,
12868 set
->fb
, set
->x
, set
->y
);
12872 crtc_state
= drm_atomic_get_crtc_state(state
, set
->crtc
);
12873 if (IS_ERR(crtc_state
))
12874 return PTR_ERR(crtc_state
);
12877 drm_mode_copy(&crtc_state
->mode
, set
->mode
);
12879 if (set
->num_connectors
)
12880 crtc_state
->active
= true;
12885 static bool primary_plane_visible(struct drm_crtc
*crtc
)
12887 struct intel_plane_state
*plane_state
=
12888 to_intel_plane_state(crtc
->primary
->state
);
12890 return plane_state
->visible
;
12893 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12895 struct drm_device
*dev
;
12896 struct drm_atomic_state
*state
= NULL
;
12897 struct intel_crtc_state
*pipe_config
;
12898 bool primary_plane_was_visible
;
12902 BUG_ON(!set
->crtc
);
12903 BUG_ON(!set
->crtc
->helper_private
);
12905 /* Enforce sane interface api - has been abused by the fb helper. */
12906 BUG_ON(!set
->mode
&& set
->fb
);
12907 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12910 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12911 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12912 (int)set
->num_connectors
, set
->x
, set
->y
);
12914 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12917 dev
= set
->crtc
->dev
;
12919 state
= drm_atomic_state_alloc(dev
);
12923 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12925 ret
= intel_modeset_stage_output_state(dev
, set
, state
);
12929 pipe_config
= intel_modeset_compute_config(set
->crtc
, state
);
12930 if (IS_ERR(pipe_config
)) {
12931 ret
= PTR_ERR(pipe_config
);
12935 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12937 primary_plane_was_visible
= primary_plane_visible(set
->crtc
);
12939 ret
= intel_set_mode_with_config(set
->crtc
, pipe_config
);
12942 pipe_config
->base
.enable
&&
12943 pipe_config
->base
.planes_changed
&&
12944 !needs_modeset(&pipe_config
->base
)) {
12945 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12948 * We need to make sure the primary plane is re-enabled if it
12949 * has previously been turned off.
12951 if (ret
== 0 && !primary_plane_was_visible
&&
12952 primary_plane_visible(set
->crtc
)) {
12953 WARN_ON(!intel_crtc
->active
);
12954 intel_post_enable_primary(set
->crtc
);
12958 * In the fastboot case this may be our only check of the
12959 * state after boot. It would be better to only do it on
12960 * the first update, but we don't have a nice way of doing that
12961 * (and really, set_config isn't used much for high freq page
12962 * flipping, so increasing its cost here shouldn't be a big
12965 if (i915
.fastboot
&& ret
== 0)
12966 intel_modeset_check_state(set
->crtc
->dev
);
12970 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12971 set
->crtc
->base
.id
, ret
);
12976 drm_atomic_state_free(state
);
12980 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12981 .gamma_set
= intel_crtc_gamma_set
,
12982 .set_config
= intel_crtc_set_config
,
12983 .destroy
= intel_crtc_destroy
,
12984 .page_flip
= intel_crtc_page_flip
,
12985 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12986 .atomic_destroy_state
= intel_crtc_destroy_state
,
12989 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
12990 struct intel_shared_dpll
*pll
,
12991 struct intel_dpll_hw_state
*hw_state
)
12995 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
12998 val
= I915_READ(PCH_DPLL(pll
->id
));
12999 hw_state
->dpll
= val
;
13000 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13001 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13003 return val
& DPLL_VCO_ENABLE
;
13006 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13007 struct intel_shared_dpll
*pll
)
13009 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13010 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13013 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13014 struct intel_shared_dpll
*pll
)
13016 /* PCH refclock must be enabled first */
13017 ibx_assert_pch_refclk_enabled(dev_priv
);
13019 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13021 /* Wait for the clocks to stabilize. */
13022 POSTING_READ(PCH_DPLL(pll
->id
));
13025 /* The pixel multiplier can only be updated once the
13026 * DPLL is enabled and the clocks are stable.
13028 * So write it again.
13030 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13031 POSTING_READ(PCH_DPLL(pll
->id
));
13035 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13036 struct intel_shared_dpll
*pll
)
13038 struct drm_device
*dev
= dev_priv
->dev
;
13039 struct intel_crtc
*crtc
;
13041 /* Make sure no transcoder isn't still depending on us. */
13042 for_each_intel_crtc(dev
, crtc
) {
13043 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13044 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13047 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13048 POSTING_READ(PCH_DPLL(pll
->id
));
13052 static char *ibx_pch_dpll_names
[] = {
13057 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13062 dev_priv
->num_shared_dpll
= 2;
13064 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13065 dev_priv
->shared_dplls
[i
].id
= i
;
13066 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13067 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13068 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13069 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13070 dev_priv
->shared_dplls
[i
].get_hw_state
=
13071 ibx_pch_dpll_get_hw_state
;
13075 static void intel_shared_dpll_init(struct drm_device
*dev
)
13077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13080 intel_ddi_pll_init(dev
);
13081 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13082 ibx_pch_dpll_init(dev
);
13084 dev_priv
->num_shared_dpll
= 0;
13086 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13090 * intel_wm_need_update - Check whether watermarks need updating
13091 * @plane: drm plane
13092 * @state: new plane state
13094 * Check current plane state versus the new one to determine whether
13095 * watermarks need to be recalculated.
13097 * Returns true or false.
13099 bool intel_wm_need_update(struct drm_plane
*plane
,
13100 struct drm_plane_state
*state
)
13102 /* Update watermarks on tiling changes. */
13103 if (!plane
->state
->fb
|| !state
->fb
||
13104 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
13105 plane
->state
->rotation
!= state
->rotation
)
13112 * intel_prepare_plane_fb - Prepare fb for usage on plane
13113 * @plane: drm plane to prepare for
13114 * @fb: framebuffer to prepare for presentation
13116 * Prepares a framebuffer for usage on a display plane. Generally this
13117 * involves pinning the underlying object and updating the frontbuffer tracking
13118 * bits. Some older platforms need special physical address handling for
13121 * Returns 0 on success, negative error code on failure.
13124 intel_prepare_plane_fb(struct drm_plane
*plane
,
13125 struct drm_framebuffer
*fb
,
13126 const struct drm_plane_state
*new_state
)
13128 struct drm_device
*dev
= plane
->dev
;
13129 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13130 enum pipe pipe
= intel_plane
->pipe
;
13131 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13132 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13133 unsigned frontbuffer_bits
= 0;
13139 switch (plane
->type
) {
13140 case DRM_PLANE_TYPE_PRIMARY
:
13141 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13143 case DRM_PLANE_TYPE_CURSOR
:
13144 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13146 case DRM_PLANE_TYPE_OVERLAY
:
13147 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
13151 mutex_lock(&dev
->struct_mutex
);
13153 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13154 INTEL_INFO(dev
)->cursor_needs_physical
) {
13155 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13156 ret
= i915_gem_object_attach_phys(obj
, align
);
13158 DRM_DEBUG_KMS("failed to attach phys object\n");
13160 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
13164 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
13166 mutex_unlock(&dev
->struct_mutex
);
13172 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13173 * @plane: drm plane to clean up for
13174 * @fb: old framebuffer that was on plane
13176 * Cleans up a framebuffer that has just been removed from a plane.
13179 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13180 struct drm_framebuffer
*fb
,
13181 const struct drm_plane_state
*old_state
)
13183 struct drm_device
*dev
= plane
->dev
;
13184 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13189 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13190 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13191 mutex_lock(&dev
->struct_mutex
);
13192 intel_unpin_fb_obj(fb
, old_state
);
13193 mutex_unlock(&dev
->struct_mutex
);
13198 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13201 struct drm_device
*dev
;
13202 struct drm_i915_private
*dev_priv
;
13203 int crtc_clock
, cdclk
;
13205 if (!intel_crtc
|| !crtc_state
)
13206 return DRM_PLANE_HELPER_NO_SCALING
;
13208 dev
= intel_crtc
->base
.dev
;
13209 dev_priv
= dev
->dev_private
;
13210 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13211 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
13213 if (!crtc_clock
|| !cdclk
)
13214 return DRM_PLANE_HELPER_NO_SCALING
;
13217 * skl max scale is lower of:
13218 * close to 3 but not 3, -1 is for that purpose
13222 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13228 intel_check_primary_plane(struct drm_plane
*plane
,
13229 struct intel_plane_state
*state
)
13231 struct drm_device
*dev
= plane
->dev
;
13232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13233 struct drm_crtc
*crtc
= state
->base
.crtc
;
13234 struct intel_crtc
*intel_crtc
;
13235 struct intel_crtc_state
*crtc_state
;
13236 struct drm_framebuffer
*fb
= state
->base
.fb
;
13237 struct drm_rect
*dest
= &state
->dst
;
13238 struct drm_rect
*src
= &state
->src
;
13239 const struct drm_rect
*clip
= &state
->clip
;
13240 bool can_position
= false;
13241 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13242 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13245 crtc
= crtc
? crtc
: plane
->crtc
;
13246 intel_crtc
= to_intel_crtc(crtc
);
13247 crtc_state
= state
->base
.state
?
13248 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
13250 if (INTEL_INFO(dev
)->gen
>= 9) {
13251 /* use scaler when colorkey is not required */
13252 if (to_intel_plane(plane
)->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13254 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
13256 can_position
= true;
13259 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13263 can_position
, true,
13268 if (intel_crtc
->active
) {
13269 struct intel_plane_state
*old_state
=
13270 to_intel_plane_state(plane
->state
);
13272 intel_crtc
->atomic
.wait_for_flips
= true;
13275 * FBC does not work on some platforms for rotated
13276 * planes, so disable it when rotation is not 0 and
13277 * update it when rotation is set back to 0.
13279 * FIXME: This is redundant with the fbc update done in
13280 * the primary plane enable function except that that
13281 * one is done too late. We eventually need to unify
13284 if (state
->visible
&&
13285 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
13286 dev_priv
->fbc
.crtc
== intel_crtc
&&
13287 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
13288 intel_crtc
->atomic
.disable_fbc
= true;
13291 if (state
->visible
&& !old_state
->visible
) {
13293 * BDW signals flip done immediately if the plane
13294 * is disabled, even if the plane enable is already
13295 * armed to occur at the next vblank :(
13297 if (IS_BROADWELL(dev
))
13298 intel_crtc
->atomic
.wait_vblank
= true;
13301 intel_crtc
->atomic
.fb_bits
|=
13302 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
13304 intel_crtc
->atomic
.update_fbc
= true;
13306 if (intel_wm_need_update(plane
, &state
->base
))
13307 intel_crtc
->atomic
.update_wm
= true;
13310 if (INTEL_INFO(dev
)->gen
>= 9) {
13311 ret
= skl_update_scaler_users(intel_crtc
, crtc_state
,
13312 to_intel_plane(plane
), state
, 0);
13321 intel_commit_primary_plane(struct drm_plane
*plane
,
13322 struct intel_plane_state
*state
)
13324 struct drm_crtc
*crtc
= state
->base
.crtc
;
13325 struct drm_framebuffer
*fb
= state
->base
.fb
;
13326 struct drm_device
*dev
= plane
->dev
;
13327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13328 struct intel_crtc
*intel_crtc
;
13329 struct drm_rect
*src
= &state
->src
;
13331 crtc
= crtc
? crtc
: plane
->crtc
;
13332 intel_crtc
= to_intel_crtc(crtc
);
13335 crtc
->x
= src
->x1
>> 16;
13336 crtc
->y
= src
->y1
>> 16;
13338 if (intel_crtc
->active
) {
13339 if (state
->visible
)
13340 /* FIXME: kill this fastboot hack */
13341 intel_update_pipe_size(intel_crtc
);
13343 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
13349 intel_disable_primary_plane(struct drm_plane
*plane
,
13350 struct drm_crtc
*crtc
,
13353 struct drm_device
*dev
= plane
->dev
;
13354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13356 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13359 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13361 struct drm_device
*dev
= crtc
->dev
;
13362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13363 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13364 struct intel_plane
*intel_plane
;
13365 struct drm_plane
*p
;
13366 unsigned fb_bits
= 0;
13368 /* Track fb's for any planes being disabled */
13369 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
13370 intel_plane
= to_intel_plane(p
);
13372 if (intel_crtc
->atomic
.disabled_planes
&
13373 (1 << drm_plane_index(p
))) {
13375 case DRM_PLANE_TYPE_PRIMARY
:
13376 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
13378 case DRM_PLANE_TYPE_CURSOR
:
13379 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
13381 case DRM_PLANE_TYPE_OVERLAY
:
13382 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
13386 mutex_lock(&dev
->struct_mutex
);
13387 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
13388 mutex_unlock(&dev
->struct_mutex
);
13392 if (intel_crtc
->atomic
.wait_for_flips
)
13393 intel_crtc_wait_for_pending_flips(crtc
);
13395 if (intel_crtc
->atomic
.disable_fbc
)
13396 intel_fbc_disable(dev
);
13398 if (intel_crtc
->atomic
.pre_disable_primary
)
13399 intel_pre_disable_primary(crtc
);
13401 if (intel_crtc
->atomic
.update_wm
)
13402 intel_update_watermarks(crtc
);
13404 intel_runtime_pm_get(dev_priv
);
13406 /* Perform vblank evasion around commit operation */
13407 if (intel_crtc
->active
)
13408 intel_crtc
->atomic
.evade
=
13409 intel_pipe_update_start(intel_crtc
,
13410 &intel_crtc
->atomic
.start_vbl_count
);
13413 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13415 struct drm_device
*dev
= crtc
->dev
;
13416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13417 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13418 struct drm_plane
*p
;
13420 if (intel_crtc
->atomic
.evade
)
13421 intel_pipe_update_end(intel_crtc
,
13422 intel_crtc
->atomic
.start_vbl_count
);
13424 intel_runtime_pm_put(dev_priv
);
13426 if (intel_crtc
->atomic
.wait_vblank
)
13427 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
13429 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
13431 if (intel_crtc
->atomic
.update_fbc
) {
13432 mutex_lock(&dev
->struct_mutex
);
13433 intel_fbc_update(dev
);
13434 mutex_unlock(&dev
->struct_mutex
);
13437 if (intel_crtc
->atomic
.post_enable_primary
)
13438 intel_post_enable_primary(crtc
);
13440 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
13441 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
13442 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
13445 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
13449 * intel_plane_destroy - destroy a plane
13450 * @plane: plane to destroy
13452 * Common destruction function for all types of planes (primary, cursor,
13455 void intel_plane_destroy(struct drm_plane
*plane
)
13457 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13458 drm_plane_cleanup(plane
);
13459 kfree(intel_plane
);
13462 const struct drm_plane_funcs intel_plane_funcs
= {
13463 .update_plane
= drm_atomic_helper_update_plane
,
13464 .disable_plane
= drm_atomic_helper_disable_plane
,
13465 .destroy
= intel_plane_destroy
,
13466 .set_property
= drm_atomic_helper_plane_set_property
,
13467 .atomic_get_property
= intel_plane_atomic_get_property
,
13468 .atomic_set_property
= intel_plane_atomic_set_property
,
13469 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13470 .atomic_destroy_state
= intel_plane_destroy_state
,
13474 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13477 struct intel_plane
*primary
;
13478 struct intel_plane_state
*state
;
13479 const uint32_t *intel_primary_formats
;
13482 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13483 if (primary
== NULL
)
13486 state
= intel_create_plane_state(&primary
->base
);
13491 primary
->base
.state
= &state
->base
;
13493 primary
->can_scale
= false;
13494 primary
->max_downscale
= 1;
13495 if (INTEL_INFO(dev
)->gen
>= 9) {
13496 primary
->can_scale
= true;
13497 state
->scaler_id
= -1;
13499 primary
->pipe
= pipe
;
13500 primary
->plane
= pipe
;
13501 primary
->check_plane
= intel_check_primary_plane
;
13502 primary
->commit_plane
= intel_commit_primary_plane
;
13503 primary
->disable_plane
= intel_disable_primary_plane
;
13504 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13505 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13506 primary
->plane
= !pipe
;
13508 if (INTEL_INFO(dev
)->gen
>= 9) {
13509 intel_primary_formats
= skl_primary_formats
;
13510 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13511 } else if (INTEL_INFO(dev
)->gen
>= 4) {
13512 intel_primary_formats
= i965_primary_formats
;
13513 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13515 intel_primary_formats
= i8xx_primary_formats
;
13516 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13519 drm_universal_plane_init(dev
, &primary
->base
, 0,
13520 &intel_plane_funcs
,
13521 intel_primary_formats
, num_formats
,
13522 DRM_PLANE_TYPE_PRIMARY
);
13524 if (INTEL_INFO(dev
)->gen
>= 4)
13525 intel_create_rotation_property(dev
, primary
);
13527 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13529 return &primary
->base
;
13532 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13534 if (!dev
->mode_config
.rotation_property
) {
13535 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13536 BIT(DRM_ROTATE_180
);
13538 if (INTEL_INFO(dev
)->gen
>= 9)
13539 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13541 dev
->mode_config
.rotation_property
=
13542 drm_mode_create_rotation_property(dev
, flags
);
13544 if (dev
->mode_config
.rotation_property
)
13545 drm_object_attach_property(&plane
->base
.base
,
13546 dev
->mode_config
.rotation_property
,
13547 plane
->base
.state
->rotation
);
13551 intel_check_cursor_plane(struct drm_plane
*plane
,
13552 struct intel_plane_state
*state
)
13554 struct drm_crtc
*crtc
= state
->base
.crtc
;
13555 struct drm_device
*dev
= plane
->dev
;
13556 struct drm_framebuffer
*fb
= state
->base
.fb
;
13557 struct drm_rect
*dest
= &state
->dst
;
13558 struct drm_rect
*src
= &state
->src
;
13559 const struct drm_rect
*clip
= &state
->clip
;
13560 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13561 struct intel_crtc
*intel_crtc
;
13565 crtc
= crtc
? crtc
: plane
->crtc
;
13566 intel_crtc
= to_intel_crtc(crtc
);
13568 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13570 DRM_PLANE_HELPER_NO_SCALING
,
13571 DRM_PLANE_HELPER_NO_SCALING
,
13572 true, true, &state
->visible
);
13577 /* if we want to turn off the cursor ignore width and height */
13581 /* Check for which cursor types we support */
13582 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13583 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13584 state
->base
.crtc_w
, state
->base
.crtc_h
);
13588 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13589 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13590 DRM_DEBUG_KMS("buffer is too small\n");
13594 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13595 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13600 if (intel_crtc
->active
) {
13601 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
13602 intel_crtc
->atomic
.update_wm
= true;
13604 intel_crtc
->atomic
.fb_bits
|=
13605 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
13612 intel_disable_cursor_plane(struct drm_plane
*plane
,
13613 struct drm_crtc
*crtc
,
13616 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13620 intel_crtc
->cursor_bo
= NULL
;
13621 intel_crtc
->cursor_addr
= 0;
13624 intel_crtc_update_cursor(crtc
, false);
13628 intel_commit_cursor_plane(struct drm_plane
*plane
,
13629 struct intel_plane_state
*state
)
13631 struct drm_crtc
*crtc
= state
->base
.crtc
;
13632 struct drm_device
*dev
= plane
->dev
;
13633 struct intel_crtc
*intel_crtc
;
13634 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13637 crtc
= crtc
? crtc
: plane
->crtc
;
13638 intel_crtc
= to_intel_crtc(crtc
);
13640 plane
->fb
= state
->base
.fb
;
13641 crtc
->cursor_x
= state
->base
.crtc_x
;
13642 crtc
->cursor_y
= state
->base
.crtc_y
;
13644 if (intel_crtc
->cursor_bo
== obj
)
13649 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13650 addr
= i915_gem_obj_ggtt_offset(obj
);
13652 addr
= obj
->phys_handle
->busaddr
;
13654 intel_crtc
->cursor_addr
= addr
;
13655 intel_crtc
->cursor_bo
= obj
;
13658 if (intel_crtc
->active
)
13659 intel_crtc_update_cursor(crtc
, state
->visible
);
13662 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13665 struct intel_plane
*cursor
;
13666 struct intel_plane_state
*state
;
13668 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13669 if (cursor
== NULL
)
13672 state
= intel_create_plane_state(&cursor
->base
);
13677 cursor
->base
.state
= &state
->base
;
13679 cursor
->can_scale
= false;
13680 cursor
->max_downscale
= 1;
13681 cursor
->pipe
= pipe
;
13682 cursor
->plane
= pipe
;
13683 cursor
->check_plane
= intel_check_cursor_plane
;
13684 cursor
->commit_plane
= intel_commit_cursor_plane
;
13685 cursor
->disable_plane
= intel_disable_cursor_plane
;
13687 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13688 &intel_plane_funcs
,
13689 intel_cursor_formats
,
13690 ARRAY_SIZE(intel_cursor_formats
),
13691 DRM_PLANE_TYPE_CURSOR
);
13693 if (INTEL_INFO(dev
)->gen
>= 4) {
13694 if (!dev
->mode_config
.rotation_property
)
13695 dev
->mode_config
.rotation_property
=
13696 drm_mode_create_rotation_property(dev
,
13697 BIT(DRM_ROTATE_0
) |
13698 BIT(DRM_ROTATE_180
));
13699 if (dev
->mode_config
.rotation_property
)
13700 drm_object_attach_property(&cursor
->base
.base
,
13701 dev
->mode_config
.rotation_property
,
13702 state
->base
.rotation
);
13705 if (INTEL_INFO(dev
)->gen
>=9)
13706 state
->scaler_id
= -1;
13708 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13710 return &cursor
->base
;
13713 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13714 struct intel_crtc_state
*crtc_state
)
13717 struct intel_scaler
*intel_scaler
;
13718 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13720 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13721 intel_scaler
= &scaler_state
->scalers
[i
];
13722 intel_scaler
->in_use
= 0;
13723 intel_scaler
->id
= i
;
13725 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13728 scaler_state
->scaler_id
= -1;
13731 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13734 struct intel_crtc
*intel_crtc
;
13735 struct intel_crtc_state
*crtc_state
= NULL
;
13736 struct drm_plane
*primary
= NULL
;
13737 struct drm_plane
*cursor
= NULL
;
13740 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13741 if (intel_crtc
== NULL
)
13744 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13747 intel_crtc
->config
= crtc_state
;
13748 intel_crtc
->base
.state
= &crtc_state
->base
;
13749 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13751 /* initialize shared scalers */
13752 if (INTEL_INFO(dev
)->gen
>= 9) {
13753 if (pipe
== PIPE_C
)
13754 intel_crtc
->num_scalers
= 1;
13756 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13758 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13761 primary
= intel_primary_plane_create(dev
, pipe
);
13765 cursor
= intel_cursor_plane_create(dev
, pipe
);
13769 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13770 cursor
, &intel_crtc_funcs
);
13774 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13775 for (i
= 0; i
< 256; i
++) {
13776 intel_crtc
->lut_r
[i
] = i
;
13777 intel_crtc
->lut_g
[i
] = i
;
13778 intel_crtc
->lut_b
[i
] = i
;
13782 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13783 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13785 intel_crtc
->pipe
= pipe
;
13786 intel_crtc
->plane
= pipe
;
13787 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13788 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13789 intel_crtc
->plane
= !pipe
;
13792 intel_crtc
->cursor_base
= ~0;
13793 intel_crtc
->cursor_cntl
= ~0;
13794 intel_crtc
->cursor_size
= ~0;
13796 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13797 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13798 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13799 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13801 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13803 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13808 drm_plane_cleanup(primary
);
13810 drm_plane_cleanup(cursor
);
13815 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13817 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13818 struct drm_device
*dev
= connector
->base
.dev
;
13820 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13822 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13823 return INVALID_PIPE
;
13825 return to_intel_crtc(encoder
->crtc
)->pipe
;
13828 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13829 struct drm_file
*file
)
13831 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13832 struct drm_crtc
*drmmode_crtc
;
13833 struct intel_crtc
*crtc
;
13835 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13837 if (!drmmode_crtc
) {
13838 DRM_ERROR("no such CRTC id\n");
13842 crtc
= to_intel_crtc(drmmode_crtc
);
13843 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13848 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13850 struct drm_device
*dev
= encoder
->base
.dev
;
13851 struct intel_encoder
*source_encoder
;
13852 int index_mask
= 0;
13855 for_each_intel_encoder(dev
, source_encoder
) {
13856 if (encoders_cloneable(encoder
, source_encoder
))
13857 index_mask
|= (1 << entry
);
13865 static bool has_edp_a(struct drm_device
*dev
)
13867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13869 if (!IS_MOBILE(dev
))
13872 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13875 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13881 static bool intel_crt_present(struct drm_device
*dev
)
13883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13885 if (INTEL_INFO(dev
)->gen
>= 9)
13888 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13891 if (IS_CHERRYVIEW(dev
))
13894 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13900 static void intel_setup_outputs(struct drm_device
*dev
)
13902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13903 struct intel_encoder
*encoder
;
13904 bool dpd_is_edp
= false;
13906 intel_lvds_init(dev
);
13908 if (intel_crt_present(dev
))
13909 intel_crt_init(dev
);
13911 if (IS_BROXTON(dev
)) {
13913 * FIXME: Broxton doesn't support port detection via the
13914 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13915 * detect the ports.
13917 intel_ddi_init(dev
, PORT_A
);
13918 intel_ddi_init(dev
, PORT_B
);
13919 intel_ddi_init(dev
, PORT_C
);
13920 } else if (HAS_DDI(dev
)) {
13924 * Haswell uses DDI functions to detect digital outputs.
13925 * On SKL pre-D0 the strap isn't connected, so we assume
13928 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13929 /* WaIgnoreDDIAStrap: skl */
13931 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13932 intel_ddi_init(dev
, PORT_A
);
13934 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13936 found
= I915_READ(SFUSE_STRAP
);
13938 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13939 intel_ddi_init(dev
, PORT_B
);
13940 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13941 intel_ddi_init(dev
, PORT_C
);
13942 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13943 intel_ddi_init(dev
, PORT_D
);
13944 } else if (HAS_PCH_SPLIT(dev
)) {
13946 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13948 if (has_edp_a(dev
))
13949 intel_dp_init(dev
, DP_A
, PORT_A
);
13951 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13952 /* PCH SDVOB multiplex with HDMIB */
13953 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13955 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13956 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13957 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13960 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13961 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13963 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13964 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13966 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13967 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13969 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13970 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13971 } else if (IS_VALLEYVIEW(dev
)) {
13973 * The DP_DETECTED bit is the latched state of the DDC
13974 * SDA pin at boot. However since eDP doesn't require DDC
13975 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13976 * eDP ports may have been muxed to an alternate function.
13977 * Thus we can't rely on the DP_DETECTED bit alone to detect
13978 * eDP ports. Consult the VBT as well as DP_DETECTED to
13979 * detect eDP ports.
13981 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13982 !intel_dp_is_edp(dev
, PORT_B
))
13983 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13985 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13986 intel_dp_is_edp(dev
, PORT_B
))
13987 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13989 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13990 !intel_dp_is_edp(dev
, PORT_C
))
13991 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13993 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13994 intel_dp_is_edp(dev
, PORT_C
))
13995 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13997 if (IS_CHERRYVIEW(dev
)) {
13998 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13999 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
14001 /* eDP not supported on port D, so don't check VBT */
14002 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
14003 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
14006 intel_dsi_init(dev
);
14007 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
14008 bool found
= false;
14010 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14011 DRM_DEBUG_KMS("probing SDVOB\n");
14012 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14013 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
14014 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14015 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14018 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
14019 intel_dp_init(dev
, DP_B
, PORT_B
);
14022 /* Before G4X SDVOC doesn't have its own detect register */
14024 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14025 DRM_DEBUG_KMS("probing SDVOC\n");
14026 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14029 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14031 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
14032 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14033 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14035 if (SUPPORTS_INTEGRATED_DP(dev
))
14036 intel_dp_init(dev
, DP_C
, PORT_C
);
14039 if (SUPPORTS_INTEGRATED_DP(dev
) &&
14040 (I915_READ(DP_D
) & DP_DETECTED
))
14041 intel_dp_init(dev
, DP_D
, PORT_D
);
14042 } else if (IS_GEN2(dev
))
14043 intel_dvo_init(dev
);
14045 if (SUPPORTS_TV(dev
))
14046 intel_tv_init(dev
);
14048 intel_psr_init(dev
);
14050 for_each_intel_encoder(dev
, encoder
) {
14051 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14052 encoder
->base
.possible_clones
=
14053 intel_encoder_clones(encoder
);
14056 intel_init_pch_refclk(dev
);
14058 drm_helper_move_panel_connectors_to_head(dev
);
14061 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14063 struct drm_device
*dev
= fb
->dev
;
14064 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14066 drm_framebuffer_cleanup(fb
);
14067 mutex_lock(&dev
->struct_mutex
);
14068 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14069 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14070 mutex_unlock(&dev
->struct_mutex
);
14074 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14075 struct drm_file
*file
,
14076 unsigned int *handle
)
14078 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14079 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14081 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14084 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14085 .destroy
= intel_user_framebuffer_destroy
,
14086 .create_handle
= intel_user_framebuffer_create_handle
,
14090 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14091 uint32_t pixel_format
)
14093 u32 gen
= INTEL_INFO(dev
)->gen
;
14096 /* "The stride in bytes must not exceed the of the size of 8K
14097 * pixels and 32K bytes."
14099 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14100 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14102 } else if (gen
>= 4) {
14103 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14107 } else if (gen
>= 3) {
14108 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14113 /* XXX DSPC is limited to 4k tiled */
14118 static int intel_framebuffer_init(struct drm_device
*dev
,
14119 struct intel_framebuffer
*intel_fb
,
14120 struct drm_mode_fb_cmd2
*mode_cmd
,
14121 struct drm_i915_gem_object
*obj
)
14123 unsigned int aligned_height
;
14125 u32 pitch_limit
, stride_alignment
;
14127 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14129 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14130 /* Enforce that fb modifier and tiling mode match, but only for
14131 * X-tiled. This is needed for FBC. */
14132 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14133 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14134 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14138 if (obj
->tiling_mode
== I915_TILING_X
)
14139 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14140 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14141 DRM_DEBUG("No Y tiling for legacy addfb\n");
14146 /* Passed in modifier sanity checking. */
14147 switch (mode_cmd
->modifier
[0]) {
14148 case I915_FORMAT_MOD_Y_TILED
:
14149 case I915_FORMAT_MOD_Yf_TILED
:
14150 if (INTEL_INFO(dev
)->gen
< 9) {
14151 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14152 mode_cmd
->modifier
[0]);
14155 case DRM_FORMAT_MOD_NONE
:
14156 case I915_FORMAT_MOD_X_TILED
:
14159 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14160 mode_cmd
->modifier
[0]);
14164 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14165 mode_cmd
->pixel_format
);
14166 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14167 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14168 mode_cmd
->pitches
[0], stride_alignment
);
14172 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14173 mode_cmd
->pixel_format
);
14174 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14175 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14176 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14177 "tiled" : "linear",
14178 mode_cmd
->pitches
[0], pitch_limit
);
14182 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14183 mode_cmd
->pitches
[0] != obj
->stride
) {
14184 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14185 mode_cmd
->pitches
[0], obj
->stride
);
14189 /* Reject formats not supported by any plane early. */
14190 switch (mode_cmd
->pixel_format
) {
14191 case DRM_FORMAT_C8
:
14192 case DRM_FORMAT_RGB565
:
14193 case DRM_FORMAT_XRGB8888
:
14194 case DRM_FORMAT_ARGB8888
:
14196 case DRM_FORMAT_XRGB1555
:
14197 if (INTEL_INFO(dev
)->gen
> 3) {
14198 DRM_DEBUG("unsupported pixel format: %s\n",
14199 drm_get_format_name(mode_cmd
->pixel_format
));
14203 case DRM_FORMAT_ABGR8888
:
14204 if (!IS_VALLEYVIEW(dev
) && INTEL_INFO(dev
)->gen
< 9) {
14205 DRM_DEBUG("unsupported pixel format: %s\n",
14206 drm_get_format_name(mode_cmd
->pixel_format
));
14210 case DRM_FORMAT_XBGR8888
:
14211 case DRM_FORMAT_XRGB2101010
:
14212 case DRM_FORMAT_XBGR2101010
:
14213 if (INTEL_INFO(dev
)->gen
< 4) {
14214 DRM_DEBUG("unsupported pixel format: %s\n",
14215 drm_get_format_name(mode_cmd
->pixel_format
));
14219 case DRM_FORMAT_ABGR2101010
:
14220 if (!IS_VALLEYVIEW(dev
)) {
14221 DRM_DEBUG("unsupported pixel format: %s\n",
14222 drm_get_format_name(mode_cmd
->pixel_format
));
14226 case DRM_FORMAT_YUYV
:
14227 case DRM_FORMAT_UYVY
:
14228 case DRM_FORMAT_YVYU
:
14229 case DRM_FORMAT_VYUY
:
14230 if (INTEL_INFO(dev
)->gen
< 5) {
14231 DRM_DEBUG("unsupported pixel format: %s\n",
14232 drm_get_format_name(mode_cmd
->pixel_format
));
14237 DRM_DEBUG("unsupported pixel format: %s\n",
14238 drm_get_format_name(mode_cmd
->pixel_format
));
14242 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14243 if (mode_cmd
->offsets
[0] != 0)
14246 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14247 mode_cmd
->pixel_format
,
14248 mode_cmd
->modifier
[0]);
14249 /* FIXME drm helper for size checks (especially planar formats)? */
14250 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14253 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14254 intel_fb
->obj
= obj
;
14255 intel_fb
->obj
->framebuffer_references
++;
14257 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14259 DRM_ERROR("framebuffer init failed %d\n", ret
);
14266 static struct drm_framebuffer
*
14267 intel_user_framebuffer_create(struct drm_device
*dev
,
14268 struct drm_file
*filp
,
14269 struct drm_mode_fb_cmd2
*mode_cmd
)
14271 struct drm_i915_gem_object
*obj
;
14273 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14274 mode_cmd
->handles
[0]));
14275 if (&obj
->base
== NULL
)
14276 return ERR_PTR(-ENOENT
);
14278 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14281 #ifndef CONFIG_DRM_I915_FBDEV
14282 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14287 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14288 .fb_create
= intel_user_framebuffer_create
,
14289 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14290 .atomic_check
= intel_atomic_check
,
14291 .atomic_commit
= intel_atomic_commit
,
14294 /* Set up chip specific display functions */
14295 static void intel_init_display(struct drm_device
*dev
)
14297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14299 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14300 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14301 else if (IS_CHERRYVIEW(dev
))
14302 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14303 else if (IS_VALLEYVIEW(dev
))
14304 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14305 else if (IS_PINEVIEW(dev
))
14306 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14308 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14310 if (INTEL_INFO(dev
)->gen
>= 9) {
14311 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14312 dev_priv
->display
.get_initial_plane_config
=
14313 skylake_get_initial_plane_config
;
14314 dev_priv
->display
.crtc_compute_clock
=
14315 haswell_crtc_compute_clock
;
14316 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14317 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14318 dev_priv
->display
.off
= ironlake_crtc_off
;
14319 dev_priv
->display
.update_primary_plane
=
14320 skylake_update_primary_plane
;
14321 } else if (HAS_DDI(dev
)) {
14322 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14323 dev_priv
->display
.get_initial_plane_config
=
14324 ironlake_get_initial_plane_config
;
14325 dev_priv
->display
.crtc_compute_clock
=
14326 haswell_crtc_compute_clock
;
14327 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14328 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14329 dev_priv
->display
.off
= ironlake_crtc_off
;
14330 dev_priv
->display
.update_primary_plane
=
14331 ironlake_update_primary_plane
;
14332 } else if (HAS_PCH_SPLIT(dev
)) {
14333 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14334 dev_priv
->display
.get_initial_plane_config
=
14335 ironlake_get_initial_plane_config
;
14336 dev_priv
->display
.crtc_compute_clock
=
14337 ironlake_crtc_compute_clock
;
14338 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14339 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14340 dev_priv
->display
.off
= ironlake_crtc_off
;
14341 dev_priv
->display
.update_primary_plane
=
14342 ironlake_update_primary_plane
;
14343 } else if (IS_VALLEYVIEW(dev
)) {
14344 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14345 dev_priv
->display
.get_initial_plane_config
=
14346 i9xx_get_initial_plane_config
;
14347 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14348 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14349 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14350 dev_priv
->display
.off
= i9xx_crtc_off
;
14351 dev_priv
->display
.update_primary_plane
=
14352 i9xx_update_primary_plane
;
14354 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14355 dev_priv
->display
.get_initial_plane_config
=
14356 i9xx_get_initial_plane_config
;
14357 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14358 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14359 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14360 dev_priv
->display
.off
= i9xx_crtc_off
;
14361 dev_priv
->display
.update_primary_plane
=
14362 i9xx_update_primary_plane
;
14365 /* Returns the core display clock speed */
14366 if (IS_SKYLAKE(dev
))
14367 dev_priv
->display
.get_display_clock_speed
=
14368 skylake_get_display_clock_speed
;
14369 else if (IS_BROADWELL(dev
))
14370 dev_priv
->display
.get_display_clock_speed
=
14371 broadwell_get_display_clock_speed
;
14372 else if (IS_HASWELL(dev
))
14373 dev_priv
->display
.get_display_clock_speed
=
14374 haswell_get_display_clock_speed
;
14375 else if (IS_VALLEYVIEW(dev
))
14376 dev_priv
->display
.get_display_clock_speed
=
14377 valleyview_get_display_clock_speed
;
14378 else if (IS_GEN5(dev
))
14379 dev_priv
->display
.get_display_clock_speed
=
14380 ilk_get_display_clock_speed
;
14381 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14382 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
14383 dev_priv
->display
.get_display_clock_speed
=
14384 i945_get_display_clock_speed
;
14385 else if (IS_I915G(dev
))
14386 dev_priv
->display
.get_display_clock_speed
=
14387 i915_get_display_clock_speed
;
14388 else if (IS_I945GM(dev
) || IS_845G(dev
))
14389 dev_priv
->display
.get_display_clock_speed
=
14390 i9xx_misc_get_display_clock_speed
;
14391 else if (IS_PINEVIEW(dev
))
14392 dev_priv
->display
.get_display_clock_speed
=
14393 pnv_get_display_clock_speed
;
14394 else if (IS_I915GM(dev
))
14395 dev_priv
->display
.get_display_clock_speed
=
14396 i915gm_get_display_clock_speed
;
14397 else if (IS_I865G(dev
))
14398 dev_priv
->display
.get_display_clock_speed
=
14399 i865_get_display_clock_speed
;
14400 else if (IS_I85X(dev
))
14401 dev_priv
->display
.get_display_clock_speed
=
14402 i855_get_display_clock_speed
;
14403 else /* 852, 830 */
14404 dev_priv
->display
.get_display_clock_speed
=
14405 i830_get_display_clock_speed
;
14407 if (IS_GEN5(dev
)) {
14408 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14409 } else if (IS_GEN6(dev
)) {
14410 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14411 } else if (IS_IVYBRIDGE(dev
)) {
14412 /* FIXME: detect B0+ stepping and use auto training */
14413 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14414 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14415 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14416 } else if (IS_VALLEYVIEW(dev
)) {
14417 dev_priv
->display
.modeset_global_resources
=
14418 valleyview_modeset_global_resources
;
14419 } else if (IS_BROXTON(dev
)) {
14420 dev_priv
->display
.modeset_global_resources
=
14421 broxton_modeset_global_resources
;
14424 switch (INTEL_INFO(dev
)->gen
) {
14426 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14430 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14435 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14439 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14442 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14443 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14446 /* Drop through - unsupported since execlist only. */
14448 /* Default just returns -ENODEV to indicate unsupported */
14449 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14452 intel_panel_init_backlight_funcs(dev
);
14454 mutex_init(&dev_priv
->pps_mutex
);
14458 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14459 * resume, or other times. This quirk makes sure that's the case for
14460 * affected systems.
14462 static void quirk_pipea_force(struct drm_device
*dev
)
14464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14466 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14467 DRM_INFO("applying pipe a force quirk\n");
14470 static void quirk_pipeb_force(struct drm_device
*dev
)
14472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14474 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14475 DRM_INFO("applying pipe b force quirk\n");
14479 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14481 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14484 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14485 DRM_INFO("applying lvds SSC disable quirk\n");
14489 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14492 static void quirk_invert_brightness(struct drm_device
*dev
)
14494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14495 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14496 DRM_INFO("applying inverted panel brightness quirk\n");
14499 /* Some VBT's incorrectly indicate no backlight is present */
14500 static void quirk_backlight_present(struct drm_device
*dev
)
14502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14503 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14504 DRM_INFO("applying backlight present quirk\n");
14507 struct intel_quirk
{
14509 int subsystem_vendor
;
14510 int subsystem_device
;
14511 void (*hook
)(struct drm_device
*dev
);
14514 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14515 struct intel_dmi_quirk
{
14516 void (*hook
)(struct drm_device
*dev
);
14517 const struct dmi_system_id (*dmi_id_list
)[];
14520 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14522 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14526 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14528 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14530 .callback
= intel_dmi_reverse_brightness
,
14531 .ident
= "NCR Corporation",
14532 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14533 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14536 { } /* terminating entry */
14538 .hook
= quirk_invert_brightness
,
14542 static struct intel_quirk intel_quirks
[] = {
14543 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14544 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14546 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14547 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14549 /* 830 needs to leave pipe A & dpll A up */
14550 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14552 /* 830 needs to leave pipe B & dpll B up */
14553 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14555 /* Lenovo U160 cannot use SSC on LVDS */
14556 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14558 /* Sony Vaio Y cannot use SSC on LVDS */
14559 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14561 /* Acer Aspire 5734Z must invert backlight brightness */
14562 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14564 /* Acer/eMachines G725 */
14565 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14567 /* Acer/eMachines e725 */
14568 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14570 /* Acer/Packard Bell NCL20 */
14571 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14573 /* Acer Aspire 4736Z */
14574 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14576 /* Acer Aspire 5336 */
14577 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14579 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14580 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14582 /* Acer C720 Chromebook (Core i3 4005U) */
14583 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14585 /* Apple Macbook 2,1 (Core 2 T7400) */
14586 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14588 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14589 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14591 /* HP Chromebook 14 (Celeron 2955U) */
14592 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14594 /* Dell Chromebook 11 */
14595 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14598 static void intel_init_quirks(struct drm_device
*dev
)
14600 struct pci_dev
*d
= dev
->pdev
;
14603 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14604 struct intel_quirk
*q
= &intel_quirks
[i
];
14606 if (d
->device
== q
->device
&&
14607 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14608 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14609 (d
->subsystem_device
== q
->subsystem_device
||
14610 q
->subsystem_device
== PCI_ANY_ID
))
14613 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14614 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14615 intel_dmi_quirks
[i
].hook(dev
);
14619 /* Disable the VGA plane that we never use */
14620 static void i915_disable_vga(struct drm_device
*dev
)
14622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14624 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14626 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14627 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14628 outb(SR01
, VGA_SR_INDEX
);
14629 sr1
= inb(VGA_SR_DATA
);
14630 outb(sr1
| 1<<5, VGA_SR_DATA
);
14631 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14634 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14635 POSTING_READ(vga_reg
);
14638 void intel_modeset_init_hw(struct drm_device
*dev
)
14640 intel_prepare_ddi(dev
);
14642 if (IS_VALLEYVIEW(dev
))
14643 vlv_update_cdclk(dev
);
14645 intel_init_clock_gating(dev
);
14647 intel_enable_gt_powersave(dev
);
14650 void intel_modeset_init(struct drm_device
*dev
)
14652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14655 struct intel_crtc
*crtc
;
14657 drm_mode_config_init(dev
);
14659 dev
->mode_config
.min_width
= 0;
14660 dev
->mode_config
.min_height
= 0;
14662 dev
->mode_config
.preferred_depth
= 24;
14663 dev
->mode_config
.prefer_shadow
= 1;
14665 dev
->mode_config
.allow_fb_modifiers
= true;
14667 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14669 intel_init_quirks(dev
);
14671 intel_init_pm(dev
);
14673 if (INTEL_INFO(dev
)->num_pipes
== 0)
14676 intel_init_display(dev
);
14677 intel_init_audio(dev
);
14679 if (IS_GEN2(dev
)) {
14680 dev
->mode_config
.max_width
= 2048;
14681 dev
->mode_config
.max_height
= 2048;
14682 } else if (IS_GEN3(dev
)) {
14683 dev
->mode_config
.max_width
= 4096;
14684 dev
->mode_config
.max_height
= 4096;
14686 dev
->mode_config
.max_width
= 8192;
14687 dev
->mode_config
.max_height
= 8192;
14690 if (IS_845G(dev
) || IS_I865G(dev
)) {
14691 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14692 dev
->mode_config
.cursor_height
= 1023;
14693 } else if (IS_GEN2(dev
)) {
14694 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14695 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14697 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14698 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14701 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14703 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14704 INTEL_INFO(dev
)->num_pipes
,
14705 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14707 for_each_pipe(dev_priv
, pipe
) {
14708 intel_crtc_init(dev
, pipe
);
14709 for_each_sprite(dev_priv
, pipe
, sprite
) {
14710 ret
= intel_plane_init(dev
, pipe
, sprite
);
14712 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14713 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14717 intel_init_dpio(dev
);
14719 intel_shared_dpll_init(dev
);
14721 /* Just disable it once at startup */
14722 i915_disable_vga(dev
);
14723 intel_setup_outputs(dev
);
14725 /* Just in case the BIOS is doing something questionable. */
14726 intel_fbc_disable(dev
);
14728 drm_modeset_lock_all(dev
);
14729 intel_modeset_setup_hw_state(dev
, false);
14730 drm_modeset_unlock_all(dev
);
14732 for_each_intel_crtc(dev
, crtc
) {
14737 * Note that reserving the BIOS fb up front prevents us
14738 * from stuffing other stolen allocations like the ring
14739 * on top. This prevents some ugliness at boot time, and
14740 * can even allow for smooth boot transitions if the BIOS
14741 * fb is large enough for the active pipe configuration.
14743 if (dev_priv
->display
.get_initial_plane_config
) {
14744 dev_priv
->display
.get_initial_plane_config(crtc
,
14745 &crtc
->plane_config
);
14747 * If the fb is shared between multiple heads, we'll
14748 * just get the first one.
14750 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
14755 static void intel_enable_pipe_a(struct drm_device
*dev
)
14757 struct intel_connector
*connector
;
14758 struct drm_connector
*crt
= NULL
;
14759 struct intel_load_detect_pipe load_detect_temp
;
14760 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14762 /* We can't just switch on the pipe A, we need to set things up with a
14763 * proper mode and output configuration. As a gross hack, enable pipe A
14764 * by enabling the load detect pipe once. */
14765 for_each_intel_connector(dev
, connector
) {
14766 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14767 crt
= &connector
->base
;
14775 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14776 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14780 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14782 struct drm_device
*dev
= crtc
->base
.dev
;
14783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14786 if (INTEL_INFO(dev
)->num_pipes
== 1)
14789 reg
= DSPCNTR(!crtc
->plane
);
14790 val
= I915_READ(reg
);
14792 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14793 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14799 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14801 struct drm_device
*dev
= crtc
->base
.dev
;
14802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14805 /* Clear any frame start delays used for debugging left by the BIOS */
14806 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14807 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14809 /* restore vblank interrupts to correct state */
14810 drm_crtc_vblank_reset(&crtc
->base
);
14811 if (crtc
->active
) {
14812 update_scanline_offset(crtc
);
14813 drm_crtc_vblank_on(&crtc
->base
);
14816 /* We need to sanitize the plane -> pipe mapping first because this will
14817 * disable the crtc (and hence change the state) if it is wrong. Note
14818 * that gen4+ has a fixed plane -> pipe mapping. */
14819 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14820 struct intel_connector
*connector
;
14823 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14824 crtc
->base
.base
.id
);
14826 /* Pipe has the wrong plane attached and the plane is active.
14827 * Temporarily change the plane mapping and disable everything
14829 plane
= crtc
->plane
;
14830 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
14831 crtc
->plane
= !plane
;
14832 intel_crtc_disable_planes(&crtc
->base
);
14833 dev_priv
->display
.crtc_disable(&crtc
->base
);
14834 crtc
->plane
= plane
;
14836 /* ... and break all links. */
14837 for_each_intel_connector(dev
, connector
) {
14838 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14841 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14842 connector
->base
.encoder
= NULL
;
14844 /* multiple connectors may have the same encoder:
14845 * handle them and break crtc link separately */
14846 for_each_intel_connector(dev
, connector
)
14847 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14848 connector
->encoder
->base
.crtc
= NULL
;
14849 connector
->encoder
->connectors_active
= false;
14852 WARN_ON(crtc
->active
);
14853 crtc
->base
.state
->enable
= false;
14854 crtc
->base
.state
->active
= false;
14855 crtc
->base
.enabled
= false;
14858 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14859 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14860 /* BIOS forgot to enable pipe A, this mostly happens after
14861 * resume. Force-enable the pipe to fix this, the update_dpms
14862 * call below we restore the pipe to the right state, but leave
14863 * the required bits on. */
14864 intel_enable_pipe_a(dev
);
14867 /* Adjust the state of the output pipe according to whether we
14868 * have active connectors/encoders. */
14869 intel_crtc_update_dpms(&crtc
->base
);
14871 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14872 struct intel_encoder
*encoder
;
14874 /* This can happen either due to bugs in the get_hw_state
14875 * functions or because the pipe is force-enabled due to the
14877 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14878 crtc
->base
.base
.id
,
14879 crtc
->base
.state
->enable
? "enabled" : "disabled",
14880 crtc
->active
? "enabled" : "disabled");
14882 crtc
->base
.state
->enable
= crtc
->active
;
14883 crtc
->base
.state
->active
= crtc
->active
;
14884 crtc
->base
.enabled
= crtc
->active
;
14886 /* Because we only establish the connector -> encoder ->
14887 * crtc links if something is active, this means the
14888 * crtc is now deactivated. Break the links. connector
14889 * -> encoder links are only establish when things are
14890 * actually up, hence no need to break them. */
14891 WARN_ON(crtc
->active
);
14893 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14894 WARN_ON(encoder
->connectors_active
);
14895 encoder
->base
.crtc
= NULL
;
14899 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14901 * We start out with underrun reporting disabled to avoid races.
14902 * For correct bookkeeping mark this on active crtcs.
14904 * Also on gmch platforms we dont have any hardware bits to
14905 * disable the underrun reporting. Which means we need to start
14906 * out with underrun reporting disabled also on inactive pipes,
14907 * since otherwise we'll complain about the garbage we read when
14908 * e.g. coming up after runtime pm.
14910 * No protection against concurrent access is required - at
14911 * worst a fifo underrun happens which also sets this to false.
14913 crtc
->cpu_fifo_underrun_disabled
= true;
14914 crtc
->pch_fifo_underrun_disabled
= true;
14918 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14920 struct intel_connector
*connector
;
14921 struct drm_device
*dev
= encoder
->base
.dev
;
14923 /* We need to check both for a crtc link (meaning that the
14924 * encoder is active and trying to read from a pipe) and the
14925 * pipe itself being active. */
14926 bool has_active_crtc
= encoder
->base
.crtc
&&
14927 to_intel_crtc(encoder
->base
.crtc
)->active
;
14929 if (encoder
->connectors_active
&& !has_active_crtc
) {
14930 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14931 encoder
->base
.base
.id
,
14932 encoder
->base
.name
);
14934 /* Connector is active, but has no active pipe. This is
14935 * fallout from our resume register restoring. Disable
14936 * the encoder manually again. */
14937 if (encoder
->base
.crtc
) {
14938 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14939 encoder
->base
.base
.id
,
14940 encoder
->base
.name
);
14941 encoder
->disable(encoder
);
14942 if (encoder
->post_disable
)
14943 encoder
->post_disable(encoder
);
14945 encoder
->base
.crtc
= NULL
;
14946 encoder
->connectors_active
= false;
14948 /* Inconsistent output/port/pipe state happens presumably due to
14949 * a bug in one of the get_hw_state functions. Or someplace else
14950 * in our code, like the register restore mess on resume. Clamp
14951 * things to off as a safer default. */
14952 for_each_intel_connector(dev
, connector
) {
14953 if (connector
->encoder
!= encoder
)
14955 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14956 connector
->base
.encoder
= NULL
;
14959 /* Enabled encoders without active connectors will be fixed in
14960 * the crtc fixup. */
14963 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14966 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14968 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14969 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14970 i915_disable_vga(dev
);
14974 void i915_redisable_vga(struct drm_device
*dev
)
14976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14978 /* This function can be called both from intel_modeset_setup_hw_state or
14979 * at a very early point in our resume sequence, where the power well
14980 * structures are not yet restored. Since this function is at a very
14981 * paranoid "someone might have enabled VGA while we were not looking"
14982 * level, just check if the power well is enabled instead of trying to
14983 * follow the "don't touch the power well if we don't need it" policy
14984 * the rest of the driver uses. */
14985 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14988 i915_redisable_vga_power_on(dev
);
14991 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14993 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14998 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
15001 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15005 struct intel_crtc
*crtc
;
15006 struct intel_encoder
*encoder
;
15007 struct intel_connector
*connector
;
15010 for_each_intel_crtc(dev
, crtc
) {
15011 struct drm_plane
*primary
= crtc
->base
.primary
;
15012 struct intel_plane_state
*plane_state
;
15014 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15016 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
15018 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15021 crtc
->base
.state
->enable
= crtc
->active
;
15022 crtc
->base
.state
->active
= crtc
->active
;
15023 crtc
->base
.enabled
= crtc
->active
;
15025 plane_state
= to_intel_plane_state(primary
->state
);
15026 plane_state
->visible
= primary_get_hw_state(crtc
);
15028 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15029 crtc
->base
.base
.id
,
15030 crtc
->active
? "enabled" : "disabled");
15033 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15034 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15036 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15037 &pll
->config
.hw_state
);
15039 pll
->config
.crtc_mask
= 0;
15040 for_each_intel_crtc(dev
, crtc
) {
15041 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15043 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15047 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15048 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15050 if (pll
->config
.crtc_mask
)
15051 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15054 for_each_intel_encoder(dev
, encoder
) {
15057 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15058 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15059 encoder
->base
.crtc
= &crtc
->base
;
15060 encoder
->get_config(encoder
, crtc
->config
);
15062 encoder
->base
.crtc
= NULL
;
15065 encoder
->connectors_active
= false;
15066 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15067 encoder
->base
.base
.id
,
15068 encoder
->base
.name
,
15069 encoder
->base
.crtc
? "enabled" : "disabled",
15073 for_each_intel_connector(dev
, connector
) {
15074 if (connector
->get_hw_state(connector
)) {
15075 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15076 connector
->encoder
->connectors_active
= true;
15077 connector
->base
.encoder
= &connector
->encoder
->base
;
15079 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15080 connector
->base
.encoder
= NULL
;
15082 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15083 connector
->base
.base
.id
,
15084 connector
->base
.name
,
15085 connector
->base
.encoder
? "enabled" : "disabled");
15089 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15090 * and i915 state tracking structures. */
15091 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
15092 bool force_restore
)
15094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15096 struct intel_crtc
*crtc
;
15097 struct intel_encoder
*encoder
;
15100 intel_modeset_readout_hw_state(dev
);
15103 * Now that we have the config, copy it to each CRTC struct
15104 * Note that this could go away if we move to using crtc_config
15105 * checking everywhere.
15107 for_each_intel_crtc(dev
, crtc
) {
15108 if (crtc
->active
&& i915
.fastboot
) {
15109 intel_mode_from_pipe_config(&crtc
->base
.mode
,
15111 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15112 crtc
->base
.base
.id
);
15113 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
15117 /* HW state is read out, now we need to sanitize this mess. */
15118 for_each_intel_encoder(dev
, encoder
) {
15119 intel_sanitize_encoder(encoder
);
15122 for_each_pipe(dev_priv
, pipe
) {
15123 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15124 intel_sanitize_crtc(crtc
);
15125 intel_dump_pipe_config(crtc
, crtc
->config
,
15126 "[setup_hw_state]");
15129 intel_modeset_update_connector_atomic_state(dev
);
15131 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15132 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15134 if (!pll
->on
|| pll
->active
)
15137 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15139 pll
->disable(dev_priv
, pll
);
15144 skl_wm_get_hw_state(dev
);
15145 else if (HAS_PCH_SPLIT(dev
))
15146 ilk_wm_get_hw_state(dev
);
15148 if (force_restore
) {
15149 i915_redisable_vga(dev
);
15152 * We need to use raw interfaces for restoring state to avoid
15153 * checking (bogus) intermediate states.
15155 for_each_pipe(dev_priv
, pipe
) {
15156 struct drm_crtc
*crtc
=
15157 dev_priv
->pipe_to_crtc_mapping
[pipe
];
15159 intel_crtc_restore_mode(crtc
);
15162 intel_modeset_update_staged_output_state(dev
);
15165 intel_modeset_check_state(dev
);
15168 void intel_modeset_gem_init(struct drm_device
*dev
)
15170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15171 struct drm_crtc
*c
;
15172 struct drm_i915_gem_object
*obj
;
15175 mutex_lock(&dev
->struct_mutex
);
15176 intel_init_gt_powersave(dev
);
15177 mutex_unlock(&dev
->struct_mutex
);
15180 * There may be no VBT; and if the BIOS enabled SSC we can
15181 * just keep using it to avoid unnecessary flicker. Whereas if the
15182 * BIOS isn't using it, don't assume it will work even if the VBT
15183 * indicates as much.
15185 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
15186 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15189 intel_modeset_init_hw(dev
);
15191 intel_setup_overlay(dev
);
15194 * Make sure any fbs we allocated at startup are properly
15195 * pinned & fenced. When we do the allocation it's too early
15198 for_each_crtc(dev
, c
) {
15199 obj
= intel_fb_obj(c
->primary
->fb
);
15203 mutex_lock(&dev
->struct_mutex
);
15204 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15208 mutex_unlock(&dev
->struct_mutex
);
15210 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15211 to_intel_crtc(c
)->pipe
);
15212 drm_framebuffer_unreference(c
->primary
->fb
);
15213 c
->primary
->fb
= NULL
;
15214 update_state_fb(c
->primary
);
15218 intel_backlight_register(dev
);
15221 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15223 struct drm_connector
*connector
= &intel_connector
->base
;
15225 intel_panel_destroy_backlight(connector
);
15226 drm_connector_unregister(connector
);
15229 void intel_modeset_cleanup(struct drm_device
*dev
)
15231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15232 struct drm_connector
*connector
;
15234 intel_disable_gt_powersave(dev
);
15236 intel_backlight_unregister(dev
);
15239 * Interrupts and polling as the first thing to avoid creating havoc.
15240 * Too much stuff here (turning of connectors, ...) would
15241 * experience fancy races otherwise.
15243 intel_irq_uninstall(dev_priv
);
15246 * Due to the hpd irq storm handling the hotplug work can re-arm the
15247 * poll handlers. Hence disable polling after hpd handling is shut down.
15249 drm_kms_helper_poll_fini(dev
);
15251 mutex_lock(&dev
->struct_mutex
);
15253 intel_unregister_dsm_handler();
15255 intel_fbc_disable(dev
);
15257 mutex_unlock(&dev
->struct_mutex
);
15259 /* flush any delayed tasks or pending work */
15260 flush_scheduled_work();
15262 /* destroy the backlight and sysfs files before encoders/connectors */
15263 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15264 struct intel_connector
*intel_connector
;
15266 intel_connector
= to_intel_connector(connector
);
15267 intel_connector
->unregister(intel_connector
);
15270 drm_mode_config_cleanup(dev
);
15272 intel_cleanup_overlay(dev
);
15274 mutex_lock(&dev
->struct_mutex
);
15275 intel_cleanup_gt_powersave(dev
);
15276 mutex_unlock(&dev
->struct_mutex
);
15280 * Return which encoder is currently attached for connector.
15282 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15284 return &intel_attached_encoder(connector
)->base
;
15287 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15288 struct intel_encoder
*encoder
)
15290 connector
->encoder
= encoder
;
15291 drm_mode_connector_attach_encoder(&connector
->base
,
15296 * set vga decode state - true == enable VGA decode
15298 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15301 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15304 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15305 DRM_ERROR("failed to read control word\n");
15309 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15313 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15315 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15317 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15318 DRM_ERROR("failed to write control word\n");
15325 struct intel_display_error_state
{
15327 u32 power_well_driver
;
15329 int num_transcoders
;
15331 struct intel_cursor_error_state
{
15336 } cursor
[I915_MAX_PIPES
];
15338 struct intel_pipe_error_state
{
15339 bool power_domain_on
;
15342 } pipe
[I915_MAX_PIPES
];
15344 struct intel_plane_error_state
{
15352 } plane
[I915_MAX_PIPES
];
15354 struct intel_transcoder_error_state
{
15355 bool power_domain_on
;
15356 enum transcoder cpu_transcoder
;
15369 struct intel_display_error_state
*
15370 intel_display_capture_error_state(struct drm_device
*dev
)
15372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15373 struct intel_display_error_state
*error
;
15374 int transcoders
[] = {
15382 if (INTEL_INFO(dev
)->num_pipes
== 0)
15385 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15389 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15390 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15392 for_each_pipe(dev_priv
, i
) {
15393 error
->pipe
[i
].power_domain_on
=
15394 __intel_display_power_is_enabled(dev_priv
,
15395 POWER_DOMAIN_PIPE(i
));
15396 if (!error
->pipe
[i
].power_domain_on
)
15399 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15400 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15401 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15403 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15404 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15405 if (INTEL_INFO(dev
)->gen
<= 3) {
15406 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15407 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15409 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15410 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15411 if (INTEL_INFO(dev
)->gen
>= 4) {
15412 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15413 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15416 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15418 if (HAS_GMCH_DISPLAY(dev
))
15419 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15422 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15423 if (HAS_DDI(dev_priv
->dev
))
15424 error
->num_transcoders
++; /* Account for eDP. */
15426 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15427 enum transcoder cpu_transcoder
= transcoders
[i
];
15429 error
->transcoder
[i
].power_domain_on
=
15430 __intel_display_power_is_enabled(dev_priv
,
15431 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15432 if (!error
->transcoder
[i
].power_domain_on
)
15435 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15437 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15438 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15439 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15440 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15441 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15442 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15443 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15449 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15452 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15453 struct drm_device
*dev
,
15454 struct intel_display_error_state
*error
)
15456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15462 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15463 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15464 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15465 error
->power_well_driver
);
15466 for_each_pipe(dev_priv
, i
) {
15467 err_printf(m
, "Pipe [%d]:\n", i
);
15468 err_printf(m
, " Power: %s\n",
15469 error
->pipe
[i
].power_domain_on
? "on" : "off");
15470 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15471 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15473 err_printf(m
, "Plane [%d]:\n", i
);
15474 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15475 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15476 if (INTEL_INFO(dev
)->gen
<= 3) {
15477 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15478 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15480 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15481 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15482 if (INTEL_INFO(dev
)->gen
>= 4) {
15483 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15484 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15487 err_printf(m
, "Cursor [%d]:\n", i
);
15488 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15489 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15490 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15493 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15494 err_printf(m
, "CPU transcoder: %c\n",
15495 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15496 err_printf(m
, " Power: %s\n",
15497 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15498 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15499 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15500 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15501 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15502 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15503 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15504 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15508 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15510 struct intel_crtc
*crtc
;
15512 for_each_intel_crtc(dev
, crtc
) {
15513 struct intel_unpin_work
*work
;
15515 spin_lock_irq(&dev
->event_lock
);
15517 work
= crtc
->unpin_work
;
15519 if (work
&& work
->event
&&
15520 work
->event
->base
.file_priv
== file
) {
15521 kfree(work
->event
);
15522 work
->event
= NULL
;
15525 spin_unlock_irq(&dev
->event_lock
);