2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats
[] = {
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats
[] = {
66 DRM_FORMAT_XRGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
70 static const uint64_t i9xx_format_modifiers
[] = {
71 I915_FORMAT_MOD_X_TILED
,
72 DRM_FORMAT_MOD_LINEAR
,
73 DRM_FORMAT_MOD_INVALID
76 static const uint32_t skl_primary_formats
[] = {
83 DRM_FORMAT_XRGB2101010
,
84 DRM_FORMAT_XBGR2101010
,
91 static const uint64_t skl_format_modifiers_noccs
[] = {
92 I915_FORMAT_MOD_Yf_TILED
,
93 I915_FORMAT_MOD_Y_TILED
,
94 I915_FORMAT_MOD_X_TILED
,
95 DRM_FORMAT_MOD_LINEAR
,
96 DRM_FORMAT_MOD_INVALID
99 static const uint64_t skl_format_modifiers_ccs
[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS
,
101 I915_FORMAT_MOD_Y_TILED_CCS
,
102 I915_FORMAT_MOD_Yf_TILED
,
103 I915_FORMAT_MOD_Y_TILED
,
104 I915_FORMAT_MOD_X_TILED
,
105 DRM_FORMAT_MOD_LINEAR
,
106 DRM_FORMAT_MOD_INVALID
110 static const uint32_t intel_cursor_formats
[] = {
114 static const uint64_t cursor_format_modifiers
[] = {
115 DRM_FORMAT_MOD_LINEAR
,
116 DRM_FORMAT_MOD_INVALID
119 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
120 struct intel_crtc_state
*pipe_config
);
121 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
122 struct intel_crtc_state
*pipe_config
);
124 static int intel_framebuffer_init(struct intel_framebuffer
*ifb
,
125 struct drm_i915_gem_object
*obj
,
126 struct drm_mode_fb_cmd2
*mode_cmd
);
127 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
128 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
129 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
131 struct intel_link_m_n
*m_n
,
132 struct intel_link_m_n
*m2_n2
);
133 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
134 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
135 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
136 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
137 const struct intel_crtc_state
*pipe_config
);
138 static void chv_prepare_pll(struct intel_crtc
*crtc
,
139 const struct intel_crtc_state
*pipe_config
);
140 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
141 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
142 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
143 struct intel_crtc_state
*crtc_state
);
144 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
145 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
146 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
147 static void intel_modeset_setup_hw_state(struct drm_device
*dev
,
148 struct drm_modeset_acquire_ctx
*ctx
);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
154 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
158 int p2_slow
, p2_fast
;
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
165 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv
->sb_lock
);
169 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
170 CCK_FUSE_HPLL_FREQ_MASK
;
171 mutex_unlock(&dev_priv
->sb_lock
);
173 return vco_freq
[hpll_freq
] * 1000;
176 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
177 const char *name
, u32 reg
, int ref_freq
)
182 mutex_lock(&dev_priv
->sb_lock
);
183 val
= vlv_cck_read(dev_priv
, reg
);
184 mutex_unlock(&dev_priv
->sb_lock
);
186 divider
= val
& CCK_FREQUENCY_VALUES
;
188 WARN((val
& CCK_FREQUENCY_STATUS
) !=
189 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
190 "%s change in progress\n", name
);
192 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
195 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
196 const char *name
, u32 reg
)
198 if (dev_priv
->hpll_freq
== 0)
199 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
201 return vlv_get_cck_clock(dev_priv
, name
, reg
,
202 dev_priv
->hpll_freq
);
205 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
207 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
210 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
211 CCK_CZ_CLOCK_CONTROL
);
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
216 static inline u32
/* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
218 const struct intel_crtc_state
*pipe_config
)
220 if (HAS_DDI(dev_priv
))
221 return pipe_config
->port_clock
; /* SPLL */
222 else if (IS_GEN5(dev_priv
))
223 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
228 static const struct intel_limit intel_limits_i8xx_dac
= {
229 .dot
= { .min
= 25000, .max
= 350000 },
230 .vco
= { .min
= 908000, .max
= 1512000 },
231 .n
= { .min
= 2, .max
= 16 },
232 .m
= { .min
= 96, .max
= 140 },
233 .m1
= { .min
= 18, .max
= 26 },
234 .m2
= { .min
= 6, .max
= 16 },
235 .p
= { .min
= 4, .max
= 128 },
236 .p1
= { .min
= 2, .max
= 33 },
237 .p2
= { .dot_limit
= 165000,
238 .p2_slow
= 4, .p2_fast
= 2 },
241 static const struct intel_limit intel_limits_i8xx_dvo
= {
242 .dot
= { .min
= 25000, .max
= 350000 },
243 .vco
= { .min
= 908000, .max
= 1512000 },
244 .n
= { .min
= 2, .max
= 16 },
245 .m
= { .min
= 96, .max
= 140 },
246 .m1
= { .min
= 18, .max
= 26 },
247 .m2
= { .min
= 6, .max
= 16 },
248 .p
= { .min
= 4, .max
= 128 },
249 .p1
= { .min
= 2, .max
= 33 },
250 .p2
= { .dot_limit
= 165000,
251 .p2_slow
= 4, .p2_fast
= 4 },
254 static const struct intel_limit intel_limits_i8xx_lvds
= {
255 .dot
= { .min
= 25000, .max
= 350000 },
256 .vco
= { .min
= 908000, .max
= 1512000 },
257 .n
= { .min
= 2, .max
= 16 },
258 .m
= { .min
= 96, .max
= 140 },
259 .m1
= { .min
= 18, .max
= 26 },
260 .m2
= { .min
= 6, .max
= 16 },
261 .p
= { .min
= 4, .max
= 128 },
262 .p1
= { .min
= 1, .max
= 6 },
263 .p2
= { .dot_limit
= 165000,
264 .p2_slow
= 14, .p2_fast
= 7 },
267 static const struct intel_limit intel_limits_i9xx_sdvo
= {
268 .dot
= { .min
= 20000, .max
= 400000 },
269 .vco
= { .min
= 1400000, .max
= 2800000 },
270 .n
= { .min
= 1, .max
= 6 },
271 .m
= { .min
= 70, .max
= 120 },
272 .m1
= { .min
= 8, .max
= 18 },
273 .m2
= { .min
= 3, .max
= 7 },
274 .p
= { .min
= 5, .max
= 80 },
275 .p1
= { .min
= 1, .max
= 8 },
276 .p2
= { .dot_limit
= 200000,
277 .p2_slow
= 10, .p2_fast
= 5 },
280 static const struct intel_limit intel_limits_i9xx_lvds
= {
281 .dot
= { .min
= 20000, .max
= 400000 },
282 .vco
= { .min
= 1400000, .max
= 2800000 },
283 .n
= { .min
= 1, .max
= 6 },
284 .m
= { .min
= 70, .max
= 120 },
285 .m1
= { .min
= 8, .max
= 18 },
286 .m2
= { .min
= 3, .max
= 7 },
287 .p
= { .min
= 7, .max
= 98 },
288 .p1
= { .min
= 1, .max
= 8 },
289 .p2
= { .dot_limit
= 112000,
290 .p2_slow
= 14, .p2_fast
= 7 },
294 static const struct intel_limit intel_limits_g4x_sdvo
= {
295 .dot
= { .min
= 25000, .max
= 270000 },
296 .vco
= { .min
= 1750000, .max
= 3500000},
297 .n
= { .min
= 1, .max
= 4 },
298 .m
= { .min
= 104, .max
= 138 },
299 .m1
= { .min
= 17, .max
= 23 },
300 .m2
= { .min
= 5, .max
= 11 },
301 .p
= { .min
= 10, .max
= 30 },
302 .p1
= { .min
= 1, .max
= 3},
303 .p2
= { .dot_limit
= 270000,
309 static const struct intel_limit intel_limits_g4x_hdmi
= {
310 .dot
= { .min
= 22000, .max
= 400000 },
311 .vco
= { .min
= 1750000, .max
= 3500000},
312 .n
= { .min
= 1, .max
= 4 },
313 .m
= { .min
= 104, .max
= 138 },
314 .m1
= { .min
= 16, .max
= 23 },
315 .m2
= { .min
= 5, .max
= 11 },
316 .p
= { .min
= 5, .max
= 80 },
317 .p1
= { .min
= 1, .max
= 8},
318 .p2
= { .dot_limit
= 165000,
319 .p2_slow
= 10, .p2_fast
= 5 },
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
323 .dot
= { .min
= 20000, .max
= 115000 },
324 .vco
= { .min
= 1750000, .max
= 3500000 },
325 .n
= { .min
= 1, .max
= 3 },
326 .m
= { .min
= 104, .max
= 138 },
327 .m1
= { .min
= 17, .max
= 23 },
328 .m2
= { .min
= 5, .max
= 11 },
329 .p
= { .min
= 28, .max
= 112 },
330 .p1
= { .min
= 2, .max
= 8 },
331 .p2
= { .dot_limit
= 0,
332 .p2_slow
= 14, .p2_fast
= 14
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
337 .dot
= { .min
= 80000, .max
= 224000 },
338 .vco
= { .min
= 1750000, .max
= 3500000 },
339 .n
= { .min
= 1, .max
= 3 },
340 .m
= { .min
= 104, .max
= 138 },
341 .m1
= { .min
= 17, .max
= 23 },
342 .m2
= { .min
= 5, .max
= 11 },
343 .p
= { .min
= 14, .max
= 42 },
344 .p1
= { .min
= 2, .max
= 6 },
345 .p2
= { .dot_limit
= 0,
346 .p2_slow
= 7, .p2_fast
= 7
350 static const struct intel_limit intel_limits_pineview_sdvo
= {
351 .dot
= { .min
= 20000, .max
= 400000},
352 .vco
= { .min
= 1700000, .max
= 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n
= { .min
= 3, .max
= 6 },
355 .m
= { .min
= 2, .max
= 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1
= { .min
= 0, .max
= 0 },
358 .m2
= { .min
= 0, .max
= 254 },
359 .p
= { .min
= 5, .max
= 80 },
360 .p1
= { .min
= 1, .max
= 8 },
361 .p2
= { .dot_limit
= 200000,
362 .p2_slow
= 10, .p2_fast
= 5 },
365 static const struct intel_limit intel_limits_pineview_lvds
= {
366 .dot
= { .min
= 20000, .max
= 400000 },
367 .vco
= { .min
= 1700000, .max
= 3500000 },
368 .n
= { .min
= 3, .max
= 6 },
369 .m
= { .min
= 2, .max
= 256 },
370 .m1
= { .min
= 0, .max
= 0 },
371 .m2
= { .min
= 0, .max
= 254 },
372 .p
= { .min
= 7, .max
= 112 },
373 .p1
= { .min
= 1, .max
= 8 },
374 .p2
= { .dot_limit
= 112000,
375 .p2_slow
= 14, .p2_fast
= 14 },
378 /* Ironlake / Sandybridge
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
383 static const struct intel_limit intel_limits_ironlake_dac
= {
384 .dot
= { .min
= 25000, .max
= 350000 },
385 .vco
= { .min
= 1760000, .max
= 3510000 },
386 .n
= { .min
= 1, .max
= 5 },
387 .m
= { .min
= 79, .max
= 127 },
388 .m1
= { .min
= 12, .max
= 22 },
389 .m2
= { .min
= 5, .max
= 9 },
390 .p
= { .min
= 5, .max
= 80 },
391 .p1
= { .min
= 1, .max
= 8 },
392 .p2
= { .dot_limit
= 225000,
393 .p2_slow
= 10, .p2_fast
= 5 },
396 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
397 .dot
= { .min
= 25000, .max
= 350000 },
398 .vco
= { .min
= 1760000, .max
= 3510000 },
399 .n
= { .min
= 1, .max
= 3 },
400 .m
= { .min
= 79, .max
= 118 },
401 .m1
= { .min
= 12, .max
= 22 },
402 .m2
= { .min
= 5, .max
= 9 },
403 .p
= { .min
= 28, .max
= 112 },
404 .p1
= { .min
= 2, .max
= 8 },
405 .p2
= { .dot_limit
= 225000,
406 .p2_slow
= 14, .p2_fast
= 14 },
409 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
410 .dot
= { .min
= 25000, .max
= 350000 },
411 .vco
= { .min
= 1760000, .max
= 3510000 },
412 .n
= { .min
= 1, .max
= 3 },
413 .m
= { .min
= 79, .max
= 127 },
414 .m1
= { .min
= 12, .max
= 22 },
415 .m2
= { .min
= 5, .max
= 9 },
416 .p
= { .min
= 14, .max
= 56 },
417 .p1
= { .min
= 2, .max
= 8 },
418 .p2
= { .dot_limit
= 225000,
419 .p2_slow
= 7, .p2_fast
= 7 },
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
424 .dot
= { .min
= 25000, .max
= 350000 },
425 .vco
= { .min
= 1760000, .max
= 3510000 },
426 .n
= { .min
= 1, .max
= 2 },
427 .m
= { .min
= 79, .max
= 126 },
428 .m1
= { .min
= 12, .max
= 22 },
429 .m2
= { .min
= 5, .max
= 9 },
430 .p
= { .min
= 28, .max
= 112 },
431 .p1
= { .min
= 2, .max
= 8 },
432 .p2
= { .dot_limit
= 225000,
433 .p2_slow
= 14, .p2_fast
= 14 },
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
437 .dot
= { .min
= 25000, .max
= 350000 },
438 .vco
= { .min
= 1760000, .max
= 3510000 },
439 .n
= { .min
= 1, .max
= 3 },
440 .m
= { .min
= 79, .max
= 126 },
441 .m1
= { .min
= 12, .max
= 22 },
442 .m2
= { .min
= 5, .max
= 9 },
443 .p
= { .min
= 14, .max
= 42 },
444 .p1
= { .min
= 2, .max
= 6 },
445 .p2
= { .dot_limit
= 225000,
446 .p2_slow
= 7, .p2_fast
= 7 },
449 static const struct intel_limit intel_limits_vlv
= {
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
456 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
457 .vco
= { .min
= 4000000, .max
= 6000000 },
458 .n
= { .min
= 1, .max
= 7 },
459 .m1
= { .min
= 2, .max
= 3 },
460 .m2
= { .min
= 11, .max
= 156 },
461 .p1
= { .min
= 2, .max
= 3 },
462 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
465 static const struct intel_limit intel_limits_chv
= {
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
472 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
473 .vco
= { .min
= 4800000, .max
= 6480000 },
474 .n
= { .min
= 1, .max
= 1 },
475 .m1
= { .min
= 2, .max
= 2 },
476 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
477 .p1
= { .min
= 2, .max
= 4 },
478 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
481 static const struct intel_limit intel_limits_bxt
= {
482 /* FIXME: find real dot limits */
483 .dot
= { .min
= 0, .max
= INT_MAX
},
484 .vco
= { .min
= 4800000, .max
= 6700000 },
485 .n
= { .min
= 1, .max
= 1 },
486 .m1
= { .min
= 2, .max
= 2 },
487 /* FIXME: find real m2 limits */
488 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
489 .p1
= { .min
= 2, .max
= 4 },
490 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
494 needs_modeset(struct drm_crtc_state
*state
)
496 return drm_atomic_crtc_needs_modeset(state
);
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
510 clock
->m
= clock
->m2
+ 2;
511 clock
->p
= clock
->p1
* clock
->p2
;
512 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
514 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
515 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
520 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
522 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
525 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
527 clock
->m
= i9xx_dpll_compute_m(clock
);
528 clock
->p
= clock
->p1
* clock
->p2
;
529 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
531 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
532 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
537 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
539 clock
->m
= clock
->m1
* clock
->m2
;
540 clock
->p
= clock
->p1
* clock
->p2
;
541 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
543 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
544 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
546 return clock
->dot
/ 5;
549 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
551 clock
->m
= clock
->m1
* clock
->m2
;
552 clock
->p
= clock
->p1
* clock
->p2
;
553 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
555 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
557 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
559 return clock
->dot
/ 5;
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
568 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
569 const struct intel_limit
*limit
,
570 const struct dpll
*clock
)
572 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
573 INTELPllInvalid("n out of range\n");
574 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
579 INTELPllInvalid("m1 out of range\n");
581 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
582 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
583 if (clock
->m1
<= clock
->m2
)
584 INTELPllInvalid("m1 <= m2\n");
586 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
587 !IS_GEN9_LP(dev_priv
)) {
588 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
589 INTELPllInvalid("p out of range\n");
590 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
591 INTELPllInvalid("m out of range\n");
594 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
599 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
600 INTELPllInvalid("dot out of range\n");
606 i9xx_select_p2_div(const struct intel_limit
*limit
,
607 const struct intel_crtc_state
*crtc_state
,
610 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
612 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
618 if (intel_is_dual_link_lvds(dev
))
619 return limit
->p2
.p2_fast
;
621 return limit
->p2
.p2_slow
;
623 if (target
< limit
->p2
.dot_limit
)
624 return limit
->p2
.p2_slow
;
626 return limit
->p2
.p2_fast
;
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
635 * Target and reference clocks are specified in kHz.
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
641 i9xx_find_best_dpll(const struct intel_limit
*limit
,
642 struct intel_crtc_state
*crtc_state
,
643 int target
, int refclk
, struct dpll
*match_clock
,
644 struct dpll
*best_clock
)
646 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
650 memset(best_clock
, 0, sizeof(*best_clock
));
652 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
654 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
656 for (clock
.m2
= limit
->m2
.min
;
657 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
658 if (clock
.m2
>= clock
.m1
)
660 for (clock
.n
= limit
->n
.min
;
661 clock
.n
<= limit
->n
.max
; clock
.n
++) {
662 for (clock
.p1
= limit
->p1
.min
;
663 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
666 i9xx_calc_dpll_params(refclk
, &clock
);
667 if (!intel_PLL_is_valid(to_i915(dev
),
672 clock
.p
!= match_clock
->p
)
675 this_err
= abs(clock
.dot
- target
);
676 if (this_err
< err
) {
685 return (err
!= target
);
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
693 * Target and reference clocks are specified in kHz.
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
699 pnv_find_best_dpll(const struct intel_limit
*limit
,
700 struct intel_crtc_state
*crtc_state
,
701 int target
, int refclk
, struct dpll
*match_clock
,
702 struct dpll
*best_clock
)
704 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
708 memset(best_clock
, 0, sizeof(*best_clock
));
710 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
712 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
714 for (clock
.m2
= limit
->m2
.min
;
715 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
716 for (clock
.n
= limit
->n
.min
;
717 clock
.n
<= limit
->n
.max
; clock
.n
++) {
718 for (clock
.p1
= limit
->p1
.min
;
719 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
722 pnv_calc_dpll_params(refclk
, &clock
);
723 if (!intel_PLL_is_valid(to_i915(dev
),
728 clock
.p
!= match_clock
->p
)
731 this_err
= abs(clock
.dot
- target
);
732 if (this_err
< err
) {
741 return (err
!= target
);
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
749 * Target and reference clocks are specified in kHz.
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
755 g4x_find_best_dpll(const struct intel_limit
*limit
,
756 struct intel_crtc_state
*crtc_state
,
757 int target
, int refclk
, struct dpll
*match_clock
,
758 struct dpll
*best_clock
)
760 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
764 /* approximately equals target * 0.00585 */
765 int err_most
= (target
>> 8) + (target
>> 9);
767 memset(best_clock
, 0, sizeof(*best_clock
));
769 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
771 max_n
= limit
->n
.max
;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock
.m1
= limit
->m1
.max
;
776 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
777 for (clock
.m2
= limit
->m2
.max
;
778 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
779 for (clock
.p1
= limit
->p1
.max
;
780 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
783 i9xx_calc_dpll_params(refclk
, &clock
);
784 if (!intel_PLL_is_valid(to_i915(dev
),
789 this_err
= abs(clock
.dot
- target
);
790 if (this_err
< err_most
) {
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
807 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
808 const struct dpll
*calculated_clock
,
809 const struct dpll
*best_clock
,
810 unsigned int best_error_ppm
,
811 unsigned int *error_ppm
)
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
817 if (IS_CHERRYVIEW(to_i915(dev
))) {
820 return calculated_clock
->p
> best_clock
->p
;
823 if (WARN_ON_ONCE(!target_freq
))
826 *error_ppm
= div_u64(1000000ULL *
827 abs(target_freq
- calculated_clock
->dot
),
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
834 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
840 return *error_ppm
+ 10 < best_error_ppm
;
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
849 vlv_find_best_dpll(const struct intel_limit
*limit
,
850 struct intel_crtc_state
*crtc_state
,
851 int target
, int refclk
, struct dpll
*match_clock
,
852 struct dpll
*best_clock
)
854 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
855 struct drm_device
*dev
= crtc
->base
.dev
;
857 unsigned int bestppm
= 1000000;
858 /* min update 19.2 MHz */
859 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
862 target
*= 5; /* fast clock */
864 memset(best_clock
, 0, sizeof(*best_clock
));
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
868 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
869 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
870 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
871 clock
.p
= clock
.p1
* clock
.p2
;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
876 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
879 vlv_calc_dpll_params(refclk
, &clock
);
881 if (!intel_PLL_is_valid(to_i915(dev
),
886 if (!vlv_PLL_is_optimal(dev
, target
,
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
909 chv_find_best_dpll(const struct intel_limit
*limit
,
910 struct intel_crtc_state
*crtc_state
,
911 int target
, int refclk
, struct dpll
*match_clock
,
912 struct dpll
*best_clock
)
914 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
915 struct drm_device
*dev
= crtc
->base
.dev
;
916 unsigned int best_error_ppm
;
921 memset(best_clock
, 0, sizeof(*best_clock
));
922 best_error_ppm
= 1000000;
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
929 clock
.n
= 1, clock
.m1
= 2;
930 target
*= 5; /* fast clock */
932 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
933 for (clock
.p2
= limit
->p2
.p2_fast
;
934 clock
.p2
>= limit
->p2
.p2_slow
;
935 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
936 unsigned int error_ppm
;
938 clock
.p
= clock
.p1
* clock
.p2
;
940 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
941 clock
.n
) << 22, refclk
* clock
.m1
);
943 if (m2
> INT_MAX
/clock
.m1
)
948 chv_calc_dpll_params(refclk
, &clock
);
950 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
953 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
954 best_error_ppm
, &error_ppm
))
958 best_error_ppm
= error_ppm
;
966 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
967 struct dpll
*best_clock
)
970 const struct intel_limit
*limit
= &intel_limits_bxt
;
972 return chv_find_best_dpll(limit
, crtc_state
,
973 target_clock
, refclk
, NULL
, best_clock
);
976 bool intel_crtc_active(struct intel_crtc
*crtc
)
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
991 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
992 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
995 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
998 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1000 return crtc
->config
->cpu_transcoder
;
1003 static bool pipe_dsl_stopped(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1005 i915_reg_t reg
= PIPEDSL(pipe
);
1009 if (IS_GEN2(dev_priv
))
1010 line_mask
= DSL_LINEMASK_GEN2
;
1012 line_mask
= DSL_LINEMASK_GEN3
;
1014 line1
= I915_READ(reg
) & line_mask
;
1016 line2
= I915_READ(reg
) & line_mask
;
1018 return line1
== line2
;
1022 * intel_wait_for_pipe_off - wait for pipe to turn off
1023 * @crtc: crtc whose pipe to wait for
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1029 * On Gen4 and above:
1030 * wait for the pipe register state bit to turn off
1033 * wait for the display line value to settle (it usually
1034 * ends up stopping at the start of the next frame).
1037 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1039 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1040 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1041 enum pipe pipe
= crtc
->pipe
;
1043 if (INTEL_GEN(dev_priv
) >= 4) {
1044 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1046 /* Wait for the Pipe State to go off */
1047 if (intel_wait_for_register(dev_priv
,
1048 reg
, I965_PIPECONF_ACTIVE
, 0,
1050 WARN(1, "pipe_off wait timed out\n");
1052 /* Wait for the display line to settle */
1053 if (wait_for(pipe_dsl_stopped(dev_priv
, pipe
), 100))
1054 WARN(1, "pipe_off wait timed out\n");
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private
*dev_priv
,
1060 enum pipe pipe
, bool state
)
1065 val
= I915_READ(DPLL(pipe
));
1066 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1067 I915_STATE_WARN(cur_state
!= state
,
1068 "PLL state assertion failure (expected %s, current %s)\n",
1069 onoff(state
), onoff(cur_state
));
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1078 mutex_lock(&dev_priv
->sb_lock
);
1079 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1080 mutex_unlock(&dev_priv
->sb_lock
);
1082 cur_state
= val
& DSI_PLL_VCO_EN
;
1083 I915_STATE_WARN(cur_state
!= state
,
1084 "DSI PLL state assertion failure (expected %s, current %s)\n",
1085 onoff(state
), onoff(cur_state
));
1088 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1089 enum pipe pipe
, bool state
)
1092 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1095 if (HAS_DDI(dev_priv
)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1098 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1100 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1101 cur_state
= !!(val
& FDI_TX_ENABLE
);
1103 I915_STATE_WARN(cur_state
!= state
,
1104 "FDI TX state assertion failure (expected %s, current %s)\n",
1105 onoff(state
), onoff(cur_state
));
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1110 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1111 enum pipe pipe
, bool state
)
1116 val
= I915_READ(FDI_RX_CTL(pipe
));
1117 cur_state
= !!(val
& FDI_RX_ENABLE
);
1118 I915_STATE_WARN(cur_state
!= state
,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 onoff(state
), onoff(cur_state
));
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1130 /* ILK FDI PLL is always enabled */
1131 if (IS_GEN5(dev_priv
))
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv
))
1138 val
= I915_READ(FDI_TX_CTL(pipe
));
1139 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1143 enum pipe pipe
, bool state
)
1148 val
= I915_READ(FDI_RX_CTL(pipe
));
1149 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1150 I915_STATE_WARN(cur_state
!= state
,
1151 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152 onoff(state
), onoff(cur_state
));
1155 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1159 enum pipe panel_pipe
= PIPE_A
;
1162 if (WARN_ON(HAS_DDI(dev_priv
)))
1165 if (HAS_PCH_SPLIT(dev_priv
)) {
1168 pp_reg
= PP_CONTROL(0);
1169 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1171 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1172 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1173 panel_pipe
= PIPE_B
;
1174 /* XXX: else fix for eDP */
1175 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1176 /* presumably write lock depends on pipe, not port select */
1177 pp_reg
= PP_CONTROL(pipe
);
1180 pp_reg
= PP_CONTROL(0);
1181 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1182 panel_pipe
= PIPE_B
;
1185 val
= I915_READ(pp_reg
);
1186 if (!(val
& PANEL_POWER_ON
) ||
1187 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1190 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1191 "panel assertion failure, pipe %c regs locked\n",
1195 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1196 enum pipe pipe
, bool state
)
1200 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
1201 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1203 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1205 I915_STATE_WARN(cur_state
!= state
,
1206 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1212 void assert_pipe(struct drm_i915_private
*dev_priv
,
1213 enum pipe pipe
, bool state
)
1216 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1218 enum intel_display_power_domain power_domain
;
1220 /* we keep both pipes enabled on 830 */
1221 if (IS_I830(dev_priv
))
1224 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1225 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1226 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1227 cur_state
= !!(val
& PIPECONF_ENABLE
);
1229 intel_display_power_put(dev_priv
, power_domain
);
1234 I915_STATE_WARN(cur_state
!= state
,
1235 "pipe %c assertion failure (expected %s, current %s)\n",
1236 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1239 static void assert_plane(struct drm_i915_private
*dev_priv
,
1240 enum plane plane
, bool state
)
1245 val
= I915_READ(DSPCNTR(plane
));
1246 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1247 I915_STATE_WARN(cur_state
!= state
,
1248 "plane %c assertion failure (expected %s, current %s)\n",
1249 plane_name(plane
), onoff(state
), onoff(cur_state
));
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1255 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1260 /* Primary planes are fixed to pipes on gen4+ */
1261 if (INTEL_GEN(dev_priv
) >= 4) {
1262 u32 val
= I915_READ(DSPCNTR(pipe
));
1263 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1264 "plane %c assertion failure, should be disabled but not\n",
1269 /* Need to check both planes against the pipe */
1270 for_each_pipe(dev_priv
, i
) {
1271 u32 val
= I915_READ(DSPCNTR(i
));
1272 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1273 DISPPLANE_SEL_PIPE_SHIFT
;
1274 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1275 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276 plane_name(i
), pipe_name(pipe
));
1280 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1285 if (INTEL_GEN(dev_priv
) >= 9) {
1286 for_each_sprite(dev_priv
, pipe
, sprite
) {
1287 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1288 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1289 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290 sprite
, pipe_name(pipe
));
1292 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1293 for_each_sprite(dev_priv
, pipe
, sprite
) {
1294 u32 val
= I915_READ(SPCNTR(pipe
, PLANE_SPRITE0
+ sprite
));
1295 I915_STATE_WARN(val
& SP_ENABLE
,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1299 } else if (INTEL_GEN(dev_priv
) >= 7) {
1300 u32 val
= I915_READ(SPRCTL(pipe
));
1301 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe
), pipe_name(pipe
));
1304 } else if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
)) {
1305 u32 val
= I915_READ(DVSCNTR(pipe
));
1306 I915_STATE_WARN(val
& DVS_ENABLE
,
1307 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308 plane_name(pipe
), pipe_name(pipe
));
1312 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1314 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1315 drm_crtc_vblank_put(crtc
);
1318 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1324 val
= I915_READ(PCH_TRANSCONF(pipe
));
1325 enabled
= !!(val
& TRANS_ENABLE
);
1326 I915_STATE_WARN(enabled
,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1332 enum pipe pipe
, u32 port_sel
, u32 val
)
1334 if ((val
& DP_PORT_EN
) == 0)
1337 if (HAS_PCH_CPT(dev_priv
)) {
1338 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1339 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1341 } else if (IS_CHERRYVIEW(dev_priv
)) {
1342 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1345 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1351 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1352 enum pipe pipe
, u32 val
)
1354 if ((val
& SDVO_ENABLE
) == 0)
1357 if (HAS_PCH_CPT(dev_priv
)) {
1358 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1360 } else if (IS_CHERRYVIEW(dev_priv
)) {
1361 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1364 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1370 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1371 enum pipe pipe
, u32 val
)
1373 if ((val
& LVDS_PORT_EN
) == 0)
1376 if (HAS_PCH_CPT(dev_priv
)) {
1377 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1380 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1386 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1387 enum pipe pipe
, u32 val
)
1389 if ((val
& ADPA_DAC_ENABLE
) == 0)
1391 if (HAS_PCH_CPT(dev_priv
)) {
1392 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1395 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1401 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1402 enum pipe pipe
, i915_reg_t reg
,
1405 u32 val
= I915_READ(reg
);
1406 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1407 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1410 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1411 && (val
& DP_PIPEB_SELECT
),
1412 "IBX PCH dp port still using transcoder B\n");
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1416 enum pipe pipe
, i915_reg_t reg
)
1418 u32 val
= I915_READ(reg
);
1419 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1420 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1423 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1424 && (val
& SDVO_PIPE_B_SELECT
),
1425 "IBX PCH hdmi port still using transcoder B\n");
1428 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1433 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1434 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1435 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1437 val
= I915_READ(PCH_ADPA
);
1438 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1442 val
= I915_READ(PCH_LVDS
);
1443 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1444 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1447 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1448 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1449 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1452 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1453 const struct intel_crtc_state
*pipe_config
)
1455 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1456 enum pipe pipe
= crtc
->pipe
;
1458 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1459 POSTING_READ(DPLL(pipe
));
1462 if (intel_wait_for_register(dev_priv
,
1467 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1470 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1471 const struct intel_crtc_state
*pipe_config
)
1473 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1474 enum pipe pipe
= crtc
->pipe
;
1476 assert_pipe_disabled(dev_priv
, pipe
);
1478 /* PLL is protected by panel, make sure we can write it */
1479 assert_panel_unlocked(dev_priv
, pipe
);
1481 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1482 _vlv_enable_pll(crtc
, pipe_config
);
1484 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1485 POSTING_READ(DPLL_MD(pipe
));
1489 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1490 const struct intel_crtc_state
*pipe_config
)
1492 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1493 enum pipe pipe
= crtc
->pipe
;
1494 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1497 mutex_lock(&dev_priv
->sb_lock
);
1499 /* Enable back the 10bit clock to display controller */
1500 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1501 tmp
|= DPIO_DCLKP_EN
;
1502 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1504 mutex_unlock(&dev_priv
->sb_lock
);
1507 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1512 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1514 /* Check PLL is locked */
1515 if (intel_wait_for_register(dev_priv
,
1516 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1518 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1521 static void chv_enable_pll(struct intel_crtc
*crtc
,
1522 const struct intel_crtc_state
*pipe_config
)
1524 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1525 enum pipe pipe
= crtc
->pipe
;
1527 assert_pipe_disabled(dev_priv
, pipe
);
1529 /* PLL is protected by panel, make sure we can write it */
1530 assert_panel_unlocked(dev_priv
, pipe
);
1532 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1533 _chv_enable_pll(crtc
, pipe_config
);
1535 if (pipe
!= PIPE_A
) {
1537 * WaPixelRepeatModeFixForC0:chv
1539 * DPLLCMD is AWOL. Use chicken bits to propagate
1540 * the value from DPLLBMD to either pipe B or C.
1542 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1543 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1544 I915_WRITE(CBR4_VLV
, 0);
1545 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1548 * DPLLB VGA mode also seems to cause problems.
1549 * We should always have it disabled.
1551 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1553 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1554 POSTING_READ(DPLL_MD(pipe
));
1558 static int intel_num_dvo_pipes(struct drm_i915_private
*dev_priv
)
1560 struct intel_crtc
*crtc
;
1563 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1564 count
+= crtc
->base
.state
->active
&&
1565 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
);
1571 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1573 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1574 i915_reg_t reg
= DPLL(crtc
->pipe
);
1575 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1578 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1580 /* PLL is protected by panel, make sure we can write it */
1581 if (IS_MOBILE(dev_priv
) && !IS_I830(dev_priv
))
1582 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1584 /* Enable DVO 2x clock on both PLLs if necessary */
1585 if (IS_I830(dev_priv
) && intel_num_dvo_pipes(dev_priv
) > 0) {
1587 * It appears to be important that we don't enable this
1588 * for the current pipe before otherwise configuring the
1589 * PLL. No idea how this should be handled if multiple
1590 * DVO outputs are enabled simultaneosly.
1592 dpll
|= DPLL_DVO_2X_MODE
;
1593 I915_WRITE(DPLL(!crtc
->pipe
),
1594 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1598 * Apparently we need to have VGA mode enabled prior to changing
1599 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1600 * dividers, even though the register value does change.
1604 I915_WRITE(reg
, dpll
);
1606 /* Wait for the clocks to stabilize. */
1610 if (INTEL_GEN(dev_priv
) >= 4) {
1611 I915_WRITE(DPLL_MD(crtc
->pipe
),
1612 crtc
->config
->dpll_hw_state
.dpll_md
);
1614 /* The pixel multiplier can only be updated once the
1615 * DPLL is enabled and the clocks are stable.
1617 * So write it again.
1619 I915_WRITE(reg
, dpll
);
1622 /* We do this three times for luck */
1623 for (i
= 0; i
< 3; i
++) {
1624 I915_WRITE(reg
, dpll
);
1626 udelay(150); /* wait for warmup */
1631 * i9xx_disable_pll - disable a PLL
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe PLL to disable
1635 * Disable the PLL for @pipe, making sure the pipe is off first.
1637 * Note! This is for pre-ILK only.
1639 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1641 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1642 enum pipe pipe
= crtc
->pipe
;
1644 /* Disable DVO 2x clock on both PLLs if necessary */
1645 if (IS_I830(dev_priv
) &&
1646 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
) &&
1647 !intel_num_dvo_pipes(dev_priv
)) {
1648 I915_WRITE(DPLL(PIPE_B
),
1649 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1650 I915_WRITE(DPLL(PIPE_A
),
1651 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1654 /* Don't disable pipe or pipe PLLs if needed */
1655 if (IS_I830(dev_priv
))
1658 /* Make sure the pipe isn't still relying on us */
1659 assert_pipe_disabled(dev_priv
, pipe
);
1661 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1662 POSTING_READ(DPLL(pipe
));
1665 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv
, pipe
);
1672 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1673 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1675 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1677 I915_WRITE(DPLL(pipe
), val
);
1678 POSTING_READ(DPLL(pipe
));
1681 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1683 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv
, pipe
);
1689 val
= DPLL_SSC_REF_CLK_CHV
|
1690 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1692 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1694 I915_WRITE(DPLL(pipe
), val
);
1695 POSTING_READ(DPLL(pipe
));
1697 mutex_lock(&dev_priv
->sb_lock
);
1699 /* Disable 10bit clock to display controller */
1700 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1701 val
&= ~DPIO_DCLKP_EN
;
1702 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1704 mutex_unlock(&dev_priv
->sb_lock
);
1707 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1708 struct intel_digital_port
*dport
,
1709 unsigned int expected_mask
)
1712 i915_reg_t dpll_reg
;
1714 switch (dport
->port
) {
1716 port_mask
= DPLL_PORTB_READY_MASK
;
1720 port_mask
= DPLL_PORTC_READY_MASK
;
1722 expected_mask
<<= 4;
1725 port_mask
= DPLL_PORTD_READY_MASK
;
1726 dpll_reg
= DPIO_PHY_STATUS
;
1732 if (intel_wait_for_register(dev_priv
,
1733 dpll_reg
, port_mask
, expected_mask
,
1735 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1736 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1739 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1742 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
1745 uint32_t val
, pipeconf_val
;
1747 /* Make sure PCH DPLL is enabled */
1748 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1750 /* FDI must be feeding us bits for PCH ports */
1751 assert_fdi_tx_enabled(dev_priv
, pipe
);
1752 assert_fdi_rx_enabled(dev_priv
, pipe
);
1754 if (HAS_PCH_CPT(dev_priv
)) {
1755 /* Workaround: Set the timing override bit before enabling the
1756 * pch transcoder. */
1757 reg
= TRANS_CHICKEN2(pipe
);
1758 val
= I915_READ(reg
);
1759 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1760 I915_WRITE(reg
, val
);
1763 reg
= PCH_TRANSCONF(pipe
);
1764 val
= I915_READ(reg
);
1765 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1767 if (HAS_PCH_IBX(dev_priv
)) {
1769 * Make the BPC in transcoder be consistent with
1770 * that in pipeconf reg. For HDMI we must use 8bpc
1771 * here for both 8bpc and 12bpc.
1773 val
&= ~PIPECONF_BPC_MASK
;
1774 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_HDMI
))
1775 val
|= PIPECONF_8BPC
;
1777 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1780 val
&= ~TRANS_INTERLACE_MASK
;
1781 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1782 if (HAS_PCH_IBX(dev_priv
) &&
1783 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
1784 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1786 val
|= TRANS_INTERLACED
;
1788 val
|= TRANS_PROGRESSIVE
;
1790 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1791 if (intel_wait_for_register(dev_priv
,
1792 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1794 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1797 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1798 enum transcoder cpu_transcoder
)
1800 u32 val
, pipeconf_val
;
1802 /* FDI must be feeding us bits for PCH ports */
1803 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1804 assert_fdi_rx_enabled(dev_priv
, PIPE_A
);
1806 /* Workaround: set timing override bit. */
1807 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1808 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1809 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1812 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1814 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1815 PIPECONF_INTERLACED_ILK
)
1816 val
|= TRANS_INTERLACED
;
1818 val
|= TRANS_PROGRESSIVE
;
1820 I915_WRITE(LPT_TRANSCONF
, val
);
1821 if (intel_wait_for_register(dev_priv
,
1826 DRM_ERROR("Failed to enable PCH transcoder\n");
1829 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1835 /* FDI relies on the transcoder */
1836 assert_fdi_tx_disabled(dev_priv
, pipe
);
1837 assert_fdi_rx_disabled(dev_priv
, pipe
);
1839 /* Ports must be off as well */
1840 assert_pch_ports_disabled(dev_priv
, pipe
);
1842 reg
= PCH_TRANSCONF(pipe
);
1843 val
= I915_READ(reg
);
1844 val
&= ~TRANS_ENABLE
;
1845 I915_WRITE(reg
, val
);
1846 /* wait for PCH transcoder off, transcoder state */
1847 if (intel_wait_for_register(dev_priv
,
1848 reg
, TRANS_STATE_ENABLE
, 0,
1850 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1852 if (HAS_PCH_CPT(dev_priv
)) {
1853 /* Workaround: Clear the timing override chicken bit again. */
1854 reg
= TRANS_CHICKEN2(pipe
);
1855 val
= I915_READ(reg
);
1856 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1857 I915_WRITE(reg
, val
);
1861 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1865 val
= I915_READ(LPT_TRANSCONF
);
1866 val
&= ~TRANS_ENABLE
;
1867 I915_WRITE(LPT_TRANSCONF
, val
);
1868 /* wait for PCH transcoder off, transcoder state */
1869 if (intel_wait_for_register(dev_priv
,
1870 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1872 DRM_ERROR("Failed to disable PCH transcoder\n");
1874 /* Workaround: clear timing override bit. */
1875 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1876 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1877 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1880 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1882 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1884 WARN_ON(!crtc
->config
->has_pch_encoder
);
1886 if (HAS_PCH_LPT(dev_priv
))
1893 * intel_enable_pipe - enable a pipe, asserting requirements
1894 * @crtc: crtc responsible for the pipe
1896 * Enable @crtc's pipe, making sure that various hardware specific requirements
1897 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1899 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1901 struct drm_device
*dev
= crtc
->base
.dev
;
1902 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1903 enum pipe pipe
= crtc
->pipe
;
1904 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1908 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1910 assert_planes_disabled(dev_priv
, pipe
);
1911 assert_cursor_disabled(dev_priv
, pipe
);
1912 assert_sprites_disabled(dev_priv
, pipe
);
1915 * A pipe without a PLL won't actually be able to drive bits from
1916 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1919 if (HAS_GMCH_DISPLAY(dev_priv
)) {
1920 if (intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DSI
))
1921 assert_dsi_pll_enabled(dev_priv
);
1923 assert_pll_enabled(dev_priv
, pipe
);
1925 if (crtc
->config
->has_pch_encoder
) {
1926 /* if driving the PCH, we need FDI enabled */
1927 assert_fdi_rx_pll_enabled(dev_priv
,
1928 intel_crtc_pch_transcoder(crtc
));
1929 assert_fdi_tx_pll_enabled(dev_priv
,
1930 (enum pipe
) cpu_transcoder
);
1932 /* FIXME: assert CPU port conditions for SNB+ */
1935 reg
= PIPECONF(cpu_transcoder
);
1936 val
= I915_READ(reg
);
1937 if (val
& PIPECONF_ENABLE
) {
1938 /* we keep both pipes enabled on 830 */
1939 WARN_ON(!IS_I830(dev_priv
));
1943 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1947 * Until the pipe starts DSL will read as 0, which would cause
1948 * an apparent vblank timestamp jump, which messes up also the
1949 * frame count when it's derived from the timestamps. So let's
1950 * wait for the pipe to start properly before we call
1951 * drm_crtc_vblank_on()
1953 if (dev
->max_vblank_count
== 0 &&
1954 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
1955 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
1959 * intel_disable_pipe - disable a pipe, asserting requirements
1960 * @crtc: crtc whose pipes is to be disabled
1962 * Disable the pipe of @crtc, making sure that various hardware
1963 * specific requirements are met, if applicable, e.g. plane
1964 * disabled, panel fitter off, etc.
1966 * Will wait until the pipe has shut down before returning.
1968 static void intel_disable_pipe(struct intel_crtc
*crtc
)
1970 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1971 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1972 enum pipe pipe
= crtc
->pipe
;
1976 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
1979 * Make sure planes won't keep trying to pump pixels to us,
1980 * or we might hang the display.
1982 assert_planes_disabled(dev_priv
, pipe
);
1983 assert_cursor_disabled(dev_priv
, pipe
);
1984 assert_sprites_disabled(dev_priv
, pipe
);
1986 reg
= PIPECONF(cpu_transcoder
);
1987 val
= I915_READ(reg
);
1988 if ((val
& PIPECONF_ENABLE
) == 0)
1992 * Double wide has implications for planes
1993 * so best keep it disabled when not needed.
1995 if (crtc
->config
->double_wide
)
1996 val
&= ~PIPECONF_DOUBLE_WIDE
;
1998 /* Don't disable pipe or pipe PLLs if needed */
1999 if (!IS_I830(dev_priv
))
2000 val
&= ~PIPECONF_ENABLE
;
2002 I915_WRITE(reg
, val
);
2003 if ((val
& PIPECONF_ENABLE
) == 0)
2004 intel_wait_for_pipe_off(crtc
);
2007 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2009 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2013 intel_tile_width_bytes(const struct drm_framebuffer
*fb
, int plane
)
2015 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2016 unsigned int cpp
= fb
->format
->cpp
[plane
];
2018 switch (fb
->modifier
) {
2019 case DRM_FORMAT_MOD_LINEAR
:
2021 case I915_FORMAT_MOD_X_TILED
:
2022 if (IS_GEN2(dev_priv
))
2026 case I915_FORMAT_MOD_Y_TILED_CCS
:
2030 case I915_FORMAT_MOD_Y_TILED
:
2031 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2035 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2039 case I915_FORMAT_MOD_Yf_TILED
:
2055 MISSING_CASE(fb
->modifier
);
2061 intel_tile_height(const struct drm_framebuffer
*fb
, int plane
)
2063 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
2066 return intel_tile_size(to_i915(fb
->dev
)) /
2067 intel_tile_width_bytes(fb
, plane
);
2070 /* Return the tile dimensions in pixel units */
2071 static void intel_tile_dims(const struct drm_framebuffer
*fb
, int plane
,
2072 unsigned int *tile_width
,
2073 unsigned int *tile_height
)
2075 unsigned int tile_width_bytes
= intel_tile_width_bytes(fb
, plane
);
2076 unsigned int cpp
= fb
->format
->cpp
[plane
];
2078 *tile_width
= tile_width_bytes
/ cpp
;
2079 *tile_height
= intel_tile_size(to_i915(fb
->dev
)) / tile_width_bytes
;
2083 intel_fb_align_height(const struct drm_framebuffer
*fb
,
2084 int plane
, unsigned int height
)
2086 unsigned int tile_height
= intel_tile_height(fb
, plane
);
2088 return ALIGN(height
, tile_height
);
2091 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2093 unsigned int size
= 0;
2096 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2097 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2103 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2104 const struct drm_framebuffer
*fb
,
2105 unsigned int rotation
)
2107 view
->type
= I915_GGTT_VIEW_NORMAL
;
2108 if (drm_rotation_90_or_270(rotation
)) {
2109 view
->type
= I915_GGTT_VIEW_ROTATED
;
2110 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
2114 static unsigned int intel_cursor_alignment(const struct drm_i915_private
*dev_priv
)
2116 if (IS_I830(dev_priv
))
2118 else if (IS_I85X(dev_priv
))
2120 else if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
2126 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2128 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2130 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2131 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2133 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2139 static unsigned int intel_surf_alignment(const struct drm_framebuffer
*fb
,
2142 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2144 /* AUX_DIST needs only 4K alignment */
2148 switch (fb
->modifier
) {
2149 case DRM_FORMAT_MOD_LINEAR
:
2150 return intel_linear_alignment(dev_priv
);
2151 case I915_FORMAT_MOD_X_TILED
:
2152 if (INTEL_GEN(dev_priv
) >= 9)
2155 case I915_FORMAT_MOD_Y_TILED_CCS
:
2156 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2157 case I915_FORMAT_MOD_Y_TILED
:
2158 case I915_FORMAT_MOD_Yf_TILED
:
2159 return 1 * 1024 * 1024;
2161 MISSING_CASE(fb
->modifier
);
2167 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2169 struct drm_device
*dev
= fb
->dev
;
2170 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2171 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2172 struct i915_ggtt_view view
;
2173 struct i915_vma
*vma
;
2176 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2178 alignment
= intel_surf_alignment(fb
, 0);
2180 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2182 /* Note that the w/a also requires 64 PTE of padding following the
2183 * bo. We currently fill all unused PTE with the shadow page and so
2184 * we should always have valid PTE following the scanout preventing
2187 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2188 alignment
= 256 * 1024;
2191 * Global gtt pte registers are special registers which actually forward
2192 * writes to a chunk of system memory. Which means that there is no risk
2193 * that the register values disappear as soon as we call
2194 * intel_runtime_pm_put(), so it is correct to wrap only the
2195 * pin/unpin/fence and not more.
2197 intel_runtime_pm_get(dev_priv
);
2199 atomic_inc(&dev_priv
->gpu_error
.pending_fb_pin
);
2201 vma
= i915_gem_object_pin_to_display_plane(obj
, alignment
, &view
);
2205 if (i915_vma_is_map_and_fenceable(vma
)) {
2206 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2207 * fence, whereas 965+ only requires a fence if using
2208 * framebuffer compression. For simplicity, we always, when
2209 * possible, install a fence as the cost is not that onerous.
2211 * If we fail to fence the tiled scanout, then either the
2212 * modeset will reject the change (which is highly unlikely as
2213 * the affected systems, all but one, do not have unmappable
2214 * space) or we will not be able to enable full powersaving
2215 * techniques (also likely not to apply due to various limits
2216 * FBC and the like impose on the size of the buffer, which
2217 * presumably we violated anyway with this unmappable buffer).
2218 * Anyway, it is presumably better to stumble onwards with
2219 * something and try to run the system in a "less than optimal"
2220 * mode that matches the user configuration.
2222 if (i915_vma_get_fence(vma
) == 0)
2223 i915_vma_pin_fence(vma
);
2228 atomic_dec(&dev_priv
->gpu_error
.pending_fb_pin
);
2230 intel_runtime_pm_put(dev_priv
);
2234 void intel_unpin_fb_vma(struct i915_vma
*vma
)
2236 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2238 i915_vma_unpin_fence(vma
);
2239 i915_gem_object_unpin_from_display_plane(vma
);
2243 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int plane
,
2244 unsigned int rotation
)
2246 if (drm_rotation_90_or_270(rotation
))
2247 return to_intel_framebuffer(fb
)->rotated
[plane
].pitch
;
2249 return fb
->pitches
[plane
];
2253 * Convert the x/y offsets into a linear offset.
2254 * Only valid with 0/180 degree rotation, which is fine since linear
2255 * offset is only used with linear buffers on pre-hsw and tiled buffers
2256 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2258 u32
intel_fb_xy_to_linear(int x
, int y
,
2259 const struct intel_plane_state
*state
,
2262 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2263 unsigned int cpp
= fb
->format
->cpp
[plane
];
2264 unsigned int pitch
= fb
->pitches
[plane
];
2266 return y
* pitch
+ x
* cpp
;
2270 * Add the x/y offsets derived from fb->offsets[] to the user
2271 * specified plane src x/y offsets. The resulting x/y offsets
2272 * specify the start of scanout from the beginning of the gtt mapping.
2274 void intel_add_fb_offsets(int *x
, int *y
,
2275 const struct intel_plane_state
*state
,
2279 const struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(state
->base
.fb
);
2280 unsigned int rotation
= state
->base
.rotation
;
2282 if (drm_rotation_90_or_270(rotation
)) {
2283 *x
+= intel_fb
->rotated
[plane
].x
;
2284 *y
+= intel_fb
->rotated
[plane
].y
;
2286 *x
+= intel_fb
->normal
[plane
].x
;
2287 *y
+= intel_fb
->normal
[plane
].y
;
2291 static u32
__intel_adjust_tile_offset(int *x
, int *y
,
2292 unsigned int tile_width
,
2293 unsigned int tile_height
,
2294 unsigned int tile_size
,
2295 unsigned int pitch_tiles
,
2299 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2302 WARN_ON(old_offset
& (tile_size
- 1));
2303 WARN_ON(new_offset
& (tile_size
- 1));
2304 WARN_ON(new_offset
> old_offset
);
2306 tiles
= (old_offset
- new_offset
) / tile_size
;
2308 *y
+= tiles
/ pitch_tiles
* tile_height
;
2309 *x
+= tiles
% pitch_tiles
* tile_width
;
2311 /* minimize x in case it got needlessly big */
2312 *y
+= *x
/ pitch_pixels
* tile_height
;
2318 static u32
_intel_adjust_tile_offset(int *x
, int *y
,
2319 const struct drm_framebuffer
*fb
, int plane
,
2320 unsigned int rotation
,
2321 u32 old_offset
, u32 new_offset
)
2323 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2324 unsigned int cpp
= fb
->format
->cpp
[plane
];
2325 unsigned int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2327 WARN_ON(new_offset
> old_offset
);
2329 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
2330 unsigned int tile_size
, tile_width
, tile_height
;
2331 unsigned int pitch_tiles
;
2333 tile_size
= intel_tile_size(dev_priv
);
2334 intel_tile_dims(fb
, plane
, &tile_width
, &tile_height
);
2336 if (drm_rotation_90_or_270(rotation
)) {
2337 pitch_tiles
= pitch
/ tile_height
;
2338 swap(tile_width
, tile_height
);
2340 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2343 __intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2344 tile_size
, pitch_tiles
,
2345 old_offset
, new_offset
);
2347 old_offset
+= *y
* pitch
+ *x
* cpp
;
2349 *y
= (old_offset
- new_offset
) / pitch
;
2350 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2357 * Adjust the tile offset by moving the difference into
2360 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2361 const struct intel_plane_state
*state
, int plane
,
2362 u32 old_offset
, u32 new_offset
)
2364 return _intel_adjust_tile_offset(x
, y
, state
->base
.fb
, plane
,
2365 state
->base
.rotation
,
2366 old_offset
, new_offset
);
2370 * Computes the linear offset to the base tile and adjusts
2371 * x, y. bytes per pixel is assumed to be a power-of-two.
2373 * In the 90/270 rotated case, x and y are assumed
2374 * to be already rotated to match the rotated GTT view, and
2375 * pitch is the tile_height aligned framebuffer height.
2377 * This function is used when computing the derived information
2378 * under intel_framebuffer, so using any of that information
2379 * here is not allowed. Anything under drm_framebuffer can be
2380 * used. This is why the user has to pass in the pitch since it
2381 * is specified in the rotated orientation.
2383 static u32
_intel_compute_tile_offset(const struct drm_i915_private
*dev_priv
,
2385 const struct drm_framebuffer
*fb
, int plane
,
2387 unsigned int rotation
,
2390 uint64_t fb_modifier
= fb
->modifier
;
2391 unsigned int cpp
= fb
->format
->cpp
[plane
];
2392 u32 offset
, offset_aligned
;
2397 if (fb_modifier
!= DRM_FORMAT_MOD_LINEAR
) {
2398 unsigned int tile_size
, tile_width
, tile_height
;
2399 unsigned int tile_rows
, tiles
, pitch_tiles
;
2401 tile_size
= intel_tile_size(dev_priv
);
2402 intel_tile_dims(fb
, plane
, &tile_width
, &tile_height
);
2404 if (drm_rotation_90_or_270(rotation
)) {
2405 pitch_tiles
= pitch
/ tile_height
;
2406 swap(tile_width
, tile_height
);
2408 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2411 tile_rows
= *y
/ tile_height
;
2414 tiles
= *x
/ tile_width
;
2417 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2418 offset_aligned
= offset
& ~alignment
;
2420 __intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2421 tile_size
, pitch_tiles
,
2422 offset
, offset_aligned
);
2424 offset
= *y
* pitch
+ *x
* cpp
;
2425 offset_aligned
= offset
& ~alignment
;
2427 *y
= (offset
& alignment
) / pitch
;
2428 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2431 return offset_aligned
;
2434 u32
intel_compute_tile_offset(int *x
, int *y
,
2435 const struct intel_plane_state
*state
,
2438 struct intel_plane
*intel_plane
= to_intel_plane(state
->base
.plane
);
2439 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
2440 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2441 unsigned int rotation
= state
->base
.rotation
;
2442 int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2445 if (intel_plane
->id
== PLANE_CURSOR
)
2446 alignment
= intel_cursor_alignment(dev_priv
);
2448 alignment
= intel_surf_alignment(fb
, plane
);
2450 return _intel_compute_tile_offset(dev_priv
, x
, y
, fb
, plane
, pitch
,
2451 rotation
, alignment
);
2454 /* Convert the fb->offset[] into x/y offsets */
2455 static int intel_fb_offset_to_xy(int *x
, int *y
,
2456 const struct drm_framebuffer
*fb
, int plane
)
2458 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2460 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
&&
2461 fb
->offsets
[plane
] % intel_tile_size(dev_priv
))
2467 _intel_adjust_tile_offset(x
, y
,
2468 fb
, plane
, DRM_MODE_ROTATE_0
,
2469 fb
->offsets
[plane
], 0);
2474 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier
)
2476 switch (fb_modifier
) {
2477 case I915_FORMAT_MOD_X_TILED
:
2478 return I915_TILING_X
;
2479 case I915_FORMAT_MOD_Y_TILED
:
2480 case I915_FORMAT_MOD_Y_TILED_CCS
:
2481 return I915_TILING_Y
;
2483 return I915_TILING_NONE
;
2487 static const struct drm_format_info ccs_formats
[] = {
2488 { .format
= DRM_FORMAT_XRGB8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2489 { .format
= DRM_FORMAT_XBGR8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2490 { .format
= DRM_FORMAT_ARGB8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2491 { .format
= DRM_FORMAT_ABGR8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2494 static const struct drm_format_info
*
2495 lookup_format_info(const struct drm_format_info formats
[],
2496 int num_formats
, u32 format
)
2500 for (i
= 0; i
< num_formats
; i
++) {
2501 if (formats
[i
].format
== format
)
2508 static const struct drm_format_info
*
2509 intel_get_format_info(const struct drm_mode_fb_cmd2
*cmd
)
2511 switch (cmd
->modifier
[0]) {
2512 case I915_FORMAT_MOD_Y_TILED_CCS
:
2513 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2514 return lookup_format_info(ccs_formats
,
2515 ARRAY_SIZE(ccs_formats
),
2523 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2524 struct drm_framebuffer
*fb
)
2526 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2527 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2528 u32 gtt_offset_rotated
= 0;
2529 unsigned int max_size
= 0;
2530 int i
, num_planes
= fb
->format
->num_planes
;
2531 unsigned int tile_size
= intel_tile_size(dev_priv
);
2533 for (i
= 0; i
< num_planes
; i
++) {
2534 unsigned int width
, height
;
2535 unsigned int cpp
, size
;
2540 cpp
= fb
->format
->cpp
[i
];
2541 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2542 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2544 ret
= intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2546 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2551 if ((fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
2552 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
) && i
== 1) {
2553 int hsub
= fb
->format
->hsub
;
2554 int vsub
= fb
->format
->vsub
;
2555 int tile_width
, tile_height
;
2559 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2561 tile_height
*= vsub
;
2563 ccs_x
= (x
* hsub
) % tile_width
;
2564 ccs_y
= (y
* vsub
) % tile_height
;
2565 main_x
= intel_fb
->normal
[0].x
% tile_width
;
2566 main_y
= intel_fb
->normal
[0].y
% tile_height
;
2569 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2570 * x/y offsets must match between CCS and the main surface.
2572 if (main_x
!= ccs_x
|| main_y
!= ccs_y
) {
2573 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2576 intel_fb
->normal
[0].x
,
2577 intel_fb
->normal
[0].y
,
2584 * The fence (if used) is aligned to the start of the object
2585 * so having the framebuffer wrap around across the edge of the
2586 * fenced region doesn't really work. We have no API to configure
2587 * the fence start offset within the object (nor could we probably
2588 * on gen2/3). So it's just easier if we just require that the
2589 * fb layout agrees with the fence layout. We already check that the
2590 * fb stride matches the fence stride elsewhere.
2592 if (i
== 0 && i915_gem_object_is_tiled(intel_fb
->obj
) &&
2593 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2594 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2600 * First pixel of the framebuffer from
2601 * the start of the normal gtt mapping.
2603 intel_fb
->normal
[i
].x
= x
;
2604 intel_fb
->normal
[i
].y
= y
;
2606 offset
= _intel_compute_tile_offset(dev_priv
, &x
, &y
,
2607 fb
, i
, fb
->pitches
[i
],
2608 DRM_MODE_ROTATE_0
, tile_size
);
2609 offset
/= tile_size
;
2611 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
2612 unsigned int tile_width
, tile_height
;
2613 unsigned int pitch_tiles
;
2616 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2618 rot_info
->plane
[i
].offset
= offset
;
2619 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2620 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2621 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2623 intel_fb
->rotated
[i
].pitch
=
2624 rot_info
->plane
[i
].height
* tile_height
;
2626 /* how many tiles does this plane need */
2627 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2629 * If the plane isn't horizontally tile aligned,
2630 * we need one more tile.
2635 /* rotate the x/y offsets to match the GTT view */
2641 rot_info
->plane
[i
].width
* tile_width
,
2642 rot_info
->plane
[i
].height
* tile_height
,
2643 DRM_MODE_ROTATE_270
);
2647 /* rotate the tile dimensions to match the GTT view */
2648 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2649 swap(tile_width
, tile_height
);
2652 * We only keep the x/y offsets, so push all of the
2653 * gtt offset into the x/y offsets.
2655 __intel_adjust_tile_offset(&x
, &y
,
2656 tile_width
, tile_height
,
2657 tile_size
, pitch_tiles
,
2658 gtt_offset_rotated
* tile_size
, 0);
2660 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2663 * First pixel of the framebuffer from
2664 * the start of the rotated gtt mapping.
2666 intel_fb
->rotated
[i
].x
= x
;
2667 intel_fb
->rotated
[i
].y
= y
;
2669 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2670 x
* cpp
, tile_size
);
2673 /* how many tiles in total needed in the bo */
2674 max_size
= max(max_size
, offset
+ size
);
2677 if (max_size
* tile_size
> intel_fb
->obj
->base
.size
) {
2678 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2679 max_size
* tile_size
, intel_fb
->obj
->base
.size
);
2686 static int i9xx_format_to_fourcc(int format
)
2689 case DISPPLANE_8BPP
:
2690 return DRM_FORMAT_C8
;
2691 case DISPPLANE_BGRX555
:
2692 return DRM_FORMAT_XRGB1555
;
2693 case DISPPLANE_BGRX565
:
2694 return DRM_FORMAT_RGB565
;
2696 case DISPPLANE_BGRX888
:
2697 return DRM_FORMAT_XRGB8888
;
2698 case DISPPLANE_RGBX888
:
2699 return DRM_FORMAT_XBGR8888
;
2700 case DISPPLANE_BGRX101010
:
2701 return DRM_FORMAT_XRGB2101010
;
2702 case DISPPLANE_RGBX101010
:
2703 return DRM_FORMAT_XBGR2101010
;
2707 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2710 case PLANE_CTL_FORMAT_RGB_565
:
2711 return DRM_FORMAT_RGB565
;
2713 case PLANE_CTL_FORMAT_XRGB_8888
:
2716 return DRM_FORMAT_ABGR8888
;
2718 return DRM_FORMAT_XBGR8888
;
2721 return DRM_FORMAT_ARGB8888
;
2723 return DRM_FORMAT_XRGB8888
;
2725 case PLANE_CTL_FORMAT_XRGB_2101010
:
2727 return DRM_FORMAT_XBGR2101010
;
2729 return DRM_FORMAT_XRGB2101010
;
2734 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2735 struct intel_initial_plane_config
*plane_config
)
2737 struct drm_device
*dev
= crtc
->base
.dev
;
2738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2739 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2740 struct drm_i915_gem_object
*obj
= NULL
;
2741 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2742 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2743 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2744 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2747 size_aligned
-= base_aligned
;
2749 if (plane_config
->size
== 0)
2752 /* If the FB is too big, just don't use it since fbdev is not very
2753 * important and we should probably use that space with FBC or other
2755 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2758 mutex_lock(&dev
->struct_mutex
);
2759 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
2763 mutex_unlock(&dev
->struct_mutex
);
2767 if (plane_config
->tiling
== I915_TILING_X
)
2768 obj
->tiling_and_stride
= fb
->pitches
[0] | I915_TILING_X
;
2770 mode_cmd
.pixel_format
= fb
->format
->format
;
2771 mode_cmd
.width
= fb
->width
;
2772 mode_cmd
.height
= fb
->height
;
2773 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2774 mode_cmd
.modifier
[0] = fb
->modifier
;
2775 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2777 if (intel_framebuffer_init(to_intel_framebuffer(fb
), obj
, &mode_cmd
)) {
2778 DRM_DEBUG_KMS("intel fb init failed\n");
2783 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2787 i915_gem_object_put(obj
);
2792 intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
2793 struct intel_plane_state
*plane_state
,
2796 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2798 plane_state
->base
.visible
= visible
;
2800 /* FIXME pre-g4x don't work like this */
2802 crtc_state
->base
.plane_mask
|= BIT(drm_plane_index(&plane
->base
));
2803 crtc_state
->active_planes
|= BIT(plane
->id
);
2805 crtc_state
->base
.plane_mask
&= ~BIT(drm_plane_index(&plane
->base
));
2806 crtc_state
->active_planes
&= ~BIT(plane
->id
);
2809 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2810 crtc_state
->base
.crtc
->name
,
2811 crtc_state
->active_planes
);
2815 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2816 struct intel_initial_plane_config
*plane_config
)
2818 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2819 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2821 struct drm_i915_gem_object
*obj
;
2822 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2823 struct drm_plane_state
*plane_state
= primary
->state
;
2824 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2825 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2826 struct intel_plane_state
*intel_state
=
2827 to_intel_plane_state(plane_state
);
2828 struct drm_framebuffer
*fb
;
2830 if (!plane_config
->fb
)
2833 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2834 fb
= &plane_config
->fb
->base
;
2838 kfree(plane_config
->fb
);
2841 * Failed to alloc the obj, check to see if we should share
2842 * an fb with another CRTC instead
2844 for_each_crtc(dev
, c
) {
2845 struct intel_plane_state
*state
;
2847 if (c
== &intel_crtc
->base
)
2850 if (!to_intel_crtc(c
)->active
)
2853 state
= to_intel_plane_state(c
->primary
->state
);
2857 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
2858 fb
= c
->primary
->fb
;
2859 drm_framebuffer_reference(fb
);
2865 * We've failed to reconstruct the BIOS FB. Current display state
2866 * indicates that the primary plane is visible, but has a NULL FB,
2867 * which will lead to problems later if we don't fix it up. The
2868 * simplest solution is to just disable the primary plane now and
2869 * pretend the BIOS never had it enabled.
2871 intel_set_plane_visible(to_intel_crtc_state(crtc_state
),
2872 to_intel_plane_state(plane_state
),
2874 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2875 trace_intel_disable_plane(primary
, intel_crtc
);
2876 intel_plane
->disable_plane(intel_plane
, intel_crtc
);
2881 mutex_lock(&dev
->struct_mutex
);
2883 intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
2884 mutex_unlock(&dev
->struct_mutex
);
2885 if (IS_ERR(intel_state
->vma
)) {
2886 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2887 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
2889 intel_state
->vma
= NULL
;
2890 drm_framebuffer_unreference(fb
);
2894 plane_state
->src_x
= 0;
2895 plane_state
->src_y
= 0;
2896 plane_state
->src_w
= fb
->width
<< 16;
2897 plane_state
->src_h
= fb
->height
<< 16;
2899 plane_state
->crtc_x
= 0;
2900 plane_state
->crtc_y
= 0;
2901 plane_state
->crtc_w
= fb
->width
;
2902 plane_state
->crtc_h
= fb
->height
;
2904 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
2905 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
2907 obj
= intel_fb_obj(fb
);
2908 if (i915_gem_object_is_tiled(obj
))
2909 dev_priv
->preserve_bios_swizzle
= true;
2911 drm_framebuffer_reference(fb
);
2912 primary
->fb
= primary
->state
->fb
= fb
;
2913 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2915 intel_set_plane_visible(to_intel_crtc_state(crtc_state
),
2916 to_intel_plane_state(plane_state
),
2919 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
2920 &obj
->frontbuffer_bits
);
2923 static int skl_max_plane_width(const struct drm_framebuffer
*fb
, int plane
,
2924 unsigned int rotation
)
2926 int cpp
= fb
->format
->cpp
[plane
];
2928 switch (fb
->modifier
) {
2929 case DRM_FORMAT_MOD_LINEAR
:
2930 case I915_FORMAT_MOD_X_TILED
:
2943 case I915_FORMAT_MOD_Y_TILED_CCS
:
2944 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2945 /* FIXME AUX plane? */
2946 case I915_FORMAT_MOD_Y_TILED
:
2947 case I915_FORMAT_MOD_Yf_TILED
:
2962 MISSING_CASE(fb
->modifier
);
2968 static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state
,
2969 int main_x
, int main_y
, u32 main_offset
)
2971 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2972 int hsub
= fb
->format
->hsub
;
2973 int vsub
= fb
->format
->vsub
;
2974 int aux_x
= plane_state
->aux
.x
;
2975 int aux_y
= plane_state
->aux
.y
;
2976 u32 aux_offset
= plane_state
->aux
.offset
;
2977 u32 alignment
= intel_surf_alignment(fb
, 1);
2979 while (aux_offset
>= main_offset
&& aux_y
<= main_y
) {
2982 if (aux_x
== main_x
&& aux_y
== main_y
)
2985 if (aux_offset
== 0)
2990 aux_offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 1,
2991 aux_offset
, aux_offset
- alignment
);
2992 aux_x
= x
* hsub
+ aux_x
% hsub
;
2993 aux_y
= y
* vsub
+ aux_y
% vsub
;
2996 if (aux_x
!= main_x
|| aux_y
!= main_y
)
2999 plane_state
->aux
.offset
= aux_offset
;
3000 plane_state
->aux
.x
= aux_x
;
3001 plane_state
->aux
.y
= aux_y
;
3006 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
3008 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3009 unsigned int rotation
= plane_state
->base
.rotation
;
3010 int x
= plane_state
->base
.src
.x1
>> 16;
3011 int y
= plane_state
->base
.src
.y1
>> 16;
3012 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3013 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3014 int max_width
= skl_max_plane_width(fb
, 0, rotation
);
3015 int max_height
= 4096;
3016 u32 alignment
, offset
, aux_offset
= plane_state
->aux
.offset
;
3018 if (w
> max_width
|| h
> max_height
) {
3019 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3020 w
, h
, max_width
, max_height
);
3024 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3025 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
3026 alignment
= intel_surf_alignment(fb
, 0);
3029 * AUX surface offset is specified as the distance from the
3030 * main surface offset, and it must be non-negative. Make
3031 * sure that is what we will get.
3033 if (offset
> aux_offset
)
3034 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
3035 offset
, aux_offset
& ~(alignment
- 1));
3038 * When using an X-tiled surface, the plane blows up
3039 * if the x offset + width exceed the stride.
3041 * TODO: linear and Y-tiled seem fine, Yf untested,
3043 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
3044 int cpp
= fb
->format
->cpp
[0];
3046 while ((x
+ w
) * cpp
> fb
->pitches
[0]) {
3048 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3052 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
3053 offset
, offset
- alignment
);
3058 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3059 * they match with the main surface x/y offsets.
3061 if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
3062 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
) {
3063 while (!skl_check_main_ccs_coordinates(plane_state
, x
, y
, offset
)) {
3067 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
3068 offset
, offset
- alignment
);
3071 if (x
!= plane_state
->aux
.x
|| y
!= plane_state
->aux
.y
) {
3072 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3077 plane_state
->main
.offset
= offset
;
3078 plane_state
->main
.x
= x
;
3079 plane_state
->main
.y
= y
;
3084 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
3086 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3087 unsigned int rotation
= plane_state
->base
.rotation
;
3088 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
3089 int max_height
= 4096;
3090 int x
= plane_state
->base
.src
.x1
>> 17;
3091 int y
= plane_state
->base
.src
.y1
>> 17;
3092 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
3093 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
3096 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3097 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 1);
3099 /* FIXME not quite sure how/if these apply to the chroma plane */
3100 if (w
> max_width
|| h
> max_height
) {
3101 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3102 w
, h
, max_width
, max_height
);
3106 plane_state
->aux
.offset
= offset
;
3107 plane_state
->aux
.x
= x
;
3108 plane_state
->aux
.y
= y
;
3113 static int skl_check_ccs_aux_surface(struct intel_plane_state
*plane_state
)
3115 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
3116 struct intel_crtc
*crtc
= to_intel_crtc(plane_state
->base
.crtc
);
3117 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3118 int src_x
= plane_state
->base
.src
.x1
>> 16;
3119 int src_y
= plane_state
->base
.src
.y1
>> 16;
3120 int hsub
= fb
->format
->hsub
;
3121 int vsub
= fb
->format
->vsub
;
3122 int x
= src_x
/ hsub
;
3123 int y
= src_y
/ vsub
;
3126 switch (plane
->id
) {
3131 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3135 if (crtc
->pipe
== PIPE_C
) {
3136 DRM_DEBUG_KMS("No RC support on pipe C\n");
3140 if (plane_state
->base
.rotation
& ~(DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
)) {
3141 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3142 plane_state
->base
.rotation
);
3146 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3147 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 1);
3149 plane_state
->aux
.offset
= offset
;
3150 plane_state
->aux
.x
= x
* hsub
+ src_x
% hsub
;
3151 plane_state
->aux
.y
= y
* vsub
+ src_y
% vsub
;
3156 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
3158 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3159 unsigned int rotation
= plane_state
->base
.rotation
;
3162 if (!plane_state
->base
.visible
)
3165 /* Rotate src coordinates to match rotated GTT view */
3166 if (drm_rotation_90_or_270(rotation
))
3167 drm_rect_rotate(&plane_state
->base
.src
,
3168 fb
->width
<< 16, fb
->height
<< 16,
3169 DRM_MODE_ROTATE_270
);
3172 * Handle the AUX surface first since
3173 * the main surface setup depends on it.
3175 if (fb
->format
->format
== DRM_FORMAT_NV12
) {
3176 ret
= skl_check_nv12_aux_surface(plane_state
);
3179 } else if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
3180 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
) {
3181 ret
= skl_check_ccs_aux_surface(plane_state
);
3185 plane_state
->aux
.offset
= ~0xfff;
3186 plane_state
->aux
.x
= 0;
3187 plane_state
->aux
.y
= 0;
3190 ret
= skl_check_main_surface(plane_state
);
3197 static u32
i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3198 const struct intel_plane_state
*plane_state
)
3200 struct drm_i915_private
*dev_priv
=
3201 to_i915(plane_state
->base
.plane
->dev
);
3202 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3203 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3204 unsigned int rotation
= plane_state
->base
.rotation
;
3207 dspcntr
= DISPLAY_PLANE_ENABLE
| DISPPLANE_GAMMA_ENABLE
;
3209 if (IS_G4X(dev_priv
) || IS_GEN5(dev_priv
) ||
3210 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
3211 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3213 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3214 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3216 if (INTEL_GEN(dev_priv
) < 4)
3217 dspcntr
|= DISPPLANE_SEL_PIPE(crtc
->pipe
);
3219 switch (fb
->format
->format
) {
3221 dspcntr
|= DISPPLANE_8BPP
;
3223 case DRM_FORMAT_XRGB1555
:
3224 dspcntr
|= DISPPLANE_BGRX555
;
3226 case DRM_FORMAT_RGB565
:
3227 dspcntr
|= DISPPLANE_BGRX565
;
3229 case DRM_FORMAT_XRGB8888
:
3230 dspcntr
|= DISPPLANE_BGRX888
;
3232 case DRM_FORMAT_XBGR8888
:
3233 dspcntr
|= DISPPLANE_RGBX888
;
3235 case DRM_FORMAT_XRGB2101010
:
3236 dspcntr
|= DISPPLANE_BGRX101010
;
3238 case DRM_FORMAT_XBGR2101010
:
3239 dspcntr
|= DISPPLANE_RGBX101010
;
3242 MISSING_CASE(fb
->format
->format
);
3246 if (INTEL_GEN(dev_priv
) >= 4 &&
3247 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3248 dspcntr
|= DISPPLANE_TILED
;
3250 if (rotation
& DRM_MODE_ROTATE_180
)
3251 dspcntr
|= DISPPLANE_ROTATE_180
;
3253 if (rotation
& DRM_MODE_REFLECT_X
)
3254 dspcntr
|= DISPPLANE_MIRROR
;
3259 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
)
3261 struct drm_i915_private
*dev_priv
=
3262 to_i915(plane_state
->base
.plane
->dev
);
3263 int src_x
= plane_state
->base
.src
.x1
>> 16;
3264 int src_y
= plane_state
->base
.src
.y1
>> 16;
3267 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
3269 if (INTEL_GEN(dev_priv
) >= 4)
3270 offset
= intel_compute_tile_offset(&src_x
, &src_y
,
3275 /* HSW/BDW do this automagically in hardware */
3276 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
)) {
3277 unsigned int rotation
= plane_state
->base
.rotation
;
3278 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3279 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3281 if (rotation
& DRM_MODE_ROTATE_180
) {
3284 } else if (rotation
& DRM_MODE_REFLECT_X
) {
3289 plane_state
->main
.offset
= offset
;
3290 plane_state
->main
.x
= src_x
;
3291 plane_state
->main
.y
= src_y
;
3296 static void i9xx_update_primary_plane(struct intel_plane
*primary
,
3297 const struct intel_crtc_state
*crtc_state
,
3298 const struct intel_plane_state
*plane_state
)
3300 struct drm_i915_private
*dev_priv
= to_i915(primary
->base
.dev
);
3301 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3302 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3303 enum plane plane
= primary
->plane
;
3305 u32 dspcntr
= plane_state
->ctl
;
3306 i915_reg_t reg
= DSPCNTR(plane
);
3307 int x
= plane_state
->main
.x
;
3308 int y
= plane_state
->main
.y
;
3309 unsigned long irqflags
;
3311 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3313 if (INTEL_GEN(dev_priv
) >= 4)
3314 crtc
->dspaddr_offset
= plane_state
->main
.offset
;
3316 crtc
->dspaddr_offset
= linear_offset
;
3318 crtc
->adjusted_x
= x
;
3319 crtc
->adjusted_y
= y
;
3321 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3323 if (INTEL_GEN(dev_priv
) < 4) {
3324 /* pipesrc and dspsize control the size that is scaled from,
3325 * which should always be the user's requested size.
3327 I915_WRITE_FW(DSPSIZE(plane
),
3328 ((crtc_state
->pipe_src_h
- 1) << 16) |
3329 (crtc_state
->pipe_src_w
- 1));
3330 I915_WRITE_FW(DSPPOS(plane
), 0);
3331 } else if (IS_CHERRYVIEW(dev_priv
) && plane
== PLANE_B
) {
3332 I915_WRITE_FW(PRIMSIZE(plane
),
3333 ((crtc_state
->pipe_src_h
- 1) << 16) |
3334 (crtc_state
->pipe_src_w
- 1));
3335 I915_WRITE_FW(PRIMPOS(plane
), 0);
3336 I915_WRITE_FW(PRIMCNSTALPHA(plane
), 0);
3339 I915_WRITE_FW(reg
, dspcntr
);
3341 I915_WRITE_FW(DSPSTRIDE(plane
), fb
->pitches
[0]);
3342 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3343 I915_WRITE_FW(DSPSURF(plane
),
3344 intel_plane_ggtt_offset(plane_state
) +
3345 crtc
->dspaddr_offset
);
3346 I915_WRITE_FW(DSPOFFSET(plane
), (y
<< 16) | x
);
3347 } else if (INTEL_GEN(dev_priv
) >= 4) {
3348 I915_WRITE_FW(DSPSURF(plane
),
3349 intel_plane_ggtt_offset(plane_state
) +
3350 crtc
->dspaddr_offset
);
3351 I915_WRITE_FW(DSPTILEOFF(plane
), (y
<< 16) | x
);
3352 I915_WRITE_FW(DSPLINOFF(plane
), linear_offset
);
3354 I915_WRITE_FW(DSPADDR(plane
),
3355 intel_plane_ggtt_offset(plane_state
) +
3356 crtc
->dspaddr_offset
);
3358 POSTING_READ_FW(reg
);
3360 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3363 static void i9xx_disable_primary_plane(struct intel_plane
*primary
,
3364 struct intel_crtc
*crtc
)
3366 struct drm_i915_private
*dev_priv
= to_i915(primary
->base
.dev
);
3367 enum plane plane
= primary
->plane
;
3368 unsigned long irqflags
;
3370 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3372 I915_WRITE_FW(DSPCNTR(plane
), 0);
3373 if (INTEL_INFO(dev_priv
)->gen
>= 4)
3374 I915_WRITE_FW(DSPSURF(plane
), 0);
3376 I915_WRITE_FW(DSPADDR(plane
), 0);
3377 POSTING_READ_FW(DSPCNTR(plane
));
3379 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3383 intel_fb_stride_alignment(const struct drm_framebuffer
*fb
, int plane
)
3385 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3388 return intel_tile_width_bytes(fb
, plane
);
3391 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3393 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3394 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3396 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3397 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3398 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3402 * This function detaches (aka. unbinds) unused scalers in hardware
3404 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
3406 struct intel_crtc_scaler_state
*scaler_state
;
3409 scaler_state
= &intel_crtc
->config
->scaler_state
;
3411 /* loop through and disable scalers that aren't in use */
3412 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3413 if (!scaler_state
->scalers
[i
].in_use
)
3414 skl_detach_scaler(intel_crtc
, i
);
3418 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
3419 unsigned int rotation
)
3423 if (plane
>= fb
->format
->num_planes
)
3426 stride
= intel_fb_pitch(fb
, plane
, rotation
);
3429 * The stride is either expressed as a multiple of 64 bytes chunks for
3430 * linear buffers or in number of tiles for tiled buffers.
3432 if (drm_rotation_90_or_270(rotation
))
3433 stride
/= intel_tile_height(fb
, plane
);
3435 stride
/= intel_fb_stride_alignment(fb
, plane
);
3440 static u32
skl_plane_ctl_format(uint32_t pixel_format
)
3442 switch (pixel_format
) {
3444 return PLANE_CTL_FORMAT_INDEXED
;
3445 case DRM_FORMAT_RGB565
:
3446 return PLANE_CTL_FORMAT_RGB_565
;
3447 case DRM_FORMAT_XBGR8888
:
3448 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3449 case DRM_FORMAT_XRGB8888
:
3450 return PLANE_CTL_FORMAT_XRGB_8888
;
3452 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3453 * to be already pre-multiplied. We need to add a knob (or a different
3454 * DRM_FORMAT) for user-space to configure that.
3456 case DRM_FORMAT_ABGR8888
:
3457 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
3458 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3459 case DRM_FORMAT_ARGB8888
:
3460 return PLANE_CTL_FORMAT_XRGB_8888
|
3461 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3462 case DRM_FORMAT_XRGB2101010
:
3463 return PLANE_CTL_FORMAT_XRGB_2101010
;
3464 case DRM_FORMAT_XBGR2101010
:
3465 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3466 case DRM_FORMAT_YUYV
:
3467 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3468 case DRM_FORMAT_YVYU
:
3469 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3470 case DRM_FORMAT_UYVY
:
3471 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3472 case DRM_FORMAT_VYUY
:
3473 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3475 MISSING_CASE(pixel_format
);
3481 static u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3483 switch (fb_modifier
) {
3484 case DRM_FORMAT_MOD_LINEAR
:
3486 case I915_FORMAT_MOD_X_TILED
:
3487 return PLANE_CTL_TILED_X
;
3488 case I915_FORMAT_MOD_Y_TILED
:
3489 return PLANE_CTL_TILED_Y
;
3490 case I915_FORMAT_MOD_Y_TILED_CCS
:
3491 return PLANE_CTL_TILED_Y
| PLANE_CTL_DECOMPRESSION_ENABLE
;
3492 case I915_FORMAT_MOD_Yf_TILED
:
3493 return PLANE_CTL_TILED_YF
;
3494 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3495 return PLANE_CTL_TILED_YF
| PLANE_CTL_DECOMPRESSION_ENABLE
;
3497 MISSING_CASE(fb_modifier
);
3503 static u32
skl_plane_ctl_rotation(unsigned int rotation
)
3506 case DRM_MODE_ROTATE_0
:
3509 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3510 * while i915 HW rotation is clockwise, thats why this swapping.
3512 case DRM_MODE_ROTATE_90
:
3513 return PLANE_CTL_ROTATE_270
;
3514 case DRM_MODE_ROTATE_180
:
3515 return PLANE_CTL_ROTATE_180
;
3516 case DRM_MODE_ROTATE_270
:
3517 return PLANE_CTL_ROTATE_90
;
3519 MISSING_CASE(rotation
);
3525 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3526 const struct intel_plane_state
*plane_state
)
3528 struct drm_i915_private
*dev_priv
=
3529 to_i915(plane_state
->base
.plane
->dev
);
3530 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3531 unsigned int rotation
= plane_state
->base
.rotation
;
3532 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
3535 plane_ctl
= PLANE_CTL_ENABLE
;
3537 if (!IS_GEMINILAKE(dev_priv
) && !IS_CANNONLAKE(dev_priv
)) {
3539 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3540 PLANE_CTL_PIPE_CSC_ENABLE
|
3541 PLANE_CTL_PLANE_GAMMA_DISABLE
;
3544 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
3545 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
3546 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3548 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
3549 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
3550 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
3551 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
3556 static void skylake_update_primary_plane(struct intel_plane
*plane
,
3557 const struct intel_crtc_state
*crtc_state
,
3558 const struct intel_plane_state
*plane_state
)
3560 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3561 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3562 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3563 enum plane_id plane_id
= plane
->id
;
3564 enum pipe pipe
= plane
->pipe
;
3565 u32 plane_ctl
= plane_state
->ctl
;
3566 unsigned int rotation
= plane_state
->base
.rotation
;
3567 u32 stride
= skl_plane_stride(fb
, 0, rotation
);
3568 u32 aux_stride
= skl_plane_stride(fb
, 1, rotation
);
3569 u32 surf_addr
= plane_state
->main
.offset
;
3570 int scaler_id
= plane_state
->scaler_id
;
3571 int src_x
= plane_state
->main
.x
;
3572 int src_y
= plane_state
->main
.y
;
3573 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3574 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3575 int dst_x
= plane_state
->base
.dst
.x1
;
3576 int dst_y
= plane_state
->base
.dst
.y1
;
3577 int dst_w
= drm_rect_width(&plane_state
->base
.dst
);
3578 int dst_h
= drm_rect_height(&plane_state
->base
.dst
);
3579 unsigned long irqflags
;
3581 /* Sizes are 0 based */
3587 crtc
->dspaddr_offset
= surf_addr
;
3589 crtc
->adjusted_x
= src_x
;
3590 crtc
->adjusted_y
= src_y
;
3592 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3594 if (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
3595 I915_WRITE_FW(PLANE_COLOR_CTL(pipe
, plane_id
),
3596 PLANE_COLOR_PIPE_GAMMA_ENABLE
|
3597 PLANE_COLOR_PIPE_CSC_ENABLE
|
3598 PLANE_COLOR_PLANE_GAMMA_DISABLE
);
3601 I915_WRITE_FW(PLANE_CTL(pipe
, plane_id
), plane_ctl
);
3602 I915_WRITE_FW(PLANE_OFFSET(pipe
, plane_id
), (src_y
<< 16) | src_x
);
3603 I915_WRITE_FW(PLANE_STRIDE(pipe
, plane_id
), stride
);
3604 I915_WRITE_FW(PLANE_SIZE(pipe
, plane_id
), (src_h
<< 16) | src_w
);
3605 I915_WRITE_FW(PLANE_AUX_DIST(pipe
, plane_id
),
3606 (plane_state
->aux
.offset
- surf_addr
) | aux_stride
);
3607 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe
, plane_id
),
3608 (plane_state
->aux
.y
<< 16) | plane_state
->aux
.x
);
3610 if (scaler_id
>= 0) {
3611 uint32_t ps_ctrl
= 0;
3613 WARN_ON(!dst_w
|| !dst_h
);
3614 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(plane_id
) |
3615 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3616 I915_WRITE_FW(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3617 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3618 I915_WRITE_FW(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3619 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3620 I915_WRITE_FW(PLANE_POS(pipe
, plane_id
), 0);
3622 I915_WRITE_FW(PLANE_POS(pipe
, plane_id
), (dst_y
<< 16) | dst_x
);
3625 I915_WRITE_FW(PLANE_SURF(pipe
, plane_id
),
3626 intel_plane_ggtt_offset(plane_state
) + surf_addr
);
3628 POSTING_READ_FW(PLANE_SURF(pipe
, plane_id
));
3630 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3633 static void skylake_disable_primary_plane(struct intel_plane
*primary
,
3634 struct intel_crtc
*crtc
)
3636 struct drm_i915_private
*dev_priv
= to_i915(primary
->base
.dev
);
3637 enum plane_id plane_id
= primary
->id
;
3638 enum pipe pipe
= primary
->pipe
;
3639 unsigned long irqflags
;
3641 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3643 I915_WRITE_FW(PLANE_CTL(pipe
, plane_id
), 0);
3644 I915_WRITE_FW(PLANE_SURF(pipe
, plane_id
), 0);
3645 POSTING_READ_FW(PLANE_SURF(pipe
, plane_id
));
3647 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3651 __intel_display_resume(struct drm_device
*dev
,
3652 struct drm_atomic_state
*state
,
3653 struct drm_modeset_acquire_ctx
*ctx
)
3655 struct drm_crtc_state
*crtc_state
;
3656 struct drm_crtc
*crtc
;
3659 intel_modeset_setup_hw_state(dev
, ctx
);
3660 i915_redisable_vga(to_i915(dev
));
3666 * We've duplicated the state, pointers to the old state are invalid.
3668 * Don't attempt to use the old state until we commit the duplicated state.
3670 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3672 * Force recalculation even if we restore
3673 * current state. With fast modeset this may not result
3674 * in a modeset when the state is compatible.
3676 crtc_state
->mode_changed
= true;
3679 /* ignore any reset values/BIOS leftovers in the WM registers */
3680 if (!HAS_GMCH_DISPLAY(to_i915(dev
)))
3681 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
3683 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
3685 WARN_ON(ret
== -EDEADLK
);
3689 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
3691 return intel_has_gpu_reset(dev_priv
) &&
3692 INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
);
3695 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3697 struct drm_device
*dev
= &dev_priv
->drm
;
3698 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3699 struct drm_atomic_state
*state
;
3703 /* reset doesn't touch the display */
3704 if (!i915
.force_reset_modeset_test
&&
3705 !gpu_reset_clobbers_display(dev_priv
))
3708 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3709 set_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
3710 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
3712 if (atomic_read(&dev_priv
->gpu_error
.pending_fb_pin
)) {
3713 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3714 i915_gem_set_wedged(dev_priv
);
3718 * Need mode_config.mutex so that we don't
3719 * trample ongoing ->detect() and whatnot.
3721 mutex_lock(&dev
->mode_config
.mutex
);
3722 drm_modeset_acquire_init(ctx
, 0);
3724 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
3725 if (ret
!= -EDEADLK
)
3728 drm_modeset_backoff(ctx
);
3731 * Disabling the crtcs gracefully seems nicer. Also the
3732 * g33 docs say we should at least disable all the planes.
3734 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
3735 if (IS_ERR(state
)) {
3736 ret
= PTR_ERR(state
);
3737 DRM_ERROR("Duplicating state failed with %i\n", ret
);
3741 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
3743 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
3744 drm_atomic_state_put(state
);
3748 dev_priv
->modeset_restore_state
= state
;
3749 state
->acquire_ctx
= ctx
;
3752 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3754 struct drm_device
*dev
= &dev_priv
->drm
;
3755 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3756 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
3759 /* reset doesn't touch the display */
3760 if (!i915
.force_reset_modeset_test
&&
3761 !gpu_reset_clobbers_display(dev_priv
))
3767 dev_priv
->modeset_restore_state
= NULL
;
3769 /* reset doesn't touch the display */
3770 if (!gpu_reset_clobbers_display(dev_priv
)) {
3771 /* for testing only restore the display */
3772 ret
= __intel_display_resume(dev
, state
, ctx
);
3774 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3777 * The display has been reset as well,
3778 * so need a full re-initialization.
3780 intel_runtime_pm_disable_interrupts(dev_priv
);
3781 intel_runtime_pm_enable_interrupts(dev_priv
);
3783 intel_pps_unlock_regs_wa(dev_priv
);
3784 intel_modeset_init_hw(dev
);
3786 spin_lock_irq(&dev_priv
->irq_lock
);
3787 if (dev_priv
->display
.hpd_irq_setup
)
3788 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3789 spin_unlock_irq(&dev_priv
->irq_lock
);
3791 ret
= __intel_display_resume(dev
, state
, ctx
);
3793 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3795 intel_hpd_init(dev_priv
);
3798 drm_atomic_state_put(state
);
3800 drm_modeset_drop_locks(ctx
);
3801 drm_modeset_acquire_fini(ctx
);
3802 mutex_unlock(&dev
->mode_config
.mutex
);
3804 clear_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
3807 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3808 struct intel_crtc_state
*old_crtc_state
)
3810 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3811 struct intel_crtc_state
*pipe_config
=
3812 to_intel_crtc_state(crtc
->base
.state
);
3814 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3815 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3818 * Update pipe size and adjust fitter if needed: the reason for this is
3819 * that in compute_mode_changes we check the native mode (not the pfit
3820 * mode) to see if we can flip rather than do a full mode set. In the
3821 * fastboot case, we'll flip, but if we don't update the pipesrc and
3822 * pfit state, we'll end up with a big fb scanned out into the wrong
3826 I915_WRITE(PIPESRC(crtc
->pipe
),
3827 ((pipe_config
->pipe_src_w
- 1) << 16) |
3828 (pipe_config
->pipe_src_h
- 1));
3830 /* on skylake this is done by detaching scalers */
3831 if (INTEL_GEN(dev_priv
) >= 9) {
3832 skl_detach_scalers(crtc
);
3834 if (pipe_config
->pch_pfit
.enabled
)
3835 skylake_pfit_enable(crtc
);
3836 } else if (HAS_PCH_SPLIT(dev_priv
)) {
3837 if (pipe_config
->pch_pfit
.enabled
)
3838 ironlake_pfit_enable(crtc
);
3839 else if (old_crtc_state
->pch_pfit
.enabled
)
3840 ironlake_pfit_disable(crtc
, true);
3844 static void intel_fdi_normal_train(struct intel_crtc
*crtc
)
3846 struct drm_device
*dev
= crtc
->base
.dev
;
3847 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3848 int pipe
= crtc
->pipe
;
3852 /* enable normal train */
3853 reg
= FDI_TX_CTL(pipe
);
3854 temp
= I915_READ(reg
);
3855 if (IS_IVYBRIDGE(dev_priv
)) {
3856 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3857 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3859 temp
&= ~FDI_LINK_TRAIN_NONE
;
3860 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3862 I915_WRITE(reg
, temp
);
3864 reg
= FDI_RX_CTL(pipe
);
3865 temp
= I915_READ(reg
);
3866 if (HAS_PCH_CPT(dev_priv
)) {
3867 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3868 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3870 temp
&= ~FDI_LINK_TRAIN_NONE
;
3871 temp
|= FDI_LINK_TRAIN_NONE
;
3873 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3875 /* wait one idle pattern time */
3879 /* IVB wants error correction enabled */
3880 if (IS_IVYBRIDGE(dev_priv
))
3881 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3882 FDI_FE_ERRC_ENABLE
);
3885 /* The FDI link training functions for ILK/Ibexpeak. */
3886 static void ironlake_fdi_link_train(struct intel_crtc
*crtc
,
3887 const struct intel_crtc_state
*crtc_state
)
3889 struct drm_device
*dev
= crtc
->base
.dev
;
3890 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3891 int pipe
= crtc
->pipe
;
3895 /* FDI needs bits from pipe first */
3896 assert_pipe_enabled(dev_priv
, pipe
);
3898 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3900 reg
= FDI_RX_IMR(pipe
);
3901 temp
= I915_READ(reg
);
3902 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3903 temp
&= ~FDI_RX_BIT_LOCK
;
3904 I915_WRITE(reg
, temp
);
3908 /* enable CPU FDI TX and PCH FDI RX */
3909 reg
= FDI_TX_CTL(pipe
);
3910 temp
= I915_READ(reg
);
3911 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3912 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
3913 temp
&= ~FDI_LINK_TRAIN_NONE
;
3914 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3915 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3917 reg
= FDI_RX_CTL(pipe
);
3918 temp
= I915_READ(reg
);
3919 temp
&= ~FDI_LINK_TRAIN_NONE
;
3920 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3921 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3926 /* Ironlake workaround, enable clock pointer after FDI enable*/
3927 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3928 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3929 FDI_RX_PHASE_SYNC_POINTER_EN
);
3931 reg
= FDI_RX_IIR(pipe
);
3932 for (tries
= 0; tries
< 5; tries
++) {
3933 temp
= I915_READ(reg
);
3934 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3936 if ((temp
& FDI_RX_BIT_LOCK
)) {
3937 DRM_DEBUG_KMS("FDI train 1 done.\n");
3938 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3943 DRM_ERROR("FDI train 1 fail!\n");
3946 reg
= FDI_TX_CTL(pipe
);
3947 temp
= I915_READ(reg
);
3948 temp
&= ~FDI_LINK_TRAIN_NONE
;
3949 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3950 I915_WRITE(reg
, temp
);
3952 reg
= FDI_RX_CTL(pipe
);
3953 temp
= I915_READ(reg
);
3954 temp
&= ~FDI_LINK_TRAIN_NONE
;
3955 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3956 I915_WRITE(reg
, temp
);
3961 reg
= FDI_RX_IIR(pipe
);
3962 for (tries
= 0; tries
< 5; tries
++) {
3963 temp
= I915_READ(reg
);
3964 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3966 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3967 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3968 DRM_DEBUG_KMS("FDI train 2 done.\n");
3973 DRM_ERROR("FDI train 2 fail!\n");
3975 DRM_DEBUG_KMS("FDI train done\n");
3979 static const int snb_b_fdi_train_param
[] = {
3980 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3981 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3982 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3983 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3986 /* The FDI link training functions for SNB/Cougarpoint. */
3987 static void gen6_fdi_link_train(struct intel_crtc
*crtc
,
3988 const struct intel_crtc_state
*crtc_state
)
3990 struct drm_device
*dev
= crtc
->base
.dev
;
3991 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3992 int pipe
= crtc
->pipe
;
3996 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3998 reg
= FDI_RX_IMR(pipe
);
3999 temp
= I915_READ(reg
);
4000 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4001 temp
&= ~FDI_RX_BIT_LOCK
;
4002 I915_WRITE(reg
, temp
);
4007 /* enable CPU FDI TX and PCH FDI RX */
4008 reg
= FDI_TX_CTL(pipe
);
4009 temp
= I915_READ(reg
);
4010 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4011 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4012 temp
&= ~FDI_LINK_TRAIN_NONE
;
4013 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4014 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4016 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4017 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4019 I915_WRITE(FDI_RX_MISC(pipe
),
4020 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4022 reg
= FDI_RX_CTL(pipe
);
4023 temp
= I915_READ(reg
);
4024 if (HAS_PCH_CPT(dev_priv
)) {
4025 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4026 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4028 temp
&= ~FDI_LINK_TRAIN_NONE
;
4029 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4031 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4036 for (i
= 0; i
< 4; i
++) {
4037 reg
= FDI_TX_CTL(pipe
);
4038 temp
= I915_READ(reg
);
4039 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4040 temp
|= snb_b_fdi_train_param
[i
];
4041 I915_WRITE(reg
, temp
);
4046 for (retry
= 0; retry
< 5; retry
++) {
4047 reg
= FDI_RX_IIR(pipe
);
4048 temp
= I915_READ(reg
);
4049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4050 if (temp
& FDI_RX_BIT_LOCK
) {
4051 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4052 DRM_DEBUG_KMS("FDI train 1 done.\n");
4061 DRM_ERROR("FDI train 1 fail!\n");
4064 reg
= FDI_TX_CTL(pipe
);
4065 temp
= I915_READ(reg
);
4066 temp
&= ~FDI_LINK_TRAIN_NONE
;
4067 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4068 if (IS_GEN6(dev_priv
)) {
4069 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4071 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4073 I915_WRITE(reg
, temp
);
4075 reg
= FDI_RX_CTL(pipe
);
4076 temp
= I915_READ(reg
);
4077 if (HAS_PCH_CPT(dev_priv
)) {
4078 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4079 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4081 temp
&= ~FDI_LINK_TRAIN_NONE
;
4082 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4084 I915_WRITE(reg
, temp
);
4089 for (i
= 0; i
< 4; i
++) {
4090 reg
= FDI_TX_CTL(pipe
);
4091 temp
= I915_READ(reg
);
4092 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4093 temp
|= snb_b_fdi_train_param
[i
];
4094 I915_WRITE(reg
, temp
);
4099 for (retry
= 0; retry
< 5; retry
++) {
4100 reg
= FDI_RX_IIR(pipe
);
4101 temp
= I915_READ(reg
);
4102 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4103 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4104 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4105 DRM_DEBUG_KMS("FDI train 2 done.\n");
4114 DRM_ERROR("FDI train 2 fail!\n");
4116 DRM_DEBUG_KMS("FDI train done.\n");
4119 /* Manual link training for Ivy Bridge A0 parts */
4120 static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc
,
4121 const struct intel_crtc_state
*crtc_state
)
4123 struct drm_device
*dev
= crtc
->base
.dev
;
4124 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4125 int pipe
= crtc
->pipe
;
4129 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4131 reg
= FDI_RX_IMR(pipe
);
4132 temp
= I915_READ(reg
);
4133 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4134 temp
&= ~FDI_RX_BIT_LOCK
;
4135 I915_WRITE(reg
, temp
);
4140 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4141 I915_READ(FDI_RX_IIR(pipe
)));
4143 /* Try each vswing and preemphasis setting twice before moving on */
4144 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4145 /* disable first in case we need to retry */
4146 reg
= FDI_TX_CTL(pipe
);
4147 temp
= I915_READ(reg
);
4148 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4149 temp
&= ~FDI_TX_ENABLE
;
4150 I915_WRITE(reg
, temp
);
4152 reg
= FDI_RX_CTL(pipe
);
4153 temp
= I915_READ(reg
);
4154 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4155 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4156 temp
&= ~FDI_RX_ENABLE
;
4157 I915_WRITE(reg
, temp
);
4159 /* enable CPU FDI TX and PCH FDI RX */
4160 reg
= FDI_TX_CTL(pipe
);
4161 temp
= I915_READ(reg
);
4162 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4163 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4164 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4165 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4166 temp
|= snb_b_fdi_train_param
[j
/2];
4167 temp
|= FDI_COMPOSITE_SYNC
;
4168 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4170 I915_WRITE(FDI_RX_MISC(pipe
),
4171 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4173 reg
= FDI_RX_CTL(pipe
);
4174 temp
= I915_READ(reg
);
4175 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4176 temp
|= FDI_COMPOSITE_SYNC
;
4177 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4180 udelay(1); /* should be 0.5us */
4182 for (i
= 0; i
< 4; i
++) {
4183 reg
= FDI_RX_IIR(pipe
);
4184 temp
= I915_READ(reg
);
4185 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4187 if (temp
& FDI_RX_BIT_LOCK
||
4188 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4189 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4190 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4194 udelay(1); /* should be 0.5us */
4197 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4202 reg
= FDI_TX_CTL(pipe
);
4203 temp
= I915_READ(reg
);
4204 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4205 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4206 I915_WRITE(reg
, temp
);
4208 reg
= FDI_RX_CTL(pipe
);
4209 temp
= I915_READ(reg
);
4210 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4211 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4212 I915_WRITE(reg
, temp
);
4215 udelay(2); /* should be 1.5us */
4217 for (i
= 0; i
< 4; i
++) {
4218 reg
= FDI_RX_IIR(pipe
);
4219 temp
= I915_READ(reg
);
4220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4222 if (temp
& FDI_RX_SYMBOL_LOCK
||
4223 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4224 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4225 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4229 udelay(2); /* should be 1.5us */
4232 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4236 DRM_DEBUG_KMS("FDI train done.\n");
4239 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
4241 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4242 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4243 int pipe
= intel_crtc
->pipe
;
4247 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4248 reg
= FDI_RX_CTL(pipe
);
4249 temp
= I915_READ(reg
);
4250 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4251 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
4252 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4253 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4258 /* Switch from Rawclk to PCDclk */
4259 temp
= I915_READ(reg
);
4260 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4265 /* Enable CPU FDI TX PLL, always on for Ironlake */
4266 reg
= FDI_TX_CTL(pipe
);
4267 temp
= I915_READ(reg
);
4268 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4269 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4276 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4278 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4279 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4280 int pipe
= intel_crtc
->pipe
;
4284 /* Switch from PCDclk to Rawclk */
4285 reg
= FDI_RX_CTL(pipe
);
4286 temp
= I915_READ(reg
);
4287 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4289 /* Disable CPU FDI TX PLL */
4290 reg
= FDI_TX_CTL(pipe
);
4291 temp
= I915_READ(reg
);
4292 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4297 reg
= FDI_RX_CTL(pipe
);
4298 temp
= I915_READ(reg
);
4299 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4301 /* Wait for the clocks to turn off. */
4306 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4308 struct drm_device
*dev
= crtc
->dev
;
4309 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4311 int pipe
= intel_crtc
->pipe
;
4315 /* disable CPU FDI tx and PCH FDI rx */
4316 reg
= FDI_TX_CTL(pipe
);
4317 temp
= I915_READ(reg
);
4318 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4321 reg
= FDI_RX_CTL(pipe
);
4322 temp
= I915_READ(reg
);
4323 temp
&= ~(0x7 << 16);
4324 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4325 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4330 /* Ironlake workaround, disable clock pointer after downing FDI */
4331 if (HAS_PCH_IBX(dev_priv
))
4332 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4334 /* still set train pattern 1 */
4335 reg
= FDI_TX_CTL(pipe
);
4336 temp
= I915_READ(reg
);
4337 temp
&= ~FDI_LINK_TRAIN_NONE
;
4338 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4339 I915_WRITE(reg
, temp
);
4341 reg
= FDI_RX_CTL(pipe
);
4342 temp
= I915_READ(reg
);
4343 if (HAS_PCH_CPT(dev_priv
)) {
4344 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4345 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4347 temp
&= ~FDI_LINK_TRAIN_NONE
;
4348 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4350 /* BPC in FDI rx is consistent with that in PIPECONF */
4351 temp
&= ~(0x07 << 16);
4352 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4353 I915_WRITE(reg
, temp
);
4359 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4361 struct drm_crtc
*crtc
;
4364 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
4365 struct drm_crtc_commit
*commit
;
4366 spin_lock(&crtc
->commit_lock
);
4367 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4368 struct drm_crtc_commit
, commit_entry
);
4369 cleanup_done
= commit
?
4370 try_wait_for_completion(&commit
->cleanup_done
) : true;
4371 spin_unlock(&crtc
->commit_lock
);
4376 drm_crtc_wait_one_vblank(crtc
);
4384 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4388 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4390 mutex_lock(&dev_priv
->sb_lock
);
4392 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4393 temp
|= SBI_SSCCTL_DISABLE
;
4394 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4396 mutex_unlock(&dev_priv
->sb_lock
);
4399 /* Program iCLKIP clock to the desired frequency */
4400 static void lpt_program_iclkip(struct intel_crtc
*crtc
)
4402 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4403 int clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
4404 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4407 lpt_disable_iclkip(dev_priv
);
4409 /* The iCLK virtual clock root frequency is in MHz,
4410 * but the adjusted_mode->crtc_clock in in KHz. To get the
4411 * divisors, it is necessary to divide one by another, so we
4412 * convert the virtual clock precision to KHz here for higher
4415 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4416 u32 iclk_virtual_root_freq
= 172800 * 1000;
4417 u32 iclk_pi_range
= 64;
4418 u32 desired_divisor
;
4420 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4422 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4423 phaseinc
= desired_divisor
% iclk_pi_range
;
4426 * Near 20MHz is a corner case which is
4427 * out of range for the 7-bit divisor
4433 /* This should not happen with any sane values */
4434 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4435 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4436 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4437 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4439 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4446 mutex_lock(&dev_priv
->sb_lock
);
4448 /* Program SSCDIVINTPHASE6 */
4449 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4450 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4451 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4452 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4453 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4454 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4455 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4456 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4458 /* Program SSCAUXDIV */
4459 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4460 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4461 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4462 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4464 /* Enable modulator and associated divider */
4465 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4466 temp
&= ~SBI_SSCCTL_DISABLE
;
4467 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4469 mutex_unlock(&dev_priv
->sb_lock
);
4471 /* Wait for initialization time */
4474 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4477 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
4479 u32 divsel
, phaseinc
, auxdiv
;
4480 u32 iclk_virtual_root_freq
= 172800 * 1000;
4481 u32 iclk_pi_range
= 64;
4482 u32 desired_divisor
;
4485 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
4488 mutex_lock(&dev_priv
->sb_lock
);
4490 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4491 if (temp
& SBI_SSCCTL_DISABLE
) {
4492 mutex_unlock(&dev_priv
->sb_lock
);
4496 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4497 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
4498 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
4499 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
4500 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
4502 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4503 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
4504 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
4506 mutex_unlock(&dev_priv
->sb_lock
);
4508 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
4510 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4511 desired_divisor
<< auxdiv
);
4514 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4515 enum pipe pch_transcoder
)
4517 struct drm_device
*dev
= crtc
->base
.dev
;
4518 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4519 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4521 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4522 I915_READ(HTOTAL(cpu_transcoder
)));
4523 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4524 I915_READ(HBLANK(cpu_transcoder
)));
4525 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4526 I915_READ(HSYNC(cpu_transcoder
)));
4528 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4529 I915_READ(VTOTAL(cpu_transcoder
)));
4530 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4531 I915_READ(VBLANK(cpu_transcoder
)));
4532 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4533 I915_READ(VSYNC(cpu_transcoder
)));
4534 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4535 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4538 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4540 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4543 temp
= I915_READ(SOUTH_CHICKEN1
);
4544 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4547 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4548 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4550 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4552 temp
|= FDI_BC_BIFURCATION_SELECT
;
4554 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4555 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4556 POSTING_READ(SOUTH_CHICKEN1
);
4559 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4561 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4563 switch (intel_crtc
->pipe
) {
4567 if (intel_crtc
->config
->fdi_lanes
> 2)
4568 cpt_set_fdi_bc_bifurcation(dev
, false);
4570 cpt_set_fdi_bc_bifurcation(dev
, true);
4574 cpt_set_fdi_bc_bifurcation(dev
, true);
4582 /* Return which DP Port should be selected for Transcoder DP control */
4584 intel_trans_dp_port_sel(struct intel_crtc
*crtc
)
4586 struct drm_device
*dev
= crtc
->base
.dev
;
4587 struct intel_encoder
*encoder
;
4589 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
4590 if (encoder
->type
== INTEL_OUTPUT_DP
||
4591 encoder
->type
== INTEL_OUTPUT_EDP
)
4592 return enc_to_dig_port(&encoder
->base
)->port
;
4599 * Enable PCH resources required for PCH ports:
4601 * - FDI training & RX/TX
4602 * - update transcoder timings
4603 * - DP transcoding bits
4606 static void ironlake_pch_enable(const struct intel_crtc_state
*crtc_state
)
4608 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4609 struct drm_device
*dev
= crtc
->base
.dev
;
4610 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4611 int pipe
= crtc
->pipe
;
4614 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4616 if (IS_IVYBRIDGE(dev_priv
))
4617 ivybridge_update_fdi_bc_bifurcation(crtc
);
4619 /* Write the TU size bits before fdi link training, so that error
4620 * detection works. */
4621 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4622 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4624 /* For PCH output, training FDI link */
4625 dev_priv
->display
.fdi_link_train(crtc
, crtc_state
);
4627 /* We need to program the right clock selection before writing the pixel
4628 * mutliplier into the DPLL. */
4629 if (HAS_PCH_CPT(dev_priv
)) {
4632 temp
= I915_READ(PCH_DPLL_SEL
);
4633 temp
|= TRANS_DPLL_ENABLE(pipe
);
4634 sel
= TRANS_DPLLB_SEL(pipe
);
4635 if (crtc_state
->shared_dpll
==
4636 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4640 I915_WRITE(PCH_DPLL_SEL
, temp
);
4643 /* XXX: pch pll's can be enabled any time before we enable the PCH
4644 * transcoder, and we actually should do this to not upset any PCH
4645 * transcoder that already use the clock when we share it.
4647 * Note that enable_shared_dpll tries to do the right thing, but
4648 * get_shared_dpll unconditionally resets the pll - we need that to have
4649 * the right LVDS enable sequence. */
4650 intel_enable_shared_dpll(crtc
);
4652 /* set transcoder timing, panel must allow it */
4653 assert_panel_unlocked(dev_priv
, pipe
);
4654 ironlake_pch_transcoder_set_timings(crtc
, pipe
);
4656 intel_fdi_normal_train(crtc
);
4658 /* For PCH DP, enable TRANS_DP_CTL */
4659 if (HAS_PCH_CPT(dev_priv
) &&
4660 intel_crtc_has_dp_encoder(crtc_state
)) {
4661 const struct drm_display_mode
*adjusted_mode
=
4662 &crtc_state
->base
.adjusted_mode
;
4663 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4664 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4665 temp
= I915_READ(reg
);
4666 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4667 TRANS_DP_SYNC_MASK
|
4669 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4670 temp
|= bpc
<< 9; /* same format but at 11:9 */
4672 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4673 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4674 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4675 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4677 switch (intel_trans_dp_port_sel(crtc
)) {
4679 temp
|= TRANS_DP_PORT_SEL_B
;
4682 temp
|= TRANS_DP_PORT_SEL_C
;
4685 temp
|= TRANS_DP_PORT_SEL_D
;
4691 I915_WRITE(reg
, temp
);
4694 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4697 static void lpt_pch_enable(const struct intel_crtc_state
*crtc_state
)
4699 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4700 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4701 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
4703 assert_pch_transcoder_disabled(dev_priv
, PIPE_A
);
4705 lpt_program_iclkip(crtc
);
4707 /* Set transcoder timing. */
4708 ironlake_pch_transcoder_set_timings(crtc
, PIPE_A
);
4710 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4713 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4715 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4716 i915_reg_t dslreg
= PIPEDSL(pipe
);
4719 temp
= I915_READ(dslreg
);
4721 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4722 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4723 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4728 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4729 unsigned int scaler_user
, int *scaler_id
,
4730 int src_w
, int src_h
, int dst_w
, int dst_h
)
4732 struct intel_crtc_scaler_state
*scaler_state
=
4733 &crtc_state
->scaler_state
;
4734 struct intel_crtc
*intel_crtc
=
4735 to_intel_crtc(crtc_state
->base
.crtc
);
4736 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4737 const struct drm_display_mode
*adjusted_mode
=
4738 &crtc_state
->base
.adjusted_mode
;
4742 * Src coordinates are already rotated by 270 degrees for
4743 * the 90/270 degree plane rotation cases (to match the
4744 * GTT mapping), hence no need to account for rotation here.
4746 need_scaling
= src_w
!= dst_w
|| src_h
!= dst_h
;
4748 if (crtc_state
->ycbcr420
&& scaler_user
== SKL_CRTC_INDEX
)
4749 need_scaling
= true;
4752 * Scaling/fitting not supported in IF-ID mode in GEN9+
4753 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4754 * Once NV12 is enabled, handle it here while allocating scaler
4757 if (INTEL_GEN(dev_priv
) >= 9 && crtc_state
->base
.enable
&&
4758 need_scaling
&& adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4759 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4764 * if plane is being disabled or scaler is no more required or force detach
4765 * - free scaler binded to this plane/crtc
4766 * - in order to do this, update crtc->scaler_usage
4768 * Here scaler state in crtc_state is set free so that
4769 * scaler can be assigned to other user. Actual register
4770 * update to free the scaler is done in plane/panel-fit programming.
4771 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4773 if (force_detach
|| !need_scaling
) {
4774 if (*scaler_id
>= 0) {
4775 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4776 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4778 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4779 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4780 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4781 scaler_state
->scaler_users
);
4788 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4789 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4791 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4792 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4793 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4794 "size is out of scaler range\n",
4795 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4799 /* mark this plane as a scaler user in crtc_state */
4800 scaler_state
->scaler_users
|= (1 << scaler_user
);
4801 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4802 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4803 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4804 scaler_state
->scaler_users
);
4810 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4812 * @state: crtc's scaler state
4815 * 0 - scaler_usage updated successfully
4816 * error - requested scaling cannot be supported or other error condition
4818 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4820 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4822 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4823 &state
->scaler_state
.scaler_id
,
4824 state
->pipe_src_w
, state
->pipe_src_h
,
4825 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4829 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4831 * @state: crtc's scaler state
4832 * @plane_state: atomic plane state to update
4835 * 0 - scaler_usage updated successfully
4836 * error - requested scaling cannot be supported or other error condition
4838 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4839 struct intel_plane_state
*plane_state
)
4842 struct intel_plane
*intel_plane
=
4843 to_intel_plane(plane_state
->base
.plane
);
4844 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4847 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
4849 ret
= skl_update_scaler(crtc_state
, force_detach
,
4850 drm_plane_index(&intel_plane
->base
),
4851 &plane_state
->scaler_id
,
4852 drm_rect_width(&plane_state
->base
.src
) >> 16,
4853 drm_rect_height(&plane_state
->base
.src
) >> 16,
4854 drm_rect_width(&plane_state
->base
.dst
),
4855 drm_rect_height(&plane_state
->base
.dst
));
4857 if (ret
|| plane_state
->scaler_id
< 0)
4860 /* check colorkey */
4861 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4862 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4863 intel_plane
->base
.base
.id
,
4864 intel_plane
->base
.name
);
4868 /* Check src format */
4869 switch (fb
->format
->format
) {
4870 case DRM_FORMAT_RGB565
:
4871 case DRM_FORMAT_XBGR8888
:
4872 case DRM_FORMAT_XRGB8888
:
4873 case DRM_FORMAT_ABGR8888
:
4874 case DRM_FORMAT_ARGB8888
:
4875 case DRM_FORMAT_XRGB2101010
:
4876 case DRM_FORMAT_XBGR2101010
:
4877 case DRM_FORMAT_YUYV
:
4878 case DRM_FORMAT_YVYU
:
4879 case DRM_FORMAT_UYVY
:
4880 case DRM_FORMAT_VYUY
:
4883 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4884 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4885 fb
->base
.id
, fb
->format
->format
);
4892 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4896 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4897 skl_detach_scaler(crtc
, i
);
4900 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4902 struct drm_device
*dev
= crtc
->base
.dev
;
4903 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4904 int pipe
= crtc
->pipe
;
4905 struct intel_crtc_scaler_state
*scaler_state
=
4906 &crtc
->config
->scaler_state
;
4908 if (crtc
->config
->pch_pfit
.enabled
) {
4911 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0))
4914 id
= scaler_state
->scaler_id
;
4915 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4916 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4917 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4918 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4922 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4924 struct drm_device
*dev
= crtc
->base
.dev
;
4925 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4926 int pipe
= crtc
->pipe
;
4928 if (crtc
->config
->pch_pfit
.enabled
) {
4929 /* Force use of hard-coded filter coefficients
4930 * as some pre-programmed values are broken,
4933 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
4934 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4935 PF_PIPE_SEL_IVB(pipe
));
4937 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4938 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4939 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4943 void hsw_enable_ips(struct intel_crtc
*crtc
)
4945 struct drm_device
*dev
= crtc
->base
.dev
;
4946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4948 if (!crtc
->config
->ips_enabled
)
4952 * We can only enable IPS after we enable a plane and wait for a vblank
4953 * This function is called from post_plane_update, which is run after
4957 assert_plane_enabled(dev_priv
, crtc
->plane
);
4958 if (IS_BROADWELL(dev_priv
)) {
4959 mutex_lock(&dev_priv
->rps
.hw_lock
);
4960 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4961 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4962 /* Quoting Art Runyan: "its not safe to expect any particular
4963 * value in IPS_CTL bit 31 after enabling IPS through the
4964 * mailbox." Moreover, the mailbox may return a bogus state,
4965 * so we need to just enable it and continue on.
4968 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4969 /* The bit only becomes 1 in the next vblank, so this wait here
4970 * is essentially intel_wait_for_vblank. If we don't have this
4971 * and don't wait for vblanks until the end of crtc_enable, then
4972 * the HW state readout code will complain that the expected
4973 * IPS_CTL value is not the one we read. */
4974 if (intel_wait_for_register(dev_priv
,
4975 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
4977 DRM_ERROR("Timed out waiting for IPS enable\n");
4981 void hsw_disable_ips(struct intel_crtc
*crtc
)
4983 struct drm_device
*dev
= crtc
->base
.dev
;
4984 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4986 if (!crtc
->config
->ips_enabled
)
4989 assert_plane_enabled(dev_priv
, crtc
->plane
);
4990 if (IS_BROADWELL(dev_priv
)) {
4991 mutex_lock(&dev_priv
->rps
.hw_lock
);
4992 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4993 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4994 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4995 if (intel_wait_for_register(dev_priv
,
4996 IPS_CTL
, IPS_ENABLE
, 0,
4998 DRM_ERROR("Timed out waiting for IPS disable\n");
5000 I915_WRITE(IPS_CTL
, 0);
5001 POSTING_READ(IPS_CTL
);
5004 /* We need to wait for a vblank before we can disable the plane. */
5005 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5008 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
5010 if (intel_crtc
->overlay
) {
5011 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5013 mutex_lock(&dev
->struct_mutex
);
5014 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
5015 mutex_unlock(&dev
->struct_mutex
);
5018 /* Let userspace switch the overlay on again. In most cases userspace
5019 * has to recompute where to put it anyway.
5024 * intel_post_enable_primary - Perform operations after enabling primary plane
5025 * @crtc: the CRTC whose primary plane was just enabled
5027 * Performs potentially sleeping operations that must be done after the primary
5028 * plane is enabled, such as updating FBC and IPS. Note that this may be
5029 * called due to an explicit primary plane update, or due to an implicit
5030 * re-enable that is caused when a sprite plane is updated to no longer
5031 * completely hide the primary plane.
5034 intel_post_enable_primary(struct drm_crtc
*crtc
)
5036 struct drm_device
*dev
= crtc
->dev
;
5037 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5038 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5039 int pipe
= intel_crtc
->pipe
;
5042 * FIXME IPS should be fine as long as one plane is
5043 * enabled, but in practice it seems to have problems
5044 * when going from primary only to sprite only and vice
5047 hsw_enable_ips(intel_crtc
);
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5056 if (IS_GEN2(dev_priv
))
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5059 /* Underruns don't always raise interrupts, so check manually. */
5060 intel_check_cpu_fifo_underruns(dev_priv
);
5061 intel_check_pch_fifo_underruns(dev_priv
);
5064 /* FIXME move all this to pre_plane_update() with proper state tracking */
5066 intel_pre_disable_primary(struct drm_crtc
*crtc
)
5068 struct drm_device
*dev
= crtc
->dev
;
5069 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5070 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5071 int pipe
= intel_crtc
->pipe
;
5074 * Gen2 reports pipe underruns whenever all planes are disabled.
5075 * So diasble underrun reporting before all the planes get disabled.
5076 * FIXME: Need to fix the logic to work when we turn off all planes
5077 * but leave the pipe running.
5079 if (IS_GEN2(dev_priv
))
5080 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5083 * FIXME IPS should be fine as long as one plane is
5084 * enabled, but in practice it seems to have problems
5085 * when going from primary only to sprite only and vice
5088 hsw_disable_ips(intel_crtc
);
5091 /* FIXME get rid of this and use pre_plane_update */
5093 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5095 struct drm_device
*dev
= crtc
->dev
;
5096 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5097 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5098 int pipe
= intel_crtc
->pipe
;
5100 intel_pre_disable_primary(crtc
);
5103 * Vblank time updates from the shadow to live plane control register
5104 * are blocked if the memory self-refresh mode is active at that
5105 * moment. So to make sure the plane gets truly disabled, disable
5106 * first the self-refresh mode. The self-refresh enable bit in turn
5107 * will be checked/applied by the HW only at the next frame start
5108 * event which is after the vblank start event, so we need to have a
5109 * wait-for-vblank between disabling the plane and the pipe.
5111 if (HAS_GMCH_DISPLAY(dev_priv
) &&
5112 intel_set_memory_cxsr(dev_priv
, false))
5113 intel_wait_for_vblank(dev_priv
, pipe
);
5116 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5118 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5119 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5120 struct intel_crtc_state
*pipe_config
=
5121 to_intel_crtc_state(crtc
->base
.state
);
5122 struct drm_plane
*primary
= crtc
->base
.primary
;
5123 struct drm_plane_state
*old_pri_state
=
5124 drm_atomic_get_existing_plane_state(old_state
, primary
);
5126 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5128 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5129 intel_update_watermarks(crtc
);
5131 if (old_pri_state
) {
5132 struct intel_plane_state
*primary_state
=
5133 to_intel_plane_state(primary
->state
);
5134 struct intel_plane_state
*old_primary_state
=
5135 to_intel_plane_state(old_pri_state
);
5137 intel_fbc_post_update(crtc
);
5139 if (primary_state
->base
.visible
&&
5140 (needs_modeset(&pipe_config
->base
) ||
5141 !old_primary_state
->base
.visible
))
5142 intel_post_enable_primary(&crtc
->base
);
5146 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
,
5147 struct intel_crtc_state
*pipe_config
)
5149 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5150 struct drm_device
*dev
= crtc
->base
.dev
;
5151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5152 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5153 struct drm_plane
*primary
= crtc
->base
.primary
;
5154 struct drm_plane_state
*old_pri_state
=
5155 drm_atomic_get_existing_plane_state(old_state
, primary
);
5156 bool modeset
= needs_modeset(&pipe_config
->base
);
5157 struct intel_atomic_state
*old_intel_state
=
5158 to_intel_atomic_state(old_state
);
5160 if (old_pri_state
) {
5161 struct intel_plane_state
*primary_state
=
5162 to_intel_plane_state(primary
->state
);
5163 struct intel_plane_state
*old_primary_state
=
5164 to_intel_plane_state(old_pri_state
);
5166 intel_fbc_pre_update(crtc
, pipe_config
, primary_state
);
5168 if (old_primary_state
->base
.visible
&&
5169 (modeset
|| !primary_state
->base
.visible
))
5170 intel_pre_disable_primary(&crtc
->base
);
5174 * Vblank time updates from the shadow to live plane control register
5175 * are blocked if the memory self-refresh mode is active at that
5176 * moment. So to make sure the plane gets truly disabled, disable
5177 * first the self-refresh mode. The self-refresh enable bit in turn
5178 * will be checked/applied by the HW only at the next frame start
5179 * event which is after the vblank start event, so we need to have a
5180 * wait-for-vblank between disabling the plane and the pipe.
5182 if (HAS_GMCH_DISPLAY(dev_priv
) && old_crtc_state
->base
.active
&&
5183 pipe_config
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
5184 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5187 * IVB workaround: must disable low power watermarks for at least
5188 * one frame before enabling scaling. LP watermarks can be re-enabled
5189 * when scaling is disabled.
5191 * WaCxSRDisabledForSpriteScaling:ivb
5193 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
))
5194 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5197 * If we're doing a modeset, we're done. No need to do any pre-vblank
5198 * watermark programming here.
5200 if (needs_modeset(&pipe_config
->base
))
5204 * For platforms that support atomic watermarks, program the
5205 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5206 * will be the intermediate values that are safe for both pre- and
5207 * post- vblank; when vblank happens, the 'active' values will be set
5208 * to the final 'target' values and we'll do this again to get the
5209 * optimal watermarks. For gen9+ platforms, the values we program here
5210 * will be the final target values which will get automatically latched
5211 * at vblank time; no further programming will be necessary.
5213 * If a platform hasn't been transitioned to atomic watermarks yet,
5214 * we'll continue to update watermarks the old way, if flags tell
5217 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5218 dev_priv
->display
.initial_watermarks(old_intel_state
,
5220 else if (pipe_config
->update_wm_pre
)
5221 intel_update_watermarks(crtc
);
5224 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
5226 struct drm_device
*dev
= crtc
->dev
;
5227 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5228 struct drm_plane
*p
;
5229 int pipe
= intel_crtc
->pipe
;
5231 intel_crtc_dpms_overlay_disable(intel_crtc
);
5233 drm_for_each_plane_mask(p
, dev
, plane_mask
)
5234 to_intel_plane(p
)->disable_plane(to_intel_plane(p
), intel_crtc
);
5237 * FIXME: Once we grow proper nuclear flip support out of this we need
5238 * to compute the mask of flip planes precisely. For the time being
5239 * consider this a flip to a NULL plane.
5241 intel_frontbuffer_flip(to_i915(dev
), INTEL_FRONTBUFFER_ALL_MASK(pipe
));
5244 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
5245 struct intel_crtc_state
*crtc_state
,
5246 struct drm_atomic_state
*old_state
)
5248 struct drm_connector_state
*conn_state
;
5249 struct drm_connector
*conn
;
5252 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5253 struct intel_encoder
*encoder
=
5254 to_intel_encoder(conn_state
->best_encoder
);
5256 if (conn_state
->crtc
!= crtc
)
5259 if (encoder
->pre_pll_enable
)
5260 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
5264 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
5265 struct intel_crtc_state
*crtc_state
,
5266 struct drm_atomic_state
*old_state
)
5268 struct drm_connector_state
*conn_state
;
5269 struct drm_connector
*conn
;
5272 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5273 struct intel_encoder
*encoder
=
5274 to_intel_encoder(conn_state
->best_encoder
);
5276 if (conn_state
->crtc
!= crtc
)
5279 if (encoder
->pre_enable
)
5280 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
5284 static void intel_encoders_enable(struct drm_crtc
*crtc
,
5285 struct intel_crtc_state
*crtc_state
,
5286 struct drm_atomic_state
*old_state
)
5288 struct drm_connector_state
*conn_state
;
5289 struct drm_connector
*conn
;
5292 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5293 struct intel_encoder
*encoder
=
5294 to_intel_encoder(conn_state
->best_encoder
);
5296 if (conn_state
->crtc
!= crtc
)
5299 encoder
->enable(encoder
, crtc_state
, conn_state
);
5300 intel_opregion_notify_encoder(encoder
, true);
5304 static void intel_encoders_disable(struct drm_crtc
*crtc
,
5305 struct intel_crtc_state
*old_crtc_state
,
5306 struct drm_atomic_state
*old_state
)
5308 struct drm_connector_state
*old_conn_state
;
5309 struct drm_connector
*conn
;
5312 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5313 struct intel_encoder
*encoder
=
5314 to_intel_encoder(old_conn_state
->best_encoder
);
5316 if (old_conn_state
->crtc
!= crtc
)
5319 intel_opregion_notify_encoder(encoder
, false);
5320 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
5324 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
5325 struct intel_crtc_state
*old_crtc_state
,
5326 struct drm_atomic_state
*old_state
)
5328 struct drm_connector_state
*old_conn_state
;
5329 struct drm_connector
*conn
;
5332 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5333 struct intel_encoder
*encoder
=
5334 to_intel_encoder(old_conn_state
->best_encoder
);
5336 if (old_conn_state
->crtc
!= crtc
)
5339 if (encoder
->post_disable
)
5340 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
5344 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
5345 struct intel_crtc_state
*old_crtc_state
,
5346 struct drm_atomic_state
*old_state
)
5348 struct drm_connector_state
*old_conn_state
;
5349 struct drm_connector
*conn
;
5352 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5353 struct intel_encoder
*encoder
=
5354 to_intel_encoder(old_conn_state
->best_encoder
);
5356 if (old_conn_state
->crtc
!= crtc
)
5359 if (encoder
->post_pll_disable
)
5360 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
5364 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
5365 struct drm_atomic_state
*old_state
)
5367 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5368 struct drm_device
*dev
= crtc
->dev
;
5369 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5370 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5371 int pipe
= intel_crtc
->pipe
;
5372 struct intel_atomic_state
*old_intel_state
=
5373 to_intel_atomic_state(old_state
);
5375 if (WARN_ON(intel_crtc
->active
))
5379 * Sometimes spurious CPU pipe underruns happen during FDI
5380 * training, at least with VGA+HDMI cloning. Suppress them.
5382 * On ILK we get an occasional spurious CPU pipe underruns
5383 * between eDP port A enable and vdd enable. Also PCH port
5384 * enable seems to result in the occasional CPU pipe underrun.
5386 * Spurious PCH underruns also occur during PCH enabling.
5388 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
5389 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5390 if (intel_crtc
->config
->has_pch_encoder
)
5391 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5393 if (intel_crtc
->config
->has_pch_encoder
)
5394 intel_prepare_shared_dpll(intel_crtc
);
5396 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5397 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5399 intel_set_pipe_timings(intel_crtc
);
5400 intel_set_pipe_src_size(intel_crtc
);
5402 if (intel_crtc
->config
->has_pch_encoder
) {
5403 intel_cpu_transcoder_set_m_n(intel_crtc
,
5404 &intel_crtc
->config
->fdi_m_n
, NULL
);
5407 ironlake_set_pipeconf(crtc
);
5409 intel_crtc
->active
= true;
5411 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5413 if (intel_crtc
->config
->has_pch_encoder
) {
5414 /* Note: FDI PLL enabling _must_ be done before we enable the
5415 * cpu pipes, hence this is separate from all the other fdi/pch
5417 ironlake_fdi_pll_enable(intel_crtc
);
5419 assert_fdi_tx_disabled(dev_priv
, pipe
);
5420 assert_fdi_rx_disabled(dev_priv
, pipe
);
5423 ironlake_pfit_enable(intel_crtc
);
5426 * On ILK+ LUT must be loaded before the pipe is running but with
5429 intel_color_load_luts(&pipe_config
->base
);
5431 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5432 dev_priv
->display
.initial_watermarks(old_intel_state
, intel_crtc
->config
);
5433 intel_enable_pipe(intel_crtc
);
5435 if (intel_crtc
->config
->has_pch_encoder
)
5436 ironlake_pch_enable(pipe_config
);
5438 assert_vblank_disabled(crtc
);
5439 drm_crtc_vblank_on(crtc
);
5441 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5443 if (HAS_PCH_CPT(dev_priv
))
5444 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
5446 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5447 if (intel_crtc
->config
->has_pch_encoder
)
5448 intel_wait_for_vblank(dev_priv
, pipe
);
5449 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5450 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5453 /* IPS only exists on ULT machines and is tied to pipe A. */
5454 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
5456 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
5459 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
5460 struct drm_atomic_state
*old_state
)
5462 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5463 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5465 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
5466 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5467 struct intel_atomic_state
*old_intel_state
=
5468 to_intel_atomic_state(old_state
);
5470 if (WARN_ON(intel_crtc
->active
))
5473 if (intel_crtc
->config
->has_pch_encoder
)
5474 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
5476 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5478 if (intel_crtc
->config
->shared_dpll
)
5479 intel_enable_shared_dpll(intel_crtc
);
5481 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5482 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5484 if (!transcoder_is_dsi(cpu_transcoder
))
5485 intel_set_pipe_timings(intel_crtc
);
5487 intel_set_pipe_src_size(intel_crtc
);
5489 if (cpu_transcoder
!= TRANSCODER_EDP
&&
5490 !transcoder_is_dsi(cpu_transcoder
)) {
5491 I915_WRITE(PIPE_MULT(cpu_transcoder
),
5492 intel_crtc
->config
->pixel_multiplier
- 1);
5495 if (intel_crtc
->config
->has_pch_encoder
) {
5496 intel_cpu_transcoder_set_m_n(intel_crtc
,
5497 &intel_crtc
->config
->fdi_m_n
, NULL
);
5500 if (!transcoder_is_dsi(cpu_transcoder
))
5501 haswell_set_pipeconf(crtc
);
5503 haswell_set_pipemisc(crtc
);
5505 intel_color_set_csc(&pipe_config
->base
);
5507 intel_crtc
->active
= true;
5509 if (intel_crtc
->config
->has_pch_encoder
)
5510 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5512 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5514 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5516 if (intel_crtc
->config
->has_pch_encoder
)
5517 dev_priv
->display
.fdi_link_train(intel_crtc
, pipe_config
);
5519 if (!transcoder_is_dsi(cpu_transcoder
))
5520 intel_ddi_enable_pipe_clock(pipe_config
);
5522 if (INTEL_GEN(dev_priv
) >= 9)
5523 skylake_pfit_enable(intel_crtc
);
5525 ironlake_pfit_enable(intel_crtc
);
5528 * On ILK+ LUT must be loaded before the pipe is running but with
5531 intel_color_load_luts(&pipe_config
->base
);
5533 intel_ddi_set_pipe_settings(pipe_config
);
5534 if (!transcoder_is_dsi(cpu_transcoder
))
5535 intel_ddi_enable_transcoder_func(pipe_config
);
5537 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5538 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
5540 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5541 if (!transcoder_is_dsi(cpu_transcoder
))
5542 intel_enable_pipe(intel_crtc
);
5544 if (intel_crtc
->config
->has_pch_encoder
)
5545 lpt_pch_enable(pipe_config
);
5547 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5548 intel_ddi_set_vc_payload_alloc(pipe_config
, true);
5550 assert_vblank_disabled(crtc
);
5551 drm_crtc_vblank_on(crtc
);
5553 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5555 if (intel_crtc
->config
->has_pch_encoder
) {
5556 intel_wait_for_vblank(dev_priv
, pipe
);
5557 intel_wait_for_vblank(dev_priv
, pipe
);
5558 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5559 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
5562 /* If we change the relative order between pipe/planes enabling, we need
5563 * to change the workaround. */
5564 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
5565 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5566 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5567 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5571 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
5573 struct drm_device
*dev
= crtc
->base
.dev
;
5574 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5575 int pipe
= crtc
->pipe
;
5577 /* To avoid upsetting the power well on haswell only disable the pfit if
5578 * it's in use. The hw state code will make sure we get this right. */
5579 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
5580 I915_WRITE(PF_CTL(pipe
), 0);
5581 I915_WRITE(PF_WIN_POS(pipe
), 0);
5582 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5586 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5587 struct drm_atomic_state
*old_state
)
5589 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5590 struct drm_device
*dev
= crtc
->dev
;
5591 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5592 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5593 int pipe
= intel_crtc
->pipe
;
5596 * Sometimes spurious CPU pipe underruns happen when the
5597 * pipe is already disabled, but FDI RX/TX is still enabled.
5598 * Happens at least with VGA+HDMI cloning. Suppress them.
5600 if (intel_crtc
->config
->has_pch_encoder
) {
5601 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5602 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5605 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5607 drm_crtc_vblank_off(crtc
);
5608 assert_vblank_disabled(crtc
);
5610 intel_disable_pipe(intel_crtc
);
5612 ironlake_pfit_disable(intel_crtc
, false);
5614 if (intel_crtc
->config
->has_pch_encoder
)
5615 ironlake_fdi_disable(crtc
);
5617 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5619 if (intel_crtc
->config
->has_pch_encoder
) {
5620 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5622 if (HAS_PCH_CPT(dev_priv
)) {
5626 /* disable TRANS_DP_CTL */
5627 reg
= TRANS_DP_CTL(pipe
);
5628 temp
= I915_READ(reg
);
5629 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5630 TRANS_DP_PORT_SEL_MASK
);
5631 temp
|= TRANS_DP_PORT_SEL_NONE
;
5632 I915_WRITE(reg
, temp
);
5634 /* disable DPLL_SEL */
5635 temp
= I915_READ(PCH_DPLL_SEL
);
5636 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5637 I915_WRITE(PCH_DPLL_SEL
, temp
);
5640 ironlake_fdi_pll_disable(intel_crtc
);
5643 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5644 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5647 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5648 struct drm_atomic_state
*old_state
)
5650 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5651 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5653 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5655 if (intel_crtc
->config
->has_pch_encoder
)
5656 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
5658 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5660 drm_crtc_vblank_off(crtc
);
5661 assert_vblank_disabled(crtc
);
5663 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5664 if (!transcoder_is_dsi(cpu_transcoder
))
5665 intel_disable_pipe(intel_crtc
);
5667 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5668 intel_ddi_set_vc_payload_alloc(intel_crtc
->config
, false);
5670 if (!transcoder_is_dsi(cpu_transcoder
))
5671 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5673 if (INTEL_GEN(dev_priv
) >= 9)
5674 skylake_scaler_disable(intel_crtc
);
5676 ironlake_pfit_disable(intel_crtc
, false);
5678 if (!transcoder_is_dsi(cpu_transcoder
))
5679 intel_ddi_disable_pipe_clock(intel_crtc
->config
);
5681 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5683 if (old_crtc_state
->has_pch_encoder
)
5684 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
5687 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5689 struct drm_device
*dev
= crtc
->base
.dev
;
5690 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5691 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5693 if (!pipe_config
->gmch_pfit
.control
)
5697 * The panel fitter should only be adjusted whilst the pipe is disabled,
5698 * according to register description and PRM.
5700 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5701 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5703 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5704 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5706 /* Border color in case we don't scale up to the full screen. Black by
5707 * default, change to something else for debugging. */
5708 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5711 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
)
5715 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5717 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5719 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5721 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5723 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5726 return POWER_DOMAIN_PORT_OTHER
;
5730 static u64
get_crtc_power_domains(struct drm_crtc
*crtc
,
5731 struct intel_crtc_state
*crtc_state
)
5733 struct drm_device
*dev
= crtc
->dev
;
5734 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5735 struct drm_encoder
*encoder
;
5736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5737 enum pipe pipe
= intel_crtc
->pipe
;
5739 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5741 if (!crtc_state
->base
.active
)
5744 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5745 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5746 if (crtc_state
->pch_pfit
.enabled
||
5747 crtc_state
->pch_pfit
.force_thru
)
5748 mask
|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5750 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5751 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5753 mask
|= BIT_ULL(intel_encoder
->power_domain
);
5756 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
5757 mask
|= BIT(POWER_DOMAIN_AUDIO
);
5759 if (crtc_state
->shared_dpll
)
5760 mask
|= BIT_ULL(POWER_DOMAIN_PLLS
);
5766 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5767 struct intel_crtc_state
*crtc_state
)
5769 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5771 enum intel_display_power_domain domain
;
5772 u64 domains
, new_domains
, old_domains
;
5774 old_domains
= intel_crtc
->enabled_power_domains
;
5775 intel_crtc
->enabled_power_domains
= new_domains
=
5776 get_crtc_power_domains(crtc
, crtc_state
);
5778 domains
= new_domains
& ~old_domains
;
5780 for_each_power_domain(domain
, domains
)
5781 intel_display_power_get(dev_priv
, domain
);
5783 return old_domains
& ~new_domains
;
5786 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5789 enum intel_display_power_domain domain
;
5791 for_each_power_domain(domain
, domains
)
5792 intel_display_power_put(dev_priv
, domain
);
5795 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
5796 struct drm_atomic_state
*old_state
)
5798 struct intel_atomic_state
*old_intel_state
=
5799 to_intel_atomic_state(old_state
);
5800 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5801 struct drm_device
*dev
= crtc
->dev
;
5802 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5803 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5804 int pipe
= intel_crtc
->pipe
;
5806 if (WARN_ON(intel_crtc
->active
))
5809 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5810 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5812 intel_set_pipe_timings(intel_crtc
);
5813 intel_set_pipe_src_size(intel_crtc
);
5815 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
5816 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5818 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5819 I915_WRITE(CHV_CANVAS(pipe
), 0);
5822 i9xx_set_pipeconf(intel_crtc
);
5824 intel_crtc
->active
= true;
5826 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5828 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5830 if (IS_CHERRYVIEW(dev_priv
)) {
5831 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5832 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5834 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5835 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5838 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5840 i9xx_pfit_enable(intel_crtc
);
5842 intel_color_load_luts(&pipe_config
->base
);
5844 dev_priv
->display
.initial_watermarks(old_intel_state
,
5846 intel_enable_pipe(intel_crtc
);
5848 assert_vblank_disabled(crtc
);
5849 drm_crtc_vblank_on(crtc
);
5851 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5854 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5856 struct drm_device
*dev
= crtc
->base
.dev
;
5857 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5859 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5860 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5863 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
5864 struct drm_atomic_state
*old_state
)
5866 struct intel_atomic_state
*old_intel_state
=
5867 to_intel_atomic_state(old_state
);
5868 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5869 struct drm_device
*dev
= crtc
->dev
;
5870 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5872 enum pipe pipe
= intel_crtc
->pipe
;
5874 if (WARN_ON(intel_crtc
->active
))
5877 i9xx_set_pll_dividers(intel_crtc
);
5879 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5880 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5882 intel_set_pipe_timings(intel_crtc
);
5883 intel_set_pipe_src_size(intel_crtc
);
5885 i9xx_set_pipeconf(intel_crtc
);
5887 intel_crtc
->active
= true;
5889 if (!IS_GEN2(dev_priv
))
5890 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5892 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5894 i9xx_enable_pll(intel_crtc
);
5896 i9xx_pfit_enable(intel_crtc
);
5898 intel_color_load_luts(&pipe_config
->base
);
5900 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5901 dev_priv
->display
.initial_watermarks(old_intel_state
,
5902 intel_crtc
->config
);
5904 intel_update_watermarks(intel_crtc
);
5905 intel_enable_pipe(intel_crtc
);
5907 assert_vblank_disabled(crtc
);
5908 drm_crtc_vblank_on(crtc
);
5910 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5913 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5915 struct drm_device
*dev
= crtc
->base
.dev
;
5916 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5918 if (!crtc
->config
->gmch_pfit
.control
)
5921 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5923 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5924 I915_READ(PFIT_CONTROL
));
5925 I915_WRITE(PFIT_CONTROL
, 0);
5928 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5929 struct drm_atomic_state
*old_state
)
5931 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5932 struct drm_device
*dev
= crtc
->dev
;
5933 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5935 int pipe
= intel_crtc
->pipe
;
5938 * On gen2 planes are double buffered but the pipe isn't, so we must
5939 * wait for planes to fully turn off before disabling the pipe.
5941 if (IS_GEN2(dev_priv
))
5942 intel_wait_for_vblank(dev_priv
, pipe
);
5944 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5946 drm_crtc_vblank_off(crtc
);
5947 assert_vblank_disabled(crtc
);
5949 intel_disable_pipe(intel_crtc
);
5951 i9xx_pfit_disable(intel_crtc
);
5953 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5955 if (!intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DSI
)) {
5956 if (IS_CHERRYVIEW(dev_priv
))
5957 chv_disable_pll(dev_priv
, pipe
);
5958 else if (IS_VALLEYVIEW(dev_priv
))
5959 vlv_disable_pll(dev_priv
, pipe
);
5961 i9xx_disable_pll(intel_crtc
);
5964 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
5966 if (!IS_GEN2(dev_priv
))
5967 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5969 if (!dev_priv
->display
.initial_watermarks
)
5970 intel_update_watermarks(intel_crtc
);
5972 /* clock the pipe down to 640x480@60 to potentially save power */
5973 if (IS_I830(dev_priv
))
5974 i830_enable_pipe(dev_priv
, pipe
);
5977 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
,
5978 struct drm_modeset_acquire_ctx
*ctx
)
5980 struct intel_encoder
*encoder
;
5981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5982 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5983 enum intel_display_power_domain domain
;
5985 struct drm_atomic_state
*state
;
5986 struct intel_crtc_state
*crtc_state
;
5989 if (!intel_crtc
->active
)
5992 if (crtc
->primary
->state
->visible
) {
5993 intel_pre_disable_primary_noatomic(crtc
);
5995 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
5996 crtc
->primary
->state
->visible
= false;
5999 state
= drm_atomic_state_alloc(crtc
->dev
);
6001 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6002 crtc
->base
.id
, crtc
->name
);
6006 state
->acquire_ctx
= ctx
;
6008 /* Everything's already locked, -EDEADLK can't happen. */
6009 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6010 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6012 WARN_ON(IS_ERR(crtc_state
) || ret
);
6014 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6016 drm_atomic_state_put(state
);
6018 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6019 crtc
->base
.id
, crtc
->name
);
6021 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6022 crtc
->state
->active
= false;
6023 intel_crtc
->active
= false;
6024 crtc
->enabled
= false;
6025 crtc
->state
->connector_mask
= 0;
6026 crtc
->state
->encoder_mask
= 0;
6028 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6029 encoder
->base
.crtc
= NULL
;
6031 intel_fbc_disable(intel_crtc
);
6032 intel_update_watermarks(intel_crtc
);
6033 intel_disable_shared_dpll(intel_crtc
);
6035 domains
= intel_crtc
->enabled_power_domains
;
6036 for_each_power_domain(domain
, domains
)
6037 intel_display_power_put(dev_priv
, domain
);
6038 intel_crtc
->enabled_power_domains
= 0;
6040 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6041 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6045 * turn all crtc's off, but do not adjust state
6046 * This has to be paired with a call to intel_modeset_setup_hw_state.
6048 int intel_display_suspend(struct drm_device
*dev
)
6050 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6051 struct drm_atomic_state
*state
;
6054 state
= drm_atomic_helper_suspend(dev
);
6055 ret
= PTR_ERR_OR_ZERO(state
);
6057 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6059 dev_priv
->modeset_restore_state
= state
;
6063 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6065 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6067 drm_encoder_cleanup(encoder
);
6068 kfree(intel_encoder
);
6071 /* Cross check the actual hw state with our own modeset state tracking (and it's
6072 * internal consistency). */
6073 static void intel_connector_verify_state(struct drm_crtc_state
*crtc_state
,
6074 struct drm_connector_state
*conn_state
)
6076 struct intel_connector
*connector
= to_intel_connector(conn_state
->connector
);
6078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6079 connector
->base
.base
.id
,
6080 connector
->base
.name
);
6082 if (connector
->get_hw_state(connector
)) {
6083 struct intel_encoder
*encoder
= connector
->encoder
;
6085 I915_STATE_WARN(!crtc_state
,
6086 "connector enabled without attached crtc\n");
6091 I915_STATE_WARN(!crtc_state
->active
,
6092 "connector is active, but attached crtc isn't\n");
6094 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6097 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6098 "atomic encoder doesn't match attached encoder\n");
6100 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6101 "attached encoder crtc differs from connector crtc\n");
6103 I915_STATE_WARN(crtc_state
&& crtc_state
->active
,
6104 "attached crtc is active, but connector isn't\n");
6105 I915_STATE_WARN(!crtc_state
&& conn_state
->best_encoder
,
6106 "best encoder set without crtc!\n");
6110 int intel_connector_init(struct intel_connector
*connector
)
6112 struct intel_digital_connector_state
*conn_state
;
6115 * Allocate enough memory to hold intel_digital_connector_state,
6116 * This might be a few bytes too many, but for connectors that don't
6117 * need it we'll free the state and allocate a smaller one on the first
6118 * succesful commit anyway.
6120 conn_state
= kzalloc(sizeof(*conn_state
), GFP_KERNEL
);
6124 __drm_atomic_helper_connector_reset(&connector
->base
,
6130 struct intel_connector
*intel_connector_alloc(void)
6132 struct intel_connector
*connector
;
6134 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6138 if (intel_connector_init(connector
) < 0) {
6146 /* Simple connector->get_hw_state implementation for encoders that support only
6147 * one connector and no cloning and hence the encoder state determines the state
6148 * of the connector. */
6149 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6152 struct intel_encoder
*encoder
= connector
->encoder
;
6154 return encoder
->get_hw_state(encoder
, &pipe
);
6157 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6159 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6160 return crtc_state
->fdi_lanes
;
6165 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6166 struct intel_crtc_state
*pipe_config
)
6168 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6169 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6170 struct intel_crtc
*other_crtc
;
6171 struct intel_crtc_state
*other_crtc_state
;
6173 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6174 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6175 if (pipe_config
->fdi_lanes
> 4) {
6176 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6177 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6181 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
6182 if (pipe_config
->fdi_lanes
> 2) {
6183 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6184 pipe_config
->fdi_lanes
);
6191 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
6194 /* Ivybridge 3 pipe is really complicated */
6199 if (pipe_config
->fdi_lanes
<= 2)
6202 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
6204 intel_atomic_get_crtc_state(state
, other_crtc
);
6205 if (IS_ERR(other_crtc_state
))
6206 return PTR_ERR(other_crtc_state
);
6208 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6209 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6210 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6215 if (pipe_config
->fdi_lanes
> 2) {
6216 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6217 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6221 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
6223 intel_atomic_get_crtc_state(state
, other_crtc
);
6224 if (IS_ERR(other_crtc_state
))
6225 return PTR_ERR(other_crtc_state
);
6227 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6238 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6239 struct intel_crtc_state
*pipe_config
)
6241 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6242 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6243 int lane
, link_bw
, fdi_dotclock
, ret
;
6244 bool needs_recompute
= false;
6247 /* FDI is a binary signal running at ~2.7GHz, encoding
6248 * each output octet as 10 bits. The actual frequency
6249 * is stored as a divider into a 100MHz clock, and the
6250 * mode pixel clock is stored in units of 1KHz.
6251 * Hence the bw of each lane in terms of the mode signal
6254 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6256 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6258 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6259 pipe_config
->pipe_bpp
);
6261 pipe_config
->fdi_lanes
= lane
;
6263 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6264 link_bw
, &pipe_config
->fdi_m_n
, false);
6266 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6267 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6268 pipe_config
->pipe_bpp
-= 2*3;
6269 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6270 pipe_config
->pipe_bpp
);
6271 needs_recompute
= true;
6272 pipe_config
->bw_constrained
= true;
6277 if (needs_recompute
)
6283 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6284 struct intel_crtc_state
*pipe_config
)
6286 if (pipe_config
->pipe_bpp
> 24)
6289 /* HSW can handle pixel rate up to cdclk? */
6290 if (IS_HASWELL(dev_priv
))
6294 * We compare against max which means we must take
6295 * the increased cdclk requirement into account when
6296 * calculating the new cdclk.
6298 * Should measure whether using a lower cdclk w/o IPS
6300 return pipe_config
->pixel_rate
<=
6301 dev_priv
->max_cdclk_freq
* 95 / 100;
6304 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6305 struct intel_crtc_state
*pipe_config
)
6307 struct drm_device
*dev
= crtc
->base
.dev
;
6308 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6310 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6311 hsw_crtc_supports_ips(crtc
) &&
6312 pipe_config_supports_ips(dev_priv
, pipe_config
);
6315 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6317 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6319 /* GDG double wide on either pipe, otherwise pipe A only */
6320 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6321 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6324 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
6326 uint32_t pixel_rate
;
6328 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6331 * We only use IF-ID interlacing. If we ever use
6332 * PF-ID we'll need to adjust the pixel_rate here.
6335 if (pipe_config
->pch_pfit
.enabled
) {
6336 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
6337 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
6339 pipe_w
= pipe_config
->pipe_src_w
;
6340 pipe_h
= pipe_config
->pipe_src_h
;
6342 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
6343 pfit_h
= pfit_size
& 0xFFFF;
6344 if (pipe_w
< pfit_w
)
6346 if (pipe_h
< pfit_h
)
6349 if (WARN_ON(!pfit_w
|| !pfit_h
))
6352 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
6359 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
6361 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
6363 if (HAS_GMCH_DISPLAY(dev_priv
))
6364 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6365 crtc_state
->pixel_rate
=
6366 crtc_state
->base
.adjusted_mode
.crtc_clock
;
6368 crtc_state
->pixel_rate
=
6369 ilk_pipe_pixel_rate(crtc_state
);
6372 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6373 struct intel_crtc_state
*pipe_config
)
6375 struct drm_device
*dev
= crtc
->base
.dev
;
6376 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6377 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6378 int clock_limit
= dev_priv
->max_dotclk_freq
;
6380 if (INTEL_GEN(dev_priv
) < 4) {
6381 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6384 * Enable double wide mode when the dot clock
6385 * is > 90% of the (display) core speed.
6387 if (intel_crtc_supports_double_wide(crtc
) &&
6388 adjusted_mode
->crtc_clock
> clock_limit
) {
6389 clock_limit
= dev_priv
->max_dotclk_freq
;
6390 pipe_config
->double_wide
= true;
6394 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6395 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6396 adjusted_mode
->crtc_clock
, clock_limit
,
6397 yesno(pipe_config
->double_wide
));
6401 if (pipe_config
->ycbcr420
&& pipe_config
->base
.ctm
) {
6403 * There is only one pipe CSC unit per pipe, and we need that
6404 * for output conversion from RGB->YCBCR. So if CTM is already
6405 * applied we can't support YCBCR420 output.
6407 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6412 * Pipe horizontal size must be even in:
6414 * - LVDS dual channel mode
6415 * - Double wide pipe
6417 if ((intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6418 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6419 pipe_config
->pipe_src_w
&= ~1;
6421 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6422 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6424 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
6425 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6428 intel_crtc_compute_pixel_rate(pipe_config
);
6430 if (HAS_IPS(dev_priv
))
6431 hsw_compute_ips_config(crtc
, pipe_config
);
6433 if (pipe_config
->has_pch_encoder
)
6434 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6440 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6442 while (*num
> DATA_LINK_M_N_MASK
||
6443 *den
> DATA_LINK_M_N_MASK
) {
6449 static void compute_m_n(unsigned int m
, unsigned int n
,
6450 uint32_t *ret_m
, uint32_t *ret_n
,
6454 * Reduce M/N as much as possible without loss in precision. Several DP
6455 * dongles in particular seem to be fussy about too large *link* M/N
6456 * values. The passed in values are more likely to have the least
6457 * significant bits zero than M after rounding below, so do this first.
6460 while ((m
& 1) == 0 && (n
& 1) == 0) {
6466 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6467 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6468 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6472 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6473 int pixel_clock
, int link_clock
,
6474 struct intel_link_m_n
*m_n
,
6479 compute_m_n(bits_per_pixel
* pixel_clock
,
6480 link_clock
* nlanes
* 8,
6481 &m_n
->gmch_m
, &m_n
->gmch_n
,
6484 compute_m_n(pixel_clock
, link_clock
,
6485 &m_n
->link_m
, &m_n
->link_n
,
6489 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6491 if (i915
.panel_use_ssc
>= 0)
6492 return i915
.panel_use_ssc
!= 0;
6493 return dev_priv
->vbt
.lvds_use_ssc
6494 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6497 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6499 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6502 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6504 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6507 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6508 struct intel_crtc_state
*crtc_state
,
6509 struct dpll
*reduced_clock
)
6511 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6514 if (IS_PINEVIEW(dev_priv
)) {
6515 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6517 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6519 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6521 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6524 crtc_state
->dpll_hw_state
.fp0
= fp
;
6526 crtc
->lowfreq_avail
= false;
6527 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6529 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6530 crtc
->lowfreq_avail
= true;
6532 crtc_state
->dpll_hw_state
.fp1
= fp
;
6536 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6542 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6543 * and set it to a reasonable value instead.
6545 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6546 reg_val
&= 0xffffff00;
6547 reg_val
|= 0x00000030;
6548 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6550 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6551 reg_val
&= 0x00ffffff;
6552 reg_val
|= 0x8c000000;
6553 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6555 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6556 reg_val
&= 0xffffff00;
6557 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6559 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6560 reg_val
&= 0x00ffffff;
6561 reg_val
|= 0xb0000000;
6562 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6565 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6566 struct intel_link_m_n
*m_n
)
6568 struct drm_device
*dev
= crtc
->base
.dev
;
6569 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6570 int pipe
= crtc
->pipe
;
6572 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6573 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6574 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6575 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6578 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6579 struct intel_link_m_n
*m_n
,
6580 struct intel_link_m_n
*m2_n2
)
6582 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6583 int pipe
= crtc
->pipe
;
6584 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6586 if (INTEL_GEN(dev_priv
) >= 5) {
6587 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6588 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6589 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6590 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6591 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6592 * for gen < 8) and if DRRS is supported (to make sure the
6593 * registers are not unnecessarily accessed).
6595 if (m2_n2
&& (IS_CHERRYVIEW(dev_priv
) ||
6596 INTEL_GEN(dev_priv
) < 8) && crtc
->config
->has_drrs
) {
6597 I915_WRITE(PIPE_DATA_M2(transcoder
),
6598 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6599 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6600 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6601 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6604 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6605 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6606 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6607 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6611 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6613 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6616 dp_m_n
= &crtc
->config
->dp_m_n
;
6617 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6618 } else if (m_n
== M2_N2
) {
6621 * M2_N2 registers are not supported. Hence m2_n2 divider value
6622 * needs to be programmed into M1_N1.
6624 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6626 DRM_ERROR("Unsupported divider value\n");
6630 if (crtc
->config
->has_pch_encoder
)
6631 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6633 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6636 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
6637 struct intel_crtc_state
*pipe_config
)
6639 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
6640 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
6641 if (crtc
->pipe
!= PIPE_A
)
6642 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6644 /* DPLL not used with DSI, but still need the rest set up */
6645 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
6646 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
6647 DPLL_EXT_BUFFER_ENABLE_VLV
;
6649 pipe_config
->dpll_hw_state
.dpll_md
=
6650 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6653 static void chv_compute_dpll(struct intel_crtc
*crtc
,
6654 struct intel_crtc_state
*pipe_config
)
6656 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
6657 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
6658 if (crtc
->pipe
!= PIPE_A
)
6659 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6661 /* DPLL not used with DSI, but still need the rest set up */
6662 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
6663 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
6665 pipe_config
->dpll_hw_state
.dpll_md
=
6666 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6669 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6670 const struct intel_crtc_state
*pipe_config
)
6672 struct drm_device
*dev
= crtc
->base
.dev
;
6673 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6674 enum pipe pipe
= crtc
->pipe
;
6676 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6677 u32 coreclk
, reg_val
;
6680 I915_WRITE(DPLL(pipe
),
6681 pipe_config
->dpll_hw_state
.dpll
&
6682 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
6684 /* No need to actually set up the DPLL with DSI */
6685 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
6688 mutex_lock(&dev_priv
->sb_lock
);
6690 bestn
= pipe_config
->dpll
.n
;
6691 bestm1
= pipe_config
->dpll
.m1
;
6692 bestm2
= pipe_config
->dpll
.m2
;
6693 bestp1
= pipe_config
->dpll
.p1
;
6694 bestp2
= pipe_config
->dpll
.p2
;
6696 /* See eDP HDMI DPIO driver vbios notes doc */
6698 /* PLL B needs special handling */
6700 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6702 /* Set up Tx target for periodic Rcomp update */
6703 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6705 /* Disable target IRef on PLL */
6706 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6707 reg_val
&= 0x00ffffff;
6708 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6710 /* Disable fast lock */
6711 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6713 /* Set idtafcrecal before PLL is enabled */
6714 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6715 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6716 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6717 mdiv
|= (1 << DPIO_K_SHIFT
);
6720 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6721 * but we don't support that).
6722 * Note: don't use the DAC post divider as it seems unstable.
6724 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6725 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6727 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6728 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6730 /* Set HBR and RBR LPF coefficients */
6731 if (pipe_config
->port_clock
== 162000 ||
6732 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_ANALOG
) ||
6733 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
))
6734 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6737 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6740 if (intel_crtc_has_dp_encoder(pipe_config
)) {
6741 /* Use SSC source */
6743 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6746 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6748 } else { /* HDMI or VGA */
6749 /* Use bend source */
6751 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6754 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6758 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6759 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6760 if (intel_crtc_has_dp_encoder(crtc
->config
))
6761 coreclk
|= 0x01000000;
6762 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6764 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6765 mutex_unlock(&dev_priv
->sb_lock
);
6768 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6769 const struct intel_crtc_state
*pipe_config
)
6771 struct drm_device
*dev
= crtc
->base
.dev
;
6772 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6773 enum pipe pipe
= crtc
->pipe
;
6774 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6775 u32 loopfilter
, tribuf_calcntr
;
6776 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6780 /* Enable Refclk and SSC */
6781 I915_WRITE(DPLL(pipe
),
6782 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6784 /* No need to actually set up the DPLL with DSI */
6785 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
6788 bestn
= pipe_config
->dpll
.n
;
6789 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6790 bestm1
= pipe_config
->dpll
.m1
;
6791 bestm2
= pipe_config
->dpll
.m2
>> 22;
6792 bestp1
= pipe_config
->dpll
.p1
;
6793 bestp2
= pipe_config
->dpll
.p2
;
6794 vco
= pipe_config
->dpll
.vco
;
6798 mutex_lock(&dev_priv
->sb_lock
);
6800 /* p1 and p2 divider */
6801 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6802 5 << DPIO_CHV_S1_DIV_SHIFT
|
6803 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6804 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6805 1 << DPIO_CHV_K_DIV_SHIFT
);
6807 /* Feedback post-divider - m2 */
6808 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6810 /* Feedback refclk divider - n and m1 */
6811 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6812 DPIO_CHV_M1_DIV_BY_2
|
6813 1 << DPIO_CHV_N_DIV_SHIFT
);
6815 /* M2 fraction division */
6816 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6818 /* M2 fraction division enable */
6819 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
6820 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
6821 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
6823 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
6824 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
6826 /* Program digital lock detect threshold */
6827 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
6828 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
6829 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
6830 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
6832 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
6833 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
6836 if (vco
== 5400000) {
6837 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
6838 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
6839 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6840 tribuf_calcntr
= 0x9;
6841 } else if (vco
<= 6200000) {
6842 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
6843 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
6844 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6845 tribuf_calcntr
= 0x9;
6846 } else if (vco
<= 6480000) {
6847 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6848 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6849 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6850 tribuf_calcntr
= 0x8;
6852 /* Not supported. Apply the same limits as in the max case */
6853 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6854 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6855 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6858 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6860 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
6861 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
6862 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
6863 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
6866 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6867 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6870 mutex_unlock(&dev_priv
->sb_lock
);
6874 * vlv_force_pll_on - forcibly enable just the PLL
6875 * @dev_priv: i915 private structure
6876 * @pipe: pipe PLL to enable
6877 * @dpll: PLL configuration
6879 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6880 * in cases where we need the PLL enabled even when @pipe is not going to
6883 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
6884 const struct dpll
*dpll
)
6886 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
6887 struct intel_crtc_state
*pipe_config
;
6889 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
6893 pipe_config
->base
.crtc
= &crtc
->base
;
6894 pipe_config
->pixel_multiplier
= 1;
6895 pipe_config
->dpll
= *dpll
;
6897 if (IS_CHERRYVIEW(dev_priv
)) {
6898 chv_compute_dpll(crtc
, pipe_config
);
6899 chv_prepare_pll(crtc
, pipe_config
);
6900 chv_enable_pll(crtc
, pipe_config
);
6902 vlv_compute_dpll(crtc
, pipe_config
);
6903 vlv_prepare_pll(crtc
, pipe_config
);
6904 vlv_enable_pll(crtc
, pipe_config
);
6913 * vlv_force_pll_off - forcibly disable just the PLL
6914 * @dev_priv: i915 private structure
6915 * @pipe: pipe PLL to disable
6917 * Disable the PLL for @pipe. To be used in cases where we need
6918 * the PLL enabled even when @pipe is not going to be enabled.
6920 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
6922 if (IS_CHERRYVIEW(dev_priv
))
6923 chv_disable_pll(dev_priv
, pipe
);
6925 vlv_disable_pll(dev_priv
, pipe
);
6928 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
6929 struct intel_crtc_state
*crtc_state
,
6930 struct dpll
*reduced_clock
)
6932 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6934 struct dpll
*clock
= &crtc_state
->dpll
;
6936 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6938 dpll
= DPLL_VGA_MODE_DIS
;
6940 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
6941 dpll
|= DPLLB_MODE_LVDS
;
6943 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6945 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
6946 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
6947 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6948 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6951 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
6952 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
6953 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6955 if (intel_crtc_has_dp_encoder(crtc_state
))
6956 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6958 /* compute bitmask from p1 value */
6959 if (IS_PINEVIEW(dev_priv
))
6960 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6962 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6963 if (IS_G4X(dev_priv
) && reduced_clock
)
6964 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6966 switch (clock
->p2
) {
6968 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6971 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6974 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6977 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6980 if (INTEL_GEN(dev_priv
) >= 4)
6981 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6983 if (crtc_state
->sdvo_tv_clock
)
6984 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6985 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6986 intel_panel_use_ssc(dev_priv
))
6987 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6989 dpll
|= PLL_REF_INPUT_DREFCLK
;
6991 dpll
|= DPLL_VCO_ENABLE
;
6992 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6994 if (INTEL_GEN(dev_priv
) >= 4) {
6995 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6996 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6997 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7001 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7002 struct intel_crtc_state
*crtc_state
,
7003 struct dpll
*reduced_clock
)
7005 struct drm_device
*dev
= crtc
->base
.dev
;
7006 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7008 struct dpll
*clock
= &crtc_state
->dpll
;
7010 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7012 dpll
= DPLL_VGA_MODE_DIS
;
7014 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7015 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7018 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7020 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7022 dpll
|= PLL_P2_DIVIDE_BY_4
;
7025 if (!IS_I830(dev_priv
) &&
7026 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7027 dpll
|= DPLL_DVO_2X_MODE
;
7029 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7030 intel_panel_use_ssc(dev_priv
))
7031 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7033 dpll
|= PLL_REF_INPUT_DREFCLK
;
7035 dpll
|= DPLL_VCO_ENABLE
;
7036 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7039 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7041 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
7042 enum pipe pipe
= intel_crtc
->pipe
;
7043 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7044 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7045 uint32_t crtc_vtotal
, crtc_vblank_end
;
7048 /* We need to be careful not to changed the adjusted mode, for otherwise
7049 * the hw state checker will get angry at the mismatch. */
7050 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7051 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7053 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7054 /* the chip adds 2 halflines automatically */
7056 crtc_vblank_end
-= 1;
7058 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7059 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7061 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7062 adjusted_mode
->crtc_htotal
/ 2;
7064 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7067 if (INTEL_GEN(dev_priv
) > 3)
7068 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7070 I915_WRITE(HTOTAL(cpu_transcoder
),
7071 (adjusted_mode
->crtc_hdisplay
- 1) |
7072 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7073 I915_WRITE(HBLANK(cpu_transcoder
),
7074 (adjusted_mode
->crtc_hblank_start
- 1) |
7075 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7076 I915_WRITE(HSYNC(cpu_transcoder
),
7077 (adjusted_mode
->crtc_hsync_start
- 1) |
7078 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7080 I915_WRITE(VTOTAL(cpu_transcoder
),
7081 (adjusted_mode
->crtc_vdisplay
- 1) |
7082 ((crtc_vtotal
- 1) << 16));
7083 I915_WRITE(VBLANK(cpu_transcoder
),
7084 (adjusted_mode
->crtc_vblank_start
- 1) |
7085 ((crtc_vblank_end
- 1) << 16));
7086 I915_WRITE(VSYNC(cpu_transcoder
),
7087 (adjusted_mode
->crtc_vsync_start
- 1) |
7088 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7090 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7091 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7092 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7094 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
7095 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7096 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7100 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7102 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7103 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7104 enum pipe pipe
= intel_crtc
->pipe
;
7106 /* pipesrc controls the size that is scaled from, which should
7107 * always be the user's requested size.
7109 I915_WRITE(PIPESRC(pipe
),
7110 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7111 (intel_crtc
->config
->pipe_src_h
- 1));
7114 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7115 struct intel_crtc_state
*pipe_config
)
7117 struct drm_device
*dev
= crtc
->base
.dev
;
7118 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7119 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7122 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7123 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7124 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7125 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7126 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7127 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7128 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7129 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7130 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7132 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7133 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7134 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7135 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7136 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7137 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7138 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7139 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7140 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7142 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7143 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7144 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7145 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7149 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7150 struct intel_crtc_state
*pipe_config
)
7152 struct drm_device
*dev
= crtc
->base
.dev
;
7153 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7156 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7157 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7158 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7160 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7161 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7164 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7165 struct intel_crtc_state
*pipe_config
)
7167 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7168 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7169 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7170 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7172 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7173 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7174 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7175 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7177 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7178 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7180 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7182 mode
->hsync
= drm_mode_hsync(mode
);
7183 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7184 drm_mode_set_name(mode
);
7187 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7189 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
7194 /* we keep both pipes enabled on 830 */
7195 if (IS_I830(dev_priv
))
7196 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7198 if (intel_crtc
->config
->double_wide
)
7199 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7201 /* only g4x and later have fancy bpc/dither controls */
7202 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
7203 IS_CHERRYVIEW(dev_priv
)) {
7204 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7205 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7206 pipeconf
|= PIPECONF_DITHER_EN
|
7207 PIPECONF_DITHER_TYPE_SP
;
7209 switch (intel_crtc
->config
->pipe_bpp
) {
7211 pipeconf
|= PIPECONF_6BPC
;
7214 pipeconf
|= PIPECONF_8BPC
;
7217 pipeconf
|= PIPECONF_10BPC
;
7220 /* Case prevented by intel_choose_pipe_bpp_dither. */
7225 if (HAS_PIPE_CXSR(dev_priv
)) {
7226 if (intel_crtc
->lowfreq_avail
) {
7227 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7228 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7230 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7234 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7235 if (INTEL_GEN(dev_priv
) < 4 ||
7236 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7237 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7239 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7241 pipeconf
|= PIPECONF_PROGRESSIVE
;
7243 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7244 intel_crtc
->config
->limited_color_range
)
7245 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7247 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7248 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7251 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7252 struct intel_crtc_state
*crtc_state
)
7254 struct drm_device
*dev
= crtc
->base
.dev
;
7255 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7256 const struct intel_limit
*limit
;
7259 memset(&crtc_state
->dpll_hw_state
, 0,
7260 sizeof(crtc_state
->dpll_hw_state
));
7262 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7263 if (intel_panel_use_ssc(dev_priv
)) {
7264 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7265 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7268 limit
= &intel_limits_i8xx_lvds
;
7269 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7270 limit
= &intel_limits_i8xx_dvo
;
7272 limit
= &intel_limits_i8xx_dac
;
7275 if (!crtc_state
->clock_set
&&
7276 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7277 refclk
, NULL
, &crtc_state
->dpll
)) {
7278 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7282 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7287 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7288 struct intel_crtc_state
*crtc_state
)
7290 struct drm_device
*dev
= crtc
->base
.dev
;
7291 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7292 const struct intel_limit
*limit
;
7295 memset(&crtc_state
->dpll_hw_state
, 0,
7296 sizeof(crtc_state
->dpll_hw_state
));
7298 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7299 if (intel_panel_use_ssc(dev_priv
)) {
7300 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7301 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7304 if (intel_is_dual_link_lvds(dev
))
7305 limit
= &intel_limits_g4x_dual_channel_lvds
;
7307 limit
= &intel_limits_g4x_single_channel_lvds
;
7308 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7309 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7310 limit
= &intel_limits_g4x_hdmi
;
7311 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7312 limit
= &intel_limits_g4x_sdvo
;
7314 /* The option is for other outputs */
7315 limit
= &intel_limits_i9xx_sdvo
;
7318 if (!crtc_state
->clock_set
&&
7319 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7320 refclk
, NULL
, &crtc_state
->dpll
)) {
7321 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7325 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7330 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7331 struct intel_crtc_state
*crtc_state
)
7333 struct drm_device
*dev
= crtc
->base
.dev
;
7334 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7335 const struct intel_limit
*limit
;
7338 memset(&crtc_state
->dpll_hw_state
, 0,
7339 sizeof(crtc_state
->dpll_hw_state
));
7341 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7342 if (intel_panel_use_ssc(dev_priv
)) {
7343 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7344 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7347 limit
= &intel_limits_pineview_lvds
;
7349 limit
= &intel_limits_pineview_sdvo
;
7352 if (!crtc_state
->clock_set
&&
7353 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7354 refclk
, NULL
, &crtc_state
->dpll
)) {
7355 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7359 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7364 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7365 struct intel_crtc_state
*crtc_state
)
7367 struct drm_device
*dev
= crtc
->base
.dev
;
7368 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7369 const struct intel_limit
*limit
;
7372 memset(&crtc_state
->dpll_hw_state
, 0,
7373 sizeof(crtc_state
->dpll_hw_state
));
7375 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7376 if (intel_panel_use_ssc(dev_priv
)) {
7377 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7378 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7381 limit
= &intel_limits_i9xx_lvds
;
7383 limit
= &intel_limits_i9xx_sdvo
;
7386 if (!crtc_state
->clock_set
&&
7387 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7388 refclk
, NULL
, &crtc_state
->dpll
)) {
7389 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7393 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7398 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
7399 struct intel_crtc_state
*crtc_state
)
7401 int refclk
= 100000;
7402 const struct intel_limit
*limit
= &intel_limits_chv
;
7404 memset(&crtc_state
->dpll_hw_state
, 0,
7405 sizeof(crtc_state
->dpll_hw_state
));
7407 if (!crtc_state
->clock_set
&&
7408 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7409 refclk
, NULL
, &crtc_state
->dpll
)) {
7410 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7414 chv_compute_dpll(crtc
, crtc_state
);
7419 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
7420 struct intel_crtc_state
*crtc_state
)
7422 int refclk
= 100000;
7423 const struct intel_limit
*limit
= &intel_limits_vlv
;
7425 memset(&crtc_state
->dpll_hw_state
, 0,
7426 sizeof(crtc_state
->dpll_hw_state
));
7428 if (!crtc_state
->clock_set
&&
7429 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7430 refclk
, NULL
, &crtc_state
->dpll
)) {
7431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7435 vlv_compute_dpll(crtc
, crtc_state
);
7440 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7441 struct intel_crtc_state
*pipe_config
)
7443 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7446 if (INTEL_GEN(dev_priv
) <= 3 &&
7447 (IS_I830(dev_priv
) || !IS_MOBILE(dev_priv
)))
7450 tmp
= I915_READ(PFIT_CONTROL
);
7451 if (!(tmp
& PFIT_ENABLE
))
7454 /* Check whether the pfit is attached to our pipe. */
7455 if (INTEL_GEN(dev_priv
) < 4) {
7456 if (crtc
->pipe
!= PIPE_B
)
7459 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7463 pipe_config
->gmch_pfit
.control
= tmp
;
7464 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7467 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7468 struct intel_crtc_state
*pipe_config
)
7470 struct drm_device
*dev
= crtc
->base
.dev
;
7471 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7472 int pipe
= pipe_config
->cpu_transcoder
;
7475 int refclk
= 100000;
7477 /* In case of DSI, DPLL will not be used */
7478 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7481 mutex_lock(&dev_priv
->sb_lock
);
7482 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7483 mutex_unlock(&dev_priv
->sb_lock
);
7485 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7486 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7487 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7488 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7489 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7491 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
7495 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7496 struct intel_initial_plane_config
*plane_config
)
7498 struct drm_device
*dev
= crtc
->base
.dev
;
7499 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7500 u32 val
, base
, offset
;
7501 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7502 int fourcc
, pixel_format
;
7503 unsigned int aligned_height
;
7504 struct drm_framebuffer
*fb
;
7505 struct intel_framebuffer
*intel_fb
;
7507 val
= I915_READ(DSPCNTR(plane
));
7508 if (!(val
& DISPLAY_PLANE_ENABLE
))
7511 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7513 DRM_DEBUG_KMS("failed to alloc fb\n");
7517 fb
= &intel_fb
->base
;
7521 if (INTEL_GEN(dev_priv
) >= 4) {
7522 if (val
& DISPPLANE_TILED
) {
7523 plane_config
->tiling
= I915_TILING_X
;
7524 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
7528 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7529 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7530 fb
->format
= drm_format_info(fourcc
);
7532 if (INTEL_GEN(dev_priv
) >= 4) {
7533 if (plane_config
->tiling
)
7534 offset
= I915_READ(DSPTILEOFF(plane
));
7536 offset
= I915_READ(DSPLINOFF(plane
));
7537 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7539 base
= I915_READ(DSPADDR(plane
));
7541 plane_config
->base
= base
;
7543 val
= I915_READ(PIPESRC(pipe
));
7544 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7545 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7547 val
= I915_READ(DSPSTRIDE(pipe
));
7548 fb
->pitches
[0] = val
& 0xffffffc0;
7550 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
7552 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7554 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7555 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7556 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
7557 plane_config
->size
);
7559 plane_config
->fb
= intel_fb
;
7562 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7563 struct intel_crtc_state
*pipe_config
)
7565 struct drm_device
*dev
= crtc
->base
.dev
;
7566 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7567 int pipe
= pipe_config
->cpu_transcoder
;
7568 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7570 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
7571 int refclk
= 100000;
7573 /* In case of DSI, DPLL will not be used */
7574 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7577 mutex_lock(&dev_priv
->sb_lock
);
7578 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7579 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7580 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7581 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7582 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7583 mutex_unlock(&dev_priv
->sb_lock
);
7585 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7586 clock
.m2
= (pll_dw0
& 0xff) << 22;
7587 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
7588 clock
.m2
|= pll_dw2
& 0x3fffff;
7589 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7590 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7591 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7593 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
7596 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7597 struct intel_crtc_state
*pipe_config
)
7599 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7600 enum intel_display_power_domain power_domain
;
7604 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
7605 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
7608 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7609 pipe_config
->shared_dpll
= NULL
;
7613 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7614 if (!(tmp
& PIPECONF_ENABLE
))
7617 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
7618 IS_CHERRYVIEW(dev_priv
)) {
7619 switch (tmp
& PIPECONF_BPC_MASK
) {
7621 pipe_config
->pipe_bpp
= 18;
7624 pipe_config
->pipe_bpp
= 24;
7626 case PIPECONF_10BPC
:
7627 pipe_config
->pipe_bpp
= 30;
7634 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7635 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7636 pipe_config
->limited_color_range
= true;
7638 if (INTEL_GEN(dev_priv
) < 4)
7639 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7641 intel_get_pipe_timings(crtc
, pipe_config
);
7642 intel_get_pipe_src_size(crtc
, pipe_config
);
7644 i9xx_get_pfit_config(crtc
, pipe_config
);
7646 if (INTEL_GEN(dev_priv
) >= 4) {
7647 /* No way to read it out on pipes B and C */
7648 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
7649 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
7651 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7652 pipe_config
->pixel_multiplier
=
7653 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7654 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7655 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7656 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
7657 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
7658 tmp
= I915_READ(DPLL(crtc
->pipe
));
7659 pipe_config
->pixel_multiplier
=
7660 ((tmp
& SDVO_MULTIPLIER_MASK
)
7661 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7663 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7664 * port and will be fixed up in the encoder->get_config
7666 pipe_config
->pixel_multiplier
= 1;
7668 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7669 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
7671 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7672 * on 830. Filter it out here so that we don't
7673 * report errors due to that.
7675 if (IS_I830(dev_priv
))
7676 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7678 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7679 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7681 /* Mask out read-only status bits. */
7682 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7683 DPLL_PORTC_READY_MASK
|
7684 DPLL_PORTB_READY_MASK
);
7687 if (IS_CHERRYVIEW(dev_priv
))
7688 chv_crtc_clock_get(crtc
, pipe_config
);
7689 else if (IS_VALLEYVIEW(dev_priv
))
7690 vlv_crtc_clock_get(crtc
, pipe_config
);
7692 i9xx_crtc_clock_get(crtc
, pipe_config
);
7695 * Normally the dotclock is filled in by the encoder .get_config()
7696 * but in case the pipe is enabled w/o any ports we need a sane
7699 pipe_config
->base
.adjusted_mode
.crtc_clock
=
7700 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
7705 intel_display_power_put(dev_priv
, power_domain
);
7710 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
7712 struct intel_encoder
*encoder
;
7715 bool has_lvds
= false;
7716 bool has_cpu_edp
= false;
7717 bool has_panel
= false;
7718 bool has_ck505
= false;
7719 bool can_ssc
= false;
7720 bool using_ssc_source
= false;
7722 /* We need to take the global config into account */
7723 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7724 switch (encoder
->type
) {
7725 case INTEL_OUTPUT_LVDS
:
7729 case INTEL_OUTPUT_EDP
:
7731 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7739 if (HAS_PCH_IBX(dev_priv
)) {
7740 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7741 can_ssc
= has_ck505
;
7747 /* Check if any DPLLs are using the SSC source */
7748 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
7749 u32 temp
= I915_READ(PCH_DPLL(i
));
7751 if (!(temp
& DPLL_VCO_ENABLE
))
7754 if ((temp
& PLL_REF_INPUT_MASK
) ==
7755 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
7756 using_ssc_source
= true;
7761 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7762 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
7764 /* Ironlake: try to setup display ref clock before DPLL
7765 * enabling. This is only under driver's control after
7766 * PCH B stepping, previous chipset stepping should be
7767 * ignoring this setting.
7769 val
= I915_READ(PCH_DREF_CONTROL
);
7771 /* As we must carefully and slowly disable/enable each source in turn,
7772 * compute the final state we want first and check if we need to
7773 * make any changes at all.
7776 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7778 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7780 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7782 final
&= ~DREF_SSC_SOURCE_MASK
;
7783 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7784 final
&= ~DREF_SSC1_ENABLE
;
7787 final
|= DREF_SSC_SOURCE_ENABLE
;
7789 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7790 final
|= DREF_SSC1_ENABLE
;
7793 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7794 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7796 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7798 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7799 } else if (using_ssc_source
) {
7800 final
|= DREF_SSC_SOURCE_ENABLE
;
7801 final
|= DREF_SSC1_ENABLE
;
7807 /* Always enable nonspread source */
7808 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7811 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7813 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7816 val
&= ~DREF_SSC_SOURCE_MASK
;
7817 val
|= DREF_SSC_SOURCE_ENABLE
;
7819 /* SSC must be turned on before enabling the CPU output */
7820 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7821 DRM_DEBUG_KMS("Using SSC on panel\n");
7822 val
|= DREF_SSC1_ENABLE
;
7824 val
&= ~DREF_SSC1_ENABLE
;
7826 /* Get SSC going before enabling the outputs */
7827 I915_WRITE(PCH_DREF_CONTROL
, val
);
7828 POSTING_READ(PCH_DREF_CONTROL
);
7831 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7833 /* Enable CPU source on CPU attached eDP */
7835 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7836 DRM_DEBUG_KMS("Using SSC on eDP\n");
7837 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7839 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7841 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7843 I915_WRITE(PCH_DREF_CONTROL
, val
);
7844 POSTING_READ(PCH_DREF_CONTROL
);
7847 DRM_DEBUG_KMS("Disabling CPU source output\n");
7849 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7851 /* Turn off CPU output */
7852 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7854 I915_WRITE(PCH_DREF_CONTROL
, val
);
7855 POSTING_READ(PCH_DREF_CONTROL
);
7858 if (!using_ssc_source
) {
7859 DRM_DEBUG_KMS("Disabling SSC source\n");
7861 /* Turn off the SSC source */
7862 val
&= ~DREF_SSC_SOURCE_MASK
;
7863 val
|= DREF_SSC_SOURCE_DISABLE
;
7866 val
&= ~DREF_SSC1_ENABLE
;
7868 I915_WRITE(PCH_DREF_CONTROL
, val
);
7869 POSTING_READ(PCH_DREF_CONTROL
);
7874 BUG_ON(val
!= final
);
7877 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7881 tmp
= I915_READ(SOUTH_CHICKEN2
);
7882 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7883 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7885 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
7886 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7887 DRM_ERROR("FDI mPHY reset assert timeout\n");
7889 tmp
= I915_READ(SOUTH_CHICKEN2
);
7890 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7891 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7893 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
7894 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7895 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7898 /* WaMPhyProgramming:hsw */
7899 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7903 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7904 tmp
&= ~(0xFF << 24);
7905 tmp
|= (0x12 << 24);
7906 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7908 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7910 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7912 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7914 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7916 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7917 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7918 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7920 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7921 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7922 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7924 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7927 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
7929 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
7932 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7934 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7937 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7939 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7942 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7944 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7945 tmp
&= ~(0xFF << 16);
7946 tmp
|= (0x1C << 16);
7947 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7949 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7950 tmp
&= ~(0xFF << 16);
7951 tmp
|= (0x1C << 16);
7952 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7954 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7956 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7958 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7960 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7962 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7963 tmp
&= ~(0xF << 28);
7965 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7967 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7968 tmp
&= ~(0xF << 28);
7970 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7973 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7974 * Programming" based on the parameters passed:
7975 * - Sequence to enable CLKOUT_DP
7976 * - Sequence to enable CLKOUT_DP without spread
7977 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7979 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
7980 bool with_spread
, bool with_fdi
)
7984 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7986 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
7987 with_fdi
, "LP PCH doesn't have FDI\n"))
7990 mutex_lock(&dev_priv
->sb_lock
);
7992 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7993 tmp
&= ~SBI_SSCCTL_DISABLE
;
7994 tmp
|= SBI_SSCCTL_PATHALT
;
7995 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8000 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8001 tmp
&= ~SBI_SSCCTL_PATHALT
;
8002 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8005 lpt_reset_fdi_mphy(dev_priv
);
8006 lpt_program_fdi_mphy(dev_priv
);
8010 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
8011 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8012 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8013 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8015 mutex_unlock(&dev_priv
->sb_lock
);
8018 /* Sequence to disable CLKOUT_DP */
8019 static void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
8023 mutex_lock(&dev_priv
->sb_lock
);
8025 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
8026 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8027 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8028 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8030 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8031 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8032 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8033 tmp
|= SBI_SSCCTL_PATHALT
;
8034 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8037 tmp
|= SBI_SSCCTL_DISABLE
;
8038 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8041 mutex_unlock(&dev_priv
->sb_lock
);
8044 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8046 static const uint16_t sscdivintphase
[] = {
8047 [BEND_IDX( 50)] = 0x3B23,
8048 [BEND_IDX( 45)] = 0x3B23,
8049 [BEND_IDX( 40)] = 0x3C23,
8050 [BEND_IDX( 35)] = 0x3C23,
8051 [BEND_IDX( 30)] = 0x3D23,
8052 [BEND_IDX( 25)] = 0x3D23,
8053 [BEND_IDX( 20)] = 0x3E23,
8054 [BEND_IDX( 15)] = 0x3E23,
8055 [BEND_IDX( 10)] = 0x3F23,
8056 [BEND_IDX( 5)] = 0x3F23,
8057 [BEND_IDX( 0)] = 0x0025,
8058 [BEND_IDX( -5)] = 0x0025,
8059 [BEND_IDX(-10)] = 0x0125,
8060 [BEND_IDX(-15)] = 0x0125,
8061 [BEND_IDX(-20)] = 0x0225,
8062 [BEND_IDX(-25)] = 0x0225,
8063 [BEND_IDX(-30)] = 0x0325,
8064 [BEND_IDX(-35)] = 0x0325,
8065 [BEND_IDX(-40)] = 0x0425,
8066 [BEND_IDX(-45)] = 0x0425,
8067 [BEND_IDX(-50)] = 0x0525,
8072 * steps -50 to 50 inclusive, in steps of 5
8073 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8074 * change in clock period = -(steps / 10) * 5.787 ps
8076 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8079 int idx
= BEND_IDX(steps
);
8081 if (WARN_ON(steps
% 5 != 0))
8084 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8087 mutex_lock(&dev_priv
->sb_lock
);
8089 if (steps
% 10 != 0)
8093 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8095 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8097 tmp
|= sscdivintphase
[idx
];
8098 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8100 mutex_unlock(&dev_priv
->sb_lock
);
8105 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8107 struct intel_encoder
*encoder
;
8108 bool has_vga
= false;
8110 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8111 switch (encoder
->type
) {
8112 case INTEL_OUTPUT_ANALOG
:
8121 lpt_bend_clkout_dp(dev_priv
, 0);
8122 lpt_enable_clkout_dp(dev_priv
, true, true);
8124 lpt_disable_clkout_dp(dev_priv
);
8129 * Initialize reference clocks when the driver loads
8131 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8133 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
8134 ironlake_init_pch_refclk(dev_priv
);
8135 else if (HAS_PCH_LPT(dev_priv
))
8136 lpt_init_pch_refclk(dev_priv
);
8139 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8141 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8143 int pipe
= intel_crtc
->pipe
;
8148 switch (intel_crtc
->config
->pipe_bpp
) {
8150 val
|= PIPECONF_6BPC
;
8153 val
|= PIPECONF_8BPC
;
8156 val
|= PIPECONF_10BPC
;
8159 val
|= PIPECONF_12BPC
;
8162 /* Case prevented by intel_choose_pipe_bpp_dither. */
8166 if (intel_crtc
->config
->dither
)
8167 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8169 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8170 val
|= PIPECONF_INTERLACED_ILK
;
8172 val
|= PIPECONF_PROGRESSIVE
;
8174 if (intel_crtc
->config
->limited_color_range
)
8175 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8177 I915_WRITE(PIPECONF(pipe
), val
);
8178 POSTING_READ(PIPECONF(pipe
));
8181 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8183 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8184 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8185 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8188 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8189 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8191 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8192 val
|= PIPECONF_INTERLACED_ILK
;
8194 val
|= PIPECONF_PROGRESSIVE
;
8196 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8197 POSTING_READ(PIPECONF(cpu_transcoder
));
8200 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8202 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8203 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8204 struct intel_crtc_state
*config
= intel_crtc
->config
;
8206 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8209 switch (intel_crtc
->config
->pipe_bpp
) {
8211 val
|= PIPEMISC_DITHER_6_BPC
;
8214 val
|= PIPEMISC_DITHER_8_BPC
;
8217 val
|= PIPEMISC_DITHER_10_BPC
;
8220 val
|= PIPEMISC_DITHER_12_BPC
;
8223 /* Case prevented by pipe_config_set_bpp. */
8227 if (intel_crtc
->config
->dither
)
8228 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8230 if (config
->ycbcr420
) {
8231 val
|= PIPEMISC_OUTPUT_COLORSPACE_YUV
|
8232 PIPEMISC_YUV420_ENABLE
|
8233 PIPEMISC_YUV420_MODE_FULL_BLEND
;
8236 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8240 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8243 * Account for spread spectrum to avoid
8244 * oversubscribing the link. Max center spread
8245 * is 2.5%; use 5% for safety's sake.
8247 u32 bps
= target_clock
* bpp
* 21 / 20;
8248 return DIV_ROUND_UP(bps
, link_bw
* 8);
8251 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8253 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8256 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8257 struct intel_crtc_state
*crtc_state
,
8258 struct dpll
*reduced_clock
)
8260 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8261 struct drm_device
*dev
= crtc
->dev
;
8262 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8266 /* Enable autotuning of the PLL clock (if permissible) */
8268 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8269 if ((intel_panel_use_ssc(dev_priv
) &&
8270 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8271 (HAS_PCH_IBX(dev_priv
) && intel_is_dual_link_lvds(dev
)))
8273 } else if (crtc_state
->sdvo_tv_clock
)
8276 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8278 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8281 if (reduced_clock
) {
8282 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8284 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8292 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8293 dpll
|= DPLLB_MODE_LVDS
;
8295 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8297 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8298 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8300 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8301 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8302 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8304 if (intel_crtc_has_dp_encoder(crtc_state
))
8305 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8308 * The high speed IO clock is only really required for
8309 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8310 * possible to share the DPLL between CRT and HDMI. Enabling
8311 * the clock needlessly does no real harm, except use up a
8312 * bit of power potentially.
8314 * We'll limit this to IVB with 3 pipes, since it has only two
8315 * DPLLs and so DPLL sharing is the only way to get three pipes
8316 * driving PCH ports at the same time. On SNB we could do this,
8317 * and potentially avoid enabling the second DPLL, but it's not
8318 * clear if it''s a win or loss power wise. No point in doing
8319 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8321 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
8322 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
8323 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8325 /* compute bitmask from p1 value */
8326 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8328 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8330 switch (crtc_state
->dpll
.p2
) {
8332 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8335 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8338 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8341 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8345 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8346 intel_panel_use_ssc(dev_priv
))
8347 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8349 dpll
|= PLL_REF_INPUT_DREFCLK
;
8351 dpll
|= DPLL_VCO_ENABLE
;
8353 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8354 crtc_state
->dpll_hw_state
.fp0
= fp
;
8355 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8358 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8359 struct intel_crtc_state
*crtc_state
)
8361 struct drm_device
*dev
= crtc
->base
.dev
;
8362 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8363 const struct intel_limit
*limit
;
8364 int refclk
= 120000;
8366 memset(&crtc_state
->dpll_hw_state
, 0,
8367 sizeof(crtc_state
->dpll_hw_state
));
8369 crtc
->lowfreq_avail
= false;
8371 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8372 if (!crtc_state
->has_pch_encoder
)
8375 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8376 if (intel_panel_use_ssc(dev_priv
)) {
8377 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8378 dev_priv
->vbt
.lvds_ssc_freq
);
8379 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8382 if (intel_is_dual_link_lvds(dev
)) {
8383 if (refclk
== 100000)
8384 limit
= &intel_limits_ironlake_dual_lvds_100m
;
8386 limit
= &intel_limits_ironlake_dual_lvds
;
8388 if (refclk
== 100000)
8389 limit
= &intel_limits_ironlake_single_lvds_100m
;
8391 limit
= &intel_limits_ironlake_single_lvds
;
8394 limit
= &intel_limits_ironlake_dac
;
8397 if (!crtc_state
->clock_set
&&
8398 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8399 refclk
, NULL
, &crtc_state
->dpll
)) {
8400 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8404 ironlake_compute_dpll(crtc
, crtc_state
, NULL
);
8406 if (!intel_get_shared_dpll(crtc
, crtc_state
, NULL
)) {
8407 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8408 pipe_name(crtc
->pipe
));
8415 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8416 struct intel_link_m_n
*m_n
)
8418 struct drm_device
*dev
= crtc
->base
.dev
;
8419 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8420 enum pipe pipe
= crtc
->pipe
;
8422 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8423 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8424 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8426 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8427 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8428 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8431 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8432 enum transcoder transcoder
,
8433 struct intel_link_m_n
*m_n
,
8434 struct intel_link_m_n
*m2_n2
)
8436 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8437 enum pipe pipe
= crtc
->pipe
;
8439 if (INTEL_GEN(dev_priv
) >= 5) {
8440 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8441 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8442 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8444 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8445 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8446 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8447 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8448 * gen < 8) and if DRRS is supported (to make sure the
8449 * registers are not unnecessarily read).
8451 if (m2_n2
&& INTEL_GEN(dev_priv
) < 8 &&
8452 crtc
->config
->has_drrs
) {
8453 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8454 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8455 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8457 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8458 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8459 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8462 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8463 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8464 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8466 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8467 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8468 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8472 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8473 struct intel_crtc_state
*pipe_config
)
8475 if (pipe_config
->has_pch_encoder
)
8476 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8478 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8479 &pipe_config
->dp_m_n
,
8480 &pipe_config
->dp_m2_n2
);
8483 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8484 struct intel_crtc_state
*pipe_config
)
8486 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8487 &pipe_config
->fdi_m_n
, NULL
);
8490 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8491 struct intel_crtc_state
*pipe_config
)
8493 struct drm_device
*dev
= crtc
->base
.dev
;
8494 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8495 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8496 uint32_t ps_ctrl
= 0;
8500 /* find scaler attached to this pipe */
8501 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8502 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8503 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8505 pipe_config
->pch_pfit
.enabled
= true;
8506 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8507 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8512 scaler_state
->scaler_id
= id
;
8514 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8516 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8521 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8522 struct intel_initial_plane_config
*plane_config
)
8524 struct drm_device
*dev
= crtc
->base
.dev
;
8525 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8526 u32 val
, base
, offset
, stride_mult
, tiling
;
8527 int pipe
= crtc
->pipe
;
8528 int fourcc
, pixel_format
;
8529 unsigned int aligned_height
;
8530 struct drm_framebuffer
*fb
;
8531 struct intel_framebuffer
*intel_fb
;
8533 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8535 DRM_DEBUG_KMS("failed to alloc fb\n");
8539 fb
= &intel_fb
->base
;
8543 val
= I915_READ(PLANE_CTL(pipe
, 0));
8544 if (!(val
& PLANE_CTL_ENABLE
))
8547 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8548 fourcc
= skl_format_to_fourcc(pixel_format
,
8549 val
& PLANE_CTL_ORDER_RGBX
,
8550 val
& PLANE_CTL_ALPHA_MASK
);
8551 fb
->format
= drm_format_info(fourcc
);
8553 tiling
= val
& PLANE_CTL_TILED_MASK
;
8555 case PLANE_CTL_TILED_LINEAR
:
8556 fb
->modifier
= DRM_FORMAT_MOD_LINEAR
;
8558 case PLANE_CTL_TILED_X
:
8559 plane_config
->tiling
= I915_TILING_X
;
8560 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8562 case PLANE_CTL_TILED_Y
:
8563 if (val
& PLANE_CTL_DECOMPRESSION_ENABLE
)
8564 fb
->modifier
= I915_FORMAT_MOD_Y_TILED_CCS
;
8566 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
8568 case PLANE_CTL_TILED_YF
:
8569 if (val
& PLANE_CTL_DECOMPRESSION_ENABLE
)
8570 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED_CCS
;
8572 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
8575 MISSING_CASE(tiling
);
8579 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8580 plane_config
->base
= base
;
8582 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8584 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8585 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8586 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8588 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8589 stride_mult
= intel_fb_stride_alignment(fb
, 0);
8590 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8592 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8594 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8596 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8597 pipe_name(pipe
), fb
->width
, fb
->height
,
8598 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8599 plane_config
->size
);
8601 plane_config
->fb
= intel_fb
;
8608 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8609 struct intel_crtc_state
*pipe_config
)
8611 struct drm_device
*dev
= crtc
->base
.dev
;
8612 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8615 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8617 if (tmp
& PF_ENABLE
) {
8618 pipe_config
->pch_pfit
.enabled
= true;
8619 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8620 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8622 /* We currently do not free assignements of panel fitters on
8623 * ivb/hsw (since we don't use the higher upscaling modes which
8624 * differentiates them) so just WARN about this case for now. */
8625 if (IS_GEN7(dev_priv
)) {
8626 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8627 PF_PIPE_SEL_IVB(crtc
->pipe
));
8633 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8634 struct intel_initial_plane_config
*plane_config
)
8636 struct drm_device
*dev
= crtc
->base
.dev
;
8637 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8638 u32 val
, base
, offset
;
8639 int pipe
= crtc
->pipe
;
8640 int fourcc
, pixel_format
;
8641 unsigned int aligned_height
;
8642 struct drm_framebuffer
*fb
;
8643 struct intel_framebuffer
*intel_fb
;
8645 val
= I915_READ(DSPCNTR(pipe
));
8646 if (!(val
& DISPLAY_PLANE_ENABLE
))
8649 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8651 DRM_DEBUG_KMS("failed to alloc fb\n");
8655 fb
= &intel_fb
->base
;
8659 if (INTEL_GEN(dev_priv
) >= 4) {
8660 if (val
& DISPPLANE_TILED
) {
8661 plane_config
->tiling
= I915_TILING_X
;
8662 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8666 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8667 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8668 fb
->format
= drm_format_info(fourcc
);
8670 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8671 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
8672 offset
= I915_READ(DSPOFFSET(pipe
));
8674 if (plane_config
->tiling
)
8675 offset
= I915_READ(DSPTILEOFF(pipe
));
8677 offset
= I915_READ(DSPLINOFF(pipe
));
8679 plane_config
->base
= base
;
8681 val
= I915_READ(PIPESRC(pipe
));
8682 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8683 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8685 val
= I915_READ(DSPSTRIDE(pipe
));
8686 fb
->pitches
[0] = val
& 0xffffffc0;
8688 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8690 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8692 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8693 pipe_name(pipe
), fb
->width
, fb
->height
,
8694 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8695 plane_config
->size
);
8697 plane_config
->fb
= intel_fb
;
8700 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8701 struct intel_crtc_state
*pipe_config
)
8703 struct drm_device
*dev
= crtc
->base
.dev
;
8704 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8705 enum intel_display_power_domain power_domain
;
8709 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8710 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8713 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8714 pipe_config
->shared_dpll
= NULL
;
8717 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8718 if (!(tmp
& PIPECONF_ENABLE
))
8721 switch (tmp
& PIPECONF_BPC_MASK
) {
8723 pipe_config
->pipe_bpp
= 18;
8726 pipe_config
->pipe_bpp
= 24;
8728 case PIPECONF_10BPC
:
8729 pipe_config
->pipe_bpp
= 30;
8731 case PIPECONF_12BPC
:
8732 pipe_config
->pipe_bpp
= 36;
8738 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8739 pipe_config
->limited_color_range
= true;
8741 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8742 struct intel_shared_dpll
*pll
;
8743 enum intel_dpll_id pll_id
;
8745 pipe_config
->has_pch_encoder
= true;
8747 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8748 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8749 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8751 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8753 if (HAS_PCH_IBX(dev_priv
)) {
8755 * The pipe->pch transcoder and pch transcoder->pll
8758 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
8760 tmp
= I915_READ(PCH_DPLL_SEL
);
8761 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8762 pll_id
= DPLL_ID_PCH_PLL_B
;
8764 pll_id
= DPLL_ID_PCH_PLL_A
;
8767 pipe_config
->shared_dpll
=
8768 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
8769 pll
= pipe_config
->shared_dpll
;
8771 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
8772 &pipe_config
->dpll_hw_state
));
8774 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8775 pipe_config
->pixel_multiplier
=
8776 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8777 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8779 ironlake_pch_clock_get(crtc
, pipe_config
);
8781 pipe_config
->pixel_multiplier
= 1;
8784 intel_get_pipe_timings(crtc
, pipe_config
);
8785 intel_get_pipe_src_size(crtc
, pipe_config
);
8787 ironlake_get_pfit_config(crtc
, pipe_config
);
8792 intel_display_power_put(dev_priv
, power_domain
);
8797 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8799 struct drm_device
*dev
= &dev_priv
->drm
;
8800 struct intel_crtc
*crtc
;
8802 for_each_intel_crtc(dev
, crtc
)
8803 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8804 pipe_name(crtc
->pipe
));
8806 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL
)),
8807 "Display power well on\n");
8808 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8809 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8810 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8811 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON
, "Panel power on\n");
8812 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8813 "CPU PWM1 enabled\n");
8814 if (IS_HASWELL(dev_priv
))
8815 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8816 "CPU PWM2 enabled\n");
8817 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8818 "PCH PWM1 enabled\n");
8819 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8820 "Utility pin enabled\n");
8821 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8824 * In theory we can still leave IRQs enabled, as long as only the HPD
8825 * interrupts remain enabled. We used to check for that, but since it's
8826 * gen-specific and since we only disable LCPLL after we fully disable
8827 * the interrupts, the check below should be enough.
8829 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8832 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8834 if (IS_HASWELL(dev_priv
))
8835 return I915_READ(D_COMP_HSW
);
8837 return I915_READ(D_COMP_BDW
);
8840 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8842 if (IS_HASWELL(dev_priv
)) {
8843 mutex_lock(&dev_priv
->rps
.hw_lock
);
8844 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8846 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8847 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8849 I915_WRITE(D_COMP_BDW
, val
);
8850 POSTING_READ(D_COMP_BDW
);
8855 * This function implements pieces of two sequences from BSpec:
8856 * - Sequence for display software to disable LCPLL
8857 * - Sequence for display software to allow package C8+
8858 * The steps implemented here are just the steps that actually touch the LCPLL
8859 * register. Callers should take care of disabling all the display engine
8860 * functions, doing the mode unset, fixing interrupts, etc.
8862 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
8863 bool switch_to_fclk
, bool allow_power_down
)
8867 assert_can_disable_lcpll(dev_priv
);
8869 val
= I915_READ(LCPLL_CTL
);
8871 if (switch_to_fclk
) {
8872 val
|= LCPLL_CD_SOURCE_FCLK
;
8873 I915_WRITE(LCPLL_CTL
, val
);
8875 if (wait_for_us(I915_READ(LCPLL_CTL
) &
8876 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
8877 DRM_ERROR("Switching to FCLK failed\n");
8879 val
= I915_READ(LCPLL_CTL
);
8882 val
|= LCPLL_PLL_DISABLE
;
8883 I915_WRITE(LCPLL_CTL
, val
);
8884 POSTING_READ(LCPLL_CTL
);
8886 if (intel_wait_for_register(dev_priv
, LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
8887 DRM_ERROR("LCPLL still locked\n");
8889 val
= hsw_read_dcomp(dev_priv
);
8890 val
|= D_COMP_COMP_DISABLE
;
8891 hsw_write_dcomp(dev_priv
, val
);
8894 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
8896 DRM_ERROR("D_COMP RCOMP still in progress\n");
8898 if (allow_power_down
) {
8899 val
= I915_READ(LCPLL_CTL
);
8900 val
|= LCPLL_POWER_DOWN_ALLOW
;
8901 I915_WRITE(LCPLL_CTL
, val
);
8902 POSTING_READ(LCPLL_CTL
);
8907 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8910 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
8914 val
= I915_READ(LCPLL_CTL
);
8916 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
8917 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
8921 * Make sure we're not on PC8 state before disabling PC8, otherwise
8922 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8924 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
8926 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
8927 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
8928 I915_WRITE(LCPLL_CTL
, val
);
8929 POSTING_READ(LCPLL_CTL
);
8932 val
= hsw_read_dcomp(dev_priv
);
8933 val
|= D_COMP_COMP_FORCE
;
8934 val
&= ~D_COMP_COMP_DISABLE
;
8935 hsw_write_dcomp(dev_priv
, val
);
8937 val
= I915_READ(LCPLL_CTL
);
8938 val
&= ~LCPLL_PLL_DISABLE
;
8939 I915_WRITE(LCPLL_CTL
, val
);
8941 if (intel_wait_for_register(dev_priv
,
8942 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
8944 DRM_ERROR("LCPLL not locked yet\n");
8946 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8947 val
= I915_READ(LCPLL_CTL
);
8948 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8949 I915_WRITE(LCPLL_CTL
, val
);
8951 if (wait_for_us((I915_READ(LCPLL_CTL
) &
8952 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8953 DRM_ERROR("Switching back to LCPLL failed\n");
8956 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8957 intel_update_cdclk(dev_priv
);
8961 * Package states C8 and deeper are really deep PC states that can only be
8962 * reached when all the devices on the system allow it, so even if the graphics
8963 * device allows PC8+, it doesn't mean the system will actually get to these
8964 * states. Our driver only allows PC8+ when going into runtime PM.
8966 * The requirements for PC8+ are that all the outputs are disabled, the power
8967 * well is disabled and most interrupts are disabled, and these are also
8968 * requirements for runtime PM. When these conditions are met, we manually do
8969 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8970 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8973 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8974 * the state of some registers, so when we come back from PC8+ we need to
8975 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8976 * need to take care of the registers kept by RC6. Notice that this happens even
8977 * if we don't put the device in PCI D3 state (which is what currently happens
8978 * because of the runtime PM support).
8980 * For more, read "Display Sequences for Package C8" on the hardware
8983 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8987 DRM_DEBUG_KMS("Enabling package C8+\n");
8989 if (HAS_PCH_LPT_LP(dev_priv
)) {
8990 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8991 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8992 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8995 lpt_disable_clkout_dp(dev_priv
);
8996 hsw_disable_lcpll(dev_priv
, true, true);
8999 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9003 DRM_DEBUG_KMS("Disabling package C8+\n");
9005 hsw_restore_lcpll(dev_priv
);
9006 lpt_init_pch_refclk(dev_priv
);
9008 if (HAS_PCH_LPT_LP(dev_priv
)) {
9009 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9010 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9011 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9015 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9016 struct intel_crtc_state
*crtc_state
)
9018 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
)) {
9019 struct intel_encoder
*encoder
=
9020 intel_ddi_get_crtc_new_encoder(crtc_state
);
9022 if (!intel_get_shared_dpll(crtc
, crtc_state
, encoder
)) {
9023 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9024 pipe_name(crtc
->pipe
));
9029 crtc
->lowfreq_avail
= false;
9034 static void cannonlake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9036 struct intel_crtc_state
*pipe_config
)
9038 enum intel_dpll_id id
;
9041 temp
= I915_READ(DPCLKA_CFGCR0
) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9042 id
= temp
>> (port
* 2);
9044 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL2
))
9047 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9050 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9052 struct intel_crtc_state
*pipe_config
)
9054 enum intel_dpll_id id
;
9058 id
= DPLL_ID_SKL_DPLL0
;
9061 id
= DPLL_ID_SKL_DPLL1
;
9064 id
= DPLL_ID_SKL_DPLL2
;
9067 DRM_ERROR("Incorrect port type\n");
9071 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9074 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9076 struct intel_crtc_state
*pipe_config
)
9078 enum intel_dpll_id id
;
9081 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9082 id
= temp
>> (port
* 3 + 1);
9084 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
9087 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9090 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9092 struct intel_crtc_state
*pipe_config
)
9094 enum intel_dpll_id id
;
9095 uint32_t ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9097 switch (ddi_pll_sel
) {
9098 case PORT_CLK_SEL_WRPLL1
:
9099 id
= DPLL_ID_WRPLL1
;
9101 case PORT_CLK_SEL_WRPLL2
:
9102 id
= DPLL_ID_WRPLL2
;
9104 case PORT_CLK_SEL_SPLL
:
9107 case PORT_CLK_SEL_LCPLL_810
:
9108 id
= DPLL_ID_LCPLL_810
;
9110 case PORT_CLK_SEL_LCPLL_1350
:
9111 id
= DPLL_ID_LCPLL_1350
;
9113 case PORT_CLK_SEL_LCPLL_2700
:
9114 id
= DPLL_ID_LCPLL_2700
;
9117 MISSING_CASE(ddi_pll_sel
);
9119 case PORT_CLK_SEL_NONE
:
9123 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9126 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9127 struct intel_crtc_state
*pipe_config
,
9128 u64
*power_domain_mask
)
9130 struct drm_device
*dev
= crtc
->base
.dev
;
9131 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9132 enum intel_display_power_domain power_domain
;
9136 * The pipe->transcoder mapping is fixed with the exception of the eDP
9137 * transcoder handled below.
9139 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9142 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9143 * consistency and less surprising code; it's in always on power).
9145 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9146 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9147 enum pipe trans_edp_pipe
;
9148 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9150 WARN(1, "unknown pipe linked to edp transcoder\n");
9151 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9152 case TRANS_DDI_EDP_INPUT_A_ON
:
9153 trans_edp_pipe
= PIPE_A
;
9155 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9156 trans_edp_pipe
= PIPE_B
;
9158 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9159 trans_edp_pipe
= PIPE_C
;
9163 if (trans_edp_pipe
== crtc
->pipe
)
9164 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9167 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9168 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9170 *power_domain_mask
|= BIT_ULL(power_domain
);
9172 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9174 return tmp
& PIPECONF_ENABLE
;
9177 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
9178 struct intel_crtc_state
*pipe_config
,
9179 u64
*power_domain_mask
)
9181 struct drm_device
*dev
= crtc
->base
.dev
;
9182 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9183 enum intel_display_power_domain power_domain
;
9185 enum transcoder cpu_transcoder
;
9188 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
9190 cpu_transcoder
= TRANSCODER_DSI_A
;
9192 cpu_transcoder
= TRANSCODER_DSI_C
;
9194 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
9195 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9197 *power_domain_mask
|= BIT_ULL(power_domain
);
9200 * The PLL needs to be enabled with a valid divider
9201 * configuration, otherwise accessing DSI registers will hang
9202 * the machine. See BSpec North Display Engine
9203 * registers/MIPI[BXT]. We can break out here early, since we
9204 * need the same DSI PLL to be enabled for both DSI ports.
9206 if (!intel_dsi_pll_is_enabled(dev_priv
))
9209 /* XXX: this works for video mode only */
9210 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
9211 if (!(tmp
& DPI_ENABLE
))
9214 tmp
= I915_READ(MIPI_CTRL(port
));
9215 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
9218 pipe_config
->cpu_transcoder
= cpu_transcoder
;
9222 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
9225 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9226 struct intel_crtc_state
*pipe_config
)
9228 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9229 struct intel_shared_dpll
*pll
;
9233 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9235 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9237 if (IS_CANNONLAKE(dev_priv
))
9238 cannonlake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9239 else if (IS_GEN9_BC(dev_priv
))
9240 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9241 else if (IS_GEN9_LP(dev_priv
))
9242 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9244 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9246 pll
= pipe_config
->shared_dpll
;
9248 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9249 &pipe_config
->dpll_hw_state
));
9253 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9254 * DDI E. So just check whether this pipe is wired to DDI E and whether
9255 * the PCH transcoder is on.
9257 if (INTEL_GEN(dev_priv
) < 9 &&
9258 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9259 pipe_config
->has_pch_encoder
= true;
9261 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9262 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9263 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9265 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9269 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9270 struct intel_crtc_state
*pipe_config
)
9272 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9273 enum intel_display_power_domain power_domain
;
9274 u64 power_domain_mask
;
9277 intel_crtc_init_scalers(crtc
, pipe_config
);
9279 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9280 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9282 power_domain_mask
= BIT_ULL(power_domain
);
9284 pipe_config
->shared_dpll
= NULL
;
9286 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
9288 if (IS_GEN9_LP(dev_priv
) &&
9289 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &power_domain_mask
)) {
9297 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
9298 haswell_get_ddi_port_state(crtc
, pipe_config
);
9299 intel_get_pipe_timings(crtc
, pipe_config
);
9302 intel_get_pipe_src_size(crtc
, pipe_config
);
9304 pipe_config
->gamma_mode
=
9305 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
9307 if (IS_BROADWELL(dev_priv
) || dev_priv
->info
.gen
>= 9) {
9308 u32 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
9309 bool clrspace_yuv
= tmp
& PIPEMISC_OUTPUT_COLORSPACE_YUV
;
9311 if (IS_GEMINILAKE(dev_priv
) || dev_priv
->info
.gen
>= 10) {
9312 bool blend_mode_420
= tmp
&
9313 PIPEMISC_YUV420_MODE_FULL_BLEND
;
9315 pipe_config
->ycbcr420
= tmp
& PIPEMISC_YUV420_ENABLE
;
9316 if (pipe_config
->ycbcr420
!= clrspace_yuv
||
9317 pipe_config
->ycbcr420
!= blend_mode_420
)
9318 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp
);
9319 } else if (clrspace_yuv
) {
9320 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9324 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9325 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
9326 power_domain_mask
|= BIT_ULL(power_domain
);
9327 if (INTEL_GEN(dev_priv
) >= 9)
9328 skylake_get_pfit_config(crtc
, pipe_config
);
9330 ironlake_get_pfit_config(crtc
, pipe_config
);
9333 if (IS_HASWELL(dev_priv
))
9334 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9335 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9337 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
9338 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
9339 pipe_config
->pixel_multiplier
=
9340 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9342 pipe_config
->pixel_multiplier
= 1;
9346 for_each_power_domain(power_domain
, power_domain_mask
)
9347 intel_display_power_put(dev_priv
, power_domain
);
9352 static u32
intel_cursor_base(const struct intel_plane_state
*plane_state
)
9354 struct drm_i915_private
*dev_priv
=
9355 to_i915(plane_state
->base
.plane
->dev
);
9356 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9357 const struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9360 if (INTEL_INFO(dev_priv
)->cursor_needs_physical
)
9361 base
= obj
->phys_handle
->busaddr
;
9363 base
= intel_plane_ggtt_offset(plane_state
);
9365 base
+= plane_state
->main
.offset
;
9367 /* ILK+ do this automagically */
9368 if (HAS_GMCH_DISPLAY(dev_priv
) &&
9369 plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
9370 base
+= (plane_state
->base
.crtc_h
*
9371 plane_state
->base
.crtc_w
- 1) * fb
->format
->cpp
[0];
9376 static u32
intel_cursor_position(const struct intel_plane_state
*plane_state
)
9378 int x
= plane_state
->base
.crtc_x
;
9379 int y
= plane_state
->base
.crtc_y
;
9383 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9386 pos
|= x
<< CURSOR_X_SHIFT
;
9389 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9392 pos
|= y
<< CURSOR_Y_SHIFT
;
9397 static bool intel_cursor_size_ok(const struct intel_plane_state
*plane_state
)
9399 const struct drm_mode_config
*config
=
9400 &plane_state
->base
.plane
->dev
->mode_config
;
9401 int width
= plane_state
->base
.crtc_w
;
9402 int height
= plane_state
->base
.crtc_h
;
9404 return width
> 0 && width
<= config
->cursor_width
&&
9405 height
> 0 && height
<= config
->cursor_height
;
9408 static int intel_check_cursor(struct intel_crtc_state
*crtc_state
,
9409 struct intel_plane_state
*plane_state
)
9411 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9416 ret
= drm_plane_helper_check_state(&plane_state
->base
,
9418 DRM_PLANE_HELPER_NO_SCALING
,
9419 DRM_PLANE_HELPER_NO_SCALING
,
9427 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
9428 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9432 src_x
= plane_state
->base
.src_x
>> 16;
9433 src_y
= plane_state
->base
.src_y
>> 16;
9435 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
9436 offset
= intel_compute_tile_offset(&src_x
, &src_y
, plane_state
, 0);
9438 if (src_x
!= 0 || src_y
!= 0) {
9439 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9443 plane_state
->main
.offset
= offset
;
9448 static u32
i845_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
9449 const struct intel_plane_state
*plane_state
)
9451 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9453 return CURSOR_ENABLE
|
9454 CURSOR_GAMMA_ENABLE
|
9455 CURSOR_FORMAT_ARGB
|
9456 CURSOR_STRIDE(fb
->pitches
[0]);
9459 static bool i845_cursor_size_ok(const struct intel_plane_state
*plane_state
)
9461 int width
= plane_state
->base
.crtc_w
;
9464 * 845g/865g are only limited by the width of their cursors,
9465 * the height is arbitrary up to the precision of the register.
9467 return intel_cursor_size_ok(plane_state
) && IS_ALIGNED(width
, 64);
9470 static int i845_check_cursor(struct intel_plane
*plane
,
9471 struct intel_crtc_state
*crtc_state
,
9472 struct intel_plane_state
*plane_state
)
9474 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9477 ret
= intel_check_cursor(crtc_state
, plane_state
);
9481 /* if we want to turn off the cursor ignore width and height */
9485 /* Check for which cursor types we support */
9486 if (!i845_cursor_size_ok(plane_state
)) {
9487 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9488 plane_state
->base
.crtc_w
,
9489 plane_state
->base
.crtc_h
);
9493 switch (fb
->pitches
[0]) {
9500 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9505 plane_state
->ctl
= i845_cursor_ctl(crtc_state
, plane_state
);
9510 static void i845_update_cursor(struct intel_plane
*plane
,
9511 const struct intel_crtc_state
*crtc_state
,
9512 const struct intel_plane_state
*plane_state
)
9514 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
9515 u32 cntl
= 0, base
= 0, pos
= 0, size
= 0;
9516 unsigned long irqflags
;
9518 if (plane_state
&& plane_state
->base
.visible
) {
9519 unsigned int width
= plane_state
->base
.crtc_w
;
9520 unsigned int height
= plane_state
->base
.crtc_h
;
9522 cntl
= plane_state
->ctl
;
9523 size
= (height
<< 12) | width
;
9525 base
= intel_cursor_base(plane_state
);
9526 pos
= intel_cursor_position(plane_state
);
9529 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
9531 /* On these chipsets we can only modify the base/size/stride
9532 * whilst the cursor is disabled.
9534 if (plane
->cursor
.base
!= base
||
9535 plane
->cursor
.size
!= size
||
9536 plane
->cursor
.cntl
!= cntl
) {
9537 I915_WRITE_FW(CURCNTR(PIPE_A
), 0);
9538 I915_WRITE_FW(CURBASE(PIPE_A
), base
);
9539 I915_WRITE_FW(CURSIZE
, size
);
9540 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
9541 I915_WRITE_FW(CURCNTR(PIPE_A
), cntl
);
9543 plane
->cursor
.base
= base
;
9544 plane
->cursor
.size
= size
;
9545 plane
->cursor
.cntl
= cntl
;
9547 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
9550 POSTING_READ_FW(CURCNTR(PIPE_A
));
9552 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
9555 static void i845_disable_cursor(struct intel_plane
*plane
,
9556 struct intel_crtc
*crtc
)
9558 i845_update_cursor(plane
, NULL
, NULL
);
9561 static u32
i9xx_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
9562 const struct intel_plane_state
*plane_state
)
9564 struct drm_i915_private
*dev_priv
=
9565 to_i915(plane_state
->base
.plane
->dev
);
9566 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9569 cntl
= MCURSOR_GAMMA_ENABLE
;
9571 if (HAS_DDI(dev_priv
))
9572 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9574 cntl
|= MCURSOR_PIPE_SELECT(crtc
->pipe
);
9576 switch (plane_state
->base
.crtc_w
) {
9578 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9581 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9584 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9587 MISSING_CASE(plane_state
->base
.crtc_w
);
9591 if (plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
9592 cntl
|= CURSOR_ROTATE_180
;
9597 static bool i9xx_cursor_size_ok(const struct intel_plane_state
*plane_state
)
9599 struct drm_i915_private
*dev_priv
=
9600 to_i915(plane_state
->base
.plane
->dev
);
9601 int width
= plane_state
->base
.crtc_w
;
9602 int height
= plane_state
->base
.crtc_h
;
9604 if (!intel_cursor_size_ok(plane_state
))
9607 /* Cursor width is limited to a few power-of-two sizes */
9618 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9619 * height from 8 lines up to the cursor width, when the
9620 * cursor is not rotated. Everything else requires square
9623 if (HAS_CUR_FBC(dev_priv
) &&
9624 plane_state
->base
.rotation
& DRM_MODE_ROTATE_0
) {
9625 if (height
< 8 || height
> width
)
9628 if (height
!= width
)
9635 static int i9xx_check_cursor(struct intel_plane
*plane
,
9636 struct intel_crtc_state
*crtc_state
,
9637 struct intel_plane_state
*plane_state
)
9639 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
9640 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9641 enum pipe pipe
= plane
->pipe
;
9644 ret
= intel_check_cursor(crtc_state
, plane_state
);
9648 /* if we want to turn off the cursor ignore width and height */
9652 /* Check for which cursor types we support */
9653 if (!i9xx_cursor_size_ok(plane_state
)) {
9654 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9655 plane_state
->base
.crtc_w
,
9656 plane_state
->base
.crtc_h
);
9660 if (fb
->pitches
[0] != plane_state
->base
.crtc_w
* fb
->format
->cpp
[0]) {
9661 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9662 fb
->pitches
[0], plane_state
->base
.crtc_w
);
9667 * There's something wrong with the cursor on CHV pipe C.
9668 * If it straddles the left edge of the screen then
9669 * moving it away from the edge or disabling it often
9670 * results in a pipe underrun, and often that can lead to
9671 * dead pipe (constant underrun reported, and it scans
9672 * out just a solid color). To recover from that, the
9673 * display power well must be turned off and on again.
9674 * Refuse the put the cursor into that compromised position.
9676 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_C
&&
9677 plane_state
->base
.visible
&& plane_state
->base
.crtc_x
< 0) {
9678 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9682 plane_state
->ctl
= i9xx_cursor_ctl(crtc_state
, plane_state
);
9687 static void i9xx_update_cursor(struct intel_plane
*plane
,
9688 const struct intel_crtc_state
*crtc_state
,
9689 const struct intel_plane_state
*plane_state
)
9691 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
9692 enum pipe pipe
= plane
->pipe
;
9693 u32 cntl
= 0, base
= 0, pos
= 0, fbc_ctl
= 0;
9694 unsigned long irqflags
;
9696 if (plane_state
&& plane_state
->base
.visible
) {
9697 cntl
= plane_state
->ctl
;
9699 if (plane_state
->base
.crtc_h
!= plane_state
->base
.crtc_w
)
9700 fbc_ctl
= CUR_FBC_CTL_EN
| (plane_state
->base
.crtc_h
- 1);
9702 base
= intel_cursor_base(plane_state
);
9703 pos
= intel_cursor_position(plane_state
);
9706 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
9709 * On some platforms writing CURCNTR first will also
9710 * cause CURPOS to be armed by the CURBASE write.
9711 * Without the CURCNTR write the CURPOS write would
9712 * arm itself. Thus we always start the full update
9713 * with a CURCNTR write.
9715 * On other platforms CURPOS always requires the
9716 * CURBASE write to arm the update. Additonally
9717 * a write to any of the cursor register will cancel
9718 * an already armed cursor update. Thus leaving out
9719 * the CURBASE write after CURPOS could lead to a
9720 * cursor that doesn't appear to move, or even change
9721 * shape. Thus we always write CURBASE.
9723 * CURCNTR and CUR_FBC_CTL are always
9724 * armed by the CURBASE write only.
9726 if (plane
->cursor
.base
!= base
||
9727 plane
->cursor
.size
!= fbc_ctl
||
9728 plane
->cursor
.cntl
!= cntl
) {
9729 I915_WRITE_FW(CURCNTR(pipe
), cntl
);
9730 if (HAS_CUR_FBC(dev_priv
))
9731 I915_WRITE_FW(CUR_FBC_CTL(pipe
), fbc_ctl
);
9732 I915_WRITE_FW(CURPOS(pipe
), pos
);
9733 I915_WRITE_FW(CURBASE(pipe
), base
);
9735 plane
->cursor
.base
= base
;
9736 plane
->cursor
.size
= fbc_ctl
;
9737 plane
->cursor
.cntl
= cntl
;
9739 I915_WRITE_FW(CURPOS(pipe
), pos
);
9740 I915_WRITE_FW(CURBASE(pipe
), base
);
9743 POSTING_READ_FW(CURBASE(pipe
));
9745 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
9748 static void i9xx_disable_cursor(struct intel_plane
*plane
,
9749 struct intel_crtc
*crtc
)
9751 i9xx_update_cursor(plane
, NULL
, NULL
);
9755 /* VESA 640x480x72Hz mode to set on the pipe */
9756 static struct drm_display_mode load_detect_mode
= {
9757 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9758 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9761 struct drm_framebuffer
*
9762 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
9763 struct drm_mode_fb_cmd2
*mode_cmd
)
9765 struct intel_framebuffer
*intel_fb
;
9768 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9770 return ERR_PTR(-ENOMEM
);
9772 ret
= intel_framebuffer_init(intel_fb
, obj
, mode_cmd
);
9776 return &intel_fb
->base
;
9780 return ERR_PTR(ret
);
9784 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9786 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9787 return ALIGN(pitch
, 64);
9791 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9793 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9794 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9797 static struct drm_framebuffer
*
9798 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9799 struct drm_display_mode
*mode
,
9802 struct drm_framebuffer
*fb
;
9803 struct drm_i915_gem_object
*obj
;
9804 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9806 obj
= i915_gem_object_create(to_i915(dev
),
9807 intel_framebuffer_size_for_mode(mode
, bpp
));
9809 return ERR_CAST(obj
);
9811 mode_cmd
.width
= mode
->hdisplay
;
9812 mode_cmd
.height
= mode
->vdisplay
;
9813 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9815 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9817 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
9819 i915_gem_object_put(obj
);
9824 static struct drm_framebuffer
*
9825 mode_fits_in_fbdev(struct drm_device
*dev
,
9826 struct drm_display_mode
*mode
)
9828 #ifdef CONFIG_DRM_FBDEV_EMULATION
9829 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9830 struct drm_i915_gem_object
*obj
;
9831 struct drm_framebuffer
*fb
;
9833 if (!dev_priv
->fbdev
)
9836 if (!dev_priv
->fbdev
->fb
)
9839 obj
= dev_priv
->fbdev
->fb
->obj
;
9842 fb
= &dev_priv
->fbdev
->fb
->base
;
9843 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9844 fb
->format
->cpp
[0] * 8))
9847 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9850 drm_framebuffer_reference(fb
);
9857 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
9858 struct drm_crtc
*crtc
,
9859 struct drm_display_mode
*mode
,
9860 struct drm_framebuffer
*fb
,
9863 struct drm_plane_state
*plane_state
;
9864 int hdisplay
, vdisplay
;
9867 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
9868 if (IS_ERR(plane_state
))
9869 return PTR_ERR(plane_state
);
9872 drm_mode_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
9874 hdisplay
= vdisplay
= 0;
9876 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
9879 drm_atomic_set_fb_for_plane(plane_state
, fb
);
9880 plane_state
->crtc_x
= 0;
9881 plane_state
->crtc_y
= 0;
9882 plane_state
->crtc_w
= hdisplay
;
9883 plane_state
->crtc_h
= vdisplay
;
9884 plane_state
->src_x
= x
<< 16;
9885 plane_state
->src_y
= y
<< 16;
9886 plane_state
->src_w
= hdisplay
<< 16;
9887 plane_state
->src_h
= vdisplay
<< 16;
9892 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
9893 struct drm_display_mode
*mode
,
9894 struct intel_load_detect_pipe
*old
,
9895 struct drm_modeset_acquire_ctx
*ctx
)
9897 struct intel_crtc
*intel_crtc
;
9898 struct intel_encoder
*intel_encoder
=
9899 intel_attached_encoder(connector
);
9900 struct drm_crtc
*possible_crtc
;
9901 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9902 struct drm_crtc
*crtc
= NULL
;
9903 struct drm_device
*dev
= encoder
->dev
;
9904 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9905 struct drm_framebuffer
*fb
;
9906 struct drm_mode_config
*config
= &dev
->mode_config
;
9907 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
9908 struct drm_connector_state
*connector_state
;
9909 struct intel_crtc_state
*crtc_state
;
9912 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9913 connector
->base
.id
, connector
->name
,
9914 encoder
->base
.id
, encoder
->name
);
9916 old
->restore_state
= NULL
;
9918 WARN_ON(!drm_modeset_is_locked(&config
->connection_mutex
));
9921 * Algorithm gets a little messy:
9923 * - if the connector already has an assigned crtc, use it (but make
9924 * sure it's on first)
9926 * - try to find the first unused crtc that can drive this connector,
9927 * and use that if we find one
9930 /* See if we already have a CRTC for this connector */
9931 if (connector
->state
->crtc
) {
9932 crtc
= connector
->state
->crtc
;
9934 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9938 /* Make sure the crtc and connector are running */
9942 /* Find an unused one (if possible) */
9943 for_each_crtc(dev
, possible_crtc
) {
9945 if (!(encoder
->possible_crtcs
& (1 << i
)))
9948 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
9952 if (possible_crtc
->state
->enable
) {
9953 drm_modeset_unlock(&possible_crtc
->mutex
);
9957 crtc
= possible_crtc
;
9962 * If we didn't find an unused CRTC, don't use any.
9965 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9971 intel_crtc
= to_intel_crtc(crtc
);
9973 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9977 state
= drm_atomic_state_alloc(dev
);
9978 restore_state
= drm_atomic_state_alloc(dev
);
9979 if (!state
|| !restore_state
) {
9984 state
->acquire_ctx
= ctx
;
9985 restore_state
->acquire_ctx
= ctx
;
9987 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9988 if (IS_ERR(connector_state
)) {
9989 ret
= PTR_ERR(connector_state
);
9993 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
9997 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9998 if (IS_ERR(crtc_state
)) {
9999 ret
= PTR_ERR(crtc_state
);
10003 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10006 mode
= &load_detect_mode
;
10008 /* We need a framebuffer large enough to accommodate all accesses
10009 * that the plane may generate whilst we perform load detection.
10010 * We can not rely on the fbcon either being present (we get called
10011 * during its initialisation to detect all boot displays, or it may
10012 * not even exist) or that it is large enough to satisfy the
10015 fb
= mode_fits_in_fbdev(dev
, mode
);
10017 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10018 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10020 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10022 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10027 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10031 drm_framebuffer_unreference(fb
);
10033 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10037 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10039 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10041 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
10043 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10047 ret
= drm_atomic_commit(state
);
10049 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10053 old
->restore_state
= restore_state
;
10054 drm_atomic_state_put(state
);
10056 /* let the connector get through one full cycle before testing */
10057 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
10062 drm_atomic_state_put(state
);
10065 if (restore_state
) {
10066 drm_atomic_state_put(restore_state
);
10067 restore_state
= NULL
;
10070 if (ret
== -EDEADLK
)
10076 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10077 struct intel_load_detect_pipe
*old
,
10078 struct drm_modeset_acquire_ctx
*ctx
)
10080 struct intel_encoder
*intel_encoder
=
10081 intel_attached_encoder(connector
);
10082 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10083 struct drm_atomic_state
*state
= old
->restore_state
;
10086 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10087 connector
->base
.id
, connector
->name
,
10088 encoder
->base
.id
, encoder
->name
);
10093 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
10095 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10096 drm_atomic_state_put(state
);
10099 static int i9xx_pll_refclk(struct drm_device
*dev
,
10100 const struct intel_crtc_state
*pipe_config
)
10102 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10103 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10105 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10106 return dev_priv
->vbt
.lvds_ssc_freq
;
10107 else if (HAS_PCH_SPLIT(dev_priv
))
10109 else if (!IS_GEN2(dev_priv
))
10115 /* Returns the clock of the currently programmed mode of the given pipe. */
10116 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10117 struct intel_crtc_state
*pipe_config
)
10119 struct drm_device
*dev
= crtc
->base
.dev
;
10120 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10121 int pipe
= pipe_config
->cpu_transcoder
;
10122 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10126 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10128 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10129 fp
= pipe_config
->dpll_hw_state
.fp0
;
10131 fp
= pipe_config
->dpll_hw_state
.fp1
;
10133 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10134 if (IS_PINEVIEW(dev_priv
)) {
10135 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10136 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10138 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10139 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10142 if (!IS_GEN2(dev_priv
)) {
10143 if (IS_PINEVIEW(dev_priv
))
10144 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10145 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10147 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10148 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10150 switch (dpll
& DPLL_MODE_MASK
) {
10151 case DPLLB_MODE_DAC_SERIAL
:
10152 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10155 case DPLLB_MODE_LVDS
:
10156 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10160 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10161 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10165 if (IS_PINEVIEW(dev_priv
))
10166 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10168 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10170 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
10171 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10174 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10175 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10177 if (lvds
& LVDS_CLKB_POWER_UP
)
10182 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10185 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10186 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10188 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10194 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10198 * This value includes pixel_multiplier. We will use
10199 * port_clock to compute adjusted_mode.crtc_clock in the
10200 * encoder's get_config() function.
10202 pipe_config
->port_clock
= port_clock
;
10205 int intel_dotclock_calculate(int link_freq
,
10206 const struct intel_link_m_n
*m_n
)
10209 * The calculation for the data clock is:
10210 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10211 * But we want to avoid losing precison if possible, so:
10212 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10214 * and the link clock is simpler:
10215 * link_clock = (m * link_clock) / n
10221 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10224 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10225 struct intel_crtc_state
*pipe_config
)
10227 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10229 /* read out port_clock from the DPLL */
10230 i9xx_crtc_clock_get(crtc
, pipe_config
);
10233 * In case there is an active pipe without active ports,
10234 * we may need some idea for the dotclock anyway.
10235 * Calculate one based on the FDI configuration.
10237 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10238 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10239 &pipe_config
->fdi_m_n
);
10242 /** Returns the currently programmed mode of the given pipe. */
10243 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10244 struct drm_crtc
*crtc
)
10246 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10247 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10248 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10249 struct drm_display_mode
*mode
;
10250 struct intel_crtc_state
*pipe_config
;
10251 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10252 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10253 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10254 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10255 enum pipe pipe
= intel_crtc
->pipe
;
10257 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10261 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10262 if (!pipe_config
) {
10268 * Construct a pipe_config sufficient for getting the clock info
10269 * back out of crtc_clock_get.
10271 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10272 * to use a real value here instead.
10274 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
10275 pipe_config
->pixel_multiplier
= 1;
10276 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10277 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10278 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10279 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
10281 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
10282 mode
->hdisplay
= (htot
& 0xffff) + 1;
10283 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10284 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10285 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10286 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10287 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10288 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10289 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10291 drm_mode_set_name(mode
);
10293 kfree(pipe_config
);
10298 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10302 drm_crtc_cleanup(crtc
);
10307 * intel_wm_need_update - Check whether watermarks need updating
10308 * @plane: drm plane
10309 * @state: new plane state
10311 * Check current plane state versus the new one to determine whether
10312 * watermarks need to be recalculated.
10314 * Returns true or false.
10316 static bool intel_wm_need_update(struct drm_plane
*plane
,
10317 struct drm_plane_state
*state
)
10319 struct intel_plane_state
*new = to_intel_plane_state(state
);
10320 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
10322 /* Update watermarks on tiling or size changes. */
10323 if (new->base
.visible
!= cur
->base
.visible
)
10326 if (!cur
->base
.fb
|| !new->base
.fb
)
10329 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
10330 cur
->base
.rotation
!= new->base
.rotation
||
10331 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
10332 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
10333 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
10334 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
10340 static bool needs_scaling(struct intel_plane_state
*state
)
10342 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
10343 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
10344 int dst_w
= drm_rect_width(&state
->base
.dst
);
10345 int dst_h
= drm_rect_height(&state
->base
.dst
);
10347 return (src_w
!= dst_w
|| src_h
!= dst_h
);
10350 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
10351 struct drm_plane_state
*plane_state
)
10353 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
10354 struct drm_crtc
*crtc
= crtc_state
->crtc
;
10355 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10356 struct intel_plane
*plane
= to_intel_plane(plane_state
->plane
);
10357 struct drm_device
*dev
= crtc
->dev
;
10358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10359 struct intel_plane_state
*old_plane_state
=
10360 to_intel_plane_state(plane
->base
.state
);
10361 bool mode_changed
= needs_modeset(crtc_state
);
10362 bool was_crtc_enabled
= crtc
->state
->active
;
10363 bool is_crtc_enabled
= crtc_state
->active
;
10364 bool turn_off
, turn_on
, visible
, was_visible
;
10365 struct drm_framebuffer
*fb
= plane_state
->fb
;
10368 if (INTEL_GEN(dev_priv
) >= 9 && plane
->id
!= PLANE_CURSOR
) {
10369 ret
= skl_update_scaler_plane(
10370 to_intel_crtc_state(crtc_state
),
10371 to_intel_plane_state(plane_state
));
10376 was_visible
= old_plane_state
->base
.visible
;
10377 visible
= plane_state
->visible
;
10379 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
10380 was_visible
= false;
10383 * Visibility is calculated as if the crtc was on, but
10384 * after scaler setup everything depends on it being off
10385 * when the crtc isn't active.
10387 * FIXME this is wrong for watermarks. Watermarks should also
10388 * be computed as if the pipe would be active. Perhaps move
10389 * per-plane wm computation to the .check_plane() hook, and
10390 * only combine the results from all planes in the current place?
10392 if (!is_crtc_enabled
) {
10393 plane_state
->visible
= visible
= false;
10394 to_intel_crtc_state(crtc_state
)->active_planes
&= ~BIT(plane
->id
);
10397 if (!was_visible
&& !visible
)
10400 if (fb
!= old_plane_state
->base
.fb
)
10401 pipe_config
->fb_changed
= true;
10403 turn_off
= was_visible
&& (!visible
|| mode_changed
);
10404 turn_on
= visible
&& (!was_visible
|| mode_changed
);
10406 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10407 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
10408 plane
->base
.base
.id
, plane
->base
.name
,
10409 fb
? fb
->base
.id
: -1);
10411 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10412 plane
->base
.base
.id
, plane
->base
.name
,
10413 was_visible
, visible
,
10414 turn_off
, turn_on
, mode_changed
);
10417 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10418 pipe_config
->update_wm_pre
= true;
10420 /* must disable cxsr around plane enable/disable */
10421 if (plane
->id
!= PLANE_CURSOR
)
10422 pipe_config
->disable_cxsr
= true;
10423 } else if (turn_off
) {
10424 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10425 pipe_config
->update_wm_post
= true;
10427 /* must disable cxsr around plane enable/disable */
10428 if (plane
->id
!= PLANE_CURSOR
)
10429 pipe_config
->disable_cxsr
= true;
10430 } else if (intel_wm_need_update(&plane
->base
, plane_state
)) {
10431 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
10432 /* FIXME bollocks */
10433 pipe_config
->update_wm_pre
= true;
10434 pipe_config
->update_wm_post
= true;
10438 if (visible
|| was_visible
)
10439 pipe_config
->fb_bits
|= plane
->frontbuffer_bit
;
10442 * WaCxSRDisabledForSpriteScaling:ivb
10444 * cstate->update_wm was already set above, so this flag will
10445 * take effect when we commit and program watermarks.
10447 if (plane
->id
== PLANE_SPRITE0
&& IS_IVYBRIDGE(dev_priv
) &&
10448 needs_scaling(to_intel_plane_state(plane_state
)) &&
10449 !needs_scaling(old_plane_state
))
10450 pipe_config
->disable_lp_wm
= true;
10455 static bool encoders_cloneable(const struct intel_encoder
*a
,
10456 const struct intel_encoder
*b
)
10458 /* masks could be asymmetric, so check both ways */
10459 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10460 b
->cloneable
& (1 << a
->type
));
10463 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
10464 struct intel_crtc
*crtc
,
10465 struct intel_encoder
*encoder
)
10467 struct intel_encoder
*source_encoder
;
10468 struct drm_connector
*connector
;
10469 struct drm_connector_state
*connector_state
;
10472 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10473 if (connector_state
->crtc
!= &crtc
->base
)
10477 to_intel_encoder(connector_state
->best_encoder
);
10478 if (!encoders_cloneable(encoder
, source_encoder
))
10485 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
10486 struct drm_crtc_state
*crtc_state
)
10488 struct drm_device
*dev
= crtc
->dev
;
10489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10490 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10491 struct intel_crtc_state
*pipe_config
=
10492 to_intel_crtc_state(crtc_state
);
10493 struct drm_atomic_state
*state
= crtc_state
->state
;
10495 bool mode_changed
= needs_modeset(crtc_state
);
10497 if (mode_changed
&& !crtc_state
->active
)
10498 pipe_config
->update_wm_post
= true;
10500 if (mode_changed
&& crtc_state
->enable
&&
10501 dev_priv
->display
.crtc_compute_clock
&&
10502 !WARN_ON(pipe_config
->shared_dpll
)) {
10503 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
10509 if (crtc_state
->color_mgmt_changed
) {
10510 ret
= intel_color_check(crtc
, crtc_state
);
10515 * Changing color management on Intel hardware is
10516 * handled as part of planes update.
10518 crtc_state
->planes_changed
= true;
10522 if (dev_priv
->display
.compute_pipe_wm
) {
10523 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
10525 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10530 if (dev_priv
->display
.compute_intermediate_wm
&&
10531 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
10532 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
10536 * Calculate 'intermediate' watermarks that satisfy both the
10537 * old state and the new state. We can program these
10540 ret
= dev_priv
->display
.compute_intermediate_wm(dev
,
10544 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10547 } else if (dev_priv
->display
.compute_intermediate_wm
) {
10548 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
10549 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
10552 if (INTEL_GEN(dev_priv
) >= 9) {
10554 ret
= skl_update_scaler_crtc(pipe_config
);
10557 ret
= skl_check_pipe_max_pixel_rate(intel_crtc
,
10560 ret
= intel_atomic_setup_scalers(dev_priv
, intel_crtc
,
10567 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
10568 .atomic_begin
= intel_begin_crtc_commit
,
10569 .atomic_flush
= intel_finish_crtc_commit
,
10570 .atomic_check
= intel_crtc_atomic_check
,
10573 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
10575 struct intel_connector
*connector
;
10576 struct drm_connector_list_iter conn_iter
;
10578 drm_connector_list_iter_begin(dev
, &conn_iter
);
10579 for_each_intel_connector_iter(connector
, &conn_iter
) {
10580 if (connector
->base
.state
->crtc
)
10581 drm_connector_unreference(&connector
->base
);
10583 if (connector
->base
.encoder
) {
10584 connector
->base
.state
->best_encoder
=
10585 connector
->base
.encoder
;
10586 connector
->base
.state
->crtc
=
10587 connector
->base
.encoder
->crtc
;
10589 drm_connector_reference(&connector
->base
);
10591 connector
->base
.state
->best_encoder
= NULL
;
10592 connector
->base
.state
->crtc
= NULL
;
10595 drm_connector_list_iter_end(&conn_iter
);
10599 connected_sink_compute_bpp(struct intel_connector
*connector
,
10600 struct intel_crtc_state
*pipe_config
)
10602 const struct drm_display_info
*info
= &connector
->base
.display_info
;
10603 int bpp
= pipe_config
->pipe_bpp
;
10605 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10606 connector
->base
.base
.id
,
10607 connector
->base
.name
);
10609 /* Don't use an invalid EDID bpc value */
10610 if (info
->bpc
!= 0 && info
->bpc
* 3 < bpp
) {
10611 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10612 bpp
, info
->bpc
* 3);
10613 pipe_config
->pipe_bpp
= info
->bpc
* 3;
10616 /* Clamp bpp to 8 on screens without EDID 1.4 */
10617 if (info
->bpc
== 0 && bpp
> 24) {
10618 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10620 pipe_config
->pipe_bpp
= 24;
10625 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10626 struct intel_crtc_state
*pipe_config
)
10628 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10629 struct drm_atomic_state
*state
;
10630 struct drm_connector
*connector
;
10631 struct drm_connector_state
*connector_state
;
10634 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
10635 IS_CHERRYVIEW(dev_priv
)))
10637 else if (INTEL_GEN(dev_priv
) >= 5)
10643 pipe_config
->pipe_bpp
= bpp
;
10645 state
= pipe_config
->base
.state
;
10647 /* Clamp display bpp to EDID value */
10648 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10649 if (connector_state
->crtc
!= &crtc
->base
)
10652 connected_sink_compute_bpp(to_intel_connector(connector
),
10659 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10661 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10662 "type: 0x%x flags: 0x%x\n",
10664 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10665 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10666 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10667 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10671 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
10672 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
10674 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10676 m_n
->gmch_m
, m_n
->gmch_n
,
10677 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
10680 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10681 struct intel_crtc_state
*pipe_config
,
10682 const char *context
)
10684 struct drm_device
*dev
= crtc
->base
.dev
;
10685 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10686 struct drm_plane
*plane
;
10687 struct intel_plane
*intel_plane
;
10688 struct intel_plane_state
*state
;
10689 struct drm_framebuffer
*fb
;
10691 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10692 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
10694 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10695 transcoder_name(pipe_config
->cpu_transcoder
),
10696 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10698 if (pipe_config
->has_pch_encoder
)
10699 intel_dump_m_n_config(pipe_config
, "fdi",
10700 pipe_config
->fdi_lanes
,
10701 &pipe_config
->fdi_m_n
);
10703 if (pipe_config
->ycbcr420
)
10704 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10706 if (intel_crtc_has_dp_encoder(pipe_config
)) {
10707 intel_dump_m_n_config(pipe_config
, "dp m_n",
10708 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
10709 if (pipe_config
->has_drrs
)
10710 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
10711 pipe_config
->lane_count
,
10712 &pipe_config
->dp_m2_n2
);
10715 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10716 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
10718 DRM_DEBUG_KMS("requested mode:\n");
10719 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10720 DRM_DEBUG_KMS("adjusted mode:\n");
10721 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10722 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10723 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10724 pipe_config
->port_clock
,
10725 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
10726 pipe_config
->pixel_rate
);
10728 if (INTEL_GEN(dev_priv
) >= 9)
10729 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10731 pipe_config
->scaler_state
.scaler_users
,
10732 pipe_config
->scaler_state
.scaler_id
);
10734 if (HAS_GMCH_DISPLAY(dev_priv
))
10735 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10736 pipe_config
->gmch_pfit
.control
,
10737 pipe_config
->gmch_pfit
.pgm_ratios
,
10738 pipe_config
->gmch_pfit
.lvds_border_bits
);
10740 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10741 pipe_config
->pch_pfit
.pos
,
10742 pipe_config
->pch_pfit
.size
,
10743 enableddisabled(pipe_config
->pch_pfit
.enabled
));
10745 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10746 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
10748 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
10750 DRM_DEBUG_KMS("planes on this crtc\n");
10751 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
10752 struct drm_format_name_buf format_name
;
10753 intel_plane
= to_intel_plane(plane
);
10754 if (intel_plane
->pipe
!= crtc
->pipe
)
10757 state
= to_intel_plane_state(plane
->state
);
10758 fb
= state
->base
.fb
;
10760 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10761 plane
->base
.id
, plane
->name
, state
->scaler_id
);
10765 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10766 plane
->base
.id
, plane
->name
,
10767 fb
->base
.id
, fb
->width
, fb
->height
,
10768 drm_get_format_name(fb
->format
->format
, &format_name
));
10769 if (INTEL_GEN(dev_priv
) >= 9)
10770 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10772 state
->base
.src
.x1
>> 16,
10773 state
->base
.src
.y1
>> 16,
10774 drm_rect_width(&state
->base
.src
) >> 16,
10775 drm_rect_height(&state
->base
.src
) >> 16,
10776 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
10777 drm_rect_width(&state
->base
.dst
),
10778 drm_rect_height(&state
->base
.dst
));
10782 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
10784 struct drm_device
*dev
= state
->dev
;
10785 struct drm_connector
*connector
;
10786 struct drm_connector_list_iter conn_iter
;
10787 unsigned int used_ports
= 0;
10788 unsigned int used_mst_ports
= 0;
10791 * Walk the connector list instead of the encoder
10792 * list to detect the problem on ddi platforms
10793 * where there's just one encoder per digital port.
10795 drm_connector_list_iter_begin(dev
, &conn_iter
);
10796 drm_for_each_connector_iter(connector
, &conn_iter
) {
10797 struct drm_connector_state
*connector_state
;
10798 struct intel_encoder
*encoder
;
10800 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
10801 if (!connector_state
)
10802 connector_state
= connector
->state
;
10804 if (!connector_state
->best_encoder
)
10807 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10809 WARN_ON(!connector_state
->crtc
);
10811 switch (encoder
->type
) {
10812 unsigned int port_mask
;
10813 case INTEL_OUTPUT_UNKNOWN
:
10814 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
10816 case INTEL_OUTPUT_DP
:
10817 case INTEL_OUTPUT_HDMI
:
10818 case INTEL_OUTPUT_EDP
:
10819 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10821 /* the same port mustn't appear more than once */
10822 if (used_ports
& port_mask
)
10825 used_ports
|= port_mask
;
10827 case INTEL_OUTPUT_DP_MST
:
10829 1 << enc_to_mst(&encoder
->base
)->primary
->port
;
10835 drm_connector_list_iter_end(&conn_iter
);
10837 /* can't mix MST and SST/HDMI on the same port */
10838 if (used_ports
& used_mst_ports
)
10845 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
10847 struct drm_i915_private
*dev_priv
=
10848 to_i915(crtc_state
->base
.crtc
->dev
);
10849 struct intel_crtc_scaler_state scaler_state
;
10850 struct intel_dpll_hw_state dpll_hw_state
;
10851 struct intel_shared_dpll
*shared_dpll
;
10852 struct intel_crtc_wm_state wm_state
;
10855 /* FIXME: before the switch to atomic started, a new pipe_config was
10856 * kzalloc'd. Code that depends on any field being zero should be
10857 * fixed, so that the crtc_state can be safely duplicated. For now,
10858 * only fields that are know to not cause problems are preserved. */
10860 scaler_state
= crtc_state
->scaler_state
;
10861 shared_dpll
= crtc_state
->shared_dpll
;
10862 dpll_hw_state
= crtc_state
->dpll_hw_state
;
10863 force_thru
= crtc_state
->pch_pfit
.force_thru
;
10864 if (IS_G4X(dev_priv
) ||
10865 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
10866 wm_state
= crtc_state
->wm
;
10868 /* Keep base drm_crtc_state intact, only clear our extended struct */
10869 BUILD_BUG_ON(offsetof(struct intel_crtc_state
, base
));
10870 memset(&crtc_state
->base
+ 1, 0,
10871 sizeof(*crtc_state
) - sizeof(crtc_state
->base
));
10873 crtc_state
->scaler_state
= scaler_state
;
10874 crtc_state
->shared_dpll
= shared_dpll
;
10875 crtc_state
->dpll_hw_state
= dpll_hw_state
;
10876 crtc_state
->pch_pfit
.force_thru
= force_thru
;
10877 if (IS_G4X(dev_priv
) ||
10878 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
10879 crtc_state
->wm
= wm_state
;
10883 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10884 struct intel_crtc_state
*pipe_config
)
10886 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
10887 struct intel_encoder
*encoder
;
10888 struct drm_connector
*connector
;
10889 struct drm_connector_state
*connector_state
;
10890 int base_bpp
, ret
= -EINVAL
;
10894 clear_intel_crtc_state(pipe_config
);
10896 pipe_config
->cpu_transcoder
=
10897 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10900 * Sanitize sync polarity flags based on requested ones. If neither
10901 * positive or negative polarity is requested, treat this as meaning
10902 * negative polarity.
10904 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10905 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10906 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10908 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10909 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10910 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10912 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10918 * Determine the real pipe dimensions. Note that stereo modes can
10919 * increase the actual pipe size due to the frame doubling and
10920 * insertion of additional space for blanks between the frame. This
10921 * is stored in the crtc timings. We use the requested mode to do this
10922 * computation to clearly distinguish it from the adjusted mode, which
10923 * can be changed by the connectors in the below retry loop.
10925 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
10926 &pipe_config
->pipe_src_w
,
10927 &pipe_config
->pipe_src_h
);
10929 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10930 if (connector_state
->crtc
!= crtc
)
10933 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10935 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
10936 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10941 * Determine output_types before calling the .compute_config()
10942 * hooks so that the hooks can use this information safely.
10944 pipe_config
->output_types
|= 1 << encoder
->type
;
10948 /* Ensure the port clock defaults are reset when retrying. */
10949 pipe_config
->port_clock
= 0;
10950 pipe_config
->pixel_multiplier
= 1;
10952 /* Fill in default crtc timings, allow encoders to overwrite them. */
10953 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10954 CRTC_STEREO_DOUBLE
);
10956 /* Pass our mode to the connectors and the CRTC to give them a chance to
10957 * adjust it according to limitations or connector properties, and also
10958 * a chance to reject the mode entirely.
10960 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10961 if (connector_state
->crtc
!= crtc
)
10964 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10966 if (!(encoder
->compute_config(encoder
, pipe_config
, connector_state
))) {
10967 DRM_DEBUG_KMS("Encoder config failure\n");
10972 /* Set default port clock if not overwritten by the encoder. Needs to be
10973 * done afterwards in case the encoder adjusts the mode. */
10974 if (!pipe_config
->port_clock
)
10975 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10976 * pipe_config
->pixel_multiplier
;
10978 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10980 DRM_DEBUG_KMS("CRTC fixup failed\n");
10984 if (ret
== RETRY
) {
10985 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10990 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10992 goto encoder_retry
;
10995 /* Dithering seems to not pass-through bits correctly when it should, so
10996 * only enable it on 6bpc panels and when its not a compliance
10997 * test requesting 6bpc video pattern.
10999 pipe_config
->dither
= (pipe_config
->pipe_bpp
== 6*3) &&
11000 !pipe_config
->dither_force_disable
;
11001 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11002 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11009 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
11011 struct drm_crtc
*crtc
;
11012 struct drm_crtc_state
*new_crtc_state
;
11015 /* Double check state. */
11016 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
11017 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(new_crtc_state
);
11020 * Update legacy state to satisfy fbc code. This can
11021 * be removed when fbc uses the atomic state.
11023 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
11024 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
11026 crtc
->primary
->fb
= plane_state
->fb
;
11027 crtc
->x
= plane_state
->src_x
>> 16;
11028 crtc
->y
= plane_state
->src_y
>> 16;
11033 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11037 if (clock1
== clock2
)
11040 if (!clock1
|| !clock2
)
11043 diff
= abs(clock1
- clock2
);
11045 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11052 intel_compare_m_n(unsigned int m
, unsigned int n
,
11053 unsigned int m2
, unsigned int n2
,
11056 if (m
== m2
&& n
== n2
)
11059 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
11062 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
11069 } else if (n
< n2
) {
11079 return intel_fuzzy_clock_check(m
, m2
);
11083 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
11084 struct intel_link_m_n
*m2_n2
,
11087 if (m_n
->tu
== m2_n2
->tu
&&
11088 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
11089 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
11090 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
11091 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
11101 static void __printf(3, 4)
11102 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
11105 unsigned int category
;
11106 struct va_format vaf
;
11110 level
= KERN_DEBUG
;
11111 category
= DRM_UT_KMS
;
11114 category
= DRM_UT_NONE
;
11117 va_start(args
, format
);
11121 drm_printk(level
, category
, "mismatch in %s %pV", name
, &vaf
);
11127 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
11128 struct intel_crtc_state
*current_config
,
11129 struct intel_crtc_state
*pipe_config
,
11134 #define PIPE_CONF_CHECK_X(name) \
11135 if (current_config->name != pipe_config->name) { \
11136 pipe_config_err(adjust, __stringify(name), \
11137 "(expected 0x%08x, found 0x%08x)\n", \
11138 current_config->name, \
11139 pipe_config->name); \
11143 #define PIPE_CONF_CHECK_I(name) \
11144 if (current_config->name != pipe_config->name) { \
11145 pipe_config_err(adjust, __stringify(name), \
11146 "(expected %i, found %i)\n", \
11147 current_config->name, \
11148 pipe_config->name); \
11152 #define PIPE_CONF_CHECK_P(name) \
11153 if (current_config->name != pipe_config->name) { \
11154 pipe_config_err(adjust, __stringify(name), \
11155 "(expected %p, found %p)\n", \
11156 current_config->name, \
11157 pipe_config->name); \
11161 #define PIPE_CONF_CHECK_M_N(name) \
11162 if (!intel_compare_link_m_n(¤t_config->name, \
11163 &pipe_config->name,\
11165 pipe_config_err(adjust, __stringify(name), \
11166 "(expected tu %i gmch %i/%i link %i/%i, " \
11167 "found tu %i, gmch %i/%i link %i/%i)\n", \
11168 current_config->name.tu, \
11169 current_config->name.gmch_m, \
11170 current_config->name.gmch_n, \
11171 current_config->name.link_m, \
11172 current_config->name.link_n, \
11173 pipe_config->name.tu, \
11174 pipe_config->name.gmch_m, \
11175 pipe_config->name.gmch_n, \
11176 pipe_config->name.link_m, \
11177 pipe_config->name.link_n); \
11181 /* This is required for BDW+ where there is only one set of registers for
11182 * switching between high and low RR.
11183 * This macro can be used whenever a comparison has to be made between one
11184 * hw state and multiple sw state variables.
11186 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11187 if (!intel_compare_link_m_n(¤t_config->name, \
11188 &pipe_config->name, adjust) && \
11189 !intel_compare_link_m_n(¤t_config->alt_name, \
11190 &pipe_config->name, adjust)) { \
11191 pipe_config_err(adjust, __stringify(name), \
11192 "(expected tu %i gmch %i/%i link %i/%i, " \
11193 "or tu %i gmch %i/%i link %i/%i, " \
11194 "found tu %i, gmch %i/%i link %i/%i)\n", \
11195 current_config->name.tu, \
11196 current_config->name.gmch_m, \
11197 current_config->name.gmch_n, \
11198 current_config->name.link_m, \
11199 current_config->name.link_n, \
11200 current_config->alt_name.tu, \
11201 current_config->alt_name.gmch_m, \
11202 current_config->alt_name.gmch_n, \
11203 current_config->alt_name.link_m, \
11204 current_config->alt_name.link_n, \
11205 pipe_config->name.tu, \
11206 pipe_config->name.gmch_m, \
11207 pipe_config->name.gmch_n, \
11208 pipe_config->name.link_m, \
11209 pipe_config->name.link_n); \
11213 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11214 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11215 pipe_config_err(adjust, __stringify(name), \
11216 "(%x) (expected %i, found %i)\n", \
11218 current_config->name & (mask), \
11219 pipe_config->name & (mask)); \
11223 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11224 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11225 pipe_config_err(adjust, __stringify(name), \
11226 "(expected %i, found %i)\n", \
11227 current_config->name, \
11228 pipe_config->name); \
11232 #define PIPE_CONF_QUIRK(quirk) \
11233 ((current_config->quirks | pipe_config->quirks) & (quirk))
11235 PIPE_CONF_CHECK_I(cpu_transcoder
);
11237 PIPE_CONF_CHECK_I(has_pch_encoder
);
11238 PIPE_CONF_CHECK_I(fdi_lanes
);
11239 PIPE_CONF_CHECK_M_N(fdi_m_n
);
11241 PIPE_CONF_CHECK_I(lane_count
);
11242 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
11244 if (INTEL_GEN(dev_priv
) < 8) {
11245 PIPE_CONF_CHECK_M_N(dp_m_n
);
11247 if (current_config
->has_drrs
)
11248 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
11250 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
11252 PIPE_CONF_CHECK_X(output_types
);
11254 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11255 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11256 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11257 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11258 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11259 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11261 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11262 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11263 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11264 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11265 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11266 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11268 PIPE_CONF_CHECK_I(pixel_multiplier
);
11269 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11270 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
11271 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
11272 PIPE_CONF_CHECK_I(limited_color_range
);
11274 PIPE_CONF_CHECK_I(hdmi_scrambling
);
11275 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio
);
11276 PIPE_CONF_CHECK_I(has_infoframe
);
11277 PIPE_CONF_CHECK_I(ycbcr420
);
11279 PIPE_CONF_CHECK_I(has_audio
);
11281 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11282 DRM_MODE_FLAG_INTERLACE
);
11284 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11285 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11286 DRM_MODE_FLAG_PHSYNC
);
11287 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11288 DRM_MODE_FLAG_NHSYNC
);
11289 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11290 DRM_MODE_FLAG_PVSYNC
);
11291 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11292 DRM_MODE_FLAG_NVSYNC
);
11295 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
11296 /* pfit ratios are autocomputed by the hw on gen4+ */
11297 if (INTEL_GEN(dev_priv
) < 4)
11298 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
11299 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
11302 PIPE_CONF_CHECK_I(pipe_src_w
);
11303 PIPE_CONF_CHECK_I(pipe_src_h
);
11305 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11306 if (current_config
->pch_pfit
.enabled
) {
11307 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
11308 PIPE_CONF_CHECK_X(pch_pfit
.size
);
11311 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
11312 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate
);
11315 /* BDW+ don't expose a synchronous way to read the state */
11316 if (IS_HASWELL(dev_priv
))
11317 PIPE_CONF_CHECK_I(ips_enabled
);
11319 PIPE_CONF_CHECK_I(double_wide
);
11321 PIPE_CONF_CHECK_P(shared_dpll
);
11322 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11323 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11324 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11325 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11326 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11327 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
11328 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11329 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11330 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11332 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
11333 PIPE_CONF_CHECK_X(dsi_pll
.div
);
11335 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
11336 PIPE_CONF_CHECK_I(pipe_bpp
);
11338 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11339 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11341 #undef PIPE_CONF_CHECK_X
11342 #undef PIPE_CONF_CHECK_I
11343 #undef PIPE_CONF_CHECK_P
11344 #undef PIPE_CONF_CHECK_FLAGS
11345 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11346 #undef PIPE_CONF_QUIRK
11351 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
11352 const struct intel_crtc_state
*pipe_config
)
11354 if (pipe_config
->has_pch_encoder
) {
11355 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11356 &pipe_config
->fdi_m_n
);
11357 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
11360 * FDI already provided one idea for the dotclock.
11361 * Yell if the encoder disagrees.
11363 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
11364 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11365 fdi_dotclock
, dotclock
);
11369 static void verify_wm_state(struct drm_crtc
*crtc
,
11370 struct drm_crtc_state
*new_state
)
11372 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
11373 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11374 struct skl_pipe_wm hw_wm
, *sw_wm
;
11375 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
11376 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
11377 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11378 const enum pipe pipe
= intel_crtc
->pipe
;
11379 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
11381 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
11384 skl_pipe_wm_get_hw_state(crtc
, &hw_wm
);
11385 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
11387 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11388 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11391 for_each_universal_plane(dev_priv
, pipe
, plane
) {
11392 hw_plane_wm
= &hw_wm
.planes
[plane
];
11393 sw_plane_wm
= &sw_wm
->planes
[plane
];
11396 for (level
= 0; level
<= max_level
; level
++) {
11397 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
11398 &sw_plane_wm
->wm
[level
]))
11401 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11402 pipe_name(pipe
), plane
+ 1, level
,
11403 sw_plane_wm
->wm
[level
].plane_en
,
11404 sw_plane_wm
->wm
[level
].plane_res_b
,
11405 sw_plane_wm
->wm
[level
].plane_res_l
,
11406 hw_plane_wm
->wm
[level
].plane_en
,
11407 hw_plane_wm
->wm
[level
].plane_res_b
,
11408 hw_plane_wm
->wm
[level
].plane_res_l
);
11411 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
11412 &sw_plane_wm
->trans_wm
)) {
11413 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11414 pipe_name(pipe
), plane
+ 1,
11415 sw_plane_wm
->trans_wm
.plane_en
,
11416 sw_plane_wm
->trans_wm
.plane_res_b
,
11417 sw_plane_wm
->trans_wm
.plane_res_l
,
11418 hw_plane_wm
->trans_wm
.plane_en
,
11419 hw_plane_wm
->trans_wm
.plane_res_b
,
11420 hw_plane_wm
->trans_wm
.plane_res_l
);
11424 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][plane
];
11425 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][plane
];
11427 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
11428 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11429 pipe_name(pipe
), plane
+ 1,
11430 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
11431 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
11437 * If the cursor plane isn't active, we may not have updated it's ddb
11438 * allocation. In that case since the ddb allocation will be updated
11439 * once the plane becomes visible, we can skip this check
11442 hw_plane_wm
= &hw_wm
.planes
[PLANE_CURSOR
];
11443 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
11446 for (level
= 0; level
<= max_level
; level
++) {
11447 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
11448 &sw_plane_wm
->wm
[level
]))
11451 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11452 pipe_name(pipe
), level
,
11453 sw_plane_wm
->wm
[level
].plane_en
,
11454 sw_plane_wm
->wm
[level
].plane_res_b
,
11455 sw_plane_wm
->wm
[level
].plane_res_l
,
11456 hw_plane_wm
->wm
[level
].plane_en
,
11457 hw_plane_wm
->wm
[level
].plane_res_b
,
11458 hw_plane_wm
->wm
[level
].plane_res_l
);
11461 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
11462 &sw_plane_wm
->trans_wm
)) {
11463 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11465 sw_plane_wm
->trans_wm
.plane_en
,
11466 sw_plane_wm
->trans_wm
.plane_res_b
,
11467 sw_plane_wm
->trans_wm
.plane_res_l
,
11468 hw_plane_wm
->trans_wm
.plane_en
,
11469 hw_plane_wm
->trans_wm
.plane_res_b
,
11470 hw_plane_wm
->trans_wm
.plane_res_l
);
11474 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
11475 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
11477 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
11478 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11480 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
11481 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
11487 verify_connector_state(struct drm_device
*dev
,
11488 struct drm_atomic_state
*state
,
11489 struct drm_crtc
*crtc
)
11491 struct drm_connector
*connector
;
11492 struct drm_connector_state
*new_conn_state
;
11495 for_each_new_connector_in_state(state
, connector
, new_conn_state
, i
) {
11496 struct drm_encoder
*encoder
= connector
->encoder
;
11497 struct drm_crtc_state
*crtc_state
= NULL
;
11499 if (new_conn_state
->crtc
!= crtc
)
11503 crtc_state
= drm_atomic_get_new_crtc_state(state
, new_conn_state
->crtc
);
11505 intel_connector_verify_state(crtc_state
, new_conn_state
);
11507 I915_STATE_WARN(new_conn_state
->best_encoder
!= encoder
,
11508 "connector's atomic encoder doesn't match legacy encoder\n");
11513 verify_encoder_state(struct drm_device
*dev
, struct drm_atomic_state
*state
)
11515 struct intel_encoder
*encoder
;
11516 struct drm_connector
*connector
;
11517 struct drm_connector_state
*old_conn_state
, *new_conn_state
;
11520 for_each_intel_encoder(dev
, encoder
) {
11521 bool enabled
= false, found
= false;
11524 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11525 encoder
->base
.base
.id
,
11526 encoder
->base
.name
);
11528 for_each_oldnew_connector_in_state(state
, connector
, old_conn_state
,
11529 new_conn_state
, i
) {
11530 if (old_conn_state
->best_encoder
== &encoder
->base
)
11533 if (new_conn_state
->best_encoder
!= &encoder
->base
)
11535 found
= enabled
= true;
11537 I915_STATE_WARN(new_conn_state
->crtc
!=
11538 encoder
->base
.crtc
,
11539 "connector's crtc doesn't match encoder crtc\n");
11545 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
11546 "encoder's enabled state mismatch "
11547 "(expected %i, found %i)\n",
11548 !!encoder
->base
.crtc
, enabled
);
11550 if (!encoder
->base
.crtc
) {
11553 active
= encoder
->get_hw_state(encoder
, &pipe
);
11554 I915_STATE_WARN(active
,
11555 "encoder detached but still enabled on pipe %c.\n",
11562 verify_crtc_state(struct drm_crtc
*crtc
,
11563 struct drm_crtc_state
*old_crtc_state
,
11564 struct drm_crtc_state
*new_crtc_state
)
11566 struct drm_device
*dev
= crtc
->dev
;
11567 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11568 struct intel_encoder
*encoder
;
11569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11570 struct intel_crtc_state
*pipe_config
, *sw_config
;
11571 struct drm_atomic_state
*old_state
;
11574 old_state
= old_crtc_state
->state
;
11575 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
11576 pipe_config
= to_intel_crtc_state(old_crtc_state
);
11577 memset(pipe_config
, 0, sizeof(*pipe_config
));
11578 pipe_config
->base
.crtc
= crtc
;
11579 pipe_config
->base
.state
= old_state
;
11581 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
11583 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
11585 /* we keep both pipes enabled on 830 */
11586 if (IS_I830(dev_priv
))
11587 active
= new_crtc_state
->active
;
11589 I915_STATE_WARN(new_crtc_state
->active
!= active
,
11590 "crtc active state doesn't match with hw state "
11591 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
11593 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
11594 "transitional active state does not match atomic hw state "
11595 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
11597 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
11600 active
= encoder
->get_hw_state(encoder
, &pipe
);
11601 I915_STATE_WARN(active
!= new_crtc_state
->active
,
11602 "[ENCODER:%i] active %i with crtc active %i\n",
11603 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
11605 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
11606 "Encoder connected to wrong pipe %c\n",
11610 pipe_config
->output_types
|= 1 << encoder
->type
;
11611 encoder
->get_config(encoder
, pipe_config
);
11615 intel_crtc_compute_pixel_rate(pipe_config
);
11617 if (!new_crtc_state
->active
)
11620 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
11622 sw_config
= to_intel_crtc_state(new_crtc_state
);
11623 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
11624 pipe_config
, false)) {
11625 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11626 intel_dump_pipe_config(intel_crtc
, pipe_config
,
11628 intel_dump_pipe_config(intel_crtc
, sw_config
,
11634 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
11635 struct intel_shared_dpll
*pll
,
11636 struct drm_crtc
*crtc
,
11637 struct drm_crtc_state
*new_state
)
11639 struct intel_dpll_hw_state dpll_hw_state
;
11640 unsigned crtc_mask
;
11643 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
11645 DRM_DEBUG_KMS("%s\n", pll
->name
);
11647 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11649 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
11650 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
11651 "pll in active use but not on in sw tracking\n");
11652 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
11653 "pll is on but not used by any active crtc\n");
11654 I915_STATE_WARN(pll
->on
!= active
,
11655 "pll on state mismatch (expected %i, found %i)\n",
11660 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
11661 "more active pll users than references: %x vs %x\n",
11662 pll
->active_mask
, pll
->state
.crtc_mask
);
11667 crtc_mask
= 1 << drm_crtc_index(crtc
);
11669 if (new_state
->active
)
11670 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
11671 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11672 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
11674 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
11675 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11676 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
11678 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
11679 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11680 crtc_mask
, pll
->state
.crtc_mask
);
11682 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
11684 sizeof(dpll_hw_state
)),
11685 "pll hw state mismatch\n");
11689 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
11690 struct drm_crtc_state
*old_crtc_state
,
11691 struct drm_crtc_state
*new_crtc_state
)
11693 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11694 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
11695 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
11697 if (new_state
->shared_dpll
)
11698 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
11700 if (old_state
->shared_dpll
&&
11701 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
11702 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
11703 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
11705 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
11706 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11707 pipe_name(drm_crtc_index(crtc
)));
11708 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
11709 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11710 pipe_name(drm_crtc_index(crtc
)));
11715 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
11716 struct drm_atomic_state
*state
,
11717 struct drm_crtc_state
*old_state
,
11718 struct drm_crtc_state
*new_state
)
11720 if (!needs_modeset(new_state
) &&
11721 !to_intel_crtc_state(new_state
)->update_pipe
)
11724 verify_wm_state(crtc
, new_state
);
11725 verify_connector_state(crtc
->dev
, state
, crtc
);
11726 verify_crtc_state(crtc
, old_state
, new_state
);
11727 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
11731 verify_disabled_dpll_state(struct drm_device
*dev
)
11733 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11736 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
11737 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
11741 intel_modeset_verify_disabled(struct drm_device
*dev
,
11742 struct drm_atomic_state
*state
)
11744 verify_encoder_state(dev
, state
);
11745 verify_connector_state(dev
, state
, NULL
);
11746 verify_disabled_dpll_state(dev
);
11749 static void update_scanline_offset(struct intel_crtc
*crtc
)
11751 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11754 * The scanline counter increments at the leading edge of hsync.
11756 * On most platforms it starts counting from vtotal-1 on the
11757 * first active line. That means the scanline counter value is
11758 * always one less than what we would expect. Ie. just after
11759 * start of vblank, which also occurs at start of hsync (on the
11760 * last active line), the scanline counter will read vblank_start-1.
11762 * On gen2 the scanline counter starts counting from 1 instead
11763 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11764 * to keep the value positive), instead of adding one.
11766 * On HSW+ the behaviour of the scanline counter depends on the output
11767 * type. For DP ports it behaves like most other platforms, but on HDMI
11768 * there's an extra 1 line difference. So we need to add two instead of
11769 * one to the value.
11771 * On VLV/CHV DSI the scanline counter would appear to increment
11772 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11773 * that means we can't tell whether we're in vblank or not while
11774 * we're on that particular line. We must still set scanline_offset
11775 * to 1 so that the vblank timestamps come out correct when we query
11776 * the scanline counter from within the vblank interrupt handler.
11777 * However if queried just before the start of vblank we'll get an
11778 * answer that's slightly in the future.
11780 if (IS_GEN2(dev_priv
)) {
11781 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
11784 vtotal
= adjusted_mode
->crtc_vtotal
;
11785 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11788 crtc
->scanline_offset
= vtotal
- 1;
11789 } else if (HAS_DDI(dev_priv
) &&
11790 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
)) {
11791 crtc
->scanline_offset
= 2;
11793 crtc
->scanline_offset
= 1;
11796 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
11798 struct drm_device
*dev
= state
->dev
;
11799 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11800 struct drm_crtc
*crtc
;
11801 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
11804 if (!dev_priv
->display
.crtc_compute_clock
)
11807 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
11808 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11809 struct intel_shared_dpll
*old_dpll
=
11810 to_intel_crtc_state(old_crtc_state
)->shared_dpll
;
11812 if (!needs_modeset(new_crtc_state
))
11815 to_intel_crtc_state(new_crtc_state
)->shared_dpll
= NULL
;
11820 intel_release_shared_dpll(old_dpll
, intel_crtc
, state
);
11825 * This implements the workaround described in the "notes" section of the mode
11826 * set sequence documentation. When going from no pipes or single pipe to
11827 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11828 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11830 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
11832 struct drm_crtc_state
*crtc_state
;
11833 struct intel_crtc
*intel_crtc
;
11834 struct drm_crtc
*crtc
;
11835 struct intel_crtc_state
*first_crtc_state
= NULL
;
11836 struct intel_crtc_state
*other_crtc_state
= NULL
;
11837 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
11840 /* look at all crtc's that are going to be enabled in during modeset */
11841 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
11842 intel_crtc
= to_intel_crtc(crtc
);
11844 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
11847 if (first_crtc_state
) {
11848 other_crtc_state
= to_intel_crtc_state(crtc_state
);
11851 first_crtc_state
= to_intel_crtc_state(crtc_state
);
11852 first_pipe
= intel_crtc
->pipe
;
11856 /* No workaround needed? */
11857 if (!first_crtc_state
)
11860 /* w/a possibly needed, check how many crtc's are already enabled. */
11861 for_each_intel_crtc(state
->dev
, intel_crtc
) {
11862 struct intel_crtc_state
*pipe_config
;
11864 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
11865 if (IS_ERR(pipe_config
))
11866 return PTR_ERR(pipe_config
);
11868 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
11870 if (!pipe_config
->base
.active
||
11871 needs_modeset(&pipe_config
->base
))
11874 /* 2 or more enabled crtcs means no need for w/a */
11875 if (enabled_pipe
!= INVALID_PIPE
)
11878 enabled_pipe
= intel_crtc
->pipe
;
11881 if (enabled_pipe
!= INVALID_PIPE
)
11882 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
11883 else if (other_crtc_state
)
11884 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
11889 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
11891 struct drm_crtc
*crtc
;
11893 /* Add all pipes to the state */
11894 for_each_crtc(state
->dev
, crtc
) {
11895 struct drm_crtc_state
*crtc_state
;
11897 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
11898 if (IS_ERR(crtc_state
))
11899 return PTR_ERR(crtc_state
);
11905 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
11907 struct drm_crtc
*crtc
;
11910 * Add all pipes to the state, and force
11911 * a modeset on all the active ones.
11913 for_each_crtc(state
->dev
, crtc
) {
11914 struct drm_crtc_state
*crtc_state
;
11917 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
11918 if (IS_ERR(crtc_state
))
11919 return PTR_ERR(crtc_state
);
11921 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
11924 crtc_state
->mode_changed
= true;
11926 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
11930 ret
= drm_atomic_add_affected_planes(state
, crtc
);
11938 static int intel_modeset_checks(struct drm_atomic_state
*state
)
11940 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
11941 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
11942 struct drm_crtc
*crtc
;
11943 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
11946 if (!check_digital_port_conflicts(state
)) {
11947 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11951 intel_state
->modeset
= true;
11952 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
11953 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
11954 intel_state
->cdclk
.actual
= dev_priv
->cdclk
.actual
;
11956 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
11957 if (new_crtc_state
->active
)
11958 intel_state
->active_crtcs
|= 1 << i
;
11960 intel_state
->active_crtcs
&= ~(1 << i
);
11962 if (old_crtc_state
->active
!= new_crtc_state
->active
)
11963 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
11967 * See if the config requires any additional preparation, e.g.
11968 * to adjust global state with pipes off. We need to do this
11969 * here so we can get the modeset_pipe updated config for the new
11970 * mode set on this crtc. For other crtcs we need to use the
11971 * adjusted_mode bits in the crtc directly.
11973 if (dev_priv
->display
.modeset_calc_cdclk
) {
11974 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
11979 * Writes to dev_priv->cdclk.logical must protected by
11980 * holding all the crtc locks, even if we don't end up
11981 * touching the hardware
11983 if (!intel_cdclk_state_compare(&dev_priv
->cdclk
.logical
,
11984 &intel_state
->cdclk
.logical
)) {
11985 ret
= intel_lock_all_pipes(state
);
11990 /* All pipes must be switched off while we change the cdclk. */
11991 if (!intel_cdclk_state_compare(&dev_priv
->cdclk
.actual
,
11992 &intel_state
->cdclk
.actual
)) {
11993 ret
= intel_modeset_all_pipes(state
);
11998 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11999 intel_state
->cdclk
.logical
.cdclk
,
12000 intel_state
->cdclk
.actual
.cdclk
);
12002 to_intel_atomic_state(state
)->cdclk
.logical
= dev_priv
->cdclk
.logical
;
12005 intel_modeset_clear_plls(state
);
12007 if (IS_HASWELL(dev_priv
))
12008 return haswell_mode_set_planes_workaround(state
);
12014 * Handle calculation of various watermark data at the end of the atomic check
12015 * phase. The code here should be run after the per-crtc and per-plane 'check'
12016 * handlers to ensure that all derived state has been updated.
12018 static int calc_watermark_data(struct drm_atomic_state
*state
)
12020 struct drm_device
*dev
= state
->dev
;
12021 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12023 /* Is there platform-specific watermark information to calculate? */
12024 if (dev_priv
->display
.compute_global_watermarks
)
12025 return dev_priv
->display
.compute_global_watermarks(state
);
12031 * intel_atomic_check - validate state object
12033 * @state: state to validate
12035 static int intel_atomic_check(struct drm_device
*dev
,
12036 struct drm_atomic_state
*state
)
12038 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12039 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12040 struct drm_crtc
*crtc
;
12041 struct drm_crtc_state
*old_crtc_state
, *crtc_state
;
12043 bool any_ms
= false;
12045 ret
= drm_atomic_helper_check_modeset(dev
, state
);
12049 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, crtc_state
, i
) {
12050 struct intel_crtc_state
*pipe_config
=
12051 to_intel_crtc_state(crtc_state
);
12053 /* Catch I915_MODE_FLAG_INHERITED */
12054 if (crtc_state
->mode
.private_flags
!= old_crtc_state
->mode
.private_flags
)
12055 crtc_state
->mode_changed
= true;
12057 if (!needs_modeset(crtc_state
))
12060 if (!crtc_state
->enable
) {
12065 /* FIXME: For only active_changed we shouldn't need to do any
12066 * state recomputation at all. */
12068 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12072 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
12074 intel_dump_pipe_config(to_intel_crtc(crtc
),
12075 pipe_config
, "[failed]");
12079 if (i915
.fastboot
&&
12080 intel_pipe_config_compare(dev_priv
,
12081 to_intel_crtc_state(old_crtc_state
),
12082 pipe_config
, true)) {
12083 crtc_state
->mode_changed
= false;
12084 pipe_config
->update_pipe
= true;
12087 if (needs_modeset(crtc_state
))
12090 ret
= drm_atomic_add_affected_planes(state
, crtc
);
12094 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
12095 needs_modeset(crtc_state
) ?
12096 "[modeset]" : "[fastset]");
12100 ret
= intel_modeset_checks(state
);
12105 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
12108 ret
= drm_atomic_helper_check_planes(dev
, state
);
12112 intel_fbc_choose_crtc(dev_priv
, state
);
12113 return calc_watermark_data(state
);
12116 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
12117 struct drm_atomic_state
*state
)
12119 return drm_atomic_helper_prepare_planes(dev
, state
);
12122 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
12124 struct drm_device
*dev
= crtc
->base
.dev
;
12126 if (!dev
->max_vblank_count
)
12127 return drm_crtc_accurate_vblank_count(&crtc
->base
);
12129 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
12132 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
12133 struct drm_i915_private
*dev_priv
,
12134 unsigned crtc_mask
)
12136 unsigned last_vblank_count
[I915_MAX_PIPES
];
12143 for_each_pipe(dev_priv
, pipe
) {
12144 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
,
12147 if (!((1 << pipe
) & crtc_mask
))
12150 ret
= drm_crtc_vblank_get(&crtc
->base
);
12151 if (WARN_ON(ret
!= 0)) {
12152 crtc_mask
&= ~(1 << pipe
);
12156 last_vblank_count
[pipe
] = drm_crtc_vblank_count(&crtc
->base
);
12159 for_each_pipe(dev_priv
, pipe
) {
12160 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
,
12164 if (!((1 << pipe
) & crtc_mask
))
12167 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
12168 last_vblank_count
[pipe
] !=
12169 drm_crtc_vblank_count(&crtc
->base
),
12170 msecs_to_jiffies(50));
12172 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
12174 drm_crtc_vblank_put(&crtc
->base
);
12178 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
12180 /* fb updated, need to unpin old fb */
12181 if (crtc_state
->fb_changed
)
12184 /* wm changes, need vblank before final wm's */
12185 if (crtc_state
->update_wm_post
)
12188 if (crtc_state
->wm
.need_postvbl_update
)
12194 static void intel_update_crtc(struct drm_crtc
*crtc
,
12195 struct drm_atomic_state
*state
,
12196 struct drm_crtc_state
*old_crtc_state
,
12197 struct drm_crtc_state
*new_crtc_state
,
12198 unsigned int *crtc_vblank_mask
)
12200 struct drm_device
*dev
= crtc
->dev
;
12201 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12203 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(new_crtc_state
);
12204 bool modeset
= needs_modeset(new_crtc_state
);
12207 update_scanline_offset(intel_crtc
);
12208 dev_priv
->display
.crtc_enable(pipe_config
, state
);
12210 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
12214 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12216 intel_crtc
, pipe_config
,
12217 to_intel_plane_state(crtc
->primary
->state
));
12220 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
12222 if (needs_vblank_wait(pipe_config
))
12223 *crtc_vblank_mask
|= drm_crtc_mask(crtc
);
12226 static void intel_update_crtcs(struct drm_atomic_state
*state
,
12227 unsigned int *crtc_vblank_mask
)
12229 struct drm_crtc
*crtc
;
12230 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12233 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12234 if (!new_crtc_state
->active
)
12237 intel_update_crtc(crtc
, state
, old_crtc_state
,
12238 new_crtc_state
, crtc_vblank_mask
);
12242 static void skl_update_crtcs(struct drm_atomic_state
*state
,
12243 unsigned int *crtc_vblank_mask
)
12245 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
12246 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12247 struct drm_crtc
*crtc
;
12248 struct intel_crtc
*intel_crtc
;
12249 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12250 struct intel_crtc_state
*cstate
;
12251 unsigned int updated
= 0;
12256 const struct skl_ddb_entry
*entries
[I915_MAX_PIPES
] = {};
12258 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
)
12259 /* ignore allocations for crtc's that have been turned off. */
12260 if (new_crtc_state
->active
)
12261 entries
[i
] = &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
12264 * Whenever the number of active pipes changes, we need to make sure we
12265 * update the pipes in the right order so that their ddb allocations
12266 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12267 * cause pipe underruns and other bad stuff.
12272 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12273 bool vbl_wait
= false;
12274 unsigned int cmask
= drm_crtc_mask(crtc
);
12276 intel_crtc
= to_intel_crtc(crtc
);
12277 cstate
= to_intel_crtc_state(crtc
->state
);
12278 pipe
= intel_crtc
->pipe
;
12280 if (updated
& cmask
|| !cstate
->base
.active
)
12283 if (skl_ddb_allocation_overlaps(entries
, &cstate
->wm
.skl
.ddb
, i
))
12287 entries
[i
] = &cstate
->wm
.skl
.ddb
;
12290 * If this is an already active pipe, it's DDB changed,
12291 * and this isn't the last pipe that needs updating
12292 * then we need to wait for a vblank to pass for the
12293 * new ddb allocation to take effect.
12295 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
12296 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
12297 !new_crtc_state
->active_changed
&&
12298 intel_state
->wm_results
.dirty_pipes
!= updated
)
12301 intel_update_crtc(crtc
, state
, old_crtc_state
,
12302 new_crtc_state
, crtc_vblank_mask
);
12305 intel_wait_for_vblank(dev_priv
, pipe
);
12309 } while (progress
);
12312 static void intel_atomic_helper_free_state(struct drm_i915_private
*dev_priv
)
12314 struct intel_atomic_state
*state
, *next
;
12315 struct llist_node
*freed
;
12317 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
12318 llist_for_each_entry_safe(state
, next
, freed
, freed
)
12319 drm_atomic_state_put(&state
->base
);
12322 static void intel_atomic_helper_free_state_worker(struct work_struct
*work
)
12324 struct drm_i915_private
*dev_priv
=
12325 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
12327 intel_atomic_helper_free_state(dev_priv
);
12330 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
12332 struct wait_queue_entry wait_fence
, wait_reset
;
12333 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
12335 init_wait_entry(&wait_fence
, 0);
12336 init_wait_entry(&wait_reset
, 0);
12338 prepare_to_wait(&intel_state
->commit_ready
.wait
,
12339 &wait_fence
, TASK_UNINTERRUPTIBLE
);
12340 prepare_to_wait(&dev_priv
->gpu_error
.wait_queue
,
12341 &wait_reset
, TASK_UNINTERRUPTIBLE
);
12344 if (i915_sw_fence_done(&intel_state
->commit_ready
)
12345 || test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
12350 finish_wait(&intel_state
->commit_ready
.wait
, &wait_fence
);
12351 finish_wait(&dev_priv
->gpu_error
.wait_queue
, &wait_reset
);
12354 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
12356 struct drm_device
*dev
= state
->dev
;
12357 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12359 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12360 struct drm_crtc
*crtc
;
12361 struct intel_crtc_state
*intel_cstate
;
12362 bool hw_check
= intel_state
->modeset
;
12363 u64 put_domains
[I915_MAX_PIPES
] = {};
12364 unsigned crtc_vblank_mask
= 0;
12367 intel_atomic_commit_fence_wait(intel_state
);
12369 drm_atomic_helper_wait_for_dependencies(state
);
12371 if (intel_state
->modeset
)
12372 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
12374 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12377 if (needs_modeset(new_crtc_state
) ||
12378 to_intel_crtc_state(new_crtc_state
)->update_pipe
) {
12381 put_domains
[to_intel_crtc(crtc
)->pipe
] =
12382 modeset_get_crtc_power_domains(crtc
,
12383 to_intel_crtc_state(new_crtc_state
));
12386 if (!needs_modeset(new_crtc_state
))
12389 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
12390 to_intel_crtc_state(new_crtc_state
));
12392 if (old_crtc_state
->active
) {
12393 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
12394 dev_priv
->display
.crtc_disable(to_intel_crtc_state(old_crtc_state
), state
);
12395 intel_crtc
->active
= false;
12396 intel_fbc_disable(intel_crtc
);
12397 intel_disable_shared_dpll(intel_crtc
);
12400 * Underruns don't always raise
12401 * interrupts, so check manually.
12403 intel_check_cpu_fifo_underruns(dev_priv
);
12404 intel_check_pch_fifo_underruns(dev_priv
);
12406 if (!crtc
->state
->active
) {
12408 * Make sure we don't call initial_watermarks
12409 * for ILK-style watermark updates.
12411 * No clue what this is supposed to achieve.
12413 if (INTEL_GEN(dev_priv
) >= 9)
12414 dev_priv
->display
.initial_watermarks(intel_state
,
12415 to_intel_crtc_state(crtc
->state
));
12420 /* Only after disabling all output pipelines that will be changed can we
12421 * update the the output configuration. */
12422 intel_modeset_update_crtc_state(state
);
12424 if (intel_state
->modeset
) {
12425 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
12427 intel_set_cdclk(dev_priv
, &dev_priv
->cdclk
.actual
);
12430 * SKL workaround: bspec recommends we disable the SAGV when we
12431 * have more then one pipe enabled
12433 if (!intel_can_enable_sagv(state
))
12434 intel_disable_sagv(dev_priv
);
12436 intel_modeset_verify_disabled(dev
, state
);
12439 /* Complete the events for pipes that have now been disabled */
12440 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
12441 bool modeset
= needs_modeset(new_crtc_state
);
12443 /* Complete events for now disable pipes here. */
12444 if (modeset
&& !new_crtc_state
->active
&& new_crtc_state
->event
) {
12445 spin_lock_irq(&dev
->event_lock
);
12446 drm_crtc_send_vblank_event(crtc
, new_crtc_state
->event
);
12447 spin_unlock_irq(&dev
->event_lock
);
12449 new_crtc_state
->event
= NULL
;
12453 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12454 dev_priv
->display
.update_crtcs(state
, &crtc_vblank_mask
);
12456 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12457 * already, but still need the state for the delayed optimization. To
12459 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12460 * - schedule that vblank worker _before_ calling hw_done
12461 * - at the start of commit_tail, cancel it _synchrously
12462 * - switch over to the vblank wait helper in the core after that since
12463 * we don't need out special handling any more.
12465 if (!state
->legacy_cursor_update
)
12466 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
12469 * Now that the vblank has passed, we can go ahead and program the
12470 * optimal watermarks on platforms that need two-step watermark
12473 * TODO: Move this (and other cleanup) to an async worker eventually.
12475 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
12476 intel_cstate
= to_intel_crtc_state(new_crtc_state
);
12478 if (dev_priv
->display
.optimize_watermarks
)
12479 dev_priv
->display
.optimize_watermarks(intel_state
,
12483 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12484 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
12486 if (put_domains
[i
])
12487 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
12489 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, new_crtc_state
);
12492 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
12493 intel_enable_sagv(dev_priv
);
12495 drm_atomic_helper_commit_hw_done(state
);
12497 if (intel_state
->modeset
) {
12498 /* As one of the primary mmio accessors, KMS has a high
12499 * likelihood of triggering bugs in unclaimed access. After we
12500 * finish modesetting, see if an error has been flagged, and if
12501 * so enable debugging for the next modeset - and hope we catch
12504 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
12505 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
12508 drm_atomic_helper_cleanup_planes(dev
, state
);
12510 drm_atomic_helper_commit_cleanup_done(state
);
12512 drm_atomic_state_put(state
);
12514 intel_atomic_helper_free_state(dev_priv
);
12517 static void intel_atomic_commit_work(struct work_struct
*work
)
12519 struct drm_atomic_state
*state
=
12520 container_of(work
, struct drm_atomic_state
, commit_work
);
12522 intel_atomic_commit_tail(state
);
12525 static int __i915_sw_fence_call
12526 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
12527 enum i915_sw_fence_notify notify
)
12529 struct intel_atomic_state
*state
=
12530 container_of(fence
, struct intel_atomic_state
, commit_ready
);
12533 case FENCE_COMPLETE
:
12534 /* we do blocking waits in the worker, nothing to do here */
12538 struct intel_atomic_helper
*helper
=
12539 &to_i915(state
->base
.dev
)->atomic_helper
;
12541 if (llist_add(&state
->freed
, &helper
->free_list
))
12542 schedule_work(&helper
->free_work
);
12547 return NOTIFY_DONE
;
12550 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
12552 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
12553 struct drm_plane
*plane
;
12556 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
)
12557 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
12558 intel_fb_obj(new_plane_state
->fb
),
12559 to_intel_plane(plane
)->frontbuffer_bit
);
12563 * intel_atomic_commit - commit validated state object
12565 * @state: the top-level driver state object
12566 * @nonblock: nonblocking commit
12568 * This function commits a top-level state object that has been validated
12569 * with drm_atomic_helper_check().
12572 * Zero for success or -errno.
12574 static int intel_atomic_commit(struct drm_device
*dev
,
12575 struct drm_atomic_state
*state
,
12578 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12579 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12582 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
12586 drm_atomic_state_get(state
);
12587 i915_sw_fence_init(&intel_state
->commit_ready
,
12588 intel_atomic_commit_ready
);
12590 ret
= intel_atomic_prepare_commit(dev
, state
);
12592 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
12593 i915_sw_fence_commit(&intel_state
->commit_ready
);
12598 * The intel_legacy_cursor_update() fast path takes care
12599 * of avoiding the vblank waits for simple cursor
12600 * movement and flips. For cursor on/off and size changes,
12601 * we want to perform the vblank waits so that watermark
12602 * updates happen during the correct frames. Gen9+ have
12603 * double buffered watermarks and so shouldn't need this.
12605 * Do this after drm_atomic_helper_setup_commit() and
12606 * intel_atomic_prepare_commit() because we still want
12607 * to skip the flip and fb cleanup waits. Although that
12608 * does risk yanking the mapping from under the display
12611 * FIXME doing watermarks and fb cleanup from a vblank worker
12612 * (assuming we had any) would solve these problems.
12614 if (INTEL_GEN(dev_priv
) < 9)
12615 state
->legacy_cursor_update
= false;
12617 ret
= drm_atomic_helper_swap_state(state
, true);
12619 i915_sw_fence_commit(&intel_state
->commit_ready
);
12621 drm_atomic_helper_cleanup_planes(dev
, state
);
12624 dev_priv
->wm
.distrust_bios_wm
= false;
12625 intel_shared_dpll_swap_state(state
);
12626 intel_atomic_track_fbs(state
);
12628 if (intel_state
->modeset
) {
12629 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
12630 sizeof(intel_state
->min_pixclk
));
12631 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
12632 dev_priv
->cdclk
.logical
= intel_state
->cdclk
.logical
;
12633 dev_priv
->cdclk
.actual
= intel_state
->cdclk
.actual
;
12636 drm_atomic_state_get(state
);
12637 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
12639 i915_sw_fence_commit(&intel_state
->commit_ready
);
12641 queue_work(system_unbound_wq
, &state
->commit_work
);
12643 intel_atomic_commit_tail(state
);
12649 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12650 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
12651 .set_config
= drm_atomic_helper_set_config
,
12652 .destroy
= intel_crtc_destroy
,
12653 .page_flip
= drm_atomic_helper_page_flip
,
12654 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12655 .atomic_destroy_state
= intel_crtc_destroy_state
,
12656 .set_crc_source
= intel_crtc_set_crc_source
,
12660 * intel_prepare_plane_fb - Prepare fb for usage on plane
12661 * @plane: drm plane to prepare for
12662 * @fb: framebuffer to prepare for presentation
12664 * Prepares a framebuffer for usage on a display plane. Generally this
12665 * involves pinning the underlying object and updating the frontbuffer tracking
12666 * bits. Some older platforms need special physical address handling for
12669 * Must be called with struct_mutex held.
12671 * Returns 0 on success, negative error code on failure.
12674 intel_prepare_plane_fb(struct drm_plane
*plane
,
12675 struct drm_plane_state
*new_state
)
12677 struct intel_atomic_state
*intel_state
=
12678 to_intel_atomic_state(new_state
->state
);
12679 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
12680 struct drm_framebuffer
*fb
= new_state
->fb
;
12681 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12682 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
12686 struct drm_crtc_state
*crtc_state
=
12687 drm_atomic_get_existing_crtc_state(new_state
->state
,
12688 plane
->state
->crtc
);
12690 /* Big Hammer, we also need to ensure that any pending
12691 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12692 * current scanout is retired before unpinning the old
12693 * framebuffer. Note that we rely on userspace rendering
12694 * into the buffer attached to the pipe they are waiting
12695 * on. If not, userspace generates a GPU hang with IPEHR
12696 * point to the MI_WAIT_FOR_EVENT.
12698 * This should only fail upon a hung GPU, in which case we
12699 * can safely continue.
12701 if (needs_modeset(crtc_state
)) {
12702 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
12703 old_obj
->resv
, NULL
,
12711 if (new_state
->fence
) { /* explicit fencing */
12712 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
12714 I915_FENCE_TIMEOUT
,
12723 ret
= i915_gem_object_pin_pages(obj
);
12727 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
12729 i915_gem_object_unpin_pages(obj
);
12733 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
12734 INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
12735 const int align
= intel_cursor_alignment(dev_priv
);
12737 ret
= i915_gem_object_attach_phys(obj
, align
);
12739 struct i915_vma
*vma
;
12741 vma
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
12743 to_intel_plane_state(new_state
)->vma
= vma
;
12745 ret
= PTR_ERR(vma
);
12748 i915_gem_object_wait_priority(obj
, 0, I915_PRIORITY_DISPLAY
);
12750 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
12751 i915_gem_object_unpin_pages(obj
);
12755 if (!new_state
->fence
) { /* implicit fencing */
12756 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
12758 false, I915_FENCE_TIMEOUT
,
12768 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12769 * @plane: drm plane to clean up for
12770 * @fb: old framebuffer that was on plane
12772 * Cleans up a framebuffer that has just been removed from a plane.
12774 * Must be called with struct_mutex held.
12777 intel_cleanup_plane_fb(struct drm_plane
*plane
,
12778 struct drm_plane_state
*old_state
)
12780 struct i915_vma
*vma
;
12782 /* Should only be called after a successful intel_prepare_plane_fb()! */
12783 vma
= fetch_and_zero(&to_intel_plane_state(old_state
)->vma
);
12785 mutex_lock(&plane
->dev
->struct_mutex
);
12786 intel_unpin_fb_vma(vma
);
12787 mutex_unlock(&plane
->dev
->struct_mutex
);
12792 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
12794 struct drm_i915_private
*dev_priv
;
12796 int crtc_clock
, max_dotclk
;
12798 if (!intel_crtc
|| !crtc_state
->base
.enable
)
12799 return DRM_PLANE_HELPER_NO_SCALING
;
12801 dev_priv
= to_i915(intel_crtc
->base
.dev
);
12803 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
12804 max_dotclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
.logical
.cdclk
;
12806 if (IS_GEMINILAKE(dev_priv
))
12809 if (WARN_ON_ONCE(!crtc_clock
|| max_dotclk
< crtc_clock
))
12810 return DRM_PLANE_HELPER_NO_SCALING
;
12813 * skl max scale is lower of:
12814 * close to 3 but not 3, -1 is for that purpose
12818 max_scale
= min((1 << 16) * 3 - 1,
12819 (1 << 8) * ((max_dotclk
<< 8) / crtc_clock
));
12825 intel_check_primary_plane(struct intel_plane
*plane
,
12826 struct intel_crtc_state
*crtc_state
,
12827 struct intel_plane_state
*state
)
12829 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
12830 struct drm_crtc
*crtc
= state
->base
.crtc
;
12831 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
12832 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
12833 bool can_position
= false;
12836 if (INTEL_GEN(dev_priv
) >= 9) {
12837 /* use scaler when colorkey is not required */
12838 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
12840 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
12842 can_position
= true;
12845 ret
= drm_plane_helper_check_state(&state
->base
,
12847 min_scale
, max_scale
,
12848 can_position
, true);
12852 if (!state
->base
.fb
)
12855 if (INTEL_GEN(dev_priv
) >= 9) {
12856 ret
= skl_check_plane_surface(state
);
12860 state
->ctl
= skl_plane_ctl(crtc_state
, state
);
12862 ret
= i9xx_check_plane_surface(state
);
12866 state
->ctl
= i9xx_plane_ctl(crtc_state
, state
);
12872 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
12873 struct drm_crtc_state
*old_crtc_state
)
12875 struct drm_device
*dev
= crtc
->dev
;
12876 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12877 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12878 struct intel_crtc_state
*intel_cstate
=
12879 to_intel_crtc_state(crtc
->state
);
12880 struct intel_crtc_state
*old_intel_cstate
=
12881 to_intel_crtc_state(old_crtc_state
);
12882 struct intel_atomic_state
*old_intel_state
=
12883 to_intel_atomic_state(old_crtc_state
->state
);
12884 bool modeset
= needs_modeset(crtc
->state
);
12887 (intel_cstate
->base
.color_mgmt_changed
||
12888 intel_cstate
->update_pipe
)) {
12889 intel_color_set_csc(crtc
->state
);
12890 intel_color_load_luts(crtc
->state
);
12893 /* Perform vblank evasion around commit operation */
12894 intel_pipe_update_start(intel_crtc
);
12899 if (intel_cstate
->update_pipe
)
12900 intel_update_pipe_config(intel_crtc
, old_intel_cstate
);
12901 else if (INTEL_GEN(dev_priv
) >= 9)
12902 skl_detach_scalers(intel_crtc
);
12905 if (dev_priv
->display
.atomic_update_watermarks
)
12906 dev_priv
->display
.atomic_update_watermarks(old_intel_state
,
12910 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
12911 struct drm_crtc_state
*old_crtc_state
)
12913 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12915 intel_pipe_update_end(intel_crtc
);
12919 * intel_plane_destroy - destroy a plane
12920 * @plane: plane to destroy
12922 * Common destruction function for all types of planes (primary, cursor,
12925 void intel_plane_destroy(struct drm_plane
*plane
)
12927 drm_plane_cleanup(plane
);
12928 kfree(to_intel_plane(plane
));
12931 static bool i8xx_mod_supported(uint32_t format
, uint64_t modifier
)
12934 case DRM_FORMAT_C8
:
12935 case DRM_FORMAT_RGB565
:
12936 case DRM_FORMAT_XRGB1555
:
12937 case DRM_FORMAT_XRGB8888
:
12938 return modifier
== DRM_FORMAT_MOD_LINEAR
||
12939 modifier
== I915_FORMAT_MOD_X_TILED
;
12945 static bool i965_mod_supported(uint32_t format
, uint64_t modifier
)
12948 case DRM_FORMAT_C8
:
12949 case DRM_FORMAT_RGB565
:
12950 case DRM_FORMAT_XRGB8888
:
12951 case DRM_FORMAT_XBGR8888
:
12952 case DRM_FORMAT_XRGB2101010
:
12953 case DRM_FORMAT_XBGR2101010
:
12954 return modifier
== DRM_FORMAT_MOD_LINEAR
||
12955 modifier
== I915_FORMAT_MOD_X_TILED
;
12961 static bool skl_mod_supported(uint32_t format
, uint64_t modifier
)
12964 case DRM_FORMAT_XRGB8888
:
12965 case DRM_FORMAT_XBGR8888
:
12966 case DRM_FORMAT_ARGB8888
:
12967 case DRM_FORMAT_ABGR8888
:
12968 if (modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
||
12969 modifier
== I915_FORMAT_MOD_Y_TILED_CCS
)
12972 case DRM_FORMAT_RGB565
:
12973 case DRM_FORMAT_XRGB2101010
:
12974 case DRM_FORMAT_XBGR2101010
:
12975 case DRM_FORMAT_YUYV
:
12976 case DRM_FORMAT_YVYU
:
12977 case DRM_FORMAT_UYVY
:
12978 case DRM_FORMAT_VYUY
:
12979 if (modifier
== I915_FORMAT_MOD_Yf_TILED
)
12982 case DRM_FORMAT_C8
:
12983 if (modifier
== DRM_FORMAT_MOD_LINEAR
||
12984 modifier
== I915_FORMAT_MOD_X_TILED
||
12985 modifier
== I915_FORMAT_MOD_Y_TILED
)
12993 static bool intel_primary_plane_format_mod_supported(struct drm_plane
*plane
,
12997 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
12999 if (WARN_ON(modifier
== DRM_FORMAT_MOD_INVALID
))
13002 if ((modifier
>> 56) != DRM_FORMAT_MOD_VENDOR_INTEL
&&
13003 modifier
!= DRM_FORMAT_MOD_LINEAR
)
13006 if (INTEL_GEN(dev_priv
) >= 9)
13007 return skl_mod_supported(format
, modifier
);
13008 else if (INTEL_GEN(dev_priv
) >= 4)
13009 return i965_mod_supported(format
, modifier
);
13011 return i8xx_mod_supported(format
, modifier
);
13016 static bool intel_cursor_plane_format_mod_supported(struct drm_plane
*plane
,
13020 if (WARN_ON(modifier
== DRM_FORMAT_MOD_INVALID
))
13023 return modifier
== DRM_FORMAT_MOD_LINEAR
&& format
== DRM_FORMAT_ARGB8888
;
13026 static struct drm_plane_funcs intel_plane_funcs
= {
13027 .update_plane
= drm_atomic_helper_update_plane
,
13028 .disable_plane
= drm_atomic_helper_disable_plane
,
13029 .destroy
= intel_plane_destroy
,
13030 .atomic_get_property
= intel_plane_atomic_get_property
,
13031 .atomic_set_property
= intel_plane_atomic_set_property
,
13032 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13033 .atomic_destroy_state
= intel_plane_destroy_state
,
13034 .format_mod_supported
= intel_primary_plane_format_mod_supported
,
13038 intel_legacy_cursor_update(struct drm_plane
*plane
,
13039 struct drm_crtc
*crtc
,
13040 struct drm_framebuffer
*fb
,
13041 int crtc_x
, int crtc_y
,
13042 unsigned int crtc_w
, unsigned int crtc_h
,
13043 uint32_t src_x
, uint32_t src_y
,
13044 uint32_t src_w
, uint32_t src_h
,
13045 struct drm_modeset_acquire_ctx
*ctx
)
13047 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
13049 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
13050 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13051 struct drm_framebuffer
*old_fb
;
13052 struct drm_crtc_state
*crtc_state
= crtc
->state
;
13053 struct i915_vma
*old_vma
, *vma
;
13056 * When crtc is inactive or there is a modeset pending,
13057 * wait for it to complete in the slowpath
13059 if (!crtc_state
->active
|| needs_modeset(crtc_state
) ||
13060 to_intel_crtc_state(crtc_state
)->update_pipe
)
13063 old_plane_state
= plane
->state
;
13066 * If any parameters change that may affect watermarks,
13067 * take the slowpath. Only changing fb or position should be
13070 if (old_plane_state
->crtc
!= crtc
||
13071 old_plane_state
->src_w
!= src_w
||
13072 old_plane_state
->src_h
!= src_h
||
13073 old_plane_state
->crtc_w
!= crtc_w
||
13074 old_plane_state
->crtc_h
!= crtc_h
||
13075 !old_plane_state
->fb
!= !fb
)
13078 new_plane_state
= intel_plane_duplicate_state(plane
);
13079 if (!new_plane_state
)
13082 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
13084 new_plane_state
->src_x
= src_x
;
13085 new_plane_state
->src_y
= src_y
;
13086 new_plane_state
->src_w
= src_w
;
13087 new_plane_state
->src_h
= src_h
;
13088 new_plane_state
->crtc_x
= crtc_x
;
13089 new_plane_state
->crtc_y
= crtc_y
;
13090 new_plane_state
->crtc_w
= crtc_w
;
13091 new_plane_state
->crtc_h
= crtc_h
;
13093 ret
= intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc
->state
),
13094 to_intel_plane_state(new_plane_state
));
13098 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
13102 if (INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
13103 int align
= intel_cursor_alignment(dev_priv
);
13105 ret
= i915_gem_object_attach_phys(intel_fb_obj(fb
), align
);
13107 DRM_DEBUG_KMS("failed to attach phys object\n");
13111 vma
= intel_pin_and_fence_fb_obj(fb
, new_plane_state
->rotation
);
13113 DRM_DEBUG_KMS("failed to pin object\n");
13115 ret
= PTR_ERR(vma
);
13119 to_intel_plane_state(new_plane_state
)->vma
= vma
;
13122 old_fb
= old_plane_state
->fb
;
13123 old_vma
= to_intel_plane_state(old_plane_state
)->vma
;
13125 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
13126 intel_plane
->frontbuffer_bit
);
13128 /* Swap plane state */
13129 new_plane_state
->fence
= old_plane_state
->fence
;
13130 *to_intel_plane_state(old_plane_state
) = *to_intel_plane_state(new_plane_state
);
13131 new_plane_state
->fence
= NULL
;
13132 new_plane_state
->fb
= old_fb
;
13133 to_intel_plane_state(new_plane_state
)->vma
= NULL
;
13135 if (plane
->state
->visible
) {
13136 trace_intel_update_plane(plane
, to_intel_crtc(crtc
));
13137 intel_plane
->update_plane(intel_plane
,
13138 to_intel_crtc_state(crtc
->state
),
13139 to_intel_plane_state(plane
->state
));
13141 trace_intel_disable_plane(plane
, to_intel_crtc(crtc
));
13142 intel_plane
->disable_plane(intel_plane
, to_intel_crtc(crtc
));
13146 intel_unpin_fb_vma(old_vma
);
13149 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
13151 intel_plane_destroy_state(plane
, new_plane_state
);
13155 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
13156 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
13157 src_x
, src_y
, src_w
, src_h
, ctx
);
13160 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
13161 .update_plane
= intel_legacy_cursor_update
,
13162 .disable_plane
= drm_atomic_helper_disable_plane
,
13163 .destroy
= intel_plane_destroy
,
13164 .atomic_get_property
= intel_plane_atomic_get_property
,
13165 .atomic_set_property
= intel_plane_atomic_set_property
,
13166 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13167 .atomic_destroy_state
= intel_plane_destroy_state
,
13168 .format_mod_supported
= intel_cursor_plane_format_mod_supported
,
13171 static struct intel_plane
*
13172 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
13174 struct intel_plane
*primary
= NULL
;
13175 struct intel_plane_state
*state
= NULL
;
13176 const uint32_t *intel_primary_formats
;
13177 unsigned int supported_rotations
;
13178 unsigned int num_formats
;
13179 const uint64_t *modifiers
;
13182 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13188 state
= intel_create_plane_state(&primary
->base
);
13194 primary
->base
.state
= &state
->base
;
13196 primary
->can_scale
= false;
13197 primary
->max_downscale
= 1;
13198 if (INTEL_GEN(dev_priv
) >= 9) {
13199 primary
->can_scale
= true;
13200 state
->scaler_id
= -1;
13202 primary
->pipe
= pipe
;
13204 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13205 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13207 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
13208 primary
->plane
= (enum plane
) !pipe
;
13210 primary
->plane
= (enum plane
) pipe
;
13211 primary
->id
= PLANE_PRIMARY
;
13212 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13213 primary
->check_plane
= intel_check_primary_plane
;
13215 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
13216 intel_primary_formats
= skl_primary_formats
;
13217 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13218 modifiers
= skl_format_modifiers_ccs
;
13220 primary
->update_plane
= skylake_update_primary_plane
;
13221 primary
->disable_plane
= skylake_disable_primary_plane
;
13222 } else if (INTEL_GEN(dev_priv
) >= 9) {
13223 intel_primary_formats
= skl_primary_formats
;
13224 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13226 modifiers
= skl_format_modifiers_ccs
;
13228 modifiers
= skl_format_modifiers_noccs
;
13230 primary
->update_plane
= skylake_update_primary_plane
;
13231 primary
->disable_plane
= skylake_disable_primary_plane
;
13232 } else if (INTEL_GEN(dev_priv
) >= 4) {
13233 intel_primary_formats
= i965_primary_formats
;
13234 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13235 modifiers
= i9xx_format_modifiers
;
13237 primary
->update_plane
= i9xx_update_primary_plane
;
13238 primary
->disable_plane
= i9xx_disable_primary_plane
;
13240 intel_primary_formats
= i8xx_primary_formats
;
13241 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13242 modifiers
= i9xx_format_modifiers
;
13244 primary
->update_plane
= i9xx_update_primary_plane
;
13245 primary
->disable_plane
= i9xx_disable_primary_plane
;
13248 if (INTEL_GEN(dev_priv
) >= 9)
13249 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
13250 0, &intel_plane_funcs
,
13251 intel_primary_formats
, num_formats
,
13253 DRM_PLANE_TYPE_PRIMARY
,
13254 "plane 1%c", pipe_name(pipe
));
13255 else if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
13256 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
13257 0, &intel_plane_funcs
,
13258 intel_primary_formats
, num_formats
,
13260 DRM_PLANE_TYPE_PRIMARY
,
13261 "primary %c", pipe_name(pipe
));
13263 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
13264 0, &intel_plane_funcs
,
13265 intel_primary_formats
, num_formats
,
13267 DRM_PLANE_TYPE_PRIMARY
,
13268 "plane %c", plane_name(primary
->plane
));
13272 if (INTEL_GEN(dev_priv
) >= 9) {
13273 supported_rotations
=
13274 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_90
|
13275 DRM_MODE_ROTATE_180
| DRM_MODE_ROTATE_270
;
13276 } else if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
13277 supported_rotations
=
13278 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
13279 DRM_MODE_REFLECT_X
;
13280 } else if (INTEL_GEN(dev_priv
) >= 4) {
13281 supported_rotations
=
13282 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
13284 supported_rotations
= DRM_MODE_ROTATE_0
;
13287 if (INTEL_GEN(dev_priv
) >= 4)
13288 drm_plane_create_rotation_property(&primary
->base
,
13290 supported_rotations
);
13292 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13300 return ERR_PTR(ret
);
13303 static struct intel_plane
*
13304 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
,
13307 struct intel_plane
*cursor
= NULL
;
13308 struct intel_plane_state
*state
= NULL
;
13311 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13317 state
= intel_create_plane_state(&cursor
->base
);
13323 cursor
->base
.state
= &state
->base
;
13325 cursor
->can_scale
= false;
13326 cursor
->max_downscale
= 1;
13327 cursor
->pipe
= pipe
;
13328 cursor
->plane
= pipe
;
13329 cursor
->id
= PLANE_CURSOR
;
13330 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13332 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
13333 cursor
->update_plane
= i845_update_cursor
;
13334 cursor
->disable_plane
= i845_disable_cursor
;
13335 cursor
->check_plane
= i845_check_cursor
;
13337 cursor
->update_plane
= i9xx_update_cursor
;
13338 cursor
->disable_plane
= i9xx_disable_cursor
;
13339 cursor
->check_plane
= i9xx_check_cursor
;
13342 cursor
->cursor
.base
= ~0;
13343 cursor
->cursor
.cntl
= ~0;
13345 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
) || HAS_CUR_FBC(dev_priv
))
13346 cursor
->cursor
.size
= ~0;
13348 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
13349 0, &intel_cursor_plane_funcs
,
13350 intel_cursor_formats
,
13351 ARRAY_SIZE(intel_cursor_formats
),
13352 cursor_format_modifiers
,
13353 DRM_PLANE_TYPE_CURSOR
,
13354 "cursor %c", pipe_name(pipe
));
13358 if (INTEL_GEN(dev_priv
) >= 4)
13359 drm_plane_create_rotation_property(&cursor
->base
,
13361 DRM_MODE_ROTATE_0
|
13362 DRM_MODE_ROTATE_180
);
13364 if (INTEL_GEN(dev_priv
) >= 9)
13365 state
->scaler_id
= -1;
13367 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13375 return ERR_PTR(ret
);
13378 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
13379 struct intel_crtc_state
*crtc_state
)
13381 struct intel_crtc_scaler_state
*scaler_state
=
13382 &crtc_state
->scaler_state
;
13383 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
13386 crtc
->num_scalers
= dev_priv
->info
.num_scalers
[crtc
->pipe
];
13387 if (!crtc
->num_scalers
)
13390 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
13391 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
13393 scaler
->in_use
= 0;
13394 scaler
->mode
= PS_SCALER_MODE_DYN
;
13397 scaler_state
->scaler_id
= -1;
13400 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
13402 struct intel_crtc
*intel_crtc
;
13403 struct intel_crtc_state
*crtc_state
= NULL
;
13404 struct intel_plane
*primary
= NULL
;
13405 struct intel_plane
*cursor
= NULL
;
13408 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13412 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13417 intel_crtc
->config
= crtc_state
;
13418 intel_crtc
->base
.state
= &crtc_state
->base
;
13419 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13421 primary
= intel_primary_plane_create(dev_priv
, pipe
);
13422 if (IS_ERR(primary
)) {
13423 ret
= PTR_ERR(primary
);
13426 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
13428 for_each_sprite(dev_priv
, pipe
, sprite
) {
13429 struct intel_plane
*plane
;
13431 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
13432 if (IS_ERR(plane
)) {
13433 ret
= PTR_ERR(plane
);
13436 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
13439 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
13440 if (IS_ERR(cursor
)) {
13441 ret
= PTR_ERR(cursor
);
13444 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
13446 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
13447 &primary
->base
, &cursor
->base
,
13449 "pipe %c", pipe_name(pipe
));
13453 intel_crtc
->pipe
= pipe
;
13454 intel_crtc
->plane
= primary
->plane
;
13456 /* initialize shared scalers */
13457 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
13459 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13460 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13461 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = intel_crtc
;
13462 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = intel_crtc
;
13464 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13466 intel_color_init(&intel_crtc
->base
);
13468 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13474 * drm_mode_config_cleanup() will free up any
13475 * crtcs/planes already initialized.
13483 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13485 struct drm_device
*dev
= connector
->base
.dev
;
13487 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13489 if (!connector
->base
.state
->crtc
)
13490 return INVALID_PIPE
;
13492 return to_intel_crtc(connector
->base
.state
->crtc
)->pipe
;
13495 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13496 struct drm_file
*file
)
13498 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13499 struct drm_crtc
*drmmode_crtc
;
13500 struct intel_crtc
*crtc
;
13502 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13506 crtc
= to_intel_crtc(drmmode_crtc
);
13507 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13512 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13514 struct drm_device
*dev
= encoder
->base
.dev
;
13515 struct intel_encoder
*source_encoder
;
13516 int index_mask
= 0;
13519 for_each_intel_encoder(dev
, source_encoder
) {
13520 if (encoders_cloneable(encoder
, source_encoder
))
13521 index_mask
|= (1 << entry
);
13529 static bool has_edp_a(struct drm_i915_private
*dev_priv
)
13531 if (!IS_MOBILE(dev_priv
))
13534 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13537 if (IS_GEN5(dev_priv
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13543 static bool intel_crt_present(struct drm_i915_private
*dev_priv
)
13545 if (INTEL_GEN(dev_priv
) >= 9)
13548 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
13551 if (IS_CHERRYVIEW(dev_priv
))
13554 if (HAS_PCH_LPT_H(dev_priv
) &&
13555 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
13558 /* DDI E can't be used if DDI A requires 4 lanes */
13559 if (HAS_DDI(dev_priv
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
13562 if (!dev_priv
->vbt
.int_crt_support
)
13568 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
13573 if (HAS_DDI(dev_priv
))
13576 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13577 * everywhere where registers can be write protected.
13579 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
13584 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
13585 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
13587 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
13588 I915_WRITE(PP_CONTROL(pps_idx
), val
);
13592 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
13594 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
13595 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
13596 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
13597 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
13599 dev_priv
->pps_mmio_base
= PPS_BASE
;
13601 intel_pps_unlock_regs_wa(dev_priv
);
13604 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
13606 struct intel_encoder
*encoder
;
13607 bool dpd_is_edp
= false;
13609 intel_pps_init(dev_priv
);
13612 * intel_edp_init_connector() depends on this completing first, to
13613 * prevent the registeration of both eDP and LVDS and the incorrect
13614 * sharing of the PPS.
13616 intel_lvds_init(dev_priv
);
13618 if (intel_crt_present(dev_priv
))
13619 intel_crt_init(dev_priv
);
13621 if (IS_GEN9_LP(dev_priv
)) {
13623 * FIXME: Broxton doesn't support port detection via the
13624 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13625 * detect the ports.
13627 intel_ddi_init(dev_priv
, PORT_A
);
13628 intel_ddi_init(dev_priv
, PORT_B
);
13629 intel_ddi_init(dev_priv
, PORT_C
);
13631 intel_dsi_init(dev_priv
);
13632 } else if (HAS_DDI(dev_priv
)) {
13636 * Haswell uses DDI functions to detect digital outputs.
13637 * On SKL pre-D0 the strap isn't connected, so we assume
13640 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
13641 /* WaIgnoreDDIAStrap: skl */
13642 if (found
|| IS_GEN9_BC(dev_priv
))
13643 intel_ddi_init(dev_priv
, PORT_A
);
13645 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13647 found
= I915_READ(SFUSE_STRAP
);
13649 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13650 intel_ddi_init(dev_priv
, PORT_B
);
13651 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13652 intel_ddi_init(dev_priv
, PORT_C
);
13653 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13654 intel_ddi_init(dev_priv
, PORT_D
);
13656 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13658 if (IS_GEN9_BC(dev_priv
) &&
13659 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
13660 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
13661 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
13662 intel_ddi_init(dev_priv
, PORT_E
);
13664 } else if (HAS_PCH_SPLIT(dev_priv
)) {
13666 dpd_is_edp
= intel_dp_is_edp(dev_priv
, PORT_D
);
13668 if (has_edp_a(dev_priv
))
13669 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
13671 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13672 /* PCH SDVOB multiplex with HDMIB */
13673 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
13675 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
13676 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13677 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
13680 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13681 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
13683 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13684 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
13686 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13687 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
13689 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13690 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
13691 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
13692 bool has_edp
, has_port
;
13695 * The DP_DETECTED bit is the latched state of the DDC
13696 * SDA pin at boot. However since eDP doesn't require DDC
13697 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13698 * eDP ports may have been muxed to an alternate function.
13699 * Thus we can't rely on the DP_DETECTED bit alone to detect
13700 * eDP ports. Consult the VBT as well as DP_DETECTED to
13701 * detect eDP ports.
13703 * Sadly the straps seem to be missing sometimes even for HDMI
13704 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13705 * and VBT for the presence of the port. Additionally we can't
13706 * trust the port type the VBT declares as we've seen at least
13707 * HDMI ports that the VBT claim are DP or eDP.
13709 has_edp
= intel_dp_is_edp(dev_priv
, PORT_B
);
13710 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
13711 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
13712 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
13713 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
13714 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
13716 has_edp
= intel_dp_is_edp(dev_priv
, PORT_C
);
13717 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
13718 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
13719 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
13720 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
13721 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
13723 if (IS_CHERRYVIEW(dev_priv
)) {
13725 * eDP not supported on port D,
13726 * so no need to worry about it
13728 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
13729 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
13730 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
13731 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
13732 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
13735 intel_dsi_init(dev_priv
);
13736 } else if (!IS_GEN2(dev_priv
) && !IS_PINEVIEW(dev_priv
)) {
13737 bool found
= false;
13739 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13740 DRM_DEBUG_KMS("probing SDVOB\n");
13741 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
13742 if (!found
&& IS_G4X(dev_priv
)) {
13743 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13744 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
13747 if (!found
&& IS_G4X(dev_priv
))
13748 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
13751 /* Before G4X SDVOC doesn't have its own detect register */
13753 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13754 DRM_DEBUG_KMS("probing SDVOC\n");
13755 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
13758 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
13760 if (IS_G4X(dev_priv
)) {
13761 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13762 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
13764 if (IS_G4X(dev_priv
))
13765 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
13768 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
13769 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
13770 } else if (IS_GEN2(dev_priv
))
13771 intel_dvo_init(dev_priv
);
13773 if (SUPPORTS_TV(dev_priv
))
13774 intel_tv_init(dev_priv
);
13776 intel_psr_init(dev_priv
);
13778 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
13779 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
13780 encoder
->base
.possible_clones
=
13781 intel_encoder_clones(encoder
);
13784 intel_init_pch_refclk(dev_priv
);
13786 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
13789 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
13791 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13793 drm_framebuffer_cleanup(fb
);
13795 i915_gem_object_lock(intel_fb
->obj
);
13796 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
13797 i915_gem_object_unlock(intel_fb
->obj
);
13799 i915_gem_object_put(intel_fb
->obj
);
13804 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
13805 struct drm_file
*file
,
13806 unsigned int *handle
)
13808 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13809 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
13811 if (obj
->userptr
.mm
) {
13812 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13816 return drm_gem_handle_create(file
, &obj
->base
, handle
);
13819 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
13820 struct drm_file
*file
,
13821 unsigned flags
, unsigned color
,
13822 struct drm_clip_rect
*clips
,
13823 unsigned num_clips
)
13825 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13827 i915_gem_object_flush_if_display(obj
);
13828 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
13833 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
13834 .destroy
= intel_user_framebuffer_destroy
,
13835 .create_handle
= intel_user_framebuffer_create_handle
,
13836 .dirty
= intel_user_framebuffer_dirty
,
13840 u32
intel_fb_pitch_limit(struct drm_i915_private
*dev_priv
,
13841 uint64_t fb_modifier
, uint32_t pixel_format
)
13843 u32 gen
= INTEL_GEN(dev_priv
);
13846 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
13848 /* "The stride in bytes must not exceed the of the size of 8K
13849 * pixels and 32K bytes."
13851 return min(8192 * cpp
, 32768);
13852 } else if (gen
>= 5 && !HAS_GMCH_DISPLAY(dev_priv
)) {
13854 } else if (gen
>= 4) {
13855 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13859 } else if (gen
>= 3) {
13860 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13865 /* XXX DSPC is limited to 4k tiled */
13870 static int intel_framebuffer_init(struct intel_framebuffer
*intel_fb
,
13871 struct drm_i915_gem_object
*obj
,
13872 struct drm_mode_fb_cmd2
*mode_cmd
)
13874 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
13875 struct drm_framebuffer
*fb
= &intel_fb
->base
;
13876 struct drm_format_name_buf format_name
;
13878 unsigned int tiling
, stride
;
13882 i915_gem_object_lock(obj
);
13883 obj
->framebuffer_references
++;
13884 tiling
= i915_gem_object_get_tiling(obj
);
13885 stride
= i915_gem_object_get_stride(obj
);
13886 i915_gem_object_unlock(obj
);
13888 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
13890 * If there's a fence, enforce that
13891 * the fb modifier and tiling mode match.
13893 if (tiling
!= I915_TILING_NONE
&&
13894 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
13895 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13899 if (tiling
== I915_TILING_X
) {
13900 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
13901 } else if (tiling
== I915_TILING_Y
) {
13902 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13907 /* Passed in modifier sanity checking. */
13908 switch (mode_cmd
->modifier
[0]) {
13909 case I915_FORMAT_MOD_Y_TILED_CCS
:
13910 case I915_FORMAT_MOD_Yf_TILED_CCS
:
13911 switch (mode_cmd
->pixel_format
) {
13912 case DRM_FORMAT_XBGR8888
:
13913 case DRM_FORMAT_ABGR8888
:
13914 case DRM_FORMAT_XRGB8888
:
13915 case DRM_FORMAT_ARGB8888
:
13918 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13922 case I915_FORMAT_MOD_Y_TILED
:
13923 case I915_FORMAT_MOD_Yf_TILED
:
13924 if (INTEL_GEN(dev_priv
) < 9) {
13925 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13926 mode_cmd
->modifier
[0]);
13929 case DRM_FORMAT_MOD_LINEAR
:
13930 case I915_FORMAT_MOD_X_TILED
:
13933 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13934 mode_cmd
->modifier
[0]);
13939 * gen2/3 display engine uses the fence if present,
13940 * so the tiling mode must match the fb modifier exactly.
13942 if (INTEL_INFO(dev_priv
)->gen
< 4 &&
13943 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
13944 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13948 pitch_limit
= intel_fb_pitch_limit(dev_priv
, mode_cmd
->modifier
[0],
13949 mode_cmd
->pixel_format
);
13950 if (mode_cmd
->pitches
[0] > pitch_limit
) {
13951 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13952 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_LINEAR
?
13953 "tiled" : "linear",
13954 mode_cmd
->pitches
[0], pitch_limit
);
13959 * If there's a fence, enforce that
13960 * the fb pitch and fence stride match.
13962 if (tiling
!= I915_TILING_NONE
&& mode_cmd
->pitches
[0] != stride
) {
13963 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13964 mode_cmd
->pitches
[0], stride
);
13968 /* Reject formats not supported by any plane early. */
13969 switch (mode_cmd
->pixel_format
) {
13970 case DRM_FORMAT_C8
:
13971 case DRM_FORMAT_RGB565
:
13972 case DRM_FORMAT_XRGB8888
:
13973 case DRM_FORMAT_ARGB8888
:
13975 case DRM_FORMAT_XRGB1555
:
13976 if (INTEL_GEN(dev_priv
) > 3) {
13977 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13978 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13982 case DRM_FORMAT_ABGR8888
:
13983 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
13984 INTEL_GEN(dev_priv
) < 9) {
13985 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13986 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13990 case DRM_FORMAT_XBGR8888
:
13991 case DRM_FORMAT_XRGB2101010
:
13992 case DRM_FORMAT_XBGR2101010
:
13993 if (INTEL_GEN(dev_priv
) < 4) {
13994 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13995 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13999 case DRM_FORMAT_ABGR2101010
:
14000 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
14001 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14002 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
14006 case DRM_FORMAT_YUYV
:
14007 case DRM_FORMAT_UYVY
:
14008 case DRM_FORMAT_YVYU
:
14009 case DRM_FORMAT_VYUY
:
14010 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
14011 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14012 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
14017 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14018 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
14022 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14023 if (mode_cmd
->offsets
[0] != 0)
14026 drm_helper_mode_fill_fb_struct(&dev_priv
->drm
, fb
, mode_cmd
);
14028 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
14029 u32 stride_alignment
;
14031 if (mode_cmd
->handles
[i
] != mode_cmd
->handles
[0]) {
14032 DRM_DEBUG_KMS("bad plane %d handle\n", i
);
14036 stride_alignment
= intel_fb_stride_alignment(fb
, i
);
14039 * Display WA #0531: skl,bxt,kbl,glk
14041 * Render decompression and plane width > 3840
14042 * combined with horizontal panning requires the
14043 * plane stride to be a multiple of 4. We'll just
14044 * require the entire fb to accommodate that to avoid
14045 * potential runtime errors at plane configuration time.
14047 if (IS_GEN9(dev_priv
) && i
== 0 && fb
->width
> 3840 &&
14048 (fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
14049 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
))
14050 stride_alignment
*= 4;
14052 if (fb
->pitches
[i
] & (stride_alignment
- 1)) {
14053 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14054 i
, fb
->pitches
[i
], stride_alignment
);
14059 intel_fb
->obj
= obj
;
14061 ret
= intel_fill_fb_info(dev_priv
, fb
);
14065 ret
= drm_framebuffer_init(&dev_priv
->drm
, fb
, &intel_fb_funcs
);
14067 DRM_ERROR("framebuffer init failed %d\n", ret
);
14074 i915_gem_object_lock(obj
);
14075 obj
->framebuffer_references
--;
14076 i915_gem_object_unlock(obj
);
14080 static struct drm_framebuffer
*
14081 intel_user_framebuffer_create(struct drm_device
*dev
,
14082 struct drm_file
*filp
,
14083 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
14085 struct drm_framebuffer
*fb
;
14086 struct drm_i915_gem_object
*obj
;
14087 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
14089 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
14091 return ERR_PTR(-ENOENT
);
14093 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
14095 i915_gem_object_put(obj
);
14100 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
14102 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14104 drm_atomic_state_default_release(state
);
14106 i915_sw_fence_fini(&intel_state
->commit_ready
);
14111 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14112 .fb_create
= intel_user_framebuffer_create
,
14113 .get_format_info
= intel_get_format_info
,
14114 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14115 .atomic_check
= intel_atomic_check
,
14116 .atomic_commit
= intel_atomic_commit
,
14117 .atomic_state_alloc
= intel_atomic_state_alloc
,
14118 .atomic_state_clear
= intel_atomic_state_clear
,
14119 .atomic_state_free
= intel_atomic_state_free
,
14123 * intel_init_display_hooks - initialize the display modesetting hooks
14124 * @dev_priv: device private
14126 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
14128 intel_init_cdclk_hooks(dev_priv
);
14130 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
14131 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14132 dev_priv
->display
.get_initial_plane_config
=
14133 skylake_get_initial_plane_config
;
14134 dev_priv
->display
.crtc_compute_clock
=
14135 haswell_crtc_compute_clock
;
14136 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14137 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14138 } else if (HAS_DDI(dev_priv
)) {
14139 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14140 dev_priv
->display
.get_initial_plane_config
=
14141 ironlake_get_initial_plane_config
;
14142 dev_priv
->display
.crtc_compute_clock
=
14143 haswell_crtc_compute_clock
;
14144 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14145 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14146 } else if (HAS_PCH_SPLIT(dev_priv
)) {
14147 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14148 dev_priv
->display
.get_initial_plane_config
=
14149 ironlake_get_initial_plane_config
;
14150 dev_priv
->display
.crtc_compute_clock
=
14151 ironlake_crtc_compute_clock
;
14152 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14153 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14154 } else if (IS_CHERRYVIEW(dev_priv
)) {
14155 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14156 dev_priv
->display
.get_initial_plane_config
=
14157 i9xx_get_initial_plane_config
;
14158 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
14159 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14160 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14161 } else if (IS_VALLEYVIEW(dev_priv
)) {
14162 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14163 dev_priv
->display
.get_initial_plane_config
=
14164 i9xx_get_initial_plane_config
;
14165 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
14166 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14167 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14168 } else if (IS_G4X(dev_priv
)) {
14169 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14170 dev_priv
->display
.get_initial_plane_config
=
14171 i9xx_get_initial_plane_config
;
14172 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
14173 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14174 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14175 } else if (IS_PINEVIEW(dev_priv
)) {
14176 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14177 dev_priv
->display
.get_initial_plane_config
=
14178 i9xx_get_initial_plane_config
;
14179 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
14180 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14181 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14182 } else if (!IS_GEN2(dev_priv
)) {
14183 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14184 dev_priv
->display
.get_initial_plane_config
=
14185 i9xx_get_initial_plane_config
;
14186 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14187 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14188 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14190 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14191 dev_priv
->display
.get_initial_plane_config
=
14192 i9xx_get_initial_plane_config
;
14193 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
14194 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14195 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14198 if (IS_GEN5(dev_priv
)) {
14199 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14200 } else if (IS_GEN6(dev_priv
)) {
14201 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14202 } else if (IS_IVYBRIDGE(dev_priv
)) {
14203 /* FIXME: detect B0+ stepping and use auto training */
14204 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14205 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
14206 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14209 if (dev_priv
->info
.gen
>= 9)
14210 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
14212 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
14216 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14218 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14220 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14221 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14222 DRM_INFO("applying lvds SSC disable quirk\n");
14226 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14229 static void quirk_invert_brightness(struct drm_device
*dev
)
14231 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14232 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14233 DRM_INFO("applying inverted panel brightness quirk\n");
14236 /* Some VBT's incorrectly indicate no backlight is present */
14237 static void quirk_backlight_present(struct drm_device
*dev
)
14239 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14240 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14241 DRM_INFO("applying backlight present quirk\n");
14244 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14245 * which is 300 ms greater than eDP spec T12 min.
14247 static void quirk_increase_t12_delay(struct drm_device
*dev
)
14249 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14251 dev_priv
->quirks
|= QUIRK_INCREASE_T12_DELAY
;
14252 DRM_INFO("Applying T12 delay quirk\n");
14255 struct intel_quirk
{
14257 int subsystem_vendor
;
14258 int subsystem_device
;
14259 void (*hook
)(struct drm_device
*dev
);
14262 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14263 struct intel_dmi_quirk
{
14264 void (*hook
)(struct drm_device
*dev
);
14265 const struct dmi_system_id (*dmi_id_list
)[];
14268 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14270 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14274 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14276 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14278 .callback
= intel_dmi_reverse_brightness
,
14279 .ident
= "NCR Corporation",
14280 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14281 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14284 { } /* terminating entry */
14286 .hook
= quirk_invert_brightness
,
14290 static struct intel_quirk intel_quirks
[] = {
14291 /* Lenovo U160 cannot use SSC on LVDS */
14292 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14294 /* Sony Vaio Y cannot use SSC on LVDS */
14295 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14297 /* Acer Aspire 5734Z must invert backlight brightness */
14298 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14300 /* Acer/eMachines G725 */
14301 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14303 /* Acer/eMachines e725 */
14304 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14306 /* Acer/Packard Bell NCL20 */
14307 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14309 /* Acer Aspire 4736Z */
14310 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14312 /* Acer Aspire 5336 */
14313 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14315 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14316 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14318 /* Acer C720 Chromebook (Core i3 4005U) */
14319 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14321 /* Apple Macbook 2,1 (Core 2 T7400) */
14322 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14324 /* Apple Macbook 4,1 */
14325 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
14327 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14328 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14330 /* HP Chromebook 14 (Celeron 2955U) */
14331 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14333 /* Dell Chromebook 11 */
14334 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14336 /* Dell Chromebook 11 (2015 version) */
14337 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
14339 /* Toshiba Satellite P50-C-18C */
14340 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay
},
14343 static void intel_init_quirks(struct drm_device
*dev
)
14345 struct pci_dev
*d
= dev
->pdev
;
14348 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14349 struct intel_quirk
*q
= &intel_quirks
[i
];
14351 if (d
->device
== q
->device
&&
14352 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14353 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14354 (d
->subsystem_device
== q
->subsystem_device
||
14355 q
->subsystem_device
== PCI_ANY_ID
))
14358 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14359 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14360 intel_dmi_quirks
[i
].hook(dev
);
14364 /* Disable the VGA plane that we never use */
14365 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
14367 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
14369 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
14371 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14372 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
14373 outb(SR01
, VGA_SR_INDEX
);
14374 sr1
= inb(VGA_SR_DATA
);
14375 outb(sr1
| 1<<5, VGA_SR_DATA
);
14376 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
14379 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14380 POSTING_READ(vga_reg
);
14383 void intel_modeset_init_hw(struct drm_device
*dev
)
14385 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14387 intel_update_cdclk(dev_priv
);
14388 dev_priv
->cdclk
.logical
= dev_priv
->cdclk
.actual
= dev_priv
->cdclk
.hw
;
14390 intel_init_clock_gating(dev_priv
);
14394 * Calculate what we think the watermarks should be for the state we've read
14395 * out of the hardware and then immediately program those watermarks so that
14396 * we ensure the hardware settings match our internal state.
14398 * We can calculate what we think WM's should be by creating a duplicate of the
14399 * current state (which was constructed during hardware readout) and running it
14400 * through the atomic check code to calculate new watermark values in the
14403 static void sanitize_watermarks(struct drm_device
*dev
)
14405 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14406 struct drm_atomic_state
*state
;
14407 struct intel_atomic_state
*intel_state
;
14408 struct drm_crtc
*crtc
;
14409 struct drm_crtc_state
*cstate
;
14410 struct drm_modeset_acquire_ctx ctx
;
14414 /* Only supported on platforms that use atomic watermark design */
14415 if (!dev_priv
->display
.optimize_watermarks
)
14419 * We need to hold connection_mutex before calling duplicate_state so
14420 * that the connector loop is protected.
14422 drm_modeset_acquire_init(&ctx
, 0);
14424 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
14425 if (ret
== -EDEADLK
) {
14426 drm_modeset_backoff(&ctx
);
14428 } else if (WARN_ON(ret
)) {
14432 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
14433 if (WARN_ON(IS_ERR(state
)))
14436 intel_state
= to_intel_atomic_state(state
);
14439 * Hardware readout is the only time we don't want to calculate
14440 * intermediate watermarks (since we don't trust the current
14443 if (!HAS_GMCH_DISPLAY(dev_priv
))
14444 intel_state
->skip_intermediate_wm
= true;
14446 ret
= intel_atomic_check(dev
, state
);
14449 * If we fail here, it means that the hardware appears to be
14450 * programmed in a way that shouldn't be possible, given our
14451 * understanding of watermark requirements. This might mean a
14452 * mistake in the hardware readout code or a mistake in the
14453 * watermark calculations for a given platform. Raise a WARN
14454 * so that this is noticeable.
14456 * If this actually happens, we'll have to just leave the
14457 * BIOS-programmed watermarks untouched and hope for the best.
14459 WARN(true, "Could not determine valid watermarks for inherited state\n");
14463 /* Write calculated watermark values back */
14464 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
14465 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
14467 cs
->wm
.need_postvbl_update
= true;
14468 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
14472 drm_atomic_state_put(state
);
14474 drm_modeset_drop_locks(&ctx
);
14475 drm_modeset_acquire_fini(&ctx
);
14478 int intel_modeset_init(struct drm_device
*dev
)
14480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14481 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
14483 struct intel_crtc
*crtc
;
14485 drm_mode_config_init(dev
);
14487 dev
->mode_config
.min_width
= 0;
14488 dev
->mode_config
.min_height
= 0;
14490 dev
->mode_config
.preferred_depth
= 24;
14491 dev
->mode_config
.prefer_shadow
= 1;
14493 dev
->mode_config
.allow_fb_modifiers
= true;
14495 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14497 init_llist_head(&dev_priv
->atomic_helper
.free_list
);
14498 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
14499 intel_atomic_helper_free_state_worker
);
14501 intel_init_quirks(dev
);
14503 intel_init_pm(dev_priv
);
14505 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
14509 * There may be no VBT; and if the BIOS enabled SSC we can
14510 * just keep using it to avoid unnecessary flicker. Whereas if the
14511 * BIOS isn't using it, don't assume it will work even if the VBT
14512 * indicates as much.
14514 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
14515 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14518 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
14519 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14520 bios_lvds_use_ssc
? "en" : "dis",
14521 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
14522 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
14526 if (IS_GEN2(dev_priv
)) {
14527 dev
->mode_config
.max_width
= 2048;
14528 dev
->mode_config
.max_height
= 2048;
14529 } else if (IS_GEN3(dev_priv
)) {
14530 dev
->mode_config
.max_width
= 4096;
14531 dev
->mode_config
.max_height
= 4096;
14533 dev
->mode_config
.max_width
= 8192;
14534 dev
->mode_config
.max_height
= 8192;
14537 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
14538 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
14539 dev
->mode_config
.cursor_height
= 1023;
14540 } else if (IS_GEN2(dev_priv
)) {
14541 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14542 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14544 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14545 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14548 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
14550 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14551 INTEL_INFO(dev_priv
)->num_pipes
,
14552 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
14554 for_each_pipe(dev_priv
, pipe
) {
14557 ret
= intel_crtc_init(dev_priv
, pipe
);
14559 drm_mode_config_cleanup(dev
);
14564 intel_shared_dpll_init(dev
);
14566 intel_update_czclk(dev_priv
);
14567 intel_modeset_init_hw(dev
);
14569 if (dev_priv
->max_cdclk_freq
== 0)
14570 intel_update_max_cdclk(dev_priv
);
14572 /* Just disable it once at startup */
14573 i915_disable_vga(dev_priv
);
14574 intel_setup_outputs(dev_priv
);
14576 drm_modeset_lock_all(dev
);
14577 intel_modeset_setup_hw_state(dev
, dev
->mode_config
.acquire_ctx
);
14578 drm_modeset_unlock_all(dev
);
14580 for_each_intel_crtc(dev
, crtc
) {
14581 struct intel_initial_plane_config plane_config
= {};
14587 * Note that reserving the BIOS fb up front prevents us
14588 * from stuffing other stolen allocations like the ring
14589 * on top. This prevents some ugliness at boot time, and
14590 * can even allow for smooth boot transitions if the BIOS
14591 * fb is large enough for the active pipe configuration.
14593 dev_priv
->display
.get_initial_plane_config(crtc
,
14597 * If the fb is shared between multiple heads, we'll
14598 * just get the first one.
14600 intel_find_initial_plane_obj(crtc
, &plane_config
);
14604 * Make sure hardware watermarks really match the state we read out.
14605 * Note that we need to do this after reconstructing the BIOS fb's
14606 * since the watermark calculation done here will use pstate->fb.
14608 if (!HAS_GMCH_DISPLAY(dev_priv
))
14609 sanitize_watermarks(dev
);
14614 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14616 /* 640x480@60Hz, ~25175 kHz */
14617 struct dpll clock
= {
14627 WARN_ON(i9xx_calc_dpll_params(48000, &clock
) != 25154);
14629 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14630 pipe_name(pipe
), clock
.vco
, clock
.dot
);
14632 fp
= i9xx_dpll_compute_fp(&clock
);
14633 dpll
= (I915_READ(DPLL(pipe
)) & DPLL_DVO_2X_MODE
) |
14634 DPLL_VGA_MODE_DIS
|
14635 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
14636 PLL_P2_DIVIDE_BY_4
|
14637 PLL_REF_INPUT_DREFCLK
|
14640 I915_WRITE(FP0(pipe
), fp
);
14641 I915_WRITE(FP1(pipe
), fp
);
14643 I915_WRITE(HTOTAL(pipe
), (640 - 1) | ((800 - 1) << 16));
14644 I915_WRITE(HBLANK(pipe
), (640 - 1) | ((800 - 1) << 16));
14645 I915_WRITE(HSYNC(pipe
), (656 - 1) | ((752 - 1) << 16));
14646 I915_WRITE(VTOTAL(pipe
), (480 - 1) | ((525 - 1) << 16));
14647 I915_WRITE(VBLANK(pipe
), (480 - 1) | ((525 - 1) << 16));
14648 I915_WRITE(VSYNC(pipe
), (490 - 1) | ((492 - 1) << 16));
14649 I915_WRITE(PIPESRC(pipe
), ((640 - 1) << 16) | (480 - 1));
14652 * Apparently we need to have VGA mode enabled prior to changing
14653 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14654 * dividers, even though the register value does change.
14656 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
14657 I915_WRITE(DPLL(pipe
), dpll
);
14659 /* Wait for the clocks to stabilize. */
14660 POSTING_READ(DPLL(pipe
));
14663 /* The pixel multiplier can only be updated once the
14664 * DPLL is enabled and the clocks are stable.
14666 * So write it again.
14668 I915_WRITE(DPLL(pipe
), dpll
);
14670 /* We do this three times for luck */
14671 for (i
= 0; i
< 3 ; i
++) {
14672 I915_WRITE(DPLL(pipe
), dpll
);
14673 POSTING_READ(DPLL(pipe
));
14674 udelay(150); /* wait for warmup */
14677 I915_WRITE(PIPECONF(pipe
), PIPECONF_ENABLE
| PIPECONF_PROGRESSIVE
);
14678 POSTING_READ(PIPECONF(pipe
));
14681 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14683 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14686 assert_plane_disabled(dev_priv
, PLANE_A
);
14687 assert_plane_disabled(dev_priv
, PLANE_B
);
14689 I915_WRITE(PIPECONF(pipe
), 0);
14690 POSTING_READ(PIPECONF(pipe
));
14692 if (wait_for(pipe_dsl_stopped(dev_priv
, pipe
), 100))
14693 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe
));
14695 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
14696 POSTING_READ(DPLL(pipe
));
14700 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14702 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14705 if (INTEL_INFO(dev_priv
)->num_pipes
== 1)
14708 val
= I915_READ(DSPCNTR(!crtc
->plane
));
14710 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14711 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14717 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
14719 struct drm_device
*dev
= crtc
->base
.dev
;
14720 struct intel_encoder
*encoder
;
14722 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
14728 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
14730 struct drm_device
*dev
= encoder
->base
.dev
;
14731 struct intel_connector
*connector
;
14733 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
14739 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
14740 enum transcoder pch_transcoder
)
14742 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
14743 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== TRANSCODER_A
);
14746 static void intel_sanitize_crtc(struct intel_crtc
*crtc
,
14747 struct drm_modeset_acquire_ctx
*ctx
)
14749 struct drm_device
*dev
= crtc
->base
.dev
;
14750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14751 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
14753 /* Clear any frame start delays used for debugging left by the BIOS */
14754 if (!transcoder_is_dsi(cpu_transcoder
)) {
14755 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
14758 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14761 /* restore vblank interrupts to correct state */
14762 drm_crtc_vblank_reset(&crtc
->base
);
14763 if (crtc
->active
) {
14764 struct intel_plane
*plane
;
14766 drm_crtc_vblank_on(&crtc
->base
);
14768 /* Disable everything but the primary plane */
14769 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
14770 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
14773 trace_intel_disable_plane(&plane
->base
, crtc
);
14774 plane
->disable_plane(plane
, crtc
);
14778 /* We need to sanitize the plane -> pipe mapping first because this will
14779 * disable the crtc (and hence change the state) if it is wrong. Note
14780 * that gen4+ has a fixed plane -> pipe mapping. */
14781 if (INTEL_GEN(dev_priv
) < 4 && !intel_check_plane_mapping(crtc
)) {
14784 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14785 crtc
->base
.base
.id
, crtc
->base
.name
);
14787 /* Pipe has the wrong plane attached and the plane is active.
14788 * Temporarily change the plane mapping and disable everything
14790 plane
= crtc
->plane
;
14791 crtc
->base
.primary
->state
->visible
= true;
14792 crtc
->plane
= !plane
;
14793 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
14794 crtc
->plane
= plane
;
14797 /* Adjust the state of the output pipe according to whether we
14798 * have active connectors/encoders. */
14799 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
14800 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
14802 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev_priv
)) {
14804 * We start out with underrun reporting disabled to avoid races.
14805 * For correct bookkeeping mark this on active crtcs.
14807 * Also on gmch platforms we dont have any hardware bits to
14808 * disable the underrun reporting. Which means we need to start
14809 * out with underrun reporting disabled also on inactive pipes,
14810 * since otherwise we'll complain about the garbage we read when
14811 * e.g. coming up after runtime pm.
14813 * No protection against concurrent access is required - at
14814 * worst a fifo underrun happens which also sets this to false.
14816 crtc
->cpu_fifo_underrun_disabled
= true;
14818 * We track the PCH trancoder underrun reporting state
14819 * within the crtc. With crtc for pipe A housing the underrun
14820 * reporting state for PCH transcoder A, crtc for pipe B housing
14821 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14822 * and marking underrun reporting as disabled for the non-existing
14823 * PCH transcoders B and C would prevent enabling the south
14824 * error interrupt (see cpt_can_enable_serr_int()).
14826 if (has_pch_trancoder(dev_priv
, (enum transcoder
)crtc
->pipe
))
14827 crtc
->pch_fifo_underrun_disabled
= true;
14831 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14833 struct intel_connector
*connector
;
14835 /* We need to check both for a crtc link (meaning that the
14836 * encoder is active and trying to read from a pipe) and the
14837 * pipe itself being active. */
14838 bool has_active_crtc
= encoder
->base
.crtc
&&
14839 to_intel_crtc(encoder
->base
.crtc
)->active
;
14841 connector
= intel_encoder_find_connector(encoder
);
14842 if (connector
&& !has_active_crtc
) {
14843 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14844 encoder
->base
.base
.id
,
14845 encoder
->base
.name
);
14847 /* Connector is active, but has no active pipe. This is
14848 * fallout from our resume register restoring. Disable
14849 * the encoder manually again. */
14850 if (encoder
->base
.crtc
) {
14851 struct drm_crtc_state
*crtc_state
= encoder
->base
.crtc
->state
;
14853 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14854 encoder
->base
.base
.id
,
14855 encoder
->base
.name
);
14856 encoder
->disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
14857 if (encoder
->post_disable
)
14858 encoder
->post_disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
14860 encoder
->base
.crtc
= NULL
;
14862 /* Inconsistent output/port/pipe state happens presumably due to
14863 * a bug in one of the get_hw_state functions. Or someplace else
14864 * in our code, like the register restore mess on resume. Clamp
14865 * things to off as a safer default. */
14867 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14868 connector
->base
.encoder
= NULL
;
14870 /* Enabled encoders without active connectors will be fixed in
14871 * the crtc fixup. */
14874 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
14876 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
14878 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14879 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14880 i915_disable_vga(dev_priv
);
14884 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
14886 /* This function can be called both from intel_modeset_setup_hw_state or
14887 * at a very early point in our resume sequence, where the power well
14888 * structures are not yet restored. Since this function is at a very
14889 * paranoid "someone might have enabled VGA while we were not looking"
14890 * level, just check if the power well is enabled instead of trying to
14891 * follow the "don't touch the power well if we don't need it" policy
14892 * the rest of the driver uses. */
14893 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14896 i915_redisable_vga_power_on(dev_priv
);
14898 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
14901 static bool primary_get_hw_state(struct intel_plane
*plane
)
14903 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
14905 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
14908 /* FIXME read out full plane state for all planes */
14909 static void readout_plane_state(struct intel_crtc
*crtc
)
14911 struct intel_plane
*primary
= to_intel_plane(crtc
->base
.primary
);
14914 visible
= crtc
->active
&& primary_get_hw_state(primary
);
14916 intel_set_plane_visible(to_intel_crtc_state(crtc
->base
.state
),
14917 to_intel_plane_state(primary
->base
.state
),
14921 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14923 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14925 struct intel_crtc
*crtc
;
14926 struct intel_encoder
*encoder
;
14927 struct intel_connector
*connector
;
14928 struct drm_connector_list_iter conn_iter
;
14931 dev_priv
->active_crtcs
= 0;
14933 for_each_intel_crtc(dev
, crtc
) {
14934 struct intel_crtc_state
*crtc_state
=
14935 to_intel_crtc_state(crtc
->base
.state
);
14937 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
14938 memset(crtc_state
, 0, sizeof(*crtc_state
));
14939 crtc_state
->base
.crtc
= &crtc
->base
;
14941 crtc_state
->base
.active
= crtc_state
->base
.enable
=
14942 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
14944 crtc
->base
.enabled
= crtc_state
->base
.enable
;
14945 crtc
->active
= crtc_state
->base
.active
;
14947 if (crtc_state
->base
.active
)
14948 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
14950 readout_plane_state(crtc
);
14952 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14953 crtc
->base
.base
.id
, crtc
->base
.name
,
14954 enableddisabled(crtc_state
->base
.active
));
14957 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14958 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14960 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
14961 &pll
->state
.hw_state
);
14962 pll
->state
.crtc_mask
= 0;
14963 for_each_intel_crtc(dev
, crtc
) {
14964 struct intel_crtc_state
*crtc_state
=
14965 to_intel_crtc_state(crtc
->base
.state
);
14967 if (crtc_state
->base
.active
&&
14968 crtc_state
->shared_dpll
== pll
)
14969 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
14971 pll
->active_mask
= pll
->state
.crtc_mask
;
14973 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14974 pll
->name
, pll
->state
.crtc_mask
, pll
->on
);
14977 for_each_intel_encoder(dev
, encoder
) {
14980 if (encoder
->get_hw_state(encoder
, &pipe
)) {
14981 struct intel_crtc_state
*crtc_state
;
14983 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
14984 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
14986 encoder
->base
.crtc
= &crtc
->base
;
14987 crtc_state
->output_types
|= 1 << encoder
->type
;
14988 encoder
->get_config(encoder
, crtc_state
);
14990 encoder
->base
.crtc
= NULL
;
14993 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14994 encoder
->base
.base
.id
, encoder
->base
.name
,
14995 enableddisabled(encoder
->base
.crtc
),
14999 drm_connector_list_iter_begin(dev
, &conn_iter
);
15000 for_each_intel_connector_iter(connector
, &conn_iter
) {
15001 if (connector
->get_hw_state(connector
)) {
15002 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15004 encoder
= connector
->encoder
;
15005 connector
->base
.encoder
= &encoder
->base
;
15007 if (encoder
->base
.crtc
&&
15008 encoder
->base
.crtc
->state
->active
) {
15010 * This has to be done during hardware readout
15011 * because anything calling .crtc_disable may
15012 * rely on the connector_mask being accurate.
15014 encoder
->base
.crtc
->state
->connector_mask
|=
15015 1 << drm_connector_index(&connector
->base
);
15016 encoder
->base
.crtc
->state
->encoder_mask
|=
15017 1 << drm_encoder_index(&encoder
->base
);
15021 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15022 connector
->base
.encoder
= NULL
;
15024 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15025 connector
->base
.base
.id
, connector
->base
.name
,
15026 enableddisabled(connector
->base
.encoder
));
15028 drm_connector_list_iter_end(&conn_iter
);
15030 for_each_intel_crtc(dev
, crtc
) {
15031 struct intel_crtc_state
*crtc_state
=
15032 to_intel_crtc_state(crtc
->base
.state
);
15035 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15036 if (crtc_state
->base
.active
) {
15037 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
15038 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
15039 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15042 * The initial mode needs to be set in order to keep
15043 * the atomic core happy. It wants a valid mode if the
15044 * crtc's enabled, so we do the above call.
15046 * But we don't set all the derived state fully, hence
15047 * set a flag to indicate that a full recalculation is
15048 * needed on the next commit.
15050 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15052 intel_crtc_compute_pixel_rate(crtc_state
);
15054 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
) ||
15055 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15056 pixclk
= crtc_state
->pixel_rate
;
15058 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
15060 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15061 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
15062 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
15064 drm_calc_timestamping_constants(&crtc
->base
,
15065 &crtc_state
->base
.adjusted_mode
);
15066 update_scanline_offset(crtc
);
15069 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
15071 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
15076 get_encoder_power_domains(struct drm_i915_private
*dev_priv
)
15078 struct intel_encoder
*encoder
;
15080 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15082 enum intel_display_power_domain domain
;
15084 if (!encoder
->get_power_domains
)
15087 get_domains
= encoder
->get_power_domains(encoder
);
15088 for_each_power_domain(domain
, get_domains
)
15089 intel_display_power_get(dev_priv
, domain
);
15093 /* Scan out the current hw modeset state,
15094 * and sanitizes it to the current state
15097 intel_modeset_setup_hw_state(struct drm_device
*dev
,
15098 struct drm_modeset_acquire_ctx
*ctx
)
15100 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15102 struct intel_crtc
*crtc
;
15103 struct intel_encoder
*encoder
;
15106 intel_modeset_readout_hw_state(dev
);
15108 /* HW state is read out, now we need to sanitize this mess. */
15109 get_encoder_power_domains(dev_priv
);
15111 for_each_intel_encoder(dev
, encoder
) {
15112 intel_sanitize_encoder(encoder
);
15115 for_each_pipe(dev_priv
, pipe
) {
15116 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15118 intel_sanitize_crtc(crtc
, ctx
);
15119 intel_dump_pipe_config(crtc
, crtc
->config
,
15120 "[setup_hw_state]");
15123 intel_modeset_update_connector_atomic_state(dev
);
15125 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15126 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15128 if (!pll
->on
|| pll
->active_mask
)
15131 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15133 pll
->funcs
.disable(dev_priv
, pll
);
15137 if (IS_G4X(dev_priv
)) {
15138 g4x_wm_get_hw_state(dev
);
15139 g4x_wm_sanitize(dev_priv
);
15140 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15141 vlv_wm_get_hw_state(dev
);
15142 vlv_wm_sanitize(dev_priv
);
15143 } else if (INTEL_GEN(dev_priv
) >= 9) {
15144 skl_wm_get_hw_state(dev
);
15145 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15146 ilk_wm_get_hw_state(dev
);
15149 for_each_intel_crtc(dev
, crtc
) {
15152 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
15153 if (WARN_ON(put_domains
))
15154 modeset_put_power_domains(dev_priv
, put_domains
);
15156 intel_display_set_init_power(dev_priv
, false);
15158 intel_power_domains_verify_state(dev_priv
);
15160 intel_fbc_init_pipe_state(dev_priv
);
15163 void intel_display_resume(struct drm_device
*dev
)
15165 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15166 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
15167 struct drm_modeset_acquire_ctx ctx
;
15170 dev_priv
->modeset_restore_state
= NULL
;
15172 state
->acquire_ctx
= &ctx
;
15174 drm_modeset_acquire_init(&ctx
, 0);
15177 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15178 if (ret
!= -EDEADLK
)
15181 drm_modeset_backoff(&ctx
);
15185 ret
= __intel_display_resume(dev
, state
, &ctx
);
15187 drm_modeset_drop_locks(&ctx
);
15188 drm_modeset_acquire_fini(&ctx
);
15191 DRM_ERROR("Restoring old state failed with %i\n", ret
);
15193 drm_atomic_state_put(state
);
15196 void intel_modeset_gem_init(struct drm_device
*dev
)
15198 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15200 intel_init_gt_powersave(dev_priv
);
15202 intel_setup_overlay(dev_priv
);
15205 int intel_connector_register(struct drm_connector
*connector
)
15207 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
15210 ret
= intel_backlight_device_register(intel_connector
);
15220 void intel_connector_unregister(struct drm_connector
*connector
)
15222 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
15224 intel_backlight_device_unregister(intel_connector
);
15225 intel_panel_destroy_backlight(connector
);
15228 void intel_modeset_cleanup(struct drm_device
*dev
)
15230 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15232 flush_work(&dev_priv
->atomic_helper
.free_work
);
15233 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
15235 intel_disable_gt_powersave(dev_priv
);
15238 * Interrupts and polling as the first thing to avoid creating havoc.
15239 * Too much stuff here (turning of connectors, ...) would
15240 * experience fancy races otherwise.
15242 intel_irq_uninstall(dev_priv
);
15245 * Due to the hpd irq storm handling the hotplug work can re-arm the
15246 * poll handlers. Hence disable polling after hpd handling is shut down.
15248 drm_kms_helper_poll_fini(dev
);
15250 /* poll work can call into fbdev, hence clean that up afterwards */
15251 intel_fbdev_fini(dev_priv
);
15253 intel_unregister_dsm_handler();
15255 intel_fbc_global_disable(dev_priv
);
15257 /* flush any delayed tasks or pending work */
15258 flush_scheduled_work();
15260 drm_mode_config_cleanup(dev
);
15262 intel_cleanup_overlay(dev_priv
);
15264 intel_cleanup_gt_powersave(dev_priv
);
15266 intel_teardown_gmbus(dev_priv
);
15269 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15270 struct intel_encoder
*encoder
)
15272 connector
->encoder
= encoder
;
15273 drm_mode_connector_attach_encoder(&connector
->base
,
15278 * set vga decode state - true == enable VGA decode
15280 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
15282 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15285 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15286 DRM_ERROR("failed to read control word\n");
15290 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15294 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15296 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15298 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15299 DRM_ERROR("failed to write control word\n");
15306 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15308 struct intel_display_error_state
{
15310 u32 power_well_driver
;
15312 int num_transcoders
;
15314 struct intel_cursor_error_state
{
15319 } cursor
[I915_MAX_PIPES
];
15321 struct intel_pipe_error_state
{
15322 bool power_domain_on
;
15325 } pipe
[I915_MAX_PIPES
];
15327 struct intel_plane_error_state
{
15335 } plane
[I915_MAX_PIPES
];
15337 struct intel_transcoder_error_state
{
15338 bool power_domain_on
;
15339 enum transcoder cpu_transcoder
;
15352 struct intel_display_error_state
*
15353 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
15355 struct intel_display_error_state
*error
;
15356 int transcoders
[] = {
15364 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
15367 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15371 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
15372 error
->power_well_driver
=
15373 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL
));
15375 for_each_pipe(dev_priv
, i
) {
15376 error
->pipe
[i
].power_domain_on
=
15377 __intel_display_power_is_enabled(dev_priv
,
15378 POWER_DOMAIN_PIPE(i
));
15379 if (!error
->pipe
[i
].power_domain_on
)
15382 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15383 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15384 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15386 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15387 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15388 if (INTEL_GEN(dev_priv
) <= 3) {
15389 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15390 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15392 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
15393 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15394 if (INTEL_GEN(dev_priv
) >= 4) {
15395 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15396 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15399 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15401 if (HAS_GMCH_DISPLAY(dev_priv
))
15402 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15405 /* Note: this does not include DSI transcoders. */
15406 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
15407 if (HAS_DDI(dev_priv
))
15408 error
->num_transcoders
++; /* Account for eDP. */
15410 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15411 enum transcoder cpu_transcoder
= transcoders
[i
];
15413 error
->transcoder
[i
].power_domain_on
=
15414 __intel_display_power_is_enabled(dev_priv
,
15415 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15416 if (!error
->transcoder
[i
].power_domain_on
)
15419 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15421 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15422 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15423 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15424 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15425 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15426 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15427 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15433 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15436 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15437 struct intel_display_error_state
*error
)
15439 struct drm_i915_private
*dev_priv
= m
->i915
;
15445 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
15446 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
15447 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15448 error
->power_well_driver
);
15449 for_each_pipe(dev_priv
, i
) {
15450 err_printf(m
, "Pipe [%d]:\n", i
);
15451 err_printf(m
, " Power: %s\n",
15452 onoff(error
->pipe
[i
].power_domain_on
));
15453 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15454 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15456 err_printf(m
, "Plane [%d]:\n", i
);
15457 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15458 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15459 if (INTEL_GEN(dev_priv
) <= 3) {
15460 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15461 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15463 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
15464 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15465 if (INTEL_GEN(dev_priv
) >= 4) {
15466 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15467 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15470 err_printf(m
, "Cursor [%d]:\n", i
);
15471 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15472 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15473 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15476 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15477 err_printf(m
, "CPU transcoder: %s\n",
15478 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15479 err_printf(m
, " Power: %s\n",
15480 onoff(error
->transcoder
[i
].power_domain_on
));
15481 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15482 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15483 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15484 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15485 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15486 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15487 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);