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Merge tag 'drm-intel-next-2015-05-22' of git://anongit.freedesktop.org/drm-intel...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_crtc *crtc,
90 struct drm_atomic_state *state);
91 static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
100 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
101 static void haswell_set_pipeconf(struct drm_crtc *crtc);
102 static void intel_set_pipe_csc(struct drm_crtc *crtc);
103 static void vlv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void chv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
109 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
111 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
113 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
115
116 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117 {
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122 }
123
124 typedef struct {
125 int min, max;
126 } intel_range_t;
127
128 typedef struct {
129 int dot_limit;
130 int p2_slow, p2_fast;
131 } intel_p2_t;
132
133 typedef struct intel_limit intel_limit_t;
134 struct intel_limit {
135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
137 };
138
139 int
140 intel_pch_rawclk(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147 }
148
149 static inline u32 /* units of 100MHz */
150 intel_fdi_link_freq(struct drm_device *dev)
151 {
152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
157 }
158
159 static const intel_limit_t intel_limits_i8xx_dac = {
160 .dot = { .min = 25000, .max = 350000 },
161 .vco = { .min = 908000, .max = 1512000 },
162 .n = { .min = 2, .max = 16 },
163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
170 };
171
172 static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
174 .vco = { .min = 908000, .max = 1512000 },
175 .n = { .min = 2, .max = 16 },
176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183 };
184
185 static const intel_limit_t intel_limits_i8xx_lvds = {
186 .dot = { .min = 25000, .max = 350000 },
187 .vco = { .min = 908000, .max = 1512000 },
188 .n = { .min = 2, .max = 16 },
189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
196 };
197
198 static const intel_limit_t intel_limits_i9xx_sdvo = {
199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_i9xx_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
222 };
223
224
225 static const intel_limit_t intel_limits_g4x_sdvo = {
226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
237 },
238 };
239
240 static const intel_limit_t intel_limits_g4x_hdmi = {
241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
264 },
265 };
266
267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
278 },
279 };
280
281 static const intel_limit_t intel_limits_pineview_sdvo = {
282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
284 /* Pineview's Ncounter is a ring counter */
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 /* Pineview only has one combined m divider, which we treat as m2. */
288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
294 };
295
296 static const intel_limit_t intel_limits_pineview_lvds = {
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
307 };
308
309 /* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
314 static const intel_limit_t intel_limits_ironlake_dac = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
325 };
326
327 static const intel_limit_t intel_limits_ironlake_single_lvds = {
328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
338 };
339
340 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
351 };
352
353 /* LVDS 100mhz refclk limits. */
354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
362 .p1 = { .min = 2, .max = 8 },
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
365 };
366
367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
375 .p1 = { .min = 2, .max = 6 },
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
378 };
379
380 static const intel_limit_t intel_limits_vlv = {
381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
388 .vco = { .min = 4000000, .max = 6000000 },
389 .n = { .min = 1, .max = 7 },
390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
392 .p1 = { .min = 2, .max = 3 },
393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
394 };
395
396 static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
404 .vco = { .min = 4800000, .max = 6480000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410 };
411
412 static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422 };
423
424 static void vlv_clock(int refclk, intel_clock_t *clock)
425 {
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
432 }
433
434 /**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
437 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
438 {
439 struct drm_device *dev = crtc->base.dev;
440 struct intel_encoder *encoder;
441
442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
443 if (encoder->type == type)
444 return true;
445
446 return false;
447 }
448
449 /**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
455 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
457 {
458 struct drm_atomic_state *state = crtc_state->base.state;
459 struct drm_connector *connector;
460 struct drm_connector_state *connector_state;
461 struct intel_encoder *encoder;
462 int i, num_connectors = 0;
463
464 for_each_connector_in_state(state, connector, connector_state, i) {
465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
469
470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
472 return true;
473 }
474
475 WARN_ON(num_connectors == 0);
476
477 return false;
478 }
479
480 static const intel_limit_t *
481 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
482 {
483 struct drm_device *dev = crtc_state->base.crtc->dev;
484 const intel_limit_t *limit;
485
486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
487 if (intel_is_dual_link_lvds(dev)) {
488 if (refclk == 100000)
489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
498 } else
499 limit = &intel_limits_ironlake_dac;
500
501 return limit;
502 }
503
504 static const intel_limit_t *
505 intel_g4x_limit(struct intel_crtc_state *crtc_state)
506 {
507 struct drm_device *dev = crtc_state->base.crtc->dev;
508 const intel_limit_t *limit;
509
510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
511 if (intel_is_dual_link_lvds(dev))
512 limit = &intel_limits_g4x_dual_channel_lvds;
513 else
514 limit = &intel_limits_g4x_single_channel_lvds;
515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
517 limit = &intel_limits_g4x_hdmi;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
519 limit = &intel_limits_g4x_sdvo;
520 } else /* The option is for other outputs */
521 limit = &intel_limits_i9xx_sdvo;
522
523 return limit;
524 }
525
526 static const intel_limit_t *
527 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
528 {
529 struct drm_device *dev = crtc_state->base.crtc->dev;
530 const intel_limit_t *limit;
531
532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
535 limit = intel_ironlake_limit(crtc_state, refclk);
536 else if (IS_G4X(dev)) {
537 limit = intel_g4x_limit(crtc_state);
538 } else if (IS_PINEVIEW(dev)) {
539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
540 limit = &intel_limits_pineview_lvds;
541 else
542 limit = &intel_limits_pineview_sdvo;
543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
545 } else if (IS_VALLEYVIEW(dev)) {
546 limit = &intel_limits_vlv;
547 } else if (!IS_GEN2(dev)) {
548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
552 } else {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i8xx_lvds;
555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
556 limit = &intel_limits_i8xx_dvo;
557 else
558 limit = &intel_limits_i8xx_dac;
559 }
560 return limit;
561 }
562
563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
564 static void pineview_clock(int refclk, intel_clock_t *clock)
565 {
566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
572 }
573
574 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575 {
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577 }
578
579 static void i9xx_clock(int refclk, intel_clock_t *clock)
580 {
581 clock->m = i9xx_dpll_compute_m(clock);
582 clock->p = clock->p1 * clock->p2;
583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 }
588
589 static void chv_clock(int refclk, intel_clock_t *clock)
590 {
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598 }
599
600 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
601 /**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
606 static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
609 {
610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid("p1 out of range\n");
614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
615 INTELPllInvalid("m2 out of range\n");
616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
617 INTELPllInvalid("m1 out of range\n");
618
619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
636 INTELPllInvalid("dot out of range\n");
637
638 return true;
639 }
640
641 static bool
642 i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
646 {
647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
648 struct drm_device *dev = crtc->base.dev;
649 intel_clock_t clock;
650 int err = target;
651
652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
653 /*
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
657 */
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
669 memset(best_clock, 0, sizeof(*best_clock));
670
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 if (clock.m2 >= clock.m1)
676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
681 int this_err;
682
683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702 }
703
704 static bool
705 pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
709 {
710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
711 struct drm_device *dev = crtc->base.dev;
712 intel_clock_t clock;
713 int err = target;
714
715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
716 /*
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
720 */
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
742 int this_err;
743
744 pineview_clock(refclk, &clock);
745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
747 continue;
748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763 }
764
765 static bool
766 g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
770 {
771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
772 struct drm_device *dev = crtc->base.dev;
773 intel_clock_t clock;
774 int max_n;
775 bool found;
776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
778 found = false;
779
780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
781 if (intel_is_dual_link_lvds(dev))
782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 /* based on hardware requirement, prefere larger m1,m2 */
797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
805 i9xx_clock(refclk, &clock);
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 this_err = abs(clock.dot - target);
811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
821 return found;
822 }
823
824 /*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833 {
834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862 }
863
864 static bool
865 vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
869 {
870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
871 struct drm_device *dev = crtc->base.dev;
872 intel_clock_t clock;
873 unsigned int bestppm = 1000000;
874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
876 bool found = false;
877
878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
881
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
887 clock.p = clock.p1 * clock.p2;
888 /* based on hardware requirement, prefer bigger m1,m2 values */
889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
890 unsigned int ppm;
891
892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
896
897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
899 continue;
900
901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
906
907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
910 }
911 }
912 }
913 }
914
915 return found;
916 }
917
918 static bool
919 chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923 {
924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
925 struct drm_device *dev = crtc->base.dev;
926 unsigned int best_error_ppm;
927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
932 best_error_ppm = 1000000;
933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
946 unsigned int error_ppm;
947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
970 }
971 }
972
973 return found;
974 }
975
976 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978 {
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983 }
984
985 bool intel_crtc_active(struct drm_crtc *crtc)
986 {
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
992 * We can ditch the adjusted_mode.crtc_clock check as soon
993 * as Haswell has gained clock readout/fastboot support.
994 *
995 * We can ditch the crtc->primary->fb check as soon as we can
996 * properly reconstruct framebuffers.
997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
1001 */
1002 return intel_crtc->active && crtc->primary->state->fb &&
1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
1004 }
1005
1006 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008 {
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
1012 return intel_crtc->config->cpu_transcoder;
1013 }
1014
1015 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016 {
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032 }
1033
1034 /*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
1036 * @crtc: crtc whose pipe to wait for
1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
1048 *
1049 */
1050 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1051 {
1052 struct drm_device *dev = crtc->base.dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1055 enum pipe pipe = crtc->pipe;
1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
1058 int reg = PIPECONF(cpu_transcoder);
1059
1060 /* Wait for the Pipe State to go off */
1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 } else {
1065 /* Wait for the display line to settle */
1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1067 WARN(1, "pipe_off wait timed out\n");
1068 }
1069 }
1070
1071 /*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080 {
1081 u32 bit;
1082
1083 if (HAS_PCH_IBX(dev_priv->dev)) {
1084 switch (port->port) {
1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
1098 switch (port->port) {
1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114 }
1115
1116 static const char *state_string(bool enabled)
1117 {
1118 return enabled ? "on" : "off";
1119 }
1120
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
1124 {
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
1132 I915_STATE_WARN(cur_state != state,
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135 }
1136
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139 {
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->dpio_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
1148 I915_STATE_WARN(cur_state != state,
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
1155 struct intel_shared_dpll *
1156 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157 {
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
1160 if (crtc->config->shared_dpll < 0)
1161 return NULL;
1162
1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1164 }
1165
1166 /* For ILK+ */
1167 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
1170 {
1171 bool cur_state;
1172 struct intel_dpll_hw_state hw_state;
1173
1174 if (WARN (!pll,
1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
1176 return;
1177
1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1179 I915_STATE_WARN(cur_state != state,
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186 {
1187 int reg;
1188 u32 val;
1189 bool cur_state;
1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
1192
1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206 }
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212 {
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
1220 I915_STATE_WARN(cur_state != state,
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223 }
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229 {
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1235 return;
1236
1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238 if (HAS_DDI(dev_priv->dev))
1239 return;
1240
1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1244 }
1245
1246 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
1259 }
1260
1261 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
1263 {
1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
1268 bool locked = true;
1269
1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
1276 pp_reg = PCH_PP_CONTROL;
1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
1287 } else {
1288 pp_reg = PP_CONTROL;
1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1296 locked = false;
1297
1298 I915_STATE_WARN(panel_pipe == pipe && locked,
1299 "panel assertion failure, pipe %c regs locked\n",
1300 pipe_name(pipe));
1301 }
1302
1303 static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305 {
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
1309 if (IS_845G(dev) || IS_I865G(dev))
1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1311 else
1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1313
1314 I915_STATE_WARN(cur_state != state,
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317 }
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
1321 void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
1323 {
1324 int reg;
1325 u32 val;
1326 bool cur_state;
1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
1329
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1333 state = true;
1334
1335 if (!intel_display_power_is_enabled(dev_priv,
1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
1344 I915_STATE_WARN(cur_state != state,
1345 "pipe %c assertion failure (expected %s, current %s)\n",
1346 pipe_name(pipe), state_string(state), state_string(cur_state));
1347 }
1348
1349 static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
1351 {
1352 int reg;
1353 u32 val;
1354 bool cur_state;
1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1359 I915_STATE_WARN(cur_state != state,
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
1362 }
1363
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
1367 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369 {
1370 struct drm_device *dev = dev_priv->dev;
1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
1382 return;
1383 }
1384
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv, i) {
1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 struct drm_device *dev = dev_priv->dev;
1401 int reg, sprite;
1402 u32 val;
1403
1404 if (INTEL_INFO(dev)->gen >= 9) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 val = I915_READ(PLANE_CTL(pipe, sprite));
1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
1412 for_each_sprite(dev_priv, pipe, sprite) {
1413 reg = SPCNTR(pipe, sprite);
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SP_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 sprite_name(pipe, sprite), pipe_name(pipe));
1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
1421 val = I915_READ(reg);
1422 I915_STATE_WARN(val & SPRITE_ENABLE,
1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
1427 val = I915_READ(reg);
1428 I915_STATE_WARN(val & DVS_ENABLE,
1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430 plane_name(pipe), pipe_name(pipe));
1431 }
1432 }
1433
1434 static void assert_vblank_disabled(struct drm_crtc *crtc)
1435 {
1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1437 drm_crtc_vblank_put(crtc);
1438 }
1439
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1441 {
1442 u32 val;
1443 bool enabled;
1444
1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1446
1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1451 }
1452
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
1455 {
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
1460 reg = PCH_TRANSCONF(pipe);
1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
1463 I915_STATE_WARN(enabled,
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
1466 }
1467
1468 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
1470 {
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487 }
1488
1489 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491 {
1492 if ((val & SDVO_ENABLE) == 0)
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1497 return false;
1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1501 } else {
1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1503 return false;
1504 }
1505 return true;
1506 }
1507
1508 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510 {
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526 {
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537 }
1538
1539 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1540 enum pipe pipe, int reg, u32 port_sel)
1541 {
1542 u32 val = I915_READ(reg);
1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545 reg, pipe_name(pipe));
1546
1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1548 && (val & DP_PIPEB_SELECT),
1549 "IBX PCH dp port still using transcoder B\n");
1550 }
1551
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554 {
1555 u32 val = I915_READ(reg);
1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558 reg, pipe_name(pipe));
1559
1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1561 && (val & SDVO_PIPE_B_SELECT),
1562 "IBX PCH hdmi port still using transcoder B\n");
1563 }
1564
1565 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567 {
1568 int reg;
1569 u32 val;
1570
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
1579 pipe_name(pipe));
1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1590 }
1591
1592 static void intel_init_dpio(struct drm_device *dev)
1593 {
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
1610 }
1611
1612 static void vlv_enable_pll(struct intel_crtc *crtc,
1613 const struct intel_crtc_state *pipe_config)
1614 {
1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
1619
1620 assert_pipe_disabled(dev_priv, crtc->pipe);
1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
1626 if (IS_MOBILE(dev_priv->dev))
1627 assert_panel_unlocked(dev_priv, crtc->pipe);
1628
1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1637 POSTING_READ(DPLL_MD(crtc->pipe));
1638
1639 /* We do this three times for luck */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 }
1650
1651 static void chv_enable_pll(struct intel_crtc *crtc,
1652 const struct intel_crtc_state *pipe_config)
1653 {
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->dpio_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1678
1679 /* Check PLL is locked */
1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
1683 /* not sure when this should be written */
1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1685 POSTING_READ(DPLL_MD(pipe));
1686
1687 mutex_unlock(&dev_priv->dpio_lock);
1688 }
1689
1690 static int intel_num_dvo_pipes(struct drm_device *dev)
1691 {
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1698
1699 return count;
1700 }
1701
1702 static void i9xx_enable_pll(struct intel_crtc *crtc)
1703 {
1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
1708
1709 assert_pipe_disabled(dev_priv, crtc->pipe);
1710
1711 /* No really, not for ILK+ */
1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1713
1714 /* PLL is protected by panel, make sure we can write it */
1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
1717
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
1737 crtc->config->dpll_hw_state.dpll_md);
1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
1746
1747 /* We do this three times for luck */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg, dpll);
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg, dpll);
1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757 }
1758
1759 /**
1760 * i9xx_disable_pll - disable a PLL
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1768 static void i9xx_disable_pll(struct intel_crtc *crtc)
1769 {
1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
1794 }
1795
1796 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797 {
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
1807 if (pipe == PIPE_B)
1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
1811
1812 }
1813
1814 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815 {
1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1817 u32 val;
1818
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
1821
1822 /* Set PLL en = 0 */
1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
1828
1829 mutex_lock(&dev_priv->dpio_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
1847 mutex_unlock(&dev_priv->dpio_lock);
1848 }
1849
1850 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
1853 {
1854 u32 port_mask;
1855 int dpll_reg;
1856
1857 switch (dport->port) {
1858 case PORT_B:
1859 port_mask = DPLL_PORTB_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_C:
1863 port_mask = DPLL_PORTC_READY_MASK;
1864 dpll_reg = DPLL(0);
1865 expected_mask <<= 4;
1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
1870 break;
1871 default:
1872 BUG();
1873 }
1874
1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878 }
1879
1880 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881 {
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
1889 WARN_ON(!pll->config.crtc_mask);
1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897 }
1898
1899 /**
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
1907 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1908 {
1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1912
1913 if (WARN_ON(pll == NULL))
1914 return;
1915
1916 if (WARN_ON(pll->config.crtc_mask == 0))
1917 return;
1918
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll->name, pll->active, pll->on,
1921 crtc->base.base.id);
1922
1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
1925 assert_shared_dpll_enabled(dev_priv, pll);
1926 return;
1927 }
1928 WARN_ON(pll->on);
1929
1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1933 pll->enable(dev_priv, pll);
1934 pll->on = true;
1935 }
1936
1937 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1938 {
1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1942
1943 /* PCH only available on ILK+ */
1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
1945 if (WARN_ON(pll == NULL))
1946 return;
1947
1948 if (WARN_ON(pll->config.crtc_mask == 0))
1949 return;
1950
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
1953 crtc->base.base.id);
1954
1955 if (WARN_ON(pll->active == 0)) {
1956 assert_shared_dpll_disabled(dev_priv, pll);
1957 return;
1958 }
1959
1960 assert_shared_dpll_enabled(dev_priv, pll);
1961 WARN_ON(!pll->on);
1962 if (--pll->active)
1963 return;
1964
1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966 pll->disable(dev_priv, pll);
1967 pll->on = false;
1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970 }
1971
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
1974 {
1975 struct drm_device *dev = dev_priv->dev;
1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 uint32_t reg, val, pipeconf_val;
1979
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv,
1985 intel_crtc_to_shared_dpll(intel_crtc));
1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
1998 }
1999
2000 reg = PCH_TRANSCONF(pipe);
2001 val = I915_READ(reg);
2002 pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
2011 }
2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2015 if (HAS_PCH_IBX(dev_priv->dev) &&
2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2026 }
2027
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum transcoder cpu_transcoder)
2030 {
2031 u32 val, pipeconf_val;
2032
2033 /* PCH only available on ILK+ */
2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035
2036 /* FDI must be feeding us bits for PCH ports */
2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039
2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
2045 val = TRANS_ENABLE;
2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047
2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
2050 val |= TRANS_INTERLACED;
2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2056 DRM_ERROR("Failed to enable PCH transcoder\n");
2057 }
2058
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061 {
2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
2072 reg = PCH_TRANSCONF(pipe);
2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
2087 }
2088
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2090 {
2091 u32 val;
2092
2093 val = I915_READ(LPT_TRANSCONF);
2094 val &= ~TRANS_ENABLE;
2095 I915_WRITE(LPT_TRANSCONF, val);
2096 /* wait for PCH transcoder off, transcoder state */
2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2098 DRM_ERROR("Failed to disable PCH transcoder\n");
2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2103 I915_WRITE(_TRANSA_CHICKEN2, val);
2104 }
2105
2106 /**
2107 * intel_enable_pipe - enable a pipe, asserting requirements
2108 * @crtc: crtc responsible for the pipe
2109 *
2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112 */
2113 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 {
2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
2120 enum pipe pch_transcoder;
2121 int reg;
2122 u32 val;
2123
2124 assert_planes_disabled(dev_priv, pipe);
2125 assert_cursor_disabled(dev_priv, pipe);
2126 assert_sprites_disabled(dev_priv, pipe);
2127
2128 if (HAS_PCH_LPT(dev_priv->dev))
2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
2143 else {
2144 if (crtc->config->has_pch_encoder) {
2145 /* if driving the PCH, we need FDI enabled */
2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
2152
2153 reg = PIPECONF(cpu_transcoder);
2154 val = I915_READ(reg);
2155 if (val & PIPECONF_ENABLE) {
2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2158 return;
2159 }
2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
2162 POSTING_READ(reg);
2163 }
2164
2165 /**
2166 * intel_disable_pipe - disable a pipe, asserting requirements
2167 * @crtc: crtc whose pipes is to be disabled
2168 *
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
2175 static void intel_disable_pipe(struct intel_crtc *crtc)
2176 {
2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2179 enum pipe pipe = crtc->pipe;
2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
2188 assert_cursor_disabled(dev_priv, pipe);
2189 assert_sprites_disabled(dev_priv, pipe);
2190
2191 reg = PIPECONF(cpu_transcoder);
2192 val = I915_READ(reg);
2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
2200 if (crtc->config->double_wide)
2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
2211 }
2212
2213 /*
2214 * Plane regs are double buffered, going from enabled->disabled needs a
2215 * trigger in order to latch. The display address reg provides this.
2216 */
2217 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2218 enum plane plane)
2219 {
2220 struct drm_device *dev = dev_priv->dev;
2221 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2222
2223 I915_WRITE(reg, I915_READ(reg));
2224 POSTING_READ(reg);
2225 }
2226
2227 /**
2228 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2229 * @plane: plane to be enabled
2230 * @crtc: crtc for the plane
2231 *
2232 * Enable @plane on @crtc, making sure that the pipe is running first.
2233 */
2234 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2235 struct drm_crtc *crtc)
2236 {
2237 struct drm_device *dev = plane->dev;
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2240
2241 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2242 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2243 to_intel_plane_state(plane->state)->visible = true;
2244
2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
2247 }
2248
2249 static bool need_vtd_wa(struct drm_device *dev)
2250 {
2251 #ifdef CONFIG_INTEL_IOMMU
2252 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2253 return true;
2254 #endif
2255 return false;
2256 }
2257
2258 unsigned int
2259 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2260 uint64_t fb_format_modifier)
2261 {
2262 unsigned int tile_height;
2263 uint32_t pixel_bytes;
2264
2265 switch (fb_format_modifier) {
2266 case DRM_FORMAT_MOD_NONE:
2267 tile_height = 1;
2268 break;
2269 case I915_FORMAT_MOD_X_TILED:
2270 tile_height = IS_GEN2(dev) ? 16 : 8;
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 tile_height = 32;
2274 break;
2275 case I915_FORMAT_MOD_Yf_TILED:
2276 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2277 switch (pixel_bytes) {
2278 default:
2279 case 1:
2280 tile_height = 64;
2281 break;
2282 case 2:
2283 case 4:
2284 tile_height = 32;
2285 break;
2286 case 8:
2287 tile_height = 16;
2288 break;
2289 case 16:
2290 WARN_ONCE(1,
2291 "128-bit pixels are not supported for display!");
2292 tile_height = 16;
2293 break;
2294 }
2295 break;
2296 default:
2297 MISSING_CASE(fb_format_modifier);
2298 tile_height = 1;
2299 break;
2300 }
2301
2302 return tile_height;
2303 }
2304
2305 unsigned int
2306 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2307 uint32_t pixel_format, uint64_t fb_format_modifier)
2308 {
2309 return ALIGN(height, intel_tile_height(dev, pixel_format,
2310 fb_format_modifier));
2311 }
2312
2313 static int
2314 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2315 const struct drm_plane_state *plane_state)
2316 {
2317 struct intel_rotation_info *info = &view->rotation_info;
2318
2319 *view = i915_ggtt_view_normal;
2320
2321 if (!plane_state)
2322 return 0;
2323
2324 if (!intel_rotation_90_or_270(plane_state->rotation))
2325 return 0;
2326
2327 *view = i915_ggtt_view_rotated;
2328
2329 info->height = fb->height;
2330 info->pixel_format = fb->pixel_format;
2331 info->pitch = fb->pitches[0];
2332 info->fb_modifier = fb->modifier[0];
2333
2334 return 0;
2335 }
2336
2337 int
2338 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2339 struct drm_framebuffer *fb,
2340 const struct drm_plane_state *plane_state,
2341 struct intel_engine_cs *pipelined)
2342 {
2343 struct drm_device *dev = fb->dev;
2344 struct drm_i915_private *dev_priv = dev->dev_private;
2345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2346 struct i915_ggtt_view view;
2347 u32 alignment;
2348 int ret;
2349
2350 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2351
2352 switch (fb->modifier[0]) {
2353 case DRM_FORMAT_MOD_NONE:
2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2357 alignment = 128 * 1024;
2358 else if (INTEL_INFO(dev)->gen >= 4)
2359 alignment = 4 * 1024;
2360 else
2361 alignment = 64 * 1024;
2362 break;
2363 case I915_FORMAT_MOD_X_TILED:
2364 if (INTEL_INFO(dev)->gen >= 9)
2365 alignment = 256 * 1024;
2366 else {
2367 /* pin() will align the object as required by fence */
2368 alignment = 0;
2369 }
2370 break;
2371 case I915_FORMAT_MOD_Y_TILED:
2372 case I915_FORMAT_MOD_Yf_TILED:
2373 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2374 "Y tiling bo slipped through, driver bug!\n"))
2375 return -EINVAL;
2376 alignment = 1 * 1024 * 1024;
2377 break;
2378 default:
2379 MISSING_CASE(fb->modifier[0]);
2380 return -EINVAL;
2381 }
2382
2383 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2384 if (ret)
2385 return ret;
2386
2387 /* Note that the w/a also requires 64 PTE of padding following the
2388 * bo. We currently fill all unused PTE with the shadow page and so
2389 * we should always have valid PTE following the scanout preventing
2390 * the VT-d warning.
2391 */
2392 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2393 alignment = 256 * 1024;
2394
2395 /*
2396 * Global gtt pte registers are special registers which actually forward
2397 * writes to a chunk of system memory. Which means that there is no risk
2398 * that the register values disappear as soon as we call
2399 * intel_runtime_pm_put(), so it is correct to wrap only the
2400 * pin/unpin/fence and not more.
2401 */
2402 intel_runtime_pm_get(dev_priv);
2403
2404 dev_priv->mm.interruptible = false;
2405 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2406 &view);
2407 if (ret)
2408 goto err_interruptible;
2409
2410 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2411 * fence, whereas 965+ only requires a fence if using
2412 * framebuffer compression. For simplicity, we always install
2413 * a fence as the cost is not that onerous.
2414 */
2415 ret = i915_gem_object_get_fence(obj);
2416 if (ret)
2417 goto err_unpin;
2418
2419 i915_gem_object_pin_fence(obj);
2420
2421 dev_priv->mm.interruptible = true;
2422 intel_runtime_pm_put(dev_priv);
2423 return 0;
2424
2425 err_unpin:
2426 i915_gem_object_unpin_from_display_plane(obj, &view);
2427 err_interruptible:
2428 dev_priv->mm.interruptible = true;
2429 intel_runtime_pm_put(dev_priv);
2430 return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
2435 {
2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437 struct i915_ggtt_view view;
2438 int ret;
2439
2440 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
2442 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443 WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
2445 i915_gem_object_unpin_fence(obj);
2446 i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
2451 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2452 unsigned int tiling_mode,
2453 unsigned int cpp,
2454 unsigned int pitch)
2455 {
2456 if (tiling_mode != I915_TILING_NONE) {
2457 unsigned int tile_rows, tiles;
2458
2459 tile_rows = *y / 8;
2460 *y %= 8;
2461
2462 tiles = *x / (512/cpp);
2463 *x %= 512/cpp;
2464
2465 return tile_rows * pitch * 8 + tiles * 4096;
2466 } else {
2467 unsigned int offset;
2468
2469 offset = *y * pitch + *x * cpp;
2470 *y = 0;
2471 *x = (offset & 4095) / cpp;
2472 return offset & -4096;
2473 }
2474 }
2475
2476 static int i9xx_format_to_fourcc(int format)
2477 {
2478 switch (format) {
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2485 default:
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2494 }
2495 }
2496
2497 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498 {
2499 switch (format) {
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2502 default:
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2504 if (rgb_order) {
2505 if (alpha)
2506 return DRM_FORMAT_ABGR8888;
2507 else
2508 return DRM_FORMAT_XBGR8888;
2509 } else {
2510 if (alpha)
2511 return DRM_FORMAT_ARGB8888;
2512 else
2513 return DRM_FORMAT_XRGB8888;
2514 }
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2516 if (rgb_order)
2517 return DRM_FORMAT_XBGR2101010;
2518 else
2519 return DRM_FORMAT_XRGB2101010;
2520 }
2521 }
2522
2523 static bool
2524 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
2526 {
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530 struct drm_framebuffer *fb = &plane_config->fb->base;
2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533 PAGE_SIZE);
2534
2535 size_aligned -= base_aligned;
2536
2537 if (plane_config->size == 0)
2538 return false;
2539
2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
2544 if (!obj)
2545 return false;
2546
2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
2549 obj->stride = fb->pitches[0];
2550
2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558 mutex_lock(&dev->struct_mutex);
2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560 &mode_cmd, obj)) {
2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
2564 mutex_unlock(&dev->struct_mutex);
2565
2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567 return true;
2568
2569 out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
2572 return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
2592 {
2593 struct drm_device *dev = intel_crtc->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2597 struct drm_i915_gem_object *obj;
2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_framebuffer *fb;
2600
2601 if (!plane_config->fb)
2602 return;
2603
2604 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2605 fb = &plane_config->fb->base;
2606 goto valid_fb;
2607 }
2608
2609 kfree(plane_config->fb);
2610
2611 /*
2612 * Failed to alloc the obj, check to see if we should share
2613 * an fb with another CRTC instead
2614 */
2615 for_each_crtc(dev, c) {
2616 i = to_intel_crtc(c);
2617
2618 if (c == &intel_crtc->base)
2619 continue;
2620
2621 if (!i->active)
2622 continue;
2623
2624 fb = c->primary->fb;
2625 if (!fb)
2626 continue;
2627
2628 obj = intel_fb_obj(fb);
2629 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2630 drm_framebuffer_reference(fb);
2631 goto valid_fb;
2632 }
2633 }
2634
2635 return;
2636
2637 valid_fb:
2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
2642 primary->fb = fb;
2643 primary->state->crtc = &intel_crtc->base;
2644 primary->crtc = &intel_crtc->base;
2645 update_state_fb(primary);
2646 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2647 }
2648
2649 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
2652 {
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
2658 struct drm_i915_gem_object *obj;
2659 int plane = intel_crtc->plane;
2660 unsigned long linear_offset;
2661 u32 dspcntr;
2662 u32 reg = DSPCNTR(plane);
2663 int pixel_size;
2664
2665 if (!visible || !fb) {
2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
2683 dspcntr |= DISPLAY_PLANE_ENABLE;
2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
2695 I915_WRITE(DSPPOS(plane), 0);
2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2702 }
2703
2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
2708 case DRM_FORMAT_XRGB1555:
2709 dspcntr |= DISPPLANE_BGRX555;
2710 break;
2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 dspcntr |= DISPPLANE_RGBX101010;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
2733
2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
2738
2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742 pixel_size,
2743 fb->pitches[0]);
2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
2746 intel_crtc->dspaddr_offset = linear_offset;
2747 }
2748
2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765 if (INTEL_INFO(dev)->gen >= 4) {
2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770 } else
2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2772 POSTING_READ(reg);
2773 }
2774
2775 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
2778 {
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
2784 struct drm_i915_gem_object *obj;
2785 int plane = intel_crtc->plane;
2786 unsigned long linear_offset;
2787 u32 dspcntr;
2788 u32 reg = DSPCNTR(plane);
2789 int pixel_size;
2790
2791 if (!visible || !fb) {
2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
2806 dspcntr |= DISPLAY_PLANE_ENABLE;
2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2810
2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
2817 break;
2818 case DRM_FORMAT_XRGB8888:
2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
2822 dspcntr |= DISPPLANE_RGBX888;
2823 break;
2824 case DRM_FORMAT_XRGB2101010:
2825 dspcntr |= DISPPLANE_BGRX101010;
2826 break;
2827 case DRM_FORMAT_XBGR2101010:
2828 dspcntr |= DISPPLANE_RGBX101010;
2829 break;
2830 default:
2831 BUG();
2832 }
2833
2834 if (obj->tiling_mode != I915_TILING_NONE)
2835 dspcntr |= DISPPLANE_TILED;
2836
2837 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2838 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2839
2840 linear_offset = y * fb->pitches[0] + x * pixel_size;
2841 intel_crtc->dspaddr_offset =
2842 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2843 pixel_size,
2844 fb->pitches[0]);
2845 linear_offset -= intel_crtc->dspaddr_offset;
2846 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2847 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850 x += (intel_crtc->config->pipe_src_w - 1);
2851 y += (intel_crtc->config->pipe_src_h - 1);
2852
2853 /* Finding the last pixel of the last line of the display
2854 data and adding to linear_offset*/
2855 linear_offset +=
2856 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2857 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2858 }
2859 }
2860
2861 I915_WRITE(reg, dspcntr);
2862
2863 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2864 I915_WRITE(DSPSURF(plane),
2865 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2866 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2867 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2868 } else {
2869 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2870 I915_WRITE(DSPLINOFF(plane), linear_offset);
2871 }
2872 POSTING_READ(reg);
2873 }
2874
2875 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2876 uint32_t pixel_format)
2877 {
2878 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2879
2880 /*
2881 * The stride is either expressed as a multiple of 64 bytes
2882 * chunks for linear buffers or in number of tiles for tiled
2883 * buffers.
2884 */
2885 switch (fb_modifier) {
2886 case DRM_FORMAT_MOD_NONE:
2887 return 64;
2888 case I915_FORMAT_MOD_X_TILED:
2889 if (INTEL_INFO(dev)->gen == 2)
2890 return 128;
2891 return 512;
2892 case I915_FORMAT_MOD_Y_TILED:
2893 /* No need to check for old gens and Y tiling since this is
2894 * about the display engine and those will be blocked before
2895 * we get here.
2896 */
2897 return 128;
2898 case I915_FORMAT_MOD_Yf_TILED:
2899 if (bits_per_pixel == 8)
2900 return 64;
2901 else
2902 return 128;
2903 default:
2904 MISSING_CASE(fb_modifier);
2905 return 64;
2906 }
2907 }
2908
2909 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2910 struct drm_i915_gem_object *obj)
2911 {
2912 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2913
2914 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2915 view = &i915_ggtt_view_rotated;
2916
2917 return i915_gem_obj_ggtt_offset_view(obj, view);
2918 }
2919
2920 /*
2921 * This function detaches (aka. unbinds) unused scalers in hardware
2922 */
2923 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2924 {
2925 struct drm_device *dev;
2926 struct drm_i915_private *dev_priv;
2927 struct intel_crtc_scaler_state *scaler_state;
2928 int i;
2929
2930 if (!intel_crtc || !intel_crtc->config)
2931 return;
2932
2933 dev = intel_crtc->base.dev;
2934 dev_priv = dev->dev_private;
2935 scaler_state = &intel_crtc->config->scaler_state;
2936
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use) {
2940 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2941 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2942 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2943 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2944 intel_crtc->base.base.id, intel_crtc->pipe, i);
2945 }
2946 }
2947 }
2948
2949 u32 skl_plane_ctl_format(uint32_t pixel_format)
2950 {
2951 switch (pixel_format) {
2952 case DRM_FORMAT_C8:
2953 return PLANE_CTL_FORMAT_INDEXED;
2954 case DRM_FORMAT_RGB565:
2955 return PLANE_CTL_FORMAT_RGB_565;
2956 case DRM_FORMAT_XBGR8888:
2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2958 case DRM_FORMAT_XRGB8888:
2959 return PLANE_CTL_FORMAT_XRGB_8888;
2960 /*
2961 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2962 * to be already pre-multiplied. We need to add a knob (or a different
2963 * DRM_FORMAT) for user-space to configure that.
2964 */
2965 case DRM_FORMAT_ABGR8888:
2966 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2968 case DRM_FORMAT_ARGB8888:
2969 return PLANE_CTL_FORMAT_XRGB_8888 |
2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971 case DRM_FORMAT_XRGB2101010:
2972 return PLANE_CTL_FORMAT_XRGB_2101010;
2973 case DRM_FORMAT_XBGR2101010:
2974 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2975 case DRM_FORMAT_YUYV:
2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2977 case DRM_FORMAT_YVYU:
2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2979 case DRM_FORMAT_UYVY:
2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2981 case DRM_FORMAT_VYUY:
2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2983 default:
2984 MISSING_CASE(pixel_format);
2985 }
2986
2987 return 0;
2988 }
2989
2990 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2991 {
2992 switch (fb_modifier) {
2993 case DRM_FORMAT_MOD_NONE:
2994 break;
2995 case I915_FORMAT_MOD_X_TILED:
2996 return PLANE_CTL_TILED_X;
2997 case I915_FORMAT_MOD_Y_TILED:
2998 return PLANE_CTL_TILED_Y;
2999 case I915_FORMAT_MOD_Yf_TILED:
3000 return PLANE_CTL_TILED_YF;
3001 default:
3002 MISSING_CASE(fb_modifier);
3003 }
3004
3005 return 0;
3006 }
3007
3008 u32 skl_plane_ctl_rotation(unsigned int rotation)
3009 {
3010 switch (rotation) {
3011 case BIT(DRM_ROTATE_0):
3012 break;
3013 /*
3014 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3015 * while i915 HW rotation is clockwise, thats why this swapping.
3016 */
3017 case BIT(DRM_ROTATE_90):
3018 return PLANE_CTL_ROTATE_270;
3019 case BIT(DRM_ROTATE_180):
3020 return PLANE_CTL_ROTATE_180;
3021 case BIT(DRM_ROTATE_270):
3022 return PLANE_CTL_ROTATE_90;
3023 default:
3024 MISSING_CASE(rotation);
3025 }
3026
3027 return 0;
3028 }
3029
3030 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3031 struct drm_framebuffer *fb,
3032 int x, int y)
3033 {
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 struct drm_plane *plane = crtc->primary;
3038 bool visible = to_intel_plane_state(plane->state)->visible;
3039 struct drm_i915_gem_object *obj;
3040 int pipe = intel_crtc->pipe;
3041 u32 plane_ctl, stride_div, stride;
3042 u32 tile_height, plane_offset, plane_size;
3043 unsigned int rotation;
3044 int x_offset, y_offset;
3045 unsigned long surf_addr;
3046 struct intel_crtc_state *crtc_state = intel_crtc->config;
3047 struct intel_plane_state *plane_state;
3048 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3049 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3050 int scaler_id = -1;
3051
3052 plane_state = to_intel_plane_state(plane->state);
3053
3054 if (!visible || !fb) {
3055 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe, 0));
3058 return;
3059 }
3060
3061 plane_ctl = PLANE_CTL_ENABLE |
3062 PLANE_CTL_PIPE_GAMMA_ENABLE |
3063 PLANE_CTL_PIPE_CSC_ENABLE;
3064
3065 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3066 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3067 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3068
3069 rotation = plane->state->rotation;
3070 plane_ctl |= skl_plane_ctl_rotation(rotation);
3071
3072 obj = intel_fb_obj(fb);
3073 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3074 fb->pixel_format);
3075 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3076
3077 /*
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3081 */
3082 if (drm_rect_width(&plane_state->src)) {
3083 scaler_id = plane_state->scaler_id;
3084 src_x = plane_state->src.x1 >> 16;
3085 src_y = plane_state->src.y1 >> 16;
3086 src_w = drm_rect_width(&plane_state->src) >> 16;
3087 src_h = drm_rect_height(&plane_state->src) >> 16;
3088 dst_x = plane_state->dst.x1;
3089 dst_y = plane_state->dst.y1;
3090 dst_w = drm_rect_width(&plane_state->dst);
3091 dst_h = drm_rect_height(&plane_state->dst);
3092
3093 WARN_ON(x != src_x || y != src_y);
3094 } else {
3095 src_w = intel_crtc->config->pipe_src_w;
3096 src_h = intel_crtc->config->pipe_src_h;
3097 }
3098
3099 if (intel_rotation_90_or_270(rotation)) {
3100 /* stride = Surface height in tiles */
3101 tile_height = intel_tile_height(dev, fb->pixel_format,
3102 fb->modifier[0]);
3103 stride = DIV_ROUND_UP(fb->height, tile_height);
3104 x_offset = stride * tile_height - y - src_h;
3105 y_offset = x;
3106 plane_size = (src_w - 1) << 16 | (src_h - 1);
3107 } else {
3108 stride = fb->pitches[0] / stride_div;
3109 x_offset = x;
3110 y_offset = y;
3111 plane_size = (src_h - 1) << 16 | (src_w - 1);
3112 }
3113 plane_offset = y_offset << 16 | x_offset;
3114
3115 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3116 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3117 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3118 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3119
3120 if (scaler_id >= 0) {
3121 uint32_t ps_ctrl = 0;
3122
3123 WARN_ON(!dst_w || !dst_h);
3124 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3125 crtc_state->scaler_state.scalers[scaler_id].mode;
3126 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3130 I915_WRITE(PLANE_POS(pipe, 0), 0);
3131 } else {
3132 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3133 }
3134
3135 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3136
3137 POSTING_READ(PLANE_SURF(pipe, 0));
3138 }
3139
3140 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3141 static int
3142 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3143 int x, int y, enum mode_set_atomic state)
3144 {
3145 struct drm_device *dev = crtc->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147
3148 if (dev_priv->display.disable_fbc)
3149 dev_priv->display.disable_fbc(dev);
3150
3151 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3152
3153 return 0;
3154 }
3155
3156 static void intel_complete_page_flips(struct drm_device *dev)
3157 {
3158 struct drm_crtc *crtc;
3159
3160 for_each_crtc(dev, crtc) {
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 enum plane plane = intel_crtc->plane;
3163
3164 intel_prepare_page_flip(dev, plane);
3165 intel_finish_page_flip_plane(dev, plane);
3166 }
3167 }
3168
3169 static void intel_update_primary_planes(struct drm_device *dev)
3170 {
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct drm_crtc *crtc;
3173
3174 for_each_crtc(dev, crtc) {
3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176
3177 drm_modeset_lock(&crtc->mutex, NULL);
3178 /*
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
3181 * a NULL crtc->primary->fb.
3182 */
3183 if (intel_crtc->active && crtc->primary->fb)
3184 dev_priv->display.update_primary_plane(crtc,
3185 crtc->primary->fb,
3186 crtc->x,
3187 crtc->y);
3188 drm_modeset_unlock(&crtc->mutex);
3189 }
3190 }
3191
3192 void intel_crtc_reset(struct intel_crtc *crtc)
3193 {
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195
3196 if (!crtc->active)
3197 return;
3198
3199 intel_crtc_disable_planes(&crtc->base);
3200 dev_priv->display.crtc_disable(&crtc->base);
3201 dev_priv->display.crtc_enable(&crtc->base);
3202 intel_crtc_enable_planes(&crtc->base);
3203 }
3204
3205 void intel_prepare_reset(struct drm_device *dev)
3206 {
3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208 struct intel_crtc *crtc;
3209
3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
3219
3220 /*
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3223 */
3224 for_each_intel_crtc(dev, crtc) {
3225 if (!crtc->active)
3226 continue;
3227
3228 intel_crtc_disable_planes(&crtc->base);
3229 dev_priv->display.crtc_disable(&crtc->base);
3230 }
3231 }
3232
3233 void intel_finish_reset(struct drm_device *dev)
3234 {
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 */
3256 intel_update_primary_planes(dev);
3257 return;
3258 }
3259
3260 /*
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3263 */
3264 intel_runtime_pm_disable_interrupts(dev_priv);
3265 intel_runtime_pm_enable_interrupts(dev_priv);
3266
3267 intel_modeset_init_hw(dev);
3268
3269 spin_lock_irq(&dev_priv->irq_lock);
3270 if (dev_priv->display.hpd_irq_setup)
3271 dev_priv->display.hpd_irq_setup(dev);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273
3274 intel_modeset_setup_hw_state(dev, true);
3275
3276 intel_hpd_init(dev_priv);
3277
3278 drm_modeset_unlock_all(dev);
3279 }
3280
3281 static void
3282 intel_finish_fb(struct drm_framebuffer *old_fb)
3283 {
3284 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3285 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3286 bool was_interruptible = dev_priv->mm.interruptible;
3287 int ret;
3288
3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
3296 *
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3299 */
3300 dev_priv->mm.interruptible = false;
3301 ret = i915_gem_object_wait_rendering(obj, true);
3302 dev_priv->mm.interruptible = was_interruptible;
3303
3304 WARN_ON(ret);
3305 }
3306
3307 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308 {
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 bool pending;
3313
3314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 return false;
3317
3318 spin_lock_irq(&dev->event_lock);
3319 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3320 spin_unlock_irq(&dev->event_lock);
3321
3322 return pending;
3323 }
3324
3325 static void intel_update_pipe_size(struct intel_crtc *crtc)
3326 {
3327 struct drm_device *dev = crtc->base.dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 const struct drm_display_mode *adjusted_mode;
3330
3331 if (!i915.fastboot)
3332 return;
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 *
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3346 */
3347
3348 adjusted_mode = &crtc->config->base.adjusted_mode;
3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3352 (adjusted_mode->crtc_vdisplay - 1));
3353 if (!crtc->config->pch_pfit.enabled &&
3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3356 I915_WRITE(PF_CTL(crtc->pipe), 0);
3357 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3359 }
3360 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3361 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3362 }
3363
3364 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365 {
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
3375 if (IS_IVYBRIDGE(dev)) {
3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3381 }
3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
3403 }
3404
3405 /* The FDI link training functions for ILK/Ibexpeak. */
3406 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407 {
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
3412 u32 reg, temp, tries;
3413
3414 /* FDI needs bits from pipe first */
3415 assert_pipe_enabled(dev_priv, pipe);
3416
3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
3425 udelay(150);
3426
3427 /* enable CPU FDI TX and PCH FDI RX */
3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3435
3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
3443 udelay(150);
3444
3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
3449
3450 reg = FDI_RX_IIR(pipe);
3451 for (tries = 0; tries < 5; tries++) {
3452 temp = I915_READ(reg);
3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3458 break;
3459 }
3460 }
3461 if (tries == 5)
3462 DRM_ERROR("FDI train 1 fail!\n");
3463
3464 /* Train 2 */
3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
3469 I915_WRITE(reg, temp);
3470
3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
3478 udelay(150);
3479
3480 reg = FDI_RX_IIR(pipe);
3481 for (tries = 0; tries < 5; tries++) {
3482 temp = I915_READ(reg);
3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
3490 }
3491 if (tries == 5)
3492 DRM_ERROR("FDI train 2 fail!\n");
3493
3494 DRM_DEBUG_KMS("FDI train done\n");
3495
3496 }
3497
3498 static const int snb_b_fdi_train_param[] = {
3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503 };
3504
3505 /* The FDI link training functions for SNB/Cougarpoint. */
3506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507 {
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
3512 u32 reg, temp, i, retry;
3513
3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
3523 udelay(150);
3524
3525 /* enable CPU FDI TX and PCH FDI RX */
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3536
3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
3552 udelay(150);
3553
3554 for (i = 0; i < 4; i++) {
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
3562 udelay(500);
3563
3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
3574 }
3575 if (retry < 5)
3576 break;
3577 }
3578 if (i == 4)
3579 DRM_ERROR("FDI train 1 fail!\n");
3580
3581 /* Train 2 */
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
3591 I915_WRITE(reg, temp);
3592
3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(150);
3606
3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
3615 udelay(500);
3616
3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
3627 }
3628 if (retry < 5)
3629 break;
3630 }
3631 if (i == 4)
3632 DRM_ERROR("FDI train 2 fail!\n");
3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635 }
3636
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639 {
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
3644 u32 reg, temp, i, j;
3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
3668
3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
3675
3676 /* enable CPU FDI TX and PCH FDI RX */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3686
3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3689
3690 reg = FDI_RX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3695
3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
3698
3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3703
3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
3717
3718 /* Train 2 */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
3732 udelay(2); /* should be 1.5us */
3733
3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3738
3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
3747 }
3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3750 }
3751
3752 train_done:
3753 DRM_DEBUG_KMS("FDI train done.\n");
3754 }
3755
3756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3757 {
3758 struct drm_device *dev = intel_crtc->base.dev;
3759 struct drm_i915_private *dev_priv = dev->dev_private;
3760 int pipe = intel_crtc->pipe;
3761 u32 reg, temp;
3762
3763
3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
3780 udelay(200);
3781
3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3787
3788 POSTING_READ(reg);
3789 udelay(100);
3790 }
3791 }
3792
3793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794 {
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820 }
3821
3822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823 {
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
3846 if (HAS_PCH_IBX(dev))
3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872 }
3873
3874 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875 {
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
3885 for_each_intel_crtc(dev, crtc) {
3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896 }
3897
3898 static void page_flip_completed(struct intel_crtc *intel_crtc)
3899 {
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919 }
3920
3921 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925
3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932 spin_lock_irq(&dev->event_lock);
3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
3937 spin_unlock_irq(&dev->event_lock);
3938 }
3939
3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
3945 }
3946
3947 /* Program iCLKIP clock to the desired frequency */
3948 static void lpt_program_iclkip(struct drm_crtc *crtc)
3949 {
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
3956 mutex_lock(&dev_priv->dpio_lock);
3957
3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3970 if (clock == 20000) {
3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
3985 desired_divisor = (iclk_virtual_root_freq / clock);
3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4001 clock,
4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4016
4017 /* Program SSCAUXDIV */
4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4022
4023 /* Enable modulator and associated divider */
4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4025 temp &= ~SBI_SSCCTL_DISABLE;
4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4032
4033 mutex_unlock(&dev_priv->dpio_lock);
4034 }
4035
4036 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038 {
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058 }
4059
4060 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4061 {
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079 }
4080
4081 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082 {
4083 struct drm_device *dev = intel_crtc->base.dev;
4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
4089 if (intel_crtc->config->fdi_lanes > 2)
4090 cpt_set_fdi_bc_bifurcation(dev, false);
4091 else
4092 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094 break;
4095 case PIPE_C:
4096 cpt_set_fdi_bc_bifurcation(dev, true);
4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102 }
4103
4104 /*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112 static void ironlake_pch_enable(struct drm_crtc *crtc)
4113 {
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
4118 u32 reg, temp;
4119
4120 assert_pch_transcoder_disabled(dev_priv, pipe);
4121
4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
4130 /* For PCH output, training FDI link */
4131 dev_priv->display.fdi_link_train(crtc);
4132
4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
4135 if (HAS_PCH_CPT(dev)) {
4136 u32 sel;
4137
4138 temp = I915_READ(PCH_DPLL_SEL);
4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4142 temp |= sel;
4143 else
4144 temp &= ~sel;
4145 I915_WRITE(PCH_DPLL_SEL, temp);
4146 }
4147
4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
4155 intel_enable_shared_dpll(intel_crtc);
4156
4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4160
4161 intel_fdi_normal_train(crtc);
4162
4163 /* For PCH DP, enable TRANS_DP_CTL */
4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
4171 temp |= TRANS_DP_OUTPUT_ENABLE;
4172 temp |= bpc << 9; /* same format but at 11:9 */
4173
4174 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4175 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4176 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4177 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4178
4179 switch (intel_trans_dp_port_sel(crtc)) {
4180 case PCH_DP_B:
4181 temp |= TRANS_DP_PORT_SEL_B;
4182 break;
4183 case PCH_DP_C:
4184 temp |= TRANS_DP_PORT_SEL_C;
4185 break;
4186 case PCH_DP_D:
4187 temp |= TRANS_DP_PORT_SEL_D;
4188 break;
4189 default:
4190 BUG();
4191 }
4192
4193 I915_WRITE(reg, temp);
4194 }
4195
4196 ironlake_enable_pch_transcoder(dev_priv, pipe);
4197 }
4198
4199 static void lpt_pch_enable(struct drm_crtc *crtc)
4200 {
4201 struct drm_device *dev = crtc->dev;
4202 struct drm_i915_private *dev_priv = dev->dev_private;
4203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4205
4206 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4207
4208 lpt_program_iclkip(crtc);
4209
4210 /* Set transcoder timing. */
4211 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4212
4213 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4214 }
4215
4216 void intel_put_shared_dpll(struct intel_crtc *crtc)
4217 {
4218 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4219
4220 if (pll == NULL)
4221 return;
4222
4223 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4224 WARN(1, "bad %s crtc mask\n", pll->name);
4225 return;
4226 }
4227
4228 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4229 if (pll->config.crtc_mask == 0) {
4230 WARN_ON(pll->on);
4231 WARN_ON(pll->active);
4232 }
4233
4234 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4235 }
4236
4237 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4238 struct intel_crtc_state *crtc_state)
4239 {
4240 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4241 struct intel_shared_dpll *pll;
4242 enum intel_dpll_id i;
4243
4244 if (HAS_PCH_IBX(dev_priv->dev)) {
4245 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4246 i = (enum intel_dpll_id) crtc->pipe;
4247 pll = &dev_priv->shared_dplls[i];
4248
4249 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4250 crtc->base.base.id, pll->name);
4251
4252 WARN_ON(pll->new_config->crtc_mask);
4253
4254 goto found;
4255 }
4256
4257 if (IS_BROXTON(dev_priv->dev)) {
4258 /* PLL is attached to port in bxt */
4259 struct intel_encoder *encoder;
4260 struct intel_digital_port *intel_dig_port;
4261
4262 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4263 if (WARN_ON(!encoder))
4264 return NULL;
4265
4266 intel_dig_port = enc_to_dig_port(&encoder->base);
4267 /* 1:1 mapping between ports and PLLs */
4268 i = (enum intel_dpll_id)intel_dig_port->port;
4269 pll = &dev_priv->shared_dplls[i];
4270 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4271 crtc->base.base.id, pll->name);
4272 WARN_ON(pll->new_config->crtc_mask);
4273
4274 goto found;
4275 }
4276
4277 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4278 pll = &dev_priv->shared_dplls[i];
4279
4280 /* Only want to check enabled timings first */
4281 if (pll->new_config->crtc_mask == 0)
4282 continue;
4283
4284 if (memcmp(&crtc_state->dpll_hw_state,
4285 &pll->new_config->hw_state,
4286 sizeof(pll->new_config->hw_state)) == 0) {
4287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4288 crtc->base.base.id, pll->name,
4289 pll->new_config->crtc_mask,
4290 pll->active);
4291 goto found;
4292 }
4293 }
4294
4295 /* Ok no matching timings, maybe there's a free one? */
4296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4297 pll = &dev_priv->shared_dplls[i];
4298 if (pll->new_config->crtc_mask == 0) {
4299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4300 crtc->base.base.id, pll->name);
4301 goto found;
4302 }
4303 }
4304
4305 return NULL;
4306
4307 found:
4308 if (pll->new_config->crtc_mask == 0)
4309 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4310
4311 crtc_state->shared_dpll = i;
4312 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4313 pipe_name(crtc->pipe));
4314
4315 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4316
4317 return pll;
4318 }
4319
4320 /**
4321 * intel_shared_dpll_start_config - start a new PLL staged config
4322 * @dev_priv: DRM device
4323 * @clear_pipes: mask of pipes that will have their PLLs freed
4324 *
4325 * Starts a new PLL staged config, copying the current config but
4326 * releasing the references of pipes specified in clear_pipes.
4327 */
4328 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4329 unsigned clear_pipes)
4330 {
4331 struct intel_shared_dpll *pll;
4332 enum intel_dpll_id i;
4333
4334 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4335 pll = &dev_priv->shared_dplls[i];
4336
4337 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4338 GFP_KERNEL);
4339 if (!pll->new_config)
4340 goto cleanup;
4341
4342 pll->new_config->crtc_mask &= ~clear_pipes;
4343 }
4344
4345 return 0;
4346
4347 cleanup:
4348 while (--i >= 0) {
4349 pll = &dev_priv->shared_dplls[i];
4350 kfree(pll->new_config);
4351 pll->new_config = NULL;
4352 }
4353
4354 return -ENOMEM;
4355 }
4356
4357 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4358 {
4359 struct intel_shared_dpll *pll;
4360 enum intel_dpll_id i;
4361
4362 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4363 pll = &dev_priv->shared_dplls[i];
4364
4365 WARN_ON(pll->new_config == &pll->config);
4366
4367 pll->config = *pll->new_config;
4368 kfree(pll->new_config);
4369 pll->new_config = NULL;
4370 }
4371 }
4372
4373 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4374 {
4375 struct intel_shared_dpll *pll;
4376 enum intel_dpll_id i;
4377
4378 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4379 pll = &dev_priv->shared_dplls[i];
4380
4381 WARN_ON(pll->new_config == &pll->config);
4382
4383 kfree(pll->new_config);
4384 pll->new_config = NULL;
4385 }
4386 }
4387
4388 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4389 {
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 int dslreg = PIPEDSL(pipe);
4392 u32 temp;
4393
4394 temp = I915_READ(dslreg);
4395 udelay(500);
4396 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4397 if (wait_for(I915_READ(dslreg) != temp, 5))
4398 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4399 }
4400 }
4401
4402 /**
4403 * skl_update_scaler_users - Stages update to crtc's scaler state
4404 * @intel_crtc: crtc
4405 * @crtc_state: crtc_state
4406 * @plane: plane (NULL indicates crtc is requesting update)
4407 * @plane_state: plane's state
4408 * @force_detach: request unconditional detachment of scaler
4409 *
4410 * This function updates scaler state for requested plane or crtc.
4411 * To request scaler usage update for a plane, caller shall pass plane pointer.
4412 * To request scaler usage update for crtc, caller shall pass plane pointer
4413 * as NULL.
4414 *
4415 * Return
4416 * 0 - scaler_usage updated successfully
4417 * error - requested scaling cannot be supported or other error condition
4418 */
4419 int
4420 skl_update_scaler_users(
4421 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4422 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4423 int force_detach)
4424 {
4425 int need_scaling;
4426 int idx;
4427 int src_w, src_h, dst_w, dst_h;
4428 int *scaler_id;
4429 struct drm_framebuffer *fb;
4430 struct intel_crtc_scaler_state *scaler_state;
4431 unsigned int rotation;
4432
4433 if (!intel_crtc || !crtc_state)
4434 return 0;
4435
4436 scaler_state = &crtc_state->scaler_state;
4437
4438 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4439 fb = intel_plane ? plane_state->base.fb : NULL;
4440
4441 if (intel_plane) {
4442 src_w = drm_rect_width(&plane_state->src) >> 16;
4443 src_h = drm_rect_height(&plane_state->src) >> 16;
4444 dst_w = drm_rect_width(&plane_state->dst);
4445 dst_h = drm_rect_height(&plane_state->dst);
4446 scaler_id = &plane_state->scaler_id;
4447 rotation = plane_state->base.rotation;
4448 } else {
4449 struct drm_display_mode *adjusted_mode =
4450 &crtc_state->base.adjusted_mode;
4451 src_w = crtc_state->pipe_src_w;
4452 src_h = crtc_state->pipe_src_h;
4453 dst_w = adjusted_mode->hdisplay;
4454 dst_h = adjusted_mode->vdisplay;
4455 scaler_id = &scaler_state->scaler_id;
4456 rotation = DRM_ROTATE_0;
4457 }
4458
4459 need_scaling = intel_rotation_90_or_270(rotation) ?
4460 (src_h != dst_w || src_w != dst_h):
4461 (src_w != dst_w || src_h != dst_h);
4462
4463 /*
4464 * if plane is being disabled or scaler is no more required or force detach
4465 * - free scaler binded to this plane/crtc
4466 * - in order to do this, update crtc->scaler_usage
4467 *
4468 * Here scaler state in crtc_state is set free so that
4469 * scaler can be assigned to other user. Actual register
4470 * update to free the scaler is done in plane/panel-fit programming.
4471 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4472 */
4473 if (force_detach || !need_scaling || (intel_plane &&
4474 (!fb || !plane_state->visible))) {
4475 if (*scaler_id >= 0) {
4476 scaler_state->scaler_users &= ~(1 << idx);
4477 scaler_state->scalers[*scaler_id].in_use = 0;
4478
4479 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4480 "crtc_state = %p scaler_users = 0x%x\n",
4481 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4482 intel_plane ? intel_plane->base.base.id :
4483 intel_crtc->base.base.id, crtc_state,
4484 scaler_state->scaler_users);
4485 *scaler_id = -1;
4486 }
4487 return 0;
4488 }
4489
4490 /* range checks */
4491 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4492 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4493
4494 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4495 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4496 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4497 "size is out of scaler range\n",
4498 intel_plane ? "PLANE" : "CRTC",
4499 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4500 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4501 return -EINVAL;
4502 }
4503
4504 /* check colorkey */
4505 if (WARN_ON(intel_plane &&
4506 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4507 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4508 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4509 return -EINVAL;
4510 }
4511
4512 /* Check src format */
4513 if (intel_plane) {
4514 switch (fb->pixel_format) {
4515 case DRM_FORMAT_RGB565:
4516 case DRM_FORMAT_XBGR8888:
4517 case DRM_FORMAT_XRGB8888:
4518 case DRM_FORMAT_ABGR8888:
4519 case DRM_FORMAT_ARGB8888:
4520 case DRM_FORMAT_XRGB2101010:
4521 case DRM_FORMAT_XBGR2101010:
4522 case DRM_FORMAT_YUYV:
4523 case DRM_FORMAT_YVYU:
4524 case DRM_FORMAT_UYVY:
4525 case DRM_FORMAT_VYUY:
4526 break;
4527 default:
4528 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4529 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4530 return -EINVAL;
4531 }
4532 }
4533
4534 /* mark this plane as a scaler user in crtc_state */
4535 scaler_state->scaler_users |= (1 << idx);
4536 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4537 "crtc_state = %p scaler_users = 0x%x\n",
4538 intel_plane ? "PLANE" : "CRTC",
4539 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4540 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4541 return 0;
4542 }
4543
4544 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4545 {
4546 struct drm_device *dev = crtc->base.dev;
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 int pipe = crtc->pipe;
4549 struct intel_crtc_scaler_state *scaler_state =
4550 &crtc->config->scaler_state;
4551
4552 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4553
4554 /* To update pfit, first update scaler state */
4555 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4556 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4557 skl_detach_scalers(crtc);
4558 if (!enable)
4559 return;
4560
4561 if (crtc->config->pch_pfit.enabled) {
4562 int id;
4563
4564 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4565 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4566 return;
4567 }
4568
4569 id = scaler_state->scaler_id;
4570 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4571 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4572 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4573 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4574
4575 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4576 }
4577 }
4578
4579 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4580 {
4581 struct drm_device *dev = crtc->base.dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583 int pipe = crtc->pipe;
4584
4585 if (crtc->config->pch_pfit.enabled) {
4586 /* Force use of hard-coded filter coefficients
4587 * as some pre-programmed values are broken,
4588 * e.g. x201.
4589 */
4590 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4591 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4592 PF_PIPE_SEL_IVB(pipe));
4593 else
4594 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4595 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4596 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4597 }
4598 }
4599
4600 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4601 {
4602 struct drm_device *dev = crtc->dev;
4603 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4604 struct drm_plane *plane;
4605 struct intel_plane *intel_plane;
4606
4607 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4608 intel_plane = to_intel_plane(plane);
4609 if (intel_plane->pipe == pipe)
4610 intel_plane_restore(&intel_plane->base);
4611 }
4612 }
4613
4614 void hsw_enable_ips(struct intel_crtc *crtc)
4615 {
4616 struct drm_device *dev = crtc->base.dev;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618
4619 if (!crtc->config->ips_enabled)
4620 return;
4621
4622 /* We can only enable IPS after we enable a plane and wait for a vblank */
4623 intel_wait_for_vblank(dev, crtc->pipe);
4624
4625 assert_plane_enabled(dev_priv, crtc->plane);
4626 if (IS_BROADWELL(dev)) {
4627 mutex_lock(&dev_priv->rps.hw_lock);
4628 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4629 mutex_unlock(&dev_priv->rps.hw_lock);
4630 /* Quoting Art Runyan: "its not safe to expect any particular
4631 * value in IPS_CTL bit 31 after enabling IPS through the
4632 * mailbox." Moreover, the mailbox may return a bogus state,
4633 * so we need to just enable it and continue on.
4634 */
4635 } else {
4636 I915_WRITE(IPS_CTL, IPS_ENABLE);
4637 /* The bit only becomes 1 in the next vblank, so this wait here
4638 * is essentially intel_wait_for_vblank. If we don't have this
4639 * and don't wait for vblanks until the end of crtc_enable, then
4640 * the HW state readout code will complain that the expected
4641 * IPS_CTL value is not the one we read. */
4642 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4643 DRM_ERROR("Timed out waiting for IPS enable\n");
4644 }
4645 }
4646
4647 void hsw_disable_ips(struct intel_crtc *crtc)
4648 {
4649 struct drm_device *dev = crtc->base.dev;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651
4652 if (!crtc->config->ips_enabled)
4653 return;
4654
4655 assert_plane_enabled(dev_priv, crtc->plane);
4656 if (IS_BROADWELL(dev)) {
4657 mutex_lock(&dev_priv->rps.hw_lock);
4658 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4659 mutex_unlock(&dev_priv->rps.hw_lock);
4660 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4661 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4662 DRM_ERROR("Timed out waiting for IPS disable\n");
4663 } else {
4664 I915_WRITE(IPS_CTL, 0);
4665 POSTING_READ(IPS_CTL);
4666 }
4667
4668 /* We need to wait for a vblank before we can disable the plane. */
4669 intel_wait_for_vblank(dev, crtc->pipe);
4670 }
4671
4672 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4673 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4674 {
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 enum pipe pipe = intel_crtc->pipe;
4679 int palreg = PALETTE(pipe);
4680 int i;
4681 bool reenable_ips = false;
4682
4683 /* The clocks have to be on to load the palette. */
4684 if (!crtc->state->enable || !intel_crtc->active)
4685 return;
4686
4687 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4688 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4689 assert_dsi_pll_enabled(dev_priv);
4690 else
4691 assert_pll_enabled(dev_priv, pipe);
4692 }
4693
4694 /* use legacy palette for Ironlake */
4695 if (!HAS_GMCH_DISPLAY(dev))
4696 palreg = LGC_PALETTE(pipe);
4697
4698 /* Workaround : Do not read or write the pipe palette/gamma data while
4699 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4700 */
4701 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4702 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4703 GAMMA_MODE_MODE_SPLIT)) {
4704 hsw_disable_ips(intel_crtc);
4705 reenable_ips = true;
4706 }
4707
4708 for (i = 0; i < 256; i++) {
4709 I915_WRITE(palreg + 4 * i,
4710 (intel_crtc->lut_r[i] << 16) |
4711 (intel_crtc->lut_g[i] << 8) |
4712 intel_crtc->lut_b[i]);
4713 }
4714
4715 if (reenable_ips)
4716 hsw_enable_ips(intel_crtc);
4717 }
4718
4719 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4720 {
4721 if (intel_crtc->overlay) {
4722 struct drm_device *dev = intel_crtc->base.dev;
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724
4725 mutex_lock(&dev->struct_mutex);
4726 dev_priv->mm.interruptible = false;
4727 (void) intel_overlay_switch_off(intel_crtc->overlay);
4728 dev_priv->mm.interruptible = true;
4729 mutex_unlock(&dev->struct_mutex);
4730 }
4731
4732 /* Let userspace switch the overlay on again. In most cases userspace
4733 * has to recompute where to put it anyway.
4734 */
4735 }
4736
4737 /**
4738 * intel_post_enable_primary - Perform operations after enabling primary plane
4739 * @crtc: the CRTC whose primary plane was just enabled
4740 *
4741 * Performs potentially sleeping operations that must be done after the primary
4742 * plane is enabled, such as updating FBC and IPS. Note that this may be
4743 * called due to an explicit primary plane update, or due to an implicit
4744 * re-enable that is caused when a sprite plane is updated to no longer
4745 * completely hide the primary plane.
4746 */
4747 static void
4748 intel_post_enable_primary(struct drm_crtc *crtc)
4749 {
4750 struct drm_device *dev = crtc->dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
4754
4755 /*
4756 * BDW signals flip done immediately if the plane
4757 * is disabled, even if the plane enable is already
4758 * armed to occur at the next vblank :(
4759 */
4760 if (IS_BROADWELL(dev))
4761 intel_wait_for_vblank(dev, pipe);
4762
4763 /*
4764 * FIXME IPS should be fine as long as one plane is
4765 * enabled, but in practice it seems to have problems
4766 * when going from primary only to sprite only and vice
4767 * versa.
4768 */
4769 hsw_enable_ips(intel_crtc);
4770
4771 mutex_lock(&dev->struct_mutex);
4772 intel_fbc_update(dev);
4773 mutex_unlock(&dev->struct_mutex);
4774
4775 /*
4776 * Gen2 reports pipe underruns whenever all planes are disabled.
4777 * So don't enable underrun reporting before at least some planes
4778 * are enabled.
4779 * FIXME: Need to fix the logic to work when we turn off all planes
4780 * but leave the pipe running.
4781 */
4782 if (IS_GEN2(dev))
4783 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4784
4785 /* Underruns don't raise interrupts, so check manually. */
4786 if (HAS_GMCH_DISPLAY(dev))
4787 i9xx_check_fifo_underruns(dev_priv);
4788 }
4789
4790 /**
4791 * intel_pre_disable_primary - Perform operations before disabling primary plane
4792 * @crtc: the CRTC whose primary plane is to be disabled
4793 *
4794 * Performs potentially sleeping operations that must be done before the
4795 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4796 * be called due to an explicit primary plane update, or due to an implicit
4797 * disable that is caused when a sprite plane completely hides the primary
4798 * plane.
4799 */
4800 static void
4801 intel_pre_disable_primary(struct drm_crtc *crtc)
4802 {
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806 int pipe = intel_crtc->pipe;
4807
4808 /*
4809 * Gen2 reports pipe underruns whenever all planes are disabled.
4810 * So diasble underrun reporting before all the planes get disabled.
4811 * FIXME: Need to fix the logic to work when we turn off all planes
4812 * but leave the pipe running.
4813 */
4814 if (IS_GEN2(dev))
4815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4816
4817 /*
4818 * Vblank time updates from the shadow to live plane control register
4819 * are blocked if the memory self-refresh mode is active at that
4820 * moment. So to make sure the plane gets truly disabled, disable
4821 * first the self-refresh mode. The self-refresh enable bit in turn
4822 * will be checked/applied by the HW only at the next frame start
4823 * event which is after the vblank start event, so we need to have a
4824 * wait-for-vblank between disabling the plane and the pipe.
4825 */
4826 if (HAS_GMCH_DISPLAY(dev))
4827 intel_set_memory_cxsr(dev_priv, false);
4828
4829 mutex_lock(&dev->struct_mutex);
4830 if (dev_priv->fbc.crtc == intel_crtc)
4831 intel_fbc_disable(dev);
4832 mutex_unlock(&dev->struct_mutex);
4833
4834 /*
4835 * FIXME IPS should be fine as long as one plane is
4836 * enabled, but in practice it seems to have problems
4837 * when going from primary only to sprite only and vice
4838 * versa.
4839 */
4840 hsw_disable_ips(intel_crtc);
4841 }
4842
4843 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4844 {
4845 intel_enable_primary_hw_plane(crtc->primary, crtc);
4846 intel_enable_sprite_planes(crtc);
4847 intel_crtc_update_cursor(crtc, true);
4848
4849 intel_post_enable_primary(crtc);
4850 }
4851
4852 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4853 {
4854 struct drm_device *dev = crtc->dev;
4855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4856 struct intel_plane *intel_plane;
4857 int pipe = intel_crtc->pipe;
4858
4859 intel_crtc_wait_for_pending_flips(crtc);
4860
4861 intel_pre_disable_primary(crtc);
4862
4863 intel_crtc_dpms_overlay_disable(intel_crtc);
4864 for_each_intel_plane(dev, intel_plane) {
4865 if (intel_plane->pipe == pipe) {
4866 struct drm_crtc *from = intel_plane->base.crtc;
4867
4868 intel_plane->disable_plane(&intel_plane->base,
4869 from ?: crtc, true);
4870 }
4871 }
4872
4873 /*
4874 * FIXME: Once we grow proper nuclear flip support out of this we need
4875 * to compute the mask of flip planes precisely. For the time being
4876 * consider this a flip to a NULL plane.
4877 */
4878 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4879 }
4880
4881 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4882 {
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4886 struct intel_encoder *encoder;
4887 int pipe = intel_crtc->pipe;
4888
4889 WARN_ON(!crtc->state->enable);
4890
4891 if (intel_crtc->active)
4892 return;
4893
4894 if (intel_crtc->config->has_pch_encoder)
4895 intel_prepare_shared_dpll(intel_crtc);
4896
4897 if (intel_crtc->config->has_dp_encoder)
4898 intel_dp_set_m_n(intel_crtc, M1_N1);
4899
4900 intel_set_pipe_timings(intel_crtc);
4901
4902 if (intel_crtc->config->has_pch_encoder) {
4903 intel_cpu_transcoder_set_m_n(intel_crtc,
4904 &intel_crtc->config->fdi_m_n, NULL);
4905 }
4906
4907 ironlake_set_pipeconf(crtc);
4908
4909 intel_crtc->active = true;
4910
4911 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4912 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4913
4914 for_each_encoder_on_crtc(dev, crtc, encoder)
4915 if (encoder->pre_enable)
4916 encoder->pre_enable(encoder);
4917
4918 if (intel_crtc->config->has_pch_encoder) {
4919 /* Note: FDI PLL enabling _must_ be done before we enable the
4920 * cpu pipes, hence this is separate from all the other fdi/pch
4921 * enabling. */
4922 ironlake_fdi_pll_enable(intel_crtc);
4923 } else {
4924 assert_fdi_tx_disabled(dev_priv, pipe);
4925 assert_fdi_rx_disabled(dev_priv, pipe);
4926 }
4927
4928 ironlake_pfit_enable(intel_crtc);
4929
4930 /*
4931 * On ILK+ LUT must be loaded before the pipe is running but with
4932 * clocks enabled
4933 */
4934 intel_crtc_load_lut(crtc);
4935
4936 intel_update_watermarks(crtc);
4937 intel_enable_pipe(intel_crtc);
4938
4939 if (intel_crtc->config->has_pch_encoder)
4940 ironlake_pch_enable(crtc);
4941
4942 assert_vblank_disabled(crtc);
4943 drm_crtc_vblank_on(crtc);
4944
4945 for_each_encoder_on_crtc(dev, crtc, encoder)
4946 encoder->enable(encoder);
4947
4948 if (HAS_PCH_CPT(dev))
4949 cpt_verify_modeset(dev, intel_crtc->pipe);
4950 }
4951
4952 /* IPS only exists on ULT machines and is tied to pipe A. */
4953 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4954 {
4955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4956 }
4957
4958 /*
4959 * This implements the workaround described in the "notes" section of the mode
4960 * set sequence documentation. When going from no pipes or single pipe to
4961 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4962 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4963 */
4964 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4965 {
4966 struct drm_device *dev = crtc->base.dev;
4967 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4968
4969 /* We want to get the other_active_crtc only if there's only 1 other
4970 * active crtc. */
4971 for_each_intel_crtc(dev, crtc_it) {
4972 if (!crtc_it->active || crtc_it == crtc)
4973 continue;
4974
4975 if (other_active_crtc)
4976 return;
4977
4978 other_active_crtc = crtc_it;
4979 }
4980 if (!other_active_crtc)
4981 return;
4982
4983 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4984 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985 }
4986
4987 static void haswell_crtc_enable(struct drm_crtc *crtc)
4988 {
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992 struct intel_encoder *encoder;
4993 int pipe = intel_crtc->pipe;
4994
4995 WARN_ON(!crtc->state->enable);
4996
4997 if (intel_crtc->active)
4998 return;
4999
5000 if (intel_crtc_to_shared_dpll(intel_crtc))
5001 intel_enable_shared_dpll(intel_crtc);
5002
5003 if (intel_crtc->config->has_dp_encoder)
5004 intel_dp_set_m_n(intel_crtc, M1_N1);
5005
5006 intel_set_pipe_timings(intel_crtc);
5007
5008 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5009 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5010 intel_crtc->config->pixel_multiplier - 1);
5011 }
5012
5013 if (intel_crtc->config->has_pch_encoder) {
5014 intel_cpu_transcoder_set_m_n(intel_crtc,
5015 &intel_crtc->config->fdi_m_n, NULL);
5016 }
5017
5018 haswell_set_pipeconf(crtc);
5019
5020 intel_set_pipe_csc(crtc);
5021
5022 intel_crtc->active = true;
5023
5024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->pre_enable)
5027 encoder->pre_enable(encoder);
5028
5029 if (intel_crtc->config->has_pch_encoder) {
5030 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5031 true);
5032 dev_priv->display.fdi_link_train(crtc);
5033 }
5034
5035 intel_ddi_enable_pipe_clock(intel_crtc);
5036
5037 if (INTEL_INFO(dev)->gen == 9)
5038 skylake_pfit_update(intel_crtc, 1);
5039 else if (INTEL_INFO(dev)->gen < 9)
5040 ironlake_pfit_enable(intel_crtc);
5041 else
5042 MISSING_CASE(INTEL_INFO(dev)->gen);
5043
5044 /*
5045 * On ILK+ LUT must be loaded before the pipe is running but with
5046 * clocks enabled
5047 */
5048 intel_crtc_load_lut(crtc);
5049
5050 intel_ddi_set_pipe_settings(crtc);
5051 intel_ddi_enable_transcoder_func(crtc);
5052
5053 intel_update_watermarks(crtc);
5054 intel_enable_pipe(intel_crtc);
5055
5056 if (intel_crtc->config->has_pch_encoder)
5057 lpt_pch_enable(crtc);
5058
5059 if (intel_crtc->config->dp_encoder_is_mst)
5060 intel_ddi_set_vc_payload_alloc(crtc, true);
5061
5062 assert_vblank_disabled(crtc);
5063 drm_crtc_vblank_on(crtc);
5064
5065 for_each_encoder_on_crtc(dev, crtc, encoder) {
5066 encoder->enable(encoder);
5067 intel_opregion_notify_encoder(encoder, true);
5068 }
5069
5070 /* If we change the relative order between pipe/planes enabling, we need
5071 * to change the workaround. */
5072 haswell_mode_set_planes_workaround(intel_crtc);
5073 }
5074
5075 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5076 {
5077 struct drm_device *dev = crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 int pipe = crtc->pipe;
5080
5081 /* To avoid upsetting the power well on haswell only disable the pfit if
5082 * it's in use. The hw state code will make sure we get this right. */
5083 if (crtc->config->pch_pfit.enabled) {
5084 I915_WRITE(PF_CTL(pipe), 0);
5085 I915_WRITE(PF_WIN_POS(pipe), 0);
5086 I915_WRITE(PF_WIN_SZ(pipe), 0);
5087 }
5088 }
5089
5090 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5091 {
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095 struct intel_encoder *encoder;
5096 int pipe = intel_crtc->pipe;
5097 u32 reg, temp;
5098
5099 if (!intel_crtc->active)
5100 return;
5101
5102 for_each_encoder_on_crtc(dev, crtc, encoder)
5103 encoder->disable(encoder);
5104
5105 drm_crtc_vblank_off(crtc);
5106 assert_vblank_disabled(crtc);
5107
5108 if (intel_crtc->config->has_pch_encoder)
5109 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5110
5111 intel_disable_pipe(intel_crtc);
5112
5113 ironlake_pfit_disable(intel_crtc);
5114
5115 if (intel_crtc->config->has_pch_encoder)
5116 ironlake_fdi_disable(crtc);
5117
5118 for_each_encoder_on_crtc(dev, crtc, encoder)
5119 if (encoder->post_disable)
5120 encoder->post_disable(encoder);
5121
5122 if (intel_crtc->config->has_pch_encoder) {
5123 ironlake_disable_pch_transcoder(dev_priv, pipe);
5124
5125 if (HAS_PCH_CPT(dev)) {
5126 /* disable TRANS_DP_CTL */
5127 reg = TRANS_DP_CTL(pipe);
5128 temp = I915_READ(reg);
5129 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5130 TRANS_DP_PORT_SEL_MASK);
5131 temp |= TRANS_DP_PORT_SEL_NONE;
5132 I915_WRITE(reg, temp);
5133
5134 /* disable DPLL_SEL */
5135 temp = I915_READ(PCH_DPLL_SEL);
5136 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5137 I915_WRITE(PCH_DPLL_SEL, temp);
5138 }
5139
5140 /* disable PCH DPLL */
5141 intel_disable_shared_dpll(intel_crtc);
5142
5143 ironlake_fdi_pll_disable(intel_crtc);
5144 }
5145
5146 intel_crtc->active = false;
5147 intel_update_watermarks(crtc);
5148
5149 mutex_lock(&dev->struct_mutex);
5150 intel_fbc_update(dev);
5151 mutex_unlock(&dev->struct_mutex);
5152 }
5153
5154 static void haswell_crtc_disable(struct drm_crtc *crtc)
5155 {
5156 struct drm_device *dev = crtc->dev;
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5159 struct intel_encoder *encoder;
5160 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5161
5162 if (!intel_crtc->active)
5163 return;
5164
5165 for_each_encoder_on_crtc(dev, crtc, encoder) {
5166 intel_opregion_notify_encoder(encoder, false);
5167 encoder->disable(encoder);
5168 }
5169
5170 drm_crtc_vblank_off(crtc);
5171 assert_vblank_disabled(crtc);
5172
5173 if (intel_crtc->config->has_pch_encoder)
5174 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5175 false);
5176 intel_disable_pipe(intel_crtc);
5177
5178 if (intel_crtc->config->dp_encoder_is_mst)
5179 intel_ddi_set_vc_payload_alloc(crtc, false);
5180
5181 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5182
5183 if (INTEL_INFO(dev)->gen == 9)
5184 skylake_pfit_update(intel_crtc, 0);
5185 else if (INTEL_INFO(dev)->gen < 9)
5186 ironlake_pfit_disable(intel_crtc);
5187 else
5188 MISSING_CASE(INTEL_INFO(dev)->gen);
5189
5190 intel_ddi_disable_pipe_clock(intel_crtc);
5191
5192 if (intel_crtc->config->has_pch_encoder) {
5193 lpt_disable_pch_transcoder(dev_priv);
5194 intel_ddi_fdi_disable(crtc);
5195 }
5196
5197 for_each_encoder_on_crtc(dev, crtc, encoder)
5198 if (encoder->post_disable)
5199 encoder->post_disable(encoder);
5200
5201 intel_crtc->active = false;
5202 intel_update_watermarks(crtc);
5203
5204 mutex_lock(&dev->struct_mutex);
5205 intel_fbc_update(dev);
5206 mutex_unlock(&dev->struct_mutex);
5207
5208 if (intel_crtc_to_shared_dpll(intel_crtc))
5209 intel_disable_shared_dpll(intel_crtc);
5210 }
5211
5212 static void ironlake_crtc_off(struct drm_crtc *crtc)
5213 {
5214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5215 intel_put_shared_dpll(intel_crtc);
5216 }
5217
5218
5219 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5220 {
5221 struct drm_device *dev = crtc->base.dev;
5222 struct drm_i915_private *dev_priv = dev->dev_private;
5223 struct intel_crtc_state *pipe_config = crtc->config;
5224
5225 if (!pipe_config->gmch_pfit.control)
5226 return;
5227
5228 /*
5229 * The panel fitter should only be adjusted whilst the pipe is disabled,
5230 * according to register description and PRM.
5231 */
5232 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5233 assert_pipe_disabled(dev_priv, crtc->pipe);
5234
5235 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5236 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5237
5238 /* Border color in case we don't scale up to the full screen. Black by
5239 * default, change to something else for debugging. */
5240 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5241 }
5242
5243 static enum intel_display_power_domain port_to_power_domain(enum port port)
5244 {
5245 switch (port) {
5246 case PORT_A:
5247 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5248 case PORT_B:
5249 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5250 case PORT_C:
5251 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5252 case PORT_D:
5253 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5254 default:
5255 WARN_ON_ONCE(1);
5256 return POWER_DOMAIN_PORT_OTHER;
5257 }
5258 }
5259
5260 #define for_each_power_domain(domain, mask) \
5261 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5262 if ((1 << (domain)) & (mask))
5263
5264 enum intel_display_power_domain
5265 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5266 {
5267 struct drm_device *dev = intel_encoder->base.dev;
5268 struct intel_digital_port *intel_dig_port;
5269
5270 switch (intel_encoder->type) {
5271 case INTEL_OUTPUT_UNKNOWN:
5272 /* Only DDI platforms should ever use this output type */
5273 WARN_ON_ONCE(!HAS_DDI(dev));
5274 case INTEL_OUTPUT_DISPLAYPORT:
5275 case INTEL_OUTPUT_HDMI:
5276 case INTEL_OUTPUT_EDP:
5277 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5278 return port_to_power_domain(intel_dig_port->port);
5279 case INTEL_OUTPUT_DP_MST:
5280 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5281 return port_to_power_domain(intel_dig_port->port);
5282 case INTEL_OUTPUT_ANALOG:
5283 return POWER_DOMAIN_PORT_CRT;
5284 case INTEL_OUTPUT_DSI:
5285 return POWER_DOMAIN_PORT_DSI;
5286 default:
5287 return POWER_DOMAIN_PORT_OTHER;
5288 }
5289 }
5290
5291 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5292 {
5293 struct drm_device *dev = crtc->dev;
5294 struct intel_encoder *intel_encoder;
5295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5296 enum pipe pipe = intel_crtc->pipe;
5297 unsigned long mask;
5298 enum transcoder transcoder;
5299
5300 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5301
5302 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5303 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5304 if (intel_crtc->config->pch_pfit.enabled ||
5305 intel_crtc->config->pch_pfit.force_thru)
5306 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5307
5308 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5309 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5310
5311 return mask;
5312 }
5313
5314 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5315 {
5316 struct drm_device *dev = state->dev;
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5319 struct intel_crtc *crtc;
5320
5321 /*
5322 * First get all needed power domains, then put all unneeded, to avoid
5323 * any unnecessary toggling of the power wells.
5324 */
5325 for_each_intel_crtc(dev, crtc) {
5326 enum intel_display_power_domain domain;
5327
5328 if (!crtc->base.state->enable)
5329 continue;
5330
5331 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5332
5333 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5334 intel_display_power_get(dev_priv, domain);
5335 }
5336
5337 if (dev_priv->display.modeset_global_resources)
5338 dev_priv->display.modeset_global_resources(state);
5339
5340 for_each_intel_crtc(dev, crtc) {
5341 enum intel_display_power_domain domain;
5342
5343 for_each_power_domain(domain, crtc->enabled_power_domains)
5344 intel_display_power_put(dev_priv, domain);
5345
5346 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5347 }
5348
5349 intel_display_set_init_power(dev_priv, false);
5350 }
5351
5352 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5353 {
5354 struct drm_i915_private *dev_priv = dev->dev_private;
5355 uint32_t divider;
5356 uint32_t ratio;
5357 uint32_t current_freq;
5358 int ret;
5359
5360 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5361 switch (frequency) {
5362 case 144000:
5363 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5364 ratio = BXT_DE_PLL_RATIO(60);
5365 break;
5366 case 288000:
5367 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5368 ratio = BXT_DE_PLL_RATIO(60);
5369 break;
5370 case 384000:
5371 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5372 ratio = BXT_DE_PLL_RATIO(60);
5373 break;
5374 case 576000:
5375 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5376 ratio = BXT_DE_PLL_RATIO(60);
5377 break;
5378 case 624000:
5379 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5380 ratio = BXT_DE_PLL_RATIO(65);
5381 break;
5382 case 19200:
5383 /*
5384 * Bypass frequency with DE PLL disabled. Init ratio, divider
5385 * to suppress GCC warning.
5386 */
5387 ratio = 0;
5388 divider = 0;
5389 break;
5390 default:
5391 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5392
5393 return;
5394 }
5395
5396 mutex_lock(&dev_priv->rps.hw_lock);
5397 /* Inform power controller of upcoming frequency change */
5398 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5399 0x80000000);
5400 mutex_unlock(&dev_priv->rps.hw_lock);
5401
5402 if (ret) {
5403 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5404 ret, frequency);
5405 return;
5406 }
5407
5408 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5409 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5410 current_freq = current_freq * 500 + 1000;
5411
5412 /*
5413 * DE PLL has to be disabled when
5414 * - setting to 19.2MHz (bypass, PLL isn't used)
5415 * - before setting to 624MHz (PLL needs toggling)
5416 * - before setting to any frequency from 624MHz (PLL needs toggling)
5417 */
5418 if (frequency == 19200 || frequency == 624000 ||
5419 current_freq == 624000) {
5420 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5421 /* Timeout 200us */
5422 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5423 1))
5424 DRM_ERROR("timout waiting for DE PLL unlock\n");
5425 }
5426
5427 if (frequency != 19200) {
5428 uint32_t val;
5429
5430 val = I915_READ(BXT_DE_PLL_CTL);
5431 val &= ~BXT_DE_PLL_RATIO_MASK;
5432 val |= ratio;
5433 I915_WRITE(BXT_DE_PLL_CTL, val);
5434
5435 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5436 /* Timeout 200us */
5437 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5438 DRM_ERROR("timeout waiting for DE PLL lock\n");
5439
5440 val = I915_READ(CDCLK_CTL);
5441 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5442 val |= divider;
5443 /*
5444 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5445 * enable otherwise.
5446 */
5447 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5448 if (frequency >= 500000)
5449 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5450
5451 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5452 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5453 val |= (frequency - 1000) / 500;
5454 I915_WRITE(CDCLK_CTL, val);
5455 }
5456
5457 mutex_lock(&dev_priv->rps.hw_lock);
5458 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5459 DIV_ROUND_UP(frequency, 25000));
5460 mutex_unlock(&dev_priv->rps.hw_lock);
5461
5462 if (ret) {
5463 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5464 ret, frequency);
5465 return;
5466 }
5467
5468 dev_priv->cdclk_freq = frequency;
5469 }
5470
5471 void broxton_init_cdclk(struct drm_device *dev)
5472 {
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 uint32_t val;
5475
5476 /*
5477 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5478 * or else the reset will hang because there is no PCH to respond.
5479 * Move the handshake programming to initialization sequence.
5480 * Previously was left up to BIOS.
5481 */
5482 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5483 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5484 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5485
5486 /* Enable PG1 for cdclk */
5487 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5488
5489 /* check if cd clock is enabled */
5490 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5491 DRM_DEBUG_KMS("Display already initialized\n");
5492 return;
5493 }
5494
5495 /*
5496 * FIXME:
5497 * - The initial CDCLK needs to be read from VBT.
5498 * Need to make this change after VBT has changes for BXT.
5499 * - check if setting the max (or any) cdclk freq is really necessary
5500 * here, it belongs to modeset time
5501 */
5502 broxton_set_cdclk(dev, 624000);
5503
5504 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5505 POSTING_READ(DBUF_CTL);
5506
5507 udelay(10);
5508
5509 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5510 DRM_ERROR("DBuf power enable timeout!\n");
5511 }
5512
5513 void broxton_uninit_cdclk(struct drm_device *dev)
5514 {
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5518 POSTING_READ(DBUF_CTL);
5519
5520 udelay(10);
5521
5522 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5523 DRM_ERROR("DBuf power disable timeout!\n");
5524
5525 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5526 broxton_set_cdclk(dev, 19200);
5527
5528 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5529 }
5530
5531 static const struct skl_cdclk_entry {
5532 unsigned int freq;
5533 unsigned int vco;
5534 } skl_cdclk_frequencies[] = {
5535 { .freq = 308570, .vco = 8640 },
5536 { .freq = 337500, .vco = 8100 },
5537 { .freq = 432000, .vco = 8640 },
5538 { .freq = 450000, .vco = 8100 },
5539 { .freq = 540000, .vco = 8100 },
5540 { .freq = 617140, .vco = 8640 },
5541 { .freq = 675000, .vco = 8100 },
5542 };
5543
5544 static unsigned int skl_cdclk_decimal(unsigned int freq)
5545 {
5546 return (freq - 1000) / 500;
5547 }
5548
5549 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5550 {
5551 unsigned int i;
5552
5553 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5554 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5555
5556 if (e->freq == freq)
5557 return e->vco;
5558 }
5559
5560 return 8100;
5561 }
5562
5563 static void
5564 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5565 {
5566 unsigned int min_freq;
5567 u32 val;
5568
5569 /* select the minimum CDCLK before enabling DPLL 0 */
5570 val = I915_READ(CDCLK_CTL);
5571 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5572 val |= CDCLK_FREQ_337_308;
5573
5574 if (required_vco == 8640)
5575 min_freq = 308570;
5576 else
5577 min_freq = 337500;
5578
5579 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5580
5581 I915_WRITE(CDCLK_CTL, val);
5582 POSTING_READ(CDCLK_CTL);
5583
5584 /*
5585 * We always enable DPLL0 with the lowest link rate possible, but still
5586 * taking into account the VCO required to operate the eDP panel at the
5587 * desired frequency. The usual DP link rates operate with a VCO of
5588 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5589 * The modeset code is responsible for the selection of the exact link
5590 * rate later on, with the constraint of choosing a frequency that
5591 * works with required_vco.
5592 */
5593 val = I915_READ(DPLL_CTRL1);
5594
5595 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5596 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5597 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5598 if (required_vco == 8640)
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5600 SKL_DPLL0);
5601 else
5602 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5603 SKL_DPLL0);
5604
5605 I915_WRITE(DPLL_CTRL1, val);
5606 POSTING_READ(DPLL_CTRL1);
5607
5608 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5609
5610 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5611 DRM_ERROR("DPLL0 not locked\n");
5612 }
5613
5614 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5615 {
5616 int ret;
5617 u32 val;
5618
5619 /* inform PCU we want to change CDCLK */
5620 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5621 mutex_lock(&dev_priv->rps.hw_lock);
5622 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5623 mutex_unlock(&dev_priv->rps.hw_lock);
5624
5625 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5626 }
5627
5628 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5629 {
5630 unsigned int i;
5631
5632 for (i = 0; i < 15; i++) {
5633 if (skl_cdclk_pcu_ready(dev_priv))
5634 return true;
5635 udelay(10);
5636 }
5637
5638 return false;
5639 }
5640
5641 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5642 {
5643 u32 freq_select, pcu_ack;
5644
5645 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5646
5647 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5648 DRM_ERROR("failed to inform PCU about cdclk change\n");
5649 return;
5650 }
5651
5652 /* set CDCLK_CTL */
5653 switch(freq) {
5654 case 450000:
5655 case 432000:
5656 freq_select = CDCLK_FREQ_450_432;
5657 pcu_ack = 1;
5658 break;
5659 case 540000:
5660 freq_select = CDCLK_FREQ_540;
5661 pcu_ack = 2;
5662 break;
5663 case 308570:
5664 case 337500:
5665 default:
5666 freq_select = CDCLK_FREQ_337_308;
5667 pcu_ack = 0;
5668 break;
5669 case 617140:
5670 case 675000:
5671 freq_select = CDCLK_FREQ_675_617;
5672 pcu_ack = 3;
5673 break;
5674 }
5675
5676 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5677 POSTING_READ(CDCLK_CTL);
5678
5679 /* inform PCU of the change */
5680 mutex_lock(&dev_priv->rps.hw_lock);
5681 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5682 mutex_unlock(&dev_priv->rps.hw_lock);
5683 }
5684
5685 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5686 {
5687 /* disable DBUF power */
5688 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5689 POSTING_READ(DBUF_CTL);
5690
5691 udelay(10);
5692
5693 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5694 DRM_ERROR("DBuf power disable timeout\n");
5695
5696 /* disable DPLL0 */
5697 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5698 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5699 DRM_ERROR("Couldn't disable DPLL0\n");
5700
5701 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5702 }
5703
5704 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5705 {
5706 u32 val;
5707 unsigned int required_vco;
5708
5709 /* enable PCH reset handshake */
5710 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5711 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5712
5713 /* enable PG1 and Misc I/O */
5714 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5715
5716 /* DPLL0 already enabed !? */
5717 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5718 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5719 return;
5720 }
5721
5722 /* enable DPLL0 */
5723 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5724 skl_dpll0_enable(dev_priv, required_vco);
5725
5726 /* set CDCLK to the frequency the BIOS chose */
5727 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5728
5729 /* enable DBUF power */
5730 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5731 POSTING_READ(DBUF_CTL);
5732
5733 udelay(10);
5734
5735 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5736 DRM_ERROR("DBuf power enable timeout\n");
5737 }
5738
5739 /* returns HPLL frequency in kHz */
5740 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5741 {
5742 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5743
5744 /* Obtain SKU information */
5745 mutex_lock(&dev_priv->dpio_lock);
5746 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5747 CCK_FUSE_HPLL_FREQ_MASK;
5748 mutex_unlock(&dev_priv->dpio_lock);
5749
5750 return vco_freq[hpll_freq] * 1000;
5751 }
5752
5753 static void vlv_update_cdclk(struct drm_device *dev)
5754 {
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756
5757 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5758 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5759 dev_priv->cdclk_freq);
5760
5761 /*
5762 * Program the gmbus_freq based on the cdclk frequency.
5763 * BSpec erroneously claims we should aim for 4MHz, but
5764 * in fact 1MHz is the correct frequency.
5765 */
5766 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5767 }
5768
5769 /* Adjust CDclk dividers to allow high res or save power if possible */
5770 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5771 {
5772 struct drm_i915_private *dev_priv = dev->dev_private;
5773 u32 val, cmd;
5774
5775 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5776 != dev_priv->cdclk_freq);
5777
5778 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5779 cmd = 2;
5780 else if (cdclk == 266667)
5781 cmd = 1;
5782 else
5783 cmd = 0;
5784
5785 mutex_lock(&dev_priv->rps.hw_lock);
5786 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5787 val &= ~DSPFREQGUAR_MASK;
5788 val |= (cmd << DSPFREQGUAR_SHIFT);
5789 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5790 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5791 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5792 50)) {
5793 DRM_ERROR("timed out waiting for CDclk change\n");
5794 }
5795 mutex_unlock(&dev_priv->rps.hw_lock);
5796
5797 if (cdclk == 400000) {
5798 u32 divider;
5799
5800 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5801
5802 mutex_lock(&dev_priv->dpio_lock);
5803 /* adjust cdclk divider */
5804 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5805 val &= ~DISPLAY_FREQUENCY_VALUES;
5806 val |= divider;
5807 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5808
5809 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5810 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5811 50))
5812 DRM_ERROR("timed out waiting for CDclk change\n");
5813 mutex_unlock(&dev_priv->dpio_lock);
5814 }
5815
5816 mutex_lock(&dev_priv->dpio_lock);
5817 /* adjust self-refresh exit latency value */
5818 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5819 val &= ~0x7f;
5820
5821 /*
5822 * For high bandwidth configs, we set a higher latency in the bunit
5823 * so that the core display fetch happens in time to avoid underruns.
5824 */
5825 if (cdclk == 400000)
5826 val |= 4500 / 250; /* 4.5 usec */
5827 else
5828 val |= 3000 / 250; /* 3.0 usec */
5829 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5830 mutex_unlock(&dev_priv->dpio_lock);
5831
5832 vlv_update_cdclk(dev);
5833 }
5834
5835 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5836 {
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 u32 val, cmd;
5839
5840 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5841 != dev_priv->cdclk_freq);
5842
5843 switch (cdclk) {
5844 case 333333:
5845 case 320000:
5846 case 266667:
5847 case 200000:
5848 break;
5849 default:
5850 MISSING_CASE(cdclk);
5851 return;
5852 }
5853
5854 /*
5855 * Specs are full of misinformation, but testing on actual
5856 * hardware has shown that we just need to write the desired
5857 * CCK divider into the Punit register.
5858 */
5859 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5860
5861 mutex_lock(&dev_priv->rps.hw_lock);
5862 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5863 val &= ~DSPFREQGUAR_MASK_CHV;
5864 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5865 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5866 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5867 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5868 50)) {
5869 DRM_ERROR("timed out waiting for CDclk change\n");
5870 }
5871 mutex_unlock(&dev_priv->rps.hw_lock);
5872
5873 vlv_update_cdclk(dev);
5874 }
5875
5876 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5877 int max_pixclk)
5878 {
5879 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5880 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5881
5882 /*
5883 * Really only a few cases to deal with, as only 4 CDclks are supported:
5884 * 200MHz
5885 * 267MHz
5886 * 320/333MHz (depends on HPLL freq)
5887 * 400MHz (VLV only)
5888 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5889 * of the lower bin and adjust if needed.
5890 *
5891 * We seem to get an unstable or solid color picture at 200MHz.
5892 * Not sure what's wrong. For now use 200MHz only when all pipes
5893 * are off.
5894 */
5895 if (!IS_CHERRYVIEW(dev_priv) &&
5896 max_pixclk > freq_320*limit/100)
5897 return 400000;
5898 else if (max_pixclk > 266667*limit/100)
5899 return freq_320;
5900 else if (max_pixclk > 0)
5901 return 266667;
5902 else
5903 return 200000;
5904 }
5905
5906 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5907 int max_pixclk)
5908 {
5909 /*
5910 * FIXME:
5911 * - remove the guardband, it's not needed on BXT
5912 * - set 19.2MHz bypass frequency if there are no active pipes
5913 */
5914 if (max_pixclk > 576000*9/10)
5915 return 624000;
5916 else if (max_pixclk > 384000*9/10)
5917 return 576000;
5918 else if (max_pixclk > 288000*9/10)
5919 return 384000;
5920 else if (max_pixclk > 144000*9/10)
5921 return 288000;
5922 else
5923 return 144000;
5924 }
5925
5926 /* Compute the max pixel clock for new configuration. Uses atomic state if
5927 * that's non-NULL, look at current state otherwise. */
5928 static int intel_mode_max_pixclk(struct drm_device *dev,
5929 struct drm_atomic_state *state)
5930 {
5931 struct intel_crtc *intel_crtc;
5932 struct intel_crtc_state *crtc_state;
5933 int max_pixclk = 0;
5934
5935 for_each_intel_crtc(dev, intel_crtc) {
5936 if (state)
5937 crtc_state =
5938 intel_atomic_get_crtc_state(state, intel_crtc);
5939 else
5940 crtc_state = intel_crtc->config;
5941 if (IS_ERR(crtc_state))
5942 return PTR_ERR(crtc_state);
5943
5944 if (!crtc_state->base.enable)
5945 continue;
5946
5947 max_pixclk = max(max_pixclk,
5948 crtc_state->base.adjusted_mode.crtc_clock);
5949 }
5950
5951 return max_pixclk;
5952 }
5953
5954 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5955 {
5956 struct drm_i915_private *dev_priv = to_i915(state->dev);
5957 struct drm_crtc *crtc;
5958 struct drm_crtc_state *crtc_state;
5959 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5960 int cdclk, i;
5961
5962 if (max_pixclk < 0)
5963 return max_pixclk;
5964
5965 if (IS_VALLEYVIEW(dev_priv))
5966 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5967 else
5968 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5969
5970 if (cdclk == dev_priv->cdclk_freq)
5971 return 0;
5972
5973 /* add all active pipes to the state */
5974 for_each_crtc(state->dev, crtc) {
5975 if (!crtc->state->enable)
5976 continue;
5977
5978 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5979 if (IS_ERR(crtc_state))
5980 return PTR_ERR(crtc_state);
5981 }
5982
5983 /* disable/enable all currently active pipes while we change cdclk */
5984 for_each_crtc_in_state(state, crtc, crtc_state, i)
5985 if (crtc_state->enable)
5986 crtc_state->mode_changed = true;
5987
5988 return 0;
5989 }
5990
5991 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5992 {
5993 unsigned int credits, default_credits;
5994
5995 if (IS_CHERRYVIEW(dev_priv))
5996 default_credits = PFI_CREDIT(12);
5997 else
5998 default_credits = PFI_CREDIT(8);
5999
6000 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
6001 /* CHV suggested value is 31 or 63 */
6002 if (IS_CHERRYVIEW(dev_priv))
6003 credits = PFI_CREDIT_31;
6004 else
6005 credits = PFI_CREDIT(15);
6006 } else {
6007 credits = default_credits;
6008 }
6009
6010 /*
6011 * WA - write default credits before re-programming
6012 * FIXME: should we also set the resend bit here?
6013 */
6014 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6015 default_credits);
6016
6017 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6018 credits | PFI_CREDIT_RESEND);
6019
6020 /*
6021 * FIXME is this guaranteed to clear
6022 * immediately or should we poll for it?
6023 */
6024 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6025 }
6026
6027 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6028 {
6029 struct drm_device *dev = old_state->dev;
6030 struct drm_i915_private *dev_priv = dev->dev_private;
6031 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6032 int req_cdclk;
6033
6034 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6035 * never fail. */
6036 if (WARN_ON(max_pixclk < 0))
6037 return;
6038
6039 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6040
6041 if (req_cdclk != dev_priv->cdclk_freq) {
6042 /*
6043 * FIXME: We can end up here with all power domains off, yet
6044 * with a CDCLK frequency other than the minimum. To account
6045 * for this take the PIPE-A power domain, which covers the HW
6046 * blocks needed for the following programming. This can be
6047 * removed once it's guaranteed that we get here either with
6048 * the minimum CDCLK set, or the required power domains
6049 * enabled.
6050 */
6051 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6052
6053 if (IS_CHERRYVIEW(dev))
6054 cherryview_set_cdclk(dev, req_cdclk);
6055 else
6056 valleyview_set_cdclk(dev, req_cdclk);
6057
6058 vlv_program_pfi_credits(dev_priv);
6059
6060 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6061 }
6062 }
6063
6064 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6065 {
6066 struct drm_device *dev = crtc->dev;
6067 struct drm_i915_private *dev_priv = to_i915(dev);
6068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6069 struct intel_encoder *encoder;
6070 int pipe = intel_crtc->pipe;
6071 bool is_dsi;
6072
6073 WARN_ON(!crtc->state->enable);
6074
6075 if (intel_crtc->active)
6076 return;
6077
6078 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6079
6080 if (!is_dsi) {
6081 if (IS_CHERRYVIEW(dev))
6082 chv_prepare_pll(intel_crtc, intel_crtc->config);
6083 else
6084 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6085 }
6086
6087 if (intel_crtc->config->has_dp_encoder)
6088 intel_dp_set_m_n(intel_crtc, M1_N1);
6089
6090 intel_set_pipe_timings(intel_crtc);
6091
6092 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094
6095 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6096 I915_WRITE(CHV_CANVAS(pipe), 0);
6097 }
6098
6099 i9xx_set_pipeconf(intel_crtc);
6100
6101 intel_crtc->active = true;
6102
6103 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6104
6105 for_each_encoder_on_crtc(dev, crtc, encoder)
6106 if (encoder->pre_pll_enable)
6107 encoder->pre_pll_enable(encoder);
6108
6109 if (!is_dsi) {
6110 if (IS_CHERRYVIEW(dev))
6111 chv_enable_pll(intel_crtc, intel_crtc->config);
6112 else
6113 vlv_enable_pll(intel_crtc, intel_crtc->config);
6114 }
6115
6116 for_each_encoder_on_crtc(dev, crtc, encoder)
6117 if (encoder->pre_enable)
6118 encoder->pre_enable(encoder);
6119
6120 i9xx_pfit_enable(intel_crtc);
6121
6122 intel_crtc_load_lut(crtc);
6123
6124 intel_update_watermarks(crtc);
6125 intel_enable_pipe(intel_crtc);
6126
6127 assert_vblank_disabled(crtc);
6128 drm_crtc_vblank_on(crtc);
6129
6130 for_each_encoder_on_crtc(dev, crtc, encoder)
6131 encoder->enable(encoder);
6132 }
6133
6134 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6135 {
6136 struct drm_device *dev = crtc->base.dev;
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6138
6139 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6140 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6141 }
6142
6143 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6144 {
6145 struct drm_device *dev = crtc->dev;
6146 struct drm_i915_private *dev_priv = to_i915(dev);
6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148 struct intel_encoder *encoder;
6149 int pipe = intel_crtc->pipe;
6150
6151 WARN_ON(!crtc->state->enable);
6152
6153 if (intel_crtc->active)
6154 return;
6155
6156 i9xx_set_pll_dividers(intel_crtc);
6157
6158 if (intel_crtc->config->has_dp_encoder)
6159 intel_dp_set_m_n(intel_crtc, M1_N1);
6160
6161 intel_set_pipe_timings(intel_crtc);
6162
6163 i9xx_set_pipeconf(intel_crtc);
6164
6165 intel_crtc->active = true;
6166
6167 if (!IS_GEN2(dev))
6168 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6169
6170 for_each_encoder_on_crtc(dev, crtc, encoder)
6171 if (encoder->pre_enable)
6172 encoder->pre_enable(encoder);
6173
6174 i9xx_enable_pll(intel_crtc);
6175
6176 i9xx_pfit_enable(intel_crtc);
6177
6178 intel_crtc_load_lut(crtc);
6179
6180 intel_update_watermarks(crtc);
6181 intel_enable_pipe(intel_crtc);
6182
6183 assert_vblank_disabled(crtc);
6184 drm_crtc_vblank_on(crtc);
6185
6186 for_each_encoder_on_crtc(dev, crtc, encoder)
6187 encoder->enable(encoder);
6188 }
6189
6190 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6191 {
6192 struct drm_device *dev = crtc->base.dev;
6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194
6195 if (!crtc->config->gmch_pfit.control)
6196 return;
6197
6198 assert_pipe_disabled(dev_priv, crtc->pipe);
6199
6200 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6201 I915_READ(PFIT_CONTROL));
6202 I915_WRITE(PFIT_CONTROL, 0);
6203 }
6204
6205 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6206 {
6207 struct drm_device *dev = crtc->dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 struct intel_encoder *encoder;
6211 int pipe = intel_crtc->pipe;
6212
6213 if (!intel_crtc->active)
6214 return;
6215
6216 /*
6217 * On gen2 planes are double buffered but the pipe isn't, so we must
6218 * wait for planes to fully turn off before disabling the pipe.
6219 * We also need to wait on all gmch platforms because of the
6220 * self-refresh mode constraint explained above.
6221 */
6222 intel_wait_for_vblank(dev, pipe);
6223
6224 for_each_encoder_on_crtc(dev, crtc, encoder)
6225 encoder->disable(encoder);
6226
6227 drm_crtc_vblank_off(crtc);
6228 assert_vblank_disabled(crtc);
6229
6230 intel_disable_pipe(intel_crtc);
6231
6232 i9xx_pfit_disable(intel_crtc);
6233
6234 for_each_encoder_on_crtc(dev, crtc, encoder)
6235 if (encoder->post_disable)
6236 encoder->post_disable(encoder);
6237
6238 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6239 if (IS_CHERRYVIEW(dev))
6240 chv_disable_pll(dev_priv, pipe);
6241 else if (IS_VALLEYVIEW(dev))
6242 vlv_disable_pll(dev_priv, pipe);
6243 else
6244 i9xx_disable_pll(intel_crtc);
6245 }
6246
6247 if (!IS_GEN2(dev))
6248 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6249
6250 intel_crtc->active = false;
6251 intel_update_watermarks(crtc);
6252
6253 mutex_lock(&dev->struct_mutex);
6254 intel_fbc_update(dev);
6255 mutex_unlock(&dev->struct_mutex);
6256 }
6257
6258 static void i9xx_crtc_off(struct drm_crtc *crtc)
6259 {
6260 }
6261
6262 /* Master function to enable/disable CRTC and corresponding power wells */
6263 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6264 {
6265 struct drm_device *dev = crtc->dev;
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268 enum intel_display_power_domain domain;
6269 unsigned long domains;
6270
6271 if (enable) {
6272 if (!intel_crtc->active) {
6273 domains = get_crtc_power_domains(crtc);
6274 for_each_power_domain(domain, domains)
6275 intel_display_power_get(dev_priv, domain);
6276 intel_crtc->enabled_power_domains = domains;
6277
6278 dev_priv->display.crtc_enable(crtc);
6279 intel_crtc_enable_planes(crtc);
6280 }
6281 } else {
6282 if (intel_crtc->active) {
6283 intel_crtc_disable_planes(crtc);
6284 dev_priv->display.crtc_disable(crtc);
6285
6286 domains = intel_crtc->enabled_power_domains;
6287 for_each_power_domain(domain, domains)
6288 intel_display_power_put(dev_priv, domain);
6289 intel_crtc->enabled_power_domains = 0;
6290 }
6291 }
6292 }
6293
6294 /**
6295 * Sets the power management mode of the pipe and plane.
6296 */
6297 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6298 {
6299 struct drm_device *dev = crtc->dev;
6300 struct intel_encoder *intel_encoder;
6301 bool enable = false;
6302
6303 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6304 enable |= intel_encoder->connectors_active;
6305
6306 intel_crtc_control(crtc, enable);
6307
6308 crtc->state->active = enable;
6309 }
6310
6311 static void intel_crtc_disable(struct drm_crtc *crtc)
6312 {
6313 struct drm_device *dev = crtc->dev;
6314 struct drm_connector *connector;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316
6317 /* crtc should still be enabled when we disable it. */
6318 WARN_ON(!crtc->state->enable);
6319
6320 intel_crtc_disable_planes(crtc);
6321 dev_priv->display.crtc_disable(crtc);
6322 dev_priv->display.off(crtc);
6323
6324 drm_plane_helper_disable(crtc->primary);
6325
6326 /* Update computed state. */
6327 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6328 if (!connector->encoder || !connector->encoder->crtc)
6329 continue;
6330
6331 if (connector->encoder->crtc != crtc)
6332 continue;
6333
6334 connector->dpms = DRM_MODE_DPMS_OFF;
6335 to_intel_encoder(connector->encoder)->connectors_active = false;
6336 }
6337 }
6338
6339 void intel_encoder_destroy(struct drm_encoder *encoder)
6340 {
6341 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6342
6343 drm_encoder_cleanup(encoder);
6344 kfree(intel_encoder);
6345 }
6346
6347 /* Simple dpms helper for encoders with just one connector, no cloning and only
6348 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6349 * state of the entire output pipe. */
6350 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6351 {
6352 if (mode == DRM_MODE_DPMS_ON) {
6353 encoder->connectors_active = true;
6354
6355 intel_crtc_update_dpms(encoder->base.crtc);
6356 } else {
6357 encoder->connectors_active = false;
6358
6359 intel_crtc_update_dpms(encoder->base.crtc);
6360 }
6361 }
6362
6363 /* Cross check the actual hw state with our own modeset state tracking (and it's
6364 * internal consistency). */
6365 static void intel_connector_check_state(struct intel_connector *connector)
6366 {
6367 if (connector->get_hw_state(connector)) {
6368 struct intel_encoder *encoder = connector->encoder;
6369 struct drm_crtc *crtc;
6370 bool encoder_enabled;
6371 enum pipe pipe;
6372
6373 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6374 connector->base.base.id,
6375 connector->base.name);
6376
6377 /* there is no real hw state for MST connectors */
6378 if (connector->mst_port)
6379 return;
6380
6381 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6382 "wrong connector dpms state\n");
6383 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6384 "active connector not linked to encoder\n");
6385
6386 if (encoder) {
6387 I915_STATE_WARN(!encoder->connectors_active,
6388 "encoder->connectors_active not set\n");
6389
6390 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6391 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6392 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6393 return;
6394
6395 crtc = encoder->base.crtc;
6396
6397 I915_STATE_WARN(!crtc->state->enable,
6398 "crtc not enabled\n");
6399 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6400 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6401 "encoder active on the wrong pipe\n");
6402 }
6403 }
6404 }
6405
6406 int intel_connector_init(struct intel_connector *connector)
6407 {
6408 struct drm_connector_state *connector_state;
6409
6410 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6411 if (!connector_state)
6412 return -ENOMEM;
6413
6414 connector->base.state = connector_state;
6415 return 0;
6416 }
6417
6418 struct intel_connector *intel_connector_alloc(void)
6419 {
6420 struct intel_connector *connector;
6421
6422 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6423 if (!connector)
6424 return NULL;
6425
6426 if (intel_connector_init(connector) < 0) {
6427 kfree(connector);
6428 return NULL;
6429 }
6430
6431 return connector;
6432 }
6433
6434 /* Even simpler default implementation, if there's really no special case to
6435 * consider. */
6436 void intel_connector_dpms(struct drm_connector *connector, int mode)
6437 {
6438 /* All the simple cases only support two dpms states. */
6439 if (mode != DRM_MODE_DPMS_ON)
6440 mode = DRM_MODE_DPMS_OFF;
6441
6442 if (mode == connector->dpms)
6443 return;
6444
6445 connector->dpms = mode;
6446
6447 /* Only need to change hw state when actually enabled */
6448 if (connector->encoder)
6449 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6450
6451 intel_modeset_check_state(connector->dev);
6452 }
6453
6454 /* Simple connector->get_hw_state implementation for encoders that support only
6455 * one connector and no cloning and hence the encoder state determines the state
6456 * of the connector. */
6457 bool intel_connector_get_hw_state(struct intel_connector *connector)
6458 {
6459 enum pipe pipe = 0;
6460 struct intel_encoder *encoder = connector->encoder;
6461
6462 return encoder->get_hw_state(encoder, &pipe);
6463 }
6464
6465 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6466 {
6467 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6468 return crtc_state->fdi_lanes;
6469
6470 return 0;
6471 }
6472
6473 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6474 struct intel_crtc_state *pipe_config)
6475 {
6476 struct drm_atomic_state *state = pipe_config->base.state;
6477 struct intel_crtc *other_crtc;
6478 struct intel_crtc_state *other_crtc_state;
6479
6480 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6481 pipe_name(pipe), pipe_config->fdi_lanes);
6482 if (pipe_config->fdi_lanes > 4) {
6483 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6484 pipe_name(pipe), pipe_config->fdi_lanes);
6485 return -EINVAL;
6486 }
6487
6488 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6489 if (pipe_config->fdi_lanes > 2) {
6490 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6491 pipe_config->fdi_lanes);
6492 return -EINVAL;
6493 } else {
6494 return 0;
6495 }
6496 }
6497
6498 if (INTEL_INFO(dev)->num_pipes == 2)
6499 return 0;
6500
6501 /* Ivybridge 3 pipe is really complicated */
6502 switch (pipe) {
6503 case PIPE_A:
6504 return 0;
6505 case PIPE_B:
6506 if (pipe_config->fdi_lanes <= 2)
6507 return 0;
6508
6509 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6510 other_crtc_state =
6511 intel_atomic_get_crtc_state(state, other_crtc);
6512 if (IS_ERR(other_crtc_state))
6513 return PTR_ERR(other_crtc_state);
6514
6515 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6516 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6517 pipe_name(pipe), pipe_config->fdi_lanes);
6518 return -EINVAL;
6519 }
6520 return 0;
6521 case PIPE_C:
6522 if (pipe_config->fdi_lanes > 2) {
6523 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6524 pipe_name(pipe), pipe_config->fdi_lanes);
6525 return -EINVAL;
6526 }
6527
6528 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6529 other_crtc_state =
6530 intel_atomic_get_crtc_state(state, other_crtc);
6531 if (IS_ERR(other_crtc_state))
6532 return PTR_ERR(other_crtc_state);
6533
6534 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6535 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6536 return -EINVAL;
6537 }
6538 return 0;
6539 default:
6540 BUG();
6541 }
6542 }
6543
6544 #define RETRY 1
6545 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6546 struct intel_crtc_state *pipe_config)
6547 {
6548 struct drm_device *dev = intel_crtc->base.dev;
6549 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6550 int lane, link_bw, fdi_dotclock, ret;
6551 bool needs_recompute = false;
6552
6553 retry:
6554 /* FDI is a binary signal running at ~2.7GHz, encoding
6555 * each output octet as 10 bits. The actual frequency
6556 * is stored as a divider into a 100MHz clock, and the
6557 * mode pixel clock is stored in units of 1KHz.
6558 * Hence the bw of each lane in terms of the mode signal
6559 * is:
6560 */
6561 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6562
6563 fdi_dotclock = adjusted_mode->crtc_clock;
6564
6565 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6566 pipe_config->pipe_bpp);
6567
6568 pipe_config->fdi_lanes = lane;
6569
6570 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6571 link_bw, &pipe_config->fdi_m_n);
6572
6573 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6574 intel_crtc->pipe, pipe_config);
6575 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6576 pipe_config->pipe_bpp -= 2*3;
6577 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6578 pipe_config->pipe_bpp);
6579 needs_recompute = true;
6580 pipe_config->bw_constrained = true;
6581
6582 goto retry;
6583 }
6584
6585 if (needs_recompute)
6586 return RETRY;
6587
6588 return ret;
6589 }
6590
6591 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6592 struct intel_crtc_state *pipe_config)
6593 {
6594 pipe_config->ips_enabled = i915.enable_ips &&
6595 hsw_crtc_supports_ips(crtc) &&
6596 pipe_config->pipe_bpp <= 24;
6597 }
6598
6599 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6600 struct intel_crtc_state *pipe_config)
6601 {
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = dev->dev_private;
6604 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6605 int ret;
6606
6607 /* FIXME should check pixel clock limits on all platforms */
6608 if (INTEL_INFO(dev)->gen < 4) {
6609 int clock_limit =
6610 dev_priv->display.get_display_clock_speed(dev);
6611
6612 /*
6613 * Enable pixel doubling when the dot clock
6614 * is > 90% of the (display) core speed.
6615 *
6616 * GDG double wide on either pipe,
6617 * otherwise pipe A only.
6618 */
6619 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6620 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6621 clock_limit *= 2;
6622 pipe_config->double_wide = true;
6623 }
6624
6625 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6626 return -EINVAL;
6627 }
6628
6629 /*
6630 * Pipe horizontal size must be even in:
6631 * - DVO ganged mode
6632 * - LVDS dual channel mode
6633 * - Double wide pipe
6634 */
6635 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6636 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6637 pipe_config->pipe_src_w &= ~1;
6638
6639 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6640 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6641 */
6642 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6643 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6644 return -EINVAL;
6645
6646 if (HAS_IPS(dev))
6647 hsw_compute_ips_config(crtc, pipe_config);
6648
6649 if (pipe_config->has_pch_encoder)
6650 return ironlake_fdi_compute_config(crtc, pipe_config);
6651
6652 /* FIXME: remove below call once atomic mode set is place and all crtc
6653 * related checks called from atomic_crtc_check function */
6654 ret = 0;
6655 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6656 crtc, pipe_config->base.state);
6657 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6658
6659 return ret;
6660 }
6661
6662 static int skylake_get_display_clock_speed(struct drm_device *dev)
6663 {
6664 struct drm_i915_private *dev_priv = to_i915(dev);
6665 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6666 uint32_t cdctl = I915_READ(CDCLK_CTL);
6667 uint32_t linkrate;
6668
6669 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6670 WARN(1, "LCPLL1 not enabled\n");
6671 return 24000; /* 24MHz is the cd freq with NSSC ref */
6672 }
6673
6674 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6675 return 540000;
6676
6677 linkrate = (I915_READ(DPLL_CTRL1) &
6678 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6679
6680 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6681 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6682 /* vco 8640 */
6683 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6684 case CDCLK_FREQ_450_432:
6685 return 432000;
6686 case CDCLK_FREQ_337_308:
6687 return 308570;
6688 case CDCLK_FREQ_675_617:
6689 return 617140;
6690 default:
6691 WARN(1, "Unknown cd freq selection\n");
6692 }
6693 } else {
6694 /* vco 8100 */
6695 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6696 case CDCLK_FREQ_450_432:
6697 return 450000;
6698 case CDCLK_FREQ_337_308:
6699 return 337500;
6700 case CDCLK_FREQ_675_617:
6701 return 675000;
6702 default:
6703 WARN(1, "Unknown cd freq selection\n");
6704 }
6705 }
6706
6707 /* error case, do as if DPLL0 isn't enabled */
6708 return 24000;
6709 }
6710
6711 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6712 {
6713 struct drm_i915_private *dev_priv = dev->dev_private;
6714 uint32_t lcpll = I915_READ(LCPLL_CTL);
6715 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6716
6717 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6718 return 800000;
6719 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6720 return 450000;
6721 else if (freq == LCPLL_CLK_FREQ_450)
6722 return 450000;
6723 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6724 return 540000;
6725 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6726 return 337500;
6727 else
6728 return 675000;
6729 }
6730
6731 static int haswell_get_display_clock_speed(struct drm_device *dev)
6732 {
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 uint32_t lcpll = I915_READ(LCPLL_CTL);
6735 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6736
6737 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6738 return 800000;
6739 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6740 return 450000;
6741 else if (freq == LCPLL_CLK_FREQ_450)
6742 return 450000;
6743 else if (IS_HSW_ULT(dev))
6744 return 337500;
6745 else
6746 return 540000;
6747 }
6748
6749 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6750 {
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 u32 val;
6753 int divider;
6754
6755 if (dev_priv->hpll_freq == 0)
6756 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6757
6758 mutex_lock(&dev_priv->dpio_lock);
6759 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6760 mutex_unlock(&dev_priv->dpio_lock);
6761
6762 divider = val & DISPLAY_FREQUENCY_VALUES;
6763
6764 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6765 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6766 "cdclk change in progress\n");
6767
6768 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6769 }
6770
6771 static int ilk_get_display_clock_speed(struct drm_device *dev)
6772 {
6773 return 450000;
6774 }
6775
6776 static int i945_get_display_clock_speed(struct drm_device *dev)
6777 {
6778 return 400000;
6779 }
6780
6781 static int i915_get_display_clock_speed(struct drm_device *dev)
6782 {
6783 return 333333;
6784 }
6785
6786 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6787 {
6788 return 200000;
6789 }
6790
6791 static int pnv_get_display_clock_speed(struct drm_device *dev)
6792 {
6793 u16 gcfgc = 0;
6794
6795 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6796
6797 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6798 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6799 return 266667;
6800 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6801 return 333333;
6802 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6803 return 444444;
6804 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6805 return 200000;
6806 default:
6807 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6808 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6809 return 133333;
6810 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6811 return 166667;
6812 }
6813 }
6814
6815 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6816 {
6817 u16 gcfgc = 0;
6818
6819 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6820
6821 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6822 return 133333;
6823 else {
6824 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6825 case GC_DISPLAY_CLOCK_333_MHZ:
6826 return 333333;
6827 default:
6828 case GC_DISPLAY_CLOCK_190_200_MHZ:
6829 return 190000;
6830 }
6831 }
6832 }
6833
6834 static int i865_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 return 266667;
6837 }
6838
6839 static int i855_get_display_clock_speed(struct drm_device *dev)
6840 {
6841 u16 hpllcc = 0;
6842 /* Assume that the hardware is in the high speed state. This
6843 * should be the default.
6844 */
6845 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6846 case GC_CLOCK_133_200:
6847 case GC_CLOCK_100_200:
6848 return 200000;
6849 case GC_CLOCK_166_250:
6850 return 250000;
6851 case GC_CLOCK_100_133:
6852 return 133333;
6853 }
6854
6855 /* Shouldn't happen */
6856 return 0;
6857 }
6858
6859 static int i830_get_display_clock_speed(struct drm_device *dev)
6860 {
6861 return 133333;
6862 }
6863
6864 static void
6865 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6866 {
6867 while (*num > DATA_LINK_M_N_MASK ||
6868 *den > DATA_LINK_M_N_MASK) {
6869 *num >>= 1;
6870 *den >>= 1;
6871 }
6872 }
6873
6874 static void compute_m_n(unsigned int m, unsigned int n,
6875 uint32_t *ret_m, uint32_t *ret_n)
6876 {
6877 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6878 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6879 intel_reduce_m_n_ratio(ret_m, ret_n);
6880 }
6881
6882 void
6883 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6884 int pixel_clock, int link_clock,
6885 struct intel_link_m_n *m_n)
6886 {
6887 m_n->tu = 64;
6888
6889 compute_m_n(bits_per_pixel * pixel_clock,
6890 link_clock * nlanes * 8,
6891 &m_n->gmch_m, &m_n->gmch_n);
6892
6893 compute_m_n(pixel_clock, link_clock,
6894 &m_n->link_m, &m_n->link_n);
6895 }
6896
6897 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6898 {
6899 if (i915.panel_use_ssc >= 0)
6900 return i915.panel_use_ssc != 0;
6901 return dev_priv->vbt.lvds_use_ssc
6902 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6903 }
6904
6905 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6906 int num_connectors)
6907 {
6908 struct drm_device *dev = crtc_state->base.crtc->dev;
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910 int refclk;
6911
6912 WARN_ON(!crtc_state->base.state);
6913
6914 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6915 refclk = 100000;
6916 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6917 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6918 refclk = dev_priv->vbt.lvds_ssc_freq;
6919 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6920 } else if (!IS_GEN2(dev)) {
6921 refclk = 96000;
6922 } else {
6923 refclk = 48000;
6924 }
6925
6926 return refclk;
6927 }
6928
6929 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6930 {
6931 return (1 << dpll->n) << 16 | dpll->m2;
6932 }
6933
6934 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6935 {
6936 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6937 }
6938
6939 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6940 struct intel_crtc_state *crtc_state,
6941 intel_clock_t *reduced_clock)
6942 {
6943 struct drm_device *dev = crtc->base.dev;
6944 u32 fp, fp2 = 0;
6945
6946 if (IS_PINEVIEW(dev)) {
6947 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6948 if (reduced_clock)
6949 fp2 = pnv_dpll_compute_fp(reduced_clock);
6950 } else {
6951 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6952 if (reduced_clock)
6953 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6954 }
6955
6956 crtc_state->dpll_hw_state.fp0 = fp;
6957
6958 crtc->lowfreq_avail = false;
6959 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6960 reduced_clock) {
6961 crtc_state->dpll_hw_state.fp1 = fp2;
6962 crtc->lowfreq_avail = true;
6963 } else {
6964 crtc_state->dpll_hw_state.fp1 = fp;
6965 }
6966 }
6967
6968 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6969 pipe)
6970 {
6971 u32 reg_val;
6972
6973 /*
6974 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6975 * and set it to a reasonable value instead.
6976 */
6977 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6978 reg_val &= 0xffffff00;
6979 reg_val |= 0x00000030;
6980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6981
6982 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6983 reg_val &= 0x8cffffff;
6984 reg_val = 0x8c000000;
6985 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6986
6987 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6988 reg_val &= 0xffffff00;
6989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6990
6991 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6992 reg_val &= 0x00ffffff;
6993 reg_val |= 0xb0000000;
6994 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6995 }
6996
6997 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6998 struct intel_link_m_n *m_n)
6999 {
7000 struct drm_device *dev = crtc->base.dev;
7001 struct drm_i915_private *dev_priv = dev->dev_private;
7002 int pipe = crtc->pipe;
7003
7004 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7005 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7006 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7007 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7008 }
7009
7010 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7011 struct intel_link_m_n *m_n,
7012 struct intel_link_m_n *m2_n2)
7013 {
7014 struct drm_device *dev = crtc->base.dev;
7015 struct drm_i915_private *dev_priv = dev->dev_private;
7016 int pipe = crtc->pipe;
7017 enum transcoder transcoder = crtc->config->cpu_transcoder;
7018
7019 if (INTEL_INFO(dev)->gen >= 5) {
7020 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7021 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7022 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7023 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7024 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7025 * for gen < 8) and if DRRS is supported (to make sure the
7026 * registers are not unnecessarily accessed).
7027 */
7028 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7029 crtc->config->has_drrs) {
7030 I915_WRITE(PIPE_DATA_M2(transcoder),
7031 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7032 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7033 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7034 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7035 }
7036 } else {
7037 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7038 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7039 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7040 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7041 }
7042 }
7043
7044 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7045 {
7046 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7047
7048 if (m_n == M1_N1) {
7049 dp_m_n = &crtc->config->dp_m_n;
7050 dp_m2_n2 = &crtc->config->dp_m2_n2;
7051 } else if (m_n == M2_N2) {
7052
7053 /*
7054 * M2_N2 registers are not supported. Hence m2_n2 divider value
7055 * needs to be programmed into M1_N1.
7056 */
7057 dp_m_n = &crtc->config->dp_m2_n2;
7058 } else {
7059 DRM_ERROR("Unsupported divider value\n");
7060 return;
7061 }
7062
7063 if (crtc->config->has_pch_encoder)
7064 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7065 else
7066 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7067 }
7068
7069 static void vlv_update_pll(struct intel_crtc *crtc,
7070 struct intel_crtc_state *pipe_config)
7071 {
7072 u32 dpll, dpll_md;
7073
7074 /*
7075 * Enable DPIO clock input. We should never disable the reference
7076 * clock for pipe B, since VGA hotplug / manual detection depends
7077 * on it.
7078 */
7079 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7080 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7081 /* We should never disable this, set it here for state tracking */
7082 if (crtc->pipe == PIPE_B)
7083 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7084 dpll |= DPLL_VCO_ENABLE;
7085 pipe_config->dpll_hw_state.dpll = dpll;
7086
7087 dpll_md = (pipe_config->pixel_multiplier - 1)
7088 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7089 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7090 }
7091
7092 static void vlv_prepare_pll(struct intel_crtc *crtc,
7093 const struct intel_crtc_state *pipe_config)
7094 {
7095 struct drm_device *dev = crtc->base.dev;
7096 struct drm_i915_private *dev_priv = dev->dev_private;
7097 int pipe = crtc->pipe;
7098 u32 mdiv;
7099 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7100 u32 coreclk, reg_val;
7101
7102 mutex_lock(&dev_priv->dpio_lock);
7103
7104 bestn = pipe_config->dpll.n;
7105 bestm1 = pipe_config->dpll.m1;
7106 bestm2 = pipe_config->dpll.m2;
7107 bestp1 = pipe_config->dpll.p1;
7108 bestp2 = pipe_config->dpll.p2;
7109
7110 /* See eDP HDMI DPIO driver vbios notes doc */
7111
7112 /* PLL B needs special handling */
7113 if (pipe == PIPE_B)
7114 vlv_pllb_recal_opamp(dev_priv, pipe);
7115
7116 /* Set up Tx target for periodic Rcomp update */
7117 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7118
7119 /* Disable target IRef on PLL */
7120 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7121 reg_val &= 0x00ffffff;
7122 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7123
7124 /* Disable fast lock */
7125 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7126
7127 /* Set idtafcrecal before PLL is enabled */
7128 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7129 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7130 mdiv |= ((bestn << DPIO_N_SHIFT));
7131 mdiv |= (1 << DPIO_K_SHIFT);
7132
7133 /*
7134 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7135 * but we don't support that).
7136 * Note: don't use the DAC post divider as it seems unstable.
7137 */
7138 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7139 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7140
7141 mdiv |= DPIO_ENABLE_CALIBRATION;
7142 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7143
7144 /* Set HBR and RBR LPF coefficients */
7145 if (pipe_config->port_clock == 162000 ||
7146 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7147 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7149 0x009f0003);
7150 else
7151 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7152 0x00d0000f);
7153
7154 if (pipe_config->has_dp_encoder) {
7155 /* Use SSC source */
7156 if (pipe == PIPE_A)
7157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7158 0x0df40000);
7159 else
7160 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7161 0x0df70000);
7162 } else { /* HDMI or VGA */
7163 /* Use bend source */
7164 if (pipe == PIPE_A)
7165 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7166 0x0df70000);
7167 else
7168 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7169 0x0df40000);
7170 }
7171
7172 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7173 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7174 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7175 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7176 coreclk |= 0x01000000;
7177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7178
7179 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7180 mutex_unlock(&dev_priv->dpio_lock);
7181 }
7182
7183 static void chv_update_pll(struct intel_crtc *crtc,
7184 struct intel_crtc_state *pipe_config)
7185 {
7186 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7187 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7188 DPLL_VCO_ENABLE;
7189 if (crtc->pipe != PIPE_A)
7190 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7191
7192 pipe_config->dpll_hw_state.dpll_md =
7193 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7194 }
7195
7196 static void chv_prepare_pll(struct intel_crtc *crtc,
7197 const struct intel_crtc_state *pipe_config)
7198 {
7199 struct drm_device *dev = crtc->base.dev;
7200 struct drm_i915_private *dev_priv = dev->dev_private;
7201 int pipe = crtc->pipe;
7202 int dpll_reg = DPLL(crtc->pipe);
7203 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7204 u32 loopfilter, tribuf_calcntr;
7205 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7206 u32 dpio_val;
7207 int vco;
7208
7209 bestn = pipe_config->dpll.n;
7210 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7211 bestm1 = pipe_config->dpll.m1;
7212 bestm2 = pipe_config->dpll.m2 >> 22;
7213 bestp1 = pipe_config->dpll.p1;
7214 bestp2 = pipe_config->dpll.p2;
7215 vco = pipe_config->dpll.vco;
7216 dpio_val = 0;
7217 loopfilter = 0;
7218
7219 /*
7220 * Enable Refclk and SSC
7221 */
7222 I915_WRITE(dpll_reg,
7223 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7224
7225 mutex_lock(&dev_priv->dpio_lock);
7226
7227 /* p1 and p2 divider */
7228 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7229 5 << DPIO_CHV_S1_DIV_SHIFT |
7230 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7231 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7232 1 << DPIO_CHV_K_DIV_SHIFT);
7233
7234 /* Feedback post-divider - m2 */
7235 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7236
7237 /* Feedback refclk divider - n and m1 */
7238 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7239 DPIO_CHV_M1_DIV_BY_2 |
7240 1 << DPIO_CHV_N_DIV_SHIFT);
7241
7242 /* M2 fraction division */
7243 if (bestm2_frac)
7244 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7245
7246 /* M2 fraction division enable */
7247 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7248 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7249 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7250 if (bestm2_frac)
7251 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7252 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7253
7254 /* Program digital lock detect threshold */
7255 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7256 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7257 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7258 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7259 if (!bestm2_frac)
7260 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7261 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7262
7263 /* Loop filter */
7264 if (vco == 5400000) {
7265 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7266 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7267 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7268 tribuf_calcntr = 0x9;
7269 } else if (vco <= 6200000) {
7270 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7271 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7272 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7273 tribuf_calcntr = 0x9;
7274 } else if (vco <= 6480000) {
7275 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7276 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7277 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7278 tribuf_calcntr = 0x8;
7279 } else {
7280 /* Not supported. Apply the same limits as in the max case */
7281 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7282 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7283 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7284 tribuf_calcntr = 0;
7285 }
7286 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7287
7288 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7289 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7290 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7291 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7292
7293 /* AFC Recal */
7294 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7295 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7296 DPIO_AFC_RECAL);
7297
7298 mutex_unlock(&dev_priv->dpio_lock);
7299 }
7300
7301 /**
7302 * vlv_force_pll_on - forcibly enable just the PLL
7303 * @dev_priv: i915 private structure
7304 * @pipe: pipe PLL to enable
7305 * @dpll: PLL configuration
7306 *
7307 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7308 * in cases where we need the PLL enabled even when @pipe is not going to
7309 * be enabled.
7310 */
7311 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7312 const struct dpll *dpll)
7313 {
7314 struct intel_crtc *crtc =
7315 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7316 struct intel_crtc_state pipe_config = {
7317 .base.crtc = &crtc->base,
7318 .pixel_multiplier = 1,
7319 .dpll = *dpll,
7320 };
7321
7322 if (IS_CHERRYVIEW(dev)) {
7323 chv_update_pll(crtc, &pipe_config);
7324 chv_prepare_pll(crtc, &pipe_config);
7325 chv_enable_pll(crtc, &pipe_config);
7326 } else {
7327 vlv_update_pll(crtc, &pipe_config);
7328 vlv_prepare_pll(crtc, &pipe_config);
7329 vlv_enable_pll(crtc, &pipe_config);
7330 }
7331 }
7332
7333 /**
7334 * vlv_force_pll_off - forcibly disable just the PLL
7335 * @dev_priv: i915 private structure
7336 * @pipe: pipe PLL to disable
7337 *
7338 * Disable the PLL for @pipe. To be used in cases where we need
7339 * the PLL enabled even when @pipe is not going to be enabled.
7340 */
7341 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7342 {
7343 if (IS_CHERRYVIEW(dev))
7344 chv_disable_pll(to_i915(dev), pipe);
7345 else
7346 vlv_disable_pll(to_i915(dev), pipe);
7347 }
7348
7349 static void i9xx_update_pll(struct intel_crtc *crtc,
7350 struct intel_crtc_state *crtc_state,
7351 intel_clock_t *reduced_clock,
7352 int num_connectors)
7353 {
7354 struct drm_device *dev = crtc->base.dev;
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 u32 dpll;
7357 bool is_sdvo;
7358 struct dpll *clock = &crtc_state->dpll;
7359
7360 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7361
7362 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7363 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7364
7365 dpll = DPLL_VGA_MODE_DIS;
7366
7367 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7368 dpll |= DPLLB_MODE_LVDS;
7369 else
7370 dpll |= DPLLB_MODE_DAC_SERIAL;
7371
7372 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7373 dpll |= (crtc_state->pixel_multiplier - 1)
7374 << SDVO_MULTIPLIER_SHIFT_HIRES;
7375 }
7376
7377 if (is_sdvo)
7378 dpll |= DPLL_SDVO_HIGH_SPEED;
7379
7380 if (crtc_state->has_dp_encoder)
7381 dpll |= DPLL_SDVO_HIGH_SPEED;
7382
7383 /* compute bitmask from p1 value */
7384 if (IS_PINEVIEW(dev))
7385 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7386 else {
7387 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7388 if (IS_G4X(dev) && reduced_clock)
7389 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7390 }
7391 switch (clock->p2) {
7392 case 5:
7393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7394 break;
7395 case 7:
7396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7397 break;
7398 case 10:
7399 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7400 break;
7401 case 14:
7402 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7403 break;
7404 }
7405 if (INTEL_INFO(dev)->gen >= 4)
7406 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7407
7408 if (crtc_state->sdvo_tv_clock)
7409 dpll |= PLL_REF_INPUT_TVCLKINBC;
7410 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7411 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7412 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7413 else
7414 dpll |= PLL_REF_INPUT_DREFCLK;
7415
7416 dpll |= DPLL_VCO_ENABLE;
7417 crtc_state->dpll_hw_state.dpll = dpll;
7418
7419 if (INTEL_INFO(dev)->gen >= 4) {
7420 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7421 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7422 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7423 }
7424 }
7425
7426 static void i8xx_update_pll(struct intel_crtc *crtc,
7427 struct intel_crtc_state *crtc_state,
7428 intel_clock_t *reduced_clock,
7429 int num_connectors)
7430 {
7431 struct drm_device *dev = crtc->base.dev;
7432 struct drm_i915_private *dev_priv = dev->dev_private;
7433 u32 dpll;
7434 struct dpll *clock = &crtc_state->dpll;
7435
7436 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7437
7438 dpll = DPLL_VGA_MODE_DIS;
7439
7440 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7441 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7442 } else {
7443 if (clock->p1 == 2)
7444 dpll |= PLL_P1_DIVIDE_BY_TWO;
7445 else
7446 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7447 if (clock->p2 == 4)
7448 dpll |= PLL_P2_DIVIDE_BY_4;
7449 }
7450
7451 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7452 dpll |= DPLL_DVO_2X_MODE;
7453
7454 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7455 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7456 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7457 else
7458 dpll |= PLL_REF_INPUT_DREFCLK;
7459
7460 dpll |= DPLL_VCO_ENABLE;
7461 crtc_state->dpll_hw_state.dpll = dpll;
7462 }
7463
7464 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7465 {
7466 struct drm_device *dev = intel_crtc->base.dev;
7467 struct drm_i915_private *dev_priv = dev->dev_private;
7468 enum pipe pipe = intel_crtc->pipe;
7469 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7470 struct drm_display_mode *adjusted_mode =
7471 &intel_crtc->config->base.adjusted_mode;
7472 uint32_t crtc_vtotal, crtc_vblank_end;
7473 int vsyncshift = 0;
7474
7475 /* We need to be careful not to changed the adjusted mode, for otherwise
7476 * the hw state checker will get angry at the mismatch. */
7477 crtc_vtotal = adjusted_mode->crtc_vtotal;
7478 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7479
7480 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7481 /* the chip adds 2 halflines automatically */
7482 crtc_vtotal -= 1;
7483 crtc_vblank_end -= 1;
7484
7485 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7486 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7487 else
7488 vsyncshift = adjusted_mode->crtc_hsync_start -
7489 adjusted_mode->crtc_htotal / 2;
7490 if (vsyncshift < 0)
7491 vsyncshift += adjusted_mode->crtc_htotal;
7492 }
7493
7494 if (INTEL_INFO(dev)->gen > 3)
7495 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7496
7497 I915_WRITE(HTOTAL(cpu_transcoder),
7498 (adjusted_mode->crtc_hdisplay - 1) |
7499 ((adjusted_mode->crtc_htotal - 1) << 16));
7500 I915_WRITE(HBLANK(cpu_transcoder),
7501 (adjusted_mode->crtc_hblank_start - 1) |
7502 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7503 I915_WRITE(HSYNC(cpu_transcoder),
7504 (adjusted_mode->crtc_hsync_start - 1) |
7505 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7506
7507 I915_WRITE(VTOTAL(cpu_transcoder),
7508 (adjusted_mode->crtc_vdisplay - 1) |
7509 ((crtc_vtotal - 1) << 16));
7510 I915_WRITE(VBLANK(cpu_transcoder),
7511 (adjusted_mode->crtc_vblank_start - 1) |
7512 ((crtc_vblank_end - 1) << 16));
7513 I915_WRITE(VSYNC(cpu_transcoder),
7514 (adjusted_mode->crtc_vsync_start - 1) |
7515 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7516
7517 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7518 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7519 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7520 * bits. */
7521 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7522 (pipe == PIPE_B || pipe == PIPE_C))
7523 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7524
7525 /* pipesrc controls the size that is scaled from, which should
7526 * always be the user's requested size.
7527 */
7528 I915_WRITE(PIPESRC(pipe),
7529 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7530 (intel_crtc->config->pipe_src_h - 1));
7531 }
7532
7533 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7534 struct intel_crtc_state *pipe_config)
7535 {
7536 struct drm_device *dev = crtc->base.dev;
7537 struct drm_i915_private *dev_priv = dev->dev_private;
7538 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7539 uint32_t tmp;
7540
7541 tmp = I915_READ(HTOTAL(cpu_transcoder));
7542 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7543 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7544 tmp = I915_READ(HBLANK(cpu_transcoder));
7545 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7546 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7547 tmp = I915_READ(HSYNC(cpu_transcoder));
7548 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7549 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7550
7551 tmp = I915_READ(VTOTAL(cpu_transcoder));
7552 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7553 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7554 tmp = I915_READ(VBLANK(cpu_transcoder));
7555 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7556 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7557 tmp = I915_READ(VSYNC(cpu_transcoder));
7558 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7559 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7560
7561 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7562 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7563 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7564 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7565 }
7566
7567 tmp = I915_READ(PIPESRC(crtc->pipe));
7568 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7569 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7570
7571 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7572 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7573 }
7574
7575 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7576 struct intel_crtc_state *pipe_config)
7577 {
7578 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7579 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7580 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7581 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7582
7583 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7584 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7585 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7586 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7587
7588 mode->flags = pipe_config->base.adjusted_mode.flags;
7589
7590 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7591 mode->flags |= pipe_config->base.adjusted_mode.flags;
7592 }
7593
7594 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7595 {
7596 struct drm_device *dev = intel_crtc->base.dev;
7597 struct drm_i915_private *dev_priv = dev->dev_private;
7598 uint32_t pipeconf;
7599
7600 pipeconf = 0;
7601
7602 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7603 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7604 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7605
7606 if (intel_crtc->config->double_wide)
7607 pipeconf |= PIPECONF_DOUBLE_WIDE;
7608
7609 /* only g4x and later have fancy bpc/dither controls */
7610 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7611 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7612 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7613 pipeconf |= PIPECONF_DITHER_EN |
7614 PIPECONF_DITHER_TYPE_SP;
7615
7616 switch (intel_crtc->config->pipe_bpp) {
7617 case 18:
7618 pipeconf |= PIPECONF_6BPC;
7619 break;
7620 case 24:
7621 pipeconf |= PIPECONF_8BPC;
7622 break;
7623 case 30:
7624 pipeconf |= PIPECONF_10BPC;
7625 break;
7626 default:
7627 /* Case prevented by intel_choose_pipe_bpp_dither. */
7628 BUG();
7629 }
7630 }
7631
7632 if (HAS_PIPE_CXSR(dev)) {
7633 if (intel_crtc->lowfreq_avail) {
7634 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7635 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7636 } else {
7637 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7638 }
7639 }
7640
7641 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7642 if (INTEL_INFO(dev)->gen < 4 ||
7643 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7644 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7645 else
7646 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7647 } else
7648 pipeconf |= PIPECONF_PROGRESSIVE;
7649
7650 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7651 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7652
7653 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7654 POSTING_READ(PIPECONF(intel_crtc->pipe));
7655 }
7656
7657 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7658 struct intel_crtc_state *crtc_state)
7659 {
7660 struct drm_device *dev = crtc->base.dev;
7661 struct drm_i915_private *dev_priv = dev->dev_private;
7662 int refclk, num_connectors = 0;
7663 intel_clock_t clock, reduced_clock;
7664 bool ok, has_reduced_clock = false;
7665 bool is_lvds = false, is_dsi = false;
7666 struct intel_encoder *encoder;
7667 const intel_limit_t *limit;
7668 struct drm_atomic_state *state = crtc_state->base.state;
7669 struct drm_connector *connector;
7670 struct drm_connector_state *connector_state;
7671 int i;
7672
7673 memset(&crtc_state->dpll_hw_state, 0,
7674 sizeof(crtc_state->dpll_hw_state));
7675
7676 for_each_connector_in_state(state, connector, connector_state, i) {
7677 if (connector_state->crtc != &crtc->base)
7678 continue;
7679
7680 encoder = to_intel_encoder(connector_state->best_encoder);
7681
7682 switch (encoder->type) {
7683 case INTEL_OUTPUT_LVDS:
7684 is_lvds = true;
7685 break;
7686 case INTEL_OUTPUT_DSI:
7687 is_dsi = true;
7688 break;
7689 default:
7690 break;
7691 }
7692
7693 num_connectors++;
7694 }
7695
7696 if (is_dsi)
7697 return 0;
7698
7699 if (!crtc_state->clock_set) {
7700 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7701
7702 /*
7703 * Returns a set of divisors for the desired target clock with
7704 * the given refclk, or FALSE. The returned values represent
7705 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7706 * 2) / p1 / p2.
7707 */
7708 limit = intel_limit(crtc_state, refclk);
7709 ok = dev_priv->display.find_dpll(limit, crtc_state,
7710 crtc_state->port_clock,
7711 refclk, NULL, &clock);
7712 if (!ok) {
7713 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7714 return -EINVAL;
7715 }
7716
7717 if (is_lvds && dev_priv->lvds_downclock_avail) {
7718 /*
7719 * Ensure we match the reduced clock's P to the target
7720 * clock. If the clocks don't match, we can't switch
7721 * the display clock by using the FP0/FP1. In such case
7722 * we will disable the LVDS downclock feature.
7723 */
7724 has_reduced_clock =
7725 dev_priv->display.find_dpll(limit, crtc_state,
7726 dev_priv->lvds_downclock,
7727 refclk, &clock,
7728 &reduced_clock);
7729 }
7730 /* Compat-code for transition, will disappear. */
7731 crtc_state->dpll.n = clock.n;
7732 crtc_state->dpll.m1 = clock.m1;
7733 crtc_state->dpll.m2 = clock.m2;
7734 crtc_state->dpll.p1 = clock.p1;
7735 crtc_state->dpll.p2 = clock.p2;
7736 }
7737
7738 if (IS_GEN2(dev)) {
7739 i8xx_update_pll(crtc, crtc_state,
7740 has_reduced_clock ? &reduced_clock : NULL,
7741 num_connectors);
7742 } else if (IS_CHERRYVIEW(dev)) {
7743 chv_update_pll(crtc, crtc_state);
7744 } else if (IS_VALLEYVIEW(dev)) {
7745 vlv_update_pll(crtc, crtc_state);
7746 } else {
7747 i9xx_update_pll(crtc, crtc_state,
7748 has_reduced_clock ? &reduced_clock : NULL,
7749 num_connectors);
7750 }
7751
7752 return 0;
7753 }
7754
7755 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7756 struct intel_crtc_state *pipe_config)
7757 {
7758 struct drm_device *dev = crtc->base.dev;
7759 struct drm_i915_private *dev_priv = dev->dev_private;
7760 uint32_t tmp;
7761
7762 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7763 return;
7764
7765 tmp = I915_READ(PFIT_CONTROL);
7766 if (!(tmp & PFIT_ENABLE))
7767 return;
7768
7769 /* Check whether the pfit is attached to our pipe. */
7770 if (INTEL_INFO(dev)->gen < 4) {
7771 if (crtc->pipe != PIPE_B)
7772 return;
7773 } else {
7774 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7775 return;
7776 }
7777
7778 pipe_config->gmch_pfit.control = tmp;
7779 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7780 if (INTEL_INFO(dev)->gen < 5)
7781 pipe_config->gmch_pfit.lvds_border_bits =
7782 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7783 }
7784
7785 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7786 struct intel_crtc_state *pipe_config)
7787 {
7788 struct drm_device *dev = crtc->base.dev;
7789 struct drm_i915_private *dev_priv = dev->dev_private;
7790 int pipe = pipe_config->cpu_transcoder;
7791 intel_clock_t clock;
7792 u32 mdiv;
7793 int refclk = 100000;
7794
7795 /* In case of MIPI DPLL will not even be used */
7796 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7797 return;
7798
7799 mutex_lock(&dev_priv->dpio_lock);
7800 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7801 mutex_unlock(&dev_priv->dpio_lock);
7802
7803 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7804 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7805 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7806 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7807 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7808
7809 vlv_clock(refclk, &clock);
7810
7811 /* clock.dot is the fast clock */
7812 pipe_config->port_clock = clock.dot / 5;
7813 }
7814
7815 static void
7816 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7817 struct intel_initial_plane_config *plane_config)
7818 {
7819 struct drm_device *dev = crtc->base.dev;
7820 struct drm_i915_private *dev_priv = dev->dev_private;
7821 u32 val, base, offset;
7822 int pipe = crtc->pipe, plane = crtc->plane;
7823 int fourcc, pixel_format;
7824 unsigned int aligned_height;
7825 struct drm_framebuffer *fb;
7826 struct intel_framebuffer *intel_fb;
7827
7828 val = I915_READ(DSPCNTR(plane));
7829 if (!(val & DISPLAY_PLANE_ENABLE))
7830 return;
7831
7832 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7833 if (!intel_fb) {
7834 DRM_DEBUG_KMS("failed to alloc fb\n");
7835 return;
7836 }
7837
7838 fb = &intel_fb->base;
7839
7840 if (INTEL_INFO(dev)->gen >= 4) {
7841 if (val & DISPPLANE_TILED) {
7842 plane_config->tiling = I915_TILING_X;
7843 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7844 }
7845 }
7846
7847 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7848 fourcc = i9xx_format_to_fourcc(pixel_format);
7849 fb->pixel_format = fourcc;
7850 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7851
7852 if (INTEL_INFO(dev)->gen >= 4) {
7853 if (plane_config->tiling)
7854 offset = I915_READ(DSPTILEOFF(plane));
7855 else
7856 offset = I915_READ(DSPLINOFF(plane));
7857 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7858 } else {
7859 base = I915_READ(DSPADDR(plane));
7860 }
7861 plane_config->base = base;
7862
7863 val = I915_READ(PIPESRC(pipe));
7864 fb->width = ((val >> 16) & 0xfff) + 1;
7865 fb->height = ((val >> 0) & 0xfff) + 1;
7866
7867 val = I915_READ(DSPSTRIDE(pipe));
7868 fb->pitches[0] = val & 0xffffffc0;
7869
7870 aligned_height = intel_fb_align_height(dev, fb->height,
7871 fb->pixel_format,
7872 fb->modifier[0]);
7873
7874 plane_config->size = fb->pitches[0] * aligned_height;
7875
7876 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7877 pipe_name(pipe), plane, fb->width, fb->height,
7878 fb->bits_per_pixel, base, fb->pitches[0],
7879 plane_config->size);
7880
7881 plane_config->fb = intel_fb;
7882 }
7883
7884 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7885 struct intel_crtc_state *pipe_config)
7886 {
7887 struct drm_device *dev = crtc->base.dev;
7888 struct drm_i915_private *dev_priv = dev->dev_private;
7889 int pipe = pipe_config->cpu_transcoder;
7890 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7891 intel_clock_t clock;
7892 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7893 int refclk = 100000;
7894
7895 mutex_lock(&dev_priv->dpio_lock);
7896 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7897 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7898 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7899 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7900 mutex_unlock(&dev_priv->dpio_lock);
7901
7902 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7903 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7904 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7905 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7906 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7907
7908 chv_clock(refclk, &clock);
7909
7910 /* clock.dot is the fast clock */
7911 pipe_config->port_clock = clock.dot / 5;
7912 }
7913
7914 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7915 struct intel_crtc_state *pipe_config)
7916 {
7917 struct drm_device *dev = crtc->base.dev;
7918 struct drm_i915_private *dev_priv = dev->dev_private;
7919 uint32_t tmp;
7920
7921 if (!intel_display_power_is_enabled(dev_priv,
7922 POWER_DOMAIN_PIPE(crtc->pipe)))
7923 return false;
7924
7925 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7926 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7927
7928 tmp = I915_READ(PIPECONF(crtc->pipe));
7929 if (!(tmp & PIPECONF_ENABLE))
7930 return false;
7931
7932 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7933 switch (tmp & PIPECONF_BPC_MASK) {
7934 case PIPECONF_6BPC:
7935 pipe_config->pipe_bpp = 18;
7936 break;
7937 case PIPECONF_8BPC:
7938 pipe_config->pipe_bpp = 24;
7939 break;
7940 case PIPECONF_10BPC:
7941 pipe_config->pipe_bpp = 30;
7942 break;
7943 default:
7944 break;
7945 }
7946 }
7947
7948 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7949 pipe_config->limited_color_range = true;
7950
7951 if (INTEL_INFO(dev)->gen < 4)
7952 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7953
7954 intel_get_pipe_timings(crtc, pipe_config);
7955
7956 i9xx_get_pfit_config(crtc, pipe_config);
7957
7958 if (INTEL_INFO(dev)->gen >= 4) {
7959 tmp = I915_READ(DPLL_MD(crtc->pipe));
7960 pipe_config->pixel_multiplier =
7961 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7962 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7963 pipe_config->dpll_hw_state.dpll_md = tmp;
7964 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7965 tmp = I915_READ(DPLL(crtc->pipe));
7966 pipe_config->pixel_multiplier =
7967 ((tmp & SDVO_MULTIPLIER_MASK)
7968 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7969 } else {
7970 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7971 * port and will be fixed up in the encoder->get_config
7972 * function. */
7973 pipe_config->pixel_multiplier = 1;
7974 }
7975 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7976 if (!IS_VALLEYVIEW(dev)) {
7977 /*
7978 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7979 * on 830. Filter it out here so that we don't
7980 * report errors due to that.
7981 */
7982 if (IS_I830(dev))
7983 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7984
7985 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7986 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7987 } else {
7988 /* Mask out read-only status bits. */
7989 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7990 DPLL_PORTC_READY_MASK |
7991 DPLL_PORTB_READY_MASK);
7992 }
7993
7994 if (IS_CHERRYVIEW(dev))
7995 chv_crtc_clock_get(crtc, pipe_config);
7996 else if (IS_VALLEYVIEW(dev))
7997 vlv_crtc_clock_get(crtc, pipe_config);
7998 else
7999 i9xx_crtc_clock_get(crtc, pipe_config);
8000
8001 return true;
8002 }
8003
8004 static void ironlake_init_pch_refclk(struct drm_device *dev)
8005 {
8006 struct drm_i915_private *dev_priv = dev->dev_private;
8007 struct intel_encoder *encoder;
8008 u32 val, final;
8009 bool has_lvds = false;
8010 bool has_cpu_edp = false;
8011 bool has_panel = false;
8012 bool has_ck505 = false;
8013 bool can_ssc = false;
8014
8015 /* We need to take the global config into account */
8016 for_each_intel_encoder(dev, encoder) {
8017 switch (encoder->type) {
8018 case INTEL_OUTPUT_LVDS:
8019 has_panel = true;
8020 has_lvds = true;
8021 break;
8022 case INTEL_OUTPUT_EDP:
8023 has_panel = true;
8024 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8025 has_cpu_edp = true;
8026 break;
8027 default:
8028 break;
8029 }
8030 }
8031
8032 if (HAS_PCH_IBX(dev)) {
8033 has_ck505 = dev_priv->vbt.display_clock_mode;
8034 can_ssc = has_ck505;
8035 } else {
8036 has_ck505 = false;
8037 can_ssc = true;
8038 }
8039
8040 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8041 has_panel, has_lvds, has_ck505);
8042
8043 /* Ironlake: try to setup display ref clock before DPLL
8044 * enabling. This is only under driver's control after
8045 * PCH B stepping, previous chipset stepping should be
8046 * ignoring this setting.
8047 */
8048 val = I915_READ(PCH_DREF_CONTROL);
8049
8050 /* As we must carefully and slowly disable/enable each source in turn,
8051 * compute the final state we want first and check if we need to
8052 * make any changes at all.
8053 */
8054 final = val;
8055 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8056 if (has_ck505)
8057 final |= DREF_NONSPREAD_CK505_ENABLE;
8058 else
8059 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8060
8061 final &= ~DREF_SSC_SOURCE_MASK;
8062 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8063 final &= ~DREF_SSC1_ENABLE;
8064
8065 if (has_panel) {
8066 final |= DREF_SSC_SOURCE_ENABLE;
8067
8068 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8069 final |= DREF_SSC1_ENABLE;
8070
8071 if (has_cpu_edp) {
8072 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8073 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8074 else
8075 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8076 } else
8077 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8078 } else {
8079 final |= DREF_SSC_SOURCE_DISABLE;
8080 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8081 }
8082
8083 if (final == val)
8084 return;
8085
8086 /* Always enable nonspread source */
8087 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8088
8089 if (has_ck505)
8090 val |= DREF_NONSPREAD_CK505_ENABLE;
8091 else
8092 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8093
8094 if (has_panel) {
8095 val &= ~DREF_SSC_SOURCE_MASK;
8096 val |= DREF_SSC_SOURCE_ENABLE;
8097
8098 /* SSC must be turned on before enabling the CPU output */
8099 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8100 DRM_DEBUG_KMS("Using SSC on panel\n");
8101 val |= DREF_SSC1_ENABLE;
8102 } else
8103 val &= ~DREF_SSC1_ENABLE;
8104
8105 /* Get SSC going before enabling the outputs */
8106 I915_WRITE(PCH_DREF_CONTROL, val);
8107 POSTING_READ(PCH_DREF_CONTROL);
8108 udelay(200);
8109
8110 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8111
8112 /* Enable CPU source on CPU attached eDP */
8113 if (has_cpu_edp) {
8114 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8115 DRM_DEBUG_KMS("Using SSC on eDP\n");
8116 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8117 } else
8118 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8119 } else
8120 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8121
8122 I915_WRITE(PCH_DREF_CONTROL, val);
8123 POSTING_READ(PCH_DREF_CONTROL);
8124 udelay(200);
8125 } else {
8126 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8127
8128 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8129
8130 /* Turn off CPU output */
8131 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8132
8133 I915_WRITE(PCH_DREF_CONTROL, val);
8134 POSTING_READ(PCH_DREF_CONTROL);
8135 udelay(200);
8136
8137 /* Turn off the SSC source */
8138 val &= ~DREF_SSC_SOURCE_MASK;
8139 val |= DREF_SSC_SOURCE_DISABLE;
8140
8141 /* Turn off SSC1 */
8142 val &= ~DREF_SSC1_ENABLE;
8143
8144 I915_WRITE(PCH_DREF_CONTROL, val);
8145 POSTING_READ(PCH_DREF_CONTROL);
8146 udelay(200);
8147 }
8148
8149 BUG_ON(val != final);
8150 }
8151
8152 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8153 {
8154 uint32_t tmp;
8155
8156 tmp = I915_READ(SOUTH_CHICKEN2);
8157 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8158 I915_WRITE(SOUTH_CHICKEN2, tmp);
8159
8160 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8161 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8162 DRM_ERROR("FDI mPHY reset assert timeout\n");
8163
8164 tmp = I915_READ(SOUTH_CHICKEN2);
8165 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8166 I915_WRITE(SOUTH_CHICKEN2, tmp);
8167
8168 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8169 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8170 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8171 }
8172
8173 /* WaMPhyProgramming:hsw */
8174 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8175 {
8176 uint32_t tmp;
8177
8178 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8179 tmp &= ~(0xFF << 24);
8180 tmp |= (0x12 << 24);
8181 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8182
8183 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8184 tmp |= (1 << 11);
8185 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8186
8187 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8188 tmp |= (1 << 11);
8189 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8190
8191 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8192 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8193 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8194
8195 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8196 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8197 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8198
8199 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8200 tmp &= ~(7 << 13);
8201 tmp |= (5 << 13);
8202 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8203
8204 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8205 tmp &= ~(7 << 13);
8206 tmp |= (5 << 13);
8207 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8208
8209 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8210 tmp &= ~0xFF;
8211 tmp |= 0x1C;
8212 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8213
8214 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8215 tmp &= ~0xFF;
8216 tmp |= 0x1C;
8217 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8218
8219 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8220 tmp &= ~(0xFF << 16);
8221 tmp |= (0x1C << 16);
8222 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8223
8224 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8225 tmp &= ~(0xFF << 16);
8226 tmp |= (0x1C << 16);
8227 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8228
8229 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8230 tmp |= (1 << 27);
8231 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8232
8233 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8234 tmp |= (1 << 27);
8235 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8236
8237 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8238 tmp &= ~(0xF << 28);
8239 tmp |= (4 << 28);
8240 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8241
8242 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8243 tmp &= ~(0xF << 28);
8244 tmp |= (4 << 28);
8245 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8246 }
8247
8248 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8249 * Programming" based on the parameters passed:
8250 * - Sequence to enable CLKOUT_DP
8251 * - Sequence to enable CLKOUT_DP without spread
8252 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8253 */
8254 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8255 bool with_fdi)
8256 {
8257 struct drm_i915_private *dev_priv = dev->dev_private;
8258 uint32_t reg, tmp;
8259
8260 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8261 with_spread = true;
8262 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8263 with_fdi, "LP PCH doesn't have FDI\n"))
8264 with_fdi = false;
8265
8266 mutex_lock(&dev_priv->dpio_lock);
8267
8268 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8269 tmp &= ~SBI_SSCCTL_DISABLE;
8270 tmp |= SBI_SSCCTL_PATHALT;
8271 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8272
8273 udelay(24);
8274
8275 if (with_spread) {
8276 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8277 tmp &= ~SBI_SSCCTL_PATHALT;
8278 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8279
8280 if (with_fdi) {
8281 lpt_reset_fdi_mphy(dev_priv);
8282 lpt_program_fdi_mphy(dev_priv);
8283 }
8284 }
8285
8286 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8287 SBI_GEN0 : SBI_DBUFF0;
8288 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8289 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8290 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8291
8292 mutex_unlock(&dev_priv->dpio_lock);
8293 }
8294
8295 /* Sequence to disable CLKOUT_DP */
8296 static void lpt_disable_clkout_dp(struct drm_device *dev)
8297 {
8298 struct drm_i915_private *dev_priv = dev->dev_private;
8299 uint32_t reg, tmp;
8300
8301 mutex_lock(&dev_priv->dpio_lock);
8302
8303 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8304 SBI_GEN0 : SBI_DBUFF0;
8305 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8306 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8307 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8308
8309 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8310 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8311 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8312 tmp |= SBI_SSCCTL_PATHALT;
8313 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8314 udelay(32);
8315 }
8316 tmp |= SBI_SSCCTL_DISABLE;
8317 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8318 }
8319
8320 mutex_unlock(&dev_priv->dpio_lock);
8321 }
8322
8323 static void lpt_init_pch_refclk(struct drm_device *dev)
8324 {
8325 struct intel_encoder *encoder;
8326 bool has_vga = false;
8327
8328 for_each_intel_encoder(dev, encoder) {
8329 switch (encoder->type) {
8330 case INTEL_OUTPUT_ANALOG:
8331 has_vga = true;
8332 break;
8333 default:
8334 break;
8335 }
8336 }
8337
8338 if (has_vga)
8339 lpt_enable_clkout_dp(dev, true, true);
8340 else
8341 lpt_disable_clkout_dp(dev);
8342 }
8343
8344 /*
8345 * Initialize reference clocks when the driver loads
8346 */
8347 void intel_init_pch_refclk(struct drm_device *dev)
8348 {
8349 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8350 ironlake_init_pch_refclk(dev);
8351 else if (HAS_PCH_LPT(dev))
8352 lpt_init_pch_refclk(dev);
8353 }
8354
8355 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8356 {
8357 struct drm_device *dev = crtc_state->base.crtc->dev;
8358 struct drm_i915_private *dev_priv = dev->dev_private;
8359 struct drm_atomic_state *state = crtc_state->base.state;
8360 struct drm_connector *connector;
8361 struct drm_connector_state *connector_state;
8362 struct intel_encoder *encoder;
8363 int num_connectors = 0, i;
8364 bool is_lvds = false;
8365
8366 for_each_connector_in_state(state, connector, connector_state, i) {
8367 if (connector_state->crtc != crtc_state->base.crtc)
8368 continue;
8369
8370 encoder = to_intel_encoder(connector_state->best_encoder);
8371
8372 switch (encoder->type) {
8373 case INTEL_OUTPUT_LVDS:
8374 is_lvds = true;
8375 break;
8376 default:
8377 break;
8378 }
8379 num_connectors++;
8380 }
8381
8382 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8383 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8384 dev_priv->vbt.lvds_ssc_freq);
8385 return dev_priv->vbt.lvds_ssc_freq;
8386 }
8387
8388 return 120000;
8389 }
8390
8391 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8392 {
8393 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8395 int pipe = intel_crtc->pipe;
8396 uint32_t val;
8397
8398 val = 0;
8399
8400 switch (intel_crtc->config->pipe_bpp) {
8401 case 18:
8402 val |= PIPECONF_6BPC;
8403 break;
8404 case 24:
8405 val |= PIPECONF_8BPC;
8406 break;
8407 case 30:
8408 val |= PIPECONF_10BPC;
8409 break;
8410 case 36:
8411 val |= PIPECONF_12BPC;
8412 break;
8413 default:
8414 /* Case prevented by intel_choose_pipe_bpp_dither. */
8415 BUG();
8416 }
8417
8418 if (intel_crtc->config->dither)
8419 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8420
8421 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8422 val |= PIPECONF_INTERLACED_ILK;
8423 else
8424 val |= PIPECONF_PROGRESSIVE;
8425
8426 if (intel_crtc->config->limited_color_range)
8427 val |= PIPECONF_COLOR_RANGE_SELECT;
8428
8429 I915_WRITE(PIPECONF(pipe), val);
8430 POSTING_READ(PIPECONF(pipe));
8431 }
8432
8433 /*
8434 * Set up the pipe CSC unit.
8435 *
8436 * Currently only full range RGB to limited range RGB conversion
8437 * is supported, but eventually this should handle various
8438 * RGB<->YCbCr scenarios as well.
8439 */
8440 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8441 {
8442 struct drm_device *dev = crtc->dev;
8443 struct drm_i915_private *dev_priv = dev->dev_private;
8444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8445 int pipe = intel_crtc->pipe;
8446 uint16_t coeff = 0x7800; /* 1.0 */
8447
8448 /*
8449 * TODO: Check what kind of values actually come out of the pipe
8450 * with these coeff/postoff values and adjust to get the best
8451 * accuracy. Perhaps we even need to take the bpc value into
8452 * consideration.
8453 */
8454
8455 if (intel_crtc->config->limited_color_range)
8456 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8457
8458 /*
8459 * GY/GU and RY/RU should be the other way around according
8460 * to BSpec, but reality doesn't agree. Just set them up in
8461 * a way that results in the correct picture.
8462 */
8463 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8464 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8465
8466 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8467 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8468
8469 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8470 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8471
8472 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8473 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8474 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8475
8476 if (INTEL_INFO(dev)->gen > 6) {
8477 uint16_t postoff = 0;
8478
8479 if (intel_crtc->config->limited_color_range)
8480 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8481
8482 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8483 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8484 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8485
8486 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8487 } else {
8488 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8489
8490 if (intel_crtc->config->limited_color_range)
8491 mode |= CSC_BLACK_SCREEN_OFFSET;
8492
8493 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8494 }
8495 }
8496
8497 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8498 {
8499 struct drm_device *dev = crtc->dev;
8500 struct drm_i915_private *dev_priv = dev->dev_private;
8501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8502 enum pipe pipe = intel_crtc->pipe;
8503 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8504 uint32_t val;
8505
8506 val = 0;
8507
8508 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8509 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8510
8511 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8512 val |= PIPECONF_INTERLACED_ILK;
8513 else
8514 val |= PIPECONF_PROGRESSIVE;
8515
8516 I915_WRITE(PIPECONF(cpu_transcoder), val);
8517 POSTING_READ(PIPECONF(cpu_transcoder));
8518
8519 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8520 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8521
8522 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8523 val = 0;
8524
8525 switch (intel_crtc->config->pipe_bpp) {
8526 case 18:
8527 val |= PIPEMISC_DITHER_6_BPC;
8528 break;
8529 case 24:
8530 val |= PIPEMISC_DITHER_8_BPC;
8531 break;
8532 case 30:
8533 val |= PIPEMISC_DITHER_10_BPC;
8534 break;
8535 case 36:
8536 val |= PIPEMISC_DITHER_12_BPC;
8537 break;
8538 default:
8539 /* Case prevented by pipe_config_set_bpp. */
8540 BUG();
8541 }
8542
8543 if (intel_crtc->config->dither)
8544 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8545
8546 I915_WRITE(PIPEMISC(pipe), val);
8547 }
8548 }
8549
8550 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8551 struct intel_crtc_state *crtc_state,
8552 intel_clock_t *clock,
8553 bool *has_reduced_clock,
8554 intel_clock_t *reduced_clock)
8555 {
8556 struct drm_device *dev = crtc->dev;
8557 struct drm_i915_private *dev_priv = dev->dev_private;
8558 int refclk;
8559 const intel_limit_t *limit;
8560 bool ret, is_lvds = false;
8561
8562 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8563
8564 refclk = ironlake_get_refclk(crtc_state);
8565
8566 /*
8567 * Returns a set of divisors for the desired target clock with the given
8568 * refclk, or FALSE. The returned values represent the clock equation:
8569 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8570 */
8571 limit = intel_limit(crtc_state, refclk);
8572 ret = dev_priv->display.find_dpll(limit, crtc_state,
8573 crtc_state->port_clock,
8574 refclk, NULL, clock);
8575 if (!ret)
8576 return false;
8577
8578 if (is_lvds && dev_priv->lvds_downclock_avail) {
8579 /*
8580 * Ensure we match the reduced clock's P to the target clock.
8581 * If the clocks don't match, we can't switch the display clock
8582 * by using the FP0/FP1. In such case we will disable the LVDS
8583 * downclock feature.
8584 */
8585 *has_reduced_clock =
8586 dev_priv->display.find_dpll(limit, crtc_state,
8587 dev_priv->lvds_downclock,
8588 refclk, clock,
8589 reduced_clock);
8590 }
8591
8592 return true;
8593 }
8594
8595 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8596 {
8597 /*
8598 * Account for spread spectrum to avoid
8599 * oversubscribing the link. Max center spread
8600 * is 2.5%; use 5% for safety's sake.
8601 */
8602 u32 bps = target_clock * bpp * 21 / 20;
8603 return DIV_ROUND_UP(bps, link_bw * 8);
8604 }
8605
8606 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8607 {
8608 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8609 }
8610
8611 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8612 struct intel_crtc_state *crtc_state,
8613 u32 *fp,
8614 intel_clock_t *reduced_clock, u32 *fp2)
8615 {
8616 struct drm_crtc *crtc = &intel_crtc->base;
8617 struct drm_device *dev = crtc->dev;
8618 struct drm_i915_private *dev_priv = dev->dev_private;
8619 struct drm_atomic_state *state = crtc_state->base.state;
8620 struct drm_connector *connector;
8621 struct drm_connector_state *connector_state;
8622 struct intel_encoder *encoder;
8623 uint32_t dpll;
8624 int factor, num_connectors = 0, i;
8625 bool is_lvds = false, is_sdvo = false;
8626
8627 for_each_connector_in_state(state, connector, connector_state, i) {
8628 if (connector_state->crtc != crtc_state->base.crtc)
8629 continue;
8630
8631 encoder = to_intel_encoder(connector_state->best_encoder);
8632
8633 switch (encoder->type) {
8634 case INTEL_OUTPUT_LVDS:
8635 is_lvds = true;
8636 break;
8637 case INTEL_OUTPUT_SDVO:
8638 case INTEL_OUTPUT_HDMI:
8639 is_sdvo = true;
8640 break;
8641 default:
8642 break;
8643 }
8644
8645 num_connectors++;
8646 }
8647
8648 /* Enable autotuning of the PLL clock (if permissible) */
8649 factor = 21;
8650 if (is_lvds) {
8651 if ((intel_panel_use_ssc(dev_priv) &&
8652 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8653 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8654 factor = 25;
8655 } else if (crtc_state->sdvo_tv_clock)
8656 factor = 20;
8657
8658 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8659 *fp |= FP_CB_TUNE;
8660
8661 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8662 *fp2 |= FP_CB_TUNE;
8663
8664 dpll = 0;
8665
8666 if (is_lvds)
8667 dpll |= DPLLB_MODE_LVDS;
8668 else
8669 dpll |= DPLLB_MODE_DAC_SERIAL;
8670
8671 dpll |= (crtc_state->pixel_multiplier - 1)
8672 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8673
8674 if (is_sdvo)
8675 dpll |= DPLL_SDVO_HIGH_SPEED;
8676 if (crtc_state->has_dp_encoder)
8677 dpll |= DPLL_SDVO_HIGH_SPEED;
8678
8679 /* compute bitmask from p1 value */
8680 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8681 /* also FPA1 */
8682 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8683
8684 switch (crtc_state->dpll.p2) {
8685 case 5:
8686 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8687 break;
8688 case 7:
8689 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8690 break;
8691 case 10:
8692 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8693 break;
8694 case 14:
8695 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8696 break;
8697 }
8698
8699 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8700 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8701 else
8702 dpll |= PLL_REF_INPUT_DREFCLK;
8703
8704 return dpll | DPLL_VCO_ENABLE;
8705 }
8706
8707 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8708 struct intel_crtc_state *crtc_state)
8709 {
8710 struct drm_device *dev = crtc->base.dev;
8711 intel_clock_t clock, reduced_clock;
8712 u32 dpll = 0, fp = 0, fp2 = 0;
8713 bool ok, has_reduced_clock = false;
8714 bool is_lvds = false;
8715 struct intel_shared_dpll *pll;
8716
8717 memset(&crtc_state->dpll_hw_state, 0,
8718 sizeof(crtc_state->dpll_hw_state));
8719
8720 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8721
8722 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8723 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8724
8725 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8726 &has_reduced_clock, &reduced_clock);
8727 if (!ok && !crtc_state->clock_set) {
8728 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8729 return -EINVAL;
8730 }
8731 /* Compat-code for transition, will disappear. */
8732 if (!crtc_state->clock_set) {
8733 crtc_state->dpll.n = clock.n;
8734 crtc_state->dpll.m1 = clock.m1;
8735 crtc_state->dpll.m2 = clock.m2;
8736 crtc_state->dpll.p1 = clock.p1;
8737 crtc_state->dpll.p2 = clock.p2;
8738 }
8739
8740 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8741 if (crtc_state->has_pch_encoder) {
8742 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8743 if (has_reduced_clock)
8744 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8745
8746 dpll = ironlake_compute_dpll(crtc, crtc_state,
8747 &fp, &reduced_clock,
8748 has_reduced_clock ? &fp2 : NULL);
8749
8750 crtc_state->dpll_hw_state.dpll = dpll;
8751 crtc_state->dpll_hw_state.fp0 = fp;
8752 if (has_reduced_clock)
8753 crtc_state->dpll_hw_state.fp1 = fp2;
8754 else
8755 crtc_state->dpll_hw_state.fp1 = fp;
8756
8757 pll = intel_get_shared_dpll(crtc, crtc_state);
8758 if (pll == NULL) {
8759 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8760 pipe_name(crtc->pipe));
8761 return -EINVAL;
8762 }
8763 }
8764
8765 if (is_lvds && has_reduced_clock)
8766 crtc->lowfreq_avail = true;
8767 else
8768 crtc->lowfreq_avail = false;
8769
8770 return 0;
8771 }
8772
8773 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8774 struct intel_link_m_n *m_n)
8775 {
8776 struct drm_device *dev = crtc->base.dev;
8777 struct drm_i915_private *dev_priv = dev->dev_private;
8778 enum pipe pipe = crtc->pipe;
8779
8780 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8781 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8782 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8783 & ~TU_SIZE_MASK;
8784 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8785 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8786 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8787 }
8788
8789 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8790 enum transcoder transcoder,
8791 struct intel_link_m_n *m_n,
8792 struct intel_link_m_n *m2_n2)
8793 {
8794 struct drm_device *dev = crtc->base.dev;
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796 enum pipe pipe = crtc->pipe;
8797
8798 if (INTEL_INFO(dev)->gen >= 5) {
8799 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8800 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8801 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8802 & ~TU_SIZE_MASK;
8803 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8804 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8805 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8806 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8807 * gen < 8) and if DRRS is supported (to make sure the
8808 * registers are not unnecessarily read).
8809 */
8810 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8811 crtc->config->has_drrs) {
8812 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8813 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8814 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8815 & ~TU_SIZE_MASK;
8816 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8817 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8818 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8819 }
8820 } else {
8821 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8822 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8823 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8824 & ~TU_SIZE_MASK;
8825 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8826 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8827 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8828 }
8829 }
8830
8831 void intel_dp_get_m_n(struct intel_crtc *crtc,
8832 struct intel_crtc_state *pipe_config)
8833 {
8834 if (pipe_config->has_pch_encoder)
8835 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8836 else
8837 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8838 &pipe_config->dp_m_n,
8839 &pipe_config->dp_m2_n2);
8840 }
8841
8842 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8843 struct intel_crtc_state *pipe_config)
8844 {
8845 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8846 &pipe_config->fdi_m_n, NULL);
8847 }
8848
8849 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8850 struct intel_crtc_state *pipe_config)
8851 {
8852 struct drm_device *dev = crtc->base.dev;
8853 struct drm_i915_private *dev_priv = dev->dev_private;
8854 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8855 uint32_t ps_ctrl = 0;
8856 int id = -1;
8857 int i;
8858
8859 /* find scaler attached to this pipe */
8860 for (i = 0; i < crtc->num_scalers; i++) {
8861 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8862 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8863 id = i;
8864 pipe_config->pch_pfit.enabled = true;
8865 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8866 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8867 break;
8868 }
8869 }
8870
8871 scaler_state->scaler_id = id;
8872 if (id >= 0) {
8873 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8874 } else {
8875 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8876 }
8877 }
8878
8879 static void
8880 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8881 struct intel_initial_plane_config *plane_config)
8882 {
8883 struct drm_device *dev = crtc->base.dev;
8884 struct drm_i915_private *dev_priv = dev->dev_private;
8885 u32 val, base, offset, stride_mult, tiling;
8886 int pipe = crtc->pipe;
8887 int fourcc, pixel_format;
8888 unsigned int aligned_height;
8889 struct drm_framebuffer *fb;
8890 struct intel_framebuffer *intel_fb;
8891
8892 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8893 if (!intel_fb) {
8894 DRM_DEBUG_KMS("failed to alloc fb\n");
8895 return;
8896 }
8897
8898 fb = &intel_fb->base;
8899
8900 val = I915_READ(PLANE_CTL(pipe, 0));
8901 if (!(val & PLANE_CTL_ENABLE))
8902 goto error;
8903
8904 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8905 fourcc = skl_format_to_fourcc(pixel_format,
8906 val & PLANE_CTL_ORDER_RGBX,
8907 val & PLANE_CTL_ALPHA_MASK);
8908 fb->pixel_format = fourcc;
8909 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8910
8911 tiling = val & PLANE_CTL_TILED_MASK;
8912 switch (tiling) {
8913 case PLANE_CTL_TILED_LINEAR:
8914 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8915 break;
8916 case PLANE_CTL_TILED_X:
8917 plane_config->tiling = I915_TILING_X;
8918 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8919 break;
8920 case PLANE_CTL_TILED_Y:
8921 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8922 break;
8923 case PLANE_CTL_TILED_YF:
8924 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8925 break;
8926 default:
8927 MISSING_CASE(tiling);
8928 goto error;
8929 }
8930
8931 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8932 plane_config->base = base;
8933
8934 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8935
8936 val = I915_READ(PLANE_SIZE(pipe, 0));
8937 fb->height = ((val >> 16) & 0xfff) + 1;
8938 fb->width = ((val >> 0) & 0x1fff) + 1;
8939
8940 val = I915_READ(PLANE_STRIDE(pipe, 0));
8941 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8942 fb->pixel_format);
8943 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8944
8945 aligned_height = intel_fb_align_height(dev, fb->height,
8946 fb->pixel_format,
8947 fb->modifier[0]);
8948
8949 plane_config->size = fb->pitches[0] * aligned_height;
8950
8951 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8952 pipe_name(pipe), fb->width, fb->height,
8953 fb->bits_per_pixel, base, fb->pitches[0],
8954 plane_config->size);
8955
8956 plane_config->fb = intel_fb;
8957 return;
8958
8959 error:
8960 kfree(fb);
8961 }
8962
8963 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8964 struct intel_crtc_state *pipe_config)
8965 {
8966 struct drm_device *dev = crtc->base.dev;
8967 struct drm_i915_private *dev_priv = dev->dev_private;
8968 uint32_t tmp;
8969
8970 tmp = I915_READ(PF_CTL(crtc->pipe));
8971
8972 if (tmp & PF_ENABLE) {
8973 pipe_config->pch_pfit.enabled = true;
8974 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8975 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8976
8977 /* We currently do not free assignements of panel fitters on
8978 * ivb/hsw (since we don't use the higher upscaling modes which
8979 * differentiates them) so just WARN about this case for now. */
8980 if (IS_GEN7(dev)) {
8981 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8982 PF_PIPE_SEL_IVB(crtc->pipe));
8983 }
8984 }
8985 }
8986
8987 static void
8988 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8989 struct intel_initial_plane_config *plane_config)
8990 {
8991 struct drm_device *dev = crtc->base.dev;
8992 struct drm_i915_private *dev_priv = dev->dev_private;
8993 u32 val, base, offset;
8994 int pipe = crtc->pipe;
8995 int fourcc, pixel_format;
8996 unsigned int aligned_height;
8997 struct drm_framebuffer *fb;
8998 struct intel_framebuffer *intel_fb;
8999
9000 val = I915_READ(DSPCNTR(pipe));
9001 if (!(val & DISPLAY_PLANE_ENABLE))
9002 return;
9003
9004 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9005 if (!intel_fb) {
9006 DRM_DEBUG_KMS("failed to alloc fb\n");
9007 return;
9008 }
9009
9010 fb = &intel_fb->base;
9011
9012 if (INTEL_INFO(dev)->gen >= 4) {
9013 if (val & DISPPLANE_TILED) {
9014 plane_config->tiling = I915_TILING_X;
9015 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9016 }
9017 }
9018
9019 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9020 fourcc = i9xx_format_to_fourcc(pixel_format);
9021 fb->pixel_format = fourcc;
9022 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9023
9024 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9025 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9026 offset = I915_READ(DSPOFFSET(pipe));
9027 } else {
9028 if (plane_config->tiling)
9029 offset = I915_READ(DSPTILEOFF(pipe));
9030 else
9031 offset = I915_READ(DSPLINOFF(pipe));
9032 }
9033 plane_config->base = base;
9034
9035 val = I915_READ(PIPESRC(pipe));
9036 fb->width = ((val >> 16) & 0xfff) + 1;
9037 fb->height = ((val >> 0) & 0xfff) + 1;
9038
9039 val = I915_READ(DSPSTRIDE(pipe));
9040 fb->pitches[0] = val & 0xffffffc0;
9041
9042 aligned_height = intel_fb_align_height(dev, fb->height,
9043 fb->pixel_format,
9044 fb->modifier[0]);
9045
9046 plane_config->size = fb->pitches[0] * aligned_height;
9047
9048 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9049 pipe_name(pipe), fb->width, fb->height,
9050 fb->bits_per_pixel, base, fb->pitches[0],
9051 plane_config->size);
9052
9053 plane_config->fb = intel_fb;
9054 }
9055
9056 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9057 struct intel_crtc_state *pipe_config)
9058 {
9059 struct drm_device *dev = crtc->base.dev;
9060 struct drm_i915_private *dev_priv = dev->dev_private;
9061 uint32_t tmp;
9062
9063 if (!intel_display_power_is_enabled(dev_priv,
9064 POWER_DOMAIN_PIPE(crtc->pipe)))
9065 return false;
9066
9067 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9068 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9069
9070 tmp = I915_READ(PIPECONF(crtc->pipe));
9071 if (!(tmp & PIPECONF_ENABLE))
9072 return false;
9073
9074 switch (tmp & PIPECONF_BPC_MASK) {
9075 case PIPECONF_6BPC:
9076 pipe_config->pipe_bpp = 18;
9077 break;
9078 case PIPECONF_8BPC:
9079 pipe_config->pipe_bpp = 24;
9080 break;
9081 case PIPECONF_10BPC:
9082 pipe_config->pipe_bpp = 30;
9083 break;
9084 case PIPECONF_12BPC:
9085 pipe_config->pipe_bpp = 36;
9086 break;
9087 default:
9088 break;
9089 }
9090
9091 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9092 pipe_config->limited_color_range = true;
9093
9094 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9095 struct intel_shared_dpll *pll;
9096
9097 pipe_config->has_pch_encoder = true;
9098
9099 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9100 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9101 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9102
9103 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9104
9105 if (HAS_PCH_IBX(dev_priv->dev)) {
9106 pipe_config->shared_dpll =
9107 (enum intel_dpll_id) crtc->pipe;
9108 } else {
9109 tmp = I915_READ(PCH_DPLL_SEL);
9110 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9111 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9112 else
9113 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9114 }
9115
9116 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9117
9118 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9119 &pipe_config->dpll_hw_state));
9120
9121 tmp = pipe_config->dpll_hw_state.dpll;
9122 pipe_config->pixel_multiplier =
9123 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9124 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9125
9126 ironlake_pch_clock_get(crtc, pipe_config);
9127 } else {
9128 pipe_config->pixel_multiplier = 1;
9129 }
9130
9131 intel_get_pipe_timings(crtc, pipe_config);
9132
9133 ironlake_get_pfit_config(crtc, pipe_config);
9134
9135 return true;
9136 }
9137
9138 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9139 {
9140 struct drm_device *dev = dev_priv->dev;
9141 struct intel_crtc *crtc;
9142
9143 for_each_intel_crtc(dev, crtc)
9144 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9145 pipe_name(crtc->pipe));
9146
9147 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9148 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9149 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9150 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9151 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9152 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9153 "CPU PWM1 enabled\n");
9154 if (IS_HASWELL(dev))
9155 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9156 "CPU PWM2 enabled\n");
9157 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9158 "PCH PWM1 enabled\n");
9159 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9160 "Utility pin enabled\n");
9161 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9162
9163 /*
9164 * In theory we can still leave IRQs enabled, as long as only the HPD
9165 * interrupts remain enabled. We used to check for that, but since it's
9166 * gen-specific and since we only disable LCPLL after we fully disable
9167 * the interrupts, the check below should be enough.
9168 */
9169 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9170 }
9171
9172 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9173 {
9174 struct drm_device *dev = dev_priv->dev;
9175
9176 if (IS_HASWELL(dev))
9177 return I915_READ(D_COMP_HSW);
9178 else
9179 return I915_READ(D_COMP_BDW);
9180 }
9181
9182 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9183 {
9184 struct drm_device *dev = dev_priv->dev;
9185
9186 if (IS_HASWELL(dev)) {
9187 mutex_lock(&dev_priv->rps.hw_lock);
9188 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9189 val))
9190 DRM_ERROR("Failed to write to D_COMP\n");
9191 mutex_unlock(&dev_priv->rps.hw_lock);
9192 } else {
9193 I915_WRITE(D_COMP_BDW, val);
9194 POSTING_READ(D_COMP_BDW);
9195 }
9196 }
9197
9198 /*
9199 * This function implements pieces of two sequences from BSpec:
9200 * - Sequence for display software to disable LCPLL
9201 * - Sequence for display software to allow package C8+
9202 * The steps implemented here are just the steps that actually touch the LCPLL
9203 * register. Callers should take care of disabling all the display engine
9204 * functions, doing the mode unset, fixing interrupts, etc.
9205 */
9206 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9207 bool switch_to_fclk, bool allow_power_down)
9208 {
9209 uint32_t val;
9210
9211 assert_can_disable_lcpll(dev_priv);
9212
9213 val = I915_READ(LCPLL_CTL);
9214
9215 if (switch_to_fclk) {
9216 val |= LCPLL_CD_SOURCE_FCLK;
9217 I915_WRITE(LCPLL_CTL, val);
9218
9219 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9220 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9221 DRM_ERROR("Switching to FCLK failed\n");
9222
9223 val = I915_READ(LCPLL_CTL);
9224 }
9225
9226 val |= LCPLL_PLL_DISABLE;
9227 I915_WRITE(LCPLL_CTL, val);
9228 POSTING_READ(LCPLL_CTL);
9229
9230 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9231 DRM_ERROR("LCPLL still locked\n");
9232
9233 val = hsw_read_dcomp(dev_priv);
9234 val |= D_COMP_COMP_DISABLE;
9235 hsw_write_dcomp(dev_priv, val);
9236 ndelay(100);
9237
9238 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9239 1))
9240 DRM_ERROR("D_COMP RCOMP still in progress\n");
9241
9242 if (allow_power_down) {
9243 val = I915_READ(LCPLL_CTL);
9244 val |= LCPLL_POWER_DOWN_ALLOW;
9245 I915_WRITE(LCPLL_CTL, val);
9246 POSTING_READ(LCPLL_CTL);
9247 }
9248 }
9249
9250 /*
9251 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9252 * source.
9253 */
9254 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9255 {
9256 uint32_t val;
9257
9258 val = I915_READ(LCPLL_CTL);
9259
9260 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9261 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9262 return;
9263
9264 /*
9265 * Make sure we're not on PC8 state before disabling PC8, otherwise
9266 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9267 */
9268 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9269
9270 if (val & LCPLL_POWER_DOWN_ALLOW) {
9271 val &= ~LCPLL_POWER_DOWN_ALLOW;
9272 I915_WRITE(LCPLL_CTL, val);
9273 POSTING_READ(LCPLL_CTL);
9274 }
9275
9276 val = hsw_read_dcomp(dev_priv);
9277 val |= D_COMP_COMP_FORCE;
9278 val &= ~D_COMP_COMP_DISABLE;
9279 hsw_write_dcomp(dev_priv, val);
9280
9281 val = I915_READ(LCPLL_CTL);
9282 val &= ~LCPLL_PLL_DISABLE;
9283 I915_WRITE(LCPLL_CTL, val);
9284
9285 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9286 DRM_ERROR("LCPLL not locked yet\n");
9287
9288 if (val & LCPLL_CD_SOURCE_FCLK) {
9289 val = I915_READ(LCPLL_CTL);
9290 val &= ~LCPLL_CD_SOURCE_FCLK;
9291 I915_WRITE(LCPLL_CTL, val);
9292
9293 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9294 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9295 DRM_ERROR("Switching back to LCPLL failed\n");
9296 }
9297
9298 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9299 }
9300
9301 /*
9302 * Package states C8 and deeper are really deep PC states that can only be
9303 * reached when all the devices on the system allow it, so even if the graphics
9304 * device allows PC8+, it doesn't mean the system will actually get to these
9305 * states. Our driver only allows PC8+ when going into runtime PM.
9306 *
9307 * The requirements for PC8+ are that all the outputs are disabled, the power
9308 * well is disabled and most interrupts are disabled, and these are also
9309 * requirements for runtime PM. When these conditions are met, we manually do
9310 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9311 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9312 * hang the machine.
9313 *
9314 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9315 * the state of some registers, so when we come back from PC8+ we need to
9316 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9317 * need to take care of the registers kept by RC6. Notice that this happens even
9318 * if we don't put the device in PCI D3 state (which is what currently happens
9319 * because of the runtime PM support).
9320 *
9321 * For more, read "Display Sequences for Package C8" on the hardware
9322 * documentation.
9323 */
9324 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9325 {
9326 struct drm_device *dev = dev_priv->dev;
9327 uint32_t val;
9328
9329 DRM_DEBUG_KMS("Enabling package C8+\n");
9330
9331 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9332 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9333 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9334 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9335 }
9336
9337 lpt_disable_clkout_dp(dev);
9338 hsw_disable_lcpll(dev_priv, true, true);
9339 }
9340
9341 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9342 {
9343 struct drm_device *dev = dev_priv->dev;
9344 uint32_t val;
9345
9346 DRM_DEBUG_KMS("Disabling package C8+\n");
9347
9348 hsw_restore_lcpll(dev_priv);
9349 lpt_init_pch_refclk(dev);
9350
9351 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9352 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9353 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9354 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9355 }
9356
9357 intel_prepare_ddi(dev);
9358 }
9359
9360 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9361 {
9362 struct drm_device *dev = old_state->dev;
9363 struct drm_i915_private *dev_priv = dev->dev_private;
9364 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9365 int req_cdclk;
9366
9367 /* see the comment in valleyview_modeset_global_resources */
9368 if (WARN_ON(max_pixclk < 0))
9369 return;
9370
9371 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9372
9373 if (req_cdclk != dev_priv->cdclk_freq)
9374 broxton_set_cdclk(dev, req_cdclk);
9375 }
9376
9377 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9378 struct intel_crtc_state *crtc_state)
9379 {
9380 if (!intel_ddi_pll_select(crtc, crtc_state))
9381 return -EINVAL;
9382
9383 crtc->lowfreq_avail = false;
9384
9385 return 0;
9386 }
9387
9388 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9389 enum port port,
9390 struct intel_crtc_state *pipe_config)
9391 {
9392 switch (port) {
9393 case PORT_A:
9394 pipe_config->ddi_pll_sel = SKL_DPLL0;
9395 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9396 break;
9397 case PORT_B:
9398 pipe_config->ddi_pll_sel = SKL_DPLL1;
9399 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9400 break;
9401 case PORT_C:
9402 pipe_config->ddi_pll_sel = SKL_DPLL2;
9403 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9404 break;
9405 default:
9406 DRM_ERROR("Incorrect port type\n");
9407 }
9408 }
9409
9410 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9411 enum port port,
9412 struct intel_crtc_state *pipe_config)
9413 {
9414 u32 temp, dpll_ctl1;
9415
9416 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9417 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9418
9419 switch (pipe_config->ddi_pll_sel) {
9420 case SKL_DPLL0:
9421 /*
9422 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9423 * of the shared DPLL framework and thus needs to be read out
9424 * separately
9425 */
9426 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9427 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9428 break;
9429 case SKL_DPLL1:
9430 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9431 break;
9432 case SKL_DPLL2:
9433 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9434 break;
9435 case SKL_DPLL3:
9436 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9437 break;
9438 }
9439 }
9440
9441 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9442 enum port port,
9443 struct intel_crtc_state *pipe_config)
9444 {
9445 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9446
9447 switch (pipe_config->ddi_pll_sel) {
9448 case PORT_CLK_SEL_WRPLL1:
9449 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9450 break;
9451 case PORT_CLK_SEL_WRPLL2:
9452 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9453 break;
9454 }
9455 }
9456
9457 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9458 struct intel_crtc_state *pipe_config)
9459 {
9460 struct drm_device *dev = crtc->base.dev;
9461 struct drm_i915_private *dev_priv = dev->dev_private;
9462 struct intel_shared_dpll *pll;
9463 enum port port;
9464 uint32_t tmp;
9465
9466 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9467
9468 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9469
9470 if (IS_SKYLAKE(dev))
9471 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9472 else if (IS_BROXTON(dev))
9473 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9474 else
9475 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9476
9477 if (pipe_config->shared_dpll >= 0) {
9478 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9479
9480 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9481 &pipe_config->dpll_hw_state));
9482 }
9483
9484 /*
9485 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9486 * DDI E. So just check whether this pipe is wired to DDI E and whether
9487 * the PCH transcoder is on.
9488 */
9489 if (INTEL_INFO(dev)->gen < 9 &&
9490 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9491 pipe_config->has_pch_encoder = true;
9492
9493 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9494 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9495 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9496
9497 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9498 }
9499 }
9500
9501 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9502 struct intel_crtc_state *pipe_config)
9503 {
9504 struct drm_device *dev = crtc->base.dev;
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506 enum intel_display_power_domain pfit_domain;
9507 uint32_t tmp;
9508
9509 if (!intel_display_power_is_enabled(dev_priv,
9510 POWER_DOMAIN_PIPE(crtc->pipe)))
9511 return false;
9512
9513 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9514 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9515
9516 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9517 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9518 enum pipe trans_edp_pipe;
9519 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9520 default:
9521 WARN(1, "unknown pipe linked to edp transcoder\n");
9522 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9523 case TRANS_DDI_EDP_INPUT_A_ON:
9524 trans_edp_pipe = PIPE_A;
9525 break;
9526 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9527 trans_edp_pipe = PIPE_B;
9528 break;
9529 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9530 trans_edp_pipe = PIPE_C;
9531 break;
9532 }
9533
9534 if (trans_edp_pipe == crtc->pipe)
9535 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9536 }
9537
9538 if (!intel_display_power_is_enabled(dev_priv,
9539 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9540 return false;
9541
9542 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9543 if (!(tmp & PIPECONF_ENABLE))
9544 return false;
9545
9546 haswell_get_ddi_port_state(crtc, pipe_config);
9547
9548 intel_get_pipe_timings(crtc, pipe_config);
9549
9550 if (INTEL_INFO(dev)->gen >= 9) {
9551 skl_init_scalers(dev, crtc, pipe_config);
9552 }
9553
9554 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9555
9556 if (INTEL_INFO(dev)->gen >= 9) {
9557 pipe_config->scaler_state.scaler_id = -1;
9558 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9559 }
9560
9561 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9562 if (INTEL_INFO(dev)->gen == 9)
9563 skylake_get_pfit_config(crtc, pipe_config);
9564 else if (INTEL_INFO(dev)->gen < 9)
9565 ironlake_get_pfit_config(crtc, pipe_config);
9566 else
9567 MISSING_CASE(INTEL_INFO(dev)->gen);
9568 }
9569
9570 if (IS_HASWELL(dev))
9571 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9572 (I915_READ(IPS_CTL) & IPS_ENABLE);
9573
9574 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9575 pipe_config->pixel_multiplier =
9576 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9577 } else {
9578 pipe_config->pixel_multiplier = 1;
9579 }
9580
9581 return true;
9582 }
9583
9584 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9585 {
9586 struct drm_device *dev = crtc->dev;
9587 struct drm_i915_private *dev_priv = dev->dev_private;
9588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9589 uint32_t cntl = 0, size = 0;
9590
9591 if (base) {
9592 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9593 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9594 unsigned int stride = roundup_pow_of_two(width) * 4;
9595
9596 switch (stride) {
9597 default:
9598 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9599 width, stride);
9600 stride = 256;
9601 /* fallthrough */
9602 case 256:
9603 case 512:
9604 case 1024:
9605 case 2048:
9606 break;
9607 }
9608
9609 cntl |= CURSOR_ENABLE |
9610 CURSOR_GAMMA_ENABLE |
9611 CURSOR_FORMAT_ARGB |
9612 CURSOR_STRIDE(stride);
9613
9614 size = (height << 12) | width;
9615 }
9616
9617 if (intel_crtc->cursor_cntl != 0 &&
9618 (intel_crtc->cursor_base != base ||
9619 intel_crtc->cursor_size != size ||
9620 intel_crtc->cursor_cntl != cntl)) {
9621 /* On these chipsets we can only modify the base/size/stride
9622 * whilst the cursor is disabled.
9623 */
9624 I915_WRITE(_CURACNTR, 0);
9625 POSTING_READ(_CURACNTR);
9626 intel_crtc->cursor_cntl = 0;
9627 }
9628
9629 if (intel_crtc->cursor_base != base) {
9630 I915_WRITE(_CURABASE, base);
9631 intel_crtc->cursor_base = base;
9632 }
9633
9634 if (intel_crtc->cursor_size != size) {
9635 I915_WRITE(CURSIZE, size);
9636 intel_crtc->cursor_size = size;
9637 }
9638
9639 if (intel_crtc->cursor_cntl != cntl) {
9640 I915_WRITE(_CURACNTR, cntl);
9641 POSTING_READ(_CURACNTR);
9642 intel_crtc->cursor_cntl = cntl;
9643 }
9644 }
9645
9646 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9647 {
9648 struct drm_device *dev = crtc->dev;
9649 struct drm_i915_private *dev_priv = dev->dev_private;
9650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9651 int pipe = intel_crtc->pipe;
9652 uint32_t cntl;
9653
9654 cntl = 0;
9655 if (base) {
9656 cntl = MCURSOR_GAMMA_ENABLE;
9657 switch (intel_crtc->base.cursor->state->crtc_w) {
9658 case 64:
9659 cntl |= CURSOR_MODE_64_ARGB_AX;
9660 break;
9661 case 128:
9662 cntl |= CURSOR_MODE_128_ARGB_AX;
9663 break;
9664 case 256:
9665 cntl |= CURSOR_MODE_256_ARGB_AX;
9666 break;
9667 default:
9668 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9669 return;
9670 }
9671 cntl |= pipe << 28; /* Connect to correct pipe */
9672
9673 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9674 cntl |= CURSOR_PIPE_CSC_ENABLE;
9675 }
9676
9677 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9678 cntl |= CURSOR_ROTATE_180;
9679
9680 if (intel_crtc->cursor_cntl != cntl) {
9681 I915_WRITE(CURCNTR(pipe), cntl);
9682 POSTING_READ(CURCNTR(pipe));
9683 intel_crtc->cursor_cntl = cntl;
9684 }
9685
9686 /* and commit changes on next vblank */
9687 I915_WRITE(CURBASE(pipe), base);
9688 POSTING_READ(CURBASE(pipe));
9689
9690 intel_crtc->cursor_base = base;
9691 }
9692
9693 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9694 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9695 bool on)
9696 {
9697 struct drm_device *dev = crtc->dev;
9698 struct drm_i915_private *dev_priv = dev->dev_private;
9699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9700 int pipe = intel_crtc->pipe;
9701 int x = crtc->cursor_x;
9702 int y = crtc->cursor_y;
9703 u32 base = 0, pos = 0;
9704
9705 if (on)
9706 base = intel_crtc->cursor_addr;
9707
9708 if (x >= intel_crtc->config->pipe_src_w)
9709 base = 0;
9710
9711 if (y >= intel_crtc->config->pipe_src_h)
9712 base = 0;
9713
9714 if (x < 0) {
9715 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9716 base = 0;
9717
9718 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9719 x = -x;
9720 }
9721 pos |= x << CURSOR_X_SHIFT;
9722
9723 if (y < 0) {
9724 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9725 base = 0;
9726
9727 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9728 y = -y;
9729 }
9730 pos |= y << CURSOR_Y_SHIFT;
9731
9732 if (base == 0 && intel_crtc->cursor_base == 0)
9733 return;
9734
9735 I915_WRITE(CURPOS(pipe), pos);
9736
9737 /* ILK+ do this automagically */
9738 if (HAS_GMCH_DISPLAY(dev) &&
9739 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9740 base += (intel_crtc->base.cursor->state->crtc_h *
9741 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9742 }
9743
9744 if (IS_845G(dev) || IS_I865G(dev))
9745 i845_update_cursor(crtc, base);
9746 else
9747 i9xx_update_cursor(crtc, base);
9748 }
9749
9750 static bool cursor_size_ok(struct drm_device *dev,
9751 uint32_t width, uint32_t height)
9752 {
9753 if (width == 0 || height == 0)
9754 return false;
9755
9756 /*
9757 * 845g/865g are special in that they are only limited by
9758 * the width of their cursors, the height is arbitrary up to
9759 * the precision of the register. Everything else requires
9760 * square cursors, limited to a few power-of-two sizes.
9761 */
9762 if (IS_845G(dev) || IS_I865G(dev)) {
9763 if ((width & 63) != 0)
9764 return false;
9765
9766 if (width > (IS_845G(dev) ? 64 : 512))
9767 return false;
9768
9769 if (height > 1023)
9770 return false;
9771 } else {
9772 switch (width | height) {
9773 case 256:
9774 case 128:
9775 if (IS_GEN2(dev))
9776 return false;
9777 case 64:
9778 break;
9779 default:
9780 return false;
9781 }
9782 }
9783
9784 return true;
9785 }
9786
9787 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9788 u16 *blue, uint32_t start, uint32_t size)
9789 {
9790 int end = (start + size > 256) ? 256 : start + size, i;
9791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9792
9793 for (i = start; i < end; i++) {
9794 intel_crtc->lut_r[i] = red[i] >> 8;
9795 intel_crtc->lut_g[i] = green[i] >> 8;
9796 intel_crtc->lut_b[i] = blue[i] >> 8;
9797 }
9798
9799 intel_crtc_load_lut(crtc);
9800 }
9801
9802 /* VESA 640x480x72Hz mode to set on the pipe */
9803 static struct drm_display_mode load_detect_mode = {
9804 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9805 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9806 };
9807
9808 struct drm_framebuffer *
9809 __intel_framebuffer_create(struct drm_device *dev,
9810 struct drm_mode_fb_cmd2 *mode_cmd,
9811 struct drm_i915_gem_object *obj)
9812 {
9813 struct intel_framebuffer *intel_fb;
9814 int ret;
9815
9816 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9817 if (!intel_fb) {
9818 drm_gem_object_unreference(&obj->base);
9819 return ERR_PTR(-ENOMEM);
9820 }
9821
9822 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9823 if (ret)
9824 goto err;
9825
9826 return &intel_fb->base;
9827 err:
9828 drm_gem_object_unreference(&obj->base);
9829 kfree(intel_fb);
9830
9831 return ERR_PTR(ret);
9832 }
9833
9834 static struct drm_framebuffer *
9835 intel_framebuffer_create(struct drm_device *dev,
9836 struct drm_mode_fb_cmd2 *mode_cmd,
9837 struct drm_i915_gem_object *obj)
9838 {
9839 struct drm_framebuffer *fb;
9840 int ret;
9841
9842 ret = i915_mutex_lock_interruptible(dev);
9843 if (ret)
9844 return ERR_PTR(ret);
9845 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9846 mutex_unlock(&dev->struct_mutex);
9847
9848 return fb;
9849 }
9850
9851 static u32
9852 intel_framebuffer_pitch_for_width(int width, int bpp)
9853 {
9854 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9855 return ALIGN(pitch, 64);
9856 }
9857
9858 static u32
9859 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9860 {
9861 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9862 return PAGE_ALIGN(pitch * mode->vdisplay);
9863 }
9864
9865 static struct drm_framebuffer *
9866 intel_framebuffer_create_for_mode(struct drm_device *dev,
9867 struct drm_display_mode *mode,
9868 int depth, int bpp)
9869 {
9870 struct drm_i915_gem_object *obj;
9871 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9872
9873 obj = i915_gem_alloc_object(dev,
9874 intel_framebuffer_size_for_mode(mode, bpp));
9875 if (obj == NULL)
9876 return ERR_PTR(-ENOMEM);
9877
9878 mode_cmd.width = mode->hdisplay;
9879 mode_cmd.height = mode->vdisplay;
9880 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9881 bpp);
9882 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9883
9884 return intel_framebuffer_create(dev, &mode_cmd, obj);
9885 }
9886
9887 static struct drm_framebuffer *
9888 mode_fits_in_fbdev(struct drm_device *dev,
9889 struct drm_display_mode *mode)
9890 {
9891 #ifdef CONFIG_DRM_I915_FBDEV
9892 struct drm_i915_private *dev_priv = dev->dev_private;
9893 struct drm_i915_gem_object *obj;
9894 struct drm_framebuffer *fb;
9895
9896 if (!dev_priv->fbdev)
9897 return NULL;
9898
9899 if (!dev_priv->fbdev->fb)
9900 return NULL;
9901
9902 obj = dev_priv->fbdev->fb->obj;
9903 BUG_ON(!obj);
9904
9905 fb = &dev_priv->fbdev->fb->base;
9906 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9907 fb->bits_per_pixel))
9908 return NULL;
9909
9910 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9911 return NULL;
9912
9913 return fb;
9914 #else
9915 return NULL;
9916 #endif
9917 }
9918
9919 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9920 struct drm_crtc *crtc,
9921 struct drm_display_mode *mode,
9922 struct drm_framebuffer *fb,
9923 int x, int y)
9924 {
9925 struct drm_plane_state *plane_state;
9926 int hdisplay, vdisplay;
9927 int ret;
9928
9929 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9930 if (IS_ERR(plane_state))
9931 return PTR_ERR(plane_state);
9932
9933 if (mode)
9934 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9935 else
9936 hdisplay = vdisplay = 0;
9937
9938 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9939 if (ret)
9940 return ret;
9941 drm_atomic_set_fb_for_plane(plane_state, fb);
9942 plane_state->crtc_x = 0;
9943 plane_state->crtc_y = 0;
9944 plane_state->crtc_w = hdisplay;
9945 plane_state->crtc_h = vdisplay;
9946 plane_state->src_x = x << 16;
9947 plane_state->src_y = y << 16;
9948 plane_state->src_w = hdisplay << 16;
9949 plane_state->src_h = vdisplay << 16;
9950
9951 return 0;
9952 }
9953
9954 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9955 struct drm_display_mode *mode,
9956 struct intel_load_detect_pipe *old,
9957 struct drm_modeset_acquire_ctx *ctx)
9958 {
9959 struct intel_crtc *intel_crtc;
9960 struct intel_encoder *intel_encoder =
9961 intel_attached_encoder(connector);
9962 struct drm_crtc *possible_crtc;
9963 struct drm_encoder *encoder = &intel_encoder->base;
9964 struct drm_crtc *crtc = NULL;
9965 struct drm_device *dev = encoder->dev;
9966 struct drm_framebuffer *fb;
9967 struct drm_mode_config *config = &dev->mode_config;
9968 struct drm_atomic_state *state = NULL;
9969 struct drm_connector_state *connector_state;
9970 struct intel_crtc_state *crtc_state;
9971 int ret, i = -1;
9972
9973 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9974 connector->base.id, connector->name,
9975 encoder->base.id, encoder->name);
9976
9977 retry:
9978 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9979 if (ret)
9980 goto fail_unlock;
9981
9982 /*
9983 * Algorithm gets a little messy:
9984 *
9985 * - if the connector already has an assigned crtc, use it (but make
9986 * sure it's on first)
9987 *
9988 * - try to find the first unused crtc that can drive this connector,
9989 * and use that if we find one
9990 */
9991
9992 /* See if we already have a CRTC for this connector */
9993 if (encoder->crtc) {
9994 crtc = encoder->crtc;
9995
9996 ret = drm_modeset_lock(&crtc->mutex, ctx);
9997 if (ret)
9998 goto fail_unlock;
9999 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10000 if (ret)
10001 goto fail_unlock;
10002
10003 old->dpms_mode = connector->dpms;
10004 old->load_detect_temp = false;
10005
10006 /* Make sure the crtc and connector are running */
10007 if (connector->dpms != DRM_MODE_DPMS_ON)
10008 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10009
10010 return true;
10011 }
10012
10013 /* Find an unused one (if possible) */
10014 for_each_crtc(dev, possible_crtc) {
10015 i++;
10016 if (!(encoder->possible_crtcs & (1 << i)))
10017 continue;
10018 if (possible_crtc->state->enable)
10019 continue;
10020 /* This can occur when applying the pipe A quirk on resume. */
10021 if (to_intel_crtc(possible_crtc)->new_enabled)
10022 continue;
10023
10024 crtc = possible_crtc;
10025 break;
10026 }
10027
10028 /*
10029 * If we didn't find an unused CRTC, don't use any.
10030 */
10031 if (!crtc) {
10032 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10033 goto fail_unlock;
10034 }
10035
10036 ret = drm_modeset_lock(&crtc->mutex, ctx);
10037 if (ret)
10038 goto fail_unlock;
10039 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10040 if (ret)
10041 goto fail_unlock;
10042 intel_encoder->new_crtc = to_intel_crtc(crtc);
10043 to_intel_connector(connector)->new_encoder = intel_encoder;
10044
10045 intel_crtc = to_intel_crtc(crtc);
10046 intel_crtc->new_enabled = true;
10047 old->dpms_mode = connector->dpms;
10048 old->load_detect_temp = true;
10049 old->release_fb = NULL;
10050
10051 state = drm_atomic_state_alloc(dev);
10052 if (!state)
10053 return false;
10054
10055 state->acquire_ctx = ctx;
10056
10057 connector_state = drm_atomic_get_connector_state(state, connector);
10058 if (IS_ERR(connector_state)) {
10059 ret = PTR_ERR(connector_state);
10060 goto fail;
10061 }
10062
10063 connector_state->crtc = crtc;
10064 connector_state->best_encoder = &intel_encoder->base;
10065
10066 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10067 if (IS_ERR(crtc_state)) {
10068 ret = PTR_ERR(crtc_state);
10069 goto fail;
10070 }
10071
10072 crtc_state->base.active = crtc_state->base.enable = true;
10073
10074 if (!mode)
10075 mode = &load_detect_mode;
10076
10077 /* We need a framebuffer large enough to accommodate all accesses
10078 * that the plane may generate whilst we perform load detection.
10079 * We can not rely on the fbcon either being present (we get called
10080 * during its initialisation to detect all boot displays, or it may
10081 * not even exist) or that it is large enough to satisfy the
10082 * requested mode.
10083 */
10084 fb = mode_fits_in_fbdev(dev, mode);
10085 if (fb == NULL) {
10086 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10087 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10088 old->release_fb = fb;
10089 } else
10090 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10091 if (IS_ERR(fb)) {
10092 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10093 goto fail;
10094 }
10095
10096 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10097 if (ret)
10098 goto fail;
10099
10100 drm_mode_copy(&crtc_state->base.mode, mode);
10101
10102 if (intel_set_mode(crtc, state)) {
10103 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10104 if (old->release_fb)
10105 old->release_fb->funcs->destroy(old->release_fb);
10106 goto fail;
10107 }
10108 crtc->primary->crtc = crtc;
10109
10110 /* let the connector get through one full cycle before testing */
10111 intel_wait_for_vblank(dev, intel_crtc->pipe);
10112 return true;
10113
10114 fail:
10115 intel_crtc->new_enabled = crtc->state->enable;
10116 fail_unlock:
10117 drm_atomic_state_free(state);
10118 state = NULL;
10119
10120 if (ret == -EDEADLK) {
10121 drm_modeset_backoff(ctx);
10122 goto retry;
10123 }
10124
10125 return false;
10126 }
10127
10128 void intel_release_load_detect_pipe(struct drm_connector *connector,
10129 struct intel_load_detect_pipe *old,
10130 struct drm_modeset_acquire_ctx *ctx)
10131 {
10132 struct drm_device *dev = connector->dev;
10133 struct intel_encoder *intel_encoder =
10134 intel_attached_encoder(connector);
10135 struct drm_encoder *encoder = &intel_encoder->base;
10136 struct drm_crtc *crtc = encoder->crtc;
10137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10138 struct drm_atomic_state *state;
10139 struct drm_connector_state *connector_state;
10140 struct intel_crtc_state *crtc_state;
10141 int ret;
10142
10143 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10144 connector->base.id, connector->name,
10145 encoder->base.id, encoder->name);
10146
10147 if (old->load_detect_temp) {
10148 state = drm_atomic_state_alloc(dev);
10149 if (!state)
10150 goto fail;
10151
10152 state->acquire_ctx = ctx;
10153
10154 connector_state = drm_atomic_get_connector_state(state, connector);
10155 if (IS_ERR(connector_state))
10156 goto fail;
10157
10158 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10159 if (IS_ERR(crtc_state))
10160 goto fail;
10161
10162 to_intel_connector(connector)->new_encoder = NULL;
10163 intel_encoder->new_crtc = NULL;
10164 intel_crtc->new_enabled = false;
10165
10166 connector_state->best_encoder = NULL;
10167 connector_state->crtc = NULL;
10168
10169 crtc_state->base.enable = crtc_state->base.active = false;
10170
10171 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10172 0, 0);
10173 if (ret)
10174 goto fail;
10175
10176 ret = intel_set_mode(crtc, state);
10177 if (ret)
10178 goto fail;
10179
10180 if (old->release_fb) {
10181 drm_framebuffer_unregister_private(old->release_fb);
10182 drm_framebuffer_unreference(old->release_fb);
10183 }
10184
10185 return;
10186 }
10187
10188 /* Switch crtc and encoder back off if necessary */
10189 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10190 connector->funcs->dpms(connector, old->dpms_mode);
10191
10192 return;
10193 fail:
10194 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10195 drm_atomic_state_free(state);
10196 }
10197
10198 static int i9xx_pll_refclk(struct drm_device *dev,
10199 const struct intel_crtc_state *pipe_config)
10200 {
10201 struct drm_i915_private *dev_priv = dev->dev_private;
10202 u32 dpll = pipe_config->dpll_hw_state.dpll;
10203
10204 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10205 return dev_priv->vbt.lvds_ssc_freq;
10206 else if (HAS_PCH_SPLIT(dev))
10207 return 120000;
10208 else if (!IS_GEN2(dev))
10209 return 96000;
10210 else
10211 return 48000;
10212 }
10213
10214 /* Returns the clock of the currently programmed mode of the given pipe. */
10215 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10216 struct intel_crtc_state *pipe_config)
10217 {
10218 struct drm_device *dev = crtc->base.dev;
10219 struct drm_i915_private *dev_priv = dev->dev_private;
10220 int pipe = pipe_config->cpu_transcoder;
10221 u32 dpll = pipe_config->dpll_hw_state.dpll;
10222 u32 fp;
10223 intel_clock_t clock;
10224 int refclk = i9xx_pll_refclk(dev, pipe_config);
10225
10226 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10227 fp = pipe_config->dpll_hw_state.fp0;
10228 else
10229 fp = pipe_config->dpll_hw_state.fp1;
10230
10231 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10232 if (IS_PINEVIEW(dev)) {
10233 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10234 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10235 } else {
10236 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10237 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10238 }
10239
10240 if (!IS_GEN2(dev)) {
10241 if (IS_PINEVIEW(dev))
10242 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10243 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10244 else
10245 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10246 DPLL_FPA01_P1_POST_DIV_SHIFT);
10247
10248 switch (dpll & DPLL_MODE_MASK) {
10249 case DPLLB_MODE_DAC_SERIAL:
10250 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10251 5 : 10;
10252 break;
10253 case DPLLB_MODE_LVDS:
10254 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10255 7 : 14;
10256 break;
10257 default:
10258 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10259 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10260 return;
10261 }
10262
10263 if (IS_PINEVIEW(dev))
10264 pineview_clock(refclk, &clock);
10265 else
10266 i9xx_clock(refclk, &clock);
10267 } else {
10268 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10269 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10270
10271 if (is_lvds) {
10272 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10273 DPLL_FPA01_P1_POST_DIV_SHIFT);
10274
10275 if (lvds & LVDS_CLKB_POWER_UP)
10276 clock.p2 = 7;
10277 else
10278 clock.p2 = 14;
10279 } else {
10280 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10281 clock.p1 = 2;
10282 else {
10283 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10284 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10285 }
10286 if (dpll & PLL_P2_DIVIDE_BY_4)
10287 clock.p2 = 4;
10288 else
10289 clock.p2 = 2;
10290 }
10291
10292 i9xx_clock(refclk, &clock);
10293 }
10294
10295 /*
10296 * This value includes pixel_multiplier. We will use
10297 * port_clock to compute adjusted_mode.crtc_clock in the
10298 * encoder's get_config() function.
10299 */
10300 pipe_config->port_clock = clock.dot;
10301 }
10302
10303 int intel_dotclock_calculate(int link_freq,
10304 const struct intel_link_m_n *m_n)
10305 {
10306 /*
10307 * The calculation for the data clock is:
10308 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10309 * But we want to avoid losing precison if possible, so:
10310 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10311 *
10312 * and the link clock is simpler:
10313 * link_clock = (m * link_clock) / n
10314 */
10315
10316 if (!m_n->link_n)
10317 return 0;
10318
10319 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10320 }
10321
10322 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10323 struct intel_crtc_state *pipe_config)
10324 {
10325 struct drm_device *dev = crtc->base.dev;
10326
10327 /* read out port_clock from the DPLL */
10328 i9xx_crtc_clock_get(crtc, pipe_config);
10329
10330 /*
10331 * This value does not include pixel_multiplier.
10332 * We will check that port_clock and adjusted_mode.crtc_clock
10333 * agree once we know their relationship in the encoder's
10334 * get_config() function.
10335 */
10336 pipe_config->base.adjusted_mode.crtc_clock =
10337 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10338 &pipe_config->fdi_m_n);
10339 }
10340
10341 /** Returns the currently programmed mode of the given pipe. */
10342 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10343 struct drm_crtc *crtc)
10344 {
10345 struct drm_i915_private *dev_priv = dev->dev_private;
10346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10347 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10348 struct drm_display_mode *mode;
10349 struct intel_crtc_state pipe_config;
10350 int htot = I915_READ(HTOTAL(cpu_transcoder));
10351 int hsync = I915_READ(HSYNC(cpu_transcoder));
10352 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10353 int vsync = I915_READ(VSYNC(cpu_transcoder));
10354 enum pipe pipe = intel_crtc->pipe;
10355
10356 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10357 if (!mode)
10358 return NULL;
10359
10360 /*
10361 * Construct a pipe_config sufficient for getting the clock info
10362 * back out of crtc_clock_get.
10363 *
10364 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10365 * to use a real value here instead.
10366 */
10367 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10368 pipe_config.pixel_multiplier = 1;
10369 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10370 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10371 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10372 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10373
10374 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10375 mode->hdisplay = (htot & 0xffff) + 1;
10376 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10377 mode->hsync_start = (hsync & 0xffff) + 1;
10378 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10379 mode->vdisplay = (vtot & 0xffff) + 1;
10380 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10381 mode->vsync_start = (vsync & 0xffff) + 1;
10382 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10383
10384 drm_mode_set_name(mode);
10385
10386 return mode;
10387 }
10388
10389 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10390 {
10391 struct drm_device *dev = crtc->dev;
10392 struct drm_i915_private *dev_priv = dev->dev_private;
10393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10394
10395 if (!HAS_GMCH_DISPLAY(dev))
10396 return;
10397
10398 if (!dev_priv->lvds_downclock_avail)
10399 return;
10400
10401 /*
10402 * Since this is called by a timer, we should never get here in
10403 * the manual case.
10404 */
10405 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10406 int pipe = intel_crtc->pipe;
10407 int dpll_reg = DPLL(pipe);
10408 int dpll;
10409
10410 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10411
10412 assert_panel_unlocked(dev_priv, pipe);
10413
10414 dpll = I915_READ(dpll_reg);
10415 dpll |= DISPLAY_RATE_SELECT_FPA1;
10416 I915_WRITE(dpll_reg, dpll);
10417 intel_wait_for_vblank(dev, pipe);
10418 dpll = I915_READ(dpll_reg);
10419 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10420 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10421 }
10422
10423 }
10424
10425 void intel_mark_busy(struct drm_device *dev)
10426 {
10427 struct drm_i915_private *dev_priv = dev->dev_private;
10428
10429 if (dev_priv->mm.busy)
10430 return;
10431
10432 intel_runtime_pm_get(dev_priv);
10433 i915_update_gfx_val(dev_priv);
10434 if (INTEL_INFO(dev)->gen >= 6)
10435 gen6_rps_busy(dev_priv);
10436 dev_priv->mm.busy = true;
10437 }
10438
10439 void intel_mark_idle(struct drm_device *dev)
10440 {
10441 struct drm_i915_private *dev_priv = dev->dev_private;
10442 struct drm_crtc *crtc;
10443
10444 if (!dev_priv->mm.busy)
10445 return;
10446
10447 dev_priv->mm.busy = false;
10448
10449 for_each_crtc(dev, crtc) {
10450 if (!crtc->primary->fb)
10451 continue;
10452
10453 intel_decrease_pllclock(crtc);
10454 }
10455
10456 if (INTEL_INFO(dev)->gen >= 6)
10457 gen6_rps_idle(dev->dev_private);
10458
10459 intel_runtime_pm_put(dev_priv);
10460 }
10461
10462 static void intel_crtc_destroy(struct drm_crtc *crtc)
10463 {
10464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10465 struct drm_device *dev = crtc->dev;
10466 struct intel_unpin_work *work;
10467
10468 spin_lock_irq(&dev->event_lock);
10469 work = intel_crtc->unpin_work;
10470 intel_crtc->unpin_work = NULL;
10471 spin_unlock_irq(&dev->event_lock);
10472
10473 if (work) {
10474 cancel_work_sync(&work->work);
10475 kfree(work);
10476 }
10477
10478 drm_crtc_cleanup(crtc);
10479
10480 kfree(intel_crtc);
10481 }
10482
10483 static void intel_unpin_work_fn(struct work_struct *__work)
10484 {
10485 struct intel_unpin_work *work =
10486 container_of(__work, struct intel_unpin_work, work);
10487 struct drm_device *dev = work->crtc->dev;
10488 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10489
10490 mutex_lock(&dev->struct_mutex);
10491 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10492 drm_gem_object_unreference(&work->pending_flip_obj->base);
10493
10494 intel_fbc_update(dev);
10495
10496 if (work->flip_queued_req)
10497 i915_gem_request_assign(&work->flip_queued_req, NULL);
10498 mutex_unlock(&dev->struct_mutex);
10499
10500 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10501 drm_framebuffer_unreference(work->old_fb);
10502
10503 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10504 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10505
10506 kfree(work);
10507 }
10508
10509 static void do_intel_finish_page_flip(struct drm_device *dev,
10510 struct drm_crtc *crtc)
10511 {
10512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10513 struct intel_unpin_work *work;
10514 unsigned long flags;
10515
10516 /* Ignore early vblank irqs */
10517 if (intel_crtc == NULL)
10518 return;
10519
10520 /*
10521 * This is called both by irq handlers and the reset code (to complete
10522 * lost pageflips) so needs the full irqsave spinlocks.
10523 */
10524 spin_lock_irqsave(&dev->event_lock, flags);
10525 work = intel_crtc->unpin_work;
10526
10527 /* Ensure we don't miss a work->pending update ... */
10528 smp_rmb();
10529
10530 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10531 spin_unlock_irqrestore(&dev->event_lock, flags);
10532 return;
10533 }
10534
10535 page_flip_completed(intel_crtc);
10536
10537 spin_unlock_irqrestore(&dev->event_lock, flags);
10538 }
10539
10540 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10541 {
10542 struct drm_i915_private *dev_priv = dev->dev_private;
10543 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10544
10545 do_intel_finish_page_flip(dev, crtc);
10546 }
10547
10548 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10549 {
10550 struct drm_i915_private *dev_priv = dev->dev_private;
10551 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10552
10553 do_intel_finish_page_flip(dev, crtc);
10554 }
10555
10556 /* Is 'a' after or equal to 'b'? */
10557 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10558 {
10559 return !((a - b) & 0x80000000);
10560 }
10561
10562 static bool page_flip_finished(struct intel_crtc *crtc)
10563 {
10564 struct drm_device *dev = crtc->base.dev;
10565 struct drm_i915_private *dev_priv = dev->dev_private;
10566
10567 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10568 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10569 return true;
10570
10571 /*
10572 * The relevant registers doen't exist on pre-ctg.
10573 * As the flip done interrupt doesn't trigger for mmio
10574 * flips on gmch platforms, a flip count check isn't
10575 * really needed there. But since ctg has the registers,
10576 * include it in the check anyway.
10577 */
10578 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10579 return true;
10580
10581 /*
10582 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10583 * used the same base address. In that case the mmio flip might
10584 * have completed, but the CS hasn't even executed the flip yet.
10585 *
10586 * A flip count check isn't enough as the CS might have updated
10587 * the base address just after start of vblank, but before we
10588 * managed to process the interrupt. This means we'd complete the
10589 * CS flip too soon.
10590 *
10591 * Combining both checks should get us a good enough result. It may
10592 * still happen that the CS flip has been executed, but has not
10593 * yet actually completed. But in case the base address is the same
10594 * anyway, we don't really care.
10595 */
10596 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10597 crtc->unpin_work->gtt_offset &&
10598 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10599 crtc->unpin_work->flip_count);
10600 }
10601
10602 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10603 {
10604 struct drm_i915_private *dev_priv = dev->dev_private;
10605 struct intel_crtc *intel_crtc =
10606 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10607 unsigned long flags;
10608
10609
10610 /*
10611 * This is called both by irq handlers and the reset code (to complete
10612 * lost pageflips) so needs the full irqsave spinlocks.
10613 *
10614 * NB: An MMIO update of the plane base pointer will also
10615 * generate a page-flip completion irq, i.e. every modeset
10616 * is also accompanied by a spurious intel_prepare_page_flip().
10617 */
10618 spin_lock_irqsave(&dev->event_lock, flags);
10619 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10620 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10621 spin_unlock_irqrestore(&dev->event_lock, flags);
10622 }
10623
10624 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10625 {
10626 /* Ensure that the work item is consistent when activating it ... */
10627 smp_wmb();
10628 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10629 /* and that it is marked active as soon as the irq could fire. */
10630 smp_wmb();
10631 }
10632
10633 static int intel_gen2_queue_flip(struct drm_device *dev,
10634 struct drm_crtc *crtc,
10635 struct drm_framebuffer *fb,
10636 struct drm_i915_gem_object *obj,
10637 struct intel_engine_cs *ring,
10638 uint32_t flags)
10639 {
10640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10641 u32 flip_mask;
10642 int ret;
10643
10644 ret = intel_ring_begin(ring, 6);
10645 if (ret)
10646 return ret;
10647
10648 /* Can't queue multiple flips, so wait for the previous
10649 * one to finish before executing the next.
10650 */
10651 if (intel_crtc->plane)
10652 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10653 else
10654 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10655 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10656 intel_ring_emit(ring, MI_NOOP);
10657 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10658 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10659 intel_ring_emit(ring, fb->pitches[0]);
10660 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10661 intel_ring_emit(ring, 0); /* aux display base address, unused */
10662
10663 intel_mark_page_flip_active(intel_crtc);
10664 __intel_ring_advance(ring);
10665 return 0;
10666 }
10667
10668 static int intel_gen3_queue_flip(struct drm_device *dev,
10669 struct drm_crtc *crtc,
10670 struct drm_framebuffer *fb,
10671 struct drm_i915_gem_object *obj,
10672 struct intel_engine_cs *ring,
10673 uint32_t flags)
10674 {
10675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10676 u32 flip_mask;
10677 int ret;
10678
10679 ret = intel_ring_begin(ring, 6);
10680 if (ret)
10681 return ret;
10682
10683 if (intel_crtc->plane)
10684 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10685 else
10686 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10687 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10688 intel_ring_emit(ring, MI_NOOP);
10689 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10690 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10691 intel_ring_emit(ring, fb->pitches[0]);
10692 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10693 intel_ring_emit(ring, MI_NOOP);
10694
10695 intel_mark_page_flip_active(intel_crtc);
10696 __intel_ring_advance(ring);
10697 return 0;
10698 }
10699
10700 static int intel_gen4_queue_flip(struct drm_device *dev,
10701 struct drm_crtc *crtc,
10702 struct drm_framebuffer *fb,
10703 struct drm_i915_gem_object *obj,
10704 struct intel_engine_cs *ring,
10705 uint32_t flags)
10706 {
10707 struct drm_i915_private *dev_priv = dev->dev_private;
10708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10709 uint32_t pf, pipesrc;
10710 int ret;
10711
10712 ret = intel_ring_begin(ring, 4);
10713 if (ret)
10714 return ret;
10715
10716 /* i965+ uses the linear or tiled offsets from the
10717 * Display Registers (which do not change across a page-flip)
10718 * so we need only reprogram the base address.
10719 */
10720 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10721 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10722 intel_ring_emit(ring, fb->pitches[0]);
10723 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10724 obj->tiling_mode);
10725
10726 /* XXX Enabling the panel-fitter across page-flip is so far
10727 * untested on non-native modes, so ignore it for now.
10728 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10729 */
10730 pf = 0;
10731 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10732 intel_ring_emit(ring, pf | pipesrc);
10733
10734 intel_mark_page_flip_active(intel_crtc);
10735 __intel_ring_advance(ring);
10736 return 0;
10737 }
10738
10739 static int intel_gen6_queue_flip(struct drm_device *dev,
10740 struct drm_crtc *crtc,
10741 struct drm_framebuffer *fb,
10742 struct drm_i915_gem_object *obj,
10743 struct intel_engine_cs *ring,
10744 uint32_t flags)
10745 {
10746 struct drm_i915_private *dev_priv = dev->dev_private;
10747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10748 uint32_t pf, pipesrc;
10749 int ret;
10750
10751 ret = intel_ring_begin(ring, 4);
10752 if (ret)
10753 return ret;
10754
10755 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10756 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10757 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10758 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10759
10760 /* Contrary to the suggestions in the documentation,
10761 * "Enable Panel Fitter" does not seem to be required when page
10762 * flipping with a non-native mode, and worse causes a normal
10763 * modeset to fail.
10764 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10765 */
10766 pf = 0;
10767 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10768 intel_ring_emit(ring, pf | pipesrc);
10769
10770 intel_mark_page_flip_active(intel_crtc);
10771 __intel_ring_advance(ring);
10772 return 0;
10773 }
10774
10775 static int intel_gen7_queue_flip(struct drm_device *dev,
10776 struct drm_crtc *crtc,
10777 struct drm_framebuffer *fb,
10778 struct drm_i915_gem_object *obj,
10779 struct intel_engine_cs *ring,
10780 uint32_t flags)
10781 {
10782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10783 uint32_t plane_bit = 0;
10784 int len, ret;
10785
10786 switch (intel_crtc->plane) {
10787 case PLANE_A:
10788 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10789 break;
10790 case PLANE_B:
10791 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10792 break;
10793 case PLANE_C:
10794 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10795 break;
10796 default:
10797 WARN_ONCE(1, "unknown plane in flip command\n");
10798 return -ENODEV;
10799 }
10800
10801 len = 4;
10802 if (ring->id == RCS) {
10803 len += 6;
10804 /*
10805 * On Gen 8, SRM is now taking an extra dword to accommodate
10806 * 48bits addresses, and we need a NOOP for the batch size to
10807 * stay even.
10808 */
10809 if (IS_GEN8(dev))
10810 len += 2;
10811 }
10812
10813 /*
10814 * BSpec MI_DISPLAY_FLIP for IVB:
10815 * "The full packet must be contained within the same cache line."
10816 *
10817 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10818 * cacheline, if we ever start emitting more commands before
10819 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10820 * then do the cacheline alignment, and finally emit the
10821 * MI_DISPLAY_FLIP.
10822 */
10823 ret = intel_ring_cacheline_align(ring);
10824 if (ret)
10825 return ret;
10826
10827 ret = intel_ring_begin(ring, len);
10828 if (ret)
10829 return ret;
10830
10831 /* Unmask the flip-done completion message. Note that the bspec says that
10832 * we should do this for both the BCS and RCS, and that we must not unmask
10833 * more than one flip event at any time (or ensure that one flip message
10834 * can be sent by waiting for flip-done prior to queueing new flips).
10835 * Experimentation says that BCS works despite DERRMR masking all
10836 * flip-done completion events and that unmasking all planes at once
10837 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10838 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10839 */
10840 if (ring->id == RCS) {
10841 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10842 intel_ring_emit(ring, DERRMR);
10843 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10844 DERRMR_PIPEB_PRI_FLIP_DONE |
10845 DERRMR_PIPEC_PRI_FLIP_DONE));
10846 if (IS_GEN8(dev))
10847 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10848 MI_SRM_LRM_GLOBAL_GTT);
10849 else
10850 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10851 MI_SRM_LRM_GLOBAL_GTT);
10852 intel_ring_emit(ring, DERRMR);
10853 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10854 if (IS_GEN8(dev)) {
10855 intel_ring_emit(ring, 0);
10856 intel_ring_emit(ring, MI_NOOP);
10857 }
10858 }
10859
10860 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10861 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10862 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10863 intel_ring_emit(ring, (MI_NOOP));
10864
10865 intel_mark_page_flip_active(intel_crtc);
10866 __intel_ring_advance(ring);
10867 return 0;
10868 }
10869
10870 static bool use_mmio_flip(struct intel_engine_cs *ring,
10871 struct drm_i915_gem_object *obj)
10872 {
10873 /*
10874 * This is not being used for older platforms, because
10875 * non-availability of flip done interrupt forces us to use
10876 * CS flips. Older platforms derive flip done using some clever
10877 * tricks involving the flip_pending status bits and vblank irqs.
10878 * So using MMIO flips there would disrupt this mechanism.
10879 */
10880
10881 if (ring == NULL)
10882 return true;
10883
10884 if (INTEL_INFO(ring->dev)->gen < 5)
10885 return false;
10886
10887 if (i915.use_mmio_flip < 0)
10888 return false;
10889 else if (i915.use_mmio_flip > 0)
10890 return true;
10891 else if (i915.enable_execlists)
10892 return true;
10893 else
10894 return ring != i915_gem_request_get_ring(obj->last_write_req);
10895 }
10896
10897 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10898 {
10899 struct drm_device *dev = intel_crtc->base.dev;
10900 struct drm_i915_private *dev_priv = dev->dev_private;
10901 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10902 const enum pipe pipe = intel_crtc->pipe;
10903 u32 ctl, stride;
10904
10905 ctl = I915_READ(PLANE_CTL(pipe, 0));
10906 ctl &= ~PLANE_CTL_TILED_MASK;
10907 switch (fb->modifier[0]) {
10908 case DRM_FORMAT_MOD_NONE:
10909 break;
10910 case I915_FORMAT_MOD_X_TILED:
10911 ctl |= PLANE_CTL_TILED_X;
10912 break;
10913 case I915_FORMAT_MOD_Y_TILED:
10914 ctl |= PLANE_CTL_TILED_Y;
10915 break;
10916 case I915_FORMAT_MOD_Yf_TILED:
10917 ctl |= PLANE_CTL_TILED_YF;
10918 break;
10919 default:
10920 MISSING_CASE(fb->modifier[0]);
10921 }
10922
10923 /*
10924 * The stride is either expressed as a multiple of 64 bytes chunks for
10925 * linear buffers or in number of tiles for tiled buffers.
10926 */
10927 stride = fb->pitches[0] /
10928 intel_fb_stride_alignment(dev, fb->modifier[0],
10929 fb->pixel_format);
10930
10931 /*
10932 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10933 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10934 */
10935 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10936 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10937
10938 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10939 POSTING_READ(PLANE_SURF(pipe, 0));
10940 }
10941
10942 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10943 {
10944 struct drm_device *dev = intel_crtc->base.dev;
10945 struct drm_i915_private *dev_priv = dev->dev_private;
10946 struct intel_framebuffer *intel_fb =
10947 to_intel_framebuffer(intel_crtc->base.primary->fb);
10948 struct drm_i915_gem_object *obj = intel_fb->obj;
10949 u32 dspcntr;
10950 u32 reg;
10951
10952 reg = DSPCNTR(intel_crtc->plane);
10953 dspcntr = I915_READ(reg);
10954
10955 if (obj->tiling_mode != I915_TILING_NONE)
10956 dspcntr |= DISPPLANE_TILED;
10957 else
10958 dspcntr &= ~DISPPLANE_TILED;
10959
10960 I915_WRITE(reg, dspcntr);
10961
10962 I915_WRITE(DSPSURF(intel_crtc->plane),
10963 intel_crtc->unpin_work->gtt_offset);
10964 POSTING_READ(DSPSURF(intel_crtc->plane));
10965
10966 }
10967
10968 /*
10969 * XXX: This is the temporary way to update the plane registers until we get
10970 * around to using the usual plane update functions for MMIO flips
10971 */
10972 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10973 {
10974 struct drm_device *dev = intel_crtc->base.dev;
10975 bool atomic_update;
10976 u32 start_vbl_count;
10977
10978 intel_mark_page_flip_active(intel_crtc);
10979
10980 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10981
10982 if (INTEL_INFO(dev)->gen >= 9)
10983 skl_do_mmio_flip(intel_crtc);
10984 else
10985 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10986 ilk_do_mmio_flip(intel_crtc);
10987
10988 if (atomic_update)
10989 intel_pipe_update_end(intel_crtc, start_vbl_count);
10990 }
10991
10992 static void intel_mmio_flip_work_func(struct work_struct *work)
10993 {
10994 struct intel_mmio_flip *mmio_flip =
10995 container_of(work, struct intel_mmio_flip, work);
10996
10997 if (mmio_flip->req)
10998 WARN_ON(__i915_wait_request(mmio_flip->req,
10999 mmio_flip->crtc->reset_counter,
11000 false, NULL,
11001 &mmio_flip->i915->rps.mmioflips));
11002
11003 intel_do_mmio_flip(mmio_flip->crtc);
11004
11005 i915_gem_request_unreference__unlocked(mmio_flip->req);
11006 kfree(mmio_flip);
11007 }
11008
11009 static int intel_queue_mmio_flip(struct drm_device *dev,
11010 struct drm_crtc *crtc,
11011 struct drm_framebuffer *fb,
11012 struct drm_i915_gem_object *obj,
11013 struct intel_engine_cs *ring,
11014 uint32_t flags)
11015 {
11016 struct intel_mmio_flip *mmio_flip;
11017
11018 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11019 if (mmio_flip == NULL)
11020 return -ENOMEM;
11021
11022 mmio_flip->i915 = to_i915(dev);
11023 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11024 mmio_flip->crtc = to_intel_crtc(crtc);
11025
11026 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11027 schedule_work(&mmio_flip->work);
11028
11029 return 0;
11030 }
11031
11032 static int intel_default_queue_flip(struct drm_device *dev,
11033 struct drm_crtc *crtc,
11034 struct drm_framebuffer *fb,
11035 struct drm_i915_gem_object *obj,
11036 struct intel_engine_cs *ring,
11037 uint32_t flags)
11038 {
11039 return -ENODEV;
11040 }
11041
11042 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11043 struct drm_crtc *crtc)
11044 {
11045 struct drm_i915_private *dev_priv = dev->dev_private;
11046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11047 struct intel_unpin_work *work = intel_crtc->unpin_work;
11048 u32 addr;
11049
11050 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11051 return true;
11052
11053 if (!work->enable_stall_check)
11054 return false;
11055
11056 if (work->flip_ready_vblank == 0) {
11057 if (work->flip_queued_req &&
11058 !i915_gem_request_completed(work->flip_queued_req, true))
11059 return false;
11060
11061 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11062 }
11063
11064 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11065 return false;
11066
11067 /* Potential stall - if we see that the flip has happened,
11068 * assume a missed interrupt. */
11069 if (INTEL_INFO(dev)->gen >= 4)
11070 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11071 else
11072 addr = I915_READ(DSPADDR(intel_crtc->plane));
11073
11074 /* There is a potential issue here with a false positive after a flip
11075 * to the same address. We could address this by checking for a
11076 * non-incrementing frame counter.
11077 */
11078 return addr == work->gtt_offset;
11079 }
11080
11081 void intel_check_page_flip(struct drm_device *dev, int pipe)
11082 {
11083 struct drm_i915_private *dev_priv = dev->dev_private;
11084 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11086 struct intel_unpin_work *work;
11087
11088 WARN_ON(!in_interrupt());
11089
11090 if (crtc == NULL)
11091 return;
11092
11093 spin_lock(&dev->event_lock);
11094 work = intel_crtc->unpin_work;
11095 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11096 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11097 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11098 page_flip_completed(intel_crtc);
11099 work = NULL;
11100 }
11101 if (work != NULL &&
11102 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11103 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11104 spin_unlock(&dev->event_lock);
11105 }
11106
11107 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11108 struct drm_framebuffer *fb,
11109 struct drm_pending_vblank_event *event,
11110 uint32_t page_flip_flags)
11111 {
11112 struct drm_device *dev = crtc->dev;
11113 struct drm_i915_private *dev_priv = dev->dev_private;
11114 struct drm_framebuffer *old_fb = crtc->primary->fb;
11115 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11117 struct drm_plane *primary = crtc->primary;
11118 enum pipe pipe = intel_crtc->pipe;
11119 struct intel_unpin_work *work;
11120 struct intel_engine_cs *ring;
11121 bool mmio_flip;
11122 int ret;
11123
11124 /*
11125 * drm_mode_page_flip_ioctl() should already catch this, but double
11126 * check to be safe. In the future we may enable pageflipping from
11127 * a disabled primary plane.
11128 */
11129 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11130 return -EBUSY;
11131
11132 /* Can't change pixel format via MI display flips. */
11133 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11134 return -EINVAL;
11135
11136 /*
11137 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11138 * Note that pitch changes could also affect these register.
11139 */
11140 if (INTEL_INFO(dev)->gen > 3 &&
11141 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11142 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11143 return -EINVAL;
11144
11145 if (i915_terminally_wedged(&dev_priv->gpu_error))
11146 goto out_hang;
11147
11148 work = kzalloc(sizeof(*work), GFP_KERNEL);
11149 if (work == NULL)
11150 return -ENOMEM;
11151
11152 work->event = event;
11153 work->crtc = crtc;
11154 work->old_fb = old_fb;
11155 INIT_WORK(&work->work, intel_unpin_work_fn);
11156
11157 ret = drm_crtc_vblank_get(crtc);
11158 if (ret)
11159 goto free_work;
11160
11161 /* We borrow the event spin lock for protecting unpin_work */
11162 spin_lock_irq(&dev->event_lock);
11163 if (intel_crtc->unpin_work) {
11164 /* Before declaring the flip queue wedged, check if
11165 * the hardware completed the operation behind our backs.
11166 */
11167 if (__intel_pageflip_stall_check(dev, crtc)) {
11168 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11169 page_flip_completed(intel_crtc);
11170 } else {
11171 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11172 spin_unlock_irq(&dev->event_lock);
11173
11174 drm_crtc_vblank_put(crtc);
11175 kfree(work);
11176 return -EBUSY;
11177 }
11178 }
11179 intel_crtc->unpin_work = work;
11180 spin_unlock_irq(&dev->event_lock);
11181
11182 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11183 flush_workqueue(dev_priv->wq);
11184
11185 /* Reference the objects for the scheduled work. */
11186 drm_framebuffer_reference(work->old_fb);
11187 drm_gem_object_reference(&obj->base);
11188
11189 crtc->primary->fb = fb;
11190 update_state_fb(crtc->primary);
11191
11192 work->pending_flip_obj = obj;
11193
11194 ret = i915_mutex_lock_interruptible(dev);
11195 if (ret)
11196 goto cleanup;
11197
11198 atomic_inc(&intel_crtc->unpin_work_count);
11199 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11200
11201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11202 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11203
11204 if (IS_VALLEYVIEW(dev)) {
11205 ring = &dev_priv->ring[BCS];
11206 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11207 /* vlv: DISPLAY_FLIP fails to change tiling */
11208 ring = NULL;
11209 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11210 ring = &dev_priv->ring[BCS];
11211 } else if (INTEL_INFO(dev)->gen >= 7) {
11212 ring = i915_gem_request_get_ring(obj->last_write_req);
11213 if (ring == NULL || ring->id != RCS)
11214 ring = &dev_priv->ring[BCS];
11215 } else {
11216 ring = &dev_priv->ring[RCS];
11217 }
11218
11219 mmio_flip = use_mmio_flip(ring, obj);
11220
11221 /* When using CS flips, we want to emit semaphores between rings.
11222 * However, when using mmio flips we will create a task to do the
11223 * synchronisation, so all we want here is to pin the framebuffer
11224 * into the display plane and skip any waits.
11225 */
11226 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11227 crtc->primary->state,
11228 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11229 if (ret)
11230 goto cleanup_pending;
11231
11232 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11233 + intel_crtc->dspaddr_offset;
11234
11235 if (mmio_flip) {
11236 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11237 page_flip_flags);
11238 if (ret)
11239 goto cleanup_unpin;
11240
11241 i915_gem_request_assign(&work->flip_queued_req,
11242 obj->last_write_req);
11243 } else {
11244 if (obj->last_write_req) {
11245 ret = i915_gem_check_olr(obj->last_write_req);
11246 if (ret)
11247 goto cleanup_unpin;
11248 }
11249
11250 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11251 page_flip_flags);
11252 if (ret)
11253 goto cleanup_unpin;
11254
11255 i915_gem_request_assign(&work->flip_queued_req,
11256 intel_ring_get_request(ring));
11257 }
11258
11259 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11260 work->enable_stall_check = true;
11261
11262 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11263 INTEL_FRONTBUFFER_PRIMARY(pipe));
11264
11265 intel_fbc_disable(dev);
11266 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11267 mutex_unlock(&dev->struct_mutex);
11268
11269 trace_i915_flip_request(intel_crtc->plane, obj);
11270
11271 return 0;
11272
11273 cleanup_unpin:
11274 intel_unpin_fb_obj(fb, crtc->primary->state);
11275 cleanup_pending:
11276 atomic_dec(&intel_crtc->unpin_work_count);
11277 mutex_unlock(&dev->struct_mutex);
11278 cleanup:
11279 crtc->primary->fb = old_fb;
11280 update_state_fb(crtc->primary);
11281
11282 drm_gem_object_unreference_unlocked(&obj->base);
11283 drm_framebuffer_unreference(work->old_fb);
11284
11285 spin_lock_irq(&dev->event_lock);
11286 intel_crtc->unpin_work = NULL;
11287 spin_unlock_irq(&dev->event_lock);
11288
11289 drm_crtc_vblank_put(crtc);
11290 free_work:
11291 kfree(work);
11292
11293 if (ret == -EIO) {
11294 out_hang:
11295 ret = intel_plane_restore(primary);
11296 if (ret == 0 && event) {
11297 spin_lock_irq(&dev->event_lock);
11298 drm_send_vblank_event(dev, pipe, event);
11299 spin_unlock_irq(&dev->event_lock);
11300 }
11301 }
11302 return ret;
11303 }
11304
11305 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11306 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11307 .load_lut = intel_crtc_load_lut,
11308 .atomic_begin = intel_begin_crtc_commit,
11309 .atomic_flush = intel_finish_crtc_commit,
11310 };
11311
11312 /**
11313 * intel_modeset_update_staged_output_state
11314 *
11315 * Updates the staged output configuration state, e.g. after we've read out the
11316 * current hw state.
11317 */
11318 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11319 {
11320 struct intel_crtc *crtc;
11321 struct intel_encoder *encoder;
11322 struct intel_connector *connector;
11323
11324 for_each_intel_connector(dev, connector) {
11325 connector->new_encoder =
11326 to_intel_encoder(connector->base.encoder);
11327 }
11328
11329 for_each_intel_encoder(dev, encoder) {
11330 encoder->new_crtc =
11331 to_intel_crtc(encoder->base.crtc);
11332 }
11333
11334 for_each_intel_crtc(dev, crtc) {
11335 crtc->new_enabled = crtc->base.state->enable;
11336 }
11337 }
11338
11339 /* Transitional helper to copy current connector/encoder state to
11340 * connector->state. This is needed so that code that is partially
11341 * converted to atomic does the right thing.
11342 */
11343 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11344 {
11345 struct intel_connector *connector;
11346
11347 for_each_intel_connector(dev, connector) {
11348 if (connector->base.encoder) {
11349 connector->base.state->best_encoder =
11350 connector->base.encoder;
11351 connector->base.state->crtc =
11352 connector->base.encoder->crtc;
11353 } else {
11354 connector->base.state->best_encoder = NULL;
11355 connector->base.state->crtc = NULL;
11356 }
11357 }
11358 }
11359
11360 /* Fixup legacy state after an atomic state swap.
11361 */
11362 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11363 {
11364 struct intel_crtc *crtc;
11365 struct intel_encoder *encoder;
11366 struct intel_connector *connector;
11367
11368 for_each_intel_connector(state->dev, connector) {
11369 connector->base.encoder = connector->base.state->best_encoder;
11370 if (connector->base.encoder)
11371 connector->base.encoder->crtc =
11372 connector->base.state->crtc;
11373 }
11374
11375 /* Update crtc of disabled encoders */
11376 for_each_intel_encoder(state->dev, encoder) {
11377 int num_connectors = 0;
11378
11379 for_each_intel_connector(state->dev, connector)
11380 if (connector->base.encoder == &encoder->base)
11381 num_connectors++;
11382
11383 if (num_connectors == 0)
11384 encoder->base.crtc = NULL;
11385 }
11386
11387 for_each_intel_crtc(state->dev, crtc) {
11388 crtc->base.enabled = crtc->base.state->enable;
11389 crtc->config = to_intel_crtc_state(crtc->base.state);
11390 }
11391
11392 /* Copy the new configuration to the staged state, to keep the few
11393 * pieces of code that haven't been converted yet happy */
11394 intel_modeset_update_staged_output_state(state->dev);
11395 }
11396
11397 static void
11398 connected_sink_compute_bpp(struct intel_connector *connector,
11399 struct intel_crtc_state *pipe_config)
11400 {
11401 int bpp = pipe_config->pipe_bpp;
11402
11403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11404 connector->base.base.id,
11405 connector->base.name);
11406
11407 /* Don't use an invalid EDID bpc value */
11408 if (connector->base.display_info.bpc &&
11409 connector->base.display_info.bpc * 3 < bpp) {
11410 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11411 bpp, connector->base.display_info.bpc*3);
11412 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11413 }
11414
11415 /* Clamp bpp to 8 on screens without EDID 1.4 */
11416 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11417 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11418 bpp);
11419 pipe_config->pipe_bpp = 24;
11420 }
11421 }
11422
11423 static int
11424 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11425 struct intel_crtc_state *pipe_config)
11426 {
11427 struct drm_device *dev = crtc->base.dev;
11428 struct drm_atomic_state *state;
11429 struct drm_connector *connector;
11430 struct drm_connector_state *connector_state;
11431 int bpp, i;
11432
11433 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11434 bpp = 10*3;
11435 else if (INTEL_INFO(dev)->gen >= 5)
11436 bpp = 12*3;
11437 else
11438 bpp = 8*3;
11439
11440
11441 pipe_config->pipe_bpp = bpp;
11442
11443 state = pipe_config->base.state;
11444
11445 /* Clamp display bpp to EDID value */
11446 for_each_connector_in_state(state, connector, connector_state, i) {
11447 if (connector_state->crtc != &crtc->base)
11448 continue;
11449
11450 connected_sink_compute_bpp(to_intel_connector(connector),
11451 pipe_config);
11452 }
11453
11454 return bpp;
11455 }
11456
11457 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11458 {
11459 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11460 "type: 0x%x flags: 0x%x\n",
11461 mode->crtc_clock,
11462 mode->crtc_hdisplay, mode->crtc_hsync_start,
11463 mode->crtc_hsync_end, mode->crtc_htotal,
11464 mode->crtc_vdisplay, mode->crtc_vsync_start,
11465 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11466 }
11467
11468 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11469 struct intel_crtc_state *pipe_config,
11470 const char *context)
11471 {
11472 struct drm_device *dev = crtc->base.dev;
11473 struct drm_plane *plane;
11474 struct intel_plane *intel_plane;
11475 struct intel_plane_state *state;
11476 struct drm_framebuffer *fb;
11477
11478 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11479 context, pipe_config, pipe_name(crtc->pipe));
11480
11481 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11482 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11483 pipe_config->pipe_bpp, pipe_config->dither);
11484 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11485 pipe_config->has_pch_encoder,
11486 pipe_config->fdi_lanes,
11487 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11488 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11489 pipe_config->fdi_m_n.tu);
11490 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11491 pipe_config->has_dp_encoder,
11492 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11493 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11494 pipe_config->dp_m_n.tu);
11495
11496 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11497 pipe_config->has_dp_encoder,
11498 pipe_config->dp_m2_n2.gmch_m,
11499 pipe_config->dp_m2_n2.gmch_n,
11500 pipe_config->dp_m2_n2.link_m,
11501 pipe_config->dp_m2_n2.link_n,
11502 pipe_config->dp_m2_n2.tu);
11503
11504 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11505 pipe_config->has_audio,
11506 pipe_config->has_infoframe);
11507
11508 DRM_DEBUG_KMS("requested mode:\n");
11509 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11510 DRM_DEBUG_KMS("adjusted mode:\n");
11511 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11512 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11513 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11514 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11515 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11516 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11517 crtc->num_scalers,
11518 pipe_config->scaler_state.scaler_users,
11519 pipe_config->scaler_state.scaler_id);
11520 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11521 pipe_config->gmch_pfit.control,
11522 pipe_config->gmch_pfit.pgm_ratios,
11523 pipe_config->gmch_pfit.lvds_border_bits);
11524 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11525 pipe_config->pch_pfit.pos,
11526 pipe_config->pch_pfit.size,
11527 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11528 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11529 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11530
11531 if (IS_BROXTON(dev)) {
11532 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11533 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11534 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11535 pipe_config->ddi_pll_sel,
11536 pipe_config->dpll_hw_state.ebb0,
11537 pipe_config->dpll_hw_state.pll0,
11538 pipe_config->dpll_hw_state.pll1,
11539 pipe_config->dpll_hw_state.pll2,
11540 pipe_config->dpll_hw_state.pll3,
11541 pipe_config->dpll_hw_state.pll6,
11542 pipe_config->dpll_hw_state.pll8,
11543 pipe_config->dpll_hw_state.pcsdw12);
11544 } else if (IS_SKYLAKE(dev)) {
11545 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11546 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11547 pipe_config->ddi_pll_sel,
11548 pipe_config->dpll_hw_state.ctrl1,
11549 pipe_config->dpll_hw_state.cfgcr1,
11550 pipe_config->dpll_hw_state.cfgcr2);
11551 } else if (HAS_DDI(dev)) {
11552 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11553 pipe_config->ddi_pll_sel,
11554 pipe_config->dpll_hw_state.wrpll);
11555 } else {
11556 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11557 "fp0: 0x%x, fp1: 0x%x\n",
11558 pipe_config->dpll_hw_state.dpll,
11559 pipe_config->dpll_hw_state.dpll_md,
11560 pipe_config->dpll_hw_state.fp0,
11561 pipe_config->dpll_hw_state.fp1);
11562 }
11563
11564 DRM_DEBUG_KMS("planes on this crtc\n");
11565 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11566 intel_plane = to_intel_plane(plane);
11567 if (intel_plane->pipe != crtc->pipe)
11568 continue;
11569
11570 state = to_intel_plane_state(plane->state);
11571 fb = state->base.fb;
11572 if (!fb) {
11573 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11574 "disabled, scaler_id = %d\n",
11575 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11576 plane->base.id, intel_plane->pipe,
11577 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11578 drm_plane_index(plane), state->scaler_id);
11579 continue;
11580 }
11581
11582 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11583 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11584 plane->base.id, intel_plane->pipe,
11585 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11586 drm_plane_index(plane));
11587 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11588 fb->base.id, fb->width, fb->height, fb->pixel_format);
11589 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11590 state->scaler_id,
11591 state->src.x1 >> 16, state->src.y1 >> 16,
11592 drm_rect_width(&state->src) >> 16,
11593 drm_rect_height(&state->src) >> 16,
11594 state->dst.x1, state->dst.y1,
11595 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11596 }
11597 }
11598
11599 static bool encoders_cloneable(const struct intel_encoder *a,
11600 const struct intel_encoder *b)
11601 {
11602 /* masks could be asymmetric, so check both ways */
11603 return a == b || (a->cloneable & (1 << b->type) &&
11604 b->cloneable & (1 << a->type));
11605 }
11606
11607 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11608 struct intel_crtc *crtc,
11609 struct intel_encoder *encoder)
11610 {
11611 struct intel_encoder *source_encoder;
11612 struct drm_connector *connector;
11613 struct drm_connector_state *connector_state;
11614 int i;
11615
11616 for_each_connector_in_state(state, connector, connector_state, i) {
11617 if (connector_state->crtc != &crtc->base)
11618 continue;
11619
11620 source_encoder =
11621 to_intel_encoder(connector_state->best_encoder);
11622 if (!encoders_cloneable(encoder, source_encoder))
11623 return false;
11624 }
11625
11626 return true;
11627 }
11628
11629 static bool check_encoder_cloning(struct drm_atomic_state *state,
11630 struct intel_crtc *crtc)
11631 {
11632 struct intel_encoder *encoder;
11633 struct drm_connector *connector;
11634 struct drm_connector_state *connector_state;
11635 int i;
11636
11637 for_each_connector_in_state(state, connector, connector_state, i) {
11638 if (connector_state->crtc != &crtc->base)
11639 continue;
11640
11641 encoder = to_intel_encoder(connector_state->best_encoder);
11642 if (!check_single_encoder_cloning(state, crtc, encoder))
11643 return false;
11644 }
11645
11646 return true;
11647 }
11648
11649 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11650 {
11651 struct drm_device *dev = state->dev;
11652 struct intel_encoder *encoder;
11653 struct drm_connector *connector;
11654 struct drm_connector_state *connector_state;
11655 unsigned int used_ports = 0;
11656 int i;
11657
11658 /*
11659 * Walk the connector list instead of the encoder
11660 * list to detect the problem on ddi platforms
11661 * where there's just one encoder per digital port.
11662 */
11663 for_each_connector_in_state(state, connector, connector_state, i) {
11664 if (!connector_state->best_encoder)
11665 continue;
11666
11667 encoder = to_intel_encoder(connector_state->best_encoder);
11668
11669 WARN_ON(!connector_state->crtc);
11670
11671 switch (encoder->type) {
11672 unsigned int port_mask;
11673 case INTEL_OUTPUT_UNKNOWN:
11674 if (WARN_ON(!HAS_DDI(dev)))
11675 break;
11676 case INTEL_OUTPUT_DISPLAYPORT:
11677 case INTEL_OUTPUT_HDMI:
11678 case INTEL_OUTPUT_EDP:
11679 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11680
11681 /* the same port mustn't appear more than once */
11682 if (used_ports & port_mask)
11683 return false;
11684
11685 used_ports |= port_mask;
11686 default:
11687 break;
11688 }
11689 }
11690
11691 return true;
11692 }
11693
11694 static void
11695 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11696 {
11697 struct drm_crtc_state tmp_state;
11698 struct intel_crtc_scaler_state scaler_state;
11699 struct intel_dpll_hw_state dpll_hw_state;
11700 enum intel_dpll_id shared_dpll;
11701 uint32_t ddi_pll_sel;
11702
11703 /* FIXME: before the switch to atomic started, a new pipe_config was
11704 * kzalloc'd. Code that depends on any field being zero should be
11705 * fixed, so that the crtc_state can be safely duplicated. For now,
11706 * only fields that are know to not cause problems are preserved. */
11707
11708 tmp_state = crtc_state->base;
11709 scaler_state = crtc_state->scaler_state;
11710 shared_dpll = crtc_state->shared_dpll;
11711 dpll_hw_state = crtc_state->dpll_hw_state;
11712 ddi_pll_sel = crtc_state->ddi_pll_sel;
11713
11714 memset(crtc_state, 0, sizeof *crtc_state);
11715
11716 crtc_state->base = tmp_state;
11717 crtc_state->scaler_state = scaler_state;
11718 crtc_state->shared_dpll = shared_dpll;
11719 crtc_state->dpll_hw_state = dpll_hw_state;
11720 crtc_state->ddi_pll_sel = ddi_pll_sel;
11721 }
11722
11723 static int
11724 intel_modeset_pipe_config(struct drm_crtc *crtc,
11725 struct drm_atomic_state *state,
11726 struct intel_crtc_state *pipe_config)
11727 {
11728 struct intel_encoder *encoder;
11729 struct drm_connector *connector;
11730 struct drm_connector_state *connector_state;
11731 int base_bpp, ret = -EINVAL;
11732 int i;
11733 bool retry = true;
11734
11735 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11736 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11737 return -EINVAL;
11738 }
11739
11740 if (!check_digital_port_conflicts(state)) {
11741 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11742 return -EINVAL;
11743 }
11744
11745 clear_intel_crtc_state(pipe_config);
11746
11747 pipe_config->cpu_transcoder =
11748 (enum transcoder) to_intel_crtc(crtc)->pipe;
11749
11750 /*
11751 * Sanitize sync polarity flags based on requested ones. If neither
11752 * positive or negative polarity is requested, treat this as meaning
11753 * negative polarity.
11754 */
11755 if (!(pipe_config->base.adjusted_mode.flags &
11756 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11757 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11758
11759 if (!(pipe_config->base.adjusted_mode.flags &
11760 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11761 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11762
11763 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11764 * plane pixel format and any sink constraints into account. Returns the
11765 * source plane bpp so that dithering can be selected on mismatches
11766 * after encoders and crtc also have had their say. */
11767 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11768 pipe_config);
11769 if (base_bpp < 0)
11770 goto fail;
11771
11772 /*
11773 * Determine the real pipe dimensions. Note that stereo modes can
11774 * increase the actual pipe size due to the frame doubling and
11775 * insertion of additional space for blanks between the frame. This
11776 * is stored in the crtc timings. We use the requested mode to do this
11777 * computation to clearly distinguish it from the adjusted mode, which
11778 * can be changed by the connectors in the below retry loop.
11779 */
11780 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11781 &pipe_config->pipe_src_w,
11782 &pipe_config->pipe_src_h);
11783
11784 encoder_retry:
11785 /* Ensure the port clock defaults are reset when retrying. */
11786 pipe_config->port_clock = 0;
11787 pipe_config->pixel_multiplier = 1;
11788
11789 /* Fill in default crtc timings, allow encoders to overwrite them. */
11790 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11791 CRTC_STEREO_DOUBLE);
11792
11793 /* Pass our mode to the connectors and the CRTC to give them a chance to
11794 * adjust it according to limitations or connector properties, and also
11795 * a chance to reject the mode entirely.
11796 */
11797 for_each_connector_in_state(state, connector, connector_state, i) {
11798 if (connector_state->crtc != crtc)
11799 continue;
11800
11801 encoder = to_intel_encoder(connector_state->best_encoder);
11802
11803 if (!(encoder->compute_config(encoder, pipe_config))) {
11804 DRM_DEBUG_KMS("Encoder config failure\n");
11805 goto fail;
11806 }
11807 }
11808
11809 /* Set default port clock if not overwritten by the encoder. Needs to be
11810 * done afterwards in case the encoder adjusts the mode. */
11811 if (!pipe_config->port_clock)
11812 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11813 * pipe_config->pixel_multiplier;
11814
11815 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11816 if (ret < 0) {
11817 DRM_DEBUG_KMS("CRTC fixup failed\n");
11818 goto fail;
11819 }
11820
11821 if (ret == RETRY) {
11822 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11823 ret = -EINVAL;
11824 goto fail;
11825 }
11826
11827 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11828 retry = false;
11829 goto encoder_retry;
11830 }
11831
11832 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11833 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11834 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11835
11836 return 0;
11837 fail:
11838 return ret;
11839 }
11840
11841 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11842 {
11843 struct drm_encoder *encoder;
11844 struct drm_device *dev = crtc->dev;
11845
11846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11847 if (encoder->crtc == crtc)
11848 return true;
11849
11850 return false;
11851 }
11852
11853 static bool
11854 needs_modeset(struct drm_crtc_state *state)
11855 {
11856 return state->mode_changed || state->active_changed;
11857 }
11858
11859 static void
11860 intel_modeset_update_state(struct drm_atomic_state *state)
11861 {
11862 struct drm_device *dev = state->dev;
11863 struct drm_i915_private *dev_priv = dev->dev_private;
11864 struct intel_encoder *intel_encoder;
11865 struct drm_crtc *crtc;
11866 struct drm_crtc_state *crtc_state;
11867 struct drm_connector *connector;
11868 int i;
11869
11870 intel_shared_dpll_commit(dev_priv);
11871
11872 for_each_intel_encoder(dev, intel_encoder) {
11873 if (!intel_encoder->base.crtc)
11874 continue;
11875
11876 for_each_crtc_in_state(state, crtc, crtc_state, i)
11877 if (crtc == intel_encoder->base.crtc)
11878 break;
11879
11880 if (crtc != intel_encoder->base.crtc)
11881 continue;
11882
11883 if (crtc_state->enable && needs_modeset(crtc_state))
11884 intel_encoder->connectors_active = false;
11885 }
11886
11887 drm_atomic_helper_swap_state(state->dev, state);
11888 intel_modeset_fixup_state(state);
11889
11890 /* Double check state. */
11891 for_each_crtc(dev, crtc) {
11892 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11893 }
11894
11895 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11896 if (!connector->encoder || !connector->encoder->crtc)
11897 continue;
11898
11899 for_each_crtc_in_state(state, crtc, crtc_state, i)
11900 if (crtc == connector->encoder->crtc)
11901 break;
11902
11903 if (crtc != connector->encoder->crtc)
11904 continue;
11905
11906 if (crtc->state->enable && needs_modeset(crtc->state)) {
11907 struct drm_property *dpms_property =
11908 dev->mode_config.dpms_property;
11909
11910 connector->dpms = DRM_MODE_DPMS_ON;
11911 drm_object_property_set_value(&connector->base,
11912 dpms_property,
11913 DRM_MODE_DPMS_ON);
11914
11915 intel_encoder = to_intel_encoder(connector->encoder);
11916 intel_encoder->connectors_active = true;
11917 }
11918 }
11919
11920 }
11921
11922 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11923 {
11924 int diff;
11925
11926 if (clock1 == clock2)
11927 return true;
11928
11929 if (!clock1 || !clock2)
11930 return false;
11931
11932 diff = abs(clock1 - clock2);
11933
11934 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11935 return true;
11936
11937 return false;
11938 }
11939
11940 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11941 list_for_each_entry((intel_crtc), \
11942 &(dev)->mode_config.crtc_list, \
11943 base.head) \
11944 if (mask & (1 <<(intel_crtc)->pipe))
11945
11946 static bool
11947 intel_pipe_config_compare(struct drm_device *dev,
11948 struct intel_crtc_state *current_config,
11949 struct intel_crtc_state *pipe_config)
11950 {
11951 #define PIPE_CONF_CHECK_X(name) \
11952 if (current_config->name != pipe_config->name) { \
11953 DRM_ERROR("mismatch in " #name " " \
11954 "(expected 0x%08x, found 0x%08x)\n", \
11955 current_config->name, \
11956 pipe_config->name); \
11957 return false; \
11958 }
11959
11960 #define PIPE_CONF_CHECK_I(name) \
11961 if (current_config->name != pipe_config->name) { \
11962 DRM_ERROR("mismatch in " #name " " \
11963 "(expected %i, found %i)\n", \
11964 current_config->name, \
11965 pipe_config->name); \
11966 return false; \
11967 }
11968
11969 /* This is required for BDW+ where there is only one set of registers for
11970 * switching between high and low RR.
11971 * This macro can be used whenever a comparison has to be made between one
11972 * hw state and multiple sw state variables.
11973 */
11974 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11975 if ((current_config->name != pipe_config->name) && \
11976 (current_config->alt_name != pipe_config->name)) { \
11977 DRM_ERROR("mismatch in " #name " " \
11978 "(expected %i or %i, found %i)\n", \
11979 current_config->name, \
11980 current_config->alt_name, \
11981 pipe_config->name); \
11982 return false; \
11983 }
11984
11985 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11986 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11987 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11988 "(expected %i, found %i)\n", \
11989 current_config->name & (mask), \
11990 pipe_config->name & (mask)); \
11991 return false; \
11992 }
11993
11994 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11995 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11996 DRM_ERROR("mismatch in " #name " " \
11997 "(expected %i, found %i)\n", \
11998 current_config->name, \
11999 pipe_config->name); \
12000 return false; \
12001 }
12002
12003 #define PIPE_CONF_QUIRK(quirk) \
12004 ((current_config->quirks | pipe_config->quirks) & (quirk))
12005
12006 PIPE_CONF_CHECK_I(cpu_transcoder);
12007
12008 PIPE_CONF_CHECK_I(has_pch_encoder);
12009 PIPE_CONF_CHECK_I(fdi_lanes);
12010 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12011 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12012 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12013 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12014 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12015
12016 PIPE_CONF_CHECK_I(has_dp_encoder);
12017
12018 if (INTEL_INFO(dev)->gen < 8) {
12019 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12020 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12021 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12022 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12023 PIPE_CONF_CHECK_I(dp_m_n.tu);
12024
12025 if (current_config->has_drrs) {
12026 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12027 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12028 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12029 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12030 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12031 }
12032 } else {
12033 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12034 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12035 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12036 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12037 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12038 }
12039
12040 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12042 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12043 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12044 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12045 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12046
12047 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12048 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12049 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12050 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12051 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12052 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12053
12054 PIPE_CONF_CHECK_I(pixel_multiplier);
12055 PIPE_CONF_CHECK_I(has_hdmi_sink);
12056 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12057 IS_VALLEYVIEW(dev))
12058 PIPE_CONF_CHECK_I(limited_color_range);
12059 PIPE_CONF_CHECK_I(has_infoframe);
12060
12061 PIPE_CONF_CHECK_I(has_audio);
12062
12063 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12064 DRM_MODE_FLAG_INTERLACE);
12065
12066 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12067 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12068 DRM_MODE_FLAG_PHSYNC);
12069 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12070 DRM_MODE_FLAG_NHSYNC);
12071 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12072 DRM_MODE_FLAG_PVSYNC);
12073 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12074 DRM_MODE_FLAG_NVSYNC);
12075 }
12076
12077 PIPE_CONF_CHECK_I(pipe_src_w);
12078 PIPE_CONF_CHECK_I(pipe_src_h);
12079
12080 /*
12081 * FIXME: BIOS likes to set up a cloned config with lvds+external
12082 * screen. Since we don't yet re-compute the pipe config when moving
12083 * just the lvds port away to another pipe the sw tracking won't match.
12084 *
12085 * Proper atomic modesets with recomputed global state will fix this.
12086 * Until then just don't check gmch state for inherited modes.
12087 */
12088 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12089 PIPE_CONF_CHECK_I(gmch_pfit.control);
12090 /* pfit ratios are autocomputed by the hw on gen4+ */
12091 if (INTEL_INFO(dev)->gen < 4)
12092 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12093 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12094 }
12095
12096 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12097 if (current_config->pch_pfit.enabled) {
12098 PIPE_CONF_CHECK_I(pch_pfit.pos);
12099 PIPE_CONF_CHECK_I(pch_pfit.size);
12100 }
12101
12102 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12103
12104 /* BDW+ don't expose a synchronous way to read the state */
12105 if (IS_HASWELL(dev))
12106 PIPE_CONF_CHECK_I(ips_enabled);
12107
12108 PIPE_CONF_CHECK_I(double_wide);
12109
12110 PIPE_CONF_CHECK_X(ddi_pll_sel);
12111
12112 PIPE_CONF_CHECK_I(shared_dpll);
12113 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12114 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12115 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12116 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12117 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12118 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12119 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12120 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12121
12122 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12123 PIPE_CONF_CHECK_I(pipe_bpp);
12124
12125 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12126 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12127
12128 #undef PIPE_CONF_CHECK_X
12129 #undef PIPE_CONF_CHECK_I
12130 #undef PIPE_CONF_CHECK_I_ALT
12131 #undef PIPE_CONF_CHECK_FLAGS
12132 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12133 #undef PIPE_CONF_QUIRK
12134
12135 return true;
12136 }
12137
12138 static void check_wm_state(struct drm_device *dev)
12139 {
12140 struct drm_i915_private *dev_priv = dev->dev_private;
12141 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12142 struct intel_crtc *intel_crtc;
12143 int plane;
12144
12145 if (INTEL_INFO(dev)->gen < 9)
12146 return;
12147
12148 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12149 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12150
12151 for_each_intel_crtc(dev, intel_crtc) {
12152 struct skl_ddb_entry *hw_entry, *sw_entry;
12153 const enum pipe pipe = intel_crtc->pipe;
12154
12155 if (!intel_crtc->active)
12156 continue;
12157
12158 /* planes */
12159 for_each_plane(dev_priv, pipe, plane) {
12160 hw_entry = &hw_ddb.plane[pipe][plane];
12161 sw_entry = &sw_ddb->plane[pipe][plane];
12162
12163 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12164 continue;
12165
12166 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12167 "(expected (%u,%u), found (%u,%u))\n",
12168 pipe_name(pipe), plane + 1,
12169 sw_entry->start, sw_entry->end,
12170 hw_entry->start, hw_entry->end);
12171 }
12172
12173 /* cursor */
12174 hw_entry = &hw_ddb.cursor[pipe];
12175 sw_entry = &sw_ddb->cursor[pipe];
12176
12177 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12178 continue;
12179
12180 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12181 "(expected (%u,%u), found (%u,%u))\n",
12182 pipe_name(pipe),
12183 sw_entry->start, sw_entry->end,
12184 hw_entry->start, hw_entry->end);
12185 }
12186 }
12187
12188 static void
12189 check_connector_state(struct drm_device *dev)
12190 {
12191 struct intel_connector *connector;
12192
12193 for_each_intel_connector(dev, connector) {
12194 /* This also checks the encoder/connector hw state with the
12195 * ->get_hw_state callbacks. */
12196 intel_connector_check_state(connector);
12197
12198 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12199 "connector's staged encoder doesn't match current encoder\n");
12200 }
12201 }
12202
12203 static void
12204 check_encoder_state(struct drm_device *dev)
12205 {
12206 struct intel_encoder *encoder;
12207 struct intel_connector *connector;
12208
12209 for_each_intel_encoder(dev, encoder) {
12210 bool enabled = false;
12211 bool active = false;
12212 enum pipe pipe, tracked_pipe;
12213
12214 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12215 encoder->base.base.id,
12216 encoder->base.name);
12217
12218 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12219 "encoder's stage crtc doesn't match current crtc\n");
12220 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12221 "encoder's active_connectors set, but no crtc\n");
12222
12223 for_each_intel_connector(dev, connector) {
12224 if (connector->base.encoder != &encoder->base)
12225 continue;
12226 enabled = true;
12227 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12228 active = true;
12229 }
12230 /*
12231 * for MST connectors if we unplug the connector is gone
12232 * away but the encoder is still connected to a crtc
12233 * until a modeset happens in response to the hotplug.
12234 */
12235 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12236 continue;
12237
12238 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12239 "encoder's enabled state mismatch "
12240 "(expected %i, found %i)\n",
12241 !!encoder->base.crtc, enabled);
12242 I915_STATE_WARN(active && !encoder->base.crtc,
12243 "active encoder with no crtc\n");
12244
12245 I915_STATE_WARN(encoder->connectors_active != active,
12246 "encoder's computed active state doesn't match tracked active state "
12247 "(expected %i, found %i)\n", active, encoder->connectors_active);
12248
12249 active = encoder->get_hw_state(encoder, &pipe);
12250 I915_STATE_WARN(active != encoder->connectors_active,
12251 "encoder's hw state doesn't match sw tracking "
12252 "(expected %i, found %i)\n",
12253 encoder->connectors_active, active);
12254
12255 if (!encoder->base.crtc)
12256 continue;
12257
12258 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12259 I915_STATE_WARN(active && pipe != tracked_pipe,
12260 "active encoder's pipe doesn't match"
12261 "(expected %i, found %i)\n",
12262 tracked_pipe, pipe);
12263
12264 }
12265 }
12266
12267 static void
12268 check_crtc_state(struct drm_device *dev)
12269 {
12270 struct drm_i915_private *dev_priv = dev->dev_private;
12271 struct intel_crtc *crtc;
12272 struct intel_encoder *encoder;
12273 struct intel_crtc_state pipe_config;
12274
12275 for_each_intel_crtc(dev, crtc) {
12276 bool enabled = false;
12277 bool active = false;
12278
12279 memset(&pipe_config, 0, sizeof(pipe_config));
12280
12281 DRM_DEBUG_KMS("[CRTC:%d]\n",
12282 crtc->base.base.id);
12283
12284 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12285 "active crtc, but not enabled in sw tracking\n");
12286
12287 for_each_intel_encoder(dev, encoder) {
12288 if (encoder->base.crtc != &crtc->base)
12289 continue;
12290 enabled = true;
12291 if (encoder->connectors_active)
12292 active = true;
12293 }
12294
12295 I915_STATE_WARN(active != crtc->active,
12296 "crtc's computed active state doesn't match tracked active state "
12297 "(expected %i, found %i)\n", active, crtc->active);
12298 I915_STATE_WARN(enabled != crtc->base.state->enable,
12299 "crtc's computed enabled state doesn't match tracked enabled state "
12300 "(expected %i, found %i)\n", enabled,
12301 crtc->base.state->enable);
12302
12303 active = dev_priv->display.get_pipe_config(crtc,
12304 &pipe_config);
12305
12306 /* hw state is inconsistent with the pipe quirk */
12307 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12308 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12309 active = crtc->active;
12310
12311 for_each_intel_encoder(dev, encoder) {
12312 enum pipe pipe;
12313 if (encoder->base.crtc != &crtc->base)
12314 continue;
12315 if (encoder->get_hw_state(encoder, &pipe))
12316 encoder->get_config(encoder, &pipe_config);
12317 }
12318
12319 I915_STATE_WARN(crtc->active != active,
12320 "crtc active state doesn't match with hw state "
12321 "(expected %i, found %i)\n", crtc->active, active);
12322
12323 if (active &&
12324 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12325 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12326 intel_dump_pipe_config(crtc, &pipe_config,
12327 "[hw state]");
12328 intel_dump_pipe_config(crtc, crtc->config,
12329 "[sw state]");
12330 }
12331 }
12332 }
12333
12334 static void
12335 check_shared_dpll_state(struct drm_device *dev)
12336 {
12337 struct drm_i915_private *dev_priv = dev->dev_private;
12338 struct intel_crtc *crtc;
12339 struct intel_dpll_hw_state dpll_hw_state;
12340 int i;
12341
12342 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12343 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12344 int enabled_crtcs = 0, active_crtcs = 0;
12345 bool active;
12346
12347 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12348
12349 DRM_DEBUG_KMS("%s\n", pll->name);
12350
12351 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12352
12353 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12354 "more active pll users than references: %i vs %i\n",
12355 pll->active, hweight32(pll->config.crtc_mask));
12356 I915_STATE_WARN(pll->active && !pll->on,
12357 "pll in active use but not on in sw tracking\n");
12358 I915_STATE_WARN(pll->on && !pll->active,
12359 "pll in on but not on in use in sw tracking\n");
12360 I915_STATE_WARN(pll->on != active,
12361 "pll on state mismatch (expected %i, found %i)\n",
12362 pll->on, active);
12363
12364 for_each_intel_crtc(dev, crtc) {
12365 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12366 enabled_crtcs++;
12367 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12368 active_crtcs++;
12369 }
12370 I915_STATE_WARN(pll->active != active_crtcs,
12371 "pll active crtcs mismatch (expected %i, found %i)\n",
12372 pll->active, active_crtcs);
12373 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12374 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12375 hweight32(pll->config.crtc_mask), enabled_crtcs);
12376
12377 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12378 sizeof(dpll_hw_state)),
12379 "pll hw state mismatch\n");
12380 }
12381 }
12382
12383 void
12384 intel_modeset_check_state(struct drm_device *dev)
12385 {
12386 check_wm_state(dev);
12387 check_connector_state(dev);
12388 check_encoder_state(dev);
12389 check_crtc_state(dev);
12390 check_shared_dpll_state(dev);
12391 }
12392
12393 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12394 int dotclock)
12395 {
12396 /*
12397 * FDI already provided one idea for the dotclock.
12398 * Yell if the encoder disagrees.
12399 */
12400 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12401 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12402 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12403 }
12404
12405 static void update_scanline_offset(struct intel_crtc *crtc)
12406 {
12407 struct drm_device *dev = crtc->base.dev;
12408
12409 /*
12410 * The scanline counter increments at the leading edge of hsync.
12411 *
12412 * On most platforms it starts counting from vtotal-1 on the
12413 * first active line. That means the scanline counter value is
12414 * always one less than what we would expect. Ie. just after
12415 * start of vblank, which also occurs at start of hsync (on the
12416 * last active line), the scanline counter will read vblank_start-1.
12417 *
12418 * On gen2 the scanline counter starts counting from 1 instead
12419 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12420 * to keep the value positive), instead of adding one.
12421 *
12422 * On HSW+ the behaviour of the scanline counter depends on the output
12423 * type. For DP ports it behaves like most other platforms, but on HDMI
12424 * there's an extra 1 line difference. So we need to add two instead of
12425 * one to the value.
12426 */
12427 if (IS_GEN2(dev)) {
12428 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12429 int vtotal;
12430
12431 vtotal = mode->crtc_vtotal;
12432 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12433 vtotal /= 2;
12434
12435 crtc->scanline_offset = vtotal - 1;
12436 } else if (HAS_DDI(dev) &&
12437 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12438 crtc->scanline_offset = 2;
12439 } else
12440 crtc->scanline_offset = 1;
12441 }
12442
12443 static struct intel_crtc_state *
12444 intel_modeset_compute_config(struct drm_crtc *crtc,
12445 struct drm_atomic_state *state)
12446 {
12447 struct intel_crtc_state *pipe_config;
12448 int ret = 0;
12449
12450 ret = drm_atomic_add_affected_connectors(state, crtc);
12451 if (ret)
12452 return ERR_PTR(ret);
12453
12454 ret = drm_atomic_helper_check_modeset(state->dev, state);
12455 if (ret)
12456 return ERR_PTR(ret);
12457
12458 /*
12459 * Note this needs changes when we start tracking multiple modes
12460 * and crtcs. At that point we'll need to compute the whole config
12461 * (i.e. one pipe_config for each crtc) rather than just the one
12462 * for this crtc.
12463 */
12464 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12465 if (IS_ERR(pipe_config))
12466 return pipe_config;
12467
12468 if (!pipe_config->base.enable)
12469 return pipe_config;
12470
12471 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12472 if (ret)
12473 return ERR_PTR(ret);
12474
12475 /* Check things that can only be changed through modeset */
12476 if (pipe_config->has_audio !=
12477 to_intel_crtc(crtc)->config->has_audio)
12478 pipe_config->base.mode_changed = true;
12479
12480 /*
12481 * Note we have an issue here with infoframes: current code
12482 * only updates them on the full mode set path per hw
12483 * requirements. So here we should be checking for any
12484 * required changes and forcing a mode set.
12485 */
12486
12487 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12488
12489 ret = drm_atomic_helper_check_planes(state->dev, state);
12490 if (ret)
12491 return ERR_PTR(ret);
12492
12493 return pipe_config;
12494 }
12495
12496 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12497 {
12498 struct drm_device *dev = state->dev;
12499 struct drm_i915_private *dev_priv = to_i915(dev);
12500 unsigned clear_pipes = 0;
12501 struct intel_crtc *intel_crtc;
12502 struct intel_crtc_state *intel_crtc_state;
12503 struct drm_crtc *crtc;
12504 struct drm_crtc_state *crtc_state;
12505 int ret = 0;
12506 int i;
12507
12508 if (!dev_priv->display.crtc_compute_clock)
12509 return 0;
12510
12511 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12512 intel_crtc = to_intel_crtc(crtc);
12513 intel_crtc_state = to_intel_crtc_state(crtc_state);
12514
12515 if (needs_modeset(crtc_state)) {
12516 clear_pipes |= 1 << intel_crtc->pipe;
12517 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12518 }
12519 }
12520
12521 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12522 if (ret)
12523 goto done;
12524
12525 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12526 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12527 continue;
12528
12529 intel_crtc = to_intel_crtc(crtc);
12530 intel_crtc_state = to_intel_crtc_state(crtc_state);
12531
12532 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12533 intel_crtc_state);
12534 if (ret) {
12535 intel_shared_dpll_abort_config(dev_priv);
12536 goto done;
12537 }
12538 }
12539
12540 done:
12541 return ret;
12542 }
12543
12544 /* Code that should eventually be part of atomic_check() */
12545 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12546 {
12547 struct drm_device *dev = state->dev;
12548 int ret;
12549
12550 /*
12551 * See if the config requires any additional preparation, e.g.
12552 * to adjust global state with pipes off. We need to do this
12553 * here so we can get the modeset_pipe updated config for the new
12554 * mode set on this crtc. For other crtcs we need to use the
12555 * adjusted_mode bits in the crtc directly.
12556 */
12557 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12558 ret = valleyview_modeset_global_pipes(state);
12559 if (ret)
12560 return ret;
12561 }
12562
12563 ret = __intel_set_mode_setup_plls(state);
12564 if (ret)
12565 return ret;
12566
12567 return 0;
12568 }
12569
12570 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12571 struct intel_crtc_state *pipe_config)
12572 {
12573 struct drm_device *dev = modeset_crtc->dev;
12574 struct drm_i915_private *dev_priv = dev->dev_private;
12575 struct drm_atomic_state *state = pipe_config->base.state;
12576 struct drm_crtc *crtc;
12577 struct drm_crtc_state *crtc_state;
12578 int ret = 0;
12579 int i;
12580
12581 ret = __intel_set_mode_checks(state);
12582 if (ret < 0)
12583 return ret;
12584
12585 ret = drm_atomic_helper_prepare_planes(dev, state);
12586 if (ret)
12587 return ret;
12588
12589 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12590 if (!needs_modeset(crtc_state))
12591 continue;
12592
12593 if (!crtc_state->enable) {
12594 intel_crtc_disable(crtc);
12595 } else if (crtc->state->enable) {
12596 intel_crtc_disable_planes(crtc);
12597 dev_priv->display.crtc_disable(crtc);
12598 }
12599 }
12600
12601 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12602 * to set it here already despite that we pass it down the callchain.
12603 *
12604 * Note we'll need to fix this up when we start tracking multiple
12605 * pipes; here we assume a single modeset_pipe and only track the
12606 * single crtc and mode.
12607 */
12608 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12609 modeset_crtc->mode = pipe_config->base.mode;
12610
12611 /*
12612 * Calculate and store various constants which
12613 * are later needed by vblank and swap-completion
12614 * timestamping. They are derived from true hwmode.
12615 */
12616 drm_calc_timestamping_constants(modeset_crtc,
12617 &pipe_config->base.adjusted_mode);
12618 }
12619
12620 /* Only after disabling all output pipelines that will be changed can we
12621 * update the the output configuration. */
12622 intel_modeset_update_state(state);
12623
12624 /* The state has been swaped above, so state actually contains the
12625 * old state now. */
12626
12627 modeset_update_crtc_power_domains(state);
12628
12629 drm_atomic_helper_commit_planes(dev, state);
12630
12631 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12632 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12633 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12634 continue;
12635
12636 update_scanline_offset(to_intel_crtc(crtc));
12637
12638 dev_priv->display.crtc_enable(crtc);
12639 intel_crtc_enable_planes(crtc);
12640 }
12641
12642 /* FIXME: add subpixel order */
12643
12644 drm_atomic_helper_cleanup_planes(dev, state);
12645
12646 drm_atomic_state_free(state);
12647
12648 return 0;
12649 }
12650
12651 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12652 struct intel_crtc_state *pipe_config)
12653 {
12654 int ret;
12655
12656 ret = __intel_set_mode(crtc, pipe_config);
12657
12658 if (ret == 0)
12659 intel_modeset_check_state(crtc->dev);
12660
12661 return ret;
12662 }
12663
12664 static int intel_set_mode(struct drm_crtc *crtc,
12665 struct drm_atomic_state *state)
12666 {
12667 struct intel_crtc_state *pipe_config;
12668 int ret = 0;
12669
12670 pipe_config = intel_modeset_compute_config(crtc, state);
12671 if (IS_ERR(pipe_config)) {
12672 ret = PTR_ERR(pipe_config);
12673 goto out;
12674 }
12675
12676 ret = intel_set_mode_with_config(crtc, pipe_config);
12677 if (ret)
12678 goto out;
12679
12680 out:
12681 return ret;
12682 }
12683
12684 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12685 {
12686 struct drm_device *dev = crtc->dev;
12687 struct drm_atomic_state *state;
12688 struct intel_crtc *intel_crtc;
12689 struct intel_encoder *encoder;
12690 struct intel_connector *connector;
12691 struct drm_connector_state *connector_state;
12692 struct intel_crtc_state *crtc_state;
12693 int ret;
12694
12695 state = drm_atomic_state_alloc(dev);
12696 if (!state) {
12697 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12698 crtc->base.id);
12699 return;
12700 }
12701
12702 state->acquire_ctx = dev->mode_config.acquire_ctx;
12703
12704 /* The force restore path in the HW readout code relies on the staged
12705 * config still keeping the user requested config while the actual
12706 * state has been overwritten by the configuration read from HW. We
12707 * need to copy the staged config to the atomic state, otherwise the
12708 * mode set will just reapply the state the HW is already in. */
12709 for_each_intel_encoder(dev, encoder) {
12710 if (&encoder->new_crtc->base != crtc)
12711 continue;
12712
12713 for_each_intel_connector(dev, connector) {
12714 if (connector->new_encoder != encoder)
12715 continue;
12716
12717 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12718 if (IS_ERR(connector_state)) {
12719 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12720 connector->base.base.id,
12721 connector->base.name,
12722 PTR_ERR(connector_state));
12723 continue;
12724 }
12725
12726 connector_state->crtc = crtc;
12727 connector_state->best_encoder = &encoder->base;
12728 }
12729 }
12730
12731 for_each_intel_crtc(dev, intel_crtc) {
12732 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12733 continue;
12734
12735 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12736 if (IS_ERR(crtc_state)) {
12737 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12738 intel_crtc->base.base.id,
12739 PTR_ERR(crtc_state));
12740 continue;
12741 }
12742
12743 crtc_state->base.active = crtc_state->base.enable =
12744 intel_crtc->new_enabled;
12745
12746 if (&intel_crtc->base == crtc)
12747 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12748 }
12749
12750 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12751 crtc->primary->fb, crtc->x, crtc->y);
12752
12753 ret = intel_set_mode(crtc, state);
12754 if (ret)
12755 drm_atomic_state_free(state);
12756 }
12757
12758 #undef for_each_intel_crtc_masked
12759
12760 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12761 struct drm_mode_set *set)
12762 {
12763 int ro;
12764
12765 for (ro = 0; ro < set->num_connectors; ro++)
12766 if (set->connectors[ro] == &connector->base)
12767 return true;
12768
12769 return false;
12770 }
12771
12772 static int
12773 intel_modeset_stage_output_state(struct drm_device *dev,
12774 struct drm_mode_set *set,
12775 struct drm_atomic_state *state)
12776 {
12777 struct intel_connector *connector;
12778 struct drm_connector *drm_connector;
12779 struct drm_connector_state *connector_state;
12780 struct drm_crtc *crtc;
12781 struct drm_crtc_state *crtc_state;
12782 int i, ret;
12783
12784 /* The upper layers ensure that we either disable a crtc or have a list
12785 * of connectors. For paranoia, double-check this. */
12786 WARN_ON(!set->fb && (set->num_connectors != 0));
12787 WARN_ON(set->fb && (set->num_connectors == 0));
12788
12789 for_each_intel_connector(dev, connector) {
12790 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12791
12792 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12793 continue;
12794
12795 connector_state =
12796 drm_atomic_get_connector_state(state, &connector->base);
12797 if (IS_ERR(connector_state))
12798 return PTR_ERR(connector_state);
12799
12800 if (in_mode_set) {
12801 int pipe = to_intel_crtc(set->crtc)->pipe;
12802 connector_state->best_encoder =
12803 &intel_find_encoder(connector, pipe)->base;
12804 }
12805
12806 if (connector->base.state->crtc != set->crtc)
12807 continue;
12808
12809 /* If we disable the crtc, disable all its connectors. Also, if
12810 * the connector is on the changing crtc but not on the new
12811 * connector list, disable it. */
12812 if (!set->fb || !in_mode_set) {
12813 connector_state->best_encoder = NULL;
12814
12815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12816 connector->base.base.id,
12817 connector->base.name);
12818 }
12819 }
12820 /* connector->new_encoder is now updated for all connectors. */
12821
12822 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12823 connector = to_intel_connector(drm_connector);
12824
12825 if (!connector_state->best_encoder) {
12826 ret = drm_atomic_set_crtc_for_connector(connector_state,
12827 NULL);
12828 if (ret)
12829 return ret;
12830
12831 continue;
12832 }
12833
12834 if (intel_connector_in_mode_set(connector, set)) {
12835 struct drm_crtc *crtc = connector->base.state->crtc;
12836
12837 /* If this connector was in a previous crtc, add it
12838 * to the state. We might need to disable it. */
12839 if (crtc) {
12840 crtc_state =
12841 drm_atomic_get_crtc_state(state, crtc);
12842 if (IS_ERR(crtc_state))
12843 return PTR_ERR(crtc_state);
12844 }
12845
12846 ret = drm_atomic_set_crtc_for_connector(connector_state,
12847 set->crtc);
12848 if (ret)
12849 return ret;
12850 }
12851
12852 /* Make sure the new CRTC will work with the encoder */
12853 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12854 connector_state->crtc)) {
12855 return -EINVAL;
12856 }
12857
12858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12859 connector->base.base.id,
12860 connector->base.name,
12861 connector_state->crtc->base.id);
12862
12863 if (connector_state->best_encoder != &connector->encoder->base)
12864 connector->encoder =
12865 to_intel_encoder(connector_state->best_encoder);
12866 }
12867
12868 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12869 bool has_connectors;
12870
12871 ret = drm_atomic_add_affected_connectors(state, crtc);
12872 if (ret)
12873 return ret;
12874
12875 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12876 if (has_connectors != crtc_state->enable)
12877 crtc_state->enable =
12878 crtc_state->active = has_connectors;
12879 }
12880
12881 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12882 set->fb, set->x, set->y);
12883 if (ret)
12884 return ret;
12885
12886 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12887 if (IS_ERR(crtc_state))
12888 return PTR_ERR(crtc_state);
12889
12890 if (set->mode)
12891 drm_mode_copy(&crtc_state->mode, set->mode);
12892
12893 if (set->num_connectors)
12894 crtc_state->active = true;
12895
12896 return 0;
12897 }
12898
12899 static bool primary_plane_visible(struct drm_crtc *crtc)
12900 {
12901 struct intel_plane_state *plane_state =
12902 to_intel_plane_state(crtc->primary->state);
12903
12904 return plane_state->visible;
12905 }
12906
12907 static int intel_crtc_set_config(struct drm_mode_set *set)
12908 {
12909 struct drm_device *dev;
12910 struct drm_atomic_state *state = NULL;
12911 struct intel_crtc_state *pipe_config;
12912 bool primary_plane_was_visible;
12913 int ret;
12914
12915 BUG_ON(!set);
12916 BUG_ON(!set->crtc);
12917 BUG_ON(!set->crtc->helper_private);
12918
12919 /* Enforce sane interface api - has been abused by the fb helper. */
12920 BUG_ON(!set->mode && set->fb);
12921 BUG_ON(set->fb && set->num_connectors == 0);
12922
12923 if (set->fb) {
12924 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12925 set->crtc->base.id, set->fb->base.id,
12926 (int)set->num_connectors, set->x, set->y);
12927 } else {
12928 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12929 }
12930
12931 dev = set->crtc->dev;
12932
12933 state = drm_atomic_state_alloc(dev);
12934 if (!state)
12935 return -ENOMEM;
12936
12937 state->acquire_ctx = dev->mode_config.acquire_ctx;
12938
12939 ret = intel_modeset_stage_output_state(dev, set, state);
12940 if (ret)
12941 goto out;
12942
12943 pipe_config = intel_modeset_compute_config(set->crtc, state);
12944 if (IS_ERR(pipe_config)) {
12945 ret = PTR_ERR(pipe_config);
12946 goto out;
12947 }
12948
12949 intel_update_pipe_size(to_intel_crtc(set->crtc));
12950
12951 primary_plane_was_visible = primary_plane_visible(set->crtc);
12952
12953 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12954
12955 if (ret == 0 &&
12956 pipe_config->base.enable &&
12957 pipe_config->base.planes_changed &&
12958 !needs_modeset(&pipe_config->base)) {
12959 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12960
12961 /*
12962 * We need to make sure the primary plane is re-enabled if it
12963 * has previously been turned off.
12964 */
12965 if (ret == 0 && !primary_plane_was_visible &&
12966 primary_plane_visible(set->crtc)) {
12967 WARN_ON(!intel_crtc->active);
12968 intel_post_enable_primary(set->crtc);
12969 }
12970
12971 /*
12972 * In the fastboot case this may be our only check of the
12973 * state after boot. It would be better to only do it on
12974 * the first update, but we don't have a nice way of doing that
12975 * (and really, set_config isn't used much for high freq page
12976 * flipping, so increasing its cost here shouldn't be a big
12977 * deal).
12978 */
12979 if (i915.fastboot && ret == 0)
12980 intel_modeset_check_state(set->crtc->dev);
12981 }
12982
12983 if (ret) {
12984 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12985 set->crtc->base.id, ret);
12986 }
12987
12988 out:
12989 if (ret)
12990 drm_atomic_state_free(state);
12991 return ret;
12992 }
12993
12994 static const struct drm_crtc_funcs intel_crtc_funcs = {
12995 .gamma_set = intel_crtc_gamma_set,
12996 .set_config = intel_crtc_set_config,
12997 .destroy = intel_crtc_destroy,
12998 .page_flip = intel_crtc_page_flip,
12999 .atomic_duplicate_state = intel_crtc_duplicate_state,
13000 .atomic_destroy_state = intel_crtc_destroy_state,
13001 };
13002
13003 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13004 struct intel_shared_dpll *pll,
13005 struct intel_dpll_hw_state *hw_state)
13006 {
13007 uint32_t val;
13008
13009 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13010 return false;
13011
13012 val = I915_READ(PCH_DPLL(pll->id));
13013 hw_state->dpll = val;
13014 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13015 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13016
13017 return val & DPLL_VCO_ENABLE;
13018 }
13019
13020 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13021 struct intel_shared_dpll *pll)
13022 {
13023 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13024 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13025 }
13026
13027 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13028 struct intel_shared_dpll *pll)
13029 {
13030 /* PCH refclock must be enabled first */
13031 ibx_assert_pch_refclk_enabled(dev_priv);
13032
13033 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13034
13035 /* Wait for the clocks to stabilize. */
13036 POSTING_READ(PCH_DPLL(pll->id));
13037 udelay(150);
13038
13039 /* The pixel multiplier can only be updated once the
13040 * DPLL is enabled and the clocks are stable.
13041 *
13042 * So write it again.
13043 */
13044 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13045 POSTING_READ(PCH_DPLL(pll->id));
13046 udelay(200);
13047 }
13048
13049 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13050 struct intel_shared_dpll *pll)
13051 {
13052 struct drm_device *dev = dev_priv->dev;
13053 struct intel_crtc *crtc;
13054
13055 /* Make sure no transcoder isn't still depending on us. */
13056 for_each_intel_crtc(dev, crtc) {
13057 if (intel_crtc_to_shared_dpll(crtc) == pll)
13058 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13059 }
13060
13061 I915_WRITE(PCH_DPLL(pll->id), 0);
13062 POSTING_READ(PCH_DPLL(pll->id));
13063 udelay(200);
13064 }
13065
13066 static char *ibx_pch_dpll_names[] = {
13067 "PCH DPLL A",
13068 "PCH DPLL B",
13069 };
13070
13071 static void ibx_pch_dpll_init(struct drm_device *dev)
13072 {
13073 struct drm_i915_private *dev_priv = dev->dev_private;
13074 int i;
13075
13076 dev_priv->num_shared_dpll = 2;
13077
13078 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13079 dev_priv->shared_dplls[i].id = i;
13080 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13081 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13082 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13083 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13084 dev_priv->shared_dplls[i].get_hw_state =
13085 ibx_pch_dpll_get_hw_state;
13086 }
13087 }
13088
13089 static void intel_shared_dpll_init(struct drm_device *dev)
13090 {
13091 struct drm_i915_private *dev_priv = dev->dev_private;
13092
13093 if (HAS_DDI(dev))
13094 intel_ddi_pll_init(dev);
13095 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13096 ibx_pch_dpll_init(dev);
13097 else
13098 dev_priv->num_shared_dpll = 0;
13099
13100 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13101 }
13102
13103 /**
13104 * intel_wm_need_update - Check whether watermarks need updating
13105 * @plane: drm plane
13106 * @state: new plane state
13107 *
13108 * Check current plane state versus the new one to determine whether
13109 * watermarks need to be recalculated.
13110 *
13111 * Returns true or false.
13112 */
13113 bool intel_wm_need_update(struct drm_plane *plane,
13114 struct drm_plane_state *state)
13115 {
13116 /* Update watermarks on tiling changes. */
13117 if (!plane->state->fb || !state->fb ||
13118 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13119 plane->state->rotation != state->rotation)
13120 return true;
13121
13122 return false;
13123 }
13124
13125 /**
13126 * intel_prepare_plane_fb - Prepare fb for usage on plane
13127 * @plane: drm plane to prepare for
13128 * @fb: framebuffer to prepare for presentation
13129 *
13130 * Prepares a framebuffer for usage on a display plane. Generally this
13131 * involves pinning the underlying object and updating the frontbuffer tracking
13132 * bits. Some older platforms need special physical address handling for
13133 * cursor planes.
13134 *
13135 * Returns 0 on success, negative error code on failure.
13136 */
13137 int
13138 intel_prepare_plane_fb(struct drm_plane *plane,
13139 struct drm_framebuffer *fb,
13140 const struct drm_plane_state *new_state)
13141 {
13142 struct drm_device *dev = plane->dev;
13143 struct intel_plane *intel_plane = to_intel_plane(plane);
13144 enum pipe pipe = intel_plane->pipe;
13145 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13146 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13147 unsigned frontbuffer_bits = 0;
13148 int ret = 0;
13149
13150 if (!obj)
13151 return 0;
13152
13153 switch (plane->type) {
13154 case DRM_PLANE_TYPE_PRIMARY:
13155 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13156 break;
13157 case DRM_PLANE_TYPE_CURSOR:
13158 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13159 break;
13160 case DRM_PLANE_TYPE_OVERLAY:
13161 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13162 break;
13163 }
13164
13165 mutex_lock(&dev->struct_mutex);
13166
13167 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13168 INTEL_INFO(dev)->cursor_needs_physical) {
13169 int align = IS_I830(dev) ? 16 * 1024 : 256;
13170 ret = i915_gem_object_attach_phys(obj, align);
13171 if (ret)
13172 DRM_DEBUG_KMS("failed to attach phys object\n");
13173 } else {
13174 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13175 }
13176
13177 if (ret == 0)
13178 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13179
13180 mutex_unlock(&dev->struct_mutex);
13181
13182 return ret;
13183 }
13184
13185 /**
13186 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13187 * @plane: drm plane to clean up for
13188 * @fb: old framebuffer that was on plane
13189 *
13190 * Cleans up a framebuffer that has just been removed from a plane.
13191 */
13192 void
13193 intel_cleanup_plane_fb(struct drm_plane *plane,
13194 struct drm_framebuffer *fb,
13195 const struct drm_plane_state *old_state)
13196 {
13197 struct drm_device *dev = plane->dev;
13198 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13199
13200 if (WARN_ON(!obj))
13201 return;
13202
13203 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13204 !INTEL_INFO(dev)->cursor_needs_physical) {
13205 mutex_lock(&dev->struct_mutex);
13206 intel_unpin_fb_obj(fb, old_state);
13207 mutex_unlock(&dev->struct_mutex);
13208 }
13209 }
13210
13211 int
13212 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13213 {
13214 int max_scale;
13215 struct drm_device *dev;
13216 struct drm_i915_private *dev_priv;
13217 int crtc_clock, cdclk;
13218
13219 if (!intel_crtc || !crtc_state)
13220 return DRM_PLANE_HELPER_NO_SCALING;
13221
13222 dev = intel_crtc->base.dev;
13223 dev_priv = dev->dev_private;
13224 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13225 cdclk = dev_priv->display.get_display_clock_speed(dev);
13226
13227 if (!crtc_clock || !cdclk)
13228 return DRM_PLANE_HELPER_NO_SCALING;
13229
13230 /*
13231 * skl max scale is lower of:
13232 * close to 3 but not 3, -1 is for that purpose
13233 * or
13234 * cdclk/crtc_clock
13235 */
13236 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13237
13238 return max_scale;
13239 }
13240
13241 static int
13242 intel_check_primary_plane(struct drm_plane *plane,
13243 struct intel_plane_state *state)
13244 {
13245 struct drm_device *dev = plane->dev;
13246 struct drm_i915_private *dev_priv = dev->dev_private;
13247 struct drm_crtc *crtc = state->base.crtc;
13248 struct intel_crtc *intel_crtc;
13249 struct intel_crtc_state *crtc_state;
13250 struct drm_framebuffer *fb = state->base.fb;
13251 struct drm_rect *dest = &state->dst;
13252 struct drm_rect *src = &state->src;
13253 const struct drm_rect *clip = &state->clip;
13254 bool can_position = false;
13255 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13256 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13257 int ret;
13258
13259 crtc = crtc ? crtc : plane->crtc;
13260 intel_crtc = to_intel_crtc(crtc);
13261 crtc_state = state->base.state ?
13262 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13263
13264 if (INTEL_INFO(dev)->gen >= 9) {
13265 /* use scaler when colorkey is not required */
13266 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13267 min_scale = 1;
13268 max_scale = skl_max_scale(intel_crtc, crtc_state);
13269 }
13270 can_position = true;
13271 }
13272
13273 ret = drm_plane_helper_check_update(plane, crtc, fb,
13274 src, dest, clip,
13275 min_scale,
13276 max_scale,
13277 can_position, true,
13278 &state->visible);
13279 if (ret)
13280 return ret;
13281
13282 if (intel_crtc->active) {
13283 struct intel_plane_state *old_state =
13284 to_intel_plane_state(plane->state);
13285
13286 intel_crtc->atomic.wait_for_flips = true;
13287
13288 /*
13289 * FBC does not work on some platforms for rotated
13290 * planes, so disable it when rotation is not 0 and
13291 * update it when rotation is set back to 0.
13292 *
13293 * FIXME: This is redundant with the fbc update done in
13294 * the primary plane enable function except that that
13295 * one is done too late. We eventually need to unify
13296 * this.
13297 */
13298 if (state->visible &&
13299 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13300 dev_priv->fbc.crtc == intel_crtc &&
13301 state->base.rotation != BIT(DRM_ROTATE_0)) {
13302 intel_crtc->atomic.disable_fbc = true;
13303 }
13304
13305 if (state->visible && !old_state->visible) {
13306 /*
13307 * BDW signals flip done immediately if the plane
13308 * is disabled, even if the plane enable is already
13309 * armed to occur at the next vblank :(
13310 */
13311 if (IS_BROADWELL(dev))
13312 intel_crtc->atomic.wait_vblank = true;
13313 }
13314
13315 intel_crtc->atomic.fb_bits |=
13316 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13317
13318 intel_crtc->atomic.update_fbc = true;
13319
13320 if (intel_wm_need_update(plane, &state->base))
13321 intel_crtc->atomic.update_wm = true;
13322 }
13323
13324 if (INTEL_INFO(dev)->gen >= 9) {
13325 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13326 to_intel_plane(plane), state, 0);
13327 if (ret)
13328 return ret;
13329 }
13330
13331 return 0;
13332 }
13333
13334 static void
13335 intel_commit_primary_plane(struct drm_plane *plane,
13336 struct intel_plane_state *state)
13337 {
13338 struct drm_crtc *crtc = state->base.crtc;
13339 struct drm_framebuffer *fb = state->base.fb;
13340 struct drm_device *dev = plane->dev;
13341 struct drm_i915_private *dev_priv = dev->dev_private;
13342 struct intel_crtc *intel_crtc;
13343 struct drm_rect *src = &state->src;
13344
13345 crtc = crtc ? crtc : plane->crtc;
13346 intel_crtc = to_intel_crtc(crtc);
13347
13348 plane->fb = fb;
13349 crtc->x = src->x1 >> 16;
13350 crtc->y = src->y1 >> 16;
13351
13352 if (intel_crtc->active) {
13353 if (state->visible)
13354 /* FIXME: kill this fastboot hack */
13355 intel_update_pipe_size(intel_crtc);
13356
13357 dev_priv->display.update_primary_plane(crtc, plane->fb,
13358 crtc->x, crtc->y);
13359 }
13360 }
13361
13362 static void
13363 intel_disable_primary_plane(struct drm_plane *plane,
13364 struct drm_crtc *crtc,
13365 bool force)
13366 {
13367 struct drm_device *dev = plane->dev;
13368 struct drm_i915_private *dev_priv = dev->dev_private;
13369
13370 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13371 }
13372
13373 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13374 {
13375 struct drm_device *dev = crtc->dev;
13376 struct drm_i915_private *dev_priv = dev->dev_private;
13377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13378 struct intel_plane *intel_plane;
13379 struct drm_plane *p;
13380 unsigned fb_bits = 0;
13381
13382 /* Track fb's for any planes being disabled */
13383 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13384 intel_plane = to_intel_plane(p);
13385
13386 if (intel_crtc->atomic.disabled_planes &
13387 (1 << drm_plane_index(p))) {
13388 switch (p->type) {
13389 case DRM_PLANE_TYPE_PRIMARY:
13390 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13391 break;
13392 case DRM_PLANE_TYPE_CURSOR:
13393 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13394 break;
13395 case DRM_PLANE_TYPE_OVERLAY:
13396 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13397 break;
13398 }
13399
13400 mutex_lock(&dev->struct_mutex);
13401 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13402 mutex_unlock(&dev->struct_mutex);
13403 }
13404 }
13405
13406 if (intel_crtc->atomic.wait_for_flips)
13407 intel_crtc_wait_for_pending_flips(crtc);
13408
13409 if (intel_crtc->atomic.disable_fbc)
13410 intel_fbc_disable(dev);
13411
13412 if (intel_crtc->atomic.pre_disable_primary)
13413 intel_pre_disable_primary(crtc);
13414
13415 if (intel_crtc->atomic.update_wm)
13416 intel_update_watermarks(crtc);
13417
13418 intel_runtime_pm_get(dev_priv);
13419
13420 /* Perform vblank evasion around commit operation */
13421 if (intel_crtc->active)
13422 intel_crtc->atomic.evade =
13423 intel_pipe_update_start(intel_crtc,
13424 &intel_crtc->atomic.start_vbl_count);
13425 }
13426
13427 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13428 {
13429 struct drm_device *dev = crtc->dev;
13430 struct drm_i915_private *dev_priv = dev->dev_private;
13431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13432 struct drm_plane *p;
13433
13434 if (intel_crtc->atomic.evade)
13435 intel_pipe_update_end(intel_crtc,
13436 intel_crtc->atomic.start_vbl_count);
13437
13438 intel_runtime_pm_put(dev_priv);
13439
13440 if (intel_crtc->atomic.wait_vblank)
13441 intel_wait_for_vblank(dev, intel_crtc->pipe);
13442
13443 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13444
13445 if (intel_crtc->atomic.update_fbc) {
13446 mutex_lock(&dev->struct_mutex);
13447 intel_fbc_update(dev);
13448 mutex_unlock(&dev->struct_mutex);
13449 }
13450
13451 if (intel_crtc->atomic.post_enable_primary)
13452 intel_post_enable_primary(crtc);
13453
13454 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13455 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13456 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13457 false, false);
13458
13459 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13460 }
13461
13462 /**
13463 * intel_plane_destroy - destroy a plane
13464 * @plane: plane to destroy
13465 *
13466 * Common destruction function for all types of planes (primary, cursor,
13467 * sprite).
13468 */
13469 void intel_plane_destroy(struct drm_plane *plane)
13470 {
13471 struct intel_plane *intel_plane = to_intel_plane(plane);
13472 drm_plane_cleanup(plane);
13473 kfree(intel_plane);
13474 }
13475
13476 const struct drm_plane_funcs intel_plane_funcs = {
13477 .update_plane = drm_atomic_helper_update_plane,
13478 .disable_plane = drm_atomic_helper_disable_plane,
13479 .destroy = intel_plane_destroy,
13480 .set_property = drm_atomic_helper_plane_set_property,
13481 .atomic_get_property = intel_plane_atomic_get_property,
13482 .atomic_set_property = intel_plane_atomic_set_property,
13483 .atomic_duplicate_state = intel_plane_duplicate_state,
13484 .atomic_destroy_state = intel_plane_destroy_state,
13485
13486 };
13487
13488 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13489 int pipe)
13490 {
13491 struct intel_plane *primary;
13492 struct intel_plane_state *state;
13493 const uint32_t *intel_primary_formats;
13494 int num_formats;
13495
13496 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13497 if (primary == NULL)
13498 return NULL;
13499
13500 state = intel_create_plane_state(&primary->base);
13501 if (!state) {
13502 kfree(primary);
13503 return NULL;
13504 }
13505 primary->base.state = &state->base;
13506
13507 primary->can_scale = false;
13508 primary->max_downscale = 1;
13509 if (INTEL_INFO(dev)->gen >= 9) {
13510 primary->can_scale = true;
13511 state->scaler_id = -1;
13512 }
13513 primary->pipe = pipe;
13514 primary->plane = pipe;
13515 primary->check_plane = intel_check_primary_plane;
13516 primary->commit_plane = intel_commit_primary_plane;
13517 primary->disable_plane = intel_disable_primary_plane;
13518 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13519 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13520 primary->plane = !pipe;
13521
13522 if (INTEL_INFO(dev)->gen >= 9) {
13523 intel_primary_formats = skl_primary_formats;
13524 num_formats = ARRAY_SIZE(skl_primary_formats);
13525 } else if (INTEL_INFO(dev)->gen >= 4) {
13526 intel_primary_formats = i965_primary_formats;
13527 num_formats = ARRAY_SIZE(i965_primary_formats);
13528 } else {
13529 intel_primary_formats = i8xx_primary_formats;
13530 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13531 }
13532
13533 drm_universal_plane_init(dev, &primary->base, 0,
13534 &intel_plane_funcs,
13535 intel_primary_formats, num_formats,
13536 DRM_PLANE_TYPE_PRIMARY);
13537
13538 if (INTEL_INFO(dev)->gen >= 4)
13539 intel_create_rotation_property(dev, primary);
13540
13541 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13542
13543 return &primary->base;
13544 }
13545
13546 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13547 {
13548 if (!dev->mode_config.rotation_property) {
13549 unsigned long flags = BIT(DRM_ROTATE_0) |
13550 BIT(DRM_ROTATE_180);
13551
13552 if (INTEL_INFO(dev)->gen >= 9)
13553 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13554
13555 dev->mode_config.rotation_property =
13556 drm_mode_create_rotation_property(dev, flags);
13557 }
13558 if (dev->mode_config.rotation_property)
13559 drm_object_attach_property(&plane->base.base,
13560 dev->mode_config.rotation_property,
13561 plane->base.state->rotation);
13562 }
13563
13564 static int
13565 intel_check_cursor_plane(struct drm_plane *plane,
13566 struct intel_plane_state *state)
13567 {
13568 struct drm_crtc *crtc = state->base.crtc;
13569 struct drm_device *dev = plane->dev;
13570 struct drm_framebuffer *fb = state->base.fb;
13571 struct drm_rect *dest = &state->dst;
13572 struct drm_rect *src = &state->src;
13573 const struct drm_rect *clip = &state->clip;
13574 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13575 struct intel_crtc *intel_crtc;
13576 unsigned stride;
13577 int ret;
13578
13579 crtc = crtc ? crtc : plane->crtc;
13580 intel_crtc = to_intel_crtc(crtc);
13581
13582 ret = drm_plane_helper_check_update(plane, crtc, fb,
13583 src, dest, clip,
13584 DRM_PLANE_HELPER_NO_SCALING,
13585 DRM_PLANE_HELPER_NO_SCALING,
13586 true, true, &state->visible);
13587 if (ret)
13588 return ret;
13589
13590
13591 /* if we want to turn off the cursor ignore width and height */
13592 if (!obj)
13593 goto finish;
13594
13595 /* Check for which cursor types we support */
13596 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13597 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13598 state->base.crtc_w, state->base.crtc_h);
13599 return -EINVAL;
13600 }
13601
13602 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13603 if (obj->base.size < stride * state->base.crtc_h) {
13604 DRM_DEBUG_KMS("buffer is too small\n");
13605 return -ENOMEM;
13606 }
13607
13608 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13609 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13610 ret = -EINVAL;
13611 }
13612
13613 finish:
13614 if (intel_crtc->active) {
13615 if (plane->state->crtc_w != state->base.crtc_w)
13616 intel_crtc->atomic.update_wm = true;
13617
13618 intel_crtc->atomic.fb_bits |=
13619 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13620 }
13621
13622 return ret;
13623 }
13624
13625 static void
13626 intel_disable_cursor_plane(struct drm_plane *plane,
13627 struct drm_crtc *crtc,
13628 bool force)
13629 {
13630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13631
13632 if (!force) {
13633 plane->fb = NULL;
13634 intel_crtc->cursor_bo = NULL;
13635 intel_crtc->cursor_addr = 0;
13636 }
13637
13638 intel_crtc_update_cursor(crtc, false);
13639 }
13640
13641 static void
13642 intel_commit_cursor_plane(struct drm_plane *plane,
13643 struct intel_plane_state *state)
13644 {
13645 struct drm_crtc *crtc = state->base.crtc;
13646 struct drm_device *dev = plane->dev;
13647 struct intel_crtc *intel_crtc;
13648 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13649 uint32_t addr;
13650
13651 crtc = crtc ? crtc : plane->crtc;
13652 intel_crtc = to_intel_crtc(crtc);
13653
13654 plane->fb = state->base.fb;
13655 crtc->cursor_x = state->base.crtc_x;
13656 crtc->cursor_y = state->base.crtc_y;
13657
13658 if (intel_crtc->cursor_bo == obj)
13659 goto update;
13660
13661 if (!obj)
13662 addr = 0;
13663 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13664 addr = i915_gem_obj_ggtt_offset(obj);
13665 else
13666 addr = obj->phys_handle->busaddr;
13667
13668 intel_crtc->cursor_addr = addr;
13669 intel_crtc->cursor_bo = obj;
13670 update:
13671
13672 if (intel_crtc->active)
13673 intel_crtc_update_cursor(crtc, state->visible);
13674 }
13675
13676 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13677 int pipe)
13678 {
13679 struct intel_plane *cursor;
13680 struct intel_plane_state *state;
13681
13682 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13683 if (cursor == NULL)
13684 return NULL;
13685
13686 state = intel_create_plane_state(&cursor->base);
13687 if (!state) {
13688 kfree(cursor);
13689 return NULL;
13690 }
13691 cursor->base.state = &state->base;
13692
13693 cursor->can_scale = false;
13694 cursor->max_downscale = 1;
13695 cursor->pipe = pipe;
13696 cursor->plane = pipe;
13697 cursor->check_plane = intel_check_cursor_plane;
13698 cursor->commit_plane = intel_commit_cursor_plane;
13699 cursor->disable_plane = intel_disable_cursor_plane;
13700
13701 drm_universal_plane_init(dev, &cursor->base, 0,
13702 &intel_plane_funcs,
13703 intel_cursor_formats,
13704 ARRAY_SIZE(intel_cursor_formats),
13705 DRM_PLANE_TYPE_CURSOR);
13706
13707 if (INTEL_INFO(dev)->gen >= 4) {
13708 if (!dev->mode_config.rotation_property)
13709 dev->mode_config.rotation_property =
13710 drm_mode_create_rotation_property(dev,
13711 BIT(DRM_ROTATE_0) |
13712 BIT(DRM_ROTATE_180));
13713 if (dev->mode_config.rotation_property)
13714 drm_object_attach_property(&cursor->base.base,
13715 dev->mode_config.rotation_property,
13716 state->base.rotation);
13717 }
13718
13719 if (INTEL_INFO(dev)->gen >=9)
13720 state->scaler_id = -1;
13721
13722 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13723
13724 return &cursor->base;
13725 }
13726
13727 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13728 struct intel_crtc_state *crtc_state)
13729 {
13730 int i;
13731 struct intel_scaler *intel_scaler;
13732 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13733
13734 for (i = 0; i < intel_crtc->num_scalers; i++) {
13735 intel_scaler = &scaler_state->scalers[i];
13736 intel_scaler->in_use = 0;
13737 intel_scaler->id = i;
13738
13739 intel_scaler->mode = PS_SCALER_MODE_DYN;
13740 }
13741
13742 scaler_state->scaler_id = -1;
13743 }
13744
13745 static void intel_crtc_init(struct drm_device *dev, int pipe)
13746 {
13747 struct drm_i915_private *dev_priv = dev->dev_private;
13748 struct intel_crtc *intel_crtc;
13749 struct intel_crtc_state *crtc_state = NULL;
13750 struct drm_plane *primary = NULL;
13751 struct drm_plane *cursor = NULL;
13752 int i, ret;
13753
13754 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13755 if (intel_crtc == NULL)
13756 return;
13757
13758 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13759 if (!crtc_state)
13760 goto fail;
13761 intel_crtc->config = crtc_state;
13762 intel_crtc->base.state = &crtc_state->base;
13763 crtc_state->base.crtc = &intel_crtc->base;
13764
13765 /* initialize shared scalers */
13766 if (INTEL_INFO(dev)->gen >= 9) {
13767 if (pipe == PIPE_C)
13768 intel_crtc->num_scalers = 1;
13769 else
13770 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13771
13772 skl_init_scalers(dev, intel_crtc, crtc_state);
13773 }
13774
13775 primary = intel_primary_plane_create(dev, pipe);
13776 if (!primary)
13777 goto fail;
13778
13779 cursor = intel_cursor_plane_create(dev, pipe);
13780 if (!cursor)
13781 goto fail;
13782
13783 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13784 cursor, &intel_crtc_funcs);
13785 if (ret)
13786 goto fail;
13787
13788 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13789 for (i = 0; i < 256; i++) {
13790 intel_crtc->lut_r[i] = i;
13791 intel_crtc->lut_g[i] = i;
13792 intel_crtc->lut_b[i] = i;
13793 }
13794
13795 /*
13796 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13797 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13798 */
13799 intel_crtc->pipe = pipe;
13800 intel_crtc->plane = pipe;
13801 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13802 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13803 intel_crtc->plane = !pipe;
13804 }
13805
13806 intel_crtc->cursor_base = ~0;
13807 intel_crtc->cursor_cntl = ~0;
13808 intel_crtc->cursor_size = ~0;
13809
13810 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13811 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13812 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13813 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13814
13815 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13816
13817 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13818 return;
13819
13820 fail:
13821 if (primary)
13822 drm_plane_cleanup(primary);
13823 if (cursor)
13824 drm_plane_cleanup(cursor);
13825 kfree(crtc_state);
13826 kfree(intel_crtc);
13827 }
13828
13829 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13830 {
13831 struct drm_encoder *encoder = connector->base.encoder;
13832 struct drm_device *dev = connector->base.dev;
13833
13834 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13835
13836 if (!encoder || WARN_ON(!encoder->crtc))
13837 return INVALID_PIPE;
13838
13839 return to_intel_crtc(encoder->crtc)->pipe;
13840 }
13841
13842 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13843 struct drm_file *file)
13844 {
13845 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13846 struct drm_crtc *drmmode_crtc;
13847 struct intel_crtc *crtc;
13848
13849 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13850
13851 if (!drmmode_crtc) {
13852 DRM_ERROR("no such CRTC id\n");
13853 return -ENOENT;
13854 }
13855
13856 crtc = to_intel_crtc(drmmode_crtc);
13857 pipe_from_crtc_id->pipe = crtc->pipe;
13858
13859 return 0;
13860 }
13861
13862 static int intel_encoder_clones(struct intel_encoder *encoder)
13863 {
13864 struct drm_device *dev = encoder->base.dev;
13865 struct intel_encoder *source_encoder;
13866 int index_mask = 0;
13867 int entry = 0;
13868
13869 for_each_intel_encoder(dev, source_encoder) {
13870 if (encoders_cloneable(encoder, source_encoder))
13871 index_mask |= (1 << entry);
13872
13873 entry++;
13874 }
13875
13876 return index_mask;
13877 }
13878
13879 static bool has_edp_a(struct drm_device *dev)
13880 {
13881 struct drm_i915_private *dev_priv = dev->dev_private;
13882
13883 if (!IS_MOBILE(dev))
13884 return false;
13885
13886 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13887 return false;
13888
13889 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13890 return false;
13891
13892 return true;
13893 }
13894
13895 static bool intel_crt_present(struct drm_device *dev)
13896 {
13897 struct drm_i915_private *dev_priv = dev->dev_private;
13898
13899 if (INTEL_INFO(dev)->gen >= 9)
13900 return false;
13901
13902 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13903 return false;
13904
13905 if (IS_CHERRYVIEW(dev))
13906 return false;
13907
13908 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13909 return false;
13910
13911 return true;
13912 }
13913
13914 static void intel_setup_outputs(struct drm_device *dev)
13915 {
13916 struct drm_i915_private *dev_priv = dev->dev_private;
13917 struct intel_encoder *encoder;
13918 bool dpd_is_edp = false;
13919
13920 intel_lvds_init(dev);
13921
13922 if (intel_crt_present(dev))
13923 intel_crt_init(dev);
13924
13925 if (IS_BROXTON(dev)) {
13926 /*
13927 * FIXME: Broxton doesn't support port detection via the
13928 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13929 * detect the ports.
13930 */
13931 intel_ddi_init(dev, PORT_A);
13932 intel_ddi_init(dev, PORT_B);
13933 intel_ddi_init(dev, PORT_C);
13934 } else if (HAS_DDI(dev)) {
13935 int found;
13936
13937 /*
13938 * Haswell uses DDI functions to detect digital outputs.
13939 * On SKL pre-D0 the strap isn't connected, so we assume
13940 * it's there.
13941 */
13942 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13943 /* WaIgnoreDDIAStrap: skl */
13944 if (found ||
13945 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13946 intel_ddi_init(dev, PORT_A);
13947
13948 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13949 * register */
13950 found = I915_READ(SFUSE_STRAP);
13951
13952 if (found & SFUSE_STRAP_DDIB_DETECTED)
13953 intel_ddi_init(dev, PORT_B);
13954 if (found & SFUSE_STRAP_DDIC_DETECTED)
13955 intel_ddi_init(dev, PORT_C);
13956 if (found & SFUSE_STRAP_DDID_DETECTED)
13957 intel_ddi_init(dev, PORT_D);
13958 } else if (HAS_PCH_SPLIT(dev)) {
13959 int found;
13960 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13961
13962 if (has_edp_a(dev))
13963 intel_dp_init(dev, DP_A, PORT_A);
13964
13965 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13966 /* PCH SDVOB multiplex with HDMIB */
13967 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13968 if (!found)
13969 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13970 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13971 intel_dp_init(dev, PCH_DP_B, PORT_B);
13972 }
13973
13974 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13975 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13976
13977 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13978 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13979
13980 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13981 intel_dp_init(dev, PCH_DP_C, PORT_C);
13982
13983 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13984 intel_dp_init(dev, PCH_DP_D, PORT_D);
13985 } else if (IS_VALLEYVIEW(dev)) {
13986 /*
13987 * The DP_DETECTED bit is the latched state of the DDC
13988 * SDA pin at boot. However since eDP doesn't require DDC
13989 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13990 * eDP ports may have been muxed to an alternate function.
13991 * Thus we can't rely on the DP_DETECTED bit alone to detect
13992 * eDP ports. Consult the VBT as well as DP_DETECTED to
13993 * detect eDP ports.
13994 */
13995 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13996 !intel_dp_is_edp(dev, PORT_B))
13997 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13998 PORT_B);
13999 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14000 intel_dp_is_edp(dev, PORT_B))
14001 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14002
14003 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14004 !intel_dp_is_edp(dev, PORT_C))
14005 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14006 PORT_C);
14007 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14008 intel_dp_is_edp(dev, PORT_C))
14009 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14010
14011 if (IS_CHERRYVIEW(dev)) {
14012 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14013 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14014 PORT_D);
14015 /* eDP not supported on port D, so don't check VBT */
14016 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14017 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14018 }
14019
14020 intel_dsi_init(dev);
14021 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14022 bool found = false;
14023
14024 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14025 DRM_DEBUG_KMS("probing SDVOB\n");
14026 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14027 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14028 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14029 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14030 }
14031
14032 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14033 intel_dp_init(dev, DP_B, PORT_B);
14034 }
14035
14036 /* Before G4X SDVOC doesn't have its own detect register */
14037
14038 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14039 DRM_DEBUG_KMS("probing SDVOC\n");
14040 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14041 }
14042
14043 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14044
14045 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14046 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14047 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14048 }
14049 if (SUPPORTS_INTEGRATED_DP(dev))
14050 intel_dp_init(dev, DP_C, PORT_C);
14051 }
14052
14053 if (SUPPORTS_INTEGRATED_DP(dev) &&
14054 (I915_READ(DP_D) & DP_DETECTED))
14055 intel_dp_init(dev, DP_D, PORT_D);
14056 } else if (IS_GEN2(dev))
14057 intel_dvo_init(dev);
14058
14059 if (SUPPORTS_TV(dev))
14060 intel_tv_init(dev);
14061
14062 intel_psr_init(dev);
14063
14064 for_each_intel_encoder(dev, encoder) {
14065 encoder->base.possible_crtcs = encoder->crtc_mask;
14066 encoder->base.possible_clones =
14067 intel_encoder_clones(encoder);
14068 }
14069
14070 intel_init_pch_refclk(dev);
14071
14072 drm_helper_move_panel_connectors_to_head(dev);
14073 }
14074
14075 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14076 {
14077 struct drm_device *dev = fb->dev;
14078 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14079
14080 drm_framebuffer_cleanup(fb);
14081 mutex_lock(&dev->struct_mutex);
14082 WARN_ON(!intel_fb->obj->framebuffer_references--);
14083 drm_gem_object_unreference(&intel_fb->obj->base);
14084 mutex_unlock(&dev->struct_mutex);
14085 kfree(intel_fb);
14086 }
14087
14088 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14089 struct drm_file *file,
14090 unsigned int *handle)
14091 {
14092 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14093 struct drm_i915_gem_object *obj = intel_fb->obj;
14094
14095 return drm_gem_handle_create(file, &obj->base, handle);
14096 }
14097
14098 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14099 .destroy = intel_user_framebuffer_destroy,
14100 .create_handle = intel_user_framebuffer_create_handle,
14101 };
14102
14103 static
14104 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14105 uint32_t pixel_format)
14106 {
14107 u32 gen = INTEL_INFO(dev)->gen;
14108
14109 if (gen >= 9) {
14110 /* "The stride in bytes must not exceed the of the size of 8K
14111 * pixels and 32K bytes."
14112 */
14113 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14114 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14115 return 32*1024;
14116 } else if (gen >= 4) {
14117 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14118 return 16*1024;
14119 else
14120 return 32*1024;
14121 } else if (gen >= 3) {
14122 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14123 return 8*1024;
14124 else
14125 return 16*1024;
14126 } else {
14127 /* XXX DSPC is limited to 4k tiled */
14128 return 8*1024;
14129 }
14130 }
14131
14132 static int intel_framebuffer_init(struct drm_device *dev,
14133 struct intel_framebuffer *intel_fb,
14134 struct drm_mode_fb_cmd2 *mode_cmd,
14135 struct drm_i915_gem_object *obj)
14136 {
14137 unsigned int aligned_height;
14138 int ret;
14139 u32 pitch_limit, stride_alignment;
14140
14141 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14142
14143 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14144 /* Enforce that fb modifier and tiling mode match, but only for
14145 * X-tiled. This is needed for FBC. */
14146 if (!!(obj->tiling_mode == I915_TILING_X) !=
14147 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14148 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14149 return -EINVAL;
14150 }
14151 } else {
14152 if (obj->tiling_mode == I915_TILING_X)
14153 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14154 else if (obj->tiling_mode == I915_TILING_Y) {
14155 DRM_DEBUG("No Y tiling for legacy addfb\n");
14156 return -EINVAL;
14157 }
14158 }
14159
14160 /* Passed in modifier sanity checking. */
14161 switch (mode_cmd->modifier[0]) {
14162 case I915_FORMAT_MOD_Y_TILED:
14163 case I915_FORMAT_MOD_Yf_TILED:
14164 if (INTEL_INFO(dev)->gen < 9) {
14165 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14166 mode_cmd->modifier[0]);
14167 return -EINVAL;
14168 }
14169 case DRM_FORMAT_MOD_NONE:
14170 case I915_FORMAT_MOD_X_TILED:
14171 break;
14172 default:
14173 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14174 mode_cmd->modifier[0]);
14175 return -EINVAL;
14176 }
14177
14178 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14179 mode_cmd->pixel_format);
14180 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14181 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14182 mode_cmd->pitches[0], stride_alignment);
14183 return -EINVAL;
14184 }
14185
14186 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14187 mode_cmd->pixel_format);
14188 if (mode_cmd->pitches[0] > pitch_limit) {
14189 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14190 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14191 "tiled" : "linear",
14192 mode_cmd->pitches[0], pitch_limit);
14193 return -EINVAL;
14194 }
14195
14196 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14197 mode_cmd->pitches[0] != obj->stride) {
14198 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14199 mode_cmd->pitches[0], obj->stride);
14200 return -EINVAL;
14201 }
14202
14203 /* Reject formats not supported by any plane early. */
14204 switch (mode_cmd->pixel_format) {
14205 case DRM_FORMAT_C8:
14206 case DRM_FORMAT_RGB565:
14207 case DRM_FORMAT_XRGB8888:
14208 case DRM_FORMAT_ARGB8888:
14209 break;
14210 case DRM_FORMAT_XRGB1555:
14211 if (INTEL_INFO(dev)->gen > 3) {
14212 DRM_DEBUG("unsupported pixel format: %s\n",
14213 drm_get_format_name(mode_cmd->pixel_format));
14214 return -EINVAL;
14215 }
14216 break;
14217 case DRM_FORMAT_ABGR8888:
14218 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14219 DRM_DEBUG("unsupported pixel format: %s\n",
14220 drm_get_format_name(mode_cmd->pixel_format));
14221 return -EINVAL;
14222 }
14223 break;
14224 case DRM_FORMAT_XBGR8888:
14225 case DRM_FORMAT_XRGB2101010:
14226 case DRM_FORMAT_XBGR2101010:
14227 if (INTEL_INFO(dev)->gen < 4) {
14228 DRM_DEBUG("unsupported pixel format: %s\n",
14229 drm_get_format_name(mode_cmd->pixel_format));
14230 return -EINVAL;
14231 }
14232 break;
14233 case DRM_FORMAT_ABGR2101010:
14234 if (!IS_VALLEYVIEW(dev)) {
14235 DRM_DEBUG("unsupported pixel format: %s\n",
14236 drm_get_format_name(mode_cmd->pixel_format));
14237 return -EINVAL;
14238 }
14239 break;
14240 case DRM_FORMAT_YUYV:
14241 case DRM_FORMAT_UYVY:
14242 case DRM_FORMAT_YVYU:
14243 case DRM_FORMAT_VYUY:
14244 if (INTEL_INFO(dev)->gen < 5) {
14245 DRM_DEBUG("unsupported pixel format: %s\n",
14246 drm_get_format_name(mode_cmd->pixel_format));
14247 return -EINVAL;
14248 }
14249 break;
14250 default:
14251 DRM_DEBUG("unsupported pixel format: %s\n",
14252 drm_get_format_name(mode_cmd->pixel_format));
14253 return -EINVAL;
14254 }
14255
14256 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14257 if (mode_cmd->offsets[0] != 0)
14258 return -EINVAL;
14259
14260 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14261 mode_cmd->pixel_format,
14262 mode_cmd->modifier[0]);
14263 /* FIXME drm helper for size checks (especially planar formats)? */
14264 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14265 return -EINVAL;
14266
14267 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14268 intel_fb->obj = obj;
14269 intel_fb->obj->framebuffer_references++;
14270
14271 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14272 if (ret) {
14273 DRM_ERROR("framebuffer init failed %d\n", ret);
14274 return ret;
14275 }
14276
14277 return 0;
14278 }
14279
14280 static struct drm_framebuffer *
14281 intel_user_framebuffer_create(struct drm_device *dev,
14282 struct drm_file *filp,
14283 struct drm_mode_fb_cmd2 *mode_cmd)
14284 {
14285 struct drm_i915_gem_object *obj;
14286
14287 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14288 mode_cmd->handles[0]));
14289 if (&obj->base == NULL)
14290 return ERR_PTR(-ENOENT);
14291
14292 return intel_framebuffer_create(dev, mode_cmd, obj);
14293 }
14294
14295 #ifndef CONFIG_DRM_I915_FBDEV
14296 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14297 {
14298 }
14299 #endif
14300
14301 static const struct drm_mode_config_funcs intel_mode_funcs = {
14302 .fb_create = intel_user_framebuffer_create,
14303 .output_poll_changed = intel_fbdev_output_poll_changed,
14304 .atomic_check = intel_atomic_check,
14305 .atomic_commit = intel_atomic_commit,
14306 };
14307
14308 /* Set up chip specific display functions */
14309 static void intel_init_display(struct drm_device *dev)
14310 {
14311 struct drm_i915_private *dev_priv = dev->dev_private;
14312
14313 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14314 dev_priv->display.find_dpll = g4x_find_best_dpll;
14315 else if (IS_CHERRYVIEW(dev))
14316 dev_priv->display.find_dpll = chv_find_best_dpll;
14317 else if (IS_VALLEYVIEW(dev))
14318 dev_priv->display.find_dpll = vlv_find_best_dpll;
14319 else if (IS_PINEVIEW(dev))
14320 dev_priv->display.find_dpll = pnv_find_best_dpll;
14321 else
14322 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14323
14324 if (INTEL_INFO(dev)->gen >= 9) {
14325 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14326 dev_priv->display.get_initial_plane_config =
14327 skylake_get_initial_plane_config;
14328 dev_priv->display.crtc_compute_clock =
14329 haswell_crtc_compute_clock;
14330 dev_priv->display.crtc_enable = haswell_crtc_enable;
14331 dev_priv->display.crtc_disable = haswell_crtc_disable;
14332 dev_priv->display.off = ironlake_crtc_off;
14333 dev_priv->display.update_primary_plane =
14334 skylake_update_primary_plane;
14335 } else if (HAS_DDI(dev)) {
14336 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14337 dev_priv->display.get_initial_plane_config =
14338 ironlake_get_initial_plane_config;
14339 dev_priv->display.crtc_compute_clock =
14340 haswell_crtc_compute_clock;
14341 dev_priv->display.crtc_enable = haswell_crtc_enable;
14342 dev_priv->display.crtc_disable = haswell_crtc_disable;
14343 dev_priv->display.off = ironlake_crtc_off;
14344 dev_priv->display.update_primary_plane =
14345 ironlake_update_primary_plane;
14346 } else if (HAS_PCH_SPLIT(dev)) {
14347 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14348 dev_priv->display.get_initial_plane_config =
14349 ironlake_get_initial_plane_config;
14350 dev_priv->display.crtc_compute_clock =
14351 ironlake_crtc_compute_clock;
14352 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14353 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14354 dev_priv->display.off = ironlake_crtc_off;
14355 dev_priv->display.update_primary_plane =
14356 ironlake_update_primary_plane;
14357 } else if (IS_VALLEYVIEW(dev)) {
14358 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14359 dev_priv->display.get_initial_plane_config =
14360 i9xx_get_initial_plane_config;
14361 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14362 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14363 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14364 dev_priv->display.off = i9xx_crtc_off;
14365 dev_priv->display.update_primary_plane =
14366 i9xx_update_primary_plane;
14367 } else {
14368 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14369 dev_priv->display.get_initial_plane_config =
14370 i9xx_get_initial_plane_config;
14371 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14372 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14373 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14374 dev_priv->display.off = i9xx_crtc_off;
14375 dev_priv->display.update_primary_plane =
14376 i9xx_update_primary_plane;
14377 }
14378
14379 /* Returns the core display clock speed */
14380 if (IS_SKYLAKE(dev))
14381 dev_priv->display.get_display_clock_speed =
14382 skylake_get_display_clock_speed;
14383 else if (IS_BROADWELL(dev))
14384 dev_priv->display.get_display_clock_speed =
14385 broadwell_get_display_clock_speed;
14386 else if (IS_HASWELL(dev))
14387 dev_priv->display.get_display_clock_speed =
14388 haswell_get_display_clock_speed;
14389 else if (IS_VALLEYVIEW(dev))
14390 dev_priv->display.get_display_clock_speed =
14391 valleyview_get_display_clock_speed;
14392 else if (IS_GEN5(dev))
14393 dev_priv->display.get_display_clock_speed =
14394 ilk_get_display_clock_speed;
14395 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14396 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14397 dev_priv->display.get_display_clock_speed =
14398 i945_get_display_clock_speed;
14399 else if (IS_I915G(dev))
14400 dev_priv->display.get_display_clock_speed =
14401 i915_get_display_clock_speed;
14402 else if (IS_I945GM(dev) || IS_845G(dev))
14403 dev_priv->display.get_display_clock_speed =
14404 i9xx_misc_get_display_clock_speed;
14405 else if (IS_PINEVIEW(dev))
14406 dev_priv->display.get_display_clock_speed =
14407 pnv_get_display_clock_speed;
14408 else if (IS_I915GM(dev))
14409 dev_priv->display.get_display_clock_speed =
14410 i915gm_get_display_clock_speed;
14411 else if (IS_I865G(dev))
14412 dev_priv->display.get_display_clock_speed =
14413 i865_get_display_clock_speed;
14414 else if (IS_I85X(dev))
14415 dev_priv->display.get_display_clock_speed =
14416 i855_get_display_clock_speed;
14417 else /* 852, 830 */
14418 dev_priv->display.get_display_clock_speed =
14419 i830_get_display_clock_speed;
14420
14421 if (IS_GEN5(dev)) {
14422 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14423 } else if (IS_GEN6(dev)) {
14424 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14425 } else if (IS_IVYBRIDGE(dev)) {
14426 /* FIXME: detect B0+ stepping and use auto training */
14427 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14428 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14429 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14430 } else if (IS_VALLEYVIEW(dev)) {
14431 dev_priv->display.modeset_global_resources =
14432 valleyview_modeset_global_resources;
14433 } else if (IS_BROXTON(dev)) {
14434 dev_priv->display.modeset_global_resources =
14435 broxton_modeset_global_resources;
14436 }
14437
14438 switch (INTEL_INFO(dev)->gen) {
14439 case 2:
14440 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14441 break;
14442
14443 case 3:
14444 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14445 break;
14446
14447 case 4:
14448 case 5:
14449 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14450 break;
14451
14452 case 6:
14453 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14454 break;
14455 case 7:
14456 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14457 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14458 break;
14459 case 9:
14460 /* Drop through - unsupported since execlist only. */
14461 default:
14462 /* Default just returns -ENODEV to indicate unsupported */
14463 dev_priv->display.queue_flip = intel_default_queue_flip;
14464 }
14465
14466 intel_panel_init_backlight_funcs(dev);
14467
14468 mutex_init(&dev_priv->pps_mutex);
14469 }
14470
14471 /*
14472 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14473 * resume, or other times. This quirk makes sure that's the case for
14474 * affected systems.
14475 */
14476 static void quirk_pipea_force(struct drm_device *dev)
14477 {
14478 struct drm_i915_private *dev_priv = dev->dev_private;
14479
14480 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14481 DRM_INFO("applying pipe a force quirk\n");
14482 }
14483
14484 static void quirk_pipeb_force(struct drm_device *dev)
14485 {
14486 struct drm_i915_private *dev_priv = dev->dev_private;
14487
14488 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14489 DRM_INFO("applying pipe b force quirk\n");
14490 }
14491
14492 /*
14493 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14494 */
14495 static void quirk_ssc_force_disable(struct drm_device *dev)
14496 {
14497 struct drm_i915_private *dev_priv = dev->dev_private;
14498 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14499 DRM_INFO("applying lvds SSC disable quirk\n");
14500 }
14501
14502 /*
14503 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14504 * brightness value
14505 */
14506 static void quirk_invert_brightness(struct drm_device *dev)
14507 {
14508 struct drm_i915_private *dev_priv = dev->dev_private;
14509 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14510 DRM_INFO("applying inverted panel brightness quirk\n");
14511 }
14512
14513 /* Some VBT's incorrectly indicate no backlight is present */
14514 static void quirk_backlight_present(struct drm_device *dev)
14515 {
14516 struct drm_i915_private *dev_priv = dev->dev_private;
14517 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14518 DRM_INFO("applying backlight present quirk\n");
14519 }
14520
14521 struct intel_quirk {
14522 int device;
14523 int subsystem_vendor;
14524 int subsystem_device;
14525 void (*hook)(struct drm_device *dev);
14526 };
14527
14528 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14529 struct intel_dmi_quirk {
14530 void (*hook)(struct drm_device *dev);
14531 const struct dmi_system_id (*dmi_id_list)[];
14532 };
14533
14534 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14535 {
14536 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14537 return 1;
14538 }
14539
14540 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14541 {
14542 .dmi_id_list = &(const struct dmi_system_id[]) {
14543 {
14544 .callback = intel_dmi_reverse_brightness,
14545 .ident = "NCR Corporation",
14546 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14547 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14548 },
14549 },
14550 { } /* terminating entry */
14551 },
14552 .hook = quirk_invert_brightness,
14553 },
14554 };
14555
14556 static struct intel_quirk intel_quirks[] = {
14557 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14558 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14559
14560 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14561 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14562
14563 /* 830 needs to leave pipe A & dpll A up */
14564 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14565
14566 /* 830 needs to leave pipe B & dpll B up */
14567 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14568
14569 /* Lenovo U160 cannot use SSC on LVDS */
14570 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14571
14572 /* Sony Vaio Y cannot use SSC on LVDS */
14573 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14574
14575 /* Acer Aspire 5734Z must invert backlight brightness */
14576 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14577
14578 /* Acer/eMachines G725 */
14579 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14580
14581 /* Acer/eMachines e725 */
14582 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14583
14584 /* Acer/Packard Bell NCL20 */
14585 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14586
14587 /* Acer Aspire 4736Z */
14588 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14589
14590 /* Acer Aspire 5336 */
14591 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14592
14593 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14594 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14595
14596 /* Acer C720 Chromebook (Core i3 4005U) */
14597 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14598
14599 /* Apple Macbook 2,1 (Core 2 T7400) */
14600 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14601
14602 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14603 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14604
14605 /* HP Chromebook 14 (Celeron 2955U) */
14606 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14607
14608 /* Dell Chromebook 11 */
14609 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14610 };
14611
14612 static void intel_init_quirks(struct drm_device *dev)
14613 {
14614 struct pci_dev *d = dev->pdev;
14615 int i;
14616
14617 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14618 struct intel_quirk *q = &intel_quirks[i];
14619
14620 if (d->device == q->device &&
14621 (d->subsystem_vendor == q->subsystem_vendor ||
14622 q->subsystem_vendor == PCI_ANY_ID) &&
14623 (d->subsystem_device == q->subsystem_device ||
14624 q->subsystem_device == PCI_ANY_ID))
14625 q->hook(dev);
14626 }
14627 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14628 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14629 intel_dmi_quirks[i].hook(dev);
14630 }
14631 }
14632
14633 /* Disable the VGA plane that we never use */
14634 static void i915_disable_vga(struct drm_device *dev)
14635 {
14636 struct drm_i915_private *dev_priv = dev->dev_private;
14637 u8 sr1;
14638 u32 vga_reg = i915_vgacntrl_reg(dev);
14639
14640 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14641 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14642 outb(SR01, VGA_SR_INDEX);
14643 sr1 = inb(VGA_SR_DATA);
14644 outb(sr1 | 1<<5, VGA_SR_DATA);
14645 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14646 udelay(300);
14647
14648 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14649 POSTING_READ(vga_reg);
14650 }
14651
14652 void intel_modeset_init_hw(struct drm_device *dev)
14653 {
14654 intel_prepare_ddi(dev);
14655
14656 if (IS_VALLEYVIEW(dev))
14657 vlv_update_cdclk(dev);
14658
14659 intel_init_clock_gating(dev);
14660
14661 intel_enable_gt_powersave(dev);
14662 }
14663
14664 void intel_modeset_init(struct drm_device *dev)
14665 {
14666 struct drm_i915_private *dev_priv = dev->dev_private;
14667 int sprite, ret;
14668 enum pipe pipe;
14669 struct intel_crtc *crtc;
14670
14671 drm_mode_config_init(dev);
14672
14673 dev->mode_config.min_width = 0;
14674 dev->mode_config.min_height = 0;
14675
14676 dev->mode_config.preferred_depth = 24;
14677 dev->mode_config.prefer_shadow = 1;
14678
14679 dev->mode_config.allow_fb_modifiers = true;
14680
14681 dev->mode_config.funcs = &intel_mode_funcs;
14682
14683 intel_init_quirks(dev);
14684
14685 intel_init_pm(dev);
14686
14687 if (INTEL_INFO(dev)->num_pipes == 0)
14688 return;
14689
14690 intel_init_display(dev);
14691 intel_init_audio(dev);
14692
14693 if (IS_GEN2(dev)) {
14694 dev->mode_config.max_width = 2048;
14695 dev->mode_config.max_height = 2048;
14696 } else if (IS_GEN3(dev)) {
14697 dev->mode_config.max_width = 4096;
14698 dev->mode_config.max_height = 4096;
14699 } else {
14700 dev->mode_config.max_width = 8192;
14701 dev->mode_config.max_height = 8192;
14702 }
14703
14704 if (IS_845G(dev) || IS_I865G(dev)) {
14705 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14706 dev->mode_config.cursor_height = 1023;
14707 } else if (IS_GEN2(dev)) {
14708 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14709 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14710 } else {
14711 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14712 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14713 }
14714
14715 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14716
14717 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14718 INTEL_INFO(dev)->num_pipes,
14719 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14720
14721 for_each_pipe(dev_priv, pipe) {
14722 intel_crtc_init(dev, pipe);
14723 for_each_sprite(dev_priv, pipe, sprite) {
14724 ret = intel_plane_init(dev, pipe, sprite);
14725 if (ret)
14726 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14727 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14728 }
14729 }
14730
14731 intel_init_dpio(dev);
14732
14733 intel_shared_dpll_init(dev);
14734
14735 /* Just disable it once at startup */
14736 i915_disable_vga(dev);
14737 intel_setup_outputs(dev);
14738
14739 /* Just in case the BIOS is doing something questionable. */
14740 intel_fbc_disable(dev);
14741
14742 drm_modeset_lock_all(dev);
14743 intel_modeset_setup_hw_state(dev, false);
14744 drm_modeset_unlock_all(dev);
14745
14746 for_each_intel_crtc(dev, crtc) {
14747 if (!crtc->active)
14748 continue;
14749
14750 /*
14751 * Note that reserving the BIOS fb up front prevents us
14752 * from stuffing other stolen allocations like the ring
14753 * on top. This prevents some ugliness at boot time, and
14754 * can even allow for smooth boot transitions if the BIOS
14755 * fb is large enough for the active pipe configuration.
14756 */
14757 if (dev_priv->display.get_initial_plane_config) {
14758 dev_priv->display.get_initial_plane_config(crtc,
14759 &crtc->plane_config);
14760 /*
14761 * If the fb is shared between multiple heads, we'll
14762 * just get the first one.
14763 */
14764 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14765 }
14766 }
14767 }
14768
14769 static void intel_enable_pipe_a(struct drm_device *dev)
14770 {
14771 struct intel_connector *connector;
14772 struct drm_connector *crt = NULL;
14773 struct intel_load_detect_pipe load_detect_temp;
14774 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14775
14776 /* We can't just switch on the pipe A, we need to set things up with a
14777 * proper mode and output configuration. As a gross hack, enable pipe A
14778 * by enabling the load detect pipe once. */
14779 for_each_intel_connector(dev, connector) {
14780 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14781 crt = &connector->base;
14782 break;
14783 }
14784 }
14785
14786 if (!crt)
14787 return;
14788
14789 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14790 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14791 }
14792
14793 static bool
14794 intel_check_plane_mapping(struct intel_crtc *crtc)
14795 {
14796 struct drm_device *dev = crtc->base.dev;
14797 struct drm_i915_private *dev_priv = dev->dev_private;
14798 u32 reg, val;
14799
14800 if (INTEL_INFO(dev)->num_pipes == 1)
14801 return true;
14802
14803 reg = DSPCNTR(!crtc->plane);
14804 val = I915_READ(reg);
14805
14806 if ((val & DISPLAY_PLANE_ENABLE) &&
14807 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14808 return false;
14809
14810 return true;
14811 }
14812
14813 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14814 {
14815 struct drm_device *dev = crtc->base.dev;
14816 struct drm_i915_private *dev_priv = dev->dev_private;
14817 u32 reg;
14818
14819 /* Clear any frame start delays used for debugging left by the BIOS */
14820 reg = PIPECONF(crtc->config->cpu_transcoder);
14821 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14822
14823 /* restore vblank interrupts to correct state */
14824 drm_crtc_vblank_reset(&crtc->base);
14825 if (crtc->active) {
14826 update_scanline_offset(crtc);
14827 drm_crtc_vblank_on(&crtc->base);
14828 }
14829
14830 /* We need to sanitize the plane -> pipe mapping first because this will
14831 * disable the crtc (and hence change the state) if it is wrong. Note
14832 * that gen4+ has a fixed plane -> pipe mapping. */
14833 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14834 struct intel_connector *connector;
14835 bool plane;
14836
14837 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14838 crtc->base.base.id);
14839
14840 /* Pipe has the wrong plane attached and the plane is active.
14841 * Temporarily change the plane mapping and disable everything
14842 * ... */
14843 plane = crtc->plane;
14844 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14845 crtc->plane = !plane;
14846 intel_crtc_disable_planes(&crtc->base);
14847 dev_priv->display.crtc_disable(&crtc->base);
14848 crtc->plane = plane;
14849
14850 /* ... and break all links. */
14851 for_each_intel_connector(dev, connector) {
14852 if (connector->encoder->base.crtc != &crtc->base)
14853 continue;
14854
14855 connector->base.dpms = DRM_MODE_DPMS_OFF;
14856 connector->base.encoder = NULL;
14857 }
14858 /* multiple connectors may have the same encoder:
14859 * handle them and break crtc link separately */
14860 for_each_intel_connector(dev, connector)
14861 if (connector->encoder->base.crtc == &crtc->base) {
14862 connector->encoder->base.crtc = NULL;
14863 connector->encoder->connectors_active = false;
14864 }
14865
14866 WARN_ON(crtc->active);
14867 crtc->base.state->enable = false;
14868 crtc->base.state->active = false;
14869 crtc->base.enabled = false;
14870 }
14871
14872 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14873 crtc->pipe == PIPE_A && !crtc->active) {
14874 /* BIOS forgot to enable pipe A, this mostly happens after
14875 * resume. Force-enable the pipe to fix this, the update_dpms
14876 * call below we restore the pipe to the right state, but leave
14877 * the required bits on. */
14878 intel_enable_pipe_a(dev);
14879 }
14880
14881 /* Adjust the state of the output pipe according to whether we
14882 * have active connectors/encoders. */
14883 intel_crtc_update_dpms(&crtc->base);
14884
14885 if (crtc->active != crtc->base.state->enable) {
14886 struct intel_encoder *encoder;
14887
14888 /* This can happen either due to bugs in the get_hw_state
14889 * functions or because the pipe is force-enabled due to the
14890 * pipe A quirk. */
14891 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14892 crtc->base.base.id,
14893 crtc->base.state->enable ? "enabled" : "disabled",
14894 crtc->active ? "enabled" : "disabled");
14895
14896 crtc->base.state->enable = crtc->active;
14897 crtc->base.state->active = crtc->active;
14898 crtc->base.enabled = crtc->active;
14899
14900 /* Because we only establish the connector -> encoder ->
14901 * crtc links if something is active, this means the
14902 * crtc is now deactivated. Break the links. connector
14903 * -> encoder links are only establish when things are
14904 * actually up, hence no need to break them. */
14905 WARN_ON(crtc->active);
14906
14907 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14908 WARN_ON(encoder->connectors_active);
14909 encoder->base.crtc = NULL;
14910 }
14911 }
14912
14913 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14914 /*
14915 * We start out with underrun reporting disabled to avoid races.
14916 * For correct bookkeeping mark this on active crtcs.
14917 *
14918 * Also on gmch platforms we dont have any hardware bits to
14919 * disable the underrun reporting. Which means we need to start
14920 * out with underrun reporting disabled also on inactive pipes,
14921 * since otherwise we'll complain about the garbage we read when
14922 * e.g. coming up after runtime pm.
14923 *
14924 * No protection against concurrent access is required - at
14925 * worst a fifo underrun happens which also sets this to false.
14926 */
14927 crtc->cpu_fifo_underrun_disabled = true;
14928 crtc->pch_fifo_underrun_disabled = true;
14929 }
14930 }
14931
14932 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14933 {
14934 struct intel_connector *connector;
14935 struct drm_device *dev = encoder->base.dev;
14936
14937 /* We need to check both for a crtc link (meaning that the
14938 * encoder is active and trying to read from a pipe) and the
14939 * pipe itself being active. */
14940 bool has_active_crtc = encoder->base.crtc &&
14941 to_intel_crtc(encoder->base.crtc)->active;
14942
14943 if (encoder->connectors_active && !has_active_crtc) {
14944 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14945 encoder->base.base.id,
14946 encoder->base.name);
14947
14948 /* Connector is active, but has no active pipe. This is
14949 * fallout from our resume register restoring. Disable
14950 * the encoder manually again. */
14951 if (encoder->base.crtc) {
14952 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14953 encoder->base.base.id,
14954 encoder->base.name);
14955 encoder->disable(encoder);
14956 if (encoder->post_disable)
14957 encoder->post_disable(encoder);
14958 }
14959 encoder->base.crtc = NULL;
14960 encoder->connectors_active = false;
14961
14962 /* Inconsistent output/port/pipe state happens presumably due to
14963 * a bug in one of the get_hw_state functions. Or someplace else
14964 * in our code, like the register restore mess on resume. Clamp
14965 * things to off as a safer default. */
14966 for_each_intel_connector(dev, connector) {
14967 if (connector->encoder != encoder)
14968 continue;
14969 connector->base.dpms = DRM_MODE_DPMS_OFF;
14970 connector->base.encoder = NULL;
14971 }
14972 }
14973 /* Enabled encoders without active connectors will be fixed in
14974 * the crtc fixup. */
14975 }
14976
14977 void i915_redisable_vga_power_on(struct drm_device *dev)
14978 {
14979 struct drm_i915_private *dev_priv = dev->dev_private;
14980 u32 vga_reg = i915_vgacntrl_reg(dev);
14981
14982 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14983 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14984 i915_disable_vga(dev);
14985 }
14986 }
14987
14988 void i915_redisable_vga(struct drm_device *dev)
14989 {
14990 struct drm_i915_private *dev_priv = dev->dev_private;
14991
14992 /* This function can be called both from intel_modeset_setup_hw_state or
14993 * at a very early point in our resume sequence, where the power well
14994 * structures are not yet restored. Since this function is at a very
14995 * paranoid "someone might have enabled VGA while we were not looking"
14996 * level, just check if the power well is enabled instead of trying to
14997 * follow the "don't touch the power well if we don't need it" policy
14998 * the rest of the driver uses. */
14999 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15000 return;
15001
15002 i915_redisable_vga_power_on(dev);
15003 }
15004
15005 static bool primary_get_hw_state(struct intel_crtc *crtc)
15006 {
15007 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15008
15009 if (!crtc->active)
15010 return false;
15011
15012 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15013 }
15014
15015 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15016 {
15017 struct drm_i915_private *dev_priv = dev->dev_private;
15018 enum pipe pipe;
15019 struct intel_crtc *crtc;
15020 struct intel_encoder *encoder;
15021 struct intel_connector *connector;
15022 int i;
15023
15024 for_each_intel_crtc(dev, crtc) {
15025 struct drm_plane *primary = crtc->base.primary;
15026 struct intel_plane_state *plane_state;
15027
15028 memset(crtc->config, 0, sizeof(*crtc->config));
15029
15030 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15031
15032 crtc->active = dev_priv->display.get_pipe_config(crtc,
15033 crtc->config);
15034
15035 crtc->base.state->enable = crtc->active;
15036 crtc->base.state->active = crtc->active;
15037 crtc->base.enabled = crtc->active;
15038
15039 plane_state = to_intel_plane_state(primary->state);
15040 plane_state->visible = primary_get_hw_state(crtc);
15041
15042 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15043 crtc->base.base.id,
15044 crtc->active ? "enabled" : "disabled");
15045 }
15046
15047 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15048 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15049
15050 pll->on = pll->get_hw_state(dev_priv, pll,
15051 &pll->config.hw_state);
15052 pll->active = 0;
15053 pll->config.crtc_mask = 0;
15054 for_each_intel_crtc(dev, crtc) {
15055 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15056 pll->active++;
15057 pll->config.crtc_mask |= 1 << crtc->pipe;
15058 }
15059 }
15060
15061 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15062 pll->name, pll->config.crtc_mask, pll->on);
15063
15064 if (pll->config.crtc_mask)
15065 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15066 }
15067
15068 for_each_intel_encoder(dev, encoder) {
15069 pipe = 0;
15070
15071 if (encoder->get_hw_state(encoder, &pipe)) {
15072 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15073 encoder->base.crtc = &crtc->base;
15074 encoder->get_config(encoder, crtc->config);
15075 } else {
15076 encoder->base.crtc = NULL;
15077 }
15078
15079 encoder->connectors_active = false;
15080 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15081 encoder->base.base.id,
15082 encoder->base.name,
15083 encoder->base.crtc ? "enabled" : "disabled",
15084 pipe_name(pipe));
15085 }
15086
15087 for_each_intel_connector(dev, connector) {
15088 if (connector->get_hw_state(connector)) {
15089 connector->base.dpms = DRM_MODE_DPMS_ON;
15090 connector->encoder->connectors_active = true;
15091 connector->base.encoder = &connector->encoder->base;
15092 } else {
15093 connector->base.dpms = DRM_MODE_DPMS_OFF;
15094 connector->base.encoder = NULL;
15095 }
15096 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15097 connector->base.base.id,
15098 connector->base.name,
15099 connector->base.encoder ? "enabled" : "disabled");
15100 }
15101 }
15102
15103 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15104 * and i915 state tracking structures. */
15105 void intel_modeset_setup_hw_state(struct drm_device *dev,
15106 bool force_restore)
15107 {
15108 struct drm_i915_private *dev_priv = dev->dev_private;
15109 enum pipe pipe;
15110 struct intel_crtc *crtc;
15111 struct intel_encoder *encoder;
15112 int i;
15113
15114 intel_modeset_readout_hw_state(dev);
15115
15116 /*
15117 * Now that we have the config, copy it to each CRTC struct
15118 * Note that this could go away if we move to using crtc_config
15119 * checking everywhere.
15120 */
15121 for_each_intel_crtc(dev, crtc) {
15122 if (crtc->active && i915.fastboot) {
15123 intel_mode_from_pipe_config(&crtc->base.mode,
15124 crtc->config);
15125 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15126 crtc->base.base.id);
15127 drm_mode_debug_printmodeline(&crtc->base.mode);
15128 }
15129 }
15130
15131 /* HW state is read out, now we need to sanitize this mess. */
15132 for_each_intel_encoder(dev, encoder) {
15133 intel_sanitize_encoder(encoder);
15134 }
15135
15136 for_each_pipe(dev_priv, pipe) {
15137 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15138 intel_sanitize_crtc(crtc);
15139 intel_dump_pipe_config(crtc, crtc->config,
15140 "[setup_hw_state]");
15141 }
15142
15143 intel_modeset_update_connector_atomic_state(dev);
15144
15145 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15146 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15147
15148 if (!pll->on || pll->active)
15149 continue;
15150
15151 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15152
15153 pll->disable(dev_priv, pll);
15154 pll->on = false;
15155 }
15156
15157 if (IS_GEN9(dev))
15158 skl_wm_get_hw_state(dev);
15159 else if (HAS_PCH_SPLIT(dev))
15160 ilk_wm_get_hw_state(dev);
15161
15162 if (force_restore) {
15163 i915_redisable_vga(dev);
15164
15165 /*
15166 * We need to use raw interfaces for restoring state to avoid
15167 * checking (bogus) intermediate states.
15168 */
15169 for_each_pipe(dev_priv, pipe) {
15170 struct drm_crtc *crtc =
15171 dev_priv->pipe_to_crtc_mapping[pipe];
15172
15173 intel_crtc_restore_mode(crtc);
15174 }
15175 } else {
15176 intel_modeset_update_staged_output_state(dev);
15177 }
15178
15179 intel_modeset_check_state(dev);
15180 }
15181
15182 void intel_modeset_gem_init(struct drm_device *dev)
15183 {
15184 struct drm_i915_private *dev_priv = dev->dev_private;
15185 struct drm_crtc *c;
15186 struct drm_i915_gem_object *obj;
15187 int ret;
15188
15189 mutex_lock(&dev->struct_mutex);
15190 intel_init_gt_powersave(dev);
15191 mutex_unlock(&dev->struct_mutex);
15192
15193 /*
15194 * There may be no VBT; and if the BIOS enabled SSC we can
15195 * just keep using it to avoid unnecessary flicker. Whereas if the
15196 * BIOS isn't using it, don't assume it will work even if the VBT
15197 * indicates as much.
15198 */
15199 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15200 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15201 DREF_SSC1_ENABLE);
15202
15203 intel_modeset_init_hw(dev);
15204
15205 intel_setup_overlay(dev);
15206
15207 /*
15208 * Make sure any fbs we allocated at startup are properly
15209 * pinned & fenced. When we do the allocation it's too early
15210 * for this.
15211 */
15212 for_each_crtc(dev, c) {
15213 obj = intel_fb_obj(c->primary->fb);
15214 if (obj == NULL)
15215 continue;
15216
15217 mutex_lock(&dev->struct_mutex);
15218 ret = intel_pin_and_fence_fb_obj(c->primary,
15219 c->primary->fb,
15220 c->primary->state,
15221 NULL);
15222 mutex_unlock(&dev->struct_mutex);
15223 if (ret) {
15224 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15225 to_intel_crtc(c)->pipe);
15226 drm_framebuffer_unreference(c->primary->fb);
15227 c->primary->fb = NULL;
15228 update_state_fb(c->primary);
15229 }
15230 }
15231
15232 intel_backlight_register(dev);
15233 }
15234
15235 void intel_connector_unregister(struct intel_connector *intel_connector)
15236 {
15237 struct drm_connector *connector = &intel_connector->base;
15238
15239 intel_panel_destroy_backlight(connector);
15240 drm_connector_unregister(connector);
15241 }
15242
15243 void intel_modeset_cleanup(struct drm_device *dev)
15244 {
15245 struct drm_i915_private *dev_priv = dev->dev_private;
15246 struct drm_connector *connector;
15247
15248 intel_disable_gt_powersave(dev);
15249
15250 intel_backlight_unregister(dev);
15251
15252 /*
15253 * Interrupts and polling as the first thing to avoid creating havoc.
15254 * Too much stuff here (turning of connectors, ...) would
15255 * experience fancy races otherwise.
15256 */
15257 intel_irq_uninstall(dev_priv);
15258
15259 /*
15260 * Due to the hpd irq storm handling the hotplug work can re-arm the
15261 * poll handlers. Hence disable polling after hpd handling is shut down.
15262 */
15263 drm_kms_helper_poll_fini(dev);
15264
15265 mutex_lock(&dev->struct_mutex);
15266
15267 intel_unregister_dsm_handler();
15268
15269 intel_fbc_disable(dev);
15270
15271 mutex_unlock(&dev->struct_mutex);
15272
15273 /* flush any delayed tasks or pending work */
15274 flush_scheduled_work();
15275
15276 /* destroy the backlight and sysfs files before encoders/connectors */
15277 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15278 struct intel_connector *intel_connector;
15279
15280 intel_connector = to_intel_connector(connector);
15281 intel_connector->unregister(intel_connector);
15282 }
15283
15284 drm_mode_config_cleanup(dev);
15285
15286 intel_cleanup_overlay(dev);
15287
15288 mutex_lock(&dev->struct_mutex);
15289 intel_cleanup_gt_powersave(dev);
15290 mutex_unlock(&dev->struct_mutex);
15291 }
15292
15293 /*
15294 * Return which encoder is currently attached for connector.
15295 */
15296 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15297 {
15298 return &intel_attached_encoder(connector)->base;
15299 }
15300
15301 void intel_connector_attach_encoder(struct intel_connector *connector,
15302 struct intel_encoder *encoder)
15303 {
15304 connector->encoder = encoder;
15305 drm_mode_connector_attach_encoder(&connector->base,
15306 &encoder->base);
15307 }
15308
15309 /*
15310 * set vga decode state - true == enable VGA decode
15311 */
15312 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15313 {
15314 struct drm_i915_private *dev_priv = dev->dev_private;
15315 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15316 u16 gmch_ctrl;
15317
15318 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15319 DRM_ERROR("failed to read control word\n");
15320 return -EIO;
15321 }
15322
15323 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15324 return 0;
15325
15326 if (state)
15327 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15328 else
15329 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15330
15331 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15332 DRM_ERROR("failed to write control word\n");
15333 return -EIO;
15334 }
15335
15336 return 0;
15337 }
15338
15339 struct intel_display_error_state {
15340
15341 u32 power_well_driver;
15342
15343 int num_transcoders;
15344
15345 struct intel_cursor_error_state {
15346 u32 control;
15347 u32 position;
15348 u32 base;
15349 u32 size;
15350 } cursor[I915_MAX_PIPES];
15351
15352 struct intel_pipe_error_state {
15353 bool power_domain_on;
15354 u32 source;
15355 u32 stat;
15356 } pipe[I915_MAX_PIPES];
15357
15358 struct intel_plane_error_state {
15359 u32 control;
15360 u32 stride;
15361 u32 size;
15362 u32 pos;
15363 u32 addr;
15364 u32 surface;
15365 u32 tile_offset;
15366 } plane[I915_MAX_PIPES];
15367
15368 struct intel_transcoder_error_state {
15369 bool power_domain_on;
15370 enum transcoder cpu_transcoder;
15371
15372 u32 conf;
15373
15374 u32 htotal;
15375 u32 hblank;
15376 u32 hsync;
15377 u32 vtotal;
15378 u32 vblank;
15379 u32 vsync;
15380 } transcoder[4];
15381 };
15382
15383 struct intel_display_error_state *
15384 intel_display_capture_error_state(struct drm_device *dev)
15385 {
15386 struct drm_i915_private *dev_priv = dev->dev_private;
15387 struct intel_display_error_state *error;
15388 int transcoders[] = {
15389 TRANSCODER_A,
15390 TRANSCODER_B,
15391 TRANSCODER_C,
15392 TRANSCODER_EDP,
15393 };
15394 int i;
15395
15396 if (INTEL_INFO(dev)->num_pipes == 0)
15397 return NULL;
15398
15399 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15400 if (error == NULL)
15401 return NULL;
15402
15403 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15404 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15405
15406 for_each_pipe(dev_priv, i) {
15407 error->pipe[i].power_domain_on =
15408 __intel_display_power_is_enabled(dev_priv,
15409 POWER_DOMAIN_PIPE(i));
15410 if (!error->pipe[i].power_domain_on)
15411 continue;
15412
15413 error->cursor[i].control = I915_READ(CURCNTR(i));
15414 error->cursor[i].position = I915_READ(CURPOS(i));
15415 error->cursor[i].base = I915_READ(CURBASE(i));
15416
15417 error->plane[i].control = I915_READ(DSPCNTR(i));
15418 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15419 if (INTEL_INFO(dev)->gen <= 3) {
15420 error->plane[i].size = I915_READ(DSPSIZE(i));
15421 error->plane[i].pos = I915_READ(DSPPOS(i));
15422 }
15423 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15424 error->plane[i].addr = I915_READ(DSPADDR(i));
15425 if (INTEL_INFO(dev)->gen >= 4) {
15426 error->plane[i].surface = I915_READ(DSPSURF(i));
15427 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15428 }
15429
15430 error->pipe[i].source = I915_READ(PIPESRC(i));
15431
15432 if (HAS_GMCH_DISPLAY(dev))
15433 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15434 }
15435
15436 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15437 if (HAS_DDI(dev_priv->dev))
15438 error->num_transcoders++; /* Account for eDP. */
15439
15440 for (i = 0; i < error->num_transcoders; i++) {
15441 enum transcoder cpu_transcoder = transcoders[i];
15442
15443 error->transcoder[i].power_domain_on =
15444 __intel_display_power_is_enabled(dev_priv,
15445 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15446 if (!error->transcoder[i].power_domain_on)
15447 continue;
15448
15449 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15450
15451 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15452 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15453 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15454 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15455 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15456 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15457 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15458 }
15459
15460 return error;
15461 }
15462
15463 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15464
15465 void
15466 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15467 struct drm_device *dev,
15468 struct intel_display_error_state *error)
15469 {
15470 struct drm_i915_private *dev_priv = dev->dev_private;
15471 int i;
15472
15473 if (!error)
15474 return;
15475
15476 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15477 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15478 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15479 error->power_well_driver);
15480 for_each_pipe(dev_priv, i) {
15481 err_printf(m, "Pipe [%d]:\n", i);
15482 err_printf(m, " Power: %s\n",
15483 error->pipe[i].power_domain_on ? "on" : "off");
15484 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15485 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15486
15487 err_printf(m, "Plane [%d]:\n", i);
15488 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15489 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15490 if (INTEL_INFO(dev)->gen <= 3) {
15491 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15492 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15493 }
15494 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15495 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15496 if (INTEL_INFO(dev)->gen >= 4) {
15497 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15498 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15499 }
15500
15501 err_printf(m, "Cursor [%d]:\n", i);
15502 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15503 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15504 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15505 }
15506
15507 for (i = 0; i < error->num_transcoders; i++) {
15508 err_printf(m, "CPU transcoder: %c\n",
15509 transcoder_name(error->transcoder[i].cpu_transcoder));
15510 err_printf(m, " Power: %s\n",
15511 error->transcoder[i].power_domain_on ? "on" : "off");
15512 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15513 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15514 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15515 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15516 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15517 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15518 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15519 }
15520 }
15521
15522 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15523 {
15524 struct intel_crtc *crtc;
15525
15526 for_each_intel_crtc(dev, crtc) {
15527 struct intel_unpin_work *work;
15528
15529 spin_lock_irq(&dev->event_lock);
15530
15531 work = crtc->unpin_work;
15532
15533 if (work && work->event &&
15534 work->event->base.file_priv == file) {
15535 kfree(work->event);
15536 work->event = NULL;
15537 }
15538
15539 spin_unlock_irq(&dev->event_lock);
15540 }
15541 }
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