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drm/i915: Make IS_BROXTON only take dev_priv
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
617 !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
622 !IS_BROXTON(dev_priv)) {
623 if (clock->p < limit->p.min || limit->p.max < clock->p)
624 INTELPllInvalid("p out of range\n");
625 if (clock->m < limit->m.min || limit->m.max < clock->m)
626 INTELPllInvalid("m out of range\n");
627 }
628
629 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
630 INTELPllInvalid("vco out of range\n");
631 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632 * connector, etc., rather than just a single range.
633 */
634 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
635 INTELPllInvalid("dot out of range\n");
636
637 return true;
638 }
639
640 static int
641 i9xx_select_p2_div(const struct intel_limit *limit,
642 const struct intel_crtc_state *crtc_state,
643 int target)
644 {
645 struct drm_device *dev = crtc_state->base.crtc->dev;
646
647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648 /*
649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
652 */
653 if (intel_is_dual_link_lvds(dev))
654 return limit->p2.p2_fast;
655 else
656 return limit->p2.p2_slow;
657 } else {
658 if (target < limit->p2.dot_limit)
659 return limit->p2.p2_slow;
660 else
661 return limit->p2.p2_fast;
662 }
663 }
664
665 /*
666 * Returns a set of divisors for the desired target clock with the given
667 * refclk, or FALSE. The returned values represent the clock equation:
668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669 *
670 * Target and reference clocks are specified in kHz.
671 *
672 * If match_clock is provided, then best_clock P divider must match the P
673 * divider from @match_clock used for LVDS downclocking.
674 */
675 static bool
676 i9xx_find_best_dpll(const struct intel_limit *limit,
677 struct intel_crtc_state *crtc_state,
678 int target, int refclk, struct dpll *match_clock,
679 struct dpll *best_clock)
680 {
681 struct drm_device *dev = crtc_state->base.crtc->dev;
682 struct dpll clock;
683 int err = target;
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 if (clock.m2 >= clock.m1)
694 break;
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 i9xx_calc_dpll_params(refclk, &clock);
702 if (!intel_PLL_is_valid(to_i915(dev),
703 limit,
704 &clock))
705 continue;
706 if (match_clock &&
707 clock.p != match_clock->p)
708 continue;
709
710 this_err = abs(clock.dot - target);
711 if (this_err < err) {
712 *best_clock = clock;
713 err = this_err;
714 }
715 }
716 }
717 }
718 }
719
720 return (err != target);
721 }
722
723 /*
724 * Returns a set of divisors for the desired target clock with the given
725 * refclk, or FALSE. The returned values represent the clock equation:
726 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
727 *
728 * Target and reference clocks are specified in kHz.
729 *
730 * If match_clock is provided, then best_clock P divider must match the P
731 * divider from @match_clock used for LVDS downclocking.
732 */
733 static bool
734 pnv_find_best_dpll(const struct intel_limit *limit,
735 struct intel_crtc_state *crtc_state,
736 int target, int refclk, struct dpll *match_clock,
737 struct dpll *best_clock)
738 {
739 struct drm_device *dev = crtc_state->base.crtc->dev;
740 struct dpll clock;
741 int err = target;
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748 clock.m1++) {
749 for (clock.m2 = limit->m2.min;
750 clock.m2 <= limit->m2.max; clock.m2++) {
751 for (clock.n = limit->n.min;
752 clock.n <= limit->n.max; clock.n++) {
753 for (clock.p1 = limit->p1.min;
754 clock.p1 <= limit->p1.max; clock.p1++) {
755 int this_err;
756
757 pnv_calc_dpll_params(refclk, &clock);
758 if (!intel_PLL_is_valid(to_i915(dev),
759 limit,
760 &clock))
761 continue;
762 if (match_clock &&
763 clock.p != match_clock->p)
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 }
771 }
772 }
773 }
774 }
775
776 return (err != target);
777 }
778
779 /*
780 * Returns a set of divisors for the desired target clock with the given
781 * refclk, or FALSE. The returned values represent the clock equation:
782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
783 *
784 * Target and reference clocks are specified in kHz.
785 *
786 * If match_clock is provided, then best_clock P divider must match the P
787 * divider from @match_clock used for LVDS downclocking.
788 */
789 static bool
790 g4x_find_best_dpll(const struct intel_limit *limit,
791 struct intel_crtc_state *crtc_state,
792 int target, int refclk, struct dpll *match_clock,
793 struct dpll *best_clock)
794 {
795 struct drm_device *dev = crtc_state->base.crtc->dev;
796 struct dpll clock;
797 int max_n;
798 bool found = false;
799 /* approximately equals target * 0.00585 */
800 int err_most = (target >> 8) + (target >> 9);
801
802 memset(best_clock, 0, sizeof(*best_clock));
803
804 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
805
806 max_n = limit->n.max;
807 /* based on hardware requirement, prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirement, prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 i9xx_calc_dpll_params(refclk, &clock);
819 if (!intel_PLL_is_valid(to_i915(dev),
820 limit,
821 &clock))
822 continue;
823
824 this_err = abs(clock.dot - target);
825 if (this_err < err_most) {
826 *best_clock = clock;
827 err_most = this_err;
828 max_n = clock.n;
829 found = true;
830 }
831 }
832 }
833 }
834 }
835 return found;
836 }
837
838 /*
839 * Check if the calculated PLL configuration is more optimal compared to the
840 * best configuration and error found so far. Return the calculated error.
841 */
842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
843 const struct dpll *calculated_clock,
844 const struct dpll *best_clock,
845 unsigned int best_error_ppm,
846 unsigned int *error_ppm)
847 {
848 /*
849 * For CHV ignore the error and consider only the P value.
850 * Prefer a bigger P value based on HW requirements.
851 */
852 if (IS_CHERRYVIEW(dev)) {
853 *error_ppm = 0;
854
855 return calculated_clock->p > best_clock->p;
856 }
857
858 if (WARN_ON_ONCE(!target_freq))
859 return false;
860
861 *error_ppm = div_u64(1000000ULL *
862 abs(target_freq - calculated_clock->dot),
863 target_freq);
864 /*
865 * Prefer a better P value over a better (smaller) error if the error
866 * is small. Ensure this preference for future configurations too by
867 * setting the error to 0.
868 */
869 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
870 *error_ppm = 0;
871
872 return true;
873 }
874
875 return *error_ppm + 10 < best_error_ppm;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 vlv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 struct dpll clock;
892 unsigned int bestppm = 1000000;
893 /* min update 19.2 MHz */
894 int max_n = min(limit->n.max, refclk / 19200);
895 bool found = false;
896
897 target *= 5; /* fast clock */
898
899 memset(best_clock, 0, sizeof(*best_clock));
900
901 /* based on hardware requirement, prefer smaller n to precision */
902 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
905 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
906 clock.p = clock.p1 * clock.p2;
907 /* based on hardware requirement, prefer bigger m1,m2 values */
908 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
909 unsigned int ppm;
910
911 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
912 refclk * clock.m1);
913
914 vlv_calc_dpll_params(refclk, &clock);
915
916 if (!intel_PLL_is_valid(to_i915(dev),
917 limit,
918 &clock))
919 continue;
920
921 if (!vlv_PLL_is_optimal(dev, target,
922 &clock,
923 best_clock,
924 bestppm, &ppm))
925 continue;
926
927 *best_clock = clock;
928 bestppm = ppm;
929 found = true;
930 }
931 }
932 }
933 }
934
935 return found;
936 }
937
938 /*
939 * Returns a set of divisors for the desired target clock with the given
940 * refclk, or FALSE. The returned values represent the clock equation:
941 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
942 */
943 static bool
944 chv_find_best_dpll(const struct intel_limit *limit,
945 struct intel_crtc_state *crtc_state,
946 int target, int refclk, struct dpll *match_clock,
947 struct dpll *best_clock)
948 {
949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
950 struct drm_device *dev = crtc->base.dev;
951 unsigned int best_error_ppm;
952 struct dpll clock;
953 uint64_t m2;
954 int found = false;
955
956 memset(best_clock, 0, sizeof(*best_clock));
957 best_error_ppm = 1000000;
958
959 /*
960 * Based on hardware doc, the n always set to 1, and m1 always
961 * set to 2. If requires to support 200Mhz refclk, we need to
962 * revisit this because n may not 1 anymore.
963 */
964 clock.n = 1, clock.m1 = 2;
965 target *= 5; /* fast clock */
966
967 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968 for (clock.p2 = limit->p2.p2_fast;
969 clock.p2 >= limit->p2.p2_slow;
970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971 unsigned int error_ppm;
972
973 clock.p = clock.p1 * clock.p2;
974
975 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
976 clock.n) << 22, refclk * clock.m1);
977
978 if (m2 > INT_MAX/clock.m1)
979 continue;
980
981 clock.m2 = m2;
982
983 chv_calc_dpll_params(refclk, &clock);
984
985 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
986 continue;
987
988 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
989 best_error_ppm, &error_ppm))
990 continue;
991
992 *best_clock = clock;
993 best_error_ppm = error_ppm;
994 found = true;
995 }
996 }
997
998 return found;
999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002 struct dpll *best_clock)
1003 {
1004 int refclk = 100000;
1005 const struct intel_limit *limit = &intel_limits_bxt;
1006
1007 return chv_find_best_dpll(limit, crtc_state,
1008 target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct drm_crtc *crtc)
1012 {
1013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1014
1015 /* Be paranoid as we can arrive here with only partial
1016 * state retrieved from the hardware during setup.
1017 *
1018 * We can ditch the adjusted_mode.crtc_clock check as soon
1019 * as Haswell has gained clock readout/fastboot support.
1020 *
1021 * We can ditch the crtc->primary->fb check as soon as we can
1022 * properly reconstruct framebuffers.
1023 *
1024 * FIXME: The intel_crtc->active here should be switched to
1025 * crtc->state->active once we have proper CRTC states wired up
1026 * for atomic.
1027 */
1028 return intel_crtc->active && crtc->primary->state->fb &&
1029 intel_crtc->config->base.adjusted_mode.crtc_clock;
1030 }
1031
1032 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1033 enum pipe pipe)
1034 {
1035 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1037
1038 return intel_crtc->config->cpu_transcoder;
1039 }
1040
1041 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1042 {
1043 struct drm_i915_private *dev_priv = to_i915(dev);
1044 i915_reg_t reg = PIPEDSL(pipe);
1045 u32 line1, line2;
1046 u32 line_mask;
1047
1048 if (IS_GEN2(dev))
1049 line_mask = DSL_LINEMASK_GEN2;
1050 else
1051 line_mask = DSL_LINEMASK_GEN3;
1052
1053 line1 = I915_READ(reg) & line_mask;
1054 msleep(5);
1055 line2 = I915_READ(reg) & line_mask;
1056
1057 return line1 == line2;
1058 }
1059
1060 /*
1061 * intel_wait_for_pipe_off - wait for pipe to turn off
1062 * @crtc: crtc whose pipe to wait for
1063 *
1064 * After disabling a pipe, we can't wait for vblank in the usual way,
1065 * spinning on the vblank interrupt status bit, since we won't actually
1066 * see an interrupt when the pipe is disabled.
1067 *
1068 * On Gen4 and above:
1069 * wait for the pipe register state bit to turn off
1070 *
1071 * Otherwise:
1072 * wait for the display line value to settle (it usually
1073 * ends up stopping at the start of the next frame).
1074 *
1075 */
1076 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1077 {
1078 struct drm_device *dev = crtc->base.dev;
1079 struct drm_i915_private *dev_priv = to_i915(dev);
1080 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1081 enum pipe pipe = crtc->pipe;
1082
1083 if (INTEL_INFO(dev)->gen >= 4) {
1084 i915_reg_t reg = PIPECONF(cpu_transcoder);
1085
1086 /* Wait for the Pipe State to go off */
1087 if (intel_wait_for_register(dev_priv,
1088 reg, I965_PIPECONF_ACTIVE, 0,
1089 100))
1090 WARN(1, "pipe_off wait timed out\n");
1091 } else {
1092 /* Wait for the display line to settle */
1093 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1094 WARN(1, "pipe_off wait timed out\n");
1095 }
1096 }
1097
1098 /* Only for pre-ILK configs */
1099 void assert_pll(struct drm_i915_private *dev_priv,
1100 enum pipe pipe, bool state)
1101 {
1102 u32 val;
1103 bool cur_state;
1104
1105 val = I915_READ(DPLL(pipe));
1106 cur_state = !!(val & DPLL_VCO_ENABLE);
1107 I915_STATE_WARN(cur_state != state,
1108 "PLL state assertion failure (expected %s, current %s)\n",
1109 onoff(state), onoff(cur_state));
1110 }
1111
1112 /* XXX: the dsi pll is shared between MIPI DSI ports */
1113 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1114 {
1115 u32 val;
1116 bool cur_state;
1117
1118 mutex_lock(&dev_priv->sb_lock);
1119 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1120 mutex_unlock(&dev_priv->sb_lock);
1121
1122 cur_state = val & DSI_PLL_VCO_EN;
1123 I915_STATE_WARN(cur_state != state,
1124 "DSI PLL state assertion failure (expected %s, current %s)\n",
1125 onoff(state), onoff(cur_state));
1126 }
1127
1128 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130 {
1131 bool cur_state;
1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133 pipe);
1134
1135 if (HAS_DDI(dev_priv)) {
1136 /* DDI does not have a specific FDI_TX register */
1137 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1138 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1139 } else {
1140 u32 val = I915_READ(FDI_TX_CTL(pipe));
1141 cur_state = !!(val & FDI_TX_ENABLE);
1142 }
1143 I915_STATE_WARN(cur_state != state,
1144 "FDI TX state assertion failure (expected %s, current %s)\n",
1145 onoff(state), onoff(cur_state));
1146 }
1147 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1148 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1149
1150 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1151 enum pipe pipe, bool state)
1152 {
1153 u32 val;
1154 bool cur_state;
1155
1156 val = I915_READ(FDI_RX_CTL(pipe));
1157 cur_state = !!(val & FDI_RX_ENABLE);
1158 I915_STATE_WARN(cur_state != state,
1159 "FDI RX state assertion failure (expected %s, current %s)\n",
1160 onoff(state), onoff(cur_state));
1161 }
1162 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1163 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1164
1165 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 u32 val;
1169
1170 /* ILK FDI PLL is always enabled */
1171 if (IS_GEN5(dev_priv))
1172 return;
1173
1174 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1175 if (HAS_DDI(dev_priv))
1176 return;
1177
1178 val = I915_READ(FDI_TX_CTL(pipe));
1179 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 }
1181
1182 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1183 enum pipe pipe, bool state)
1184 {
1185 u32 val;
1186 bool cur_state;
1187
1188 val = I915_READ(FDI_RX_CTL(pipe));
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 I915_STATE_WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 onoff(state), onoff(cur_state));
1193 }
1194
1195 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1196 {
1197 i915_reg_t pp_reg;
1198 u32 val;
1199 enum pipe panel_pipe = PIPE_A;
1200 bool locked = true;
1201
1202 if (WARN_ON(HAS_DDI(dev_priv)))
1203 return;
1204
1205 if (HAS_PCH_SPLIT(dev_priv)) {
1206 u32 port_sel;
1207
1208 pp_reg = PP_CONTROL(0);
1209 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1210
1211 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1212 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1213 panel_pipe = PIPE_B;
1214 /* XXX: else fix for eDP */
1215 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1216 /* presumably write lock depends on pipe, not port select */
1217 pp_reg = PP_CONTROL(pipe);
1218 panel_pipe = pipe;
1219 } else {
1220 pp_reg = PP_CONTROL(0);
1221 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1222 panel_pipe = PIPE_B;
1223 }
1224
1225 val = I915_READ(pp_reg);
1226 if (!(val & PANEL_POWER_ON) ||
1227 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1228 locked = false;
1229
1230 I915_STATE_WARN(panel_pipe == pipe && locked,
1231 "panel assertion failure, pipe %c regs locked\n",
1232 pipe_name(pipe));
1233 }
1234
1235 static void assert_cursor(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 bool cur_state;
1239
1240 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1241 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1242 else
1243 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1244
1245 I915_STATE_WARN(cur_state != state,
1246 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1247 pipe_name(pipe), onoff(state), onoff(cur_state));
1248 }
1249 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1250 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1251
1252 void assert_pipe(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, bool state)
1254 {
1255 bool cur_state;
1256 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1257 pipe);
1258 enum intel_display_power_domain power_domain;
1259
1260 /* if we need the pipe quirk it must be always on */
1261 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1262 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1263 state = true;
1264
1265 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1266 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1267 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1268 cur_state = !!(val & PIPECONF_ENABLE);
1269
1270 intel_display_power_put(dev_priv, power_domain);
1271 } else {
1272 cur_state = false;
1273 }
1274
1275 I915_STATE_WARN(cur_state != state,
1276 "pipe %c assertion failure (expected %s, current %s)\n",
1277 pipe_name(pipe), onoff(state), onoff(cur_state));
1278 }
1279
1280 static void assert_plane(struct drm_i915_private *dev_priv,
1281 enum plane plane, bool state)
1282 {
1283 u32 val;
1284 bool cur_state;
1285
1286 val = I915_READ(DSPCNTR(plane));
1287 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1288 I915_STATE_WARN(cur_state != state,
1289 "plane %c assertion failure (expected %s, current %s)\n",
1290 plane_name(plane), onoff(state), onoff(cur_state));
1291 }
1292
1293 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1294 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1295
1296 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe)
1298 {
1299 struct drm_device *dev = &dev_priv->drm;
1300 int i;
1301
1302 /* Primary planes are fixed to pipes on gen4+ */
1303 if (INTEL_INFO(dev)->gen >= 4) {
1304 u32 val = I915_READ(DSPCNTR(pipe));
1305 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1306 "plane %c assertion failure, should be disabled but not\n",
1307 plane_name(pipe));
1308 return;
1309 }
1310
1311 /* Need to check both planes against the pipe */
1312 for_each_pipe(dev_priv, i) {
1313 u32 val = I915_READ(DSPCNTR(i));
1314 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1315 DISPPLANE_SEL_PIPE_SHIFT;
1316 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1317 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1318 plane_name(i), pipe_name(pipe));
1319 }
1320 }
1321
1322 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe)
1324 {
1325 struct drm_device *dev = &dev_priv->drm;
1326 int sprite;
1327
1328 if (INTEL_INFO(dev)->gen >= 9) {
1329 for_each_sprite(dev_priv, pipe, sprite) {
1330 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1331 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1332 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1333 sprite, pipe_name(pipe));
1334 }
1335 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1336 for_each_sprite(dev_priv, pipe, sprite) {
1337 u32 val = I915_READ(SPCNTR(pipe, sprite));
1338 I915_STATE_WARN(val & SP_ENABLE,
1339 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340 sprite_name(pipe, sprite), pipe_name(pipe));
1341 }
1342 } else if (INTEL_INFO(dev)->gen >= 7) {
1343 u32 val = I915_READ(SPRCTL(pipe));
1344 I915_STATE_WARN(val & SPRITE_ENABLE,
1345 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1346 plane_name(pipe), pipe_name(pipe));
1347 } else if (INTEL_INFO(dev)->gen >= 5) {
1348 u32 val = I915_READ(DVSCNTR(pipe));
1349 I915_STATE_WARN(val & DVS_ENABLE,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe), pipe_name(pipe));
1352 }
1353 }
1354
1355 static void assert_vblank_disabled(struct drm_crtc *crtc)
1356 {
1357 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1358 drm_crtc_vblank_put(crtc);
1359 }
1360
1361 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1362 enum pipe pipe)
1363 {
1364 u32 val;
1365 bool enabled;
1366
1367 val = I915_READ(PCH_TRANSCONF(pipe));
1368 enabled = !!(val & TRANS_ENABLE);
1369 I915_STATE_WARN(enabled,
1370 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1371 pipe_name(pipe));
1372 }
1373
1374 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1375 enum pipe pipe, u32 port_sel, u32 val)
1376 {
1377 if ((val & DP_PORT_EN) == 0)
1378 return false;
1379
1380 if (HAS_PCH_CPT(dev_priv)) {
1381 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1382 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383 return false;
1384 } else if (IS_CHERRYVIEW(dev_priv)) {
1385 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386 return false;
1387 } else {
1388 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389 return false;
1390 }
1391 return true;
1392 }
1393
1394 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, u32 val)
1396 {
1397 if ((val & SDVO_ENABLE) == 0)
1398 return false;
1399
1400 if (HAS_PCH_CPT(dev_priv)) {
1401 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1402 return false;
1403 } else if (IS_CHERRYVIEW(dev_priv)) {
1404 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405 return false;
1406 } else {
1407 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1408 return false;
1409 }
1410 return true;
1411 }
1412
1413 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 val)
1415 {
1416 if ((val & LVDS_PORT_EN) == 0)
1417 return false;
1418
1419 if (HAS_PCH_CPT(dev_priv)) {
1420 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421 return false;
1422 } else {
1423 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424 return false;
1425 }
1426 return true;
1427 }
1428
1429 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, u32 val)
1431 {
1432 if ((val & ADPA_DAC_ENABLE) == 0)
1433 return false;
1434 if (HAS_PCH_CPT(dev_priv)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439 return false;
1440 }
1441 return true;
1442 }
1443
1444 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, i915_reg_t reg,
1446 u32 port_sel)
1447 {
1448 u32 val = I915_READ(reg);
1449 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1450 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1451 i915_mmio_reg_offset(reg), pipe_name(pipe));
1452
1453 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1454 && (val & DP_PIPEB_SELECT),
1455 "IBX PCH dp port still using transcoder B\n");
1456 }
1457
1458 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe, i915_reg_t reg)
1460 {
1461 u32 val = I915_READ(reg);
1462 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1463 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1464 i915_mmio_reg_offset(reg), pipe_name(pipe));
1465
1466 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1467 && (val & SDVO_PIPE_B_SELECT),
1468 "IBX PCH hdmi port still using transcoder B\n");
1469 }
1470
1471 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1472 enum pipe pipe)
1473 {
1474 u32 val;
1475
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1479
1480 val = I915_READ(PCH_ADPA);
1481 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482 "PCH VGA enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 val = I915_READ(PCH_LVDS);
1486 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1487 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488 pipe_name(pipe));
1489
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1493 }
1494
1495 static void _vlv_enable_pll(struct intel_crtc *crtc,
1496 const struct intel_crtc_state *pipe_config)
1497 {
1498 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1499 enum pipe pipe = crtc->pipe;
1500
1501 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1502 POSTING_READ(DPLL(pipe));
1503 udelay(150);
1504
1505 if (intel_wait_for_register(dev_priv,
1506 DPLL(pipe),
1507 DPLL_LOCK_VLV,
1508 DPLL_LOCK_VLV,
1509 1))
1510 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1511 }
1512
1513 static void vlv_enable_pll(struct intel_crtc *crtc,
1514 const struct intel_crtc_state *pipe_config)
1515 {
1516 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1517 enum pipe pipe = crtc->pipe;
1518
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 /* PLL is protected by panel, make sure we can write it */
1522 assert_panel_unlocked(dev_priv, pipe);
1523
1524 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1525 _vlv_enable_pll(crtc, pipe_config);
1526
1527 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1528 POSTING_READ(DPLL_MD(pipe));
1529 }
1530
1531
1532 static void _chv_enable_pll(struct intel_crtc *crtc,
1533 const struct intel_crtc_state *pipe_config)
1534 {
1535 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536 enum pipe pipe = crtc->pipe;
1537 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1538 u32 tmp;
1539
1540 mutex_lock(&dev_priv->sb_lock);
1541
1542 /* Enable back the 10bit clock to display controller */
1543 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1544 tmp |= DPIO_DCLKP_EN;
1545 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1546
1547 mutex_unlock(&dev_priv->sb_lock);
1548
1549 /*
1550 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1551 */
1552 udelay(1);
1553
1554 /* Enable PLL */
1555 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1556
1557 /* Check PLL is locked */
1558 if (intel_wait_for_register(dev_priv,
1559 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1560 1))
1561 DRM_ERROR("PLL %d failed to lock\n", pipe);
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc,
1565 const struct intel_crtc_state *pipe_config)
1566 {
1567 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568 enum pipe pipe = crtc->pipe;
1569
1570 assert_pipe_disabled(dev_priv, pipe);
1571
1572 /* PLL is protected by panel, make sure we can write it */
1573 assert_panel_unlocked(dev_priv, pipe);
1574
1575 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1576 _chv_enable_pll(crtc, pipe_config);
1577
1578 if (pipe != PIPE_A) {
1579 /*
1580 * WaPixelRepeatModeFixForC0:chv
1581 *
1582 * DPLLCMD is AWOL. Use chicken bits to propagate
1583 * the value from DPLLBMD to either pipe B or C.
1584 */
1585 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1586 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1587 I915_WRITE(CBR4_VLV, 0);
1588 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1589
1590 /*
1591 * DPLLB VGA mode also seems to cause problems.
1592 * We should always have it disabled.
1593 */
1594 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1595 } else {
1596 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1597 POSTING_READ(DPLL_MD(pipe));
1598 }
1599 }
1600
1601 static int intel_num_dvo_pipes(struct drm_device *dev)
1602 {
1603 struct intel_crtc *crtc;
1604 int count = 0;
1605
1606 for_each_intel_crtc(dev, crtc) {
1607 count += crtc->base.state->active &&
1608 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1609 }
1610
1611 return count;
1612 }
1613
1614 static void i9xx_enable_pll(struct intel_crtc *crtc)
1615 {
1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = to_i915(dev);
1618 i915_reg_t reg = DPLL(crtc->pipe);
1619 u32 dpll = crtc->config->dpll_hw_state.dpll;
1620
1621 assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623 /* PLL is protected by panel, make sure we can write it */
1624 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1625 assert_panel_unlocked(dev_priv, crtc->pipe);
1626
1627 /* Enable DVO 2x clock on both PLLs if necessary */
1628 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
1629 /*
1630 * It appears to be important that we don't enable this
1631 * for the current pipe before otherwise configuring the
1632 * PLL. No idea how this should be handled if multiple
1633 * DVO outputs are enabled simultaneosly.
1634 */
1635 dpll |= DPLL_DVO_2X_MODE;
1636 I915_WRITE(DPLL(!crtc->pipe),
1637 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1638 }
1639
1640 /*
1641 * Apparently we need to have VGA mode enabled prior to changing
1642 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1643 * dividers, even though the register value does change.
1644 */
1645 I915_WRITE(reg, 0);
1646
1647 I915_WRITE(reg, dpll);
1648
1649 /* Wait for the clocks to stabilize. */
1650 POSTING_READ(reg);
1651 udelay(150);
1652
1653 if (INTEL_INFO(dev)->gen >= 4) {
1654 I915_WRITE(DPLL_MD(crtc->pipe),
1655 crtc->config->dpll_hw_state.dpll_md);
1656 } else {
1657 /* The pixel multiplier can only be updated once the
1658 * DPLL is enabled and the clocks are stable.
1659 *
1660 * So write it again.
1661 */
1662 I915_WRITE(reg, dpll);
1663 }
1664
1665 /* We do this three times for luck */
1666 I915_WRITE(reg, dpll);
1667 POSTING_READ(reg);
1668 udelay(150); /* wait for warmup */
1669 I915_WRITE(reg, dpll);
1670 POSTING_READ(reg);
1671 udelay(150); /* wait for warmup */
1672 I915_WRITE(reg, dpll);
1673 POSTING_READ(reg);
1674 udelay(150); /* wait for warmup */
1675 }
1676
1677 /**
1678 * i9xx_disable_pll - disable a PLL
1679 * @dev_priv: i915 private structure
1680 * @pipe: pipe PLL to disable
1681 *
1682 * Disable the PLL for @pipe, making sure the pipe is off first.
1683 *
1684 * Note! This is for pre-ILK only.
1685 */
1686 static void i9xx_disable_pll(struct intel_crtc *crtc)
1687 {
1688 struct drm_device *dev = crtc->base.dev;
1689 struct drm_i915_private *dev_priv = to_i915(dev);
1690 enum pipe pipe = crtc->pipe;
1691
1692 /* Disable DVO 2x clock on both PLLs if necessary */
1693 if (IS_I830(dev_priv) &&
1694 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1695 !intel_num_dvo_pipes(dev)) {
1696 I915_WRITE(DPLL(PIPE_B),
1697 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1698 I915_WRITE(DPLL(PIPE_A),
1699 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1700 }
1701
1702 /* Don't disable pipe or pipe PLLs if needed */
1703 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1704 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1705 return;
1706
1707 /* Make sure the pipe isn't still relying on us */
1708 assert_pipe_disabled(dev_priv, pipe);
1709
1710 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1711 POSTING_READ(DPLL(pipe));
1712 }
1713
1714 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1715 {
1716 u32 val;
1717
1718 /* Make sure the pipe isn't still relying on us */
1719 assert_pipe_disabled(dev_priv, pipe);
1720
1721 val = DPLL_INTEGRATED_REF_CLK_VLV |
1722 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1723 if (pipe != PIPE_A)
1724 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1725
1726 I915_WRITE(DPLL(pipe), val);
1727 POSTING_READ(DPLL(pipe));
1728 }
1729
1730 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1731 {
1732 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1733 u32 val;
1734
1735 /* Make sure the pipe isn't still relying on us */
1736 assert_pipe_disabled(dev_priv, pipe);
1737
1738 val = DPLL_SSC_REF_CLK_CHV |
1739 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1740 if (pipe != PIPE_A)
1741 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1742
1743 I915_WRITE(DPLL(pipe), val);
1744 POSTING_READ(DPLL(pipe));
1745
1746 mutex_lock(&dev_priv->sb_lock);
1747
1748 /* Disable 10bit clock to display controller */
1749 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1750 val &= ~DPIO_DCLKP_EN;
1751 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1752
1753 mutex_unlock(&dev_priv->sb_lock);
1754 }
1755
1756 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1757 struct intel_digital_port *dport,
1758 unsigned int expected_mask)
1759 {
1760 u32 port_mask;
1761 i915_reg_t dpll_reg;
1762
1763 switch (dport->port) {
1764 case PORT_B:
1765 port_mask = DPLL_PORTB_READY_MASK;
1766 dpll_reg = DPLL(0);
1767 break;
1768 case PORT_C:
1769 port_mask = DPLL_PORTC_READY_MASK;
1770 dpll_reg = DPLL(0);
1771 expected_mask <<= 4;
1772 break;
1773 case PORT_D:
1774 port_mask = DPLL_PORTD_READY_MASK;
1775 dpll_reg = DPIO_PHY_STATUS;
1776 break;
1777 default:
1778 BUG();
1779 }
1780
1781 if (intel_wait_for_register(dev_priv,
1782 dpll_reg, port_mask, expected_mask,
1783 1000))
1784 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1785 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1786 }
1787
1788 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789 enum pipe pipe)
1790 {
1791 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793 i915_reg_t reg;
1794 uint32_t val, pipeconf_val;
1795
1796 /* Make sure PCH DPLL is enabled */
1797 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1798
1799 /* FDI must be feeding us bits for PCH ports */
1800 assert_fdi_tx_enabled(dev_priv, pipe);
1801 assert_fdi_rx_enabled(dev_priv, pipe);
1802
1803 if (HAS_PCH_CPT(dev_priv)) {
1804 /* Workaround: Set the timing override bit before enabling the
1805 * pch transcoder. */
1806 reg = TRANS_CHICKEN2(pipe);
1807 val = I915_READ(reg);
1808 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809 I915_WRITE(reg, val);
1810 }
1811
1812 reg = PCH_TRANSCONF(pipe);
1813 val = I915_READ(reg);
1814 pipeconf_val = I915_READ(PIPECONF(pipe));
1815
1816 if (HAS_PCH_IBX(dev_priv)) {
1817 /*
1818 * Make the BPC in transcoder be consistent with
1819 * that in pipeconf reg. For HDMI we must use 8bpc
1820 * here for both 8bpc and 12bpc.
1821 */
1822 val &= ~PIPECONF_BPC_MASK;
1823 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1824 val |= PIPECONF_8BPC;
1825 else
1826 val |= pipeconf_val & PIPECONF_BPC_MASK;
1827 }
1828
1829 val &= ~TRANS_INTERLACE_MASK;
1830 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1831 if (HAS_PCH_IBX(dev_priv) &&
1832 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1833 val |= TRANS_LEGACY_INTERLACED_ILK;
1834 else
1835 val |= TRANS_INTERLACED;
1836 else
1837 val |= TRANS_PROGRESSIVE;
1838
1839 I915_WRITE(reg, val | TRANS_ENABLE);
1840 if (intel_wait_for_register(dev_priv,
1841 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1842 100))
1843 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1844 }
1845
1846 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1847 enum transcoder cpu_transcoder)
1848 {
1849 u32 val, pipeconf_val;
1850
1851 /* FDI must be feeding us bits for PCH ports */
1852 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1853 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1854
1855 /* Workaround: set timing override bit. */
1856 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1857 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1859
1860 val = TRANS_ENABLE;
1861 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1862
1863 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1864 PIPECONF_INTERLACED_ILK)
1865 val |= TRANS_INTERLACED;
1866 else
1867 val |= TRANS_PROGRESSIVE;
1868
1869 I915_WRITE(LPT_TRANSCONF, val);
1870 if (intel_wait_for_register(dev_priv,
1871 LPT_TRANSCONF,
1872 TRANS_STATE_ENABLE,
1873 TRANS_STATE_ENABLE,
1874 100))
1875 DRM_ERROR("Failed to enable PCH transcoder\n");
1876 }
1877
1878 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum pipe pipe)
1880 {
1881 i915_reg_t reg;
1882 uint32_t val;
1883
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1890
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1898 50))
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901 if (HAS_PCH_CPT(dev_priv)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1907 }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912 u32 val;
1913
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920 50))
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1932 *
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1943 i915_reg_t reg;
1944 u32 val;
1945
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1951
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = TRANSCODER_A;
1954 else
1955 pch_transcoder = pipe;
1956
1957 /*
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 * need the check.
1961 */
1962 if (HAS_GMCH_DISPLAY(dev_priv)) {
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1965 else
1966 assert_pll_enabled(dev_priv, pipe);
1967 } else {
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1973 }
1974 /* FIXME: assert CPU port conditions for SNB+ */
1975 }
1976
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982 return;
1983 }
1984
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1986 POSTING_READ(reg);
1987
1988 /*
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1994 */
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2003 *
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2007 *
2008 * Will wait until the pipe has shut down before returning.
2009 */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2015 i915_reg_t reg;
2016 u32 val;
2017
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020 /*
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2023 */
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2031 return;
2032
2033 /*
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2036 */
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2044
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2057 {
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2060 return cpp;
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2063 return 128;
2064 else
2065 return 512;
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068 return 128;
2069 else
2070 return 512;
2071 case I915_FORMAT_MOD_Yf_TILED:
2072 switch (cpp) {
2073 case 1:
2074 return 64;
2075 case 2:
2076 case 4:
2077 return 128;
2078 case 8:
2079 case 16:
2080 return 256;
2081 default:
2082 MISSING_CASE(cpp);
2083 return cpp;
2084 }
2085 break;
2086 default:
2087 MISSING_CASE(fb_modifier);
2088 return cpp;
2089 }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2094 {
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096 return 1;
2097 else
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2107 unsigned int cpp)
2108 {
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123 return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128 unsigned int size = 0;
2129 int i;
2130
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134 return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2141 {
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145 } else {
2146 *view = i915_ggtt_view_normal;
2147 }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2153 return 256 * 1024;
2154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156 return 128 * 1024;
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2158 return 4 * 1024;
2159 else
2160 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2165 {
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2171 return 256 * 1024;
2172 return 0;
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2176 default:
2177 MISSING_CASE(fb_modifier);
2178 return 0;
2179 }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185 struct drm_device *dev = fb->dev;
2186 struct drm_i915_private *dev_priv = to_i915(dev);
2187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188 struct i915_ggtt_view view;
2189 struct i915_vma *vma;
2190 u32 alignment;
2191
2192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196 intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198 /* Note that the w/a also requires 64 PTE of padding following the
2199 * bo. We currently fill all unused PTE with the shadow page and so
2200 * we should always have valid PTE following the scanout preventing
2201 * the VT-d warning.
2202 */
2203 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204 alignment = 256 * 1024;
2205
2206 /*
2207 * Global gtt pte registers are special registers which actually forward
2208 * writes to a chunk of system memory. Which means that there is no risk
2209 * that the register values disappear as soon as we call
2210 * intel_runtime_pm_put(), so it is correct to wrap only the
2211 * pin/unpin/fence and not more.
2212 */
2213 intel_runtime_pm_get(dev_priv);
2214
2215 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216 if (IS_ERR(vma))
2217 goto err;
2218
2219 if (i915_vma_is_map_and_fenceable(vma)) {
2220 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221 * fence, whereas 965+ only requires a fence if using
2222 * framebuffer compression. For simplicity, we always, when
2223 * possible, install a fence as the cost is not that onerous.
2224 *
2225 * If we fail to fence the tiled scanout, then either the
2226 * modeset will reject the change (which is highly unlikely as
2227 * the affected systems, all but one, do not have unmappable
2228 * space) or we will not be able to enable full powersaving
2229 * techniques (also likely not to apply due to various limits
2230 * FBC and the like impose on the size of the buffer, which
2231 * presumably we violated anyway with this unmappable buffer).
2232 * Anyway, it is presumably better to stumble onwards with
2233 * something and try to run the system in a "less than optimal"
2234 * mode that matches the user configuration.
2235 */
2236 if (i915_vma_get_fence(vma) == 0)
2237 i915_vma_pin_fence(vma);
2238 }
2239
2240 err:
2241 intel_runtime_pm_put(dev_priv);
2242 return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 struct i915_ggtt_view view;
2249 struct i915_vma *vma;
2250
2251 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253 intel_fill_fb_ggtt_view(&view, fb, rotation);
2254 vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256 i915_vma_unpin_fence(vma);
2257 i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation)
2262 {
2263 if (intel_rotation_90_or_270(rotation))
2264 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265 else
2266 return fb->pitches[plane];
2267 }
2268
2269 /*
2270 * Convert the x/y offsets into a linear offset.
2271 * Only valid with 0/180 degree rotation, which is fine since linear
2272 * offset is only used with linear buffers on pre-hsw and tiled buffers
2273 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274 */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276 const struct intel_plane_state *state,
2277 int plane)
2278 {
2279 const struct drm_framebuffer *fb = state->base.fb;
2280 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281 unsigned int pitch = fb->pitches[plane];
2282
2283 return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287 * Add the x/y offsets derived from fb->offsets[] to the user
2288 * specified plane src x/y offsets. The resulting x/y offsets
2289 * specify the start of scanout from the beginning of the gtt mapping.
2290 */
2291 void intel_add_fb_offsets(int *x, int *y,
2292 const struct intel_plane_state *state,
2293 int plane)
2294
2295 {
2296 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297 unsigned int rotation = state->base.rotation;
2298
2299 if (intel_rotation_90_or_270(rotation)) {
2300 *x += intel_fb->rotated[plane].x;
2301 *y += intel_fb->rotated[plane].y;
2302 } else {
2303 *x += intel_fb->normal[plane].x;
2304 *y += intel_fb->normal[plane].y;
2305 }
2306 }
2307
2308 /*
2309 * Input tile dimensions and pitch must already be
2310 * rotated to match x and y, and in pixel units.
2311 */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313 unsigned int tile_width,
2314 unsigned int tile_height,
2315 unsigned int tile_size,
2316 unsigned int pitch_tiles,
2317 u32 old_offset,
2318 u32 new_offset)
2319 {
2320 unsigned int pitch_pixels = pitch_tiles * tile_width;
2321 unsigned int tiles;
2322
2323 WARN_ON(old_offset & (tile_size - 1));
2324 WARN_ON(new_offset & (tile_size - 1));
2325 WARN_ON(new_offset > old_offset);
2326
2327 tiles = (old_offset - new_offset) / tile_size;
2328
2329 *y += tiles / pitch_tiles * tile_height;
2330 *x += tiles % pitch_tiles * tile_width;
2331
2332 /* minimize x in case it got needlessly big */
2333 *y += *x / pitch_pixels * tile_height;
2334 *x %= pitch_pixels;
2335
2336 return new_offset;
2337 }
2338
2339 /*
2340 * Adjust the tile offset by moving the difference into
2341 * the x/y offsets.
2342 */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344 const struct intel_plane_state *state, int plane,
2345 u32 old_offset, u32 new_offset)
2346 {
2347 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348 const struct drm_framebuffer *fb = state->base.fb;
2349 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350 unsigned int rotation = state->base.rotation;
2351 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353 WARN_ON(new_offset > old_offset);
2354
2355 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361 fb->modifier[plane], cpp);
2362
2363 if (intel_rotation_90_or_270(rotation)) {
2364 pitch_tiles = pitch / tile_height;
2365 swap(tile_width, tile_height);
2366 } else {
2367 pitch_tiles = pitch / (tile_width * cpp);
2368 }
2369
2370 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371 tile_size, pitch_tiles,
2372 old_offset, new_offset);
2373 } else {
2374 old_offset += *y * pitch + *x * cpp;
2375
2376 *y = (old_offset - new_offset) / pitch;
2377 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378 }
2379
2380 return new_offset;
2381 }
2382
2383 /*
2384 * Computes the linear offset to the base tile and adjusts
2385 * x, y. bytes per pixel is assumed to be a power-of-two.
2386 *
2387 * In the 90/270 rotated case, x and y are assumed
2388 * to be already rotated to match the rotated GTT view, and
2389 * pitch is the tile_height aligned framebuffer height.
2390 *
2391 * This function is used when computing the derived information
2392 * under intel_framebuffer, so using any of that information
2393 * here is not allowed. Anything under drm_framebuffer can be
2394 * used. This is why the user has to pass in the pitch since it
2395 * is specified in the rotated orientation.
2396 */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398 int *x, int *y,
2399 const struct drm_framebuffer *fb, int plane,
2400 unsigned int pitch,
2401 unsigned int rotation,
2402 u32 alignment)
2403 {
2404 uint64_t fb_modifier = fb->modifier[plane];
2405 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406 u32 offset, offset_aligned;
2407
2408 if (alignment)
2409 alignment--;
2410
2411 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412 unsigned int tile_size, tile_width, tile_height;
2413 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415 tile_size = intel_tile_size(dev_priv);
2416 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417 fb_modifier, cpp);
2418
2419 if (intel_rotation_90_or_270(rotation)) {
2420 pitch_tiles = pitch / tile_height;
2421 swap(tile_width, tile_height);
2422 } else {
2423 pitch_tiles = pitch / (tile_width * cpp);
2424 }
2425
2426 tile_rows = *y / tile_height;
2427 *y %= tile_height;
2428
2429 tiles = *x / tile_width;
2430 *x %= tile_width;
2431
2432 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433 offset_aligned = offset & ~alignment;
2434
2435 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436 tile_size, pitch_tiles,
2437 offset, offset_aligned);
2438 } else {
2439 offset = *y * pitch + *x * cpp;
2440 offset_aligned = offset & ~alignment;
2441
2442 *y = (offset & alignment) / pitch;
2443 *x = ((offset & alignment) - *y * pitch) / cpp;
2444 }
2445
2446 return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450 const struct intel_plane_state *state,
2451 int plane)
2452 {
2453 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454 const struct drm_framebuffer *fb = state->base.fb;
2455 unsigned int rotation = state->base.rotation;
2456 int pitch = intel_fb_pitch(fb, plane, rotation);
2457 u32 alignment;
2458
2459 /* AUX_DIST needs only 4K alignment */
2460 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461 alignment = 4096;
2462 else
2463 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466 rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471 const struct drm_framebuffer *fb, int plane)
2472 {
2473 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474 unsigned int pitch = fb->pitches[plane];
2475 u32 linear_offset = fb->offsets[plane];
2476
2477 *y = linear_offset / pitch;
2478 *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483 switch (fb_modifier) {
2484 case I915_FORMAT_MOD_X_TILED:
2485 return I915_TILING_X;
2486 case I915_FORMAT_MOD_Y_TILED:
2487 return I915_TILING_Y;
2488 default:
2489 return I915_TILING_NONE;
2490 }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495 struct drm_framebuffer *fb)
2496 {
2497 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499 u32 gtt_offset_rotated = 0;
2500 unsigned int max_size = 0;
2501 uint32_t format = fb->pixel_format;
2502 int i, num_planes = drm_format_num_planes(format);
2503 unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505 for (i = 0; i < num_planes; i++) {
2506 unsigned int width, height;
2507 unsigned int cpp, size;
2508 u32 offset;
2509 int x, y;
2510
2511 cpp = drm_format_plane_cpp(format, i);
2512 width = drm_format_plane_width(fb->width, format, i);
2513 height = drm_format_plane_height(fb->height, format, i);
2514
2515 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517 /*
2518 * The fence (if used) is aligned to the start of the object
2519 * so having the framebuffer wrap around across the edge of the
2520 * fenced region doesn't really work. We have no API to configure
2521 * the fence start offset within the object (nor could we probably
2522 * on gen2/3). So it's just easier if we just require that the
2523 * fb layout agrees with the fence layout. We already check that the
2524 * fb stride matches the fence stride elsewhere.
2525 */
2526 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527 (x + width) * cpp > fb->pitches[i]) {
2528 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529 i, fb->offsets[i]);
2530 return -EINVAL;
2531 }
2532
2533 /*
2534 * First pixel of the framebuffer from
2535 * the start of the normal gtt mapping.
2536 */
2537 intel_fb->normal[i].x = x;
2538 intel_fb->normal[i].y = y;
2539
2540 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541 fb, 0, fb->pitches[i],
2542 DRM_ROTATE_0, tile_size);
2543 offset /= tile_size;
2544
2545 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546 unsigned int tile_width, tile_height;
2547 unsigned int pitch_tiles;
2548 struct drm_rect r;
2549
2550 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551 fb->modifier[i], cpp);
2552
2553 rot_info->plane[i].offset = offset;
2554 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558 intel_fb->rotated[i].pitch =
2559 rot_info->plane[i].height * tile_height;
2560
2561 /* how many tiles does this plane need */
2562 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563 /*
2564 * If the plane isn't horizontally tile aligned,
2565 * we need one more tile.
2566 */
2567 if (x != 0)
2568 size++;
2569
2570 /* rotate the x/y offsets to match the GTT view */
2571 r.x1 = x;
2572 r.y1 = y;
2573 r.x2 = x + width;
2574 r.y2 = y + height;
2575 drm_rect_rotate(&r,
2576 rot_info->plane[i].width * tile_width,
2577 rot_info->plane[i].height * tile_height,
2578 DRM_ROTATE_270);
2579 x = r.x1;
2580 y = r.y1;
2581
2582 /* rotate the tile dimensions to match the GTT view */
2583 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584 swap(tile_width, tile_height);
2585
2586 /*
2587 * We only keep the x/y offsets, so push all of the
2588 * gtt offset into the x/y offsets.
2589 */
2590 _intel_adjust_tile_offset(&x, &y, tile_size,
2591 tile_width, tile_height, pitch_tiles,
2592 gtt_offset_rotated * tile_size, 0);
2593
2594 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596 /*
2597 * First pixel of the framebuffer from
2598 * the start of the rotated gtt mapping.
2599 */
2600 intel_fb->rotated[i].x = x;
2601 intel_fb->rotated[i].y = y;
2602 } else {
2603 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604 x * cpp, tile_size);
2605 }
2606
2607 /* how many tiles in total needed in the bo */
2608 max_size = max(max_size, offset + size);
2609 }
2610
2611 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614 return -EINVAL;
2615 }
2616
2617 return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622 switch (format) {
2623 case DISPPLANE_8BPP:
2624 return DRM_FORMAT_C8;
2625 case DISPPLANE_BGRX555:
2626 return DRM_FORMAT_XRGB1555;
2627 case DISPPLANE_BGRX565:
2628 return DRM_FORMAT_RGB565;
2629 default:
2630 case DISPPLANE_BGRX888:
2631 return DRM_FORMAT_XRGB8888;
2632 case DISPPLANE_RGBX888:
2633 return DRM_FORMAT_XBGR8888;
2634 case DISPPLANE_BGRX101010:
2635 return DRM_FORMAT_XRGB2101010;
2636 case DISPPLANE_RGBX101010:
2637 return DRM_FORMAT_XBGR2101010;
2638 }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643 switch (format) {
2644 case PLANE_CTL_FORMAT_RGB_565:
2645 return DRM_FORMAT_RGB565;
2646 default:
2647 case PLANE_CTL_FORMAT_XRGB_8888:
2648 if (rgb_order) {
2649 if (alpha)
2650 return DRM_FORMAT_ABGR8888;
2651 else
2652 return DRM_FORMAT_XBGR8888;
2653 } else {
2654 if (alpha)
2655 return DRM_FORMAT_ARGB8888;
2656 else
2657 return DRM_FORMAT_XRGB8888;
2658 }
2659 case PLANE_CTL_FORMAT_XRGB_2101010:
2660 if (rgb_order)
2661 return DRM_FORMAT_XBGR2101010;
2662 else
2663 return DRM_FORMAT_XRGB2101010;
2664 }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669 struct intel_initial_plane_config *plane_config)
2670 {
2671 struct drm_device *dev = crtc->base.dev;
2672 struct drm_i915_private *dev_priv = to_i915(dev);
2673 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674 struct drm_i915_gem_object *obj = NULL;
2675 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676 struct drm_framebuffer *fb = &plane_config->fb->base;
2677 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679 PAGE_SIZE);
2680
2681 size_aligned -= base_aligned;
2682
2683 if (plane_config->size == 0)
2684 return false;
2685
2686 /* If the FB is too big, just don't use it since fbdev is not very
2687 * important and we should probably use that space with FBC or other
2688 * features. */
2689 if (size_aligned * 2 > ggtt->stolen_usable_size)
2690 return false;
2691
2692 mutex_lock(&dev->struct_mutex);
2693
2694 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695 base_aligned,
2696 base_aligned,
2697 size_aligned);
2698 if (!obj) {
2699 mutex_unlock(&dev->struct_mutex);
2700 return false;
2701 }
2702
2703 if (plane_config->tiling == I915_TILING_X)
2704 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706 mode_cmd.pixel_format = fb->pixel_format;
2707 mode_cmd.width = fb->width;
2708 mode_cmd.height = fb->height;
2709 mode_cmd.pitches[0] = fb->pitches[0];
2710 mode_cmd.modifier[0] = fb->modifier[0];
2711 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714 &mode_cmd, obj)) {
2715 DRM_DEBUG_KMS("intel fb init failed\n");
2716 goto out_unref_obj;
2717 }
2718
2719 mutex_unlock(&dev->struct_mutex);
2720
2721 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722 return true;
2723
2724 out_unref_obj:
2725 i915_gem_object_put(obj);
2726 mutex_unlock(&dev->struct_mutex);
2727 return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734 if (plane->fb == plane->state->fb)
2735 return;
2736
2737 if (plane->state->fb)
2738 drm_framebuffer_unreference(plane->state->fb);
2739 plane->state->fb = plane->fb;
2740 if (plane->state->fb)
2741 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746 struct intel_initial_plane_config *plane_config)
2747 {
2748 struct drm_device *dev = intel_crtc->base.dev;
2749 struct drm_i915_private *dev_priv = to_i915(dev);
2750 struct drm_crtc *c;
2751 struct intel_crtc *i;
2752 struct drm_i915_gem_object *obj;
2753 struct drm_plane *primary = intel_crtc->base.primary;
2754 struct drm_plane_state *plane_state = primary->state;
2755 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756 struct intel_plane *intel_plane = to_intel_plane(primary);
2757 struct intel_plane_state *intel_state =
2758 to_intel_plane_state(plane_state);
2759 struct drm_framebuffer *fb;
2760
2761 if (!plane_config->fb)
2762 return;
2763
2764 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765 fb = &plane_config->fb->base;
2766 goto valid_fb;
2767 }
2768
2769 kfree(plane_config->fb);
2770
2771 /*
2772 * Failed to alloc the obj, check to see if we should share
2773 * an fb with another CRTC instead
2774 */
2775 for_each_crtc(dev, c) {
2776 i = to_intel_crtc(c);
2777
2778 if (c == &intel_crtc->base)
2779 continue;
2780
2781 if (!i->active)
2782 continue;
2783
2784 fb = c->primary->fb;
2785 if (!fb)
2786 continue;
2787
2788 obj = intel_fb_obj(fb);
2789 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790 drm_framebuffer_reference(fb);
2791 goto valid_fb;
2792 }
2793 }
2794
2795 /*
2796 * We've failed to reconstruct the BIOS FB. Current display state
2797 * indicates that the primary plane is visible, but has a NULL FB,
2798 * which will lead to problems later if we don't fix it up. The
2799 * simplest solution is to just disable the primary plane now and
2800 * pretend the BIOS never had it enabled.
2801 */
2802 to_intel_plane_state(plane_state)->base.visible = false;
2803 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805 intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807 return;
2808
2809 valid_fb:
2810 plane_state->src_x = 0;
2811 plane_state->src_y = 0;
2812 plane_state->src_w = fb->width << 16;
2813 plane_state->src_h = fb->height << 16;
2814
2815 plane_state->crtc_x = 0;
2816 plane_state->crtc_y = 0;
2817 plane_state->crtc_w = fb->width;
2818 plane_state->crtc_h = fb->height;
2819
2820 intel_state->base.src.x1 = plane_state->src_x;
2821 intel_state->base.src.y1 = plane_state->src_y;
2822 intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823 intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824 intel_state->base.dst.x1 = plane_state->crtc_x;
2825 intel_state->base.dst.y1 = plane_state->crtc_y;
2826 intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827 intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829 obj = intel_fb_obj(fb);
2830 if (i915_gem_object_is_tiled(obj))
2831 dev_priv->preserve_bios_swizzle = true;
2832
2833 drm_framebuffer_reference(fb);
2834 primary->fb = primary->state->fb = fb;
2835 primary->crtc = primary->state->crtc = &intel_crtc->base;
2836 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838 &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842 unsigned int rotation)
2843 {
2844 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846 switch (fb->modifier[plane]) {
2847 case DRM_FORMAT_MOD_NONE:
2848 case I915_FORMAT_MOD_X_TILED:
2849 switch (cpp) {
2850 case 8:
2851 return 4096;
2852 case 4:
2853 case 2:
2854 case 1:
2855 return 8192;
2856 default:
2857 MISSING_CASE(cpp);
2858 break;
2859 }
2860 break;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 case I915_FORMAT_MOD_Yf_TILED:
2863 switch (cpp) {
2864 case 8:
2865 return 2048;
2866 case 4:
2867 return 4096;
2868 case 2:
2869 case 1:
2870 return 8192;
2871 default:
2872 MISSING_CASE(cpp);
2873 break;
2874 }
2875 break;
2876 default:
2877 MISSING_CASE(fb->modifier[plane]);
2878 }
2879
2880 return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886 const struct drm_framebuffer *fb = plane_state->base.fb;
2887 unsigned int rotation = plane_state->base.rotation;
2888 int x = plane_state->base.src.x1 >> 16;
2889 int y = plane_state->base.src.y1 >> 16;
2890 int w = drm_rect_width(&plane_state->base.src) >> 16;
2891 int h = drm_rect_height(&plane_state->base.src) >> 16;
2892 int max_width = skl_max_plane_width(fb, 0, rotation);
2893 int max_height = 4096;
2894 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896 if (w > max_width || h > max_height) {
2897 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898 w, h, max_width, max_height);
2899 return -EINVAL;
2900 }
2901
2902 intel_add_fb_offsets(&x, &y, plane_state, 0);
2903 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907 /*
2908 * AUX surface offset is specified as the distance from the
2909 * main surface offset, and it must be non-negative. Make
2910 * sure that is what we will get.
2911 */
2912 if (offset > aux_offset)
2913 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914 offset, aux_offset & ~(alignment - 1));
2915
2916 /*
2917 * When using an X-tiled surface, the plane blows up
2918 * if the x offset + width exceed the stride.
2919 *
2920 * TODO: linear and Y-tiled seem fine, Yf untested,
2921 */
2922 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925 while ((x + w) * cpp > fb->pitches[0]) {
2926 if (offset == 0) {
2927 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928 return -EINVAL;
2929 }
2930
2931 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932 offset, offset - alignment);
2933 }
2934 }
2935
2936 plane_state->main.offset = offset;
2937 plane_state->main.x = x;
2938 plane_state->main.y = y;
2939
2940 return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945 const struct drm_framebuffer *fb = plane_state->base.fb;
2946 unsigned int rotation = plane_state->base.rotation;
2947 int max_width = skl_max_plane_width(fb, 1, rotation);
2948 int max_height = 4096;
2949 int x = plane_state->base.src.x1 >> 17;
2950 int y = plane_state->base.src.y1 >> 17;
2951 int w = drm_rect_width(&plane_state->base.src) >> 17;
2952 int h = drm_rect_height(&plane_state->base.src) >> 17;
2953 u32 offset;
2954
2955 intel_add_fb_offsets(&x, &y, plane_state, 1);
2956 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958 /* FIXME not quite sure how/if these apply to the chroma plane */
2959 if (w > max_width || h > max_height) {
2960 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961 w, h, max_width, max_height);
2962 return -EINVAL;
2963 }
2964
2965 plane_state->aux.offset = offset;
2966 plane_state->aux.x = x;
2967 plane_state->aux.y = y;
2968
2969 return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974 const struct drm_framebuffer *fb = plane_state->base.fb;
2975 unsigned int rotation = plane_state->base.rotation;
2976 int ret;
2977
2978 /* Rotate src coordinates to match rotated GTT view */
2979 if (intel_rotation_90_or_270(rotation))
2980 drm_rect_rotate(&plane_state->base.src,
2981 fb->width, fb->height, DRM_ROTATE_270);
2982
2983 /*
2984 * Handle the AUX surface first since
2985 * the main surface setup depends on it.
2986 */
2987 if (fb->pixel_format == DRM_FORMAT_NV12) {
2988 ret = skl_check_nv12_aux_surface(plane_state);
2989 if (ret)
2990 return ret;
2991 } else {
2992 plane_state->aux.offset = ~0xfff;
2993 plane_state->aux.x = 0;
2994 plane_state->aux.y = 0;
2995 }
2996
2997 ret = skl_check_main_surface(plane_state);
2998 if (ret)
2999 return ret;
3000
3001 return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005 const struct intel_crtc_state *crtc_state,
3006 const struct intel_plane_state *plane_state)
3007 {
3008 struct drm_device *dev = primary->dev;
3009 struct drm_i915_private *dev_priv = to_i915(dev);
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011 struct drm_framebuffer *fb = plane_state->base.fb;
3012 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013 int plane = intel_crtc->plane;
3014 u32 linear_offset;
3015 u32 dspcntr;
3016 i915_reg_t reg = DSPCNTR(plane);
3017 unsigned int rotation = plane_state->base.rotation;
3018 int x = plane_state->base.src.x1 >> 16;
3019 int y = plane_state->base.src.y1 >> 16;
3020
3021 dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023 dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025 if (INTEL_INFO(dev)->gen < 4) {
3026 if (intel_crtc->pipe == PIPE_B)
3027 dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029 /* pipesrc and dspsize control the size that is scaled from,
3030 * which should always be the user's requested size.
3031 */
3032 I915_WRITE(DSPSIZE(plane),
3033 ((crtc_state->pipe_src_h - 1) << 16) |
3034 (crtc_state->pipe_src_w - 1));
3035 I915_WRITE(DSPPOS(plane), 0);
3036 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037 I915_WRITE(PRIMSIZE(plane),
3038 ((crtc_state->pipe_src_h - 1) << 16) |
3039 (crtc_state->pipe_src_w - 1));
3040 I915_WRITE(PRIMPOS(plane), 0);
3041 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042 }
3043
3044 switch (fb->pixel_format) {
3045 case DRM_FORMAT_C8:
3046 dspcntr |= DISPPLANE_8BPP;
3047 break;
3048 case DRM_FORMAT_XRGB1555:
3049 dspcntr |= DISPPLANE_BGRX555;
3050 break;
3051 case DRM_FORMAT_RGB565:
3052 dspcntr |= DISPPLANE_BGRX565;
3053 break;
3054 case DRM_FORMAT_XRGB8888:
3055 dspcntr |= DISPPLANE_BGRX888;
3056 break;
3057 case DRM_FORMAT_XBGR8888:
3058 dspcntr |= DISPPLANE_RGBX888;
3059 break;
3060 case DRM_FORMAT_XRGB2101010:
3061 dspcntr |= DISPPLANE_BGRX101010;
3062 break;
3063 case DRM_FORMAT_XBGR2101010:
3064 dspcntr |= DISPPLANE_RGBX101010;
3065 break;
3066 default:
3067 BUG();
3068 }
3069
3070 if (INTEL_GEN(dev_priv) >= 4 &&
3071 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072 dspcntr |= DISPPLANE_TILED;
3073
3074 if (IS_G4X(dev))
3075 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077 intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079 if (INTEL_INFO(dev)->gen >= 4)
3080 intel_crtc->dspaddr_offset =
3081 intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083 if (rotation == DRM_ROTATE_180) {
3084 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086 x += (crtc_state->pipe_src_w - 1);
3087 y += (crtc_state->pipe_src_h - 1);
3088 }
3089
3090 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092 if (INTEL_INFO(dev)->gen < 4)
3093 intel_crtc->dspaddr_offset = linear_offset;
3094
3095 intel_crtc->adjusted_x = x;
3096 intel_crtc->adjusted_y = y;
3097
3098 I915_WRITE(reg, dspcntr);
3099
3100 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101 if (INTEL_INFO(dev)->gen >= 4) {
3102 I915_WRITE(DSPSURF(plane),
3103 intel_fb_gtt_offset(fb, rotation) +
3104 intel_crtc->dspaddr_offset);
3105 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107 } else
3108 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109 POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113 struct drm_crtc *crtc)
3114 {
3115 struct drm_device *dev = crtc->dev;
3116 struct drm_i915_private *dev_priv = to_i915(dev);
3117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118 int plane = intel_crtc->plane;
3119
3120 I915_WRITE(DSPCNTR(plane), 0);
3121 if (INTEL_INFO(dev_priv)->gen >= 4)
3122 I915_WRITE(DSPSURF(plane), 0);
3123 else
3124 I915_WRITE(DSPADDR(plane), 0);
3125 POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129 const struct intel_crtc_state *crtc_state,
3130 const struct intel_plane_state *plane_state)
3131 {
3132 struct drm_device *dev = primary->dev;
3133 struct drm_i915_private *dev_priv = to_i915(dev);
3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135 struct drm_framebuffer *fb = plane_state->base.fb;
3136 int plane = intel_crtc->plane;
3137 u32 linear_offset;
3138 u32 dspcntr;
3139 i915_reg_t reg = DSPCNTR(plane);
3140 unsigned int rotation = plane_state->base.rotation;
3141 int x = plane_state->base.src.x1 >> 16;
3142 int y = plane_state->base.src.y1 >> 16;
3143
3144 dspcntr = DISPPLANE_GAMMA_ENABLE;
3145 dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3148 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150 switch (fb->pixel_format) {
3151 case DRM_FORMAT_C8:
3152 dspcntr |= DISPPLANE_8BPP;
3153 break;
3154 case DRM_FORMAT_RGB565:
3155 dspcntr |= DISPPLANE_BGRX565;
3156 break;
3157 case DRM_FORMAT_XRGB8888:
3158 dspcntr |= DISPPLANE_BGRX888;
3159 break;
3160 case DRM_FORMAT_XBGR8888:
3161 dspcntr |= DISPPLANE_RGBX888;
3162 break;
3163 case DRM_FORMAT_XRGB2101010:
3164 dspcntr |= DISPPLANE_BGRX101010;
3165 break;
3166 case DRM_FORMAT_XBGR2101010:
3167 dspcntr |= DISPPLANE_RGBX101010;
3168 break;
3169 default:
3170 BUG();
3171 }
3172
3173 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174 dspcntr |= DISPPLANE_TILED;
3175
3176 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3177 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179 intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181 intel_crtc->dspaddr_offset =
3182 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184 if (rotation == DRM_ROTATE_180) {
3185 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3188 x += (crtc_state->pipe_src_w - 1);
3189 y += (crtc_state->pipe_src_h - 1);
3190 }
3191 }
3192
3193 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195 intel_crtc->adjusted_x = x;
3196 intel_crtc->adjusted_y = y;
3197
3198 I915_WRITE(reg, dspcntr);
3199
3200 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201 I915_WRITE(DSPSURF(plane),
3202 intel_fb_gtt_offset(fb, rotation) +
3203 intel_crtc->dspaddr_offset);
3204 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3205 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206 } else {
3207 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209 }
3210 POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214 uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217 return 64;
3218 } else {
3219 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222 }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226 unsigned int rotation)
3227 {
3228 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229 struct i915_ggtt_view view;
3230 struct i915_vma *vma;
3231
3232 intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234 vma = i915_gem_object_to_ggtt(obj, &view);
3235 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236 view.type))
3237 return -1;
3238
3239 return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244 struct drm_device *dev = intel_crtc->base.dev;
3245 struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253 * This function detaches (aka. unbinds) unused scalers in hardware
3254 */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257 struct intel_crtc_scaler_state *scaler_state;
3258 int i;
3259
3260 scaler_state = &intel_crtc->config->scaler_state;
3261
3262 /* loop through and disable scalers that aren't in use */
3263 for (i = 0; i < intel_crtc->num_scalers; i++) {
3264 if (!scaler_state->scalers[i].in_use)
3265 skl_detach_scaler(intel_crtc, i);
3266 }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270 unsigned int rotation)
3271 {
3272 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273 u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275 /*
3276 * The stride is either expressed as a multiple of 64 bytes chunks for
3277 * linear buffers or in number of tiles for tiled buffers.
3278 */
3279 if (intel_rotation_90_or_270(rotation)) {
3280 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283 } else {
3284 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285 fb->pixel_format);
3286 }
3287
3288 return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293 switch (pixel_format) {
3294 case DRM_FORMAT_C8:
3295 return PLANE_CTL_FORMAT_INDEXED;
3296 case DRM_FORMAT_RGB565:
3297 return PLANE_CTL_FORMAT_RGB_565;
3298 case DRM_FORMAT_XBGR8888:
3299 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300 case DRM_FORMAT_XRGB8888:
3301 return PLANE_CTL_FORMAT_XRGB_8888;
3302 /*
3303 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304 * to be already pre-multiplied. We need to add a knob (or a different
3305 * DRM_FORMAT) for user-space to configure that.
3306 */
3307 case DRM_FORMAT_ABGR8888:
3308 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310 case DRM_FORMAT_ARGB8888:
3311 return PLANE_CTL_FORMAT_XRGB_8888 |
3312 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313 case DRM_FORMAT_XRGB2101010:
3314 return PLANE_CTL_FORMAT_XRGB_2101010;
3315 case DRM_FORMAT_XBGR2101010:
3316 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317 case DRM_FORMAT_YUYV:
3318 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319 case DRM_FORMAT_YVYU:
3320 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321 case DRM_FORMAT_UYVY:
3322 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323 case DRM_FORMAT_VYUY:
3324 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325 default:
3326 MISSING_CASE(pixel_format);
3327 }
3328
3329 return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334 switch (fb_modifier) {
3335 case DRM_FORMAT_MOD_NONE:
3336 break;
3337 case I915_FORMAT_MOD_X_TILED:
3338 return PLANE_CTL_TILED_X;
3339 case I915_FORMAT_MOD_Y_TILED:
3340 return PLANE_CTL_TILED_Y;
3341 case I915_FORMAT_MOD_Yf_TILED:
3342 return PLANE_CTL_TILED_YF;
3343 default:
3344 MISSING_CASE(fb_modifier);
3345 }
3346
3347 return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352 switch (rotation) {
3353 case DRM_ROTATE_0:
3354 break;
3355 /*
3356 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357 * while i915 HW rotation is clockwise, thats why this swapping.
3358 */
3359 case DRM_ROTATE_90:
3360 return PLANE_CTL_ROTATE_270;
3361 case DRM_ROTATE_180:
3362 return PLANE_CTL_ROTATE_180;
3363 case DRM_ROTATE_270:
3364 return PLANE_CTL_ROTATE_90;
3365 default:
3366 MISSING_CASE(rotation);
3367 }
3368
3369 return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373 const struct intel_crtc_state *crtc_state,
3374 const struct intel_plane_state *plane_state)
3375 {
3376 struct drm_device *dev = plane->dev;
3377 struct drm_i915_private *dev_priv = to_i915(dev);
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379 struct drm_framebuffer *fb = plane_state->base.fb;
3380 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381 int pipe = intel_crtc->pipe;
3382 u32 plane_ctl;
3383 unsigned int rotation = plane_state->base.rotation;
3384 u32 stride = skl_plane_stride(fb, 0, rotation);
3385 u32 surf_addr = plane_state->main.offset;
3386 int scaler_id = plane_state->scaler_id;
3387 int src_x = plane_state->main.x;
3388 int src_y = plane_state->main.y;
3389 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391 int dst_x = plane_state->base.dst.x1;
3392 int dst_y = plane_state->base.dst.y1;
3393 int dst_w = drm_rect_width(&plane_state->base.dst);
3394 int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396 plane_ctl = PLANE_CTL_ENABLE |
3397 PLANE_CTL_PIPE_GAMMA_ENABLE |
3398 PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403 plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405 /* Sizes are 0 based */
3406 src_w--;
3407 src_h--;
3408 dst_w--;
3409 dst_h--;
3410
3411 intel_crtc->dspaddr_offset = surf_addr;
3412
3413 intel_crtc->adjusted_x = src_x;
3414 intel_crtc->adjusted_y = src_y;
3415
3416 if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3417 skl_write_plane_wm(intel_crtc, wm, 0);
3418
3419 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3420 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3421 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3422 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3423
3424 if (scaler_id >= 0) {
3425 uint32_t ps_ctrl = 0;
3426
3427 WARN_ON(!dst_w || !dst_h);
3428 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3429 crtc_state->scaler_state.scalers[scaler_id].mode;
3430 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3431 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3432 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3433 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3434 I915_WRITE(PLANE_POS(pipe, 0), 0);
3435 } else {
3436 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3437 }
3438
3439 I915_WRITE(PLANE_SURF(pipe, 0),
3440 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3441
3442 POSTING_READ(PLANE_SURF(pipe, 0));
3443 }
3444
3445 static void skylake_disable_primary_plane(struct drm_plane *primary,
3446 struct drm_crtc *crtc)
3447 {
3448 struct drm_device *dev = crtc->dev;
3449 struct drm_i915_private *dev_priv = to_i915(dev);
3450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451 int pipe = intel_crtc->pipe;
3452
3453 /*
3454 * We only populate skl_results on watermark updates, and if the
3455 * plane's visiblity isn't actually changing neither is its watermarks.
3456 */
3457 if (!crtc->primary->state->visible)
3458 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3459
3460 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3461 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3462 POSTING_READ(PLANE_SURF(pipe, 0));
3463 }
3464
3465 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3466 static int
3467 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3468 int x, int y, enum mode_set_atomic state)
3469 {
3470 /* Support for kgdboc is disabled, this needs a major rework. */
3471 DRM_ERROR("legacy panic handler not supported any more.\n");
3472
3473 return -ENODEV;
3474 }
3475
3476 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3477 {
3478 struct intel_crtc *crtc;
3479
3480 for_each_intel_crtc(&dev_priv->drm, crtc)
3481 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3482 }
3483
3484 static void intel_update_primary_planes(struct drm_device *dev)
3485 {
3486 struct drm_crtc *crtc;
3487
3488 for_each_crtc(dev, crtc) {
3489 struct intel_plane *plane = to_intel_plane(crtc->primary);
3490 struct intel_plane_state *plane_state =
3491 to_intel_plane_state(plane->base.state);
3492
3493 if (plane_state->base.visible)
3494 plane->update_plane(&plane->base,
3495 to_intel_crtc_state(crtc->state),
3496 plane_state);
3497 }
3498 }
3499
3500 static int
3501 __intel_display_resume(struct drm_device *dev,
3502 struct drm_atomic_state *state)
3503 {
3504 struct drm_crtc_state *crtc_state;
3505 struct drm_crtc *crtc;
3506 int i, ret;
3507
3508 intel_modeset_setup_hw_state(dev);
3509 i915_redisable_vga(dev);
3510
3511 if (!state)
3512 return 0;
3513
3514 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3515 /*
3516 * Force recalculation even if we restore
3517 * current state. With fast modeset this may not result
3518 * in a modeset when the state is compatible.
3519 */
3520 crtc_state->mode_changed = true;
3521 }
3522
3523 /* ignore any reset values/BIOS leftovers in the WM registers */
3524 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3525
3526 ret = drm_atomic_commit(state);
3527
3528 WARN_ON(ret == -EDEADLK);
3529 return ret;
3530 }
3531
3532 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3533 {
3534 return intel_has_gpu_reset(dev_priv) &&
3535 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3536 }
3537
3538 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3539 {
3540 struct drm_device *dev = &dev_priv->drm;
3541 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3542 struct drm_atomic_state *state;
3543 int ret;
3544
3545 /*
3546 * Need mode_config.mutex so that we don't
3547 * trample ongoing ->detect() and whatnot.
3548 */
3549 mutex_lock(&dev->mode_config.mutex);
3550 drm_modeset_acquire_init(ctx, 0);
3551 while (1) {
3552 ret = drm_modeset_lock_all_ctx(dev, ctx);
3553 if (ret != -EDEADLK)
3554 break;
3555
3556 drm_modeset_backoff(ctx);
3557 }
3558
3559 /* reset doesn't touch the display, but flips might get nuked anyway, */
3560 if (!i915.force_reset_modeset_test &&
3561 !gpu_reset_clobbers_display(dev_priv))
3562 return;
3563
3564 /*
3565 * Disabling the crtcs gracefully seems nicer. Also the
3566 * g33 docs say we should at least disable all the planes.
3567 */
3568 state = drm_atomic_helper_duplicate_state(dev, ctx);
3569 if (IS_ERR(state)) {
3570 ret = PTR_ERR(state);
3571 state = NULL;
3572 DRM_ERROR("Duplicating state failed with %i\n", ret);
3573 goto err;
3574 }
3575
3576 ret = drm_atomic_helper_disable_all(dev, ctx);
3577 if (ret) {
3578 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3579 goto err;
3580 }
3581
3582 dev_priv->modeset_restore_state = state;
3583 state->acquire_ctx = ctx;
3584 return;
3585
3586 err:
3587 drm_atomic_state_free(state);
3588 }
3589
3590 void intel_finish_reset(struct drm_i915_private *dev_priv)
3591 {
3592 struct drm_device *dev = &dev_priv->drm;
3593 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3594 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3595 int ret;
3596
3597 /*
3598 * Flips in the rings will be nuked by the reset,
3599 * so complete all pending flips so that user space
3600 * will get its events and not get stuck.
3601 */
3602 intel_complete_page_flips(dev_priv);
3603
3604 dev_priv->modeset_restore_state = NULL;
3605
3606 /* reset doesn't touch the display */
3607 if (!gpu_reset_clobbers_display(dev_priv)) {
3608 if (!state) {
3609 /*
3610 * Flips in the rings have been nuked by the reset,
3611 * so update the base address of all primary
3612 * planes to the the last fb to make sure we're
3613 * showing the correct fb after a reset.
3614 *
3615 * FIXME: Atomic will make this obsolete since we won't schedule
3616 * CS-based flips (which might get lost in gpu resets) any more.
3617 */
3618 intel_update_primary_planes(dev);
3619 } else {
3620 ret = __intel_display_resume(dev, state);
3621 if (ret)
3622 DRM_ERROR("Restoring old state failed with %i\n", ret);
3623 }
3624 } else {
3625 /*
3626 * The display has been reset as well,
3627 * so need a full re-initialization.
3628 */
3629 intel_runtime_pm_disable_interrupts(dev_priv);
3630 intel_runtime_pm_enable_interrupts(dev_priv);
3631
3632 intel_pps_unlock_regs_wa(dev_priv);
3633 intel_modeset_init_hw(dev);
3634
3635 spin_lock_irq(&dev_priv->irq_lock);
3636 if (dev_priv->display.hpd_irq_setup)
3637 dev_priv->display.hpd_irq_setup(dev_priv);
3638 spin_unlock_irq(&dev_priv->irq_lock);
3639
3640 ret = __intel_display_resume(dev, state);
3641 if (ret)
3642 DRM_ERROR("Restoring old state failed with %i\n", ret);
3643
3644 intel_hpd_init(dev_priv);
3645 }
3646
3647 drm_modeset_drop_locks(ctx);
3648 drm_modeset_acquire_fini(ctx);
3649 mutex_unlock(&dev->mode_config.mutex);
3650 }
3651
3652 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3653 {
3654 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3655
3656 if (i915_reset_in_progress(error))
3657 return true;
3658
3659 if (crtc->reset_count != i915_reset_count(error))
3660 return true;
3661
3662 return false;
3663 }
3664
3665 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3666 {
3667 struct drm_device *dev = crtc->dev;
3668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3669 bool pending;
3670
3671 if (abort_flip_on_reset(intel_crtc))
3672 return false;
3673
3674 spin_lock_irq(&dev->event_lock);
3675 pending = to_intel_crtc(crtc)->flip_work != NULL;
3676 spin_unlock_irq(&dev->event_lock);
3677
3678 return pending;
3679 }
3680
3681 static void intel_update_pipe_config(struct intel_crtc *crtc,
3682 struct intel_crtc_state *old_crtc_state)
3683 {
3684 struct drm_device *dev = crtc->base.dev;
3685 struct drm_i915_private *dev_priv = to_i915(dev);
3686 struct intel_crtc_state *pipe_config =
3687 to_intel_crtc_state(crtc->base.state);
3688
3689 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3690 crtc->base.mode = crtc->base.state->mode;
3691
3692 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3693 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3694 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3695
3696 /*
3697 * Update pipe size and adjust fitter if needed: the reason for this is
3698 * that in compute_mode_changes we check the native mode (not the pfit
3699 * mode) to see if we can flip rather than do a full mode set. In the
3700 * fastboot case, we'll flip, but if we don't update the pipesrc and
3701 * pfit state, we'll end up with a big fb scanned out into the wrong
3702 * sized surface.
3703 */
3704
3705 I915_WRITE(PIPESRC(crtc->pipe),
3706 ((pipe_config->pipe_src_w - 1) << 16) |
3707 (pipe_config->pipe_src_h - 1));
3708
3709 /* on skylake this is done by detaching scalers */
3710 if (INTEL_INFO(dev)->gen >= 9) {
3711 skl_detach_scalers(crtc);
3712
3713 if (pipe_config->pch_pfit.enabled)
3714 skylake_pfit_enable(crtc);
3715 } else if (HAS_PCH_SPLIT(dev_priv)) {
3716 if (pipe_config->pch_pfit.enabled)
3717 ironlake_pfit_enable(crtc);
3718 else if (old_crtc_state->pch_pfit.enabled)
3719 ironlake_pfit_disable(crtc, true);
3720 }
3721 }
3722
3723 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3724 {
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = to_i915(dev);
3727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728 int pipe = intel_crtc->pipe;
3729 i915_reg_t reg;
3730 u32 temp;
3731
3732 /* enable normal train */
3733 reg = FDI_TX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 if (IS_IVYBRIDGE(dev_priv)) {
3736 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3737 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3738 } else {
3739 temp &= ~FDI_LINK_TRAIN_NONE;
3740 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3741 }
3742 I915_WRITE(reg, temp);
3743
3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 if (HAS_PCH_CPT(dev_priv)) {
3747 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3748 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3749 } else {
3750 temp &= ~FDI_LINK_TRAIN_NONE;
3751 temp |= FDI_LINK_TRAIN_NONE;
3752 }
3753 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3754
3755 /* wait one idle pattern time */
3756 POSTING_READ(reg);
3757 udelay(1000);
3758
3759 /* IVB wants error correction enabled */
3760 if (IS_IVYBRIDGE(dev_priv))
3761 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3762 FDI_FE_ERRC_ENABLE);
3763 }
3764
3765 /* The FDI link training functions for ILK/Ibexpeak. */
3766 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3767 {
3768 struct drm_device *dev = crtc->dev;
3769 struct drm_i915_private *dev_priv = to_i915(dev);
3770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3771 int pipe = intel_crtc->pipe;
3772 i915_reg_t reg;
3773 u32 temp, tries;
3774
3775 /* FDI needs bits from pipe first */
3776 assert_pipe_enabled(dev_priv, pipe);
3777
3778 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3779 for train result */
3780 reg = FDI_RX_IMR(pipe);
3781 temp = I915_READ(reg);
3782 temp &= ~FDI_RX_SYMBOL_LOCK;
3783 temp &= ~FDI_RX_BIT_LOCK;
3784 I915_WRITE(reg, temp);
3785 I915_READ(reg);
3786 udelay(150);
3787
3788 /* enable CPU FDI TX and PCH FDI RX */
3789 reg = FDI_TX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3792 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3793 temp &= ~FDI_LINK_TRAIN_NONE;
3794 temp |= FDI_LINK_TRAIN_PATTERN_1;
3795 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3796
3797 reg = FDI_RX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 temp &= ~FDI_LINK_TRAIN_NONE;
3800 temp |= FDI_LINK_TRAIN_PATTERN_1;
3801 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3802
3803 POSTING_READ(reg);
3804 udelay(150);
3805
3806 /* Ironlake workaround, enable clock pointer after FDI enable*/
3807 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3808 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3809 FDI_RX_PHASE_SYNC_POINTER_EN);
3810
3811 reg = FDI_RX_IIR(pipe);
3812 for (tries = 0; tries < 5; tries++) {
3813 temp = I915_READ(reg);
3814 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3815
3816 if ((temp & FDI_RX_BIT_LOCK)) {
3817 DRM_DEBUG_KMS("FDI train 1 done.\n");
3818 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3819 break;
3820 }
3821 }
3822 if (tries == 5)
3823 DRM_ERROR("FDI train 1 fail!\n");
3824
3825 /* Train 2 */
3826 reg = FDI_TX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 temp &= ~FDI_LINK_TRAIN_NONE;
3829 temp |= FDI_LINK_TRAIN_PATTERN_2;
3830 I915_WRITE(reg, temp);
3831
3832 reg = FDI_RX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_2;
3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(150);
3840
3841 reg = FDI_RX_IIR(pipe);
3842 for (tries = 0; tries < 5; tries++) {
3843 temp = I915_READ(reg);
3844 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3845
3846 if (temp & FDI_RX_SYMBOL_LOCK) {
3847 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3848 DRM_DEBUG_KMS("FDI train 2 done.\n");
3849 break;
3850 }
3851 }
3852 if (tries == 5)
3853 DRM_ERROR("FDI train 2 fail!\n");
3854
3855 DRM_DEBUG_KMS("FDI train done\n");
3856
3857 }
3858
3859 static const int snb_b_fdi_train_param[] = {
3860 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3861 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3862 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3863 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3864 };
3865
3866 /* The FDI link training functions for SNB/Cougarpoint. */
3867 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3868 {
3869 struct drm_device *dev = crtc->dev;
3870 struct drm_i915_private *dev_priv = to_i915(dev);
3871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872 int pipe = intel_crtc->pipe;
3873 i915_reg_t reg;
3874 u32 temp, i, retry;
3875
3876 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3877 for train result */
3878 reg = FDI_RX_IMR(pipe);
3879 temp = I915_READ(reg);
3880 temp &= ~FDI_RX_SYMBOL_LOCK;
3881 temp &= ~FDI_RX_BIT_LOCK;
3882 I915_WRITE(reg, temp);
3883
3884 POSTING_READ(reg);
3885 udelay(150);
3886
3887 /* enable CPU FDI TX and PCH FDI RX */
3888 reg = FDI_TX_CTL(pipe);
3889 temp = I915_READ(reg);
3890 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3891 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3892 temp &= ~FDI_LINK_TRAIN_NONE;
3893 temp |= FDI_LINK_TRAIN_PATTERN_1;
3894 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3895 /* SNB-B */
3896 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3897 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3898
3899 I915_WRITE(FDI_RX_MISC(pipe),
3900 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3901
3902 reg = FDI_RX_CTL(pipe);
3903 temp = I915_READ(reg);
3904 if (HAS_PCH_CPT(dev_priv)) {
3905 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3906 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3907 } else {
3908 temp &= ~FDI_LINK_TRAIN_NONE;
3909 temp |= FDI_LINK_TRAIN_PATTERN_1;
3910 }
3911 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3912
3913 POSTING_READ(reg);
3914 udelay(150);
3915
3916 for (i = 0; i < 4; i++) {
3917 reg = FDI_TX_CTL(pipe);
3918 temp = I915_READ(reg);
3919 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3920 temp |= snb_b_fdi_train_param[i];
3921 I915_WRITE(reg, temp);
3922
3923 POSTING_READ(reg);
3924 udelay(500);
3925
3926 for (retry = 0; retry < 5; retry++) {
3927 reg = FDI_RX_IIR(pipe);
3928 temp = I915_READ(reg);
3929 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3930 if (temp & FDI_RX_BIT_LOCK) {
3931 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3932 DRM_DEBUG_KMS("FDI train 1 done.\n");
3933 break;
3934 }
3935 udelay(50);
3936 }
3937 if (retry < 5)
3938 break;
3939 }
3940 if (i == 4)
3941 DRM_ERROR("FDI train 1 fail!\n");
3942
3943 /* Train 2 */
3944 reg = FDI_TX_CTL(pipe);
3945 temp = I915_READ(reg);
3946 temp &= ~FDI_LINK_TRAIN_NONE;
3947 temp |= FDI_LINK_TRAIN_PATTERN_2;
3948 if (IS_GEN6(dev)) {
3949 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3950 /* SNB-B */
3951 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3952 }
3953 I915_WRITE(reg, temp);
3954
3955 reg = FDI_RX_CTL(pipe);
3956 temp = I915_READ(reg);
3957 if (HAS_PCH_CPT(dev_priv)) {
3958 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3959 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3960 } else {
3961 temp &= ~FDI_LINK_TRAIN_NONE;
3962 temp |= FDI_LINK_TRAIN_PATTERN_2;
3963 }
3964 I915_WRITE(reg, temp);
3965
3966 POSTING_READ(reg);
3967 udelay(150);
3968
3969 for (i = 0; i < 4; i++) {
3970 reg = FDI_TX_CTL(pipe);
3971 temp = I915_READ(reg);
3972 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3973 temp |= snb_b_fdi_train_param[i];
3974 I915_WRITE(reg, temp);
3975
3976 POSTING_READ(reg);
3977 udelay(500);
3978
3979 for (retry = 0; retry < 5; retry++) {
3980 reg = FDI_RX_IIR(pipe);
3981 temp = I915_READ(reg);
3982 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3983 if (temp & FDI_RX_SYMBOL_LOCK) {
3984 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3985 DRM_DEBUG_KMS("FDI train 2 done.\n");
3986 break;
3987 }
3988 udelay(50);
3989 }
3990 if (retry < 5)
3991 break;
3992 }
3993 if (i == 4)
3994 DRM_ERROR("FDI train 2 fail!\n");
3995
3996 DRM_DEBUG_KMS("FDI train done.\n");
3997 }
3998
3999 /* Manual link training for Ivy Bridge A0 parts */
4000 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4001 {
4002 struct drm_device *dev = crtc->dev;
4003 struct drm_i915_private *dev_priv = to_i915(dev);
4004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4005 int pipe = intel_crtc->pipe;
4006 i915_reg_t reg;
4007 u32 temp, i, j;
4008
4009 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4010 for train result */
4011 reg = FDI_RX_IMR(pipe);
4012 temp = I915_READ(reg);
4013 temp &= ~FDI_RX_SYMBOL_LOCK;
4014 temp &= ~FDI_RX_BIT_LOCK;
4015 I915_WRITE(reg, temp);
4016
4017 POSTING_READ(reg);
4018 udelay(150);
4019
4020 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4021 I915_READ(FDI_RX_IIR(pipe)));
4022
4023 /* Try each vswing and preemphasis setting twice before moving on */
4024 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4025 /* disable first in case we need to retry */
4026 reg = FDI_TX_CTL(pipe);
4027 temp = I915_READ(reg);
4028 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4029 temp &= ~FDI_TX_ENABLE;
4030 I915_WRITE(reg, temp);
4031
4032 reg = FDI_RX_CTL(pipe);
4033 temp = I915_READ(reg);
4034 temp &= ~FDI_LINK_TRAIN_AUTO;
4035 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4036 temp &= ~FDI_RX_ENABLE;
4037 I915_WRITE(reg, temp);
4038
4039 /* enable CPU FDI TX and PCH FDI RX */
4040 reg = FDI_TX_CTL(pipe);
4041 temp = I915_READ(reg);
4042 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4043 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4044 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4045 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4046 temp |= snb_b_fdi_train_param[j/2];
4047 temp |= FDI_COMPOSITE_SYNC;
4048 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4049
4050 I915_WRITE(FDI_RX_MISC(pipe),
4051 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4052
4053 reg = FDI_RX_CTL(pipe);
4054 temp = I915_READ(reg);
4055 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4056 temp |= FDI_COMPOSITE_SYNC;
4057 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4058
4059 POSTING_READ(reg);
4060 udelay(1); /* should be 0.5us */
4061
4062 for (i = 0; i < 4; i++) {
4063 reg = FDI_RX_IIR(pipe);
4064 temp = I915_READ(reg);
4065 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4066
4067 if (temp & FDI_RX_BIT_LOCK ||
4068 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4069 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4070 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4071 i);
4072 break;
4073 }
4074 udelay(1); /* should be 0.5us */
4075 }
4076 if (i == 4) {
4077 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4078 continue;
4079 }
4080
4081 /* Train 2 */
4082 reg = FDI_TX_CTL(pipe);
4083 temp = I915_READ(reg);
4084 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4085 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4086 I915_WRITE(reg, temp);
4087
4088 reg = FDI_RX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4091 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4092 I915_WRITE(reg, temp);
4093
4094 POSTING_READ(reg);
4095 udelay(2); /* should be 1.5us */
4096
4097 for (i = 0; i < 4; i++) {
4098 reg = FDI_RX_IIR(pipe);
4099 temp = I915_READ(reg);
4100 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4101
4102 if (temp & FDI_RX_SYMBOL_LOCK ||
4103 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4104 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4105 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4106 i);
4107 goto train_done;
4108 }
4109 udelay(2); /* should be 1.5us */
4110 }
4111 if (i == 4)
4112 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4113 }
4114
4115 train_done:
4116 DRM_DEBUG_KMS("FDI train done.\n");
4117 }
4118
4119 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4120 {
4121 struct drm_device *dev = intel_crtc->base.dev;
4122 struct drm_i915_private *dev_priv = to_i915(dev);
4123 int pipe = intel_crtc->pipe;
4124 i915_reg_t reg;
4125 u32 temp;
4126
4127 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4128 reg = FDI_RX_CTL(pipe);
4129 temp = I915_READ(reg);
4130 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4131 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4132 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4133 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4134
4135 POSTING_READ(reg);
4136 udelay(200);
4137
4138 /* Switch from Rawclk to PCDclk */
4139 temp = I915_READ(reg);
4140 I915_WRITE(reg, temp | FDI_PCDCLK);
4141
4142 POSTING_READ(reg);
4143 udelay(200);
4144
4145 /* Enable CPU FDI TX PLL, always on for Ironlake */
4146 reg = FDI_TX_CTL(pipe);
4147 temp = I915_READ(reg);
4148 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4149 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4150
4151 POSTING_READ(reg);
4152 udelay(100);
4153 }
4154 }
4155
4156 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4157 {
4158 struct drm_device *dev = intel_crtc->base.dev;
4159 struct drm_i915_private *dev_priv = to_i915(dev);
4160 int pipe = intel_crtc->pipe;
4161 i915_reg_t reg;
4162 u32 temp;
4163
4164 /* Switch from PCDclk to Rawclk */
4165 reg = FDI_RX_CTL(pipe);
4166 temp = I915_READ(reg);
4167 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4168
4169 /* Disable CPU FDI TX PLL */
4170 reg = FDI_TX_CTL(pipe);
4171 temp = I915_READ(reg);
4172 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4173
4174 POSTING_READ(reg);
4175 udelay(100);
4176
4177 reg = FDI_RX_CTL(pipe);
4178 temp = I915_READ(reg);
4179 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4180
4181 /* Wait for the clocks to turn off. */
4182 POSTING_READ(reg);
4183 udelay(100);
4184 }
4185
4186 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4187 {
4188 struct drm_device *dev = crtc->dev;
4189 struct drm_i915_private *dev_priv = to_i915(dev);
4190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191 int pipe = intel_crtc->pipe;
4192 i915_reg_t reg;
4193 u32 temp;
4194
4195 /* disable CPU FDI tx and PCH FDI rx */
4196 reg = FDI_TX_CTL(pipe);
4197 temp = I915_READ(reg);
4198 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4199 POSTING_READ(reg);
4200
4201 reg = FDI_RX_CTL(pipe);
4202 temp = I915_READ(reg);
4203 temp &= ~(0x7 << 16);
4204 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4205 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4206
4207 POSTING_READ(reg);
4208 udelay(100);
4209
4210 /* Ironlake workaround, disable clock pointer after downing FDI */
4211 if (HAS_PCH_IBX(dev_priv))
4212 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4213
4214 /* still set train pattern 1 */
4215 reg = FDI_TX_CTL(pipe);
4216 temp = I915_READ(reg);
4217 temp &= ~FDI_LINK_TRAIN_NONE;
4218 temp |= FDI_LINK_TRAIN_PATTERN_1;
4219 I915_WRITE(reg, temp);
4220
4221 reg = FDI_RX_CTL(pipe);
4222 temp = I915_READ(reg);
4223 if (HAS_PCH_CPT(dev_priv)) {
4224 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4225 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4226 } else {
4227 temp &= ~FDI_LINK_TRAIN_NONE;
4228 temp |= FDI_LINK_TRAIN_PATTERN_1;
4229 }
4230 /* BPC in FDI rx is consistent with that in PIPECONF */
4231 temp &= ~(0x07 << 16);
4232 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4233 I915_WRITE(reg, temp);
4234
4235 POSTING_READ(reg);
4236 udelay(100);
4237 }
4238
4239 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4240 {
4241 struct intel_crtc *crtc;
4242
4243 /* Note that we don't need to be called with mode_config.lock here
4244 * as our list of CRTC objects is static for the lifetime of the
4245 * device and so cannot disappear as we iterate. Similarly, we can
4246 * happily treat the predicates as racy, atomic checks as userspace
4247 * cannot claim and pin a new fb without at least acquring the
4248 * struct_mutex and so serialising with us.
4249 */
4250 for_each_intel_crtc(dev, crtc) {
4251 if (atomic_read(&crtc->unpin_work_count) == 0)
4252 continue;
4253
4254 if (crtc->flip_work)
4255 intel_wait_for_vblank(dev, crtc->pipe);
4256
4257 return true;
4258 }
4259
4260 return false;
4261 }
4262
4263 static void page_flip_completed(struct intel_crtc *intel_crtc)
4264 {
4265 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4266 struct intel_flip_work *work = intel_crtc->flip_work;
4267
4268 intel_crtc->flip_work = NULL;
4269
4270 if (work->event)
4271 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4272
4273 drm_crtc_vblank_put(&intel_crtc->base);
4274
4275 wake_up_all(&dev_priv->pending_flip_queue);
4276 queue_work(dev_priv->wq, &work->unpin_work);
4277
4278 trace_i915_flip_complete(intel_crtc->plane,
4279 work->pending_flip_obj);
4280 }
4281
4282 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4283 {
4284 struct drm_device *dev = crtc->dev;
4285 struct drm_i915_private *dev_priv = to_i915(dev);
4286 long ret;
4287
4288 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4289
4290 ret = wait_event_interruptible_timeout(
4291 dev_priv->pending_flip_queue,
4292 !intel_crtc_has_pending_flip(crtc),
4293 60*HZ);
4294
4295 if (ret < 0)
4296 return ret;
4297
4298 if (ret == 0) {
4299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4300 struct intel_flip_work *work;
4301
4302 spin_lock_irq(&dev->event_lock);
4303 work = intel_crtc->flip_work;
4304 if (work && !is_mmio_work(work)) {
4305 WARN_ONCE(1, "Removing stuck page flip\n");
4306 page_flip_completed(intel_crtc);
4307 }
4308 spin_unlock_irq(&dev->event_lock);
4309 }
4310
4311 return 0;
4312 }
4313
4314 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4315 {
4316 u32 temp;
4317
4318 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4319
4320 mutex_lock(&dev_priv->sb_lock);
4321
4322 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4323 temp |= SBI_SSCCTL_DISABLE;
4324 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4325
4326 mutex_unlock(&dev_priv->sb_lock);
4327 }
4328
4329 /* Program iCLKIP clock to the desired frequency */
4330 static void lpt_program_iclkip(struct drm_crtc *crtc)
4331 {
4332 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4333 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4334 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4335 u32 temp;
4336
4337 lpt_disable_iclkip(dev_priv);
4338
4339 /* The iCLK virtual clock root frequency is in MHz,
4340 * but the adjusted_mode->crtc_clock in in KHz. To get the
4341 * divisors, it is necessary to divide one by another, so we
4342 * convert the virtual clock precision to KHz here for higher
4343 * precision.
4344 */
4345 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4346 u32 iclk_virtual_root_freq = 172800 * 1000;
4347 u32 iclk_pi_range = 64;
4348 u32 desired_divisor;
4349
4350 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4351 clock << auxdiv);
4352 divsel = (desired_divisor / iclk_pi_range) - 2;
4353 phaseinc = desired_divisor % iclk_pi_range;
4354
4355 /*
4356 * Near 20MHz is a corner case which is
4357 * out of range for the 7-bit divisor
4358 */
4359 if (divsel <= 0x7f)
4360 break;
4361 }
4362
4363 /* This should not happen with any sane values */
4364 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4365 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4366 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4367 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4368
4369 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4370 clock,
4371 auxdiv,
4372 divsel,
4373 phasedir,
4374 phaseinc);
4375
4376 mutex_lock(&dev_priv->sb_lock);
4377
4378 /* Program SSCDIVINTPHASE6 */
4379 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4380 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4381 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4382 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4383 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4384 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4385 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4386 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4387
4388 /* Program SSCAUXDIV */
4389 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4390 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4391 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4392 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4393
4394 /* Enable modulator and associated divider */
4395 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4396 temp &= ~SBI_SSCCTL_DISABLE;
4397 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4398
4399 mutex_unlock(&dev_priv->sb_lock);
4400
4401 /* Wait for initialization time */
4402 udelay(24);
4403
4404 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4405 }
4406
4407 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4408 {
4409 u32 divsel, phaseinc, auxdiv;
4410 u32 iclk_virtual_root_freq = 172800 * 1000;
4411 u32 iclk_pi_range = 64;
4412 u32 desired_divisor;
4413 u32 temp;
4414
4415 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4416 return 0;
4417
4418 mutex_lock(&dev_priv->sb_lock);
4419
4420 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4421 if (temp & SBI_SSCCTL_DISABLE) {
4422 mutex_unlock(&dev_priv->sb_lock);
4423 return 0;
4424 }
4425
4426 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4427 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4428 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4429 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4430 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4431
4432 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4433 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4434 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4435
4436 mutex_unlock(&dev_priv->sb_lock);
4437
4438 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4439
4440 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4441 desired_divisor << auxdiv);
4442 }
4443
4444 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4445 enum pipe pch_transcoder)
4446 {
4447 struct drm_device *dev = crtc->base.dev;
4448 struct drm_i915_private *dev_priv = to_i915(dev);
4449 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4450
4451 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4452 I915_READ(HTOTAL(cpu_transcoder)));
4453 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4454 I915_READ(HBLANK(cpu_transcoder)));
4455 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4456 I915_READ(HSYNC(cpu_transcoder)));
4457
4458 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4459 I915_READ(VTOTAL(cpu_transcoder)));
4460 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4461 I915_READ(VBLANK(cpu_transcoder)));
4462 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4463 I915_READ(VSYNC(cpu_transcoder)));
4464 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4465 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4466 }
4467
4468 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4469 {
4470 struct drm_i915_private *dev_priv = to_i915(dev);
4471 uint32_t temp;
4472
4473 temp = I915_READ(SOUTH_CHICKEN1);
4474 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4475 return;
4476
4477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4479
4480 temp &= ~FDI_BC_BIFURCATION_SELECT;
4481 if (enable)
4482 temp |= FDI_BC_BIFURCATION_SELECT;
4483
4484 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4485 I915_WRITE(SOUTH_CHICKEN1, temp);
4486 POSTING_READ(SOUTH_CHICKEN1);
4487 }
4488
4489 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4490 {
4491 struct drm_device *dev = intel_crtc->base.dev;
4492
4493 switch (intel_crtc->pipe) {
4494 case PIPE_A:
4495 break;
4496 case PIPE_B:
4497 if (intel_crtc->config->fdi_lanes > 2)
4498 cpt_set_fdi_bc_bifurcation(dev, false);
4499 else
4500 cpt_set_fdi_bc_bifurcation(dev, true);
4501
4502 break;
4503 case PIPE_C:
4504 cpt_set_fdi_bc_bifurcation(dev, true);
4505
4506 break;
4507 default:
4508 BUG();
4509 }
4510 }
4511
4512 /* Return which DP Port should be selected for Transcoder DP control */
4513 static enum port
4514 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4515 {
4516 struct drm_device *dev = crtc->dev;
4517 struct intel_encoder *encoder;
4518
4519 for_each_encoder_on_crtc(dev, crtc, encoder) {
4520 if (encoder->type == INTEL_OUTPUT_DP ||
4521 encoder->type == INTEL_OUTPUT_EDP)
4522 return enc_to_dig_port(&encoder->base)->port;
4523 }
4524
4525 return -1;
4526 }
4527
4528 /*
4529 * Enable PCH resources required for PCH ports:
4530 * - PCH PLLs
4531 * - FDI training & RX/TX
4532 * - update transcoder timings
4533 * - DP transcoding bits
4534 * - transcoder
4535 */
4536 static void ironlake_pch_enable(struct drm_crtc *crtc)
4537 {
4538 struct drm_device *dev = crtc->dev;
4539 struct drm_i915_private *dev_priv = to_i915(dev);
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 int pipe = intel_crtc->pipe;
4542 u32 temp;
4543
4544 assert_pch_transcoder_disabled(dev_priv, pipe);
4545
4546 if (IS_IVYBRIDGE(dev_priv))
4547 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4548
4549 /* Write the TU size bits before fdi link training, so that error
4550 * detection works. */
4551 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4552 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4553
4554 /* For PCH output, training FDI link */
4555 dev_priv->display.fdi_link_train(crtc);
4556
4557 /* We need to program the right clock selection before writing the pixel
4558 * mutliplier into the DPLL. */
4559 if (HAS_PCH_CPT(dev_priv)) {
4560 u32 sel;
4561
4562 temp = I915_READ(PCH_DPLL_SEL);
4563 temp |= TRANS_DPLL_ENABLE(pipe);
4564 sel = TRANS_DPLLB_SEL(pipe);
4565 if (intel_crtc->config->shared_dpll ==
4566 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4567 temp |= sel;
4568 else
4569 temp &= ~sel;
4570 I915_WRITE(PCH_DPLL_SEL, temp);
4571 }
4572
4573 /* XXX: pch pll's can be enabled any time before we enable the PCH
4574 * transcoder, and we actually should do this to not upset any PCH
4575 * transcoder that already use the clock when we share it.
4576 *
4577 * Note that enable_shared_dpll tries to do the right thing, but
4578 * get_shared_dpll unconditionally resets the pll - we need that to have
4579 * the right LVDS enable sequence. */
4580 intel_enable_shared_dpll(intel_crtc);
4581
4582 /* set transcoder timing, panel must allow it */
4583 assert_panel_unlocked(dev_priv, pipe);
4584 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4585
4586 intel_fdi_normal_train(crtc);
4587
4588 /* For PCH DP, enable TRANS_DP_CTL */
4589 if (HAS_PCH_CPT(dev_priv) &&
4590 intel_crtc_has_dp_encoder(intel_crtc->config)) {
4591 const struct drm_display_mode *adjusted_mode =
4592 &intel_crtc->config->base.adjusted_mode;
4593 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4594 i915_reg_t reg = TRANS_DP_CTL(pipe);
4595 temp = I915_READ(reg);
4596 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4597 TRANS_DP_SYNC_MASK |
4598 TRANS_DP_BPC_MASK);
4599 temp |= TRANS_DP_OUTPUT_ENABLE;
4600 temp |= bpc << 9; /* same format but at 11:9 */
4601
4602 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4603 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4604 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4605 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4606
4607 switch (intel_trans_dp_port_sel(crtc)) {
4608 case PORT_B:
4609 temp |= TRANS_DP_PORT_SEL_B;
4610 break;
4611 case PORT_C:
4612 temp |= TRANS_DP_PORT_SEL_C;
4613 break;
4614 case PORT_D:
4615 temp |= TRANS_DP_PORT_SEL_D;
4616 break;
4617 default:
4618 BUG();
4619 }
4620
4621 I915_WRITE(reg, temp);
4622 }
4623
4624 ironlake_enable_pch_transcoder(dev_priv, pipe);
4625 }
4626
4627 static void lpt_pch_enable(struct drm_crtc *crtc)
4628 {
4629 struct drm_device *dev = crtc->dev;
4630 struct drm_i915_private *dev_priv = to_i915(dev);
4631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4633
4634 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4635
4636 lpt_program_iclkip(crtc);
4637
4638 /* Set transcoder timing. */
4639 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4640
4641 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4642 }
4643
4644 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4645 {
4646 struct drm_i915_private *dev_priv = to_i915(dev);
4647 i915_reg_t dslreg = PIPEDSL(pipe);
4648 u32 temp;
4649
4650 temp = I915_READ(dslreg);
4651 udelay(500);
4652 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4653 if (wait_for(I915_READ(dslreg) != temp, 5))
4654 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4655 }
4656 }
4657
4658 static int
4659 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4660 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4661 int src_w, int src_h, int dst_w, int dst_h)
4662 {
4663 struct intel_crtc_scaler_state *scaler_state =
4664 &crtc_state->scaler_state;
4665 struct intel_crtc *intel_crtc =
4666 to_intel_crtc(crtc_state->base.crtc);
4667 int need_scaling;
4668
4669 need_scaling = intel_rotation_90_or_270(rotation) ?
4670 (src_h != dst_w || src_w != dst_h):
4671 (src_w != dst_w || src_h != dst_h);
4672
4673 /*
4674 * if plane is being disabled or scaler is no more required or force detach
4675 * - free scaler binded to this plane/crtc
4676 * - in order to do this, update crtc->scaler_usage
4677 *
4678 * Here scaler state in crtc_state is set free so that
4679 * scaler can be assigned to other user. Actual register
4680 * update to free the scaler is done in plane/panel-fit programming.
4681 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4682 */
4683 if (force_detach || !need_scaling) {
4684 if (*scaler_id >= 0) {
4685 scaler_state->scaler_users &= ~(1 << scaler_user);
4686 scaler_state->scalers[*scaler_id].in_use = 0;
4687
4688 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4689 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4690 intel_crtc->pipe, scaler_user, *scaler_id,
4691 scaler_state->scaler_users);
4692 *scaler_id = -1;
4693 }
4694 return 0;
4695 }
4696
4697 /* range checks */
4698 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4699 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4700
4701 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4702 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4703 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4704 "size is out of scaler range\n",
4705 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4706 return -EINVAL;
4707 }
4708
4709 /* mark this plane as a scaler user in crtc_state */
4710 scaler_state->scaler_users |= (1 << scaler_user);
4711 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4712 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4713 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4714 scaler_state->scaler_users);
4715
4716 return 0;
4717 }
4718
4719 /**
4720 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4721 *
4722 * @state: crtc's scaler state
4723 *
4724 * Return
4725 * 0 - scaler_usage updated successfully
4726 * error - requested scaling cannot be supported or other error condition
4727 */
4728 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4729 {
4730 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4731 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4732
4733 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4734 intel_crtc->base.base.id, intel_crtc->base.name,
4735 intel_crtc->pipe, SKL_CRTC_INDEX);
4736
4737 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4738 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4739 state->pipe_src_w, state->pipe_src_h,
4740 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4741 }
4742
4743 /**
4744 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4745 *
4746 * @state: crtc's scaler state
4747 * @plane_state: atomic plane state to update
4748 *
4749 * Return
4750 * 0 - scaler_usage updated successfully
4751 * error - requested scaling cannot be supported or other error condition
4752 */
4753 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4754 struct intel_plane_state *plane_state)
4755 {
4756
4757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4758 struct intel_plane *intel_plane =
4759 to_intel_plane(plane_state->base.plane);
4760 struct drm_framebuffer *fb = plane_state->base.fb;
4761 int ret;
4762
4763 bool force_detach = !fb || !plane_state->base.visible;
4764
4765 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4766 intel_plane->base.base.id, intel_plane->base.name,
4767 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4768
4769 ret = skl_update_scaler(crtc_state, force_detach,
4770 drm_plane_index(&intel_plane->base),
4771 &plane_state->scaler_id,
4772 plane_state->base.rotation,
4773 drm_rect_width(&plane_state->base.src) >> 16,
4774 drm_rect_height(&plane_state->base.src) >> 16,
4775 drm_rect_width(&plane_state->base.dst),
4776 drm_rect_height(&plane_state->base.dst));
4777
4778 if (ret || plane_state->scaler_id < 0)
4779 return ret;
4780
4781 /* check colorkey */
4782 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4783 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4784 intel_plane->base.base.id,
4785 intel_plane->base.name);
4786 return -EINVAL;
4787 }
4788
4789 /* Check src format */
4790 switch (fb->pixel_format) {
4791 case DRM_FORMAT_RGB565:
4792 case DRM_FORMAT_XBGR8888:
4793 case DRM_FORMAT_XRGB8888:
4794 case DRM_FORMAT_ABGR8888:
4795 case DRM_FORMAT_ARGB8888:
4796 case DRM_FORMAT_XRGB2101010:
4797 case DRM_FORMAT_XBGR2101010:
4798 case DRM_FORMAT_YUYV:
4799 case DRM_FORMAT_YVYU:
4800 case DRM_FORMAT_UYVY:
4801 case DRM_FORMAT_VYUY:
4802 break;
4803 default:
4804 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4805 intel_plane->base.base.id, intel_plane->base.name,
4806 fb->base.id, fb->pixel_format);
4807 return -EINVAL;
4808 }
4809
4810 return 0;
4811 }
4812
4813 static void skylake_scaler_disable(struct intel_crtc *crtc)
4814 {
4815 int i;
4816
4817 for (i = 0; i < crtc->num_scalers; i++)
4818 skl_detach_scaler(crtc, i);
4819 }
4820
4821 static void skylake_pfit_enable(struct intel_crtc *crtc)
4822 {
4823 struct drm_device *dev = crtc->base.dev;
4824 struct drm_i915_private *dev_priv = to_i915(dev);
4825 int pipe = crtc->pipe;
4826 struct intel_crtc_scaler_state *scaler_state =
4827 &crtc->config->scaler_state;
4828
4829 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4830
4831 if (crtc->config->pch_pfit.enabled) {
4832 int id;
4833
4834 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4835 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4836 return;
4837 }
4838
4839 id = scaler_state->scaler_id;
4840 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4841 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4842 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4843 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4844
4845 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4846 }
4847 }
4848
4849 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4850 {
4851 struct drm_device *dev = crtc->base.dev;
4852 struct drm_i915_private *dev_priv = to_i915(dev);
4853 int pipe = crtc->pipe;
4854
4855 if (crtc->config->pch_pfit.enabled) {
4856 /* Force use of hard-coded filter coefficients
4857 * as some pre-programmed values are broken,
4858 * e.g. x201.
4859 */
4860 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4861 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4862 PF_PIPE_SEL_IVB(pipe));
4863 else
4864 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4865 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4866 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4867 }
4868 }
4869
4870 void hsw_enable_ips(struct intel_crtc *crtc)
4871 {
4872 struct drm_device *dev = crtc->base.dev;
4873 struct drm_i915_private *dev_priv = to_i915(dev);
4874
4875 if (!crtc->config->ips_enabled)
4876 return;
4877
4878 /*
4879 * We can only enable IPS after we enable a plane and wait for a vblank
4880 * This function is called from post_plane_update, which is run after
4881 * a vblank wait.
4882 */
4883
4884 assert_plane_enabled(dev_priv, crtc->plane);
4885 if (IS_BROADWELL(dev_priv)) {
4886 mutex_lock(&dev_priv->rps.hw_lock);
4887 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4888 mutex_unlock(&dev_priv->rps.hw_lock);
4889 /* Quoting Art Runyan: "its not safe to expect any particular
4890 * value in IPS_CTL bit 31 after enabling IPS through the
4891 * mailbox." Moreover, the mailbox may return a bogus state,
4892 * so we need to just enable it and continue on.
4893 */
4894 } else {
4895 I915_WRITE(IPS_CTL, IPS_ENABLE);
4896 /* The bit only becomes 1 in the next vblank, so this wait here
4897 * is essentially intel_wait_for_vblank. If we don't have this
4898 * and don't wait for vblanks until the end of crtc_enable, then
4899 * the HW state readout code will complain that the expected
4900 * IPS_CTL value is not the one we read. */
4901 if (intel_wait_for_register(dev_priv,
4902 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4903 50))
4904 DRM_ERROR("Timed out waiting for IPS enable\n");
4905 }
4906 }
4907
4908 void hsw_disable_ips(struct intel_crtc *crtc)
4909 {
4910 struct drm_device *dev = crtc->base.dev;
4911 struct drm_i915_private *dev_priv = to_i915(dev);
4912
4913 if (!crtc->config->ips_enabled)
4914 return;
4915
4916 assert_plane_enabled(dev_priv, crtc->plane);
4917 if (IS_BROADWELL(dev_priv)) {
4918 mutex_lock(&dev_priv->rps.hw_lock);
4919 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4920 mutex_unlock(&dev_priv->rps.hw_lock);
4921 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4922 if (intel_wait_for_register(dev_priv,
4923 IPS_CTL, IPS_ENABLE, 0,
4924 42))
4925 DRM_ERROR("Timed out waiting for IPS disable\n");
4926 } else {
4927 I915_WRITE(IPS_CTL, 0);
4928 POSTING_READ(IPS_CTL);
4929 }
4930
4931 /* We need to wait for a vblank before we can disable the plane. */
4932 intel_wait_for_vblank(dev, crtc->pipe);
4933 }
4934
4935 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4936 {
4937 if (intel_crtc->overlay) {
4938 struct drm_device *dev = intel_crtc->base.dev;
4939 struct drm_i915_private *dev_priv = to_i915(dev);
4940
4941 mutex_lock(&dev->struct_mutex);
4942 dev_priv->mm.interruptible = false;
4943 (void) intel_overlay_switch_off(intel_crtc->overlay);
4944 dev_priv->mm.interruptible = true;
4945 mutex_unlock(&dev->struct_mutex);
4946 }
4947
4948 /* Let userspace switch the overlay on again. In most cases userspace
4949 * has to recompute where to put it anyway.
4950 */
4951 }
4952
4953 /**
4954 * intel_post_enable_primary - Perform operations after enabling primary plane
4955 * @crtc: the CRTC whose primary plane was just enabled
4956 *
4957 * Performs potentially sleeping operations that must be done after the primary
4958 * plane is enabled, such as updating FBC and IPS. Note that this may be
4959 * called due to an explicit primary plane update, or due to an implicit
4960 * re-enable that is caused when a sprite plane is updated to no longer
4961 * completely hide the primary plane.
4962 */
4963 static void
4964 intel_post_enable_primary(struct drm_crtc *crtc)
4965 {
4966 struct drm_device *dev = crtc->dev;
4967 struct drm_i915_private *dev_priv = to_i915(dev);
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969 int pipe = intel_crtc->pipe;
4970
4971 /*
4972 * FIXME IPS should be fine as long as one plane is
4973 * enabled, but in practice it seems to have problems
4974 * when going from primary only to sprite only and vice
4975 * versa.
4976 */
4977 hsw_enable_ips(intel_crtc);
4978
4979 /*
4980 * Gen2 reports pipe underruns whenever all planes are disabled.
4981 * So don't enable underrun reporting before at least some planes
4982 * are enabled.
4983 * FIXME: Need to fix the logic to work when we turn off all planes
4984 * but leave the pipe running.
4985 */
4986 if (IS_GEN2(dev))
4987 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
4989 /* Underruns don't always raise interrupts, so check manually. */
4990 intel_check_cpu_fifo_underruns(dev_priv);
4991 intel_check_pch_fifo_underruns(dev_priv);
4992 }
4993
4994 /* FIXME move all this to pre_plane_update() with proper state tracking */
4995 static void
4996 intel_pre_disable_primary(struct drm_crtc *crtc)
4997 {
4998 struct drm_device *dev = crtc->dev;
4999 struct drm_i915_private *dev_priv = to_i915(dev);
5000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001 int pipe = intel_crtc->pipe;
5002
5003 /*
5004 * Gen2 reports pipe underruns whenever all planes are disabled.
5005 * So diasble underrun reporting before all the planes get disabled.
5006 * FIXME: Need to fix the logic to work when we turn off all planes
5007 * but leave the pipe running.
5008 */
5009 if (IS_GEN2(dev))
5010 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5011
5012 /*
5013 * FIXME IPS should be fine as long as one plane is
5014 * enabled, but in practice it seems to have problems
5015 * when going from primary only to sprite only and vice
5016 * versa.
5017 */
5018 hsw_disable_ips(intel_crtc);
5019 }
5020
5021 /* FIXME get rid of this and use pre_plane_update */
5022 static void
5023 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5024 {
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = to_i915(dev);
5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 int pipe = intel_crtc->pipe;
5029
5030 intel_pre_disable_primary(crtc);
5031
5032 /*
5033 * Vblank time updates from the shadow to live plane control register
5034 * are blocked if the memory self-refresh mode is active at that
5035 * moment. So to make sure the plane gets truly disabled, disable
5036 * first the self-refresh mode. The self-refresh enable bit in turn
5037 * will be checked/applied by the HW only at the next frame start
5038 * event which is after the vblank start event, so we need to have a
5039 * wait-for-vblank between disabling the plane and the pipe.
5040 */
5041 if (HAS_GMCH_DISPLAY(dev_priv)) {
5042 intel_set_memory_cxsr(dev_priv, false);
5043 dev_priv->wm.vlv.cxsr = false;
5044 intel_wait_for_vblank(dev, pipe);
5045 }
5046 }
5047
5048 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5049 {
5050 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5051 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5052 struct intel_crtc_state *pipe_config =
5053 to_intel_crtc_state(crtc->base.state);
5054 struct drm_plane *primary = crtc->base.primary;
5055 struct drm_plane_state *old_pri_state =
5056 drm_atomic_get_existing_plane_state(old_state, primary);
5057
5058 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5059
5060 crtc->wm.cxsr_allowed = true;
5061
5062 if (pipe_config->update_wm_post && pipe_config->base.active)
5063 intel_update_watermarks(&crtc->base);
5064
5065 if (old_pri_state) {
5066 struct intel_plane_state *primary_state =
5067 to_intel_plane_state(primary->state);
5068 struct intel_plane_state *old_primary_state =
5069 to_intel_plane_state(old_pri_state);
5070
5071 intel_fbc_post_update(crtc);
5072
5073 if (primary_state->base.visible &&
5074 (needs_modeset(&pipe_config->base) ||
5075 !old_primary_state->base.visible))
5076 intel_post_enable_primary(&crtc->base);
5077 }
5078 }
5079
5080 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5081 {
5082 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5083 struct drm_device *dev = crtc->base.dev;
5084 struct drm_i915_private *dev_priv = to_i915(dev);
5085 struct intel_crtc_state *pipe_config =
5086 to_intel_crtc_state(crtc->base.state);
5087 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5088 struct drm_plane *primary = crtc->base.primary;
5089 struct drm_plane_state *old_pri_state =
5090 drm_atomic_get_existing_plane_state(old_state, primary);
5091 bool modeset = needs_modeset(&pipe_config->base);
5092
5093 if (old_pri_state) {
5094 struct intel_plane_state *primary_state =
5095 to_intel_plane_state(primary->state);
5096 struct intel_plane_state *old_primary_state =
5097 to_intel_plane_state(old_pri_state);
5098
5099 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5100
5101 if (old_primary_state->base.visible &&
5102 (modeset || !primary_state->base.visible))
5103 intel_pre_disable_primary(&crtc->base);
5104 }
5105
5106 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5107 crtc->wm.cxsr_allowed = false;
5108
5109 /*
5110 * Vblank time updates from the shadow to live plane control register
5111 * are blocked if the memory self-refresh mode is active at that
5112 * moment. So to make sure the plane gets truly disabled, disable
5113 * first the self-refresh mode. The self-refresh enable bit in turn
5114 * will be checked/applied by the HW only at the next frame start
5115 * event which is after the vblank start event, so we need to have a
5116 * wait-for-vblank between disabling the plane and the pipe.
5117 */
5118 if (old_crtc_state->base.active) {
5119 intel_set_memory_cxsr(dev_priv, false);
5120 dev_priv->wm.vlv.cxsr = false;
5121 intel_wait_for_vblank(dev, crtc->pipe);
5122 }
5123 }
5124
5125 /*
5126 * IVB workaround: must disable low power watermarks for at least
5127 * one frame before enabling scaling. LP watermarks can be re-enabled
5128 * when scaling is disabled.
5129 *
5130 * WaCxSRDisabledForSpriteScaling:ivb
5131 */
5132 if (pipe_config->disable_lp_wm) {
5133 ilk_disable_lp_wm(dev);
5134 intel_wait_for_vblank(dev, crtc->pipe);
5135 }
5136
5137 /*
5138 * If we're doing a modeset, we're done. No need to do any pre-vblank
5139 * watermark programming here.
5140 */
5141 if (needs_modeset(&pipe_config->base))
5142 return;
5143
5144 /*
5145 * For platforms that support atomic watermarks, program the
5146 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5147 * will be the intermediate values that are safe for both pre- and
5148 * post- vblank; when vblank happens, the 'active' values will be set
5149 * to the final 'target' values and we'll do this again to get the
5150 * optimal watermarks. For gen9+ platforms, the values we program here
5151 * will be the final target values which will get automatically latched
5152 * at vblank time; no further programming will be necessary.
5153 *
5154 * If a platform hasn't been transitioned to atomic watermarks yet,
5155 * we'll continue to update watermarks the old way, if flags tell
5156 * us to.
5157 */
5158 if (dev_priv->display.initial_watermarks != NULL)
5159 dev_priv->display.initial_watermarks(pipe_config);
5160 else if (pipe_config->update_wm_pre)
5161 intel_update_watermarks(&crtc->base);
5162 }
5163
5164 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5165 {
5166 struct drm_device *dev = crtc->dev;
5167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168 struct drm_plane *p;
5169 int pipe = intel_crtc->pipe;
5170
5171 intel_crtc_dpms_overlay_disable(intel_crtc);
5172
5173 drm_for_each_plane_mask(p, dev, plane_mask)
5174 to_intel_plane(p)->disable_plane(p, crtc);
5175
5176 /*
5177 * FIXME: Once we grow proper nuclear flip support out of this we need
5178 * to compute the mask of flip planes precisely. For the time being
5179 * consider this a flip to a NULL plane.
5180 */
5181 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5182 }
5183
5184 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5185 struct intel_crtc_state *crtc_state,
5186 struct drm_atomic_state *old_state)
5187 {
5188 struct drm_connector_state *old_conn_state;
5189 struct drm_connector *conn;
5190 int i;
5191
5192 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5193 struct drm_connector_state *conn_state = conn->state;
5194 struct intel_encoder *encoder =
5195 to_intel_encoder(conn_state->best_encoder);
5196
5197 if (conn_state->crtc != crtc)
5198 continue;
5199
5200 if (encoder->pre_pll_enable)
5201 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5202 }
5203 }
5204
5205 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5206 struct intel_crtc_state *crtc_state,
5207 struct drm_atomic_state *old_state)
5208 {
5209 struct drm_connector_state *old_conn_state;
5210 struct drm_connector *conn;
5211 int i;
5212
5213 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5214 struct drm_connector_state *conn_state = conn->state;
5215 struct intel_encoder *encoder =
5216 to_intel_encoder(conn_state->best_encoder);
5217
5218 if (conn_state->crtc != crtc)
5219 continue;
5220
5221 if (encoder->pre_enable)
5222 encoder->pre_enable(encoder, crtc_state, conn_state);
5223 }
5224 }
5225
5226 static void intel_encoders_enable(struct drm_crtc *crtc,
5227 struct intel_crtc_state *crtc_state,
5228 struct drm_atomic_state *old_state)
5229 {
5230 struct drm_connector_state *old_conn_state;
5231 struct drm_connector *conn;
5232 int i;
5233
5234 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5235 struct drm_connector_state *conn_state = conn->state;
5236 struct intel_encoder *encoder =
5237 to_intel_encoder(conn_state->best_encoder);
5238
5239 if (conn_state->crtc != crtc)
5240 continue;
5241
5242 encoder->enable(encoder, crtc_state, conn_state);
5243 intel_opregion_notify_encoder(encoder, true);
5244 }
5245 }
5246
5247 static void intel_encoders_disable(struct drm_crtc *crtc,
5248 struct intel_crtc_state *old_crtc_state,
5249 struct drm_atomic_state *old_state)
5250 {
5251 struct drm_connector_state *old_conn_state;
5252 struct drm_connector *conn;
5253 int i;
5254
5255 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5256 struct intel_encoder *encoder =
5257 to_intel_encoder(old_conn_state->best_encoder);
5258
5259 if (old_conn_state->crtc != crtc)
5260 continue;
5261
5262 intel_opregion_notify_encoder(encoder, false);
5263 encoder->disable(encoder, old_crtc_state, old_conn_state);
5264 }
5265 }
5266
5267 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5268 struct intel_crtc_state *old_crtc_state,
5269 struct drm_atomic_state *old_state)
5270 {
5271 struct drm_connector_state *old_conn_state;
5272 struct drm_connector *conn;
5273 int i;
5274
5275 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5276 struct intel_encoder *encoder =
5277 to_intel_encoder(old_conn_state->best_encoder);
5278
5279 if (old_conn_state->crtc != crtc)
5280 continue;
5281
5282 if (encoder->post_disable)
5283 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5284 }
5285 }
5286
5287 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5288 struct intel_crtc_state *old_crtc_state,
5289 struct drm_atomic_state *old_state)
5290 {
5291 struct drm_connector_state *old_conn_state;
5292 struct drm_connector *conn;
5293 int i;
5294
5295 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5296 struct intel_encoder *encoder =
5297 to_intel_encoder(old_conn_state->best_encoder);
5298
5299 if (old_conn_state->crtc != crtc)
5300 continue;
5301
5302 if (encoder->post_pll_disable)
5303 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5304 }
5305 }
5306
5307 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5308 struct drm_atomic_state *old_state)
5309 {
5310 struct drm_crtc *crtc = pipe_config->base.crtc;
5311 struct drm_device *dev = crtc->dev;
5312 struct drm_i915_private *dev_priv = to_i915(dev);
5313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314 int pipe = intel_crtc->pipe;
5315
5316 if (WARN_ON(intel_crtc->active))
5317 return;
5318
5319 /*
5320 * Sometimes spurious CPU pipe underruns happen during FDI
5321 * training, at least with VGA+HDMI cloning. Suppress them.
5322 *
5323 * On ILK we get an occasional spurious CPU pipe underruns
5324 * between eDP port A enable and vdd enable. Also PCH port
5325 * enable seems to result in the occasional CPU pipe underrun.
5326 *
5327 * Spurious PCH underruns also occur during PCH enabling.
5328 */
5329 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5330 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5331 if (intel_crtc->config->has_pch_encoder)
5332 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5333
5334 if (intel_crtc->config->has_pch_encoder)
5335 intel_prepare_shared_dpll(intel_crtc);
5336
5337 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338 intel_dp_set_m_n(intel_crtc, M1_N1);
5339
5340 intel_set_pipe_timings(intel_crtc);
5341 intel_set_pipe_src_size(intel_crtc);
5342
5343 if (intel_crtc->config->has_pch_encoder) {
5344 intel_cpu_transcoder_set_m_n(intel_crtc,
5345 &intel_crtc->config->fdi_m_n, NULL);
5346 }
5347
5348 ironlake_set_pipeconf(crtc);
5349
5350 intel_crtc->active = true;
5351
5352 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5353
5354 if (intel_crtc->config->has_pch_encoder) {
5355 /* Note: FDI PLL enabling _must_ be done before we enable the
5356 * cpu pipes, hence this is separate from all the other fdi/pch
5357 * enabling. */
5358 ironlake_fdi_pll_enable(intel_crtc);
5359 } else {
5360 assert_fdi_tx_disabled(dev_priv, pipe);
5361 assert_fdi_rx_disabled(dev_priv, pipe);
5362 }
5363
5364 ironlake_pfit_enable(intel_crtc);
5365
5366 /*
5367 * On ILK+ LUT must be loaded before the pipe is running but with
5368 * clocks enabled
5369 */
5370 intel_color_load_luts(&pipe_config->base);
5371
5372 if (dev_priv->display.initial_watermarks != NULL)
5373 dev_priv->display.initial_watermarks(intel_crtc->config);
5374 intel_enable_pipe(intel_crtc);
5375
5376 if (intel_crtc->config->has_pch_encoder)
5377 ironlake_pch_enable(crtc);
5378
5379 assert_vblank_disabled(crtc);
5380 drm_crtc_vblank_on(crtc);
5381
5382 intel_encoders_enable(crtc, pipe_config, old_state);
5383
5384 if (HAS_PCH_CPT(dev_priv))
5385 cpt_verify_modeset(dev, intel_crtc->pipe);
5386
5387 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5388 if (intel_crtc->config->has_pch_encoder)
5389 intel_wait_for_vblank(dev, pipe);
5390 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5391 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5392 }
5393
5394 /* IPS only exists on ULT machines and is tied to pipe A. */
5395 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5396 {
5397 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5398 }
5399
5400 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5401 struct drm_atomic_state *old_state)
5402 {
5403 struct drm_crtc *crtc = pipe_config->base.crtc;
5404 struct drm_device *dev = crtc->dev;
5405 struct drm_i915_private *dev_priv = to_i915(dev);
5406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5408 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5409
5410 if (WARN_ON(intel_crtc->active))
5411 return;
5412
5413 if (intel_crtc->config->has_pch_encoder)
5414 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5415 false);
5416
5417 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5418
5419 if (intel_crtc->config->shared_dpll)
5420 intel_enable_shared_dpll(intel_crtc);
5421
5422 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5423 intel_dp_set_m_n(intel_crtc, M1_N1);
5424
5425 if (!transcoder_is_dsi(cpu_transcoder))
5426 intel_set_pipe_timings(intel_crtc);
5427
5428 intel_set_pipe_src_size(intel_crtc);
5429
5430 if (cpu_transcoder != TRANSCODER_EDP &&
5431 !transcoder_is_dsi(cpu_transcoder)) {
5432 I915_WRITE(PIPE_MULT(cpu_transcoder),
5433 intel_crtc->config->pixel_multiplier - 1);
5434 }
5435
5436 if (intel_crtc->config->has_pch_encoder) {
5437 intel_cpu_transcoder_set_m_n(intel_crtc,
5438 &intel_crtc->config->fdi_m_n, NULL);
5439 }
5440
5441 if (!transcoder_is_dsi(cpu_transcoder))
5442 haswell_set_pipeconf(crtc);
5443
5444 haswell_set_pipemisc(crtc);
5445
5446 intel_color_set_csc(&pipe_config->base);
5447
5448 intel_crtc->active = true;
5449
5450 if (intel_crtc->config->has_pch_encoder)
5451 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5452 else
5453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5454
5455 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5456
5457 if (intel_crtc->config->has_pch_encoder)
5458 dev_priv->display.fdi_link_train(crtc);
5459
5460 if (!transcoder_is_dsi(cpu_transcoder))
5461 intel_ddi_enable_pipe_clock(intel_crtc);
5462
5463 if (INTEL_INFO(dev)->gen >= 9)
5464 skylake_pfit_enable(intel_crtc);
5465 else
5466 ironlake_pfit_enable(intel_crtc);
5467
5468 /*
5469 * On ILK+ LUT must be loaded before the pipe is running but with
5470 * clocks enabled
5471 */
5472 intel_color_load_luts(&pipe_config->base);
5473
5474 intel_ddi_set_pipe_settings(crtc);
5475 if (!transcoder_is_dsi(cpu_transcoder))
5476 intel_ddi_enable_transcoder_func(crtc);
5477
5478 if (dev_priv->display.initial_watermarks != NULL)
5479 dev_priv->display.initial_watermarks(pipe_config);
5480 else
5481 intel_update_watermarks(crtc);
5482
5483 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5484 if (!transcoder_is_dsi(cpu_transcoder))
5485 intel_enable_pipe(intel_crtc);
5486
5487 if (intel_crtc->config->has_pch_encoder)
5488 lpt_pch_enable(crtc);
5489
5490 if (intel_crtc->config->dp_encoder_is_mst)
5491 intel_ddi_set_vc_payload_alloc(crtc, true);
5492
5493 assert_vblank_disabled(crtc);
5494 drm_crtc_vblank_on(crtc);
5495
5496 intel_encoders_enable(crtc, pipe_config, old_state);
5497
5498 if (intel_crtc->config->has_pch_encoder) {
5499 intel_wait_for_vblank(dev, pipe);
5500 intel_wait_for_vblank(dev, pipe);
5501 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5502 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5503 true);
5504 }
5505
5506 /* If we change the relative order between pipe/planes enabling, we need
5507 * to change the workaround. */
5508 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5509 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5510 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5511 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5512 }
5513 }
5514
5515 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5516 {
5517 struct drm_device *dev = crtc->base.dev;
5518 struct drm_i915_private *dev_priv = to_i915(dev);
5519 int pipe = crtc->pipe;
5520
5521 /* To avoid upsetting the power well on haswell only disable the pfit if
5522 * it's in use. The hw state code will make sure we get this right. */
5523 if (force || crtc->config->pch_pfit.enabled) {
5524 I915_WRITE(PF_CTL(pipe), 0);
5525 I915_WRITE(PF_WIN_POS(pipe), 0);
5526 I915_WRITE(PF_WIN_SZ(pipe), 0);
5527 }
5528 }
5529
5530 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5531 struct drm_atomic_state *old_state)
5532 {
5533 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5534 struct drm_device *dev = crtc->dev;
5535 struct drm_i915_private *dev_priv = to_i915(dev);
5536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5537 int pipe = intel_crtc->pipe;
5538
5539 /*
5540 * Sometimes spurious CPU pipe underruns happen when the
5541 * pipe is already disabled, but FDI RX/TX is still enabled.
5542 * Happens at least with VGA+HDMI cloning. Suppress them.
5543 */
5544 if (intel_crtc->config->has_pch_encoder) {
5545 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5546 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5547 }
5548
5549 intel_encoders_disable(crtc, old_crtc_state, old_state);
5550
5551 drm_crtc_vblank_off(crtc);
5552 assert_vblank_disabled(crtc);
5553
5554 intel_disable_pipe(intel_crtc);
5555
5556 ironlake_pfit_disable(intel_crtc, false);
5557
5558 if (intel_crtc->config->has_pch_encoder)
5559 ironlake_fdi_disable(crtc);
5560
5561 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5562
5563 if (intel_crtc->config->has_pch_encoder) {
5564 ironlake_disable_pch_transcoder(dev_priv, pipe);
5565
5566 if (HAS_PCH_CPT(dev_priv)) {
5567 i915_reg_t reg;
5568 u32 temp;
5569
5570 /* disable TRANS_DP_CTL */
5571 reg = TRANS_DP_CTL(pipe);
5572 temp = I915_READ(reg);
5573 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5574 TRANS_DP_PORT_SEL_MASK);
5575 temp |= TRANS_DP_PORT_SEL_NONE;
5576 I915_WRITE(reg, temp);
5577
5578 /* disable DPLL_SEL */
5579 temp = I915_READ(PCH_DPLL_SEL);
5580 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5581 I915_WRITE(PCH_DPLL_SEL, temp);
5582 }
5583
5584 ironlake_fdi_pll_disable(intel_crtc);
5585 }
5586
5587 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5588 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5589 }
5590
5591 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5592 struct drm_atomic_state *old_state)
5593 {
5594 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5595 struct drm_device *dev = crtc->dev;
5596 struct drm_i915_private *dev_priv = to_i915(dev);
5597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5598 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5599
5600 if (intel_crtc->config->has_pch_encoder)
5601 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5602 false);
5603
5604 intel_encoders_disable(crtc, old_crtc_state, old_state);
5605
5606 drm_crtc_vblank_off(crtc);
5607 assert_vblank_disabled(crtc);
5608
5609 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5610 if (!transcoder_is_dsi(cpu_transcoder))
5611 intel_disable_pipe(intel_crtc);
5612
5613 if (intel_crtc->config->dp_encoder_is_mst)
5614 intel_ddi_set_vc_payload_alloc(crtc, false);
5615
5616 if (!transcoder_is_dsi(cpu_transcoder))
5617 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5618
5619 if (INTEL_INFO(dev)->gen >= 9)
5620 skylake_scaler_disable(intel_crtc);
5621 else
5622 ironlake_pfit_disable(intel_crtc, false);
5623
5624 if (!transcoder_is_dsi(cpu_transcoder))
5625 intel_ddi_disable_pipe_clock(intel_crtc);
5626
5627 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5628
5629 if (old_crtc_state->has_pch_encoder)
5630 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5631 true);
5632 }
5633
5634 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5635 {
5636 struct drm_device *dev = crtc->base.dev;
5637 struct drm_i915_private *dev_priv = to_i915(dev);
5638 struct intel_crtc_state *pipe_config = crtc->config;
5639
5640 if (!pipe_config->gmch_pfit.control)
5641 return;
5642
5643 /*
5644 * The panel fitter should only be adjusted whilst the pipe is disabled,
5645 * according to register description and PRM.
5646 */
5647 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5648 assert_pipe_disabled(dev_priv, crtc->pipe);
5649
5650 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5651 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5652
5653 /* Border color in case we don't scale up to the full screen. Black by
5654 * default, change to something else for debugging. */
5655 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5656 }
5657
5658 static enum intel_display_power_domain port_to_power_domain(enum port port)
5659 {
5660 switch (port) {
5661 case PORT_A:
5662 return POWER_DOMAIN_PORT_DDI_A_LANES;
5663 case PORT_B:
5664 return POWER_DOMAIN_PORT_DDI_B_LANES;
5665 case PORT_C:
5666 return POWER_DOMAIN_PORT_DDI_C_LANES;
5667 case PORT_D:
5668 return POWER_DOMAIN_PORT_DDI_D_LANES;
5669 case PORT_E:
5670 return POWER_DOMAIN_PORT_DDI_E_LANES;
5671 default:
5672 MISSING_CASE(port);
5673 return POWER_DOMAIN_PORT_OTHER;
5674 }
5675 }
5676
5677 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5678 {
5679 switch (port) {
5680 case PORT_A:
5681 return POWER_DOMAIN_AUX_A;
5682 case PORT_B:
5683 return POWER_DOMAIN_AUX_B;
5684 case PORT_C:
5685 return POWER_DOMAIN_AUX_C;
5686 case PORT_D:
5687 return POWER_DOMAIN_AUX_D;
5688 case PORT_E:
5689 /* FIXME: Check VBT for actual wiring of PORT E */
5690 return POWER_DOMAIN_AUX_D;
5691 default:
5692 MISSING_CASE(port);
5693 return POWER_DOMAIN_AUX_A;
5694 }
5695 }
5696
5697 enum intel_display_power_domain
5698 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5699 {
5700 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5701 struct intel_digital_port *intel_dig_port;
5702
5703 switch (intel_encoder->type) {
5704 case INTEL_OUTPUT_UNKNOWN:
5705 /* Only DDI platforms should ever use this output type */
5706 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5707 case INTEL_OUTPUT_DP:
5708 case INTEL_OUTPUT_HDMI:
5709 case INTEL_OUTPUT_EDP:
5710 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5711 return port_to_power_domain(intel_dig_port->port);
5712 case INTEL_OUTPUT_DP_MST:
5713 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5714 return port_to_power_domain(intel_dig_port->port);
5715 case INTEL_OUTPUT_ANALOG:
5716 return POWER_DOMAIN_PORT_CRT;
5717 case INTEL_OUTPUT_DSI:
5718 return POWER_DOMAIN_PORT_DSI;
5719 default:
5720 return POWER_DOMAIN_PORT_OTHER;
5721 }
5722 }
5723
5724 enum intel_display_power_domain
5725 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5726 {
5727 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5728 struct intel_digital_port *intel_dig_port;
5729
5730 switch (intel_encoder->type) {
5731 case INTEL_OUTPUT_UNKNOWN:
5732 case INTEL_OUTPUT_HDMI:
5733 /*
5734 * Only DDI platforms should ever use these output types.
5735 * We can get here after the HDMI detect code has already set
5736 * the type of the shared encoder. Since we can't be sure
5737 * what's the status of the given connectors, play safe and
5738 * run the DP detection too.
5739 */
5740 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5741 case INTEL_OUTPUT_DP:
5742 case INTEL_OUTPUT_EDP:
5743 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5744 return port_to_aux_power_domain(intel_dig_port->port);
5745 case INTEL_OUTPUT_DP_MST:
5746 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5747 return port_to_aux_power_domain(intel_dig_port->port);
5748 default:
5749 MISSING_CASE(intel_encoder->type);
5750 return POWER_DOMAIN_AUX_A;
5751 }
5752 }
5753
5754 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5755 struct intel_crtc_state *crtc_state)
5756 {
5757 struct drm_device *dev = crtc->dev;
5758 struct drm_encoder *encoder;
5759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 enum pipe pipe = intel_crtc->pipe;
5761 unsigned long mask;
5762 enum transcoder transcoder = crtc_state->cpu_transcoder;
5763
5764 if (!crtc_state->base.active)
5765 return 0;
5766
5767 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5768 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5769 if (crtc_state->pch_pfit.enabled ||
5770 crtc_state->pch_pfit.force_thru)
5771 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5772
5773 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5774 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5775
5776 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5777 }
5778
5779 if (crtc_state->shared_dpll)
5780 mask |= BIT(POWER_DOMAIN_PLLS);
5781
5782 return mask;
5783 }
5784
5785 static unsigned long
5786 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5787 struct intel_crtc_state *crtc_state)
5788 {
5789 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791 enum intel_display_power_domain domain;
5792 unsigned long domains, new_domains, old_domains;
5793
5794 old_domains = intel_crtc->enabled_power_domains;
5795 intel_crtc->enabled_power_domains = new_domains =
5796 get_crtc_power_domains(crtc, crtc_state);
5797
5798 domains = new_domains & ~old_domains;
5799
5800 for_each_power_domain(domain, domains)
5801 intel_display_power_get(dev_priv, domain);
5802
5803 return old_domains & ~new_domains;
5804 }
5805
5806 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5807 unsigned long domains)
5808 {
5809 enum intel_display_power_domain domain;
5810
5811 for_each_power_domain(domain, domains)
5812 intel_display_power_put(dev_priv, domain);
5813 }
5814
5815 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5816 {
5817 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5818
5819 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5820 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5821 return max_cdclk_freq;
5822 else if (IS_CHERRYVIEW(dev_priv))
5823 return max_cdclk_freq*95/100;
5824 else if (INTEL_INFO(dev_priv)->gen < 4)
5825 return 2*max_cdclk_freq*90/100;
5826 else
5827 return max_cdclk_freq*90/100;
5828 }
5829
5830 static int skl_calc_cdclk(int max_pixclk, int vco);
5831
5832 static void intel_update_max_cdclk(struct drm_device *dev)
5833 {
5834 struct drm_i915_private *dev_priv = to_i915(dev);
5835
5836 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5837 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5838 int max_cdclk, vco;
5839
5840 vco = dev_priv->skl_preferred_vco_freq;
5841 WARN_ON(vco != 8100000 && vco != 8640000);
5842
5843 /*
5844 * Use the lower (vco 8640) cdclk values as a
5845 * first guess. skl_calc_cdclk() will correct it
5846 * if the preferred vco is 8100 instead.
5847 */
5848 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5849 max_cdclk = 617143;
5850 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5851 max_cdclk = 540000;
5852 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5853 max_cdclk = 432000;
5854 else
5855 max_cdclk = 308571;
5856
5857 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5858 } else if (IS_BROXTON(dev_priv)) {
5859 dev_priv->max_cdclk_freq = 624000;
5860 } else if (IS_BROADWELL(dev_priv)) {
5861 /*
5862 * FIXME with extra cooling we can allow
5863 * 540 MHz for ULX and 675 Mhz for ULT.
5864 * How can we know if extra cooling is
5865 * available? PCI ID, VTB, something else?
5866 */
5867 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5868 dev_priv->max_cdclk_freq = 450000;
5869 else if (IS_BDW_ULX(dev_priv))
5870 dev_priv->max_cdclk_freq = 450000;
5871 else if (IS_BDW_ULT(dev_priv))
5872 dev_priv->max_cdclk_freq = 540000;
5873 else
5874 dev_priv->max_cdclk_freq = 675000;
5875 } else if (IS_CHERRYVIEW(dev)) {
5876 dev_priv->max_cdclk_freq = 320000;
5877 } else if (IS_VALLEYVIEW(dev)) {
5878 dev_priv->max_cdclk_freq = 400000;
5879 } else {
5880 /* otherwise assume cdclk is fixed */
5881 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5882 }
5883
5884 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5885
5886 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5887 dev_priv->max_cdclk_freq);
5888
5889 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5890 dev_priv->max_dotclk_freq);
5891 }
5892
5893 static void intel_update_cdclk(struct drm_device *dev)
5894 {
5895 struct drm_i915_private *dev_priv = to_i915(dev);
5896
5897 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5898
5899 if (INTEL_GEN(dev_priv) >= 9)
5900 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5901 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5902 dev_priv->cdclk_pll.ref);
5903 else
5904 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5905 dev_priv->cdclk_freq);
5906
5907 /*
5908 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5909 * Programmng [sic] note: bit[9:2] should be programmed to the number
5910 * of cdclk that generates 4MHz reference clock freq which is used to
5911 * generate GMBus clock. This will vary with the cdclk freq.
5912 */
5913 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5914 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5915 }
5916
5917 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5918 static int skl_cdclk_decimal(int cdclk)
5919 {
5920 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5921 }
5922
5923 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5924 {
5925 int ratio;
5926
5927 if (cdclk == dev_priv->cdclk_pll.ref)
5928 return 0;
5929
5930 switch (cdclk) {
5931 default:
5932 MISSING_CASE(cdclk);
5933 case 144000:
5934 case 288000:
5935 case 384000:
5936 case 576000:
5937 ratio = 60;
5938 break;
5939 case 624000:
5940 ratio = 65;
5941 break;
5942 }
5943
5944 return dev_priv->cdclk_pll.ref * ratio;
5945 }
5946
5947 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5948 {
5949 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5950
5951 /* Timeout 200us */
5952 if (intel_wait_for_register(dev_priv,
5953 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5954 1))
5955 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5956
5957 dev_priv->cdclk_pll.vco = 0;
5958 }
5959
5960 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5961 {
5962 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5963 u32 val;
5964
5965 val = I915_READ(BXT_DE_PLL_CTL);
5966 val &= ~BXT_DE_PLL_RATIO_MASK;
5967 val |= BXT_DE_PLL_RATIO(ratio);
5968 I915_WRITE(BXT_DE_PLL_CTL, val);
5969
5970 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5971
5972 /* Timeout 200us */
5973 if (intel_wait_for_register(dev_priv,
5974 BXT_DE_PLL_ENABLE,
5975 BXT_DE_PLL_LOCK,
5976 BXT_DE_PLL_LOCK,
5977 1))
5978 DRM_ERROR("timeout waiting for DE PLL lock\n");
5979
5980 dev_priv->cdclk_pll.vco = vco;
5981 }
5982
5983 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5984 {
5985 u32 val, divider;
5986 int vco, ret;
5987
5988 vco = bxt_de_pll_vco(dev_priv, cdclk);
5989
5990 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5991
5992 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5993 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5994 case 8:
5995 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5996 break;
5997 case 4:
5998 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5999 break;
6000 case 3:
6001 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6002 break;
6003 case 2:
6004 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6005 break;
6006 default:
6007 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6008 WARN_ON(vco != 0);
6009
6010 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6011 break;
6012 }
6013
6014 /* Inform power controller of upcoming frequency change */
6015 mutex_lock(&dev_priv->rps.hw_lock);
6016 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6017 0x80000000);
6018 mutex_unlock(&dev_priv->rps.hw_lock);
6019
6020 if (ret) {
6021 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6022 ret, cdclk);
6023 return;
6024 }
6025
6026 if (dev_priv->cdclk_pll.vco != 0 &&
6027 dev_priv->cdclk_pll.vco != vco)
6028 bxt_de_pll_disable(dev_priv);
6029
6030 if (dev_priv->cdclk_pll.vco != vco)
6031 bxt_de_pll_enable(dev_priv, vco);
6032
6033 val = divider | skl_cdclk_decimal(cdclk);
6034 /*
6035 * FIXME if only the cd2x divider needs changing, it could be done
6036 * without shutting off the pipe (if only one pipe is active).
6037 */
6038 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6039 /*
6040 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6041 * enable otherwise.
6042 */
6043 if (cdclk >= 500000)
6044 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6045 I915_WRITE(CDCLK_CTL, val);
6046
6047 mutex_lock(&dev_priv->rps.hw_lock);
6048 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6049 DIV_ROUND_UP(cdclk, 25000));
6050 mutex_unlock(&dev_priv->rps.hw_lock);
6051
6052 if (ret) {
6053 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6054 ret, cdclk);
6055 return;
6056 }
6057
6058 intel_update_cdclk(&dev_priv->drm);
6059 }
6060
6061 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6062 {
6063 u32 cdctl, expected;
6064
6065 intel_update_cdclk(&dev_priv->drm);
6066
6067 if (dev_priv->cdclk_pll.vco == 0 ||
6068 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6069 goto sanitize;
6070
6071 /* DPLL okay; verify the cdclock
6072 *
6073 * Some BIOS versions leave an incorrect decimal frequency value and
6074 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6075 * so sanitize this register.
6076 */
6077 cdctl = I915_READ(CDCLK_CTL);
6078 /*
6079 * Let's ignore the pipe field, since BIOS could have configured the
6080 * dividers both synching to an active pipe, or asynchronously
6081 * (PIPE_NONE).
6082 */
6083 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6084
6085 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6086 skl_cdclk_decimal(dev_priv->cdclk_freq);
6087 /*
6088 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6089 * enable otherwise.
6090 */
6091 if (dev_priv->cdclk_freq >= 500000)
6092 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6093
6094 if (cdctl == expected)
6095 /* All well; nothing to sanitize */
6096 return;
6097
6098 sanitize:
6099 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6100
6101 /* force cdclk programming */
6102 dev_priv->cdclk_freq = 0;
6103
6104 /* force full PLL disable + enable */
6105 dev_priv->cdclk_pll.vco = -1;
6106 }
6107
6108 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6109 {
6110 bxt_sanitize_cdclk(dev_priv);
6111
6112 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6113 return;
6114
6115 /*
6116 * FIXME:
6117 * - The initial CDCLK needs to be read from VBT.
6118 * Need to make this change after VBT has changes for BXT.
6119 */
6120 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6121 }
6122
6123 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6124 {
6125 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6126 }
6127
6128 static int skl_calc_cdclk(int max_pixclk, int vco)
6129 {
6130 if (vco == 8640000) {
6131 if (max_pixclk > 540000)
6132 return 617143;
6133 else if (max_pixclk > 432000)
6134 return 540000;
6135 else if (max_pixclk > 308571)
6136 return 432000;
6137 else
6138 return 308571;
6139 } else {
6140 if (max_pixclk > 540000)
6141 return 675000;
6142 else if (max_pixclk > 450000)
6143 return 540000;
6144 else if (max_pixclk > 337500)
6145 return 450000;
6146 else
6147 return 337500;
6148 }
6149 }
6150
6151 static void
6152 skl_dpll0_update(struct drm_i915_private *dev_priv)
6153 {
6154 u32 val;
6155
6156 dev_priv->cdclk_pll.ref = 24000;
6157 dev_priv->cdclk_pll.vco = 0;
6158
6159 val = I915_READ(LCPLL1_CTL);
6160 if ((val & LCPLL_PLL_ENABLE) == 0)
6161 return;
6162
6163 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6164 return;
6165
6166 val = I915_READ(DPLL_CTRL1);
6167
6168 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6169 DPLL_CTRL1_SSC(SKL_DPLL0) |
6170 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6171 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6172 return;
6173
6174 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6175 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6176 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6177 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6178 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6179 dev_priv->cdclk_pll.vco = 8100000;
6180 break;
6181 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6182 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6183 dev_priv->cdclk_pll.vco = 8640000;
6184 break;
6185 default:
6186 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6187 break;
6188 }
6189 }
6190
6191 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6192 {
6193 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6194
6195 dev_priv->skl_preferred_vco_freq = vco;
6196
6197 if (changed)
6198 intel_update_max_cdclk(&dev_priv->drm);
6199 }
6200
6201 static void
6202 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6203 {
6204 int min_cdclk = skl_calc_cdclk(0, vco);
6205 u32 val;
6206
6207 WARN_ON(vco != 8100000 && vco != 8640000);
6208
6209 /* select the minimum CDCLK before enabling DPLL 0 */
6210 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6211 I915_WRITE(CDCLK_CTL, val);
6212 POSTING_READ(CDCLK_CTL);
6213
6214 /*
6215 * We always enable DPLL0 with the lowest link rate possible, but still
6216 * taking into account the VCO required to operate the eDP panel at the
6217 * desired frequency. The usual DP link rates operate with a VCO of
6218 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6219 * The modeset code is responsible for the selection of the exact link
6220 * rate later on, with the constraint of choosing a frequency that
6221 * works with vco.
6222 */
6223 val = I915_READ(DPLL_CTRL1);
6224
6225 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6226 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6227 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6228 if (vco == 8640000)
6229 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6230 SKL_DPLL0);
6231 else
6232 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6233 SKL_DPLL0);
6234
6235 I915_WRITE(DPLL_CTRL1, val);
6236 POSTING_READ(DPLL_CTRL1);
6237
6238 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6239
6240 if (intel_wait_for_register(dev_priv,
6241 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6242 5))
6243 DRM_ERROR("DPLL0 not locked\n");
6244
6245 dev_priv->cdclk_pll.vco = vco;
6246
6247 /* We'll want to keep using the current vco from now on. */
6248 skl_set_preferred_cdclk_vco(dev_priv, vco);
6249 }
6250
6251 static void
6252 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6253 {
6254 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6255 if (intel_wait_for_register(dev_priv,
6256 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6257 1))
6258 DRM_ERROR("Couldn't disable DPLL0\n");
6259
6260 dev_priv->cdclk_pll.vco = 0;
6261 }
6262
6263 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6264 {
6265 int ret;
6266 u32 val;
6267
6268 /* inform PCU we want to change CDCLK */
6269 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6270 mutex_lock(&dev_priv->rps.hw_lock);
6271 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6272 mutex_unlock(&dev_priv->rps.hw_lock);
6273
6274 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6275 }
6276
6277 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6278 {
6279 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6280 }
6281
6282 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6283 {
6284 struct drm_device *dev = &dev_priv->drm;
6285 u32 freq_select, pcu_ack;
6286
6287 WARN_ON((cdclk == 24000) != (vco == 0));
6288
6289 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6290
6291 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6292 DRM_ERROR("failed to inform PCU about cdclk change\n");
6293 return;
6294 }
6295
6296 /* set CDCLK_CTL */
6297 switch (cdclk) {
6298 case 450000:
6299 case 432000:
6300 freq_select = CDCLK_FREQ_450_432;
6301 pcu_ack = 1;
6302 break;
6303 case 540000:
6304 freq_select = CDCLK_FREQ_540;
6305 pcu_ack = 2;
6306 break;
6307 case 308571:
6308 case 337500:
6309 default:
6310 freq_select = CDCLK_FREQ_337_308;
6311 pcu_ack = 0;
6312 break;
6313 case 617143:
6314 case 675000:
6315 freq_select = CDCLK_FREQ_675_617;
6316 pcu_ack = 3;
6317 break;
6318 }
6319
6320 if (dev_priv->cdclk_pll.vco != 0 &&
6321 dev_priv->cdclk_pll.vco != vco)
6322 skl_dpll0_disable(dev_priv);
6323
6324 if (dev_priv->cdclk_pll.vco != vco)
6325 skl_dpll0_enable(dev_priv, vco);
6326
6327 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6328 POSTING_READ(CDCLK_CTL);
6329
6330 /* inform PCU of the change */
6331 mutex_lock(&dev_priv->rps.hw_lock);
6332 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6333 mutex_unlock(&dev_priv->rps.hw_lock);
6334
6335 intel_update_cdclk(dev);
6336 }
6337
6338 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6339
6340 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6341 {
6342 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6343 }
6344
6345 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6346 {
6347 int cdclk, vco;
6348
6349 skl_sanitize_cdclk(dev_priv);
6350
6351 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6352 /*
6353 * Use the current vco as our initial
6354 * guess as to what the preferred vco is.
6355 */
6356 if (dev_priv->skl_preferred_vco_freq == 0)
6357 skl_set_preferred_cdclk_vco(dev_priv,
6358 dev_priv->cdclk_pll.vco);
6359 return;
6360 }
6361
6362 vco = dev_priv->skl_preferred_vco_freq;
6363 if (vco == 0)
6364 vco = 8100000;
6365 cdclk = skl_calc_cdclk(0, vco);
6366
6367 skl_set_cdclk(dev_priv, cdclk, vco);
6368 }
6369
6370 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6371 {
6372 uint32_t cdctl, expected;
6373
6374 /*
6375 * check if the pre-os intialized the display
6376 * There is SWF18 scratchpad register defined which is set by the
6377 * pre-os which can be used by the OS drivers to check the status
6378 */
6379 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6380 goto sanitize;
6381
6382 intel_update_cdclk(&dev_priv->drm);
6383 /* Is PLL enabled and locked ? */
6384 if (dev_priv->cdclk_pll.vco == 0 ||
6385 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6386 goto sanitize;
6387
6388 /* DPLL okay; verify the cdclock
6389 *
6390 * Noticed in some instances that the freq selection is correct but
6391 * decimal part is programmed wrong from BIOS where pre-os does not
6392 * enable display. Verify the same as well.
6393 */
6394 cdctl = I915_READ(CDCLK_CTL);
6395 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6396 skl_cdclk_decimal(dev_priv->cdclk_freq);
6397 if (cdctl == expected)
6398 /* All well; nothing to sanitize */
6399 return;
6400
6401 sanitize:
6402 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6403
6404 /* force cdclk programming */
6405 dev_priv->cdclk_freq = 0;
6406 /* force full PLL disable + enable */
6407 dev_priv->cdclk_pll.vco = -1;
6408 }
6409
6410 /* Adjust CDclk dividers to allow high res or save power if possible */
6411 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6412 {
6413 struct drm_i915_private *dev_priv = to_i915(dev);
6414 u32 val, cmd;
6415
6416 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6417 != dev_priv->cdclk_freq);
6418
6419 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6420 cmd = 2;
6421 else if (cdclk == 266667)
6422 cmd = 1;
6423 else
6424 cmd = 0;
6425
6426 mutex_lock(&dev_priv->rps.hw_lock);
6427 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6428 val &= ~DSPFREQGUAR_MASK;
6429 val |= (cmd << DSPFREQGUAR_SHIFT);
6430 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6431 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6432 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6433 50)) {
6434 DRM_ERROR("timed out waiting for CDclk change\n");
6435 }
6436 mutex_unlock(&dev_priv->rps.hw_lock);
6437
6438 mutex_lock(&dev_priv->sb_lock);
6439
6440 if (cdclk == 400000) {
6441 u32 divider;
6442
6443 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6444
6445 /* adjust cdclk divider */
6446 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6447 val &= ~CCK_FREQUENCY_VALUES;
6448 val |= divider;
6449 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6450
6451 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6452 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6453 50))
6454 DRM_ERROR("timed out waiting for CDclk change\n");
6455 }
6456
6457 /* adjust self-refresh exit latency value */
6458 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6459 val &= ~0x7f;
6460
6461 /*
6462 * For high bandwidth configs, we set a higher latency in the bunit
6463 * so that the core display fetch happens in time to avoid underruns.
6464 */
6465 if (cdclk == 400000)
6466 val |= 4500 / 250; /* 4.5 usec */
6467 else
6468 val |= 3000 / 250; /* 3.0 usec */
6469 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6470
6471 mutex_unlock(&dev_priv->sb_lock);
6472
6473 intel_update_cdclk(dev);
6474 }
6475
6476 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6477 {
6478 struct drm_i915_private *dev_priv = to_i915(dev);
6479 u32 val, cmd;
6480
6481 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6482 != dev_priv->cdclk_freq);
6483
6484 switch (cdclk) {
6485 case 333333:
6486 case 320000:
6487 case 266667:
6488 case 200000:
6489 break;
6490 default:
6491 MISSING_CASE(cdclk);
6492 return;
6493 }
6494
6495 /*
6496 * Specs are full of misinformation, but testing on actual
6497 * hardware has shown that we just need to write the desired
6498 * CCK divider into the Punit register.
6499 */
6500 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6501
6502 mutex_lock(&dev_priv->rps.hw_lock);
6503 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6504 val &= ~DSPFREQGUAR_MASK_CHV;
6505 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6506 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6507 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6508 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6509 50)) {
6510 DRM_ERROR("timed out waiting for CDclk change\n");
6511 }
6512 mutex_unlock(&dev_priv->rps.hw_lock);
6513
6514 intel_update_cdclk(dev);
6515 }
6516
6517 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6518 int max_pixclk)
6519 {
6520 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6521 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6522
6523 /*
6524 * Really only a few cases to deal with, as only 4 CDclks are supported:
6525 * 200MHz
6526 * 267MHz
6527 * 320/333MHz (depends on HPLL freq)
6528 * 400MHz (VLV only)
6529 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6530 * of the lower bin and adjust if needed.
6531 *
6532 * We seem to get an unstable or solid color picture at 200MHz.
6533 * Not sure what's wrong. For now use 200MHz only when all pipes
6534 * are off.
6535 */
6536 if (!IS_CHERRYVIEW(dev_priv) &&
6537 max_pixclk > freq_320*limit/100)
6538 return 400000;
6539 else if (max_pixclk > 266667*limit/100)
6540 return freq_320;
6541 else if (max_pixclk > 0)
6542 return 266667;
6543 else
6544 return 200000;
6545 }
6546
6547 static int bxt_calc_cdclk(int max_pixclk)
6548 {
6549 if (max_pixclk > 576000)
6550 return 624000;
6551 else if (max_pixclk > 384000)
6552 return 576000;
6553 else if (max_pixclk > 288000)
6554 return 384000;
6555 else if (max_pixclk > 144000)
6556 return 288000;
6557 else
6558 return 144000;
6559 }
6560
6561 /* Compute the max pixel clock for new configuration. */
6562 static int intel_mode_max_pixclk(struct drm_device *dev,
6563 struct drm_atomic_state *state)
6564 {
6565 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6566 struct drm_i915_private *dev_priv = to_i915(dev);
6567 struct drm_crtc *crtc;
6568 struct drm_crtc_state *crtc_state;
6569 unsigned max_pixclk = 0, i;
6570 enum pipe pipe;
6571
6572 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6573 sizeof(intel_state->min_pixclk));
6574
6575 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6576 int pixclk = 0;
6577
6578 if (crtc_state->enable)
6579 pixclk = crtc_state->adjusted_mode.crtc_clock;
6580
6581 intel_state->min_pixclk[i] = pixclk;
6582 }
6583
6584 for_each_pipe(dev_priv, pipe)
6585 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6586
6587 return max_pixclk;
6588 }
6589
6590 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6591 {
6592 struct drm_device *dev = state->dev;
6593 struct drm_i915_private *dev_priv = to_i915(dev);
6594 int max_pixclk = intel_mode_max_pixclk(dev, state);
6595 struct intel_atomic_state *intel_state =
6596 to_intel_atomic_state(state);
6597
6598 intel_state->cdclk = intel_state->dev_cdclk =
6599 valleyview_calc_cdclk(dev_priv, max_pixclk);
6600
6601 if (!intel_state->active_crtcs)
6602 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6603
6604 return 0;
6605 }
6606
6607 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6608 {
6609 int max_pixclk = ilk_max_pixel_rate(state);
6610 struct intel_atomic_state *intel_state =
6611 to_intel_atomic_state(state);
6612
6613 intel_state->cdclk = intel_state->dev_cdclk =
6614 bxt_calc_cdclk(max_pixclk);
6615
6616 if (!intel_state->active_crtcs)
6617 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6618
6619 return 0;
6620 }
6621
6622 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6623 {
6624 unsigned int credits, default_credits;
6625
6626 if (IS_CHERRYVIEW(dev_priv))
6627 default_credits = PFI_CREDIT(12);
6628 else
6629 default_credits = PFI_CREDIT(8);
6630
6631 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6632 /* CHV suggested value is 31 or 63 */
6633 if (IS_CHERRYVIEW(dev_priv))
6634 credits = PFI_CREDIT_63;
6635 else
6636 credits = PFI_CREDIT(15);
6637 } else {
6638 credits = default_credits;
6639 }
6640
6641 /*
6642 * WA - write default credits before re-programming
6643 * FIXME: should we also set the resend bit here?
6644 */
6645 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6646 default_credits);
6647
6648 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6649 credits | PFI_CREDIT_RESEND);
6650
6651 /*
6652 * FIXME is this guaranteed to clear
6653 * immediately or should we poll for it?
6654 */
6655 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6656 }
6657
6658 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6659 {
6660 struct drm_device *dev = old_state->dev;
6661 struct drm_i915_private *dev_priv = to_i915(dev);
6662 struct intel_atomic_state *old_intel_state =
6663 to_intel_atomic_state(old_state);
6664 unsigned req_cdclk = old_intel_state->dev_cdclk;
6665
6666 /*
6667 * FIXME: We can end up here with all power domains off, yet
6668 * with a CDCLK frequency other than the minimum. To account
6669 * for this take the PIPE-A power domain, which covers the HW
6670 * blocks needed for the following programming. This can be
6671 * removed once it's guaranteed that we get here either with
6672 * the minimum CDCLK set, or the required power domains
6673 * enabled.
6674 */
6675 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6676
6677 if (IS_CHERRYVIEW(dev))
6678 cherryview_set_cdclk(dev, req_cdclk);
6679 else
6680 valleyview_set_cdclk(dev, req_cdclk);
6681
6682 vlv_program_pfi_credits(dev_priv);
6683
6684 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6685 }
6686
6687 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6688 struct drm_atomic_state *old_state)
6689 {
6690 struct drm_crtc *crtc = pipe_config->base.crtc;
6691 struct drm_device *dev = crtc->dev;
6692 struct drm_i915_private *dev_priv = to_i915(dev);
6693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6694 int pipe = intel_crtc->pipe;
6695
6696 if (WARN_ON(intel_crtc->active))
6697 return;
6698
6699 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6700 intel_dp_set_m_n(intel_crtc, M1_N1);
6701
6702 intel_set_pipe_timings(intel_crtc);
6703 intel_set_pipe_src_size(intel_crtc);
6704
6705 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6706 struct drm_i915_private *dev_priv = to_i915(dev);
6707
6708 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6709 I915_WRITE(CHV_CANVAS(pipe), 0);
6710 }
6711
6712 i9xx_set_pipeconf(intel_crtc);
6713
6714 intel_crtc->active = true;
6715
6716 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6717
6718 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6719
6720 if (IS_CHERRYVIEW(dev)) {
6721 chv_prepare_pll(intel_crtc, intel_crtc->config);
6722 chv_enable_pll(intel_crtc, intel_crtc->config);
6723 } else {
6724 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6725 vlv_enable_pll(intel_crtc, intel_crtc->config);
6726 }
6727
6728 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6729
6730 i9xx_pfit_enable(intel_crtc);
6731
6732 intel_color_load_luts(&pipe_config->base);
6733
6734 intel_update_watermarks(crtc);
6735 intel_enable_pipe(intel_crtc);
6736
6737 assert_vblank_disabled(crtc);
6738 drm_crtc_vblank_on(crtc);
6739
6740 intel_encoders_enable(crtc, pipe_config, old_state);
6741 }
6742
6743 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6744 {
6745 struct drm_device *dev = crtc->base.dev;
6746 struct drm_i915_private *dev_priv = to_i915(dev);
6747
6748 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6749 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6750 }
6751
6752 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6753 struct drm_atomic_state *old_state)
6754 {
6755 struct drm_crtc *crtc = pipe_config->base.crtc;
6756 struct drm_device *dev = crtc->dev;
6757 struct drm_i915_private *dev_priv = to_i915(dev);
6758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759 enum pipe pipe = intel_crtc->pipe;
6760
6761 if (WARN_ON(intel_crtc->active))
6762 return;
6763
6764 i9xx_set_pll_dividers(intel_crtc);
6765
6766 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6767 intel_dp_set_m_n(intel_crtc, M1_N1);
6768
6769 intel_set_pipe_timings(intel_crtc);
6770 intel_set_pipe_src_size(intel_crtc);
6771
6772 i9xx_set_pipeconf(intel_crtc);
6773
6774 intel_crtc->active = true;
6775
6776 if (!IS_GEN2(dev))
6777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6778
6779 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6780
6781 i9xx_enable_pll(intel_crtc);
6782
6783 i9xx_pfit_enable(intel_crtc);
6784
6785 intel_color_load_luts(&pipe_config->base);
6786
6787 intel_update_watermarks(crtc);
6788 intel_enable_pipe(intel_crtc);
6789
6790 assert_vblank_disabled(crtc);
6791 drm_crtc_vblank_on(crtc);
6792
6793 intel_encoders_enable(crtc, pipe_config, old_state);
6794 }
6795
6796 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6797 {
6798 struct drm_device *dev = crtc->base.dev;
6799 struct drm_i915_private *dev_priv = to_i915(dev);
6800
6801 if (!crtc->config->gmch_pfit.control)
6802 return;
6803
6804 assert_pipe_disabled(dev_priv, crtc->pipe);
6805
6806 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6807 I915_READ(PFIT_CONTROL));
6808 I915_WRITE(PFIT_CONTROL, 0);
6809 }
6810
6811 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6812 struct drm_atomic_state *old_state)
6813 {
6814 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6815 struct drm_device *dev = crtc->dev;
6816 struct drm_i915_private *dev_priv = to_i915(dev);
6817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6818 int pipe = intel_crtc->pipe;
6819
6820 /*
6821 * On gen2 planes are double buffered but the pipe isn't, so we must
6822 * wait for planes to fully turn off before disabling the pipe.
6823 */
6824 if (IS_GEN2(dev))
6825 intel_wait_for_vblank(dev, pipe);
6826
6827 intel_encoders_disable(crtc, old_crtc_state, old_state);
6828
6829 drm_crtc_vblank_off(crtc);
6830 assert_vblank_disabled(crtc);
6831
6832 intel_disable_pipe(intel_crtc);
6833
6834 i9xx_pfit_disable(intel_crtc);
6835
6836 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6837
6838 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6839 if (IS_CHERRYVIEW(dev))
6840 chv_disable_pll(dev_priv, pipe);
6841 else if (IS_VALLEYVIEW(dev))
6842 vlv_disable_pll(dev_priv, pipe);
6843 else
6844 i9xx_disable_pll(intel_crtc);
6845 }
6846
6847 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6848
6849 if (!IS_GEN2(dev))
6850 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6851 }
6852
6853 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6854 {
6855 struct intel_encoder *encoder;
6856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6857 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6858 enum intel_display_power_domain domain;
6859 unsigned long domains;
6860 struct drm_atomic_state *state;
6861 struct intel_crtc_state *crtc_state;
6862 int ret;
6863
6864 if (!intel_crtc->active)
6865 return;
6866
6867 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6868 WARN_ON(intel_crtc->flip_work);
6869
6870 intel_pre_disable_primary_noatomic(crtc);
6871
6872 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6873 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6874 }
6875
6876 state = drm_atomic_state_alloc(crtc->dev);
6877 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6878
6879 /* Everything's already locked, -EDEADLK can't happen. */
6880 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6881 ret = drm_atomic_add_affected_connectors(state, crtc);
6882
6883 WARN_ON(IS_ERR(crtc_state) || ret);
6884
6885 dev_priv->display.crtc_disable(crtc_state, state);
6886
6887 drm_atomic_state_free(state);
6888
6889 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6890 crtc->base.id, crtc->name);
6891
6892 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6893 crtc->state->active = false;
6894 intel_crtc->active = false;
6895 crtc->enabled = false;
6896 crtc->state->connector_mask = 0;
6897 crtc->state->encoder_mask = 0;
6898
6899 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6900 encoder->base.crtc = NULL;
6901
6902 intel_fbc_disable(intel_crtc);
6903 intel_update_watermarks(crtc);
6904 intel_disable_shared_dpll(intel_crtc);
6905
6906 domains = intel_crtc->enabled_power_domains;
6907 for_each_power_domain(domain, domains)
6908 intel_display_power_put(dev_priv, domain);
6909 intel_crtc->enabled_power_domains = 0;
6910
6911 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6912 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6913 }
6914
6915 /*
6916 * turn all crtc's off, but do not adjust state
6917 * This has to be paired with a call to intel_modeset_setup_hw_state.
6918 */
6919 int intel_display_suspend(struct drm_device *dev)
6920 {
6921 struct drm_i915_private *dev_priv = to_i915(dev);
6922 struct drm_atomic_state *state;
6923 int ret;
6924
6925 state = drm_atomic_helper_suspend(dev);
6926 ret = PTR_ERR_OR_ZERO(state);
6927 if (ret)
6928 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6929 else
6930 dev_priv->modeset_restore_state = state;
6931 return ret;
6932 }
6933
6934 void intel_encoder_destroy(struct drm_encoder *encoder)
6935 {
6936 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6937
6938 drm_encoder_cleanup(encoder);
6939 kfree(intel_encoder);
6940 }
6941
6942 /* Cross check the actual hw state with our own modeset state tracking (and it's
6943 * internal consistency). */
6944 static void intel_connector_verify_state(struct intel_connector *connector)
6945 {
6946 struct drm_crtc *crtc = connector->base.state->crtc;
6947
6948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6949 connector->base.base.id,
6950 connector->base.name);
6951
6952 if (connector->get_hw_state(connector)) {
6953 struct intel_encoder *encoder = connector->encoder;
6954 struct drm_connector_state *conn_state = connector->base.state;
6955
6956 I915_STATE_WARN(!crtc,
6957 "connector enabled without attached crtc\n");
6958
6959 if (!crtc)
6960 return;
6961
6962 I915_STATE_WARN(!crtc->state->active,
6963 "connector is active, but attached crtc isn't\n");
6964
6965 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6966 return;
6967
6968 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6969 "atomic encoder doesn't match attached encoder\n");
6970
6971 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6972 "attached encoder crtc differs from connector crtc\n");
6973 } else {
6974 I915_STATE_WARN(crtc && crtc->state->active,
6975 "attached crtc is active, but connector isn't\n");
6976 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6977 "best encoder set without crtc!\n");
6978 }
6979 }
6980
6981 int intel_connector_init(struct intel_connector *connector)
6982 {
6983 drm_atomic_helper_connector_reset(&connector->base);
6984
6985 if (!connector->base.state)
6986 return -ENOMEM;
6987
6988 return 0;
6989 }
6990
6991 struct intel_connector *intel_connector_alloc(void)
6992 {
6993 struct intel_connector *connector;
6994
6995 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6996 if (!connector)
6997 return NULL;
6998
6999 if (intel_connector_init(connector) < 0) {
7000 kfree(connector);
7001 return NULL;
7002 }
7003
7004 return connector;
7005 }
7006
7007 /* Simple connector->get_hw_state implementation for encoders that support only
7008 * one connector and no cloning and hence the encoder state determines the state
7009 * of the connector. */
7010 bool intel_connector_get_hw_state(struct intel_connector *connector)
7011 {
7012 enum pipe pipe = 0;
7013 struct intel_encoder *encoder = connector->encoder;
7014
7015 return encoder->get_hw_state(encoder, &pipe);
7016 }
7017
7018 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7019 {
7020 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7021 return crtc_state->fdi_lanes;
7022
7023 return 0;
7024 }
7025
7026 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7027 struct intel_crtc_state *pipe_config)
7028 {
7029 struct drm_i915_private *dev_priv = to_i915(dev);
7030 struct drm_atomic_state *state = pipe_config->base.state;
7031 struct intel_crtc *other_crtc;
7032 struct intel_crtc_state *other_crtc_state;
7033
7034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7035 pipe_name(pipe), pipe_config->fdi_lanes);
7036 if (pipe_config->fdi_lanes > 4) {
7037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7038 pipe_name(pipe), pipe_config->fdi_lanes);
7039 return -EINVAL;
7040 }
7041
7042 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7043 if (pipe_config->fdi_lanes > 2) {
7044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7045 pipe_config->fdi_lanes);
7046 return -EINVAL;
7047 } else {
7048 return 0;
7049 }
7050 }
7051
7052 if (INTEL_INFO(dev)->num_pipes == 2)
7053 return 0;
7054
7055 /* Ivybridge 3 pipe is really complicated */
7056 switch (pipe) {
7057 case PIPE_A:
7058 return 0;
7059 case PIPE_B:
7060 if (pipe_config->fdi_lanes <= 2)
7061 return 0;
7062
7063 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7064 other_crtc_state =
7065 intel_atomic_get_crtc_state(state, other_crtc);
7066 if (IS_ERR(other_crtc_state))
7067 return PTR_ERR(other_crtc_state);
7068
7069 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7070 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7071 pipe_name(pipe), pipe_config->fdi_lanes);
7072 return -EINVAL;
7073 }
7074 return 0;
7075 case PIPE_C:
7076 if (pipe_config->fdi_lanes > 2) {
7077 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7078 pipe_name(pipe), pipe_config->fdi_lanes);
7079 return -EINVAL;
7080 }
7081
7082 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7083 other_crtc_state =
7084 intel_atomic_get_crtc_state(state, other_crtc);
7085 if (IS_ERR(other_crtc_state))
7086 return PTR_ERR(other_crtc_state);
7087
7088 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7089 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7090 return -EINVAL;
7091 }
7092 return 0;
7093 default:
7094 BUG();
7095 }
7096 }
7097
7098 #define RETRY 1
7099 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7100 struct intel_crtc_state *pipe_config)
7101 {
7102 struct drm_device *dev = intel_crtc->base.dev;
7103 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7104 int lane, link_bw, fdi_dotclock, ret;
7105 bool needs_recompute = false;
7106
7107 retry:
7108 /* FDI is a binary signal running at ~2.7GHz, encoding
7109 * each output octet as 10 bits. The actual frequency
7110 * is stored as a divider into a 100MHz clock, and the
7111 * mode pixel clock is stored in units of 1KHz.
7112 * Hence the bw of each lane in terms of the mode signal
7113 * is:
7114 */
7115 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7116
7117 fdi_dotclock = adjusted_mode->crtc_clock;
7118
7119 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7120 pipe_config->pipe_bpp);
7121
7122 pipe_config->fdi_lanes = lane;
7123
7124 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7125 link_bw, &pipe_config->fdi_m_n);
7126
7127 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7128 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7129 pipe_config->pipe_bpp -= 2*3;
7130 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7131 pipe_config->pipe_bpp);
7132 needs_recompute = true;
7133 pipe_config->bw_constrained = true;
7134
7135 goto retry;
7136 }
7137
7138 if (needs_recompute)
7139 return RETRY;
7140
7141 return ret;
7142 }
7143
7144 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7145 struct intel_crtc_state *pipe_config)
7146 {
7147 if (pipe_config->pipe_bpp > 24)
7148 return false;
7149
7150 /* HSW can handle pixel rate up to cdclk? */
7151 if (IS_HASWELL(dev_priv))
7152 return true;
7153
7154 /*
7155 * We compare against max which means we must take
7156 * the increased cdclk requirement into account when
7157 * calculating the new cdclk.
7158 *
7159 * Should measure whether using a lower cdclk w/o IPS
7160 */
7161 return ilk_pipe_pixel_rate(pipe_config) <=
7162 dev_priv->max_cdclk_freq * 95 / 100;
7163 }
7164
7165 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7166 struct intel_crtc_state *pipe_config)
7167 {
7168 struct drm_device *dev = crtc->base.dev;
7169 struct drm_i915_private *dev_priv = to_i915(dev);
7170
7171 pipe_config->ips_enabled = i915.enable_ips &&
7172 hsw_crtc_supports_ips(crtc) &&
7173 pipe_config_supports_ips(dev_priv, pipe_config);
7174 }
7175
7176 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7177 {
7178 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7179
7180 /* GDG double wide on either pipe, otherwise pipe A only */
7181 return INTEL_INFO(dev_priv)->gen < 4 &&
7182 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7183 }
7184
7185 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7186 struct intel_crtc_state *pipe_config)
7187 {
7188 struct drm_device *dev = crtc->base.dev;
7189 struct drm_i915_private *dev_priv = to_i915(dev);
7190 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7191 int clock_limit = dev_priv->max_dotclk_freq;
7192
7193 if (INTEL_INFO(dev)->gen < 4) {
7194 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7195
7196 /*
7197 * Enable double wide mode when the dot clock
7198 * is > 90% of the (display) core speed.
7199 */
7200 if (intel_crtc_supports_double_wide(crtc) &&
7201 adjusted_mode->crtc_clock > clock_limit) {
7202 clock_limit = dev_priv->max_dotclk_freq;
7203 pipe_config->double_wide = true;
7204 }
7205 }
7206
7207 if (adjusted_mode->crtc_clock > clock_limit) {
7208 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7209 adjusted_mode->crtc_clock, clock_limit,
7210 yesno(pipe_config->double_wide));
7211 return -EINVAL;
7212 }
7213
7214 /*
7215 * Pipe horizontal size must be even in:
7216 * - DVO ganged mode
7217 * - LVDS dual channel mode
7218 * - Double wide pipe
7219 */
7220 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7221 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7222 pipe_config->pipe_src_w &= ~1;
7223
7224 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7225 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7226 */
7227 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7228 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7229 return -EINVAL;
7230
7231 if (HAS_IPS(dev_priv))
7232 hsw_compute_ips_config(crtc, pipe_config);
7233
7234 if (pipe_config->has_pch_encoder)
7235 return ironlake_fdi_compute_config(crtc, pipe_config);
7236
7237 return 0;
7238 }
7239
7240 static int skylake_get_display_clock_speed(struct drm_device *dev)
7241 {
7242 struct drm_i915_private *dev_priv = to_i915(dev);
7243 uint32_t cdctl;
7244
7245 skl_dpll0_update(dev_priv);
7246
7247 if (dev_priv->cdclk_pll.vco == 0)
7248 return dev_priv->cdclk_pll.ref;
7249
7250 cdctl = I915_READ(CDCLK_CTL);
7251
7252 if (dev_priv->cdclk_pll.vco == 8640000) {
7253 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7254 case CDCLK_FREQ_450_432:
7255 return 432000;
7256 case CDCLK_FREQ_337_308:
7257 return 308571;
7258 case CDCLK_FREQ_540:
7259 return 540000;
7260 case CDCLK_FREQ_675_617:
7261 return 617143;
7262 default:
7263 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7264 }
7265 } else {
7266 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7267 case CDCLK_FREQ_450_432:
7268 return 450000;
7269 case CDCLK_FREQ_337_308:
7270 return 337500;
7271 case CDCLK_FREQ_540:
7272 return 540000;
7273 case CDCLK_FREQ_675_617:
7274 return 675000;
7275 default:
7276 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7277 }
7278 }
7279
7280 return dev_priv->cdclk_pll.ref;
7281 }
7282
7283 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7284 {
7285 u32 val;
7286
7287 dev_priv->cdclk_pll.ref = 19200;
7288 dev_priv->cdclk_pll.vco = 0;
7289
7290 val = I915_READ(BXT_DE_PLL_ENABLE);
7291 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7292 return;
7293
7294 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7295 return;
7296
7297 val = I915_READ(BXT_DE_PLL_CTL);
7298 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7299 dev_priv->cdclk_pll.ref;
7300 }
7301
7302 static int broxton_get_display_clock_speed(struct drm_device *dev)
7303 {
7304 struct drm_i915_private *dev_priv = to_i915(dev);
7305 u32 divider;
7306 int div, vco;
7307
7308 bxt_de_pll_update(dev_priv);
7309
7310 vco = dev_priv->cdclk_pll.vco;
7311 if (vco == 0)
7312 return dev_priv->cdclk_pll.ref;
7313
7314 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7315
7316 switch (divider) {
7317 case BXT_CDCLK_CD2X_DIV_SEL_1:
7318 div = 2;
7319 break;
7320 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7321 div = 3;
7322 break;
7323 case BXT_CDCLK_CD2X_DIV_SEL_2:
7324 div = 4;
7325 break;
7326 case BXT_CDCLK_CD2X_DIV_SEL_4:
7327 div = 8;
7328 break;
7329 default:
7330 MISSING_CASE(divider);
7331 return dev_priv->cdclk_pll.ref;
7332 }
7333
7334 return DIV_ROUND_CLOSEST(vco, div);
7335 }
7336
7337 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7338 {
7339 struct drm_i915_private *dev_priv = to_i915(dev);
7340 uint32_t lcpll = I915_READ(LCPLL_CTL);
7341 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7342
7343 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7344 return 800000;
7345 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7346 return 450000;
7347 else if (freq == LCPLL_CLK_FREQ_450)
7348 return 450000;
7349 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7350 return 540000;
7351 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7352 return 337500;
7353 else
7354 return 675000;
7355 }
7356
7357 static int haswell_get_display_clock_speed(struct drm_device *dev)
7358 {
7359 struct drm_i915_private *dev_priv = to_i915(dev);
7360 uint32_t lcpll = I915_READ(LCPLL_CTL);
7361 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7362
7363 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7364 return 800000;
7365 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7366 return 450000;
7367 else if (freq == LCPLL_CLK_FREQ_450)
7368 return 450000;
7369 else if (IS_HSW_ULT(dev_priv))
7370 return 337500;
7371 else
7372 return 540000;
7373 }
7374
7375 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7376 {
7377 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7378 CCK_DISPLAY_CLOCK_CONTROL);
7379 }
7380
7381 static int ilk_get_display_clock_speed(struct drm_device *dev)
7382 {
7383 return 450000;
7384 }
7385
7386 static int i945_get_display_clock_speed(struct drm_device *dev)
7387 {
7388 return 400000;
7389 }
7390
7391 static int i915_get_display_clock_speed(struct drm_device *dev)
7392 {
7393 return 333333;
7394 }
7395
7396 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7397 {
7398 return 200000;
7399 }
7400
7401 static int pnv_get_display_clock_speed(struct drm_device *dev)
7402 {
7403 struct pci_dev *pdev = dev->pdev;
7404 u16 gcfgc = 0;
7405
7406 pci_read_config_word(pdev, GCFGC, &gcfgc);
7407
7408 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7409 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7410 return 266667;
7411 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7412 return 333333;
7413 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7414 return 444444;
7415 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7416 return 200000;
7417 default:
7418 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7419 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7420 return 133333;
7421 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7422 return 166667;
7423 }
7424 }
7425
7426 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7427 {
7428 struct pci_dev *pdev = dev->pdev;
7429 u16 gcfgc = 0;
7430
7431 pci_read_config_word(pdev, GCFGC, &gcfgc);
7432
7433 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7434 return 133333;
7435 else {
7436 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7437 case GC_DISPLAY_CLOCK_333_MHZ:
7438 return 333333;
7439 default:
7440 case GC_DISPLAY_CLOCK_190_200_MHZ:
7441 return 190000;
7442 }
7443 }
7444 }
7445
7446 static int i865_get_display_clock_speed(struct drm_device *dev)
7447 {
7448 return 266667;
7449 }
7450
7451 static int i85x_get_display_clock_speed(struct drm_device *dev)
7452 {
7453 struct pci_dev *pdev = dev->pdev;
7454 u16 hpllcc = 0;
7455
7456 /*
7457 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7458 * encoding is different :(
7459 * FIXME is this the right way to detect 852GM/852GMV?
7460 */
7461 if (pdev->revision == 0x1)
7462 return 133333;
7463
7464 pci_bus_read_config_word(pdev->bus,
7465 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7466
7467 /* Assume that the hardware is in the high speed state. This
7468 * should be the default.
7469 */
7470 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7471 case GC_CLOCK_133_200:
7472 case GC_CLOCK_133_200_2:
7473 case GC_CLOCK_100_200:
7474 return 200000;
7475 case GC_CLOCK_166_250:
7476 return 250000;
7477 case GC_CLOCK_100_133:
7478 return 133333;
7479 case GC_CLOCK_133_266:
7480 case GC_CLOCK_133_266_2:
7481 case GC_CLOCK_166_266:
7482 return 266667;
7483 }
7484
7485 /* Shouldn't happen */
7486 return 0;
7487 }
7488
7489 static int i830_get_display_clock_speed(struct drm_device *dev)
7490 {
7491 return 133333;
7492 }
7493
7494 static unsigned int intel_hpll_vco(struct drm_device *dev)
7495 {
7496 struct drm_i915_private *dev_priv = to_i915(dev);
7497 static const unsigned int blb_vco[8] = {
7498 [0] = 3200000,
7499 [1] = 4000000,
7500 [2] = 5333333,
7501 [3] = 4800000,
7502 [4] = 6400000,
7503 };
7504 static const unsigned int pnv_vco[8] = {
7505 [0] = 3200000,
7506 [1] = 4000000,
7507 [2] = 5333333,
7508 [3] = 4800000,
7509 [4] = 2666667,
7510 };
7511 static const unsigned int cl_vco[8] = {
7512 [0] = 3200000,
7513 [1] = 4000000,
7514 [2] = 5333333,
7515 [3] = 6400000,
7516 [4] = 3333333,
7517 [5] = 3566667,
7518 [6] = 4266667,
7519 };
7520 static const unsigned int elk_vco[8] = {
7521 [0] = 3200000,
7522 [1] = 4000000,
7523 [2] = 5333333,
7524 [3] = 4800000,
7525 };
7526 static const unsigned int ctg_vco[8] = {
7527 [0] = 3200000,
7528 [1] = 4000000,
7529 [2] = 5333333,
7530 [3] = 6400000,
7531 [4] = 2666667,
7532 [5] = 4266667,
7533 };
7534 const unsigned int *vco_table;
7535 unsigned int vco;
7536 uint8_t tmp = 0;
7537
7538 /* FIXME other chipsets? */
7539 if (IS_GM45(dev_priv))
7540 vco_table = ctg_vco;
7541 else if (IS_G4X(dev))
7542 vco_table = elk_vco;
7543 else if (IS_CRESTLINE(dev))
7544 vco_table = cl_vco;
7545 else if (IS_PINEVIEW(dev))
7546 vco_table = pnv_vco;
7547 else if (IS_G33(dev))
7548 vco_table = blb_vco;
7549 else
7550 return 0;
7551
7552 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7553
7554 vco = vco_table[tmp & 0x7];
7555 if (vco == 0)
7556 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7557 else
7558 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7559
7560 return vco;
7561 }
7562
7563 static int gm45_get_display_clock_speed(struct drm_device *dev)
7564 {
7565 struct pci_dev *pdev = dev->pdev;
7566 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7567 uint16_t tmp = 0;
7568
7569 pci_read_config_word(pdev, GCFGC, &tmp);
7570
7571 cdclk_sel = (tmp >> 12) & 0x1;
7572
7573 switch (vco) {
7574 case 2666667:
7575 case 4000000:
7576 case 5333333:
7577 return cdclk_sel ? 333333 : 222222;
7578 case 3200000:
7579 return cdclk_sel ? 320000 : 228571;
7580 default:
7581 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7582 return 222222;
7583 }
7584 }
7585
7586 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7587 {
7588 struct pci_dev *pdev = dev->pdev;
7589 static const uint8_t div_3200[] = { 16, 10, 8 };
7590 static const uint8_t div_4000[] = { 20, 12, 10 };
7591 static const uint8_t div_5333[] = { 24, 16, 14 };
7592 const uint8_t *div_table;
7593 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7594 uint16_t tmp = 0;
7595
7596 pci_read_config_word(pdev, GCFGC, &tmp);
7597
7598 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7599
7600 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7601 goto fail;
7602
7603 switch (vco) {
7604 case 3200000:
7605 div_table = div_3200;
7606 break;
7607 case 4000000:
7608 div_table = div_4000;
7609 break;
7610 case 5333333:
7611 div_table = div_5333;
7612 break;
7613 default:
7614 goto fail;
7615 }
7616
7617 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7618
7619 fail:
7620 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7621 return 200000;
7622 }
7623
7624 static int g33_get_display_clock_speed(struct drm_device *dev)
7625 {
7626 struct pci_dev *pdev = dev->pdev;
7627 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7628 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7629 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7630 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7631 const uint8_t *div_table;
7632 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7633 uint16_t tmp = 0;
7634
7635 pci_read_config_word(pdev, GCFGC, &tmp);
7636
7637 cdclk_sel = (tmp >> 4) & 0x7;
7638
7639 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7640 goto fail;
7641
7642 switch (vco) {
7643 case 3200000:
7644 div_table = div_3200;
7645 break;
7646 case 4000000:
7647 div_table = div_4000;
7648 break;
7649 case 4800000:
7650 div_table = div_4800;
7651 break;
7652 case 5333333:
7653 div_table = div_5333;
7654 break;
7655 default:
7656 goto fail;
7657 }
7658
7659 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7660
7661 fail:
7662 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7663 return 190476;
7664 }
7665
7666 static void
7667 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7668 {
7669 while (*num > DATA_LINK_M_N_MASK ||
7670 *den > DATA_LINK_M_N_MASK) {
7671 *num >>= 1;
7672 *den >>= 1;
7673 }
7674 }
7675
7676 static void compute_m_n(unsigned int m, unsigned int n,
7677 uint32_t *ret_m, uint32_t *ret_n)
7678 {
7679 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7680 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7681 intel_reduce_m_n_ratio(ret_m, ret_n);
7682 }
7683
7684 void
7685 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7686 int pixel_clock, int link_clock,
7687 struct intel_link_m_n *m_n)
7688 {
7689 m_n->tu = 64;
7690
7691 compute_m_n(bits_per_pixel * pixel_clock,
7692 link_clock * nlanes * 8,
7693 &m_n->gmch_m, &m_n->gmch_n);
7694
7695 compute_m_n(pixel_clock, link_clock,
7696 &m_n->link_m, &m_n->link_n);
7697 }
7698
7699 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7700 {
7701 if (i915.panel_use_ssc >= 0)
7702 return i915.panel_use_ssc != 0;
7703 return dev_priv->vbt.lvds_use_ssc
7704 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7705 }
7706
7707 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7708 {
7709 return (1 << dpll->n) << 16 | dpll->m2;
7710 }
7711
7712 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7713 {
7714 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7715 }
7716
7717 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7718 struct intel_crtc_state *crtc_state,
7719 struct dpll *reduced_clock)
7720 {
7721 struct drm_device *dev = crtc->base.dev;
7722 u32 fp, fp2 = 0;
7723
7724 if (IS_PINEVIEW(dev)) {
7725 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7726 if (reduced_clock)
7727 fp2 = pnv_dpll_compute_fp(reduced_clock);
7728 } else {
7729 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7730 if (reduced_clock)
7731 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7732 }
7733
7734 crtc_state->dpll_hw_state.fp0 = fp;
7735
7736 crtc->lowfreq_avail = false;
7737 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7738 reduced_clock) {
7739 crtc_state->dpll_hw_state.fp1 = fp2;
7740 crtc->lowfreq_avail = true;
7741 } else {
7742 crtc_state->dpll_hw_state.fp1 = fp;
7743 }
7744 }
7745
7746 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7747 pipe)
7748 {
7749 u32 reg_val;
7750
7751 /*
7752 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7753 * and set it to a reasonable value instead.
7754 */
7755 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7756 reg_val &= 0xffffff00;
7757 reg_val |= 0x00000030;
7758 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7759
7760 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7761 reg_val &= 0x8cffffff;
7762 reg_val = 0x8c000000;
7763 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7764
7765 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7766 reg_val &= 0xffffff00;
7767 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7768
7769 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7770 reg_val &= 0x00ffffff;
7771 reg_val |= 0xb0000000;
7772 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7773 }
7774
7775 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7776 struct intel_link_m_n *m_n)
7777 {
7778 struct drm_device *dev = crtc->base.dev;
7779 struct drm_i915_private *dev_priv = to_i915(dev);
7780 int pipe = crtc->pipe;
7781
7782 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7783 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7784 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7785 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7786 }
7787
7788 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7789 struct intel_link_m_n *m_n,
7790 struct intel_link_m_n *m2_n2)
7791 {
7792 struct drm_device *dev = crtc->base.dev;
7793 struct drm_i915_private *dev_priv = to_i915(dev);
7794 int pipe = crtc->pipe;
7795 enum transcoder transcoder = crtc->config->cpu_transcoder;
7796
7797 if (INTEL_INFO(dev)->gen >= 5) {
7798 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7799 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7800 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7801 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7802 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7803 * for gen < 8) and if DRRS is supported (to make sure the
7804 * registers are not unnecessarily accessed).
7805 */
7806 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7807 crtc->config->has_drrs) {
7808 I915_WRITE(PIPE_DATA_M2(transcoder),
7809 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7810 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7811 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7812 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7813 }
7814 } else {
7815 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7816 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7817 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7818 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7819 }
7820 }
7821
7822 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7823 {
7824 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7825
7826 if (m_n == M1_N1) {
7827 dp_m_n = &crtc->config->dp_m_n;
7828 dp_m2_n2 = &crtc->config->dp_m2_n2;
7829 } else if (m_n == M2_N2) {
7830
7831 /*
7832 * M2_N2 registers are not supported. Hence m2_n2 divider value
7833 * needs to be programmed into M1_N1.
7834 */
7835 dp_m_n = &crtc->config->dp_m2_n2;
7836 } else {
7837 DRM_ERROR("Unsupported divider value\n");
7838 return;
7839 }
7840
7841 if (crtc->config->has_pch_encoder)
7842 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7843 else
7844 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7845 }
7846
7847 static void vlv_compute_dpll(struct intel_crtc *crtc,
7848 struct intel_crtc_state *pipe_config)
7849 {
7850 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7851 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7852 if (crtc->pipe != PIPE_A)
7853 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7854
7855 /* DPLL not used with DSI, but still need the rest set up */
7856 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7857 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7858 DPLL_EXT_BUFFER_ENABLE_VLV;
7859
7860 pipe_config->dpll_hw_state.dpll_md =
7861 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7862 }
7863
7864 static void chv_compute_dpll(struct intel_crtc *crtc,
7865 struct intel_crtc_state *pipe_config)
7866 {
7867 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7868 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7869 if (crtc->pipe != PIPE_A)
7870 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7871
7872 /* DPLL not used with DSI, but still need the rest set up */
7873 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7874 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7875
7876 pipe_config->dpll_hw_state.dpll_md =
7877 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7878 }
7879
7880 static void vlv_prepare_pll(struct intel_crtc *crtc,
7881 const struct intel_crtc_state *pipe_config)
7882 {
7883 struct drm_device *dev = crtc->base.dev;
7884 struct drm_i915_private *dev_priv = to_i915(dev);
7885 enum pipe pipe = crtc->pipe;
7886 u32 mdiv;
7887 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7888 u32 coreclk, reg_val;
7889
7890 /* Enable Refclk */
7891 I915_WRITE(DPLL(pipe),
7892 pipe_config->dpll_hw_state.dpll &
7893 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7894
7895 /* No need to actually set up the DPLL with DSI */
7896 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7897 return;
7898
7899 mutex_lock(&dev_priv->sb_lock);
7900
7901 bestn = pipe_config->dpll.n;
7902 bestm1 = pipe_config->dpll.m1;
7903 bestm2 = pipe_config->dpll.m2;
7904 bestp1 = pipe_config->dpll.p1;
7905 bestp2 = pipe_config->dpll.p2;
7906
7907 /* See eDP HDMI DPIO driver vbios notes doc */
7908
7909 /* PLL B needs special handling */
7910 if (pipe == PIPE_B)
7911 vlv_pllb_recal_opamp(dev_priv, pipe);
7912
7913 /* Set up Tx target for periodic Rcomp update */
7914 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7915
7916 /* Disable target IRef on PLL */
7917 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7918 reg_val &= 0x00ffffff;
7919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7920
7921 /* Disable fast lock */
7922 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7923
7924 /* Set idtafcrecal before PLL is enabled */
7925 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7926 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7927 mdiv |= ((bestn << DPIO_N_SHIFT));
7928 mdiv |= (1 << DPIO_K_SHIFT);
7929
7930 /*
7931 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7932 * but we don't support that).
7933 * Note: don't use the DAC post divider as it seems unstable.
7934 */
7935 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7936 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7937
7938 mdiv |= DPIO_ENABLE_CALIBRATION;
7939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7940
7941 /* Set HBR and RBR LPF coefficients */
7942 if (pipe_config->port_clock == 162000 ||
7943 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7944 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7946 0x009f0003);
7947 else
7948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7949 0x00d0000f);
7950
7951 if (intel_crtc_has_dp_encoder(pipe_config)) {
7952 /* Use SSC source */
7953 if (pipe == PIPE_A)
7954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7955 0x0df40000);
7956 else
7957 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7958 0x0df70000);
7959 } else { /* HDMI or VGA */
7960 /* Use bend source */
7961 if (pipe == PIPE_A)
7962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7963 0x0df70000);
7964 else
7965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7966 0x0df40000);
7967 }
7968
7969 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7970 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7971 if (intel_crtc_has_dp_encoder(crtc->config))
7972 coreclk |= 0x01000000;
7973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7974
7975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7976 mutex_unlock(&dev_priv->sb_lock);
7977 }
7978
7979 static void chv_prepare_pll(struct intel_crtc *crtc,
7980 const struct intel_crtc_state *pipe_config)
7981 {
7982 struct drm_device *dev = crtc->base.dev;
7983 struct drm_i915_private *dev_priv = to_i915(dev);
7984 enum pipe pipe = crtc->pipe;
7985 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7986 u32 loopfilter, tribuf_calcntr;
7987 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7988 u32 dpio_val;
7989 int vco;
7990
7991 /* Enable Refclk and SSC */
7992 I915_WRITE(DPLL(pipe),
7993 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7994
7995 /* No need to actually set up the DPLL with DSI */
7996 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7997 return;
7998
7999 bestn = pipe_config->dpll.n;
8000 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8001 bestm1 = pipe_config->dpll.m1;
8002 bestm2 = pipe_config->dpll.m2 >> 22;
8003 bestp1 = pipe_config->dpll.p1;
8004 bestp2 = pipe_config->dpll.p2;
8005 vco = pipe_config->dpll.vco;
8006 dpio_val = 0;
8007 loopfilter = 0;
8008
8009 mutex_lock(&dev_priv->sb_lock);
8010
8011 /* p1 and p2 divider */
8012 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8013 5 << DPIO_CHV_S1_DIV_SHIFT |
8014 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8015 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8016 1 << DPIO_CHV_K_DIV_SHIFT);
8017
8018 /* Feedback post-divider - m2 */
8019 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8020
8021 /* Feedback refclk divider - n and m1 */
8022 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8023 DPIO_CHV_M1_DIV_BY_2 |
8024 1 << DPIO_CHV_N_DIV_SHIFT);
8025
8026 /* M2 fraction division */
8027 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8028
8029 /* M2 fraction division enable */
8030 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8031 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8032 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8033 if (bestm2_frac)
8034 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8035 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8036
8037 /* Program digital lock detect threshold */
8038 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8039 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8040 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8041 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8042 if (!bestm2_frac)
8043 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8044 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8045
8046 /* Loop filter */
8047 if (vco == 5400000) {
8048 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8049 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8050 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8051 tribuf_calcntr = 0x9;
8052 } else if (vco <= 6200000) {
8053 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8054 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8055 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8056 tribuf_calcntr = 0x9;
8057 } else if (vco <= 6480000) {
8058 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8059 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8060 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8061 tribuf_calcntr = 0x8;
8062 } else {
8063 /* Not supported. Apply the same limits as in the max case */
8064 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8065 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8066 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8067 tribuf_calcntr = 0;
8068 }
8069 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8070
8071 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8072 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8073 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8074 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8075
8076 /* AFC Recal */
8077 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8078 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8079 DPIO_AFC_RECAL);
8080
8081 mutex_unlock(&dev_priv->sb_lock);
8082 }
8083
8084 /**
8085 * vlv_force_pll_on - forcibly enable just the PLL
8086 * @dev_priv: i915 private structure
8087 * @pipe: pipe PLL to enable
8088 * @dpll: PLL configuration
8089 *
8090 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8091 * in cases where we need the PLL enabled even when @pipe is not going to
8092 * be enabled.
8093 */
8094 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8095 const struct dpll *dpll)
8096 {
8097 struct intel_crtc *crtc =
8098 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8099 struct intel_crtc_state *pipe_config;
8100
8101 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8102 if (!pipe_config)
8103 return -ENOMEM;
8104
8105 pipe_config->base.crtc = &crtc->base;
8106 pipe_config->pixel_multiplier = 1;
8107 pipe_config->dpll = *dpll;
8108
8109 if (IS_CHERRYVIEW(dev)) {
8110 chv_compute_dpll(crtc, pipe_config);
8111 chv_prepare_pll(crtc, pipe_config);
8112 chv_enable_pll(crtc, pipe_config);
8113 } else {
8114 vlv_compute_dpll(crtc, pipe_config);
8115 vlv_prepare_pll(crtc, pipe_config);
8116 vlv_enable_pll(crtc, pipe_config);
8117 }
8118
8119 kfree(pipe_config);
8120
8121 return 0;
8122 }
8123
8124 /**
8125 * vlv_force_pll_off - forcibly disable just the PLL
8126 * @dev_priv: i915 private structure
8127 * @pipe: pipe PLL to disable
8128 *
8129 * Disable the PLL for @pipe. To be used in cases where we need
8130 * the PLL enabled even when @pipe is not going to be enabled.
8131 */
8132 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8133 {
8134 if (IS_CHERRYVIEW(dev))
8135 chv_disable_pll(to_i915(dev), pipe);
8136 else
8137 vlv_disable_pll(to_i915(dev), pipe);
8138 }
8139
8140 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8141 struct intel_crtc_state *crtc_state,
8142 struct dpll *reduced_clock)
8143 {
8144 struct drm_device *dev = crtc->base.dev;
8145 struct drm_i915_private *dev_priv = to_i915(dev);
8146 u32 dpll;
8147 struct dpll *clock = &crtc_state->dpll;
8148
8149 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8150
8151 dpll = DPLL_VGA_MODE_DIS;
8152
8153 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8154 dpll |= DPLLB_MODE_LVDS;
8155 else
8156 dpll |= DPLLB_MODE_DAC_SERIAL;
8157
8158 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8159 dpll |= (crtc_state->pixel_multiplier - 1)
8160 << SDVO_MULTIPLIER_SHIFT_HIRES;
8161 }
8162
8163 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8164 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8165 dpll |= DPLL_SDVO_HIGH_SPEED;
8166
8167 if (intel_crtc_has_dp_encoder(crtc_state))
8168 dpll |= DPLL_SDVO_HIGH_SPEED;
8169
8170 /* compute bitmask from p1 value */
8171 if (IS_PINEVIEW(dev))
8172 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8173 else {
8174 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8175 if (IS_G4X(dev) && reduced_clock)
8176 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8177 }
8178 switch (clock->p2) {
8179 case 5:
8180 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8181 break;
8182 case 7:
8183 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8184 break;
8185 case 10:
8186 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8187 break;
8188 case 14:
8189 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8190 break;
8191 }
8192 if (INTEL_INFO(dev)->gen >= 4)
8193 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8194
8195 if (crtc_state->sdvo_tv_clock)
8196 dpll |= PLL_REF_INPUT_TVCLKINBC;
8197 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8198 intel_panel_use_ssc(dev_priv))
8199 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8200 else
8201 dpll |= PLL_REF_INPUT_DREFCLK;
8202
8203 dpll |= DPLL_VCO_ENABLE;
8204 crtc_state->dpll_hw_state.dpll = dpll;
8205
8206 if (INTEL_INFO(dev)->gen >= 4) {
8207 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8208 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8209 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8210 }
8211 }
8212
8213 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8214 struct intel_crtc_state *crtc_state,
8215 struct dpll *reduced_clock)
8216 {
8217 struct drm_device *dev = crtc->base.dev;
8218 struct drm_i915_private *dev_priv = to_i915(dev);
8219 u32 dpll;
8220 struct dpll *clock = &crtc_state->dpll;
8221
8222 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8223
8224 dpll = DPLL_VGA_MODE_DIS;
8225
8226 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8227 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8228 } else {
8229 if (clock->p1 == 2)
8230 dpll |= PLL_P1_DIVIDE_BY_TWO;
8231 else
8232 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8233 if (clock->p2 == 4)
8234 dpll |= PLL_P2_DIVIDE_BY_4;
8235 }
8236
8237 if (!IS_I830(dev_priv) &&
8238 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8239 dpll |= DPLL_DVO_2X_MODE;
8240
8241 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8242 intel_panel_use_ssc(dev_priv))
8243 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8244 else
8245 dpll |= PLL_REF_INPUT_DREFCLK;
8246
8247 dpll |= DPLL_VCO_ENABLE;
8248 crtc_state->dpll_hw_state.dpll = dpll;
8249 }
8250
8251 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8252 {
8253 struct drm_device *dev = intel_crtc->base.dev;
8254 struct drm_i915_private *dev_priv = to_i915(dev);
8255 enum pipe pipe = intel_crtc->pipe;
8256 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8257 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8258 uint32_t crtc_vtotal, crtc_vblank_end;
8259 int vsyncshift = 0;
8260
8261 /* We need to be careful not to changed the adjusted mode, for otherwise
8262 * the hw state checker will get angry at the mismatch. */
8263 crtc_vtotal = adjusted_mode->crtc_vtotal;
8264 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8265
8266 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8267 /* the chip adds 2 halflines automatically */
8268 crtc_vtotal -= 1;
8269 crtc_vblank_end -= 1;
8270
8271 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8272 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8273 else
8274 vsyncshift = adjusted_mode->crtc_hsync_start -
8275 adjusted_mode->crtc_htotal / 2;
8276 if (vsyncshift < 0)
8277 vsyncshift += adjusted_mode->crtc_htotal;
8278 }
8279
8280 if (INTEL_INFO(dev)->gen > 3)
8281 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8282
8283 I915_WRITE(HTOTAL(cpu_transcoder),
8284 (adjusted_mode->crtc_hdisplay - 1) |
8285 ((adjusted_mode->crtc_htotal - 1) << 16));
8286 I915_WRITE(HBLANK(cpu_transcoder),
8287 (adjusted_mode->crtc_hblank_start - 1) |
8288 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8289 I915_WRITE(HSYNC(cpu_transcoder),
8290 (adjusted_mode->crtc_hsync_start - 1) |
8291 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8292
8293 I915_WRITE(VTOTAL(cpu_transcoder),
8294 (adjusted_mode->crtc_vdisplay - 1) |
8295 ((crtc_vtotal - 1) << 16));
8296 I915_WRITE(VBLANK(cpu_transcoder),
8297 (adjusted_mode->crtc_vblank_start - 1) |
8298 ((crtc_vblank_end - 1) << 16));
8299 I915_WRITE(VSYNC(cpu_transcoder),
8300 (adjusted_mode->crtc_vsync_start - 1) |
8301 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8302
8303 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8304 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8305 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8306 * bits. */
8307 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8308 (pipe == PIPE_B || pipe == PIPE_C))
8309 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8310
8311 }
8312
8313 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8314 {
8315 struct drm_device *dev = intel_crtc->base.dev;
8316 struct drm_i915_private *dev_priv = to_i915(dev);
8317 enum pipe pipe = intel_crtc->pipe;
8318
8319 /* pipesrc controls the size that is scaled from, which should
8320 * always be the user's requested size.
8321 */
8322 I915_WRITE(PIPESRC(pipe),
8323 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8324 (intel_crtc->config->pipe_src_h - 1));
8325 }
8326
8327 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8328 struct intel_crtc_state *pipe_config)
8329 {
8330 struct drm_device *dev = crtc->base.dev;
8331 struct drm_i915_private *dev_priv = to_i915(dev);
8332 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8333 uint32_t tmp;
8334
8335 tmp = I915_READ(HTOTAL(cpu_transcoder));
8336 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8337 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8338 tmp = I915_READ(HBLANK(cpu_transcoder));
8339 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8340 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8341 tmp = I915_READ(HSYNC(cpu_transcoder));
8342 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8343 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8344
8345 tmp = I915_READ(VTOTAL(cpu_transcoder));
8346 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8347 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8348 tmp = I915_READ(VBLANK(cpu_transcoder));
8349 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8350 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8351 tmp = I915_READ(VSYNC(cpu_transcoder));
8352 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8353 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8354
8355 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8356 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8357 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8358 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8359 }
8360 }
8361
8362 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8363 struct intel_crtc_state *pipe_config)
8364 {
8365 struct drm_device *dev = crtc->base.dev;
8366 struct drm_i915_private *dev_priv = to_i915(dev);
8367 u32 tmp;
8368
8369 tmp = I915_READ(PIPESRC(crtc->pipe));
8370 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8371 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8372
8373 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8374 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8375 }
8376
8377 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8378 struct intel_crtc_state *pipe_config)
8379 {
8380 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8381 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8382 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8383 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8384
8385 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8386 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8387 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8388 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8389
8390 mode->flags = pipe_config->base.adjusted_mode.flags;
8391 mode->type = DRM_MODE_TYPE_DRIVER;
8392
8393 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8394 mode->flags |= pipe_config->base.adjusted_mode.flags;
8395
8396 mode->hsync = drm_mode_hsync(mode);
8397 mode->vrefresh = drm_mode_vrefresh(mode);
8398 drm_mode_set_name(mode);
8399 }
8400
8401 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8402 {
8403 struct drm_device *dev = intel_crtc->base.dev;
8404 struct drm_i915_private *dev_priv = to_i915(dev);
8405 uint32_t pipeconf;
8406
8407 pipeconf = 0;
8408
8409 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8410 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8411 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8412
8413 if (intel_crtc->config->double_wide)
8414 pipeconf |= PIPECONF_DOUBLE_WIDE;
8415
8416 /* only g4x and later have fancy bpc/dither controls */
8417 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8418 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8419 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8420 pipeconf |= PIPECONF_DITHER_EN |
8421 PIPECONF_DITHER_TYPE_SP;
8422
8423 switch (intel_crtc->config->pipe_bpp) {
8424 case 18:
8425 pipeconf |= PIPECONF_6BPC;
8426 break;
8427 case 24:
8428 pipeconf |= PIPECONF_8BPC;
8429 break;
8430 case 30:
8431 pipeconf |= PIPECONF_10BPC;
8432 break;
8433 default:
8434 /* Case prevented by intel_choose_pipe_bpp_dither. */
8435 BUG();
8436 }
8437 }
8438
8439 if (HAS_PIPE_CXSR(dev)) {
8440 if (intel_crtc->lowfreq_avail) {
8441 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8442 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8443 } else {
8444 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8445 }
8446 }
8447
8448 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8449 if (INTEL_INFO(dev)->gen < 4 ||
8450 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8451 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8452 else
8453 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8454 } else
8455 pipeconf |= PIPECONF_PROGRESSIVE;
8456
8457 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8458 intel_crtc->config->limited_color_range)
8459 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8460
8461 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8462 POSTING_READ(PIPECONF(intel_crtc->pipe));
8463 }
8464
8465 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8466 struct intel_crtc_state *crtc_state)
8467 {
8468 struct drm_device *dev = crtc->base.dev;
8469 struct drm_i915_private *dev_priv = to_i915(dev);
8470 const struct intel_limit *limit;
8471 int refclk = 48000;
8472
8473 memset(&crtc_state->dpll_hw_state, 0,
8474 sizeof(crtc_state->dpll_hw_state));
8475
8476 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8477 if (intel_panel_use_ssc(dev_priv)) {
8478 refclk = dev_priv->vbt.lvds_ssc_freq;
8479 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8480 }
8481
8482 limit = &intel_limits_i8xx_lvds;
8483 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8484 limit = &intel_limits_i8xx_dvo;
8485 } else {
8486 limit = &intel_limits_i8xx_dac;
8487 }
8488
8489 if (!crtc_state->clock_set &&
8490 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8491 refclk, NULL, &crtc_state->dpll)) {
8492 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8493 return -EINVAL;
8494 }
8495
8496 i8xx_compute_dpll(crtc, crtc_state, NULL);
8497
8498 return 0;
8499 }
8500
8501 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8502 struct intel_crtc_state *crtc_state)
8503 {
8504 struct drm_device *dev = crtc->base.dev;
8505 struct drm_i915_private *dev_priv = to_i915(dev);
8506 const struct intel_limit *limit;
8507 int refclk = 96000;
8508
8509 memset(&crtc_state->dpll_hw_state, 0,
8510 sizeof(crtc_state->dpll_hw_state));
8511
8512 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8513 if (intel_panel_use_ssc(dev_priv)) {
8514 refclk = dev_priv->vbt.lvds_ssc_freq;
8515 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8516 }
8517
8518 if (intel_is_dual_link_lvds(dev))
8519 limit = &intel_limits_g4x_dual_channel_lvds;
8520 else
8521 limit = &intel_limits_g4x_single_channel_lvds;
8522 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8523 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8524 limit = &intel_limits_g4x_hdmi;
8525 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8526 limit = &intel_limits_g4x_sdvo;
8527 } else {
8528 /* The option is for other outputs */
8529 limit = &intel_limits_i9xx_sdvo;
8530 }
8531
8532 if (!crtc_state->clock_set &&
8533 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8534 refclk, NULL, &crtc_state->dpll)) {
8535 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8536 return -EINVAL;
8537 }
8538
8539 i9xx_compute_dpll(crtc, crtc_state, NULL);
8540
8541 return 0;
8542 }
8543
8544 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8545 struct intel_crtc_state *crtc_state)
8546 {
8547 struct drm_device *dev = crtc->base.dev;
8548 struct drm_i915_private *dev_priv = to_i915(dev);
8549 const struct intel_limit *limit;
8550 int refclk = 96000;
8551
8552 memset(&crtc_state->dpll_hw_state, 0,
8553 sizeof(crtc_state->dpll_hw_state));
8554
8555 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8556 if (intel_panel_use_ssc(dev_priv)) {
8557 refclk = dev_priv->vbt.lvds_ssc_freq;
8558 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8559 }
8560
8561 limit = &intel_limits_pineview_lvds;
8562 } else {
8563 limit = &intel_limits_pineview_sdvo;
8564 }
8565
8566 if (!crtc_state->clock_set &&
8567 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8568 refclk, NULL, &crtc_state->dpll)) {
8569 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8570 return -EINVAL;
8571 }
8572
8573 i9xx_compute_dpll(crtc, crtc_state, NULL);
8574
8575 return 0;
8576 }
8577
8578 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8579 struct intel_crtc_state *crtc_state)
8580 {
8581 struct drm_device *dev = crtc->base.dev;
8582 struct drm_i915_private *dev_priv = to_i915(dev);
8583 const struct intel_limit *limit;
8584 int refclk = 96000;
8585
8586 memset(&crtc_state->dpll_hw_state, 0,
8587 sizeof(crtc_state->dpll_hw_state));
8588
8589 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8590 if (intel_panel_use_ssc(dev_priv)) {
8591 refclk = dev_priv->vbt.lvds_ssc_freq;
8592 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8593 }
8594
8595 limit = &intel_limits_i9xx_lvds;
8596 } else {
8597 limit = &intel_limits_i9xx_sdvo;
8598 }
8599
8600 if (!crtc_state->clock_set &&
8601 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8602 refclk, NULL, &crtc_state->dpll)) {
8603 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8604 return -EINVAL;
8605 }
8606
8607 i9xx_compute_dpll(crtc, crtc_state, NULL);
8608
8609 return 0;
8610 }
8611
8612 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8613 struct intel_crtc_state *crtc_state)
8614 {
8615 int refclk = 100000;
8616 const struct intel_limit *limit = &intel_limits_chv;
8617
8618 memset(&crtc_state->dpll_hw_state, 0,
8619 sizeof(crtc_state->dpll_hw_state));
8620
8621 if (!crtc_state->clock_set &&
8622 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8623 refclk, NULL, &crtc_state->dpll)) {
8624 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8625 return -EINVAL;
8626 }
8627
8628 chv_compute_dpll(crtc, crtc_state);
8629
8630 return 0;
8631 }
8632
8633 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8634 struct intel_crtc_state *crtc_state)
8635 {
8636 int refclk = 100000;
8637 const struct intel_limit *limit = &intel_limits_vlv;
8638
8639 memset(&crtc_state->dpll_hw_state, 0,
8640 sizeof(crtc_state->dpll_hw_state));
8641
8642 if (!crtc_state->clock_set &&
8643 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8644 refclk, NULL, &crtc_state->dpll)) {
8645 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8646 return -EINVAL;
8647 }
8648
8649 vlv_compute_dpll(crtc, crtc_state);
8650
8651 return 0;
8652 }
8653
8654 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8655 struct intel_crtc_state *pipe_config)
8656 {
8657 struct drm_device *dev = crtc->base.dev;
8658 struct drm_i915_private *dev_priv = to_i915(dev);
8659 uint32_t tmp;
8660
8661 if (INTEL_GEN(dev_priv) <= 3 &&
8662 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8663 return;
8664
8665 tmp = I915_READ(PFIT_CONTROL);
8666 if (!(tmp & PFIT_ENABLE))
8667 return;
8668
8669 /* Check whether the pfit is attached to our pipe. */
8670 if (INTEL_INFO(dev)->gen < 4) {
8671 if (crtc->pipe != PIPE_B)
8672 return;
8673 } else {
8674 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8675 return;
8676 }
8677
8678 pipe_config->gmch_pfit.control = tmp;
8679 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8680 }
8681
8682 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8683 struct intel_crtc_state *pipe_config)
8684 {
8685 struct drm_device *dev = crtc->base.dev;
8686 struct drm_i915_private *dev_priv = to_i915(dev);
8687 int pipe = pipe_config->cpu_transcoder;
8688 struct dpll clock;
8689 u32 mdiv;
8690 int refclk = 100000;
8691
8692 /* In case of DSI, DPLL will not be used */
8693 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8694 return;
8695
8696 mutex_lock(&dev_priv->sb_lock);
8697 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8698 mutex_unlock(&dev_priv->sb_lock);
8699
8700 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8701 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8702 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8703 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8704 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8705
8706 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8707 }
8708
8709 static void
8710 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8711 struct intel_initial_plane_config *plane_config)
8712 {
8713 struct drm_device *dev = crtc->base.dev;
8714 struct drm_i915_private *dev_priv = to_i915(dev);
8715 u32 val, base, offset;
8716 int pipe = crtc->pipe, plane = crtc->plane;
8717 int fourcc, pixel_format;
8718 unsigned int aligned_height;
8719 struct drm_framebuffer *fb;
8720 struct intel_framebuffer *intel_fb;
8721
8722 val = I915_READ(DSPCNTR(plane));
8723 if (!(val & DISPLAY_PLANE_ENABLE))
8724 return;
8725
8726 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8727 if (!intel_fb) {
8728 DRM_DEBUG_KMS("failed to alloc fb\n");
8729 return;
8730 }
8731
8732 fb = &intel_fb->base;
8733
8734 if (INTEL_INFO(dev)->gen >= 4) {
8735 if (val & DISPPLANE_TILED) {
8736 plane_config->tiling = I915_TILING_X;
8737 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8738 }
8739 }
8740
8741 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8742 fourcc = i9xx_format_to_fourcc(pixel_format);
8743 fb->pixel_format = fourcc;
8744 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8745
8746 if (INTEL_INFO(dev)->gen >= 4) {
8747 if (plane_config->tiling)
8748 offset = I915_READ(DSPTILEOFF(plane));
8749 else
8750 offset = I915_READ(DSPLINOFF(plane));
8751 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8752 } else {
8753 base = I915_READ(DSPADDR(plane));
8754 }
8755 plane_config->base = base;
8756
8757 val = I915_READ(PIPESRC(pipe));
8758 fb->width = ((val >> 16) & 0xfff) + 1;
8759 fb->height = ((val >> 0) & 0xfff) + 1;
8760
8761 val = I915_READ(DSPSTRIDE(pipe));
8762 fb->pitches[0] = val & 0xffffffc0;
8763
8764 aligned_height = intel_fb_align_height(dev, fb->height,
8765 fb->pixel_format,
8766 fb->modifier[0]);
8767
8768 plane_config->size = fb->pitches[0] * aligned_height;
8769
8770 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8771 pipe_name(pipe), plane, fb->width, fb->height,
8772 fb->bits_per_pixel, base, fb->pitches[0],
8773 plane_config->size);
8774
8775 plane_config->fb = intel_fb;
8776 }
8777
8778 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8779 struct intel_crtc_state *pipe_config)
8780 {
8781 struct drm_device *dev = crtc->base.dev;
8782 struct drm_i915_private *dev_priv = to_i915(dev);
8783 int pipe = pipe_config->cpu_transcoder;
8784 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8785 struct dpll clock;
8786 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8787 int refclk = 100000;
8788
8789 /* In case of DSI, DPLL will not be used */
8790 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8791 return;
8792
8793 mutex_lock(&dev_priv->sb_lock);
8794 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8795 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8796 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8797 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8798 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8799 mutex_unlock(&dev_priv->sb_lock);
8800
8801 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8802 clock.m2 = (pll_dw0 & 0xff) << 22;
8803 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8804 clock.m2 |= pll_dw2 & 0x3fffff;
8805 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8806 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8807 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8808
8809 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8810 }
8811
8812 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8813 struct intel_crtc_state *pipe_config)
8814 {
8815 struct drm_device *dev = crtc->base.dev;
8816 struct drm_i915_private *dev_priv = to_i915(dev);
8817 enum intel_display_power_domain power_domain;
8818 uint32_t tmp;
8819 bool ret;
8820
8821 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8822 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8823 return false;
8824
8825 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8826 pipe_config->shared_dpll = NULL;
8827
8828 ret = false;
8829
8830 tmp = I915_READ(PIPECONF(crtc->pipe));
8831 if (!(tmp & PIPECONF_ENABLE))
8832 goto out;
8833
8834 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8835 switch (tmp & PIPECONF_BPC_MASK) {
8836 case PIPECONF_6BPC:
8837 pipe_config->pipe_bpp = 18;
8838 break;
8839 case PIPECONF_8BPC:
8840 pipe_config->pipe_bpp = 24;
8841 break;
8842 case PIPECONF_10BPC:
8843 pipe_config->pipe_bpp = 30;
8844 break;
8845 default:
8846 break;
8847 }
8848 }
8849
8850 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8851 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8852 pipe_config->limited_color_range = true;
8853
8854 if (INTEL_INFO(dev)->gen < 4)
8855 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8856
8857 intel_get_pipe_timings(crtc, pipe_config);
8858 intel_get_pipe_src_size(crtc, pipe_config);
8859
8860 i9xx_get_pfit_config(crtc, pipe_config);
8861
8862 if (INTEL_INFO(dev)->gen >= 4) {
8863 /* No way to read it out on pipes B and C */
8864 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8865 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8866 else
8867 tmp = I915_READ(DPLL_MD(crtc->pipe));
8868 pipe_config->pixel_multiplier =
8869 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8870 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8871 pipe_config->dpll_hw_state.dpll_md = tmp;
8872 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8873 IS_G33(dev_priv)) {
8874 tmp = I915_READ(DPLL(crtc->pipe));
8875 pipe_config->pixel_multiplier =
8876 ((tmp & SDVO_MULTIPLIER_MASK)
8877 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8878 } else {
8879 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8880 * port and will be fixed up in the encoder->get_config
8881 * function. */
8882 pipe_config->pixel_multiplier = 1;
8883 }
8884 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8885 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8886 /*
8887 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8888 * on 830. Filter it out here so that we don't
8889 * report errors due to that.
8890 */
8891 if (IS_I830(dev_priv))
8892 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8893
8894 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8895 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8896 } else {
8897 /* Mask out read-only status bits. */
8898 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8899 DPLL_PORTC_READY_MASK |
8900 DPLL_PORTB_READY_MASK);
8901 }
8902
8903 if (IS_CHERRYVIEW(dev))
8904 chv_crtc_clock_get(crtc, pipe_config);
8905 else if (IS_VALLEYVIEW(dev))
8906 vlv_crtc_clock_get(crtc, pipe_config);
8907 else
8908 i9xx_crtc_clock_get(crtc, pipe_config);
8909
8910 /*
8911 * Normally the dotclock is filled in by the encoder .get_config()
8912 * but in case the pipe is enabled w/o any ports we need a sane
8913 * default.
8914 */
8915 pipe_config->base.adjusted_mode.crtc_clock =
8916 pipe_config->port_clock / pipe_config->pixel_multiplier;
8917
8918 ret = true;
8919
8920 out:
8921 intel_display_power_put(dev_priv, power_domain);
8922
8923 return ret;
8924 }
8925
8926 static void ironlake_init_pch_refclk(struct drm_device *dev)
8927 {
8928 struct drm_i915_private *dev_priv = to_i915(dev);
8929 struct intel_encoder *encoder;
8930 int i;
8931 u32 val, final;
8932 bool has_lvds = false;
8933 bool has_cpu_edp = false;
8934 bool has_panel = false;
8935 bool has_ck505 = false;
8936 bool can_ssc = false;
8937 bool using_ssc_source = false;
8938
8939 /* We need to take the global config into account */
8940 for_each_intel_encoder(dev, encoder) {
8941 switch (encoder->type) {
8942 case INTEL_OUTPUT_LVDS:
8943 has_panel = true;
8944 has_lvds = true;
8945 break;
8946 case INTEL_OUTPUT_EDP:
8947 has_panel = true;
8948 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8949 has_cpu_edp = true;
8950 break;
8951 default:
8952 break;
8953 }
8954 }
8955
8956 if (HAS_PCH_IBX(dev_priv)) {
8957 has_ck505 = dev_priv->vbt.display_clock_mode;
8958 can_ssc = has_ck505;
8959 } else {
8960 has_ck505 = false;
8961 can_ssc = true;
8962 }
8963
8964 /* Check if any DPLLs are using the SSC source */
8965 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8966 u32 temp = I915_READ(PCH_DPLL(i));
8967
8968 if (!(temp & DPLL_VCO_ENABLE))
8969 continue;
8970
8971 if ((temp & PLL_REF_INPUT_MASK) ==
8972 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8973 using_ssc_source = true;
8974 break;
8975 }
8976 }
8977
8978 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8979 has_panel, has_lvds, has_ck505, using_ssc_source);
8980
8981 /* Ironlake: try to setup display ref clock before DPLL
8982 * enabling. This is only under driver's control after
8983 * PCH B stepping, previous chipset stepping should be
8984 * ignoring this setting.
8985 */
8986 val = I915_READ(PCH_DREF_CONTROL);
8987
8988 /* As we must carefully and slowly disable/enable each source in turn,
8989 * compute the final state we want first and check if we need to
8990 * make any changes at all.
8991 */
8992 final = val;
8993 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8994 if (has_ck505)
8995 final |= DREF_NONSPREAD_CK505_ENABLE;
8996 else
8997 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8998
8999 final &= ~DREF_SSC_SOURCE_MASK;
9000 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9001 final &= ~DREF_SSC1_ENABLE;
9002
9003 if (has_panel) {
9004 final |= DREF_SSC_SOURCE_ENABLE;
9005
9006 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9007 final |= DREF_SSC1_ENABLE;
9008
9009 if (has_cpu_edp) {
9010 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9011 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9012 else
9013 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9014 } else
9015 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9016 } else if (using_ssc_source) {
9017 final |= DREF_SSC_SOURCE_ENABLE;
9018 final |= DREF_SSC1_ENABLE;
9019 }
9020
9021 if (final == val)
9022 return;
9023
9024 /* Always enable nonspread source */
9025 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9026
9027 if (has_ck505)
9028 val |= DREF_NONSPREAD_CK505_ENABLE;
9029 else
9030 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9031
9032 if (has_panel) {
9033 val &= ~DREF_SSC_SOURCE_MASK;
9034 val |= DREF_SSC_SOURCE_ENABLE;
9035
9036 /* SSC must be turned on before enabling the CPU output */
9037 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9038 DRM_DEBUG_KMS("Using SSC on panel\n");
9039 val |= DREF_SSC1_ENABLE;
9040 } else
9041 val &= ~DREF_SSC1_ENABLE;
9042
9043 /* Get SSC going before enabling the outputs */
9044 I915_WRITE(PCH_DREF_CONTROL, val);
9045 POSTING_READ(PCH_DREF_CONTROL);
9046 udelay(200);
9047
9048 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9049
9050 /* Enable CPU source on CPU attached eDP */
9051 if (has_cpu_edp) {
9052 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9053 DRM_DEBUG_KMS("Using SSC on eDP\n");
9054 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9055 } else
9056 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9057 } else
9058 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9059
9060 I915_WRITE(PCH_DREF_CONTROL, val);
9061 POSTING_READ(PCH_DREF_CONTROL);
9062 udelay(200);
9063 } else {
9064 DRM_DEBUG_KMS("Disabling CPU source output\n");
9065
9066 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9067
9068 /* Turn off CPU output */
9069 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9070
9071 I915_WRITE(PCH_DREF_CONTROL, val);
9072 POSTING_READ(PCH_DREF_CONTROL);
9073 udelay(200);
9074
9075 if (!using_ssc_source) {
9076 DRM_DEBUG_KMS("Disabling SSC source\n");
9077
9078 /* Turn off the SSC source */
9079 val &= ~DREF_SSC_SOURCE_MASK;
9080 val |= DREF_SSC_SOURCE_DISABLE;
9081
9082 /* Turn off SSC1 */
9083 val &= ~DREF_SSC1_ENABLE;
9084
9085 I915_WRITE(PCH_DREF_CONTROL, val);
9086 POSTING_READ(PCH_DREF_CONTROL);
9087 udelay(200);
9088 }
9089 }
9090
9091 BUG_ON(val != final);
9092 }
9093
9094 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9095 {
9096 uint32_t tmp;
9097
9098 tmp = I915_READ(SOUTH_CHICKEN2);
9099 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9100 I915_WRITE(SOUTH_CHICKEN2, tmp);
9101
9102 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9103 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9104 DRM_ERROR("FDI mPHY reset assert timeout\n");
9105
9106 tmp = I915_READ(SOUTH_CHICKEN2);
9107 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9108 I915_WRITE(SOUTH_CHICKEN2, tmp);
9109
9110 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9111 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9112 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9113 }
9114
9115 /* WaMPhyProgramming:hsw */
9116 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9117 {
9118 uint32_t tmp;
9119
9120 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9121 tmp &= ~(0xFF << 24);
9122 tmp |= (0x12 << 24);
9123 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9124
9125 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9126 tmp |= (1 << 11);
9127 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9128
9129 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9130 tmp |= (1 << 11);
9131 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9132
9133 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9134 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9135 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9136
9137 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9138 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9139 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9140
9141 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9142 tmp &= ~(7 << 13);
9143 tmp |= (5 << 13);
9144 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9145
9146 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9147 tmp &= ~(7 << 13);
9148 tmp |= (5 << 13);
9149 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9150
9151 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9152 tmp &= ~0xFF;
9153 tmp |= 0x1C;
9154 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9155
9156 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9157 tmp &= ~0xFF;
9158 tmp |= 0x1C;
9159 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9160
9161 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9162 tmp &= ~(0xFF << 16);
9163 tmp |= (0x1C << 16);
9164 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9165
9166 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9167 tmp &= ~(0xFF << 16);
9168 tmp |= (0x1C << 16);
9169 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9170
9171 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9172 tmp |= (1 << 27);
9173 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9174
9175 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9176 tmp |= (1 << 27);
9177 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9178
9179 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9180 tmp &= ~(0xF << 28);
9181 tmp |= (4 << 28);
9182 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9183
9184 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9185 tmp &= ~(0xF << 28);
9186 tmp |= (4 << 28);
9187 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9188 }
9189
9190 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9191 * Programming" based on the parameters passed:
9192 * - Sequence to enable CLKOUT_DP
9193 * - Sequence to enable CLKOUT_DP without spread
9194 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9195 */
9196 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9197 bool with_fdi)
9198 {
9199 struct drm_i915_private *dev_priv = to_i915(dev);
9200 uint32_t reg, tmp;
9201
9202 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9203 with_spread = true;
9204 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9205 with_fdi, "LP PCH doesn't have FDI\n"))
9206 with_fdi = false;
9207
9208 mutex_lock(&dev_priv->sb_lock);
9209
9210 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9211 tmp &= ~SBI_SSCCTL_DISABLE;
9212 tmp |= SBI_SSCCTL_PATHALT;
9213 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9214
9215 udelay(24);
9216
9217 if (with_spread) {
9218 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9219 tmp &= ~SBI_SSCCTL_PATHALT;
9220 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9221
9222 if (with_fdi) {
9223 lpt_reset_fdi_mphy(dev_priv);
9224 lpt_program_fdi_mphy(dev_priv);
9225 }
9226 }
9227
9228 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9229 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9230 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9231 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9232
9233 mutex_unlock(&dev_priv->sb_lock);
9234 }
9235
9236 /* Sequence to disable CLKOUT_DP */
9237 static void lpt_disable_clkout_dp(struct drm_device *dev)
9238 {
9239 struct drm_i915_private *dev_priv = to_i915(dev);
9240 uint32_t reg, tmp;
9241
9242 mutex_lock(&dev_priv->sb_lock);
9243
9244 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9245 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9246 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9247 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9248
9249 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9250 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9251 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9252 tmp |= SBI_SSCCTL_PATHALT;
9253 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9254 udelay(32);
9255 }
9256 tmp |= SBI_SSCCTL_DISABLE;
9257 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9258 }
9259
9260 mutex_unlock(&dev_priv->sb_lock);
9261 }
9262
9263 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9264
9265 static const uint16_t sscdivintphase[] = {
9266 [BEND_IDX( 50)] = 0x3B23,
9267 [BEND_IDX( 45)] = 0x3B23,
9268 [BEND_IDX( 40)] = 0x3C23,
9269 [BEND_IDX( 35)] = 0x3C23,
9270 [BEND_IDX( 30)] = 0x3D23,
9271 [BEND_IDX( 25)] = 0x3D23,
9272 [BEND_IDX( 20)] = 0x3E23,
9273 [BEND_IDX( 15)] = 0x3E23,
9274 [BEND_IDX( 10)] = 0x3F23,
9275 [BEND_IDX( 5)] = 0x3F23,
9276 [BEND_IDX( 0)] = 0x0025,
9277 [BEND_IDX( -5)] = 0x0025,
9278 [BEND_IDX(-10)] = 0x0125,
9279 [BEND_IDX(-15)] = 0x0125,
9280 [BEND_IDX(-20)] = 0x0225,
9281 [BEND_IDX(-25)] = 0x0225,
9282 [BEND_IDX(-30)] = 0x0325,
9283 [BEND_IDX(-35)] = 0x0325,
9284 [BEND_IDX(-40)] = 0x0425,
9285 [BEND_IDX(-45)] = 0x0425,
9286 [BEND_IDX(-50)] = 0x0525,
9287 };
9288
9289 /*
9290 * Bend CLKOUT_DP
9291 * steps -50 to 50 inclusive, in steps of 5
9292 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9293 * change in clock period = -(steps / 10) * 5.787 ps
9294 */
9295 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9296 {
9297 uint32_t tmp;
9298 int idx = BEND_IDX(steps);
9299
9300 if (WARN_ON(steps % 5 != 0))
9301 return;
9302
9303 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9304 return;
9305
9306 mutex_lock(&dev_priv->sb_lock);
9307
9308 if (steps % 10 != 0)
9309 tmp = 0xAAAAAAAB;
9310 else
9311 tmp = 0x00000000;
9312 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9313
9314 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9315 tmp &= 0xffff0000;
9316 tmp |= sscdivintphase[idx];
9317 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9318
9319 mutex_unlock(&dev_priv->sb_lock);
9320 }
9321
9322 #undef BEND_IDX
9323
9324 static void lpt_init_pch_refclk(struct drm_device *dev)
9325 {
9326 struct intel_encoder *encoder;
9327 bool has_vga = false;
9328
9329 for_each_intel_encoder(dev, encoder) {
9330 switch (encoder->type) {
9331 case INTEL_OUTPUT_ANALOG:
9332 has_vga = true;
9333 break;
9334 default:
9335 break;
9336 }
9337 }
9338
9339 if (has_vga) {
9340 lpt_bend_clkout_dp(to_i915(dev), 0);
9341 lpt_enable_clkout_dp(dev, true, true);
9342 } else {
9343 lpt_disable_clkout_dp(dev);
9344 }
9345 }
9346
9347 /*
9348 * Initialize reference clocks when the driver loads
9349 */
9350 void intel_init_pch_refclk(struct drm_device *dev)
9351 {
9352 struct drm_i915_private *dev_priv = to_i915(dev);
9353
9354 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9355 ironlake_init_pch_refclk(dev);
9356 else if (HAS_PCH_LPT(dev_priv))
9357 lpt_init_pch_refclk(dev);
9358 }
9359
9360 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9361 {
9362 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9364 int pipe = intel_crtc->pipe;
9365 uint32_t val;
9366
9367 val = 0;
9368
9369 switch (intel_crtc->config->pipe_bpp) {
9370 case 18:
9371 val |= PIPECONF_6BPC;
9372 break;
9373 case 24:
9374 val |= PIPECONF_8BPC;
9375 break;
9376 case 30:
9377 val |= PIPECONF_10BPC;
9378 break;
9379 case 36:
9380 val |= PIPECONF_12BPC;
9381 break;
9382 default:
9383 /* Case prevented by intel_choose_pipe_bpp_dither. */
9384 BUG();
9385 }
9386
9387 if (intel_crtc->config->dither)
9388 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9389
9390 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9391 val |= PIPECONF_INTERLACED_ILK;
9392 else
9393 val |= PIPECONF_PROGRESSIVE;
9394
9395 if (intel_crtc->config->limited_color_range)
9396 val |= PIPECONF_COLOR_RANGE_SELECT;
9397
9398 I915_WRITE(PIPECONF(pipe), val);
9399 POSTING_READ(PIPECONF(pipe));
9400 }
9401
9402 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9403 {
9404 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9406 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9407 u32 val = 0;
9408
9409 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9410 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9411
9412 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9413 val |= PIPECONF_INTERLACED_ILK;
9414 else
9415 val |= PIPECONF_PROGRESSIVE;
9416
9417 I915_WRITE(PIPECONF(cpu_transcoder), val);
9418 POSTING_READ(PIPECONF(cpu_transcoder));
9419 }
9420
9421 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9422 {
9423 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9425
9426 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9427 u32 val = 0;
9428
9429 switch (intel_crtc->config->pipe_bpp) {
9430 case 18:
9431 val |= PIPEMISC_DITHER_6_BPC;
9432 break;
9433 case 24:
9434 val |= PIPEMISC_DITHER_8_BPC;
9435 break;
9436 case 30:
9437 val |= PIPEMISC_DITHER_10_BPC;
9438 break;
9439 case 36:
9440 val |= PIPEMISC_DITHER_12_BPC;
9441 break;
9442 default:
9443 /* Case prevented by pipe_config_set_bpp. */
9444 BUG();
9445 }
9446
9447 if (intel_crtc->config->dither)
9448 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9449
9450 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9451 }
9452 }
9453
9454 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9455 {
9456 /*
9457 * Account for spread spectrum to avoid
9458 * oversubscribing the link. Max center spread
9459 * is 2.5%; use 5% for safety's sake.
9460 */
9461 u32 bps = target_clock * bpp * 21 / 20;
9462 return DIV_ROUND_UP(bps, link_bw * 8);
9463 }
9464
9465 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9466 {
9467 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9468 }
9469
9470 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9471 struct intel_crtc_state *crtc_state,
9472 struct dpll *reduced_clock)
9473 {
9474 struct drm_crtc *crtc = &intel_crtc->base;
9475 struct drm_device *dev = crtc->dev;
9476 struct drm_i915_private *dev_priv = to_i915(dev);
9477 u32 dpll, fp, fp2;
9478 int factor;
9479
9480 /* Enable autotuning of the PLL clock (if permissible) */
9481 factor = 21;
9482 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9483 if ((intel_panel_use_ssc(dev_priv) &&
9484 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9485 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9486 factor = 25;
9487 } else if (crtc_state->sdvo_tv_clock)
9488 factor = 20;
9489
9490 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9491
9492 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9493 fp |= FP_CB_TUNE;
9494
9495 if (reduced_clock) {
9496 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9497
9498 if (reduced_clock->m < factor * reduced_clock->n)
9499 fp2 |= FP_CB_TUNE;
9500 } else {
9501 fp2 = fp;
9502 }
9503
9504 dpll = 0;
9505
9506 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9507 dpll |= DPLLB_MODE_LVDS;
9508 else
9509 dpll |= DPLLB_MODE_DAC_SERIAL;
9510
9511 dpll |= (crtc_state->pixel_multiplier - 1)
9512 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9513
9514 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9515 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9516 dpll |= DPLL_SDVO_HIGH_SPEED;
9517
9518 if (intel_crtc_has_dp_encoder(crtc_state))
9519 dpll |= DPLL_SDVO_HIGH_SPEED;
9520
9521 /*
9522 * The high speed IO clock is only really required for
9523 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9524 * possible to share the DPLL between CRT and HDMI. Enabling
9525 * the clock needlessly does no real harm, except use up a
9526 * bit of power potentially.
9527 *
9528 * We'll limit this to IVB with 3 pipes, since it has only two
9529 * DPLLs and so DPLL sharing is the only way to get three pipes
9530 * driving PCH ports at the same time. On SNB we could do this,
9531 * and potentially avoid enabling the second DPLL, but it's not
9532 * clear if it''s a win or loss power wise. No point in doing
9533 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9534 */
9535 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9536 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9537 dpll |= DPLL_SDVO_HIGH_SPEED;
9538
9539 /* compute bitmask from p1 value */
9540 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9541 /* also FPA1 */
9542 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9543
9544 switch (crtc_state->dpll.p2) {
9545 case 5:
9546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9547 break;
9548 case 7:
9549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9550 break;
9551 case 10:
9552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9553 break;
9554 case 14:
9555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9556 break;
9557 }
9558
9559 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9560 intel_panel_use_ssc(dev_priv))
9561 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9562 else
9563 dpll |= PLL_REF_INPUT_DREFCLK;
9564
9565 dpll |= DPLL_VCO_ENABLE;
9566
9567 crtc_state->dpll_hw_state.dpll = dpll;
9568 crtc_state->dpll_hw_state.fp0 = fp;
9569 crtc_state->dpll_hw_state.fp1 = fp2;
9570 }
9571
9572 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9573 struct intel_crtc_state *crtc_state)
9574 {
9575 struct drm_device *dev = crtc->base.dev;
9576 struct drm_i915_private *dev_priv = to_i915(dev);
9577 struct dpll reduced_clock;
9578 bool has_reduced_clock = false;
9579 struct intel_shared_dpll *pll;
9580 const struct intel_limit *limit;
9581 int refclk = 120000;
9582
9583 memset(&crtc_state->dpll_hw_state, 0,
9584 sizeof(crtc_state->dpll_hw_state));
9585
9586 crtc->lowfreq_avail = false;
9587
9588 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9589 if (!crtc_state->has_pch_encoder)
9590 return 0;
9591
9592 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9593 if (intel_panel_use_ssc(dev_priv)) {
9594 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9595 dev_priv->vbt.lvds_ssc_freq);
9596 refclk = dev_priv->vbt.lvds_ssc_freq;
9597 }
9598
9599 if (intel_is_dual_link_lvds(dev)) {
9600 if (refclk == 100000)
9601 limit = &intel_limits_ironlake_dual_lvds_100m;
9602 else
9603 limit = &intel_limits_ironlake_dual_lvds;
9604 } else {
9605 if (refclk == 100000)
9606 limit = &intel_limits_ironlake_single_lvds_100m;
9607 else
9608 limit = &intel_limits_ironlake_single_lvds;
9609 }
9610 } else {
9611 limit = &intel_limits_ironlake_dac;
9612 }
9613
9614 if (!crtc_state->clock_set &&
9615 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9616 refclk, NULL, &crtc_state->dpll)) {
9617 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9618 return -EINVAL;
9619 }
9620
9621 ironlake_compute_dpll(crtc, crtc_state,
9622 has_reduced_clock ? &reduced_clock : NULL);
9623
9624 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9625 if (pll == NULL) {
9626 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9627 pipe_name(crtc->pipe));
9628 return -EINVAL;
9629 }
9630
9631 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9632 has_reduced_clock)
9633 crtc->lowfreq_avail = true;
9634
9635 return 0;
9636 }
9637
9638 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9639 struct intel_link_m_n *m_n)
9640 {
9641 struct drm_device *dev = crtc->base.dev;
9642 struct drm_i915_private *dev_priv = to_i915(dev);
9643 enum pipe pipe = crtc->pipe;
9644
9645 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9646 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9647 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9648 & ~TU_SIZE_MASK;
9649 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9650 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9651 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9652 }
9653
9654 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9655 enum transcoder transcoder,
9656 struct intel_link_m_n *m_n,
9657 struct intel_link_m_n *m2_n2)
9658 {
9659 struct drm_device *dev = crtc->base.dev;
9660 struct drm_i915_private *dev_priv = to_i915(dev);
9661 enum pipe pipe = crtc->pipe;
9662
9663 if (INTEL_INFO(dev)->gen >= 5) {
9664 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9665 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9666 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9667 & ~TU_SIZE_MASK;
9668 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9669 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9670 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9671 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9672 * gen < 8) and if DRRS is supported (to make sure the
9673 * registers are not unnecessarily read).
9674 */
9675 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9676 crtc->config->has_drrs) {
9677 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9678 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9679 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9680 & ~TU_SIZE_MASK;
9681 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9682 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9683 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9684 }
9685 } else {
9686 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9687 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9688 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9689 & ~TU_SIZE_MASK;
9690 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9691 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9692 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9693 }
9694 }
9695
9696 void intel_dp_get_m_n(struct intel_crtc *crtc,
9697 struct intel_crtc_state *pipe_config)
9698 {
9699 if (pipe_config->has_pch_encoder)
9700 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9701 else
9702 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9703 &pipe_config->dp_m_n,
9704 &pipe_config->dp_m2_n2);
9705 }
9706
9707 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9708 struct intel_crtc_state *pipe_config)
9709 {
9710 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9711 &pipe_config->fdi_m_n, NULL);
9712 }
9713
9714 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9715 struct intel_crtc_state *pipe_config)
9716 {
9717 struct drm_device *dev = crtc->base.dev;
9718 struct drm_i915_private *dev_priv = to_i915(dev);
9719 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9720 uint32_t ps_ctrl = 0;
9721 int id = -1;
9722 int i;
9723
9724 /* find scaler attached to this pipe */
9725 for (i = 0; i < crtc->num_scalers; i++) {
9726 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9727 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9728 id = i;
9729 pipe_config->pch_pfit.enabled = true;
9730 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9731 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9732 break;
9733 }
9734 }
9735
9736 scaler_state->scaler_id = id;
9737 if (id >= 0) {
9738 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9739 } else {
9740 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9741 }
9742 }
9743
9744 static void
9745 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9746 struct intel_initial_plane_config *plane_config)
9747 {
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = to_i915(dev);
9750 u32 val, base, offset, stride_mult, tiling;
9751 int pipe = crtc->pipe;
9752 int fourcc, pixel_format;
9753 unsigned int aligned_height;
9754 struct drm_framebuffer *fb;
9755 struct intel_framebuffer *intel_fb;
9756
9757 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9758 if (!intel_fb) {
9759 DRM_DEBUG_KMS("failed to alloc fb\n");
9760 return;
9761 }
9762
9763 fb = &intel_fb->base;
9764
9765 val = I915_READ(PLANE_CTL(pipe, 0));
9766 if (!(val & PLANE_CTL_ENABLE))
9767 goto error;
9768
9769 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9770 fourcc = skl_format_to_fourcc(pixel_format,
9771 val & PLANE_CTL_ORDER_RGBX,
9772 val & PLANE_CTL_ALPHA_MASK);
9773 fb->pixel_format = fourcc;
9774 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9775
9776 tiling = val & PLANE_CTL_TILED_MASK;
9777 switch (tiling) {
9778 case PLANE_CTL_TILED_LINEAR:
9779 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9780 break;
9781 case PLANE_CTL_TILED_X:
9782 plane_config->tiling = I915_TILING_X;
9783 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9784 break;
9785 case PLANE_CTL_TILED_Y:
9786 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9787 break;
9788 case PLANE_CTL_TILED_YF:
9789 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9790 break;
9791 default:
9792 MISSING_CASE(tiling);
9793 goto error;
9794 }
9795
9796 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9797 plane_config->base = base;
9798
9799 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9800
9801 val = I915_READ(PLANE_SIZE(pipe, 0));
9802 fb->height = ((val >> 16) & 0xfff) + 1;
9803 fb->width = ((val >> 0) & 0x1fff) + 1;
9804
9805 val = I915_READ(PLANE_STRIDE(pipe, 0));
9806 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9807 fb->pixel_format);
9808 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9809
9810 aligned_height = intel_fb_align_height(dev, fb->height,
9811 fb->pixel_format,
9812 fb->modifier[0]);
9813
9814 plane_config->size = fb->pitches[0] * aligned_height;
9815
9816 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9817 pipe_name(pipe), fb->width, fb->height,
9818 fb->bits_per_pixel, base, fb->pitches[0],
9819 plane_config->size);
9820
9821 plane_config->fb = intel_fb;
9822 return;
9823
9824 error:
9825 kfree(intel_fb);
9826 }
9827
9828 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9829 struct intel_crtc_state *pipe_config)
9830 {
9831 struct drm_device *dev = crtc->base.dev;
9832 struct drm_i915_private *dev_priv = to_i915(dev);
9833 uint32_t tmp;
9834
9835 tmp = I915_READ(PF_CTL(crtc->pipe));
9836
9837 if (tmp & PF_ENABLE) {
9838 pipe_config->pch_pfit.enabled = true;
9839 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9840 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9841
9842 /* We currently do not free assignements of panel fitters on
9843 * ivb/hsw (since we don't use the higher upscaling modes which
9844 * differentiates them) so just WARN about this case for now. */
9845 if (IS_GEN7(dev)) {
9846 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9847 PF_PIPE_SEL_IVB(crtc->pipe));
9848 }
9849 }
9850 }
9851
9852 static void
9853 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9854 struct intel_initial_plane_config *plane_config)
9855 {
9856 struct drm_device *dev = crtc->base.dev;
9857 struct drm_i915_private *dev_priv = to_i915(dev);
9858 u32 val, base, offset;
9859 int pipe = crtc->pipe;
9860 int fourcc, pixel_format;
9861 unsigned int aligned_height;
9862 struct drm_framebuffer *fb;
9863 struct intel_framebuffer *intel_fb;
9864
9865 val = I915_READ(DSPCNTR(pipe));
9866 if (!(val & DISPLAY_PLANE_ENABLE))
9867 return;
9868
9869 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9870 if (!intel_fb) {
9871 DRM_DEBUG_KMS("failed to alloc fb\n");
9872 return;
9873 }
9874
9875 fb = &intel_fb->base;
9876
9877 if (INTEL_INFO(dev)->gen >= 4) {
9878 if (val & DISPPLANE_TILED) {
9879 plane_config->tiling = I915_TILING_X;
9880 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9881 }
9882 }
9883
9884 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9885 fourcc = i9xx_format_to_fourcc(pixel_format);
9886 fb->pixel_format = fourcc;
9887 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9888
9889 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9890 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9891 offset = I915_READ(DSPOFFSET(pipe));
9892 } else {
9893 if (plane_config->tiling)
9894 offset = I915_READ(DSPTILEOFF(pipe));
9895 else
9896 offset = I915_READ(DSPLINOFF(pipe));
9897 }
9898 plane_config->base = base;
9899
9900 val = I915_READ(PIPESRC(pipe));
9901 fb->width = ((val >> 16) & 0xfff) + 1;
9902 fb->height = ((val >> 0) & 0xfff) + 1;
9903
9904 val = I915_READ(DSPSTRIDE(pipe));
9905 fb->pitches[0] = val & 0xffffffc0;
9906
9907 aligned_height = intel_fb_align_height(dev, fb->height,
9908 fb->pixel_format,
9909 fb->modifier[0]);
9910
9911 plane_config->size = fb->pitches[0] * aligned_height;
9912
9913 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9914 pipe_name(pipe), fb->width, fb->height,
9915 fb->bits_per_pixel, base, fb->pitches[0],
9916 plane_config->size);
9917
9918 plane_config->fb = intel_fb;
9919 }
9920
9921 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9922 struct intel_crtc_state *pipe_config)
9923 {
9924 struct drm_device *dev = crtc->base.dev;
9925 struct drm_i915_private *dev_priv = to_i915(dev);
9926 enum intel_display_power_domain power_domain;
9927 uint32_t tmp;
9928 bool ret;
9929
9930 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9931 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9932 return false;
9933
9934 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9935 pipe_config->shared_dpll = NULL;
9936
9937 ret = false;
9938 tmp = I915_READ(PIPECONF(crtc->pipe));
9939 if (!(tmp & PIPECONF_ENABLE))
9940 goto out;
9941
9942 switch (tmp & PIPECONF_BPC_MASK) {
9943 case PIPECONF_6BPC:
9944 pipe_config->pipe_bpp = 18;
9945 break;
9946 case PIPECONF_8BPC:
9947 pipe_config->pipe_bpp = 24;
9948 break;
9949 case PIPECONF_10BPC:
9950 pipe_config->pipe_bpp = 30;
9951 break;
9952 case PIPECONF_12BPC:
9953 pipe_config->pipe_bpp = 36;
9954 break;
9955 default:
9956 break;
9957 }
9958
9959 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9960 pipe_config->limited_color_range = true;
9961
9962 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9963 struct intel_shared_dpll *pll;
9964 enum intel_dpll_id pll_id;
9965
9966 pipe_config->has_pch_encoder = true;
9967
9968 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9969 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9970 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9971
9972 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9973
9974 if (HAS_PCH_IBX(dev_priv)) {
9975 /*
9976 * The pipe->pch transcoder and pch transcoder->pll
9977 * mapping is fixed.
9978 */
9979 pll_id = (enum intel_dpll_id) crtc->pipe;
9980 } else {
9981 tmp = I915_READ(PCH_DPLL_SEL);
9982 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9983 pll_id = DPLL_ID_PCH_PLL_B;
9984 else
9985 pll_id= DPLL_ID_PCH_PLL_A;
9986 }
9987
9988 pipe_config->shared_dpll =
9989 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9990 pll = pipe_config->shared_dpll;
9991
9992 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9993 &pipe_config->dpll_hw_state));
9994
9995 tmp = pipe_config->dpll_hw_state.dpll;
9996 pipe_config->pixel_multiplier =
9997 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9998 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9999
10000 ironlake_pch_clock_get(crtc, pipe_config);
10001 } else {
10002 pipe_config->pixel_multiplier = 1;
10003 }
10004
10005 intel_get_pipe_timings(crtc, pipe_config);
10006 intel_get_pipe_src_size(crtc, pipe_config);
10007
10008 ironlake_get_pfit_config(crtc, pipe_config);
10009
10010 ret = true;
10011
10012 out:
10013 intel_display_power_put(dev_priv, power_domain);
10014
10015 return ret;
10016 }
10017
10018 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10019 {
10020 struct drm_device *dev = &dev_priv->drm;
10021 struct intel_crtc *crtc;
10022
10023 for_each_intel_crtc(dev, crtc)
10024 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10025 pipe_name(crtc->pipe));
10026
10027 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10028 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10029 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10030 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10031 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10032 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10033 "CPU PWM1 enabled\n");
10034 if (IS_HASWELL(dev_priv))
10035 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10036 "CPU PWM2 enabled\n");
10037 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10038 "PCH PWM1 enabled\n");
10039 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10040 "Utility pin enabled\n");
10041 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10042
10043 /*
10044 * In theory we can still leave IRQs enabled, as long as only the HPD
10045 * interrupts remain enabled. We used to check for that, but since it's
10046 * gen-specific and since we only disable LCPLL after we fully disable
10047 * the interrupts, the check below should be enough.
10048 */
10049 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10050 }
10051
10052 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10053 {
10054 if (IS_HASWELL(dev_priv))
10055 return I915_READ(D_COMP_HSW);
10056 else
10057 return I915_READ(D_COMP_BDW);
10058 }
10059
10060 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10061 {
10062 if (IS_HASWELL(dev_priv)) {
10063 mutex_lock(&dev_priv->rps.hw_lock);
10064 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10065 val))
10066 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10067 mutex_unlock(&dev_priv->rps.hw_lock);
10068 } else {
10069 I915_WRITE(D_COMP_BDW, val);
10070 POSTING_READ(D_COMP_BDW);
10071 }
10072 }
10073
10074 /*
10075 * This function implements pieces of two sequences from BSpec:
10076 * - Sequence for display software to disable LCPLL
10077 * - Sequence for display software to allow package C8+
10078 * The steps implemented here are just the steps that actually touch the LCPLL
10079 * register. Callers should take care of disabling all the display engine
10080 * functions, doing the mode unset, fixing interrupts, etc.
10081 */
10082 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10083 bool switch_to_fclk, bool allow_power_down)
10084 {
10085 uint32_t val;
10086
10087 assert_can_disable_lcpll(dev_priv);
10088
10089 val = I915_READ(LCPLL_CTL);
10090
10091 if (switch_to_fclk) {
10092 val |= LCPLL_CD_SOURCE_FCLK;
10093 I915_WRITE(LCPLL_CTL, val);
10094
10095 if (wait_for_us(I915_READ(LCPLL_CTL) &
10096 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10097 DRM_ERROR("Switching to FCLK failed\n");
10098
10099 val = I915_READ(LCPLL_CTL);
10100 }
10101
10102 val |= LCPLL_PLL_DISABLE;
10103 I915_WRITE(LCPLL_CTL, val);
10104 POSTING_READ(LCPLL_CTL);
10105
10106 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10107 DRM_ERROR("LCPLL still locked\n");
10108
10109 val = hsw_read_dcomp(dev_priv);
10110 val |= D_COMP_COMP_DISABLE;
10111 hsw_write_dcomp(dev_priv, val);
10112 ndelay(100);
10113
10114 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10115 1))
10116 DRM_ERROR("D_COMP RCOMP still in progress\n");
10117
10118 if (allow_power_down) {
10119 val = I915_READ(LCPLL_CTL);
10120 val |= LCPLL_POWER_DOWN_ALLOW;
10121 I915_WRITE(LCPLL_CTL, val);
10122 POSTING_READ(LCPLL_CTL);
10123 }
10124 }
10125
10126 /*
10127 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10128 * source.
10129 */
10130 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10131 {
10132 uint32_t val;
10133
10134 val = I915_READ(LCPLL_CTL);
10135
10136 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10137 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10138 return;
10139
10140 /*
10141 * Make sure we're not on PC8 state before disabling PC8, otherwise
10142 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10143 */
10144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10145
10146 if (val & LCPLL_POWER_DOWN_ALLOW) {
10147 val &= ~LCPLL_POWER_DOWN_ALLOW;
10148 I915_WRITE(LCPLL_CTL, val);
10149 POSTING_READ(LCPLL_CTL);
10150 }
10151
10152 val = hsw_read_dcomp(dev_priv);
10153 val |= D_COMP_COMP_FORCE;
10154 val &= ~D_COMP_COMP_DISABLE;
10155 hsw_write_dcomp(dev_priv, val);
10156
10157 val = I915_READ(LCPLL_CTL);
10158 val &= ~LCPLL_PLL_DISABLE;
10159 I915_WRITE(LCPLL_CTL, val);
10160
10161 if (intel_wait_for_register(dev_priv,
10162 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10163 5))
10164 DRM_ERROR("LCPLL not locked yet\n");
10165
10166 if (val & LCPLL_CD_SOURCE_FCLK) {
10167 val = I915_READ(LCPLL_CTL);
10168 val &= ~LCPLL_CD_SOURCE_FCLK;
10169 I915_WRITE(LCPLL_CTL, val);
10170
10171 if (wait_for_us((I915_READ(LCPLL_CTL) &
10172 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10173 DRM_ERROR("Switching back to LCPLL failed\n");
10174 }
10175
10176 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10177 intel_update_cdclk(&dev_priv->drm);
10178 }
10179
10180 /*
10181 * Package states C8 and deeper are really deep PC states that can only be
10182 * reached when all the devices on the system allow it, so even if the graphics
10183 * device allows PC8+, it doesn't mean the system will actually get to these
10184 * states. Our driver only allows PC8+ when going into runtime PM.
10185 *
10186 * The requirements for PC8+ are that all the outputs are disabled, the power
10187 * well is disabled and most interrupts are disabled, and these are also
10188 * requirements for runtime PM. When these conditions are met, we manually do
10189 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10190 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10191 * hang the machine.
10192 *
10193 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10194 * the state of some registers, so when we come back from PC8+ we need to
10195 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10196 * need to take care of the registers kept by RC6. Notice that this happens even
10197 * if we don't put the device in PCI D3 state (which is what currently happens
10198 * because of the runtime PM support).
10199 *
10200 * For more, read "Display Sequences for Package C8" on the hardware
10201 * documentation.
10202 */
10203 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10204 {
10205 struct drm_device *dev = &dev_priv->drm;
10206 uint32_t val;
10207
10208 DRM_DEBUG_KMS("Enabling package C8+\n");
10209
10210 if (HAS_PCH_LPT_LP(dev_priv)) {
10211 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10212 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10213 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10214 }
10215
10216 lpt_disable_clkout_dp(dev);
10217 hsw_disable_lcpll(dev_priv, true, true);
10218 }
10219
10220 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10221 {
10222 struct drm_device *dev = &dev_priv->drm;
10223 uint32_t val;
10224
10225 DRM_DEBUG_KMS("Disabling package C8+\n");
10226
10227 hsw_restore_lcpll(dev_priv);
10228 lpt_init_pch_refclk(dev);
10229
10230 if (HAS_PCH_LPT_LP(dev_priv)) {
10231 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10232 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10233 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10234 }
10235 }
10236
10237 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10238 {
10239 struct drm_device *dev = old_state->dev;
10240 struct intel_atomic_state *old_intel_state =
10241 to_intel_atomic_state(old_state);
10242 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10243
10244 bxt_set_cdclk(to_i915(dev), req_cdclk);
10245 }
10246
10247 /* compute the max rate for new configuration */
10248 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10249 {
10250 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10251 struct drm_i915_private *dev_priv = to_i915(state->dev);
10252 struct drm_crtc *crtc;
10253 struct drm_crtc_state *cstate;
10254 struct intel_crtc_state *crtc_state;
10255 unsigned max_pixel_rate = 0, i;
10256 enum pipe pipe;
10257
10258 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10259 sizeof(intel_state->min_pixclk));
10260
10261 for_each_crtc_in_state(state, crtc, cstate, i) {
10262 int pixel_rate;
10263
10264 crtc_state = to_intel_crtc_state(cstate);
10265 if (!crtc_state->base.enable) {
10266 intel_state->min_pixclk[i] = 0;
10267 continue;
10268 }
10269
10270 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10271
10272 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10273 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10274 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10275
10276 intel_state->min_pixclk[i] = pixel_rate;
10277 }
10278
10279 for_each_pipe(dev_priv, pipe)
10280 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10281
10282 return max_pixel_rate;
10283 }
10284
10285 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10286 {
10287 struct drm_i915_private *dev_priv = to_i915(dev);
10288 uint32_t val, data;
10289 int ret;
10290
10291 if (WARN((I915_READ(LCPLL_CTL) &
10292 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10293 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10294 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10295 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10296 "trying to change cdclk frequency with cdclk not enabled\n"))
10297 return;
10298
10299 mutex_lock(&dev_priv->rps.hw_lock);
10300 ret = sandybridge_pcode_write(dev_priv,
10301 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10302 mutex_unlock(&dev_priv->rps.hw_lock);
10303 if (ret) {
10304 DRM_ERROR("failed to inform pcode about cdclk change\n");
10305 return;
10306 }
10307
10308 val = I915_READ(LCPLL_CTL);
10309 val |= LCPLL_CD_SOURCE_FCLK;
10310 I915_WRITE(LCPLL_CTL, val);
10311
10312 if (wait_for_us(I915_READ(LCPLL_CTL) &
10313 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10314 DRM_ERROR("Switching to FCLK failed\n");
10315
10316 val = I915_READ(LCPLL_CTL);
10317 val &= ~LCPLL_CLK_FREQ_MASK;
10318
10319 switch (cdclk) {
10320 case 450000:
10321 val |= LCPLL_CLK_FREQ_450;
10322 data = 0;
10323 break;
10324 case 540000:
10325 val |= LCPLL_CLK_FREQ_54O_BDW;
10326 data = 1;
10327 break;
10328 case 337500:
10329 val |= LCPLL_CLK_FREQ_337_5_BDW;
10330 data = 2;
10331 break;
10332 case 675000:
10333 val |= LCPLL_CLK_FREQ_675_BDW;
10334 data = 3;
10335 break;
10336 default:
10337 WARN(1, "invalid cdclk frequency\n");
10338 return;
10339 }
10340
10341 I915_WRITE(LCPLL_CTL, val);
10342
10343 val = I915_READ(LCPLL_CTL);
10344 val &= ~LCPLL_CD_SOURCE_FCLK;
10345 I915_WRITE(LCPLL_CTL, val);
10346
10347 if (wait_for_us((I915_READ(LCPLL_CTL) &
10348 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10349 DRM_ERROR("Switching back to LCPLL failed\n");
10350
10351 mutex_lock(&dev_priv->rps.hw_lock);
10352 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10353 mutex_unlock(&dev_priv->rps.hw_lock);
10354
10355 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10356
10357 intel_update_cdclk(dev);
10358
10359 WARN(cdclk != dev_priv->cdclk_freq,
10360 "cdclk requested %d kHz but got %d kHz\n",
10361 cdclk, dev_priv->cdclk_freq);
10362 }
10363
10364 static int broadwell_calc_cdclk(int max_pixclk)
10365 {
10366 if (max_pixclk > 540000)
10367 return 675000;
10368 else if (max_pixclk > 450000)
10369 return 540000;
10370 else if (max_pixclk > 337500)
10371 return 450000;
10372 else
10373 return 337500;
10374 }
10375
10376 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10377 {
10378 struct drm_i915_private *dev_priv = to_i915(state->dev);
10379 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10380 int max_pixclk = ilk_max_pixel_rate(state);
10381 int cdclk;
10382
10383 /*
10384 * FIXME should also account for plane ratio
10385 * once 64bpp pixel formats are supported.
10386 */
10387 cdclk = broadwell_calc_cdclk(max_pixclk);
10388
10389 if (cdclk > dev_priv->max_cdclk_freq) {
10390 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10391 cdclk, dev_priv->max_cdclk_freq);
10392 return -EINVAL;
10393 }
10394
10395 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10396 if (!intel_state->active_crtcs)
10397 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10398
10399 return 0;
10400 }
10401
10402 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10403 {
10404 struct drm_device *dev = old_state->dev;
10405 struct intel_atomic_state *old_intel_state =
10406 to_intel_atomic_state(old_state);
10407 unsigned req_cdclk = old_intel_state->dev_cdclk;
10408
10409 broadwell_set_cdclk(dev, req_cdclk);
10410 }
10411
10412 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10413 {
10414 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10415 struct drm_i915_private *dev_priv = to_i915(state->dev);
10416 const int max_pixclk = ilk_max_pixel_rate(state);
10417 int vco = intel_state->cdclk_pll_vco;
10418 int cdclk;
10419
10420 /*
10421 * FIXME should also account for plane ratio
10422 * once 64bpp pixel formats are supported.
10423 */
10424 cdclk = skl_calc_cdclk(max_pixclk, vco);
10425
10426 /*
10427 * FIXME move the cdclk caclulation to
10428 * compute_config() so we can fail gracegully.
10429 */
10430 if (cdclk > dev_priv->max_cdclk_freq) {
10431 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10432 cdclk, dev_priv->max_cdclk_freq);
10433 cdclk = dev_priv->max_cdclk_freq;
10434 }
10435
10436 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10437 if (!intel_state->active_crtcs)
10438 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10439
10440 return 0;
10441 }
10442
10443 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10444 {
10445 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10446 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10447 unsigned int req_cdclk = intel_state->dev_cdclk;
10448 unsigned int req_vco = intel_state->cdclk_pll_vco;
10449
10450 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10451 }
10452
10453 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10454 struct intel_crtc_state *crtc_state)
10455 {
10456 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10457 if (!intel_ddi_pll_select(crtc, crtc_state))
10458 return -EINVAL;
10459 }
10460
10461 crtc->lowfreq_avail = false;
10462
10463 return 0;
10464 }
10465
10466 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10467 enum port port,
10468 struct intel_crtc_state *pipe_config)
10469 {
10470 enum intel_dpll_id id;
10471
10472 switch (port) {
10473 case PORT_A:
10474 id = DPLL_ID_SKL_DPLL0;
10475 break;
10476 case PORT_B:
10477 id = DPLL_ID_SKL_DPLL1;
10478 break;
10479 case PORT_C:
10480 id = DPLL_ID_SKL_DPLL2;
10481 break;
10482 default:
10483 DRM_ERROR("Incorrect port type\n");
10484 return;
10485 }
10486
10487 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10488 }
10489
10490 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10491 enum port port,
10492 struct intel_crtc_state *pipe_config)
10493 {
10494 enum intel_dpll_id id;
10495 u32 temp;
10496
10497 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10498 id = temp >> (port * 3 + 1);
10499
10500 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10501 return;
10502
10503 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10504 }
10505
10506 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10507 enum port port,
10508 struct intel_crtc_state *pipe_config)
10509 {
10510 enum intel_dpll_id id;
10511 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10512
10513 switch (ddi_pll_sel) {
10514 case PORT_CLK_SEL_WRPLL1:
10515 id = DPLL_ID_WRPLL1;
10516 break;
10517 case PORT_CLK_SEL_WRPLL2:
10518 id = DPLL_ID_WRPLL2;
10519 break;
10520 case PORT_CLK_SEL_SPLL:
10521 id = DPLL_ID_SPLL;
10522 break;
10523 case PORT_CLK_SEL_LCPLL_810:
10524 id = DPLL_ID_LCPLL_810;
10525 break;
10526 case PORT_CLK_SEL_LCPLL_1350:
10527 id = DPLL_ID_LCPLL_1350;
10528 break;
10529 case PORT_CLK_SEL_LCPLL_2700:
10530 id = DPLL_ID_LCPLL_2700;
10531 break;
10532 default:
10533 MISSING_CASE(ddi_pll_sel);
10534 /* fall through */
10535 case PORT_CLK_SEL_NONE:
10536 return;
10537 }
10538
10539 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10540 }
10541
10542 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10543 struct intel_crtc_state *pipe_config,
10544 unsigned long *power_domain_mask)
10545 {
10546 struct drm_device *dev = crtc->base.dev;
10547 struct drm_i915_private *dev_priv = to_i915(dev);
10548 enum intel_display_power_domain power_domain;
10549 u32 tmp;
10550
10551 /*
10552 * The pipe->transcoder mapping is fixed with the exception of the eDP
10553 * transcoder handled below.
10554 */
10555 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10556
10557 /*
10558 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10559 * consistency and less surprising code; it's in always on power).
10560 */
10561 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10562 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10563 enum pipe trans_edp_pipe;
10564 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10565 default:
10566 WARN(1, "unknown pipe linked to edp transcoder\n");
10567 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10568 case TRANS_DDI_EDP_INPUT_A_ON:
10569 trans_edp_pipe = PIPE_A;
10570 break;
10571 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10572 trans_edp_pipe = PIPE_B;
10573 break;
10574 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10575 trans_edp_pipe = PIPE_C;
10576 break;
10577 }
10578
10579 if (trans_edp_pipe == crtc->pipe)
10580 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10581 }
10582
10583 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10584 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10585 return false;
10586 *power_domain_mask |= BIT(power_domain);
10587
10588 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10589
10590 return tmp & PIPECONF_ENABLE;
10591 }
10592
10593 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10594 struct intel_crtc_state *pipe_config,
10595 unsigned long *power_domain_mask)
10596 {
10597 struct drm_device *dev = crtc->base.dev;
10598 struct drm_i915_private *dev_priv = to_i915(dev);
10599 enum intel_display_power_domain power_domain;
10600 enum port port;
10601 enum transcoder cpu_transcoder;
10602 u32 tmp;
10603
10604 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10605 if (port == PORT_A)
10606 cpu_transcoder = TRANSCODER_DSI_A;
10607 else
10608 cpu_transcoder = TRANSCODER_DSI_C;
10609
10610 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10611 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10612 continue;
10613 *power_domain_mask |= BIT(power_domain);
10614
10615 /*
10616 * The PLL needs to be enabled with a valid divider
10617 * configuration, otherwise accessing DSI registers will hang
10618 * the machine. See BSpec North Display Engine
10619 * registers/MIPI[BXT]. We can break out here early, since we
10620 * need the same DSI PLL to be enabled for both DSI ports.
10621 */
10622 if (!intel_dsi_pll_is_enabled(dev_priv))
10623 break;
10624
10625 /* XXX: this works for video mode only */
10626 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10627 if (!(tmp & DPI_ENABLE))
10628 continue;
10629
10630 tmp = I915_READ(MIPI_CTRL(port));
10631 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10632 continue;
10633
10634 pipe_config->cpu_transcoder = cpu_transcoder;
10635 break;
10636 }
10637
10638 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10639 }
10640
10641 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10642 struct intel_crtc_state *pipe_config)
10643 {
10644 struct drm_device *dev = crtc->base.dev;
10645 struct drm_i915_private *dev_priv = to_i915(dev);
10646 struct intel_shared_dpll *pll;
10647 enum port port;
10648 uint32_t tmp;
10649
10650 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10651
10652 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10653
10654 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10655 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10656 else if (IS_BROXTON(dev_priv))
10657 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10658 else
10659 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10660
10661 pll = pipe_config->shared_dpll;
10662 if (pll) {
10663 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10664 &pipe_config->dpll_hw_state));
10665 }
10666
10667 /*
10668 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10669 * DDI E. So just check whether this pipe is wired to DDI E and whether
10670 * the PCH transcoder is on.
10671 */
10672 if (INTEL_INFO(dev)->gen < 9 &&
10673 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10674 pipe_config->has_pch_encoder = true;
10675
10676 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10677 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10678 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10679
10680 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10681 }
10682 }
10683
10684 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10685 struct intel_crtc_state *pipe_config)
10686 {
10687 struct drm_device *dev = crtc->base.dev;
10688 struct drm_i915_private *dev_priv = to_i915(dev);
10689 enum intel_display_power_domain power_domain;
10690 unsigned long power_domain_mask;
10691 bool active;
10692
10693 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10694 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10695 return false;
10696 power_domain_mask = BIT(power_domain);
10697
10698 pipe_config->shared_dpll = NULL;
10699
10700 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10701
10702 if (IS_BROXTON(dev_priv) &&
10703 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10704 WARN_ON(active);
10705 active = true;
10706 }
10707
10708 if (!active)
10709 goto out;
10710
10711 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10712 haswell_get_ddi_port_state(crtc, pipe_config);
10713 intel_get_pipe_timings(crtc, pipe_config);
10714 }
10715
10716 intel_get_pipe_src_size(crtc, pipe_config);
10717
10718 pipe_config->gamma_mode =
10719 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10720
10721 if (INTEL_INFO(dev)->gen >= 9) {
10722 skl_init_scalers(dev, crtc, pipe_config);
10723 }
10724
10725 if (INTEL_INFO(dev)->gen >= 9) {
10726 pipe_config->scaler_state.scaler_id = -1;
10727 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10728 }
10729
10730 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10731 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10732 power_domain_mask |= BIT(power_domain);
10733 if (INTEL_INFO(dev)->gen >= 9)
10734 skylake_get_pfit_config(crtc, pipe_config);
10735 else
10736 ironlake_get_pfit_config(crtc, pipe_config);
10737 }
10738
10739 if (IS_HASWELL(dev_priv))
10740 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10741 (I915_READ(IPS_CTL) & IPS_ENABLE);
10742
10743 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10744 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10745 pipe_config->pixel_multiplier =
10746 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10747 } else {
10748 pipe_config->pixel_multiplier = 1;
10749 }
10750
10751 out:
10752 for_each_power_domain(power_domain, power_domain_mask)
10753 intel_display_power_put(dev_priv, power_domain);
10754
10755 return active;
10756 }
10757
10758 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10759 const struct intel_plane_state *plane_state)
10760 {
10761 struct drm_device *dev = crtc->dev;
10762 struct drm_i915_private *dev_priv = to_i915(dev);
10763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10764 uint32_t cntl = 0, size = 0;
10765
10766 if (plane_state && plane_state->base.visible) {
10767 unsigned int width = plane_state->base.crtc_w;
10768 unsigned int height = plane_state->base.crtc_h;
10769 unsigned int stride = roundup_pow_of_two(width) * 4;
10770
10771 switch (stride) {
10772 default:
10773 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10774 width, stride);
10775 stride = 256;
10776 /* fallthrough */
10777 case 256:
10778 case 512:
10779 case 1024:
10780 case 2048:
10781 break;
10782 }
10783
10784 cntl |= CURSOR_ENABLE |
10785 CURSOR_GAMMA_ENABLE |
10786 CURSOR_FORMAT_ARGB |
10787 CURSOR_STRIDE(stride);
10788
10789 size = (height << 12) | width;
10790 }
10791
10792 if (intel_crtc->cursor_cntl != 0 &&
10793 (intel_crtc->cursor_base != base ||
10794 intel_crtc->cursor_size != size ||
10795 intel_crtc->cursor_cntl != cntl)) {
10796 /* On these chipsets we can only modify the base/size/stride
10797 * whilst the cursor is disabled.
10798 */
10799 I915_WRITE(CURCNTR(PIPE_A), 0);
10800 POSTING_READ(CURCNTR(PIPE_A));
10801 intel_crtc->cursor_cntl = 0;
10802 }
10803
10804 if (intel_crtc->cursor_base != base) {
10805 I915_WRITE(CURBASE(PIPE_A), base);
10806 intel_crtc->cursor_base = base;
10807 }
10808
10809 if (intel_crtc->cursor_size != size) {
10810 I915_WRITE(CURSIZE, size);
10811 intel_crtc->cursor_size = size;
10812 }
10813
10814 if (intel_crtc->cursor_cntl != cntl) {
10815 I915_WRITE(CURCNTR(PIPE_A), cntl);
10816 POSTING_READ(CURCNTR(PIPE_A));
10817 intel_crtc->cursor_cntl = cntl;
10818 }
10819 }
10820
10821 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10822 const struct intel_plane_state *plane_state)
10823 {
10824 struct drm_device *dev = crtc->dev;
10825 struct drm_i915_private *dev_priv = to_i915(dev);
10826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10827 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10828 int pipe = intel_crtc->pipe;
10829 uint32_t cntl = 0;
10830
10831 if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10832 skl_write_cursor_wm(intel_crtc, wm);
10833
10834 if (plane_state && plane_state->base.visible) {
10835 cntl = MCURSOR_GAMMA_ENABLE;
10836 switch (plane_state->base.crtc_w) {
10837 case 64:
10838 cntl |= CURSOR_MODE_64_ARGB_AX;
10839 break;
10840 case 128:
10841 cntl |= CURSOR_MODE_128_ARGB_AX;
10842 break;
10843 case 256:
10844 cntl |= CURSOR_MODE_256_ARGB_AX;
10845 break;
10846 default:
10847 MISSING_CASE(plane_state->base.crtc_w);
10848 return;
10849 }
10850 cntl |= pipe << 28; /* Connect to correct pipe */
10851
10852 if (HAS_DDI(dev_priv))
10853 cntl |= CURSOR_PIPE_CSC_ENABLE;
10854
10855 if (plane_state->base.rotation == DRM_ROTATE_180)
10856 cntl |= CURSOR_ROTATE_180;
10857 }
10858
10859 if (intel_crtc->cursor_cntl != cntl) {
10860 I915_WRITE(CURCNTR(pipe), cntl);
10861 POSTING_READ(CURCNTR(pipe));
10862 intel_crtc->cursor_cntl = cntl;
10863 }
10864
10865 /* and commit changes on next vblank */
10866 I915_WRITE(CURBASE(pipe), base);
10867 POSTING_READ(CURBASE(pipe));
10868
10869 intel_crtc->cursor_base = base;
10870 }
10871
10872 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10873 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10874 const struct intel_plane_state *plane_state)
10875 {
10876 struct drm_device *dev = crtc->dev;
10877 struct drm_i915_private *dev_priv = to_i915(dev);
10878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10879 int pipe = intel_crtc->pipe;
10880 u32 base = intel_crtc->cursor_addr;
10881 u32 pos = 0;
10882
10883 if (plane_state) {
10884 int x = plane_state->base.crtc_x;
10885 int y = plane_state->base.crtc_y;
10886
10887 if (x < 0) {
10888 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10889 x = -x;
10890 }
10891 pos |= x << CURSOR_X_SHIFT;
10892
10893 if (y < 0) {
10894 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10895 y = -y;
10896 }
10897 pos |= y << CURSOR_Y_SHIFT;
10898
10899 /* ILK+ do this automagically */
10900 if (HAS_GMCH_DISPLAY(dev_priv) &&
10901 plane_state->base.rotation == DRM_ROTATE_180) {
10902 base += (plane_state->base.crtc_h *
10903 plane_state->base.crtc_w - 1) * 4;
10904 }
10905 }
10906
10907 I915_WRITE(CURPOS(pipe), pos);
10908
10909 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10910 i845_update_cursor(crtc, base, plane_state);
10911 else
10912 i9xx_update_cursor(crtc, base, plane_state);
10913 }
10914
10915 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10916 uint32_t width, uint32_t height)
10917 {
10918 if (width == 0 || height == 0)
10919 return false;
10920
10921 /*
10922 * 845g/865g are special in that they are only limited by
10923 * the width of their cursors, the height is arbitrary up to
10924 * the precision of the register. Everything else requires
10925 * square cursors, limited to a few power-of-two sizes.
10926 */
10927 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10928 if ((width & 63) != 0)
10929 return false;
10930
10931 if (width > (IS_845G(dev_priv) ? 64 : 512))
10932 return false;
10933
10934 if (height > 1023)
10935 return false;
10936 } else {
10937 switch (width | height) {
10938 case 256:
10939 case 128:
10940 if (IS_GEN2(dev_priv))
10941 return false;
10942 case 64:
10943 break;
10944 default:
10945 return false;
10946 }
10947 }
10948
10949 return true;
10950 }
10951
10952 /* VESA 640x480x72Hz mode to set on the pipe */
10953 static struct drm_display_mode load_detect_mode = {
10954 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10955 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10956 };
10957
10958 struct drm_framebuffer *
10959 __intel_framebuffer_create(struct drm_device *dev,
10960 struct drm_mode_fb_cmd2 *mode_cmd,
10961 struct drm_i915_gem_object *obj)
10962 {
10963 struct intel_framebuffer *intel_fb;
10964 int ret;
10965
10966 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10967 if (!intel_fb)
10968 return ERR_PTR(-ENOMEM);
10969
10970 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10971 if (ret)
10972 goto err;
10973
10974 return &intel_fb->base;
10975
10976 err:
10977 kfree(intel_fb);
10978 return ERR_PTR(ret);
10979 }
10980
10981 static struct drm_framebuffer *
10982 intel_framebuffer_create(struct drm_device *dev,
10983 struct drm_mode_fb_cmd2 *mode_cmd,
10984 struct drm_i915_gem_object *obj)
10985 {
10986 struct drm_framebuffer *fb;
10987 int ret;
10988
10989 ret = i915_mutex_lock_interruptible(dev);
10990 if (ret)
10991 return ERR_PTR(ret);
10992 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10993 mutex_unlock(&dev->struct_mutex);
10994
10995 return fb;
10996 }
10997
10998 static u32
10999 intel_framebuffer_pitch_for_width(int width, int bpp)
11000 {
11001 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11002 return ALIGN(pitch, 64);
11003 }
11004
11005 static u32
11006 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11007 {
11008 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11009 return PAGE_ALIGN(pitch * mode->vdisplay);
11010 }
11011
11012 static struct drm_framebuffer *
11013 intel_framebuffer_create_for_mode(struct drm_device *dev,
11014 struct drm_display_mode *mode,
11015 int depth, int bpp)
11016 {
11017 struct drm_framebuffer *fb;
11018 struct drm_i915_gem_object *obj;
11019 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11020
11021 obj = i915_gem_object_create(dev,
11022 intel_framebuffer_size_for_mode(mode, bpp));
11023 if (IS_ERR(obj))
11024 return ERR_CAST(obj);
11025
11026 mode_cmd.width = mode->hdisplay;
11027 mode_cmd.height = mode->vdisplay;
11028 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11029 bpp);
11030 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11031
11032 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11033 if (IS_ERR(fb))
11034 i915_gem_object_put_unlocked(obj);
11035
11036 return fb;
11037 }
11038
11039 static struct drm_framebuffer *
11040 mode_fits_in_fbdev(struct drm_device *dev,
11041 struct drm_display_mode *mode)
11042 {
11043 #ifdef CONFIG_DRM_FBDEV_EMULATION
11044 struct drm_i915_private *dev_priv = to_i915(dev);
11045 struct drm_i915_gem_object *obj;
11046 struct drm_framebuffer *fb;
11047
11048 if (!dev_priv->fbdev)
11049 return NULL;
11050
11051 if (!dev_priv->fbdev->fb)
11052 return NULL;
11053
11054 obj = dev_priv->fbdev->fb->obj;
11055 BUG_ON(!obj);
11056
11057 fb = &dev_priv->fbdev->fb->base;
11058 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11059 fb->bits_per_pixel))
11060 return NULL;
11061
11062 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11063 return NULL;
11064
11065 drm_framebuffer_reference(fb);
11066 return fb;
11067 #else
11068 return NULL;
11069 #endif
11070 }
11071
11072 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11073 struct drm_crtc *crtc,
11074 struct drm_display_mode *mode,
11075 struct drm_framebuffer *fb,
11076 int x, int y)
11077 {
11078 struct drm_plane_state *plane_state;
11079 int hdisplay, vdisplay;
11080 int ret;
11081
11082 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11083 if (IS_ERR(plane_state))
11084 return PTR_ERR(plane_state);
11085
11086 if (mode)
11087 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11088 else
11089 hdisplay = vdisplay = 0;
11090
11091 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11092 if (ret)
11093 return ret;
11094 drm_atomic_set_fb_for_plane(plane_state, fb);
11095 plane_state->crtc_x = 0;
11096 plane_state->crtc_y = 0;
11097 plane_state->crtc_w = hdisplay;
11098 plane_state->crtc_h = vdisplay;
11099 plane_state->src_x = x << 16;
11100 plane_state->src_y = y << 16;
11101 plane_state->src_w = hdisplay << 16;
11102 plane_state->src_h = vdisplay << 16;
11103
11104 return 0;
11105 }
11106
11107 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11108 struct drm_display_mode *mode,
11109 struct intel_load_detect_pipe *old,
11110 struct drm_modeset_acquire_ctx *ctx)
11111 {
11112 struct intel_crtc *intel_crtc;
11113 struct intel_encoder *intel_encoder =
11114 intel_attached_encoder(connector);
11115 struct drm_crtc *possible_crtc;
11116 struct drm_encoder *encoder = &intel_encoder->base;
11117 struct drm_crtc *crtc = NULL;
11118 struct drm_device *dev = encoder->dev;
11119 struct drm_framebuffer *fb;
11120 struct drm_mode_config *config = &dev->mode_config;
11121 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11122 struct drm_connector_state *connector_state;
11123 struct intel_crtc_state *crtc_state;
11124 int ret, i = -1;
11125
11126 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11127 connector->base.id, connector->name,
11128 encoder->base.id, encoder->name);
11129
11130 old->restore_state = NULL;
11131
11132 retry:
11133 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11134 if (ret)
11135 goto fail;
11136
11137 /*
11138 * Algorithm gets a little messy:
11139 *
11140 * - if the connector already has an assigned crtc, use it (but make
11141 * sure it's on first)
11142 *
11143 * - try to find the first unused crtc that can drive this connector,
11144 * and use that if we find one
11145 */
11146
11147 /* See if we already have a CRTC for this connector */
11148 if (connector->state->crtc) {
11149 crtc = connector->state->crtc;
11150
11151 ret = drm_modeset_lock(&crtc->mutex, ctx);
11152 if (ret)
11153 goto fail;
11154
11155 /* Make sure the crtc and connector are running */
11156 goto found;
11157 }
11158
11159 /* Find an unused one (if possible) */
11160 for_each_crtc(dev, possible_crtc) {
11161 i++;
11162 if (!(encoder->possible_crtcs & (1 << i)))
11163 continue;
11164
11165 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11166 if (ret)
11167 goto fail;
11168
11169 if (possible_crtc->state->enable) {
11170 drm_modeset_unlock(&possible_crtc->mutex);
11171 continue;
11172 }
11173
11174 crtc = possible_crtc;
11175 break;
11176 }
11177
11178 /*
11179 * If we didn't find an unused CRTC, don't use any.
11180 */
11181 if (!crtc) {
11182 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11183 goto fail;
11184 }
11185
11186 found:
11187 intel_crtc = to_intel_crtc(crtc);
11188
11189 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11190 if (ret)
11191 goto fail;
11192
11193 state = drm_atomic_state_alloc(dev);
11194 restore_state = drm_atomic_state_alloc(dev);
11195 if (!state || !restore_state) {
11196 ret = -ENOMEM;
11197 goto fail;
11198 }
11199
11200 state->acquire_ctx = ctx;
11201 restore_state->acquire_ctx = ctx;
11202
11203 connector_state = drm_atomic_get_connector_state(state, connector);
11204 if (IS_ERR(connector_state)) {
11205 ret = PTR_ERR(connector_state);
11206 goto fail;
11207 }
11208
11209 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11210 if (ret)
11211 goto fail;
11212
11213 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11214 if (IS_ERR(crtc_state)) {
11215 ret = PTR_ERR(crtc_state);
11216 goto fail;
11217 }
11218
11219 crtc_state->base.active = crtc_state->base.enable = true;
11220
11221 if (!mode)
11222 mode = &load_detect_mode;
11223
11224 /* We need a framebuffer large enough to accommodate all accesses
11225 * that the plane may generate whilst we perform load detection.
11226 * We can not rely on the fbcon either being present (we get called
11227 * during its initialisation to detect all boot displays, or it may
11228 * not even exist) or that it is large enough to satisfy the
11229 * requested mode.
11230 */
11231 fb = mode_fits_in_fbdev(dev, mode);
11232 if (fb == NULL) {
11233 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11234 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11235 } else
11236 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11237 if (IS_ERR(fb)) {
11238 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11239 goto fail;
11240 }
11241
11242 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11243 if (ret)
11244 goto fail;
11245
11246 drm_framebuffer_unreference(fb);
11247
11248 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11249 if (ret)
11250 goto fail;
11251
11252 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11253 if (!ret)
11254 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11255 if (!ret)
11256 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11257 if (ret) {
11258 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11259 goto fail;
11260 }
11261
11262 ret = drm_atomic_commit(state);
11263 if (ret) {
11264 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11265 goto fail;
11266 }
11267
11268 old->restore_state = restore_state;
11269
11270 /* let the connector get through one full cycle before testing */
11271 intel_wait_for_vblank(dev, intel_crtc->pipe);
11272 return true;
11273
11274 fail:
11275 drm_atomic_state_free(state);
11276 drm_atomic_state_free(restore_state);
11277 restore_state = state = NULL;
11278
11279 if (ret == -EDEADLK) {
11280 drm_modeset_backoff(ctx);
11281 goto retry;
11282 }
11283
11284 return false;
11285 }
11286
11287 void intel_release_load_detect_pipe(struct drm_connector *connector,
11288 struct intel_load_detect_pipe *old,
11289 struct drm_modeset_acquire_ctx *ctx)
11290 {
11291 struct intel_encoder *intel_encoder =
11292 intel_attached_encoder(connector);
11293 struct drm_encoder *encoder = &intel_encoder->base;
11294 struct drm_atomic_state *state = old->restore_state;
11295 int ret;
11296
11297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11298 connector->base.id, connector->name,
11299 encoder->base.id, encoder->name);
11300
11301 if (!state)
11302 return;
11303
11304 ret = drm_atomic_commit(state);
11305 if (ret) {
11306 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11307 drm_atomic_state_free(state);
11308 }
11309 }
11310
11311 static int i9xx_pll_refclk(struct drm_device *dev,
11312 const struct intel_crtc_state *pipe_config)
11313 {
11314 struct drm_i915_private *dev_priv = to_i915(dev);
11315 u32 dpll = pipe_config->dpll_hw_state.dpll;
11316
11317 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11318 return dev_priv->vbt.lvds_ssc_freq;
11319 else if (HAS_PCH_SPLIT(dev_priv))
11320 return 120000;
11321 else if (!IS_GEN2(dev))
11322 return 96000;
11323 else
11324 return 48000;
11325 }
11326
11327 /* Returns the clock of the currently programmed mode of the given pipe. */
11328 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11329 struct intel_crtc_state *pipe_config)
11330 {
11331 struct drm_device *dev = crtc->base.dev;
11332 struct drm_i915_private *dev_priv = to_i915(dev);
11333 int pipe = pipe_config->cpu_transcoder;
11334 u32 dpll = pipe_config->dpll_hw_state.dpll;
11335 u32 fp;
11336 struct dpll clock;
11337 int port_clock;
11338 int refclk = i9xx_pll_refclk(dev, pipe_config);
11339
11340 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11341 fp = pipe_config->dpll_hw_state.fp0;
11342 else
11343 fp = pipe_config->dpll_hw_state.fp1;
11344
11345 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11346 if (IS_PINEVIEW(dev)) {
11347 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11348 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11349 } else {
11350 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11351 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11352 }
11353
11354 if (!IS_GEN2(dev)) {
11355 if (IS_PINEVIEW(dev))
11356 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11357 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11358 else
11359 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11360 DPLL_FPA01_P1_POST_DIV_SHIFT);
11361
11362 switch (dpll & DPLL_MODE_MASK) {
11363 case DPLLB_MODE_DAC_SERIAL:
11364 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11365 5 : 10;
11366 break;
11367 case DPLLB_MODE_LVDS:
11368 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11369 7 : 14;
11370 break;
11371 default:
11372 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11373 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11374 return;
11375 }
11376
11377 if (IS_PINEVIEW(dev))
11378 port_clock = pnv_calc_dpll_params(refclk, &clock);
11379 else
11380 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11381 } else {
11382 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11383 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11384
11385 if (is_lvds) {
11386 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11387 DPLL_FPA01_P1_POST_DIV_SHIFT);
11388
11389 if (lvds & LVDS_CLKB_POWER_UP)
11390 clock.p2 = 7;
11391 else
11392 clock.p2 = 14;
11393 } else {
11394 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11395 clock.p1 = 2;
11396 else {
11397 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11398 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11399 }
11400 if (dpll & PLL_P2_DIVIDE_BY_4)
11401 clock.p2 = 4;
11402 else
11403 clock.p2 = 2;
11404 }
11405
11406 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11407 }
11408
11409 /*
11410 * This value includes pixel_multiplier. We will use
11411 * port_clock to compute adjusted_mode.crtc_clock in the
11412 * encoder's get_config() function.
11413 */
11414 pipe_config->port_clock = port_clock;
11415 }
11416
11417 int intel_dotclock_calculate(int link_freq,
11418 const struct intel_link_m_n *m_n)
11419 {
11420 /*
11421 * The calculation for the data clock is:
11422 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11423 * But we want to avoid losing precison if possible, so:
11424 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11425 *
11426 * and the link clock is simpler:
11427 * link_clock = (m * link_clock) / n
11428 */
11429
11430 if (!m_n->link_n)
11431 return 0;
11432
11433 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11434 }
11435
11436 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11437 struct intel_crtc_state *pipe_config)
11438 {
11439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11440
11441 /* read out port_clock from the DPLL */
11442 i9xx_crtc_clock_get(crtc, pipe_config);
11443
11444 /*
11445 * In case there is an active pipe without active ports,
11446 * we may need some idea for the dotclock anyway.
11447 * Calculate one based on the FDI configuration.
11448 */
11449 pipe_config->base.adjusted_mode.crtc_clock =
11450 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11451 &pipe_config->fdi_m_n);
11452 }
11453
11454 /** Returns the currently programmed mode of the given pipe. */
11455 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11456 struct drm_crtc *crtc)
11457 {
11458 struct drm_i915_private *dev_priv = to_i915(dev);
11459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11460 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11461 struct drm_display_mode *mode;
11462 struct intel_crtc_state *pipe_config;
11463 int htot = I915_READ(HTOTAL(cpu_transcoder));
11464 int hsync = I915_READ(HSYNC(cpu_transcoder));
11465 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11466 int vsync = I915_READ(VSYNC(cpu_transcoder));
11467 enum pipe pipe = intel_crtc->pipe;
11468
11469 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11470 if (!mode)
11471 return NULL;
11472
11473 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11474 if (!pipe_config) {
11475 kfree(mode);
11476 return NULL;
11477 }
11478
11479 /*
11480 * Construct a pipe_config sufficient for getting the clock info
11481 * back out of crtc_clock_get.
11482 *
11483 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11484 * to use a real value here instead.
11485 */
11486 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11487 pipe_config->pixel_multiplier = 1;
11488 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11489 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11490 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11491 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11492
11493 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11494 mode->hdisplay = (htot & 0xffff) + 1;
11495 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11496 mode->hsync_start = (hsync & 0xffff) + 1;
11497 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11498 mode->vdisplay = (vtot & 0xffff) + 1;
11499 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11500 mode->vsync_start = (vsync & 0xffff) + 1;
11501 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11502
11503 drm_mode_set_name(mode);
11504
11505 kfree(pipe_config);
11506
11507 return mode;
11508 }
11509
11510 static void intel_crtc_destroy(struct drm_crtc *crtc)
11511 {
11512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11513 struct drm_device *dev = crtc->dev;
11514 struct intel_flip_work *work;
11515
11516 spin_lock_irq(&dev->event_lock);
11517 work = intel_crtc->flip_work;
11518 intel_crtc->flip_work = NULL;
11519 spin_unlock_irq(&dev->event_lock);
11520
11521 if (work) {
11522 cancel_work_sync(&work->mmio_work);
11523 cancel_work_sync(&work->unpin_work);
11524 kfree(work);
11525 }
11526
11527 drm_crtc_cleanup(crtc);
11528
11529 kfree(intel_crtc);
11530 }
11531
11532 static void intel_unpin_work_fn(struct work_struct *__work)
11533 {
11534 struct intel_flip_work *work =
11535 container_of(__work, struct intel_flip_work, unpin_work);
11536 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11537 struct drm_device *dev = crtc->base.dev;
11538 struct drm_plane *primary = crtc->base.primary;
11539
11540 if (is_mmio_work(work))
11541 flush_work(&work->mmio_work);
11542
11543 mutex_lock(&dev->struct_mutex);
11544 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11545 i915_gem_object_put(work->pending_flip_obj);
11546 mutex_unlock(&dev->struct_mutex);
11547
11548 i915_gem_request_put(work->flip_queued_req);
11549
11550 intel_frontbuffer_flip_complete(to_i915(dev),
11551 to_intel_plane(primary)->frontbuffer_bit);
11552 intel_fbc_post_update(crtc);
11553 drm_framebuffer_unreference(work->old_fb);
11554
11555 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11556 atomic_dec(&crtc->unpin_work_count);
11557
11558 kfree(work);
11559 }
11560
11561 /* Is 'a' after or equal to 'b'? */
11562 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11563 {
11564 return !((a - b) & 0x80000000);
11565 }
11566
11567 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11568 struct intel_flip_work *work)
11569 {
11570 struct drm_device *dev = crtc->base.dev;
11571 struct drm_i915_private *dev_priv = to_i915(dev);
11572
11573 if (abort_flip_on_reset(crtc))
11574 return true;
11575
11576 /*
11577 * The relevant registers doen't exist on pre-ctg.
11578 * As the flip done interrupt doesn't trigger for mmio
11579 * flips on gmch platforms, a flip count check isn't
11580 * really needed there. But since ctg has the registers,
11581 * include it in the check anyway.
11582 */
11583 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11584 return true;
11585
11586 /*
11587 * BDW signals flip done immediately if the plane
11588 * is disabled, even if the plane enable is already
11589 * armed to occur at the next vblank :(
11590 */
11591
11592 /*
11593 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11594 * used the same base address. In that case the mmio flip might
11595 * have completed, but the CS hasn't even executed the flip yet.
11596 *
11597 * A flip count check isn't enough as the CS might have updated
11598 * the base address just after start of vblank, but before we
11599 * managed to process the interrupt. This means we'd complete the
11600 * CS flip too soon.
11601 *
11602 * Combining both checks should get us a good enough result. It may
11603 * still happen that the CS flip has been executed, but has not
11604 * yet actually completed. But in case the base address is the same
11605 * anyway, we don't really care.
11606 */
11607 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11608 crtc->flip_work->gtt_offset &&
11609 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11610 crtc->flip_work->flip_count);
11611 }
11612
11613 static bool
11614 __pageflip_finished_mmio(struct intel_crtc *crtc,
11615 struct intel_flip_work *work)
11616 {
11617 /*
11618 * MMIO work completes when vblank is different from
11619 * flip_queued_vblank.
11620 *
11621 * Reset counter value doesn't matter, this is handled by
11622 * i915_wait_request finishing early, so no need to handle
11623 * reset here.
11624 */
11625 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11626 }
11627
11628
11629 static bool pageflip_finished(struct intel_crtc *crtc,
11630 struct intel_flip_work *work)
11631 {
11632 if (!atomic_read(&work->pending))
11633 return false;
11634
11635 smp_rmb();
11636
11637 if (is_mmio_work(work))
11638 return __pageflip_finished_mmio(crtc, work);
11639 else
11640 return __pageflip_finished_cs(crtc, work);
11641 }
11642
11643 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11644 {
11645 struct drm_device *dev = &dev_priv->drm;
11646 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11648 struct intel_flip_work *work;
11649 unsigned long flags;
11650
11651 /* Ignore early vblank irqs */
11652 if (!crtc)
11653 return;
11654
11655 /*
11656 * This is called both by irq handlers and the reset code (to complete
11657 * lost pageflips) so needs the full irqsave spinlocks.
11658 */
11659 spin_lock_irqsave(&dev->event_lock, flags);
11660 work = intel_crtc->flip_work;
11661
11662 if (work != NULL &&
11663 !is_mmio_work(work) &&
11664 pageflip_finished(intel_crtc, work))
11665 page_flip_completed(intel_crtc);
11666
11667 spin_unlock_irqrestore(&dev->event_lock, flags);
11668 }
11669
11670 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11671 {
11672 struct drm_device *dev = &dev_priv->drm;
11673 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11675 struct intel_flip_work *work;
11676 unsigned long flags;
11677
11678 /* Ignore early vblank irqs */
11679 if (!crtc)
11680 return;
11681
11682 /*
11683 * This is called both by irq handlers and the reset code (to complete
11684 * lost pageflips) so needs the full irqsave spinlocks.
11685 */
11686 spin_lock_irqsave(&dev->event_lock, flags);
11687 work = intel_crtc->flip_work;
11688
11689 if (work != NULL &&
11690 is_mmio_work(work) &&
11691 pageflip_finished(intel_crtc, work))
11692 page_flip_completed(intel_crtc);
11693
11694 spin_unlock_irqrestore(&dev->event_lock, flags);
11695 }
11696
11697 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11698 struct intel_flip_work *work)
11699 {
11700 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11701
11702 /* Ensure that the work item is consistent when activating it ... */
11703 smp_mb__before_atomic();
11704 atomic_set(&work->pending, 1);
11705 }
11706
11707 static int intel_gen2_queue_flip(struct drm_device *dev,
11708 struct drm_crtc *crtc,
11709 struct drm_framebuffer *fb,
11710 struct drm_i915_gem_object *obj,
11711 struct drm_i915_gem_request *req,
11712 uint32_t flags)
11713 {
11714 struct intel_ring *ring = req->ring;
11715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11716 u32 flip_mask;
11717 int ret;
11718
11719 ret = intel_ring_begin(req, 6);
11720 if (ret)
11721 return ret;
11722
11723 /* Can't queue multiple flips, so wait for the previous
11724 * one to finish before executing the next.
11725 */
11726 if (intel_crtc->plane)
11727 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11728 else
11729 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11730 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11731 intel_ring_emit(ring, MI_NOOP);
11732 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11733 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11734 intel_ring_emit(ring, fb->pitches[0]);
11735 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11736 intel_ring_emit(ring, 0); /* aux display base address, unused */
11737
11738 return 0;
11739 }
11740
11741 static int intel_gen3_queue_flip(struct drm_device *dev,
11742 struct drm_crtc *crtc,
11743 struct drm_framebuffer *fb,
11744 struct drm_i915_gem_object *obj,
11745 struct drm_i915_gem_request *req,
11746 uint32_t flags)
11747 {
11748 struct intel_ring *ring = req->ring;
11749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11750 u32 flip_mask;
11751 int ret;
11752
11753 ret = intel_ring_begin(req, 6);
11754 if (ret)
11755 return ret;
11756
11757 if (intel_crtc->plane)
11758 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11759 else
11760 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11761 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11762 intel_ring_emit(ring, MI_NOOP);
11763 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11764 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11765 intel_ring_emit(ring, fb->pitches[0]);
11766 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11767 intel_ring_emit(ring, MI_NOOP);
11768
11769 return 0;
11770 }
11771
11772 static int intel_gen4_queue_flip(struct drm_device *dev,
11773 struct drm_crtc *crtc,
11774 struct drm_framebuffer *fb,
11775 struct drm_i915_gem_object *obj,
11776 struct drm_i915_gem_request *req,
11777 uint32_t flags)
11778 {
11779 struct intel_ring *ring = req->ring;
11780 struct drm_i915_private *dev_priv = to_i915(dev);
11781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11782 uint32_t pf, pipesrc;
11783 int ret;
11784
11785 ret = intel_ring_begin(req, 4);
11786 if (ret)
11787 return ret;
11788
11789 /* i965+ uses the linear or tiled offsets from the
11790 * Display Registers (which do not change across a page-flip)
11791 * so we need only reprogram the base address.
11792 */
11793 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11794 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11795 intel_ring_emit(ring, fb->pitches[0]);
11796 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11797 intel_fb_modifier_to_tiling(fb->modifier[0]));
11798
11799 /* XXX Enabling the panel-fitter across page-flip is so far
11800 * untested on non-native modes, so ignore it for now.
11801 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11802 */
11803 pf = 0;
11804 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11805 intel_ring_emit(ring, pf | pipesrc);
11806
11807 return 0;
11808 }
11809
11810 static int intel_gen6_queue_flip(struct drm_device *dev,
11811 struct drm_crtc *crtc,
11812 struct drm_framebuffer *fb,
11813 struct drm_i915_gem_object *obj,
11814 struct drm_i915_gem_request *req,
11815 uint32_t flags)
11816 {
11817 struct intel_ring *ring = req->ring;
11818 struct drm_i915_private *dev_priv = to_i915(dev);
11819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11820 uint32_t pf, pipesrc;
11821 int ret;
11822
11823 ret = intel_ring_begin(req, 4);
11824 if (ret)
11825 return ret;
11826
11827 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11828 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11829 intel_ring_emit(ring, fb->pitches[0] |
11830 intel_fb_modifier_to_tiling(fb->modifier[0]));
11831 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11832
11833 /* Contrary to the suggestions in the documentation,
11834 * "Enable Panel Fitter" does not seem to be required when page
11835 * flipping with a non-native mode, and worse causes a normal
11836 * modeset to fail.
11837 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11838 */
11839 pf = 0;
11840 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11841 intel_ring_emit(ring, pf | pipesrc);
11842
11843 return 0;
11844 }
11845
11846 static int intel_gen7_queue_flip(struct drm_device *dev,
11847 struct drm_crtc *crtc,
11848 struct drm_framebuffer *fb,
11849 struct drm_i915_gem_object *obj,
11850 struct drm_i915_gem_request *req,
11851 uint32_t flags)
11852 {
11853 struct intel_ring *ring = req->ring;
11854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11855 uint32_t plane_bit = 0;
11856 int len, ret;
11857
11858 switch (intel_crtc->plane) {
11859 case PLANE_A:
11860 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11861 break;
11862 case PLANE_B:
11863 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11864 break;
11865 case PLANE_C:
11866 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11867 break;
11868 default:
11869 WARN_ONCE(1, "unknown plane in flip command\n");
11870 return -ENODEV;
11871 }
11872
11873 len = 4;
11874 if (req->engine->id == RCS) {
11875 len += 6;
11876 /*
11877 * On Gen 8, SRM is now taking an extra dword to accommodate
11878 * 48bits addresses, and we need a NOOP for the batch size to
11879 * stay even.
11880 */
11881 if (IS_GEN8(dev))
11882 len += 2;
11883 }
11884
11885 /*
11886 * BSpec MI_DISPLAY_FLIP for IVB:
11887 * "The full packet must be contained within the same cache line."
11888 *
11889 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11890 * cacheline, if we ever start emitting more commands before
11891 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11892 * then do the cacheline alignment, and finally emit the
11893 * MI_DISPLAY_FLIP.
11894 */
11895 ret = intel_ring_cacheline_align(req);
11896 if (ret)
11897 return ret;
11898
11899 ret = intel_ring_begin(req, len);
11900 if (ret)
11901 return ret;
11902
11903 /* Unmask the flip-done completion message. Note that the bspec says that
11904 * we should do this for both the BCS and RCS, and that we must not unmask
11905 * more than one flip event at any time (or ensure that one flip message
11906 * can be sent by waiting for flip-done prior to queueing new flips).
11907 * Experimentation says that BCS works despite DERRMR masking all
11908 * flip-done completion events and that unmasking all planes at once
11909 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11910 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11911 */
11912 if (req->engine->id == RCS) {
11913 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11914 intel_ring_emit_reg(ring, DERRMR);
11915 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11916 DERRMR_PIPEB_PRI_FLIP_DONE |
11917 DERRMR_PIPEC_PRI_FLIP_DONE));
11918 if (IS_GEN8(dev))
11919 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11920 MI_SRM_LRM_GLOBAL_GTT);
11921 else
11922 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11923 MI_SRM_LRM_GLOBAL_GTT);
11924 intel_ring_emit_reg(ring, DERRMR);
11925 intel_ring_emit(ring,
11926 i915_ggtt_offset(req->engine->scratch) + 256);
11927 if (IS_GEN8(dev)) {
11928 intel_ring_emit(ring, 0);
11929 intel_ring_emit(ring, MI_NOOP);
11930 }
11931 }
11932
11933 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11934 intel_ring_emit(ring, fb->pitches[0] |
11935 intel_fb_modifier_to_tiling(fb->modifier[0]));
11936 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11937 intel_ring_emit(ring, (MI_NOOP));
11938
11939 return 0;
11940 }
11941
11942 static bool use_mmio_flip(struct intel_engine_cs *engine,
11943 struct drm_i915_gem_object *obj)
11944 {
11945 struct reservation_object *resv;
11946
11947 /*
11948 * This is not being used for older platforms, because
11949 * non-availability of flip done interrupt forces us to use
11950 * CS flips. Older platforms derive flip done using some clever
11951 * tricks involving the flip_pending status bits and vblank irqs.
11952 * So using MMIO flips there would disrupt this mechanism.
11953 */
11954
11955 if (engine == NULL)
11956 return true;
11957
11958 if (INTEL_GEN(engine->i915) < 5)
11959 return false;
11960
11961 if (i915.use_mmio_flip < 0)
11962 return false;
11963 else if (i915.use_mmio_flip > 0)
11964 return true;
11965 else if (i915.enable_execlists)
11966 return true;
11967
11968 resv = i915_gem_object_get_dmabuf_resv(obj);
11969 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11970 return true;
11971
11972 return engine != i915_gem_active_get_engine(&obj->last_write,
11973 &obj->base.dev->struct_mutex);
11974 }
11975
11976 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11977 unsigned int rotation,
11978 struct intel_flip_work *work)
11979 {
11980 struct drm_device *dev = intel_crtc->base.dev;
11981 struct drm_i915_private *dev_priv = to_i915(dev);
11982 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11983 const enum pipe pipe = intel_crtc->pipe;
11984 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11985
11986 ctl = I915_READ(PLANE_CTL(pipe, 0));
11987 ctl &= ~PLANE_CTL_TILED_MASK;
11988 switch (fb->modifier[0]) {
11989 case DRM_FORMAT_MOD_NONE:
11990 break;
11991 case I915_FORMAT_MOD_X_TILED:
11992 ctl |= PLANE_CTL_TILED_X;
11993 break;
11994 case I915_FORMAT_MOD_Y_TILED:
11995 ctl |= PLANE_CTL_TILED_Y;
11996 break;
11997 case I915_FORMAT_MOD_Yf_TILED:
11998 ctl |= PLANE_CTL_TILED_YF;
11999 break;
12000 default:
12001 MISSING_CASE(fb->modifier[0]);
12002 }
12003
12004 /*
12005 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12006 * PLANE_SURF updates, the update is then guaranteed to be atomic.
12007 */
12008 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12009 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12010
12011 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12012 POSTING_READ(PLANE_SURF(pipe, 0));
12013 }
12014
12015 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12016 struct intel_flip_work *work)
12017 {
12018 struct drm_device *dev = intel_crtc->base.dev;
12019 struct drm_i915_private *dev_priv = to_i915(dev);
12020 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12021 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12022 u32 dspcntr;
12023
12024 dspcntr = I915_READ(reg);
12025
12026 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12027 dspcntr |= DISPPLANE_TILED;
12028 else
12029 dspcntr &= ~DISPPLANE_TILED;
12030
12031 I915_WRITE(reg, dspcntr);
12032
12033 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12034 POSTING_READ(DSPSURF(intel_crtc->plane));
12035 }
12036
12037 static void intel_mmio_flip_work_func(struct work_struct *w)
12038 {
12039 struct intel_flip_work *work =
12040 container_of(w, struct intel_flip_work, mmio_work);
12041 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12042 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12043 struct intel_framebuffer *intel_fb =
12044 to_intel_framebuffer(crtc->base.primary->fb);
12045 struct drm_i915_gem_object *obj = intel_fb->obj;
12046 struct reservation_object *resv;
12047
12048 if (work->flip_queued_req)
12049 WARN_ON(i915_wait_request(work->flip_queued_req,
12050 0, NULL, NO_WAITBOOST));
12051
12052 /* For framebuffer backed by dmabuf, wait for fence */
12053 resv = i915_gem_object_get_dmabuf_resv(obj);
12054 if (resv)
12055 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12056 MAX_SCHEDULE_TIMEOUT) < 0);
12057
12058 intel_pipe_update_start(crtc);
12059
12060 if (INTEL_GEN(dev_priv) >= 9)
12061 skl_do_mmio_flip(crtc, work->rotation, work);
12062 else
12063 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12064 ilk_do_mmio_flip(crtc, work);
12065
12066 intel_pipe_update_end(crtc, work);
12067 }
12068
12069 static int intel_default_queue_flip(struct drm_device *dev,
12070 struct drm_crtc *crtc,
12071 struct drm_framebuffer *fb,
12072 struct drm_i915_gem_object *obj,
12073 struct drm_i915_gem_request *req,
12074 uint32_t flags)
12075 {
12076 return -ENODEV;
12077 }
12078
12079 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12080 struct intel_crtc *intel_crtc,
12081 struct intel_flip_work *work)
12082 {
12083 u32 addr, vblank;
12084
12085 if (!atomic_read(&work->pending))
12086 return false;
12087
12088 smp_rmb();
12089
12090 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12091 if (work->flip_ready_vblank == 0) {
12092 if (work->flip_queued_req &&
12093 !i915_gem_request_completed(work->flip_queued_req))
12094 return false;
12095
12096 work->flip_ready_vblank = vblank;
12097 }
12098
12099 if (vblank - work->flip_ready_vblank < 3)
12100 return false;
12101
12102 /* Potential stall - if we see that the flip has happened,
12103 * assume a missed interrupt. */
12104 if (INTEL_GEN(dev_priv) >= 4)
12105 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12106 else
12107 addr = I915_READ(DSPADDR(intel_crtc->plane));
12108
12109 /* There is a potential issue here with a false positive after a flip
12110 * to the same address. We could address this by checking for a
12111 * non-incrementing frame counter.
12112 */
12113 return addr == work->gtt_offset;
12114 }
12115
12116 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12117 {
12118 struct drm_device *dev = &dev_priv->drm;
12119 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12121 struct intel_flip_work *work;
12122
12123 WARN_ON(!in_interrupt());
12124
12125 if (crtc == NULL)
12126 return;
12127
12128 spin_lock(&dev->event_lock);
12129 work = intel_crtc->flip_work;
12130
12131 if (work != NULL && !is_mmio_work(work) &&
12132 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12133 WARN_ONCE(1,
12134 "Kicking stuck page flip: queued at %d, now %d\n",
12135 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12136 page_flip_completed(intel_crtc);
12137 work = NULL;
12138 }
12139
12140 if (work != NULL && !is_mmio_work(work) &&
12141 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12142 intel_queue_rps_boost_for_request(work->flip_queued_req);
12143 spin_unlock(&dev->event_lock);
12144 }
12145
12146 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12147 struct drm_framebuffer *fb,
12148 struct drm_pending_vblank_event *event,
12149 uint32_t page_flip_flags)
12150 {
12151 struct drm_device *dev = crtc->dev;
12152 struct drm_i915_private *dev_priv = to_i915(dev);
12153 struct drm_framebuffer *old_fb = crtc->primary->fb;
12154 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12156 struct drm_plane *primary = crtc->primary;
12157 enum pipe pipe = intel_crtc->pipe;
12158 struct intel_flip_work *work;
12159 struct intel_engine_cs *engine;
12160 bool mmio_flip;
12161 struct drm_i915_gem_request *request;
12162 struct i915_vma *vma;
12163 int ret;
12164
12165 /*
12166 * drm_mode_page_flip_ioctl() should already catch this, but double
12167 * check to be safe. In the future we may enable pageflipping from
12168 * a disabled primary plane.
12169 */
12170 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12171 return -EBUSY;
12172
12173 /* Can't change pixel format via MI display flips. */
12174 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12175 return -EINVAL;
12176
12177 /*
12178 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12179 * Note that pitch changes could also affect these register.
12180 */
12181 if (INTEL_INFO(dev)->gen > 3 &&
12182 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12183 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12184 return -EINVAL;
12185
12186 if (i915_terminally_wedged(&dev_priv->gpu_error))
12187 goto out_hang;
12188
12189 work = kzalloc(sizeof(*work), GFP_KERNEL);
12190 if (work == NULL)
12191 return -ENOMEM;
12192
12193 work->event = event;
12194 work->crtc = crtc;
12195 work->old_fb = old_fb;
12196 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12197
12198 ret = drm_crtc_vblank_get(crtc);
12199 if (ret)
12200 goto free_work;
12201
12202 /* We borrow the event spin lock for protecting flip_work */
12203 spin_lock_irq(&dev->event_lock);
12204 if (intel_crtc->flip_work) {
12205 /* Before declaring the flip queue wedged, check if
12206 * the hardware completed the operation behind our backs.
12207 */
12208 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12209 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12210 page_flip_completed(intel_crtc);
12211 } else {
12212 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12213 spin_unlock_irq(&dev->event_lock);
12214
12215 drm_crtc_vblank_put(crtc);
12216 kfree(work);
12217 return -EBUSY;
12218 }
12219 }
12220 intel_crtc->flip_work = work;
12221 spin_unlock_irq(&dev->event_lock);
12222
12223 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12224 flush_workqueue(dev_priv->wq);
12225
12226 /* Reference the objects for the scheduled work. */
12227 drm_framebuffer_reference(work->old_fb);
12228
12229 crtc->primary->fb = fb;
12230 update_state_fb(crtc->primary);
12231
12232 work->pending_flip_obj = i915_gem_object_get(obj);
12233
12234 ret = i915_mutex_lock_interruptible(dev);
12235 if (ret)
12236 goto cleanup;
12237
12238 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12239 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12240 ret = -EIO;
12241 goto cleanup;
12242 }
12243
12244 atomic_inc(&intel_crtc->unpin_work_count);
12245
12246 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12247 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12248
12249 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12250 engine = dev_priv->engine[BCS];
12251 if (fb->modifier[0] != old_fb->modifier[0])
12252 /* vlv: DISPLAY_FLIP fails to change tiling */
12253 engine = NULL;
12254 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12255 engine = dev_priv->engine[BCS];
12256 } else if (INTEL_INFO(dev)->gen >= 7) {
12257 engine = i915_gem_active_get_engine(&obj->last_write,
12258 &obj->base.dev->struct_mutex);
12259 if (engine == NULL || engine->id != RCS)
12260 engine = dev_priv->engine[BCS];
12261 } else {
12262 engine = dev_priv->engine[RCS];
12263 }
12264
12265 mmio_flip = use_mmio_flip(engine, obj);
12266
12267 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12268 if (IS_ERR(vma)) {
12269 ret = PTR_ERR(vma);
12270 goto cleanup_pending;
12271 }
12272
12273 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12274 work->gtt_offset += intel_crtc->dspaddr_offset;
12275 work->rotation = crtc->primary->state->rotation;
12276
12277 /*
12278 * There's the potential that the next frame will not be compatible with
12279 * FBC, so we want to call pre_update() before the actual page flip.
12280 * The problem is that pre_update() caches some information about the fb
12281 * object, so we want to do this only after the object is pinned. Let's
12282 * be on the safe side and do this immediately before scheduling the
12283 * flip.
12284 */
12285 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12286 to_intel_plane_state(primary->state));
12287
12288 if (mmio_flip) {
12289 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12290
12291 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12292 &obj->base.dev->struct_mutex);
12293 queue_work(system_unbound_wq, &work->mmio_work);
12294 } else {
12295 request = i915_gem_request_alloc(engine, engine->last_context);
12296 if (IS_ERR(request)) {
12297 ret = PTR_ERR(request);
12298 goto cleanup_unpin;
12299 }
12300
12301 ret = i915_gem_request_await_object(request, obj, false);
12302 if (ret)
12303 goto cleanup_request;
12304
12305 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12306 page_flip_flags);
12307 if (ret)
12308 goto cleanup_request;
12309
12310 intel_mark_page_flip_active(intel_crtc, work);
12311
12312 work->flip_queued_req = i915_gem_request_get(request);
12313 i915_add_request_no_flush(request);
12314 }
12315
12316 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12317 to_intel_plane(primary)->frontbuffer_bit);
12318 mutex_unlock(&dev->struct_mutex);
12319
12320 intel_frontbuffer_flip_prepare(to_i915(dev),
12321 to_intel_plane(primary)->frontbuffer_bit);
12322
12323 trace_i915_flip_request(intel_crtc->plane, obj);
12324
12325 return 0;
12326
12327 cleanup_request:
12328 i915_add_request_no_flush(request);
12329 cleanup_unpin:
12330 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12331 cleanup_pending:
12332 atomic_dec(&intel_crtc->unpin_work_count);
12333 mutex_unlock(&dev->struct_mutex);
12334 cleanup:
12335 crtc->primary->fb = old_fb;
12336 update_state_fb(crtc->primary);
12337
12338 i915_gem_object_put_unlocked(obj);
12339 drm_framebuffer_unreference(work->old_fb);
12340
12341 spin_lock_irq(&dev->event_lock);
12342 intel_crtc->flip_work = NULL;
12343 spin_unlock_irq(&dev->event_lock);
12344
12345 drm_crtc_vblank_put(crtc);
12346 free_work:
12347 kfree(work);
12348
12349 if (ret == -EIO) {
12350 struct drm_atomic_state *state;
12351 struct drm_plane_state *plane_state;
12352
12353 out_hang:
12354 state = drm_atomic_state_alloc(dev);
12355 if (!state)
12356 return -ENOMEM;
12357 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12358
12359 retry:
12360 plane_state = drm_atomic_get_plane_state(state, primary);
12361 ret = PTR_ERR_OR_ZERO(plane_state);
12362 if (!ret) {
12363 drm_atomic_set_fb_for_plane(plane_state, fb);
12364
12365 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12366 if (!ret)
12367 ret = drm_atomic_commit(state);
12368 }
12369
12370 if (ret == -EDEADLK) {
12371 drm_modeset_backoff(state->acquire_ctx);
12372 drm_atomic_state_clear(state);
12373 goto retry;
12374 }
12375
12376 if (ret)
12377 drm_atomic_state_free(state);
12378
12379 if (ret == 0 && event) {
12380 spin_lock_irq(&dev->event_lock);
12381 drm_crtc_send_vblank_event(crtc, event);
12382 spin_unlock_irq(&dev->event_lock);
12383 }
12384 }
12385 return ret;
12386 }
12387
12388
12389 /**
12390 * intel_wm_need_update - Check whether watermarks need updating
12391 * @plane: drm plane
12392 * @state: new plane state
12393 *
12394 * Check current plane state versus the new one to determine whether
12395 * watermarks need to be recalculated.
12396 *
12397 * Returns true or false.
12398 */
12399 static bool intel_wm_need_update(struct drm_plane *plane,
12400 struct drm_plane_state *state)
12401 {
12402 struct intel_plane_state *new = to_intel_plane_state(state);
12403 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12404
12405 /* Update watermarks on tiling or size changes. */
12406 if (new->base.visible != cur->base.visible)
12407 return true;
12408
12409 if (!cur->base.fb || !new->base.fb)
12410 return false;
12411
12412 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12413 cur->base.rotation != new->base.rotation ||
12414 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12415 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12416 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12417 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12418 return true;
12419
12420 return false;
12421 }
12422
12423 static bool needs_scaling(struct intel_plane_state *state)
12424 {
12425 int src_w = drm_rect_width(&state->base.src) >> 16;
12426 int src_h = drm_rect_height(&state->base.src) >> 16;
12427 int dst_w = drm_rect_width(&state->base.dst);
12428 int dst_h = drm_rect_height(&state->base.dst);
12429
12430 return (src_w != dst_w || src_h != dst_h);
12431 }
12432
12433 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12434 struct drm_plane_state *plane_state)
12435 {
12436 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12437 struct drm_crtc *crtc = crtc_state->crtc;
12438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12439 struct drm_plane *plane = plane_state->plane;
12440 struct drm_device *dev = crtc->dev;
12441 struct drm_i915_private *dev_priv = to_i915(dev);
12442 struct intel_plane_state *old_plane_state =
12443 to_intel_plane_state(plane->state);
12444 bool mode_changed = needs_modeset(crtc_state);
12445 bool was_crtc_enabled = crtc->state->active;
12446 bool is_crtc_enabled = crtc_state->active;
12447 bool turn_off, turn_on, visible, was_visible;
12448 struct drm_framebuffer *fb = plane_state->fb;
12449 int ret;
12450
12451 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12452 ret = skl_update_scaler_plane(
12453 to_intel_crtc_state(crtc_state),
12454 to_intel_plane_state(plane_state));
12455 if (ret)
12456 return ret;
12457 }
12458
12459 was_visible = old_plane_state->base.visible;
12460 visible = to_intel_plane_state(plane_state)->base.visible;
12461
12462 if (!was_crtc_enabled && WARN_ON(was_visible))
12463 was_visible = false;
12464
12465 /*
12466 * Visibility is calculated as if the crtc was on, but
12467 * after scaler setup everything depends on it being off
12468 * when the crtc isn't active.
12469 *
12470 * FIXME this is wrong for watermarks. Watermarks should also
12471 * be computed as if the pipe would be active. Perhaps move
12472 * per-plane wm computation to the .check_plane() hook, and
12473 * only combine the results from all planes in the current place?
12474 */
12475 if (!is_crtc_enabled)
12476 to_intel_plane_state(plane_state)->base.visible = visible = false;
12477
12478 if (!was_visible && !visible)
12479 return 0;
12480
12481 if (fb != old_plane_state->base.fb)
12482 pipe_config->fb_changed = true;
12483
12484 turn_off = was_visible && (!visible || mode_changed);
12485 turn_on = visible && (!was_visible || mode_changed);
12486
12487 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12488 intel_crtc->base.base.id,
12489 intel_crtc->base.name,
12490 plane->base.id, plane->name,
12491 fb ? fb->base.id : -1);
12492
12493 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12494 plane->base.id, plane->name,
12495 was_visible, visible,
12496 turn_off, turn_on, mode_changed);
12497
12498 if (turn_on) {
12499 pipe_config->update_wm_pre = true;
12500
12501 /* must disable cxsr around plane enable/disable */
12502 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12503 pipe_config->disable_cxsr = true;
12504 } else if (turn_off) {
12505 pipe_config->update_wm_post = true;
12506
12507 /* must disable cxsr around plane enable/disable */
12508 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12509 pipe_config->disable_cxsr = true;
12510 } else if (intel_wm_need_update(plane, plane_state)) {
12511 /* FIXME bollocks */
12512 pipe_config->update_wm_pre = true;
12513 pipe_config->update_wm_post = true;
12514 }
12515
12516 /* Pre-gen9 platforms need two-step watermark updates */
12517 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12518 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12519 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12520
12521 if (visible || was_visible)
12522 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12523
12524 /*
12525 * WaCxSRDisabledForSpriteScaling:ivb
12526 *
12527 * cstate->update_wm was already set above, so this flag will
12528 * take effect when we commit and program watermarks.
12529 */
12530 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12531 needs_scaling(to_intel_plane_state(plane_state)) &&
12532 !needs_scaling(old_plane_state))
12533 pipe_config->disable_lp_wm = true;
12534
12535 return 0;
12536 }
12537
12538 static bool encoders_cloneable(const struct intel_encoder *a,
12539 const struct intel_encoder *b)
12540 {
12541 /* masks could be asymmetric, so check both ways */
12542 return a == b || (a->cloneable & (1 << b->type) &&
12543 b->cloneable & (1 << a->type));
12544 }
12545
12546 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12547 struct intel_crtc *crtc,
12548 struct intel_encoder *encoder)
12549 {
12550 struct intel_encoder *source_encoder;
12551 struct drm_connector *connector;
12552 struct drm_connector_state *connector_state;
12553 int i;
12554
12555 for_each_connector_in_state(state, connector, connector_state, i) {
12556 if (connector_state->crtc != &crtc->base)
12557 continue;
12558
12559 source_encoder =
12560 to_intel_encoder(connector_state->best_encoder);
12561 if (!encoders_cloneable(encoder, source_encoder))
12562 return false;
12563 }
12564
12565 return true;
12566 }
12567
12568 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12569 struct drm_crtc_state *crtc_state)
12570 {
12571 struct drm_device *dev = crtc->dev;
12572 struct drm_i915_private *dev_priv = to_i915(dev);
12573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12574 struct intel_crtc_state *pipe_config =
12575 to_intel_crtc_state(crtc_state);
12576 struct drm_atomic_state *state = crtc_state->state;
12577 int ret;
12578 bool mode_changed = needs_modeset(crtc_state);
12579
12580 if (mode_changed && !crtc_state->active)
12581 pipe_config->update_wm_post = true;
12582
12583 if (mode_changed && crtc_state->enable &&
12584 dev_priv->display.crtc_compute_clock &&
12585 !WARN_ON(pipe_config->shared_dpll)) {
12586 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12587 pipe_config);
12588 if (ret)
12589 return ret;
12590 }
12591
12592 if (crtc_state->color_mgmt_changed) {
12593 ret = intel_color_check(crtc, crtc_state);
12594 if (ret)
12595 return ret;
12596
12597 /*
12598 * Changing color management on Intel hardware is
12599 * handled as part of planes update.
12600 */
12601 crtc_state->planes_changed = true;
12602 }
12603
12604 ret = 0;
12605 if (dev_priv->display.compute_pipe_wm) {
12606 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12607 if (ret) {
12608 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12609 return ret;
12610 }
12611 }
12612
12613 if (dev_priv->display.compute_intermediate_wm &&
12614 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12615 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12616 return 0;
12617
12618 /*
12619 * Calculate 'intermediate' watermarks that satisfy both the
12620 * old state and the new state. We can program these
12621 * immediately.
12622 */
12623 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12624 intel_crtc,
12625 pipe_config);
12626 if (ret) {
12627 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12628 return ret;
12629 }
12630 } else if (dev_priv->display.compute_intermediate_wm) {
12631 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12632 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12633 }
12634
12635 if (INTEL_INFO(dev)->gen >= 9) {
12636 if (mode_changed)
12637 ret = skl_update_scaler_crtc(pipe_config);
12638
12639 if (!ret)
12640 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12641 pipe_config);
12642 }
12643
12644 return ret;
12645 }
12646
12647 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12648 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12649 .atomic_begin = intel_begin_crtc_commit,
12650 .atomic_flush = intel_finish_crtc_commit,
12651 .atomic_check = intel_crtc_atomic_check,
12652 };
12653
12654 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12655 {
12656 struct intel_connector *connector;
12657
12658 for_each_intel_connector(dev, connector) {
12659 if (connector->base.state->crtc)
12660 drm_connector_unreference(&connector->base);
12661
12662 if (connector->base.encoder) {
12663 connector->base.state->best_encoder =
12664 connector->base.encoder;
12665 connector->base.state->crtc =
12666 connector->base.encoder->crtc;
12667
12668 drm_connector_reference(&connector->base);
12669 } else {
12670 connector->base.state->best_encoder = NULL;
12671 connector->base.state->crtc = NULL;
12672 }
12673 }
12674 }
12675
12676 static void
12677 connected_sink_compute_bpp(struct intel_connector *connector,
12678 struct intel_crtc_state *pipe_config)
12679 {
12680 const struct drm_display_info *info = &connector->base.display_info;
12681 int bpp = pipe_config->pipe_bpp;
12682
12683 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12684 connector->base.base.id,
12685 connector->base.name);
12686
12687 /* Don't use an invalid EDID bpc value */
12688 if (info->bpc != 0 && info->bpc * 3 < bpp) {
12689 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12690 bpp, info->bpc * 3);
12691 pipe_config->pipe_bpp = info->bpc * 3;
12692 }
12693
12694 /* Clamp bpp to 8 on screens without EDID 1.4 */
12695 if (info->bpc == 0 && bpp > 24) {
12696 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12697 bpp);
12698 pipe_config->pipe_bpp = 24;
12699 }
12700 }
12701
12702 static int
12703 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12704 struct intel_crtc_state *pipe_config)
12705 {
12706 struct drm_device *dev = crtc->base.dev;
12707 struct drm_atomic_state *state;
12708 struct drm_connector *connector;
12709 struct drm_connector_state *connector_state;
12710 int bpp, i;
12711
12712 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12713 bpp = 10*3;
12714 else if (INTEL_INFO(dev)->gen >= 5)
12715 bpp = 12*3;
12716 else
12717 bpp = 8*3;
12718
12719
12720 pipe_config->pipe_bpp = bpp;
12721
12722 state = pipe_config->base.state;
12723
12724 /* Clamp display bpp to EDID value */
12725 for_each_connector_in_state(state, connector, connector_state, i) {
12726 if (connector_state->crtc != &crtc->base)
12727 continue;
12728
12729 connected_sink_compute_bpp(to_intel_connector(connector),
12730 pipe_config);
12731 }
12732
12733 return bpp;
12734 }
12735
12736 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12737 {
12738 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12739 "type: 0x%x flags: 0x%x\n",
12740 mode->crtc_clock,
12741 mode->crtc_hdisplay, mode->crtc_hsync_start,
12742 mode->crtc_hsync_end, mode->crtc_htotal,
12743 mode->crtc_vdisplay, mode->crtc_vsync_start,
12744 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12745 }
12746
12747 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12748 struct intel_crtc_state *pipe_config,
12749 const char *context)
12750 {
12751 struct drm_device *dev = crtc->base.dev;
12752 struct drm_i915_private *dev_priv = to_i915(dev);
12753 struct drm_plane *plane;
12754 struct intel_plane *intel_plane;
12755 struct intel_plane_state *state;
12756 struct drm_framebuffer *fb;
12757
12758 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12759 crtc->base.base.id, crtc->base.name,
12760 context, pipe_config, pipe_name(crtc->pipe));
12761
12762 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12763 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12764 pipe_config->pipe_bpp, pipe_config->dither);
12765 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12766 pipe_config->has_pch_encoder,
12767 pipe_config->fdi_lanes,
12768 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12769 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12770 pipe_config->fdi_m_n.tu);
12771 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12772 intel_crtc_has_dp_encoder(pipe_config),
12773 pipe_config->lane_count,
12774 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12775 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12776 pipe_config->dp_m_n.tu);
12777
12778 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12779 intel_crtc_has_dp_encoder(pipe_config),
12780 pipe_config->lane_count,
12781 pipe_config->dp_m2_n2.gmch_m,
12782 pipe_config->dp_m2_n2.gmch_n,
12783 pipe_config->dp_m2_n2.link_m,
12784 pipe_config->dp_m2_n2.link_n,
12785 pipe_config->dp_m2_n2.tu);
12786
12787 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12788 pipe_config->has_audio,
12789 pipe_config->has_infoframe);
12790
12791 DRM_DEBUG_KMS("requested mode:\n");
12792 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12793 DRM_DEBUG_KMS("adjusted mode:\n");
12794 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12795 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12796 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12797 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12798 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12799 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12800 crtc->num_scalers,
12801 pipe_config->scaler_state.scaler_users,
12802 pipe_config->scaler_state.scaler_id);
12803 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12804 pipe_config->gmch_pfit.control,
12805 pipe_config->gmch_pfit.pgm_ratios,
12806 pipe_config->gmch_pfit.lvds_border_bits);
12807 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12808 pipe_config->pch_pfit.pos,
12809 pipe_config->pch_pfit.size,
12810 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12811 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12812 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12813
12814 if (IS_BROXTON(dev_priv)) {
12815 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12816 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12817 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12818 pipe_config->dpll_hw_state.ebb0,
12819 pipe_config->dpll_hw_state.ebb4,
12820 pipe_config->dpll_hw_state.pll0,
12821 pipe_config->dpll_hw_state.pll1,
12822 pipe_config->dpll_hw_state.pll2,
12823 pipe_config->dpll_hw_state.pll3,
12824 pipe_config->dpll_hw_state.pll6,
12825 pipe_config->dpll_hw_state.pll8,
12826 pipe_config->dpll_hw_state.pll9,
12827 pipe_config->dpll_hw_state.pll10,
12828 pipe_config->dpll_hw_state.pcsdw12);
12829 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12830 DRM_DEBUG_KMS("dpll_hw_state: "
12831 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12832 pipe_config->dpll_hw_state.ctrl1,
12833 pipe_config->dpll_hw_state.cfgcr1,
12834 pipe_config->dpll_hw_state.cfgcr2);
12835 } else if (HAS_DDI(dev_priv)) {
12836 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12837 pipe_config->dpll_hw_state.wrpll,
12838 pipe_config->dpll_hw_state.spll);
12839 } else {
12840 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12841 "fp0: 0x%x, fp1: 0x%x\n",
12842 pipe_config->dpll_hw_state.dpll,
12843 pipe_config->dpll_hw_state.dpll_md,
12844 pipe_config->dpll_hw_state.fp0,
12845 pipe_config->dpll_hw_state.fp1);
12846 }
12847
12848 DRM_DEBUG_KMS("planes on this crtc\n");
12849 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12850 char *format_name;
12851 intel_plane = to_intel_plane(plane);
12852 if (intel_plane->pipe != crtc->pipe)
12853 continue;
12854
12855 state = to_intel_plane_state(plane->state);
12856 fb = state->base.fb;
12857 if (!fb) {
12858 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12859 plane->base.id, plane->name, state->scaler_id);
12860 continue;
12861 }
12862
12863 format_name = drm_get_format_name(fb->pixel_format);
12864
12865 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12866 plane->base.id, plane->name);
12867 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12868 fb->base.id, fb->width, fb->height, format_name);
12869 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12870 state->scaler_id,
12871 state->base.src.x1 >> 16,
12872 state->base.src.y1 >> 16,
12873 drm_rect_width(&state->base.src) >> 16,
12874 drm_rect_height(&state->base.src) >> 16,
12875 state->base.dst.x1, state->base.dst.y1,
12876 drm_rect_width(&state->base.dst),
12877 drm_rect_height(&state->base.dst));
12878
12879 kfree(format_name);
12880 }
12881 }
12882
12883 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12884 {
12885 struct drm_device *dev = state->dev;
12886 struct drm_connector *connector;
12887 unsigned int used_ports = 0;
12888 unsigned int used_mst_ports = 0;
12889
12890 /*
12891 * Walk the connector list instead of the encoder
12892 * list to detect the problem on ddi platforms
12893 * where there's just one encoder per digital port.
12894 */
12895 drm_for_each_connector(connector, dev) {
12896 struct drm_connector_state *connector_state;
12897 struct intel_encoder *encoder;
12898
12899 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12900 if (!connector_state)
12901 connector_state = connector->state;
12902
12903 if (!connector_state->best_encoder)
12904 continue;
12905
12906 encoder = to_intel_encoder(connector_state->best_encoder);
12907
12908 WARN_ON(!connector_state->crtc);
12909
12910 switch (encoder->type) {
12911 unsigned int port_mask;
12912 case INTEL_OUTPUT_UNKNOWN:
12913 if (WARN_ON(!HAS_DDI(to_i915(dev))))
12914 break;
12915 case INTEL_OUTPUT_DP:
12916 case INTEL_OUTPUT_HDMI:
12917 case INTEL_OUTPUT_EDP:
12918 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12919
12920 /* the same port mustn't appear more than once */
12921 if (used_ports & port_mask)
12922 return false;
12923
12924 used_ports |= port_mask;
12925 break;
12926 case INTEL_OUTPUT_DP_MST:
12927 used_mst_ports |=
12928 1 << enc_to_mst(&encoder->base)->primary->port;
12929 break;
12930 default:
12931 break;
12932 }
12933 }
12934
12935 /* can't mix MST and SST/HDMI on the same port */
12936 if (used_ports & used_mst_ports)
12937 return false;
12938
12939 return true;
12940 }
12941
12942 static void
12943 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12944 {
12945 struct drm_crtc_state tmp_state;
12946 struct intel_crtc_scaler_state scaler_state;
12947 struct intel_dpll_hw_state dpll_hw_state;
12948 struct intel_shared_dpll *shared_dpll;
12949 bool force_thru;
12950
12951 /* FIXME: before the switch to atomic started, a new pipe_config was
12952 * kzalloc'd. Code that depends on any field being zero should be
12953 * fixed, so that the crtc_state can be safely duplicated. For now,
12954 * only fields that are know to not cause problems are preserved. */
12955
12956 tmp_state = crtc_state->base;
12957 scaler_state = crtc_state->scaler_state;
12958 shared_dpll = crtc_state->shared_dpll;
12959 dpll_hw_state = crtc_state->dpll_hw_state;
12960 force_thru = crtc_state->pch_pfit.force_thru;
12961
12962 memset(crtc_state, 0, sizeof *crtc_state);
12963
12964 crtc_state->base = tmp_state;
12965 crtc_state->scaler_state = scaler_state;
12966 crtc_state->shared_dpll = shared_dpll;
12967 crtc_state->dpll_hw_state = dpll_hw_state;
12968 crtc_state->pch_pfit.force_thru = force_thru;
12969 }
12970
12971 static int
12972 intel_modeset_pipe_config(struct drm_crtc *crtc,
12973 struct intel_crtc_state *pipe_config)
12974 {
12975 struct drm_atomic_state *state = pipe_config->base.state;
12976 struct intel_encoder *encoder;
12977 struct drm_connector *connector;
12978 struct drm_connector_state *connector_state;
12979 int base_bpp, ret = -EINVAL;
12980 int i;
12981 bool retry = true;
12982
12983 clear_intel_crtc_state(pipe_config);
12984
12985 pipe_config->cpu_transcoder =
12986 (enum transcoder) to_intel_crtc(crtc)->pipe;
12987
12988 /*
12989 * Sanitize sync polarity flags based on requested ones. If neither
12990 * positive or negative polarity is requested, treat this as meaning
12991 * negative polarity.
12992 */
12993 if (!(pipe_config->base.adjusted_mode.flags &
12994 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12995 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12996
12997 if (!(pipe_config->base.adjusted_mode.flags &
12998 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12999 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13000
13001 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13002 pipe_config);
13003 if (base_bpp < 0)
13004 goto fail;
13005
13006 /*
13007 * Determine the real pipe dimensions. Note that stereo modes can
13008 * increase the actual pipe size due to the frame doubling and
13009 * insertion of additional space for blanks between the frame. This
13010 * is stored in the crtc timings. We use the requested mode to do this
13011 * computation to clearly distinguish it from the adjusted mode, which
13012 * can be changed by the connectors in the below retry loop.
13013 */
13014 drm_crtc_get_hv_timing(&pipe_config->base.mode,
13015 &pipe_config->pipe_src_w,
13016 &pipe_config->pipe_src_h);
13017
13018 for_each_connector_in_state(state, connector, connector_state, i) {
13019 if (connector_state->crtc != crtc)
13020 continue;
13021
13022 encoder = to_intel_encoder(connector_state->best_encoder);
13023
13024 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13025 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13026 goto fail;
13027 }
13028
13029 /*
13030 * Determine output_types before calling the .compute_config()
13031 * hooks so that the hooks can use this information safely.
13032 */
13033 pipe_config->output_types |= 1 << encoder->type;
13034 }
13035
13036 encoder_retry:
13037 /* Ensure the port clock defaults are reset when retrying. */
13038 pipe_config->port_clock = 0;
13039 pipe_config->pixel_multiplier = 1;
13040
13041 /* Fill in default crtc timings, allow encoders to overwrite them. */
13042 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13043 CRTC_STEREO_DOUBLE);
13044
13045 /* Pass our mode to the connectors and the CRTC to give them a chance to
13046 * adjust it according to limitations or connector properties, and also
13047 * a chance to reject the mode entirely.
13048 */
13049 for_each_connector_in_state(state, connector, connector_state, i) {
13050 if (connector_state->crtc != crtc)
13051 continue;
13052
13053 encoder = to_intel_encoder(connector_state->best_encoder);
13054
13055 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13056 DRM_DEBUG_KMS("Encoder config failure\n");
13057 goto fail;
13058 }
13059 }
13060
13061 /* Set default port clock if not overwritten by the encoder. Needs to be
13062 * done afterwards in case the encoder adjusts the mode. */
13063 if (!pipe_config->port_clock)
13064 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13065 * pipe_config->pixel_multiplier;
13066
13067 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13068 if (ret < 0) {
13069 DRM_DEBUG_KMS("CRTC fixup failed\n");
13070 goto fail;
13071 }
13072
13073 if (ret == RETRY) {
13074 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13075 ret = -EINVAL;
13076 goto fail;
13077 }
13078
13079 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13080 retry = false;
13081 goto encoder_retry;
13082 }
13083
13084 /* Dithering seems to not pass-through bits correctly when it should, so
13085 * only enable it on 6bpc panels. */
13086 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13087 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13088 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13089
13090 fail:
13091 return ret;
13092 }
13093
13094 static void
13095 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13096 {
13097 struct drm_crtc *crtc;
13098 struct drm_crtc_state *crtc_state;
13099 int i;
13100
13101 /* Double check state. */
13102 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13103 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13104
13105 /* Update hwmode for vblank functions */
13106 if (crtc->state->active)
13107 crtc->hwmode = crtc->state->adjusted_mode;
13108 else
13109 crtc->hwmode.crtc_clock = 0;
13110
13111 /*
13112 * Update legacy state to satisfy fbc code. This can
13113 * be removed when fbc uses the atomic state.
13114 */
13115 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13116 struct drm_plane_state *plane_state = crtc->primary->state;
13117
13118 crtc->primary->fb = plane_state->fb;
13119 crtc->x = plane_state->src_x >> 16;
13120 crtc->y = plane_state->src_y >> 16;
13121 }
13122 }
13123 }
13124
13125 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13126 {
13127 int diff;
13128
13129 if (clock1 == clock2)
13130 return true;
13131
13132 if (!clock1 || !clock2)
13133 return false;
13134
13135 diff = abs(clock1 - clock2);
13136
13137 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13138 return true;
13139
13140 return false;
13141 }
13142
13143 static bool
13144 intel_compare_m_n(unsigned int m, unsigned int n,
13145 unsigned int m2, unsigned int n2,
13146 bool exact)
13147 {
13148 if (m == m2 && n == n2)
13149 return true;
13150
13151 if (exact || !m || !n || !m2 || !n2)
13152 return false;
13153
13154 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13155
13156 if (n > n2) {
13157 while (n > n2) {
13158 m2 <<= 1;
13159 n2 <<= 1;
13160 }
13161 } else if (n < n2) {
13162 while (n < n2) {
13163 m <<= 1;
13164 n <<= 1;
13165 }
13166 }
13167
13168 if (n != n2)
13169 return false;
13170
13171 return intel_fuzzy_clock_check(m, m2);
13172 }
13173
13174 static bool
13175 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13176 struct intel_link_m_n *m2_n2,
13177 bool adjust)
13178 {
13179 if (m_n->tu == m2_n2->tu &&
13180 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13181 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13182 intel_compare_m_n(m_n->link_m, m_n->link_n,
13183 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13184 if (adjust)
13185 *m2_n2 = *m_n;
13186
13187 return true;
13188 }
13189
13190 return false;
13191 }
13192
13193 static bool
13194 intel_pipe_config_compare(struct drm_device *dev,
13195 struct intel_crtc_state *current_config,
13196 struct intel_crtc_state *pipe_config,
13197 bool adjust)
13198 {
13199 struct drm_i915_private *dev_priv = to_i915(dev);
13200 bool ret = true;
13201
13202 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13203 do { \
13204 if (!adjust) \
13205 DRM_ERROR(fmt, ##__VA_ARGS__); \
13206 else \
13207 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13208 } while (0)
13209
13210 #define PIPE_CONF_CHECK_X(name) \
13211 if (current_config->name != pipe_config->name) { \
13212 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13213 "(expected 0x%08x, found 0x%08x)\n", \
13214 current_config->name, \
13215 pipe_config->name); \
13216 ret = false; \
13217 }
13218
13219 #define PIPE_CONF_CHECK_I(name) \
13220 if (current_config->name != pipe_config->name) { \
13221 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13222 "(expected %i, found %i)\n", \
13223 current_config->name, \
13224 pipe_config->name); \
13225 ret = false; \
13226 }
13227
13228 #define PIPE_CONF_CHECK_P(name) \
13229 if (current_config->name != pipe_config->name) { \
13230 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13231 "(expected %p, found %p)\n", \
13232 current_config->name, \
13233 pipe_config->name); \
13234 ret = false; \
13235 }
13236
13237 #define PIPE_CONF_CHECK_M_N(name) \
13238 if (!intel_compare_link_m_n(&current_config->name, \
13239 &pipe_config->name,\
13240 adjust)) { \
13241 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13242 "(expected tu %i gmch %i/%i link %i/%i, " \
13243 "found tu %i, gmch %i/%i link %i/%i)\n", \
13244 current_config->name.tu, \
13245 current_config->name.gmch_m, \
13246 current_config->name.gmch_n, \
13247 current_config->name.link_m, \
13248 current_config->name.link_n, \
13249 pipe_config->name.tu, \
13250 pipe_config->name.gmch_m, \
13251 pipe_config->name.gmch_n, \
13252 pipe_config->name.link_m, \
13253 pipe_config->name.link_n); \
13254 ret = false; \
13255 }
13256
13257 /* This is required for BDW+ where there is only one set of registers for
13258 * switching between high and low RR.
13259 * This macro can be used whenever a comparison has to be made between one
13260 * hw state and multiple sw state variables.
13261 */
13262 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13263 if (!intel_compare_link_m_n(&current_config->name, \
13264 &pipe_config->name, adjust) && \
13265 !intel_compare_link_m_n(&current_config->alt_name, \
13266 &pipe_config->name, adjust)) { \
13267 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13268 "(expected tu %i gmch %i/%i link %i/%i, " \
13269 "or tu %i gmch %i/%i link %i/%i, " \
13270 "found tu %i, gmch %i/%i link %i/%i)\n", \
13271 current_config->name.tu, \
13272 current_config->name.gmch_m, \
13273 current_config->name.gmch_n, \
13274 current_config->name.link_m, \
13275 current_config->name.link_n, \
13276 current_config->alt_name.tu, \
13277 current_config->alt_name.gmch_m, \
13278 current_config->alt_name.gmch_n, \
13279 current_config->alt_name.link_m, \
13280 current_config->alt_name.link_n, \
13281 pipe_config->name.tu, \
13282 pipe_config->name.gmch_m, \
13283 pipe_config->name.gmch_n, \
13284 pipe_config->name.link_m, \
13285 pipe_config->name.link_n); \
13286 ret = false; \
13287 }
13288
13289 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13290 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13291 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13292 "(expected %i, found %i)\n", \
13293 current_config->name & (mask), \
13294 pipe_config->name & (mask)); \
13295 ret = false; \
13296 }
13297
13298 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13299 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13300 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13301 "(expected %i, found %i)\n", \
13302 current_config->name, \
13303 pipe_config->name); \
13304 ret = false; \
13305 }
13306
13307 #define PIPE_CONF_QUIRK(quirk) \
13308 ((current_config->quirks | pipe_config->quirks) & (quirk))
13309
13310 PIPE_CONF_CHECK_I(cpu_transcoder);
13311
13312 PIPE_CONF_CHECK_I(has_pch_encoder);
13313 PIPE_CONF_CHECK_I(fdi_lanes);
13314 PIPE_CONF_CHECK_M_N(fdi_m_n);
13315
13316 PIPE_CONF_CHECK_I(lane_count);
13317 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13318
13319 if (INTEL_INFO(dev)->gen < 8) {
13320 PIPE_CONF_CHECK_M_N(dp_m_n);
13321
13322 if (current_config->has_drrs)
13323 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13324 } else
13325 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13326
13327 PIPE_CONF_CHECK_X(output_types);
13328
13329 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13330 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13331 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13332 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13333 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13334 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13335
13336 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13337 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13338 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13339 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13340 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13341 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13342
13343 PIPE_CONF_CHECK_I(pixel_multiplier);
13344 PIPE_CONF_CHECK_I(has_hdmi_sink);
13345 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13346 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13347 PIPE_CONF_CHECK_I(limited_color_range);
13348 PIPE_CONF_CHECK_I(has_infoframe);
13349
13350 PIPE_CONF_CHECK_I(has_audio);
13351
13352 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13353 DRM_MODE_FLAG_INTERLACE);
13354
13355 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13356 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13357 DRM_MODE_FLAG_PHSYNC);
13358 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13359 DRM_MODE_FLAG_NHSYNC);
13360 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13361 DRM_MODE_FLAG_PVSYNC);
13362 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13363 DRM_MODE_FLAG_NVSYNC);
13364 }
13365
13366 PIPE_CONF_CHECK_X(gmch_pfit.control);
13367 /* pfit ratios are autocomputed by the hw on gen4+ */
13368 if (INTEL_INFO(dev)->gen < 4)
13369 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13370 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13371
13372 if (!adjust) {
13373 PIPE_CONF_CHECK_I(pipe_src_w);
13374 PIPE_CONF_CHECK_I(pipe_src_h);
13375
13376 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13377 if (current_config->pch_pfit.enabled) {
13378 PIPE_CONF_CHECK_X(pch_pfit.pos);
13379 PIPE_CONF_CHECK_X(pch_pfit.size);
13380 }
13381
13382 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13383 }
13384
13385 /* BDW+ don't expose a synchronous way to read the state */
13386 if (IS_HASWELL(dev_priv))
13387 PIPE_CONF_CHECK_I(ips_enabled);
13388
13389 PIPE_CONF_CHECK_I(double_wide);
13390
13391 PIPE_CONF_CHECK_P(shared_dpll);
13392 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13393 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13394 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13395 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13396 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13397 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13398 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13399 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13400 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13401
13402 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13403 PIPE_CONF_CHECK_X(dsi_pll.div);
13404
13405 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13406 PIPE_CONF_CHECK_I(pipe_bpp);
13407
13408 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13409 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13410
13411 #undef PIPE_CONF_CHECK_X
13412 #undef PIPE_CONF_CHECK_I
13413 #undef PIPE_CONF_CHECK_P
13414 #undef PIPE_CONF_CHECK_FLAGS
13415 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13416 #undef PIPE_CONF_QUIRK
13417 #undef INTEL_ERR_OR_DBG_KMS
13418
13419 return ret;
13420 }
13421
13422 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13423 const struct intel_crtc_state *pipe_config)
13424 {
13425 if (pipe_config->has_pch_encoder) {
13426 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13427 &pipe_config->fdi_m_n);
13428 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13429
13430 /*
13431 * FDI already provided one idea for the dotclock.
13432 * Yell if the encoder disagrees.
13433 */
13434 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13435 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13436 fdi_dotclock, dotclock);
13437 }
13438 }
13439
13440 static void verify_wm_state(struct drm_crtc *crtc,
13441 struct drm_crtc_state *new_state)
13442 {
13443 struct drm_device *dev = crtc->dev;
13444 struct drm_i915_private *dev_priv = to_i915(dev);
13445 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13446 struct skl_ddb_entry *hw_entry, *sw_entry;
13447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13448 const enum pipe pipe = intel_crtc->pipe;
13449 int plane;
13450
13451 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13452 return;
13453
13454 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13455 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13456
13457 /* planes */
13458 for_each_plane(dev_priv, pipe, plane) {
13459 hw_entry = &hw_ddb.plane[pipe][plane];
13460 sw_entry = &sw_ddb->plane[pipe][plane];
13461
13462 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13463 continue;
13464
13465 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13466 "(expected (%u,%u), found (%u,%u))\n",
13467 pipe_name(pipe), plane + 1,
13468 sw_entry->start, sw_entry->end,
13469 hw_entry->start, hw_entry->end);
13470 }
13471
13472 /*
13473 * cursor
13474 * If the cursor plane isn't active, we may not have updated it's ddb
13475 * allocation. In that case since the ddb allocation will be updated
13476 * once the plane becomes visible, we can skip this check
13477 */
13478 if (intel_crtc->cursor_addr) {
13479 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13480 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13481
13482 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13483 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13484 "(expected (%u,%u), found (%u,%u))\n",
13485 pipe_name(pipe),
13486 sw_entry->start, sw_entry->end,
13487 hw_entry->start, hw_entry->end);
13488 }
13489 }
13490 }
13491
13492 static void
13493 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13494 {
13495 struct drm_connector *connector;
13496
13497 drm_for_each_connector(connector, dev) {
13498 struct drm_encoder *encoder = connector->encoder;
13499 struct drm_connector_state *state = connector->state;
13500
13501 if (state->crtc != crtc)
13502 continue;
13503
13504 intel_connector_verify_state(to_intel_connector(connector));
13505
13506 I915_STATE_WARN(state->best_encoder != encoder,
13507 "connector's atomic encoder doesn't match legacy encoder\n");
13508 }
13509 }
13510
13511 static void
13512 verify_encoder_state(struct drm_device *dev)
13513 {
13514 struct intel_encoder *encoder;
13515 struct intel_connector *connector;
13516
13517 for_each_intel_encoder(dev, encoder) {
13518 bool enabled = false;
13519 enum pipe pipe;
13520
13521 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13522 encoder->base.base.id,
13523 encoder->base.name);
13524
13525 for_each_intel_connector(dev, connector) {
13526 if (connector->base.state->best_encoder != &encoder->base)
13527 continue;
13528 enabled = true;
13529
13530 I915_STATE_WARN(connector->base.state->crtc !=
13531 encoder->base.crtc,
13532 "connector's crtc doesn't match encoder crtc\n");
13533 }
13534
13535 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13536 "encoder's enabled state mismatch "
13537 "(expected %i, found %i)\n",
13538 !!encoder->base.crtc, enabled);
13539
13540 if (!encoder->base.crtc) {
13541 bool active;
13542
13543 active = encoder->get_hw_state(encoder, &pipe);
13544 I915_STATE_WARN(active,
13545 "encoder detached but still enabled on pipe %c.\n",
13546 pipe_name(pipe));
13547 }
13548 }
13549 }
13550
13551 static void
13552 verify_crtc_state(struct drm_crtc *crtc,
13553 struct drm_crtc_state *old_crtc_state,
13554 struct drm_crtc_state *new_crtc_state)
13555 {
13556 struct drm_device *dev = crtc->dev;
13557 struct drm_i915_private *dev_priv = to_i915(dev);
13558 struct intel_encoder *encoder;
13559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13560 struct intel_crtc_state *pipe_config, *sw_config;
13561 struct drm_atomic_state *old_state;
13562 bool active;
13563
13564 old_state = old_crtc_state->state;
13565 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13566 pipe_config = to_intel_crtc_state(old_crtc_state);
13567 memset(pipe_config, 0, sizeof(*pipe_config));
13568 pipe_config->base.crtc = crtc;
13569 pipe_config->base.state = old_state;
13570
13571 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13572
13573 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13574
13575 /* hw state is inconsistent with the pipe quirk */
13576 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13577 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13578 active = new_crtc_state->active;
13579
13580 I915_STATE_WARN(new_crtc_state->active != active,
13581 "crtc active state doesn't match with hw state "
13582 "(expected %i, found %i)\n", new_crtc_state->active, active);
13583
13584 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13585 "transitional active state does not match atomic hw state "
13586 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13587
13588 for_each_encoder_on_crtc(dev, crtc, encoder) {
13589 enum pipe pipe;
13590
13591 active = encoder->get_hw_state(encoder, &pipe);
13592 I915_STATE_WARN(active != new_crtc_state->active,
13593 "[ENCODER:%i] active %i with crtc active %i\n",
13594 encoder->base.base.id, active, new_crtc_state->active);
13595
13596 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13597 "Encoder connected to wrong pipe %c\n",
13598 pipe_name(pipe));
13599
13600 if (active) {
13601 pipe_config->output_types |= 1 << encoder->type;
13602 encoder->get_config(encoder, pipe_config);
13603 }
13604 }
13605
13606 if (!new_crtc_state->active)
13607 return;
13608
13609 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13610
13611 sw_config = to_intel_crtc_state(crtc->state);
13612 if (!intel_pipe_config_compare(dev, sw_config,
13613 pipe_config, false)) {
13614 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13615 intel_dump_pipe_config(intel_crtc, pipe_config,
13616 "[hw state]");
13617 intel_dump_pipe_config(intel_crtc, sw_config,
13618 "[sw state]");
13619 }
13620 }
13621
13622 static void
13623 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13624 struct intel_shared_dpll *pll,
13625 struct drm_crtc *crtc,
13626 struct drm_crtc_state *new_state)
13627 {
13628 struct intel_dpll_hw_state dpll_hw_state;
13629 unsigned crtc_mask;
13630 bool active;
13631
13632 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13633
13634 DRM_DEBUG_KMS("%s\n", pll->name);
13635
13636 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13637
13638 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13639 I915_STATE_WARN(!pll->on && pll->active_mask,
13640 "pll in active use but not on in sw tracking\n");
13641 I915_STATE_WARN(pll->on && !pll->active_mask,
13642 "pll is on but not used by any active crtc\n");
13643 I915_STATE_WARN(pll->on != active,
13644 "pll on state mismatch (expected %i, found %i)\n",
13645 pll->on, active);
13646 }
13647
13648 if (!crtc) {
13649 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13650 "more active pll users than references: %x vs %x\n",
13651 pll->active_mask, pll->config.crtc_mask);
13652
13653 return;
13654 }
13655
13656 crtc_mask = 1 << drm_crtc_index(crtc);
13657
13658 if (new_state->active)
13659 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13660 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13661 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13662 else
13663 I915_STATE_WARN(pll->active_mask & crtc_mask,
13664 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13665 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13666
13667 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13668 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13669 crtc_mask, pll->config.crtc_mask);
13670
13671 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13672 &dpll_hw_state,
13673 sizeof(dpll_hw_state)),
13674 "pll hw state mismatch\n");
13675 }
13676
13677 static void
13678 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13679 struct drm_crtc_state *old_crtc_state,
13680 struct drm_crtc_state *new_crtc_state)
13681 {
13682 struct drm_i915_private *dev_priv = to_i915(dev);
13683 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13684 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13685
13686 if (new_state->shared_dpll)
13687 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13688
13689 if (old_state->shared_dpll &&
13690 old_state->shared_dpll != new_state->shared_dpll) {
13691 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13692 struct intel_shared_dpll *pll = old_state->shared_dpll;
13693
13694 I915_STATE_WARN(pll->active_mask & crtc_mask,
13695 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13696 pipe_name(drm_crtc_index(crtc)));
13697 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13698 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13699 pipe_name(drm_crtc_index(crtc)));
13700 }
13701 }
13702
13703 static void
13704 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13705 struct drm_crtc_state *old_state,
13706 struct drm_crtc_state *new_state)
13707 {
13708 if (!needs_modeset(new_state) &&
13709 !to_intel_crtc_state(new_state)->update_pipe)
13710 return;
13711
13712 verify_wm_state(crtc, new_state);
13713 verify_connector_state(crtc->dev, crtc);
13714 verify_crtc_state(crtc, old_state, new_state);
13715 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13716 }
13717
13718 static void
13719 verify_disabled_dpll_state(struct drm_device *dev)
13720 {
13721 struct drm_i915_private *dev_priv = to_i915(dev);
13722 int i;
13723
13724 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13725 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13726 }
13727
13728 static void
13729 intel_modeset_verify_disabled(struct drm_device *dev)
13730 {
13731 verify_encoder_state(dev);
13732 verify_connector_state(dev, NULL);
13733 verify_disabled_dpll_state(dev);
13734 }
13735
13736 static void update_scanline_offset(struct intel_crtc *crtc)
13737 {
13738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13739
13740 /*
13741 * The scanline counter increments at the leading edge of hsync.
13742 *
13743 * On most platforms it starts counting from vtotal-1 on the
13744 * first active line. That means the scanline counter value is
13745 * always one less than what we would expect. Ie. just after
13746 * start of vblank, which also occurs at start of hsync (on the
13747 * last active line), the scanline counter will read vblank_start-1.
13748 *
13749 * On gen2 the scanline counter starts counting from 1 instead
13750 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13751 * to keep the value positive), instead of adding one.
13752 *
13753 * On HSW+ the behaviour of the scanline counter depends on the output
13754 * type. For DP ports it behaves like most other platforms, but on HDMI
13755 * there's an extra 1 line difference. So we need to add two instead of
13756 * one to the value.
13757 */
13758 if (IS_GEN2(dev_priv)) {
13759 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13760 int vtotal;
13761
13762 vtotal = adjusted_mode->crtc_vtotal;
13763 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13764 vtotal /= 2;
13765
13766 crtc->scanline_offset = vtotal - 1;
13767 } else if (HAS_DDI(dev_priv) &&
13768 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13769 crtc->scanline_offset = 2;
13770 } else
13771 crtc->scanline_offset = 1;
13772 }
13773
13774 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13775 {
13776 struct drm_device *dev = state->dev;
13777 struct drm_i915_private *dev_priv = to_i915(dev);
13778 struct intel_shared_dpll_config *shared_dpll = NULL;
13779 struct drm_crtc *crtc;
13780 struct drm_crtc_state *crtc_state;
13781 int i;
13782
13783 if (!dev_priv->display.crtc_compute_clock)
13784 return;
13785
13786 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13788 struct intel_shared_dpll *old_dpll =
13789 to_intel_crtc_state(crtc->state)->shared_dpll;
13790
13791 if (!needs_modeset(crtc_state))
13792 continue;
13793
13794 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13795
13796 if (!old_dpll)
13797 continue;
13798
13799 if (!shared_dpll)
13800 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13801
13802 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13803 }
13804 }
13805
13806 /*
13807 * This implements the workaround described in the "notes" section of the mode
13808 * set sequence documentation. When going from no pipes or single pipe to
13809 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13810 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13811 */
13812 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13813 {
13814 struct drm_crtc_state *crtc_state;
13815 struct intel_crtc *intel_crtc;
13816 struct drm_crtc *crtc;
13817 struct intel_crtc_state *first_crtc_state = NULL;
13818 struct intel_crtc_state *other_crtc_state = NULL;
13819 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13820 int i;
13821
13822 /* look at all crtc's that are going to be enabled in during modeset */
13823 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13824 intel_crtc = to_intel_crtc(crtc);
13825
13826 if (!crtc_state->active || !needs_modeset(crtc_state))
13827 continue;
13828
13829 if (first_crtc_state) {
13830 other_crtc_state = to_intel_crtc_state(crtc_state);
13831 break;
13832 } else {
13833 first_crtc_state = to_intel_crtc_state(crtc_state);
13834 first_pipe = intel_crtc->pipe;
13835 }
13836 }
13837
13838 /* No workaround needed? */
13839 if (!first_crtc_state)
13840 return 0;
13841
13842 /* w/a possibly needed, check how many crtc's are already enabled. */
13843 for_each_intel_crtc(state->dev, intel_crtc) {
13844 struct intel_crtc_state *pipe_config;
13845
13846 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13847 if (IS_ERR(pipe_config))
13848 return PTR_ERR(pipe_config);
13849
13850 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13851
13852 if (!pipe_config->base.active ||
13853 needs_modeset(&pipe_config->base))
13854 continue;
13855
13856 /* 2 or more enabled crtcs means no need for w/a */
13857 if (enabled_pipe != INVALID_PIPE)
13858 return 0;
13859
13860 enabled_pipe = intel_crtc->pipe;
13861 }
13862
13863 if (enabled_pipe != INVALID_PIPE)
13864 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13865 else if (other_crtc_state)
13866 other_crtc_state->hsw_workaround_pipe = first_pipe;
13867
13868 return 0;
13869 }
13870
13871 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13872 {
13873 struct drm_crtc *crtc;
13874 struct drm_crtc_state *crtc_state;
13875 int ret = 0;
13876
13877 /* add all active pipes to the state */
13878 for_each_crtc(state->dev, crtc) {
13879 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13880 if (IS_ERR(crtc_state))
13881 return PTR_ERR(crtc_state);
13882
13883 if (!crtc_state->active || needs_modeset(crtc_state))
13884 continue;
13885
13886 crtc_state->mode_changed = true;
13887
13888 ret = drm_atomic_add_affected_connectors(state, crtc);
13889 if (ret)
13890 break;
13891
13892 ret = drm_atomic_add_affected_planes(state, crtc);
13893 if (ret)
13894 break;
13895 }
13896
13897 return ret;
13898 }
13899
13900 static int intel_modeset_checks(struct drm_atomic_state *state)
13901 {
13902 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13903 struct drm_i915_private *dev_priv = to_i915(state->dev);
13904 struct drm_crtc *crtc;
13905 struct drm_crtc_state *crtc_state;
13906 int ret = 0, i;
13907
13908 if (!check_digital_port_conflicts(state)) {
13909 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13910 return -EINVAL;
13911 }
13912
13913 intel_state->modeset = true;
13914 intel_state->active_crtcs = dev_priv->active_crtcs;
13915
13916 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13917 if (crtc_state->active)
13918 intel_state->active_crtcs |= 1 << i;
13919 else
13920 intel_state->active_crtcs &= ~(1 << i);
13921
13922 if (crtc_state->active != crtc->state->active)
13923 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13924 }
13925
13926 /*
13927 * See if the config requires any additional preparation, e.g.
13928 * to adjust global state with pipes off. We need to do this
13929 * here so we can get the modeset_pipe updated config for the new
13930 * mode set on this crtc. For other crtcs we need to use the
13931 * adjusted_mode bits in the crtc directly.
13932 */
13933 if (dev_priv->display.modeset_calc_cdclk) {
13934 if (!intel_state->cdclk_pll_vco)
13935 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13936 if (!intel_state->cdclk_pll_vco)
13937 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13938
13939 ret = dev_priv->display.modeset_calc_cdclk(state);
13940 if (ret < 0)
13941 return ret;
13942
13943 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13944 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13945 ret = intel_modeset_all_pipes(state);
13946
13947 if (ret < 0)
13948 return ret;
13949
13950 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13951 intel_state->cdclk, intel_state->dev_cdclk);
13952 } else
13953 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13954
13955 intel_modeset_clear_plls(state);
13956
13957 if (IS_HASWELL(dev_priv))
13958 return haswell_mode_set_planes_workaround(state);
13959
13960 return 0;
13961 }
13962
13963 /*
13964 * Handle calculation of various watermark data at the end of the atomic check
13965 * phase. The code here should be run after the per-crtc and per-plane 'check'
13966 * handlers to ensure that all derived state has been updated.
13967 */
13968 static int calc_watermark_data(struct drm_atomic_state *state)
13969 {
13970 struct drm_device *dev = state->dev;
13971 struct drm_i915_private *dev_priv = to_i915(dev);
13972
13973 /* Is there platform-specific watermark information to calculate? */
13974 if (dev_priv->display.compute_global_watermarks)
13975 return dev_priv->display.compute_global_watermarks(state);
13976
13977 return 0;
13978 }
13979
13980 /**
13981 * intel_atomic_check - validate state object
13982 * @dev: drm device
13983 * @state: state to validate
13984 */
13985 static int intel_atomic_check(struct drm_device *dev,
13986 struct drm_atomic_state *state)
13987 {
13988 struct drm_i915_private *dev_priv = to_i915(dev);
13989 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13990 struct drm_crtc *crtc;
13991 struct drm_crtc_state *crtc_state;
13992 int ret, i;
13993 bool any_ms = false;
13994
13995 ret = drm_atomic_helper_check_modeset(dev, state);
13996 if (ret)
13997 return ret;
13998
13999 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14000 struct intel_crtc_state *pipe_config =
14001 to_intel_crtc_state(crtc_state);
14002
14003 /* Catch I915_MODE_FLAG_INHERITED */
14004 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14005 crtc_state->mode_changed = true;
14006
14007 if (!needs_modeset(crtc_state))
14008 continue;
14009
14010 if (!crtc_state->enable) {
14011 any_ms = true;
14012 continue;
14013 }
14014
14015 /* FIXME: For only active_changed we shouldn't need to do any
14016 * state recomputation at all. */
14017
14018 ret = drm_atomic_add_affected_connectors(state, crtc);
14019 if (ret)
14020 return ret;
14021
14022 ret = intel_modeset_pipe_config(crtc, pipe_config);
14023 if (ret) {
14024 intel_dump_pipe_config(to_intel_crtc(crtc),
14025 pipe_config, "[failed]");
14026 return ret;
14027 }
14028
14029 if (i915.fastboot &&
14030 intel_pipe_config_compare(dev,
14031 to_intel_crtc_state(crtc->state),
14032 pipe_config, true)) {
14033 crtc_state->mode_changed = false;
14034 to_intel_crtc_state(crtc_state)->update_pipe = true;
14035 }
14036
14037 if (needs_modeset(crtc_state))
14038 any_ms = true;
14039
14040 ret = drm_atomic_add_affected_planes(state, crtc);
14041 if (ret)
14042 return ret;
14043
14044 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14045 needs_modeset(crtc_state) ?
14046 "[modeset]" : "[fastset]");
14047 }
14048
14049 if (any_ms) {
14050 ret = intel_modeset_checks(state);
14051
14052 if (ret)
14053 return ret;
14054 } else
14055 intel_state->cdclk = dev_priv->cdclk_freq;
14056
14057 ret = drm_atomic_helper_check_planes(dev, state);
14058 if (ret)
14059 return ret;
14060
14061 intel_fbc_choose_crtc(dev_priv, state);
14062 return calc_watermark_data(state);
14063 }
14064
14065 static int intel_atomic_prepare_commit(struct drm_device *dev,
14066 struct drm_atomic_state *state,
14067 bool nonblock)
14068 {
14069 struct drm_i915_private *dev_priv = to_i915(dev);
14070 struct drm_plane_state *plane_state;
14071 struct drm_crtc_state *crtc_state;
14072 struct drm_plane *plane;
14073 struct drm_crtc *crtc;
14074 int i, ret;
14075
14076 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14077 if (state->legacy_cursor_update)
14078 continue;
14079
14080 ret = intel_crtc_wait_for_pending_flips(crtc);
14081 if (ret)
14082 return ret;
14083
14084 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14085 flush_workqueue(dev_priv->wq);
14086 }
14087
14088 ret = mutex_lock_interruptible(&dev->struct_mutex);
14089 if (ret)
14090 return ret;
14091
14092 ret = drm_atomic_helper_prepare_planes(dev, state);
14093 mutex_unlock(&dev->struct_mutex);
14094
14095 if (!ret && !nonblock) {
14096 for_each_plane_in_state(state, plane, plane_state, i) {
14097 struct intel_plane_state *intel_plane_state =
14098 to_intel_plane_state(plane_state);
14099
14100 if (!intel_plane_state->wait_req)
14101 continue;
14102
14103 ret = i915_wait_request(intel_plane_state->wait_req,
14104 I915_WAIT_INTERRUPTIBLE,
14105 NULL, NULL);
14106 if (ret) {
14107 /* Any hang should be swallowed by the wait */
14108 WARN_ON(ret == -EIO);
14109 mutex_lock(&dev->struct_mutex);
14110 drm_atomic_helper_cleanup_planes(dev, state);
14111 mutex_unlock(&dev->struct_mutex);
14112 break;
14113 }
14114 }
14115 }
14116
14117 return ret;
14118 }
14119
14120 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14121 {
14122 struct drm_device *dev = crtc->base.dev;
14123
14124 if (!dev->max_vblank_count)
14125 return drm_accurate_vblank_count(&crtc->base);
14126
14127 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14128 }
14129
14130 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14131 struct drm_i915_private *dev_priv,
14132 unsigned crtc_mask)
14133 {
14134 unsigned last_vblank_count[I915_MAX_PIPES];
14135 enum pipe pipe;
14136 int ret;
14137
14138 if (!crtc_mask)
14139 return;
14140
14141 for_each_pipe(dev_priv, pipe) {
14142 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14143
14144 if (!((1 << pipe) & crtc_mask))
14145 continue;
14146
14147 ret = drm_crtc_vblank_get(crtc);
14148 if (WARN_ON(ret != 0)) {
14149 crtc_mask &= ~(1 << pipe);
14150 continue;
14151 }
14152
14153 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14154 }
14155
14156 for_each_pipe(dev_priv, pipe) {
14157 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14158 long lret;
14159
14160 if (!((1 << pipe) & crtc_mask))
14161 continue;
14162
14163 lret = wait_event_timeout(dev->vblank[pipe].queue,
14164 last_vblank_count[pipe] !=
14165 drm_crtc_vblank_count(crtc),
14166 msecs_to_jiffies(50));
14167
14168 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14169
14170 drm_crtc_vblank_put(crtc);
14171 }
14172 }
14173
14174 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14175 {
14176 /* fb updated, need to unpin old fb */
14177 if (crtc_state->fb_changed)
14178 return true;
14179
14180 /* wm changes, need vblank before final wm's */
14181 if (crtc_state->update_wm_post)
14182 return true;
14183
14184 /*
14185 * cxsr is re-enabled after vblank.
14186 * This is already handled by crtc_state->update_wm_post,
14187 * but added for clarity.
14188 */
14189 if (crtc_state->disable_cxsr)
14190 return true;
14191
14192 return false;
14193 }
14194
14195 static void intel_update_crtc(struct drm_crtc *crtc,
14196 struct drm_atomic_state *state,
14197 struct drm_crtc_state *old_crtc_state,
14198 unsigned int *crtc_vblank_mask)
14199 {
14200 struct drm_device *dev = crtc->dev;
14201 struct drm_i915_private *dev_priv = to_i915(dev);
14202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14203 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14204 bool modeset = needs_modeset(crtc->state);
14205
14206 if (modeset) {
14207 update_scanline_offset(intel_crtc);
14208 dev_priv->display.crtc_enable(pipe_config, state);
14209 } else {
14210 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14211 }
14212
14213 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14214 intel_fbc_enable(
14215 intel_crtc, pipe_config,
14216 to_intel_plane_state(crtc->primary->state));
14217 }
14218
14219 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14220
14221 if (needs_vblank_wait(pipe_config))
14222 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14223 }
14224
14225 static void intel_update_crtcs(struct drm_atomic_state *state,
14226 unsigned int *crtc_vblank_mask)
14227 {
14228 struct drm_crtc *crtc;
14229 struct drm_crtc_state *old_crtc_state;
14230 int i;
14231
14232 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14233 if (!crtc->state->active)
14234 continue;
14235
14236 intel_update_crtc(crtc, state, old_crtc_state,
14237 crtc_vblank_mask);
14238 }
14239 }
14240
14241 static void skl_update_crtcs(struct drm_atomic_state *state,
14242 unsigned int *crtc_vblank_mask)
14243 {
14244 struct drm_device *dev = state->dev;
14245 struct drm_i915_private *dev_priv = to_i915(dev);
14246 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14247 struct drm_crtc *crtc;
14248 struct drm_crtc_state *old_crtc_state;
14249 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14250 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14251 unsigned int updated = 0;
14252 bool progress;
14253 enum pipe pipe;
14254
14255 /*
14256 * Whenever the number of active pipes changes, we need to make sure we
14257 * update the pipes in the right order so that their ddb allocations
14258 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14259 * cause pipe underruns and other bad stuff.
14260 */
14261 do {
14262 int i;
14263 progress = false;
14264
14265 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14266 bool vbl_wait = false;
14267 unsigned int cmask = drm_crtc_mask(crtc);
14268 pipe = to_intel_crtc(crtc)->pipe;
14269
14270 if (updated & cmask || !crtc->state->active)
14271 continue;
14272 if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14273 pipe))
14274 continue;
14275
14276 updated |= cmask;
14277
14278 /*
14279 * If this is an already active pipe, it's DDB changed,
14280 * and this isn't the last pipe that needs updating
14281 * then we need to wait for a vblank to pass for the
14282 * new ddb allocation to take effect.
14283 */
14284 if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14285 !crtc->state->active_changed &&
14286 intel_state->wm_results.dirty_pipes != updated)
14287 vbl_wait = true;
14288
14289 intel_update_crtc(crtc, state, old_crtc_state,
14290 crtc_vblank_mask);
14291
14292 if (vbl_wait)
14293 intel_wait_for_vblank(dev, pipe);
14294
14295 progress = true;
14296 }
14297 } while (progress);
14298 }
14299
14300 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14301 {
14302 struct drm_device *dev = state->dev;
14303 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14304 struct drm_i915_private *dev_priv = to_i915(dev);
14305 struct drm_crtc_state *old_crtc_state;
14306 struct drm_crtc *crtc;
14307 struct intel_crtc_state *intel_cstate;
14308 struct drm_plane *plane;
14309 struct drm_plane_state *plane_state;
14310 bool hw_check = intel_state->modeset;
14311 unsigned long put_domains[I915_MAX_PIPES] = {};
14312 unsigned crtc_vblank_mask = 0;
14313 int i, ret;
14314
14315 for_each_plane_in_state(state, plane, plane_state, i) {
14316 struct intel_plane_state *intel_plane_state =
14317 to_intel_plane_state(plane_state);
14318
14319 if (!intel_plane_state->wait_req)
14320 continue;
14321
14322 ret = i915_wait_request(intel_plane_state->wait_req,
14323 0, NULL, NULL);
14324 /* EIO should be eaten, and we can't get interrupted in the
14325 * worker, and blocking commits have waited already. */
14326 WARN_ON(ret);
14327 }
14328
14329 drm_atomic_helper_wait_for_dependencies(state);
14330
14331 if (intel_state->modeset) {
14332 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14333 sizeof(intel_state->min_pixclk));
14334 dev_priv->active_crtcs = intel_state->active_crtcs;
14335 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14336
14337 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14338 }
14339
14340 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14342
14343 if (needs_modeset(crtc->state) ||
14344 to_intel_crtc_state(crtc->state)->update_pipe) {
14345 hw_check = true;
14346
14347 put_domains[to_intel_crtc(crtc)->pipe] =
14348 modeset_get_crtc_power_domains(crtc,
14349 to_intel_crtc_state(crtc->state));
14350 }
14351
14352 if (!needs_modeset(crtc->state))
14353 continue;
14354
14355 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14356
14357 if (old_crtc_state->active) {
14358 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14359 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14360 intel_crtc->active = false;
14361 intel_fbc_disable(intel_crtc);
14362 intel_disable_shared_dpll(intel_crtc);
14363
14364 /*
14365 * Underruns don't always raise
14366 * interrupts, so check manually.
14367 */
14368 intel_check_cpu_fifo_underruns(dev_priv);
14369 intel_check_pch_fifo_underruns(dev_priv);
14370
14371 if (!crtc->state->active)
14372 intel_update_watermarks(crtc);
14373 }
14374 }
14375
14376 /* Only after disabling all output pipelines that will be changed can we
14377 * update the the output configuration. */
14378 intel_modeset_update_crtc_state(state);
14379
14380 if (intel_state->modeset) {
14381 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14382
14383 if (dev_priv->display.modeset_commit_cdclk &&
14384 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14385 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14386 dev_priv->display.modeset_commit_cdclk(state);
14387
14388 /*
14389 * SKL workaround: bspec recommends we disable the SAGV when we
14390 * have more then one pipe enabled
14391 */
14392 if (!intel_can_enable_sagv(state))
14393 intel_disable_sagv(dev_priv);
14394
14395 intel_modeset_verify_disabled(dev);
14396 }
14397
14398 /* Complete the events for pipes that have now been disabled */
14399 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14400 bool modeset = needs_modeset(crtc->state);
14401
14402 /* Complete events for now disable pipes here. */
14403 if (modeset && !crtc->state->active && crtc->state->event) {
14404 spin_lock_irq(&dev->event_lock);
14405 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14406 spin_unlock_irq(&dev->event_lock);
14407
14408 crtc->state->event = NULL;
14409 }
14410 }
14411
14412 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14413 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14414
14415 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14416 * already, but still need the state for the delayed optimization. To
14417 * fix this:
14418 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14419 * - schedule that vblank worker _before_ calling hw_done
14420 * - at the start of commit_tail, cancel it _synchrously
14421 * - switch over to the vblank wait helper in the core after that since
14422 * we don't need out special handling any more.
14423 */
14424 if (!state->legacy_cursor_update)
14425 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14426
14427 /*
14428 * Now that the vblank has passed, we can go ahead and program the
14429 * optimal watermarks on platforms that need two-step watermark
14430 * programming.
14431 *
14432 * TODO: Move this (and other cleanup) to an async worker eventually.
14433 */
14434 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14435 intel_cstate = to_intel_crtc_state(crtc->state);
14436
14437 if (dev_priv->display.optimize_watermarks)
14438 dev_priv->display.optimize_watermarks(intel_cstate);
14439 }
14440
14441 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14442 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14443
14444 if (put_domains[i])
14445 modeset_put_power_domains(dev_priv, put_domains[i]);
14446
14447 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14448 }
14449
14450 if (intel_state->modeset && intel_can_enable_sagv(state))
14451 intel_enable_sagv(dev_priv);
14452
14453 drm_atomic_helper_commit_hw_done(state);
14454
14455 if (intel_state->modeset)
14456 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14457
14458 mutex_lock(&dev->struct_mutex);
14459 drm_atomic_helper_cleanup_planes(dev, state);
14460 mutex_unlock(&dev->struct_mutex);
14461
14462 drm_atomic_helper_commit_cleanup_done(state);
14463
14464 drm_atomic_state_free(state);
14465
14466 /* As one of the primary mmio accessors, KMS has a high likelihood
14467 * of triggering bugs in unclaimed access. After we finish
14468 * modesetting, see if an error has been flagged, and if so
14469 * enable debugging for the next modeset - and hope we catch
14470 * the culprit.
14471 *
14472 * XXX note that we assume display power is on at this point.
14473 * This might hold true now but we need to add pm helper to check
14474 * unclaimed only when the hardware is on, as atomic commits
14475 * can happen also when the device is completely off.
14476 */
14477 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14478 }
14479
14480 static void intel_atomic_commit_work(struct work_struct *work)
14481 {
14482 struct drm_atomic_state *state = container_of(work,
14483 struct drm_atomic_state,
14484 commit_work);
14485 intel_atomic_commit_tail(state);
14486 }
14487
14488 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14489 {
14490 struct drm_plane_state *old_plane_state;
14491 struct drm_plane *plane;
14492 int i;
14493
14494 for_each_plane_in_state(state, plane, old_plane_state, i)
14495 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14496 intel_fb_obj(plane->state->fb),
14497 to_intel_plane(plane)->frontbuffer_bit);
14498 }
14499
14500 /**
14501 * intel_atomic_commit - commit validated state object
14502 * @dev: DRM device
14503 * @state: the top-level driver state object
14504 * @nonblock: nonblocking commit
14505 *
14506 * This function commits a top-level state object that has been validated
14507 * with drm_atomic_helper_check().
14508 *
14509 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14510 * nonblocking commits are only safe for pure plane updates. Everything else
14511 * should work though.
14512 *
14513 * RETURNS
14514 * Zero for success or -errno.
14515 */
14516 static int intel_atomic_commit(struct drm_device *dev,
14517 struct drm_atomic_state *state,
14518 bool nonblock)
14519 {
14520 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14521 struct drm_i915_private *dev_priv = to_i915(dev);
14522 int ret = 0;
14523
14524 if (intel_state->modeset && nonblock) {
14525 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14526 return -EINVAL;
14527 }
14528
14529 ret = drm_atomic_helper_setup_commit(state, nonblock);
14530 if (ret)
14531 return ret;
14532
14533 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14534
14535 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14536 if (ret) {
14537 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14538 return ret;
14539 }
14540
14541 drm_atomic_helper_swap_state(state, true);
14542 dev_priv->wm.distrust_bios_wm = false;
14543 dev_priv->wm.skl_results = intel_state->wm_results;
14544 intel_shared_dpll_commit(state);
14545 intel_atomic_track_fbs(state);
14546
14547 if (nonblock)
14548 queue_work(system_unbound_wq, &state->commit_work);
14549 else
14550 intel_atomic_commit_tail(state);
14551
14552 return 0;
14553 }
14554
14555 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14556 {
14557 struct drm_device *dev = crtc->dev;
14558 struct drm_atomic_state *state;
14559 struct drm_crtc_state *crtc_state;
14560 int ret;
14561
14562 state = drm_atomic_state_alloc(dev);
14563 if (!state) {
14564 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14565 crtc->base.id, crtc->name);
14566 return;
14567 }
14568
14569 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14570
14571 retry:
14572 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14573 ret = PTR_ERR_OR_ZERO(crtc_state);
14574 if (!ret) {
14575 if (!crtc_state->active)
14576 goto out;
14577
14578 crtc_state->mode_changed = true;
14579 ret = drm_atomic_commit(state);
14580 }
14581
14582 if (ret == -EDEADLK) {
14583 drm_atomic_state_clear(state);
14584 drm_modeset_backoff(state->acquire_ctx);
14585 goto retry;
14586 }
14587
14588 if (ret)
14589 out:
14590 drm_atomic_state_free(state);
14591 }
14592
14593 /*
14594 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14595 * drm_atomic_helper_legacy_gamma_set() directly.
14596 */
14597 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14598 u16 *red, u16 *green, u16 *blue,
14599 uint32_t size)
14600 {
14601 struct drm_device *dev = crtc->dev;
14602 struct drm_mode_config *config = &dev->mode_config;
14603 struct drm_crtc_state *state;
14604 int ret;
14605
14606 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14607 if (ret)
14608 return ret;
14609
14610 /*
14611 * Make sure we update the legacy properties so this works when
14612 * atomic is not enabled.
14613 */
14614
14615 state = crtc->state;
14616
14617 drm_object_property_set_value(&crtc->base,
14618 config->degamma_lut_property,
14619 (state->degamma_lut) ?
14620 state->degamma_lut->base.id : 0);
14621
14622 drm_object_property_set_value(&crtc->base,
14623 config->ctm_property,
14624 (state->ctm) ?
14625 state->ctm->base.id : 0);
14626
14627 drm_object_property_set_value(&crtc->base,
14628 config->gamma_lut_property,
14629 (state->gamma_lut) ?
14630 state->gamma_lut->base.id : 0);
14631
14632 return 0;
14633 }
14634
14635 static const struct drm_crtc_funcs intel_crtc_funcs = {
14636 .gamma_set = intel_atomic_legacy_gamma_set,
14637 .set_config = drm_atomic_helper_set_config,
14638 .set_property = drm_atomic_helper_crtc_set_property,
14639 .destroy = intel_crtc_destroy,
14640 .page_flip = intel_crtc_page_flip,
14641 .atomic_duplicate_state = intel_crtc_duplicate_state,
14642 .atomic_destroy_state = intel_crtc_destroy_state,
14643 };
14644
14645 /**
14646 * intel_prepare_plane_fb - Prepare fb for usage on plane
14647 * @plane: drm plane to prepare for
14648 * @fb: framebuffer to prepare for presentation
14649 *
14650 * Prepares a framebuffer for usage on a display plane. Generally this
14651 * involves pinning the underlying object and updating the frontbuffer tracking
14652 * bits. Some older platforms need special physical address handling for
14653 * cursor planes.
14654 *
14655 * Must be called with struct_mutex held.
14656 *
14657 * Returns 0 on success, negative error code on failure.
14658 */
14659 int
14660 intel_prepare_plane_fb(struct drm_plane *plane,
14661 struct drm_plane_state *new_state)
14662 {
14663 struct drm_device *dev = plane->dev;
14664 struct drm_i915_private *dev_priv = to_i915(dev);
14665 struct drm_framebuffer *fb = new_state->fb;
14666 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14667 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14668 struct reservation_object *resv;
14669 int ret = 0;
14670
14671 if (!obj && !old_obj)
14672 return 0;
14673
14674 if (old_obj) {
14675 struct drm_crtc_state *crtc_state =
14676 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14677
14678 /* Big Hammer, we also need to ensure that any pending
14679 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14680 * current scanout is retired before unpinning the old
14681 * framebuffer. Note that we rely on userspace rendering
14682 * into the buffer attached to the pipe they are waiting
14683 * on. If not, userspace generates a GPU hang with IPEHR
14684 * point to the MI_WAIT_FOR_EVENT.
14685 *
14686 * This should only fail upon a hung GPU, in which case we
14687 * can safely continue.
14688 */
14689 if (needs_modeset(crtc_state))
14690 ret = i915_gem_object_wait_rendering(old_obj, true);
14691 if (ret) {
14692 /* GPU hangs should have been swallowed by the wait */
14693 WARN_ON(ret == -EIO);
14694 return ret;
14695 }
14696 }
14697
14698 if (!obj)
14699 return 0;
14700
14701 /* For framebuffer backed by dmabuf, wait for fence */
14702 resv = i915_gem_object_get_dmabuf_resv(obj);
14703 if (resv) {
14704 long lret;
14705
14706 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14707 MAX_SCHEDULE_TIMEOUT);
14708 if (lret == -ERESTARTSYS)
14709 return lret;
14710
14711 WARN(lret < 0, "waiting returns %li\n", lret);
14712 }
14713
14714 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14715 INTEL_INFO(dev)->cursor_needs_physical) {
14716 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14717 ret = i915_gem_object_attach_phys(obj, align);
14718 if (ret)
14719 DRM_DEBUG_KMS("failed to attach phys object\n");
14720 } else {
14721 struct i915_vma *vma;
14722
14723 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14724 if (IS_ERR(vma))
14725 ret = PTR_ERR(vma);
14726 }
14727
14728 if (ret == 0) {
14729 to_intel_plane_state(new_state)->wait_req =
14730 i915_gem_active_get(&obj->last_write,
14731 &obj->base.dev->struct_mutex);
14732 }
14733
14734 return ret;
14735 }
14736
14737 /**
14738 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14739 * @plane: drm plane to clean up for
14740 * @fb: old framebuffer that was on plane
14741 *
14742 * Cleans up a framebuffer that has just been removed from a plane.
14743 *
14744 * Must be called with struct_mutex held.
14745 */
14746 void
14747 intel_cleanup_plane_fb(struct drm_plane *plane,
14748 struct drm_plane_state *old_state)
14749 {
14750 struct drm_device *dev = plane->dev;
14751 struct intel_plane_state *old_intel_state;
14752 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14753 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14754 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14755
14756 old_intel_state = to_intel_plane_state(old_state);
14757
14758 if (!obj && !old_obj)
14759 return;
14760
14761 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14762 !INTEL_INFO(dev)->cursor_needs_physical))
14763 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14764
14765 i915_gem_request_assign(&intel_state->wait_req, NULL);
14766 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14767 }
14768
14769 int
14770 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14771 {
14772 int max_scale;
14773 int crtc_clock, cdclk;
14774
14775 if (!intel_crtc || !crtc_state->base.enable)
14776 return DRM_PLANE_HELPER_NO_SCALING;
14777
14778 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14779 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14780
14781 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14782 return DRM_PLANE_HELPER_NO_SCALING;
14783
14784 /*
14785 * skl max scale is lower of:
14786 * close to 3 but not 3, -1 is for that purpose
14787 * or
14788 * cdclk/crtc_clock
14789 */
14790 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14791
14792 return max_scale;
14793 }
14794
14795 static int
14796 intel_check_primary_plane(struct drm_plane *plane,
14797 struct intel_crtc_state *crtc_state,
14798 struct intel_plane_state *state)
14799 {
14800 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14801 struct drm_crtc *crtc = state->base.crtc;
14802 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14803 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14804 bool can_position = false;
14805 int ret;
14806
14807 if (INTEL_GEN(dev_priv) >= 9) {
14808 /* use scaler when colorkey is not required */
14809 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14810 min_scale = 1;
14811 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14812 }
14813 can_position = true;
14814 }
14815
14816 ret = drm_plane_helper_check_state(&state->base,
14817 &state->clip,
14818 min_scale, max_scale,
14819 can_position, true);
14820 if (ret)
14821 return ret;
14822
14823 if (!state->base.fb)
14824 return 0;
14825
14826 if (INTEL_GEN(dev_priv) >= 9) {
14827 ret = skl_check_plane_surface(state);
14828 if (ret)
14829 return ret;
14830 }
14831
14832 return 0;
14833 }
14834
14835 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14836 struct drm_crtc_state *old_crtc_state)
14837 {
14838 struct drm_device *dev = crtc->dev;
14839 struct drm_i915_private *dev_priv = to_i915(dev);
14840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14841 struct intel_crtc_state *old_intel_state =
14842 to_intel_crtc_state(old_crtc_state);
14843 bool modeset = needs_modeset(crtc->state);
14844 enum pipe pipe = intel_crtc->pipe;
14845
14846 /* Perform vblank evasion around commit operation */
14847 intel_pipe_update_start(intel_crtc);
14848
14849 if (modeset)
14850 return;
14851
14852 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14853 intel_color_set_csc(crtc->state);
14854 intel_color_load_luts(crtc->state);
14855 }
14856
14857 if (to_intel_crtc_state(crtc->state)->update_pipe)
14858 intel_update_pipe_config(intel_crtc, old_intel_state);
14859 else if (INTEL_GEN(dev_priv) >= 9) {
14860 skl_detach_scalers(intel_crtc);
14861
14862 I915_WRITE(PIPE_WM_LINETIME(pipe),
14863 dev_priv->wm.skl_hw.wm_linetime[pipe]);
14864 }
14865 }
14866
14867 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14868 struct drm_crtc_state *old_crtc_state)
14869 {
14870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14871
14872 intel_pipe_update_end(intel_crtc, NULL);
14873 }
14874
14875 /**
14876 * intel_plane_destroy - destroy a plane
14877 * @plane: plane to destroy
14878 *
14879 * Common destruction function for all types of planes (primary, cursor,
14880 * sprite).
14881 */
14882 void intel_plane_destroy(struct drm_plane *plane)
14883 {
14884 if (!plane)
14885 return;
14886
14887 drm_plane_cleanup(plane);
14888 kfree(to_intel_plane(plane));
14889 }
14890
14891 const struct drm_plane_funcs intel_plane_funcs = {
14892 .update_plane = drm_atomic_helper_update_plane,
14893 .disable_plane = drm_atomic_helper_disable_plane,
14894 .destroy = intel_plane_destroy,
14895 .set_property = drm_atomic_helper_plane_set_property,
14896 .atomic_get_property = intel_plane_atomic_get_property,
14897 .atomic_set_property = intel_plane_atomic_set_property,
14898 .atomic_duplicate_state = intel_plane_duplicate_state,
14899 .atomic_destroy_state = intel_plane_destroy_state,
14900
14901 };
14902
14903 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14904 int pipe)
14905 {
14906 struct drm_i915_private *dev_priv = to_i915(dev);
14907 struct intel_plane *primary = NULL;
14908 struct intel_plane_state *state = NULL;
14909 const uint32_t *intel_primary_formats;
14910 unsigned int num_formats;
14911 int ret;
14912
14913 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14914 if (!primary)
14915 goto fail;
14916
14917 state = intel_create_plane_state(&primary->base);
14918 if (!state)
14919 goto fail;
14920 primary->base.state = &state->base;
14921
14922 primary->can_scale = false;
14923 primary->max_downscale = 1;
14924 if (INTEL_INFO(dev)->gen >= 9) {
14925 primary->can_scale = true;
14926 state->scaler_id = -1;
14927 }
14928 primary->pipe = pipe;
14929 primary->plane = pipe;
14930 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14931 primary->check_plane = intel_check_primary_plane;
14932 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14933 primary->plane = !pipe;
14934
14935 if (INTEL_INFO(dev)->gen >= 9) {
14936 intel_primary_formats = skl_primary_formats;
14937 num_formats = ARRAY_SIZE(skl_primary_formats);
14938
14939 primary->update_plane = skylake_update_primary_plane;
14940 primary->disable_plane = skylake_disable_primary_plane;
14941 } else if (HAS_PCH_SPLIT(dev_priv)) {
14942 intel_primary_formats = i965_primary_formats;
14943 num_formats = ARRAY_SIZE(i965_primary_formats);
14944
14945 primary->update_plane = ironlake_update_primary_plane;
14946 primary->disable_plane = i9xx_disable_primary_plane;
14947 } else if (INTEL_INFO(dev)->gen >= 4) {
14948 intel_primary_formats = i965_primary_formats;
14949 num_formats = ARRAY_SIZE(i965_primary_formats);
14950
14951 primary->update_plane = i9xx_update_primary_plane;
14952 primary->disable_plane = i9xx_disable_primary_plane;
14953 } else {
14954 intel_primary_formats = i8xx_primary_formats;
14955 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14956
14957 primary->update_plane = i9xx_update_primary_plane;
14958 primary->disable_plane = i9xx_disable_primary_plane;
14959 }
14960
14961 if (INTEL_INFO(dev)->gen >= 9)
14962 ret = drm_universal_plane_init(dev, &primary->base, 0,
14963 &intel_plane_funcs,
14964 intel_primary_formats, num_formats,
14965 DRM_PLANE_TYPE_PRIMARY,
14966 "plane 1%c", pipe_name(pipe));
14967 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14968 ret = drm_universal_plane_init(dev, &primary->base, 0,
14969 &intel_plane_funcs,
14970 intel_primary_formats, num_formats,
14971 DRM_PLANE_TYPE_PRIMARY,
14972 "primary %c", pipe_name(pipe));
14973 else
14974 ret = drm_universal_plane_init(dev, &primary->base, 0,
14975 &intel_plane_funcs,
14976 intel_primary_formats, num_formats,
14977 DRM_PLANE_TYPE_PRIMARY,
14978 "plane %c", plane_name(primary->plane));
14979 if (ret)
14980 goto fail;
14981
14982 if (INTEL_INFO(dev)->gen >= 4)
14983 intel_create_rotation_property(dev, primary);
14984
14985 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14986
14987 return &primary->base;
14988
14989 fail:
14990 kfree(state);
14991 kfree(primary);
14992
14993 return NULL;
14994 }
14995
14996 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14997 {
14998 if (!dev->mode_config.rotation_property) {
14999 unsigned long flags = DRM_ROTATE_0 |
15000 DRM_ROTATE_180;
15001
15002 if (INTEL_INFO(dev)->gen >= 9)
15003 flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
15004
15005 dev->mode_config.rotation_property =
15006 drm_mode_create_rotation_property(dev, flags);
15007 }
15008 if (dev->mode_config.rotation_property)
15009 drm_object_attach_property(&plane->base.base,
15010 dev->mode_config.rotation_property,
15011 plane->base.state->rotation);
15012 }
15013
15014 static int
15015 intel_check_cursor_plane(struct drm_plane *plane,
15016 struct intel_crtc_state *crtc_state,
15017 struct intel_plane_state *state)
15018 {
15019 struct drm_framebuffer *fb = state->base.fb;
15020 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15021 enum pipe pipe = to_intel_plane(plane)->pipe;
15022 unsigned stride;
15023 int ret;
15024
15025 ret = drm_plane_helper_check_state(&state->base,
15026 &state->clip,
15027 DRM_PLANE_HELPER_NO_SCALING,
15028 DRM_PLANE_HELPER_NO_SCALING,
15029 true, true);
15030 if (ret)
15031 return ret;
15032
15033 /* if we want to turn off the cursor ignore width and height */
15034 if (!obj)
15035 return 0;
15036
15037 /* Check for which cursor types we support */
15038 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15039 state->base.crtc_h)) {
15040 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15041 state->base.crtc_w, state->base.crtc_h);
15042 return -EINVAL;
15043 }
15044
15045 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15046 if (obj->base.size < stride * state->base.crtc_h) {
15047 DRM_DEBUG_KMS("buffer is too small\n");
15048 return -ENOMEM;
15049 }
15050
15051 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15052 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15053 return -EINVAL;
15054 }
15055
15056 /*
15057 * There's something wrong with the cursor on CHV pipe C.
15058 * If it straddles the left edge of the screen then
15059 * moving it away from the edge or disabling it often
15060 * results in a pipe underrun, and often that can lead to
15061 * dead pipe (constant underrun reported, and it scans
15062 * out just a solid color). To recover from that, the
15063 * display power well must be turned off and on again.
15064 * Refuse the put the cursor into that compromised position.
15065 */
15066 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15067 state->base.visible && state->base.crtc_x < 0) {
15068 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15069 return -EINVAL;
15070 }
15071
15072 return 0;
15073 }
15074
15075 static void
15076 intel_disable_cursor_plane(struct drm_plane *plane,
15077 struct drm_crtc *crtc)
15078 {
15079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15080
15081 intel_crtc->cursor_addr = 0;
15082 intel_crtc_update_cursor(crtc, NULL);
15083 }
15084
15085 static void
15086 intel_update_cursor_plane(struct drm_plane *plane,
15087 const struct intel_crtc_state *crtc_state,
15088 const struct intel_plane_state *state)
15089 {
15090 struct drm_crtc *crtc = crtc_state->base.crtc;
15091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15092 struct drm_device *dev = plane->dev;
15093 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15094 uint32_t addr;
15095
15096 if (!obj)
15097 addr = 0;
15098 else if (!INTEL_INFO(dev)->cursor_needs_physical)
15099 addr = i915_gem_object_ggtt_offset(obj, NULL);
15100 else
15101 addr = obj->phys_handle->busaddr;
15102
15103 intel_crtc->cursor_addr = addr;
15104 intel_crtc_update_cursor(crtc, state);
15105 }
15106
15107 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15108 int pipe)
15109 {
15110 struct intel_plane *cursor = NULL;
15111 struct intel_plane_state *state = NULL;
15112 int ret;
15113
15114 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15115 if (!cursor)
15116 goto fail;
15117
15118 state = intel_create_plane_state(&cursor->base);
15119 if (!state)
15120 goto fail;
15121 cursor->base.state = &state->base;
15122
15123 cursor->can_scale = false;
15124 cursor->max_downscale = 1;
15125 cursor->pipe = pipe;
15126 cursor->plane = pipe;
15127 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15128 cursor->check_plane = intel_check_cursor_plane;
15129 cursor->update_plane = intel_update_cursor_plane;
15130 cursor->disable_plane = intel_disable_cursor_plane;
15131
15132 ret = drm_universal_plane_init(dev, &cursor->base, 0,
15133 &intel_plane_funcs,
15134 intel_cursor_formats,
15135 ARRAY_SIZE(intel_cursor_formats),
15136 DRM_PLANE_TYPE_CURSOR,
15137 "cursor %c", pipe_name(pipe));
15138 if (ret)
15139 goto fail;
15140
15141 if (INTEL_INFO(dev)->gen >= 4) {
15142 if (!dev->mode_config.rotation_property)
15143 dev->mode_config.rotation_property =
15144 drm_mode_create_rotation_property(dev,
15145 DRM_ROTATE_0 |
15146 DRM_ROTATE_180);
15147 if (dev->mode_config.rotation_property)
15148 drm_object_attach_property(&cursor->base.base,
15149 dev->mode_config.rotation_property,
15150 state->base.rotation);
15151 }
15152
15153 if (INTEL_INFO(dev)->gen >=9)
15154 state->scaler_id = -1;
15155
15156 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15157
15158 return &cursor->base;
15159
15160 fail:
15161 kfree(state);
15162 kfree(cursor);
15163
15164 return NULL;
15165 }
15166
15167 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15168 struct intel_crtc_state *crtc_state)
15169 {
15170 int i;
15171 struct intel_scaler *intel_scaler;
15172 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15173
15174 for (i = 0; i < intel_crtc->num_scalers; i++) {
15175 intel_scaler = &scaler_state->scalers[i];
15176 intel_scaler->in_use = 0;
15177 intel_scaler->mode = PS_SCALER_MODE_DYN;
15178 }
15179
15180 scaler_state->scaler_id = -1;
15181 }
15182
15183 static void intel_crtc_init(struct drm_device *dev, int pipe)
15184 {
15185 struct drm_i915_private *dev_priv = to_i915(dev);
15186 struct intel_crtc *intel_crtc;
15187 struct intel_crtc_state *crtc_state = NULL;
15188 struct drm_plane *primary = NULL;
15189 struct drm_plane *cursor = NULL;
15190 int ret;
15191
15192 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15193 if (intel_crtc == NULL)
15194 return;
15195
15196 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15197 if (!crtc_state)
15198 goto fail;
15199 intel_crtc->config = crtc_state;
15200 intel_crtc->base.state = &crtc_state->base;
15201 crtc_state->base.crtc = &intel_crtc->base;
15202
15203 /* initialize shared scalers */
15204 if (INTEL_INFO(dev)->gen >= 9) {
15205 if (pipe == PIPE_C)
15206 intel_crtc->num_scalers = 1;
15207 else
15208 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15209
15210 skl_init_scalers(dev, intel_crtc, crtc_state);
15211 }
15212
15213 primary = intel_primary_plane_create(dev, pipe);
15214 if (!primary)
15215 goto fail;
15216
15217 cursor = intel_cursor_plane_create(dev, pipe);
15218 if (!cursor)
15219 goto fail;
15220
15221 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15222 cursor, &intel_crtc_funcs,
15223 "pipe %c", pipe_name(pipe));
15224 if (ret)
15225 goto fail;
15226
15227 /*
15228 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15229 * is hooked to pipe B. Hence we want plane A feeding pipe B.
15230 */
15231 intel_crtc->pipe = pipe;
15232 intel_crtc->plane = pipe;
15233 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15234 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15235 intel_crtc->plane = !pipe;
15236 }
15237
15238 intel_crtc->cursor_base = ~0;
15239 intel_crtc->cursor_cntl = ~0;
15240 intel_crtc->cursor_size = ~0;
15241
15242 intel_crtc->wm.cxsr_allowed = true;
15243
15244 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15245 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15246 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15247 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15248
15249 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15250
15251 intel_color_init(&intel_crtc->base);
15252
15253 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15254 return;
15255
15256 fail:
15257 intel_plane_destroy(primary);
15258 intel_plane_destroy(cursor);
15259 kfree(crtc_state);
15260 kfree(intel_crtc);
15261 }
15262
15263 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15264 {
15265 struct drm_encoder *encoder = connector->base.encoder;
15266 struct drm_device *dev = connector->base.dev;
15267
15268 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15269
15270 if (!encoder || WARN_ON(!encoder->crtc))
15271 return INVALID_PIPE;
15272
15273 return to_intel_crtc(encoder->crtc)->pipe;
15274 }
15275
15276 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15277 struct drm_file *file)
15278 {
15279 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15280 struct drm_crtc *drmmode_crtc;
15281 struct intel_crtc *crtc;
15282
15283 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15284 if (!drmmode_crtc)
15285 return -ENOENT;
15286
15287 crtc = to_intel_crtc(drmmode_crtc);
15288 pipe_from_crtc_id->pipe = crtc->pipe;
15289
15290 return 0;
15291 }
15292
15293 static int intel_encoder_clones(struct intel_encoder *encoder)
15294 {
15295 struct drm_device *dev = encoder->base.dev;
15296 struct intel_encoder *source_encoder;
15297 int index_mask = 0;
15298 int entry = 0;
15299
15300 for_each_intel_encoder(dev, source_encoder) {
15301 if (encoders_cloneable(encoder, source_encoder))
15302 index_mask |= (1 << entry);
15303
15304 entry++;
15305 }
15306
15307 return index_mask;
15308 }
15309
15310 static bool has_edp_a(struct drm_device *dev)
15311 {
15312 struct drm_i915_private *dev_priv = to_i915(dev);
15313
15314 if (!IS_MOBILE(dev))
15315 return false;
15316
15317 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15318 return false;
15319
15320 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15321 return false;
15322
15323 return true;
15324 }
15325
15326 static bool intel_crt_present(struct drm_device *dev)
15327 {
15328 struct drm_i915_private *dev_priv = to_i915(dev);
15329
15330 if (INTEL_INFO(dev)->gen >= 9)
15331 return false;
15332
15333 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15334 return false;
15335
15336 if (IS_CHERRYVIEW(dev))
15337 return false;
15338
15339 if (HAS_PCH_LPT_H(dev_priv) &&
15340 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15341 return false;
15342
15343 /* DDI E can't be used if DDI A requires 4 lanes */
15344 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15345 return false;
15346
15347 if (!dev_priv->vbt.int_crt_support)
15348 return false;
15349
15350 return true;
15351 }
15352
15353 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15354 {
15355 int pps_num;
15356 int pps_idx;
15357
15358 if (HAS_DDI(dev_priv))
15359 return;
15360 /*
15361 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15362 * everywhere where registers can be write protected.
15363 */
15364 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15365 pps_num = 2;
15366 else
15367 pps_num = 1;
15368
15369 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15370 u32 val = I915_READ(PP_CONTROL(pps_idx));
15371
15372 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15373 I915_WRITE(PP_CONTROL(pps_idx), val);
15374 }
15375 }
15376
15377 static void intel_pps_init(struct drm_i915_private *dev_priv)
15378 {
15379 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15380 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15381 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15382 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15383 else
15384 dev_priv->pps_mmio_base = PPS_BASE;
15385
15386 intel_pps_unlock_regs_wa(dev_priv);
15387 }
15388
15389 static void intel_setup_outputs(struct drm_device *dev)
15390 {
15391 struct drm_i915_private *dev_priv = to_i915(dev);
15392 struct intel_encoder *encoder;
15393 bool dpd_is_edp = false;
15394
15395 intel_pps_init(dev_priv);
15396
15397 /*
15398 * intel_edp_init_connector() depends on this completing first, to
15399 * prevent the registeration of both eDP and LVDS and the incorrect
15400 * sharing of the PPS.
15401 */
15402 intel_lvds_init(dev);
15403
15404 if (intel_crt_present(dev))
15405 intel_crt_init(dev);
15406
15407 if (IS_BROXTON(dev_priv)) {
15408 /*
15409 * FIXME: Broxton doesn't support port detection via the
15410 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15411 * detect the ports.
15412 */
15413 intel_ddi_init(dev, PORT_A);
15414 intel_ddi_init(dev, PORT_B);
15415 intel_ddi_init(dev, PORT_C);
15416
15417 intel_dsi_init(dev);
15418 } else if (HAS_DDI(dev_priv)) {
15419 int found;
15420
15421 /*
15422 * Haswell uses DDI functions to detect digital outputs.
15423 * On SKL pre-D0 the strap isn't connected, so we assume
15424 * it's there.
15425 */
15426 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15427 /* WaIgnoreDDIAStrap: skl */
15428 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15429 intel_ddi_init(dev, PORT_A);
15430
15431 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15432 * register */
15433 found = I915_READ(SFUSE_STRAP);
15434
15435 if (found & SFUSE_STRAP_DDIB_DETECTED)
15436 intel_ddi_init(dev, PORT_B);
15437 if (found & SFUSE_STRAP_DDIC_DETECTED)
15438 intel_ddi_init(dev, PORT_C);
15439 if (found & SFUSE_STRAP_DDID_DETECTED)
15440 intel_ddi_init(dev, PORT_D);
15441 /*
15442 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15443 */
15444 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15445 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15446 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15447 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15448 intel_ddi_init(dev, PORT_E);
15449
15450 } else if (HAS_PCH_SPLIT(dev_priv)) {
15451 int found;
15452 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15453
15454 if (has_edp_a(dev))
15455 intel_dp_init(dev, DP_A, PORT_A);
15456
15457 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15458 /* PCH SDVOB multiplex with HDMIB */
15459 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15460 if (!found)
15461 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15462 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15463 intel_dp_init(dev, PCH_DP_B, PORT_B);
15464 }
15465
15466 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15467 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15468
15469 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15470 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15471
15472 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15473 intel_dp_init(dev, PCH_DP_C, PORT_C);
15474
15475 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15476 intel_dp_init(dev, PCH_DP_D, PORT_D);
15477 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15478 bool has_edp, has_port;
15479
15480 /*
15481 * The DP_DETECTED bit is the latched state of the DDC
15482 * SDA pin at boot. However since eDP doesn't require DDC
15483 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15484 * eDP ports may have been muxed to an alternate function.
15485 * Thus we can't rely on the DP_DETECTED bit alone to detect
15486 * eDP ports. Consult the VBT as well as DP_DETECTED to
15487 * detect eDP ports.
15488 *
15489 * Sadly the straps seem to be missing sometimes even for HDMI
15490 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15491 * and VBT for the presence of the port. Additionally we can't
15492 * trust the port type the VBT declares as we've seen at least
15493 * HDMI ports that the VBT claim are DP or eDP.
15494 */
15495 has_edp = intel_dp_is_edp(dev, PORT_B);
15496 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15497 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15498 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15499 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15500 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15501
15502 has_edp = intel_dp_is_edp(dev, PORT_C);
15503 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15504 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15505 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15506 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15507 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15508
15509 if (IS_CHERRYVIEW(dev)) {
15510 /*
15511 * eDP not supported on port D,
15512 * so no need to worry about it
15513 */
15514 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15515 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15516 intel_dp_init(dev, CHV_DP_D, PORT_D);
15517 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15518 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15519 }
15520
15521 intel_dsi_init(dev);
15522 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15523 bool found = false;
15524
15525 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15526 DRM_DEBUG_KMS("probing SDVOB\n");
15527 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15528 if (!found && IS_G4X(dev)) {
15529 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15530 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15531 }
15532
15533 if (!found && IS_G4X(dev))
15534 intel_dp_init(dev, DP_B, PORT_B);
15535 }
15536
15537 /* Before G4X SDVOC doesn't have its own detect register */
15538
15539 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15540 DRM_DEBUG_KMS("probing SDVOC\n");
15541 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15542 }
15543
15544 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15545
15546 if (IS_G4X(dev)) {
15547 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15548 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15549 }
15550 if (IS_G4X(dev))
15551 intel_dp_init(dev, DP_C, PORT_C);
15552 }
15553
15554 if (IS_G4X(dev) &&
15555 (I915_READ(DP_D) & DP_DETECTED))
15556 intel_dp_init(dev, DP_D, PORT_D);
15557 } else if (IS_GEN2(dev))
15558 intel_dvo_init(dev);
15559
15560 if (SUPPORTS_TV(dev))
15561 intel_tv_init(dev);
15562
15563 intel_psr_init(dev);
15564
15565 for_each_intel_encoder(dev, encoder) {
15566 encoder->base.possible_crtcs = encoder->crtc_mask;
15567 encoder->base.possible_clones =
15568 intel_encoder_clones(encoder);
15569 }
15570
15571 intel_init_pch_refclk(dev);
15572
15573 drm_helper_move_panel_connectors_to_head(dev);
15574 }
15575
15576 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15577 {
15578 struct drm_device *dev = fb->dev;
15579 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15580
15581 drm_framebuffer_cleanup(fb);
15582 mutex_lock(&dev->struct_mutex);
15583 WARN_ON(!intel_fb->obj->framebuffer_references--);
15584 i915_gem_object_put(intel_fb->obj);
15585 mutex_unlock(&dev->struct_mutex);
15586 kfree(intel_fb);
15587 }
15588
15589 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15590 struct drm_file *file,
15591 unsigned int *handle)
15592 {
15593 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15594 struct drm_i915_gem_object *obj = intel_fb->obj;
15595
15596 if (obj->userptr.mm) {
15597 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15598 return -EINVAL;
15599 }
15600
15601 return drm_gem_handle_create(file, &obj->base, handle);
15602 }
15603
15604 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15605 struct drm_file *file,
15606 unsigned flags, unsigned color,
15607 struct drm_clip_rect *clips,
15608 unsigned num_clips)
15609 {
15610 struct drm_device *dev = fb->dev;
15611 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15612 struct drm_i915_gem_object *obj = intel_fb->obj;
15613
15614 mutex_lock(&dev->struct_mutex);
15615 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15616 mutex_unlock(&dev->struct_mutex);
15617
15618 return 0;
15619 }
15620
15621 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15622 .destroy = intel_user_framebuffer_destroy,
15623 .create_handle = intel_user_framebuffer_create_handle,
15624 .dirty = intel_user_framebuffer_dirty,
15625 };
15626
15627 static
15628 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15629 uint32_t pixel_format)
15630 {
15631 u32 gen = INTEL_INFO(dev)->gen;
15632
15633 if (gen >= 9) {
15634 int cpp = drm_format_plane_cpp(pixel_format, 0);
15635
15636 /* "The stride in bytes must not exceed the of the size of 8K
15637 * pixels and 32K bytes."
15638 */
15639 return min(8192 * cpp, 32768);
15640 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15641 return 32*1024;
15642 } else if (gen >= 4) {
15643 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15644 return 16*1024;
15645 else
15646 return 32*1024;
15647 } else if (gen >= 3) {
15648 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15649 return 8*1024;
15650 else
15651 return 16*1024;
15652 } else {
15653 /* XXX DSPC is limited to 4k tiled */
15654 return 8*1024;
15655 }
15656 }
15657
15658 static int intel_framebuffer_init(struct drm_device *dev,
15659 struct intel_framebuffer *intel_fb,
15660 struct drm_mode_fb_cmd2 *mode_cmd,
15661 struct drm_i915_gem_object *obj)
15662 {
15663 struct drm_i915_private *dev_priv = to_i915(dev);
15664 unsigned int tiling = i915_gem_object_get_tiling(obj);
15665 int ret;
15666 u32 pitch_limit, stride_alignment;
15667 char *format_name;
15668
15669 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15670
15671 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15672 /*
15673 * If there's a fence, enforce that
15674 * the fb modifier and tiling mode match.
15675 */
15676 if (tiling != I915_TILING_NONE &&
15677 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15678 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15679 return -EINVAL;
15680 }
15681 } else {
15682 if (tiling == I915_TILING_X) {
15683 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15684 } else if (tiling == I915_TILING_Y) {
15685 DRM_DEBUG("No Y tiling for legacy addfb\n");
15686 return -EINVAL;
15687 }
15688 }
15689
15690 /* Passed in modifier sanity checking. */
15691 switch (mode_cmd->modifier[0]) {
15692 case I915_FORMAT_MOD_Y_TILED:
15693 case I915_FORMAT_MOD_Yf_TILED:
15694 if (INTEL_INFO(dev)->gen < 9) {
15695 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15696 mode_cmd->modifier[0]);
15697 return -EINVAL;
15698 }
15699 case DRM_FORMAT_MOD_NONE:
15700 case I915_FORMAT_MOD_X_TILED:
15701 break;
15702 default:
15703 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15704 mode_cmd->modifier[0]);
15705 return -EINVAL;
15706 }
15707
15708 /*
15709 * gen2/3 display engine uses the fence if present,
15710 * so the tiling mode must match the fb modifier exactly.
15711 */
15712 if (INTEL_INFO(dev_priv)->gen < 4 &&
15713 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15714 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15715 return -EINVAL;
15716 }
15717
15718 stride_alignment = intel_fb_stride_alignment(dev_priv,
15719 mode_cmd->modifier[0],
15720 mode_cmd->pixel_format);
15721 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15722 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15723 mode_cmd->pitches[0], stride_alignment);
15724 return -EINVAL;
15725 }
15726
15727 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15728 mode_cmd->pixel_format);
15729 if (mode_cmd->pitches[0] > pitch_limit) {
15730 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15731 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15732 "tiled" : "linear",
15733 mode_cmd->pitches[0], pitch_limit);
15734 return -EINVAL;
15735 }
15736
15737 /*
15738 * If there's a fence, enforce that
15739 * the fb pitch and fence stride match.
15740 */
15741 if (tiling != I915_TILING_NONE &&
15742 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15743 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15744 mode_cmd->pitches[0],
15745 i915_gem_object_get_stride(obj));
15746 return -EINVAL;
15747 }
15748
15749 /* Reject formats not supported by any plane early. */
15750 switch (mode_cmd->pixel_format) {
15751 case DRM_FORMAT_C8:
15752 case DRM_FORMAT_RGB565:
15753 case DRM_FORMAT_XRGB8888:
15754 case DRM_FORMAT_ARGB8888:
15755 break;
15756 case DRM_FORMAT_XRGB1555:
15757 if (INTEL_INFO(dev)->gen > 3) {
15758 format_name = drm_get_format_name(mode_cmd->pixel_format);
15759 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15760 kfree(format_name);
15761 return -EINVAL;
15762 }
15763 break;
15764 case DRM_FORMAT_ABGR8888:
15765 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15766 INTEL_INFO(dev)->gen < 9) {
15767 format_name = drm_get_format_name(mode_cmd->pixel_format);
15768 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15769 kfree(format_name);
15770 return -EINVAL;
15771 }
15772 break;
15773 case DRM_FORMAT_XBGR8888:
15774 case DRM_FORMAT_XRGB2101010:
15775 case DRM_FORMAT_XBGR2101010:
15776 if (INTEL_INFO(dev)->gen < 4) {
15777 format_name = drm_get_format_name(mode_cmd->pixel_format);
15778 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15779 kfree(format_name);
15780 return -EINVAL;
15781 }
15782 break;
15783 case DRM_FORMAT_ABGR2101010:
15784 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15785 format_name = drm_get_format_name(mode_cmd->pixel_format);
15786 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15787 kfree(format_name);
15788 return -EINVAL;
15789 }
15790 break;
15791 case DRM_FORMAT_YUYV:
15792 case DRM_FORMAT_UYVY:
15793 case DRM_FORMAT_YVYU:
15794 case DRM_FORMAT_VYUY:
15795 if (INTEL_INFO(dev)->gen < 5) {
15796 format_name = drm_get_format_name(mode_cmd->pixel_format);
15797 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15798 kfree(format_name);
15799 return -EINVAL;
15800 }
15801 break;
15802 default:
15803 format_name = drm_get_format_name(mode_cmd->pixel_format);
15804 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15805 kfree(format_name);
15806 return -EINVAL;
15807 }
15808
15809 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15810 if (mode_cmd->offsets[0] != 0)
15811 return -EINVAL;
15812
15813 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15814 intel_fb->obj = obj;
15815
15816 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15817 if (ret)
15818 return ret;
15819
15820 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15821 if (ret) {
15822 DRM_ERROR("framebuffer init failed %d\n", ret);
15823 return ret;
15824 }
15825
15826 intel_fb->obj->framebuffer_references++;
15827
15828 return 0;
15829 }
15830
15831 static struct drm_framebuffer *
15832 intel_user_framebuffer_create(struct drm_device *dev,
15833 struct drm_file *filp,
15834 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15835 {
15836 struct drm_framebuffer *fb;
15837 struct drm_i915_gem_object *obj;
15838 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15839
15840 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15841 if (!obj)
15842 return ERR_PTR(-ENOENT);
15843
15844 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15845 if (IS_ERR(fb))
15846 i915_gem_object_put_unlocked(obj);
15847
15848 return fb;
15849 }
15850
15851 static const struct drm_mode_config_funcs intel_mode_funcs = {
15852 .fb_create = intel_user_framebuffer_create,
15853 .output_poll_changed = intel_fbdev_output_poll_changed,
15854 .atomic_check = intel_atomic_check,
15855 .atomic_commit = intel_atomic_commit,
15856 .atomic_state_alloc = intel_atomic_state_alloc,
15857 .atomic_state_clear = intel_atomic_state_clear,
15858 };
15859
15860 /**
15861 * intel_init_display_hooks - initialize the display modesetting hooks
15862 * @dev_priv: device private
15863 */
15864 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15865 {
15866 if (INTEL_INFO(dev_priv)->gen >= 9) {
15867 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15868 dev_priv->display.get_initial_plane_config =
15869 skylake_get_initial_plane_config;
15870 dev_priv->display.crtc_compute_clock =
15871 haswell_crtc_compute_clock;
15872 dev_priv->display.crtc_enable = haswell_crtc_enable;
15873 dev_priv->display.crtc_disable = haswell_crtc_disable;
15874 } else if (HAS_DDI(dev_priv)) {
15875 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15876 dev_priv->display.get_initial_plane_config =
15877 ironlake_get_initial_plane_config;
15878 dev_priv->display.crtc_compute_clock =
15879 haswell_crtc_compute_clock;
15880 dev_priv->display.crtc_enable = haswell_crtc_enable;
15881 dev_priv->display.crtc_disable = haswell_crtc_disable;
15882 } else if (HAS_PCH_SPLIT(dev_priv)) {
15883 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15884 dev_priv->display.get_initial_plane_config =
15885 ironlake_get_initial_plane_config;
15886 dev_priv->display.crtc_compute_clock =
15887 ironlake_crtc_compute_clock;
15888 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15889 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15890 } else if (IS_CHERRYVIEW(dev_priv)) {
15891 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15892 dev_priv->display.get_initial_plane_config =
15893 i9xx_get_initial_plane_config;
15894 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15895 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15896 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15897 } else if (IS_VALLEYVIEW(dev_priv)) {
15898 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15899 dev_priv->display.get_initial_plane_config =
15900 i9xx_get_initial_plane_config;
15901 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15902 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15903 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15904 } else if (IS_G4X(dev_priv)) {
15905 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15906 dev_priv->display.get_initial_plane_config =
15907 i9xx_get_initial_plane_config;
15908 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15909 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15910 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15911 } else if (IS_PINEVIEW(dev_priv)) {
15912 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15913 dev_priv->display.get_initial_plane_config =
15914 i9xx_get_initial_plane_config;
15915 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15916 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15917 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15918 } else if (!IS_GEN2(dev_priv)) {
15919 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15920 dev_priv->display.get_initial_plane_config =
15921 i9xx_get_initial_plane_config;
15922 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15923 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15924 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15925 } else {
15926 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15927 dev_priv->display.get_initial_plane_config =
15928 i9xx_get_initial_plane_config;
15929 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15930 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15931 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15932 }
15933
15934 /* Returns the core display clock speed */
15935 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15936 dev_priv->display.get_display_clock_speed =
15937 skylake_get_display_clock_speed;
15938 else if (IS_BROXTON(dev_priv))
15939 dev_priv->display.get_display_clock_speed =
15940 broxton_get_display_clock_speed;
15941 else if (IS_BROADWELL(dev_priv))
15942 dev_priv->display.get_display_clock_speed =
15943 broadwell_get_display_clock_speed;
15944 else if (IS_HASWELL(dev_priv))
15945 dev_priv->display.get_display_clock_speed =
15946 haswell_get_display_clock_speed;
15947 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15948 dev_priv->display.get_display_clock_speed =
15949 valleyview_get_display_clock_speed;
15950 else if (IS_GEN5(dev_priv))
15951 dev_priv->display.get_display_clock_speed =
15952 ilk_get_display_clock_speed;
15953 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15954 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15955 dev_priv->display.get_display_clock_speed =
15956 i945_get_display_clock_speed;
15957 else if (IS_GM45(dev_priv))
15958 dev_priv->display.get_display_clock_speed =
15959 gm45_get_display_clock_speed;
15960 else if (IS_CRESTLINE(dev_priv))
15961 dev_priv->display.get_display_clock_speed =
15962 i965gm_get_display_clock_speed;
15963 else if (IS_PINEVIEW(dev_priv))
15964 dev_priv->display.get_display_clock_speed =
15965 pnv_get_display_clock_speed;
15966 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15967 dev_priv->display.get_display_clock_speed =
15968 g33_get_display_clock_speed;
15969 else if (IS_I915G(dev_priv))
15970 dev_priv->display.get_display_clock_speed =
15971 i915_get_display_clock_speed;
15972 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15973 dev_priv->display.get_display_clock_speed =
15974 i9xx_misc_get_display_clock_speed;
15975 else if (IS_I915GM(dev_priv))
15976 dev_priv->display.get_display_clock_speed =
15977 i915gm_get_display_clock_speed;
15978 else if (IS_I865G(dev_priv))
15979 dev_priv->display.get_display_clock_speed =
15980 i865_get_display_clock_speed;
15981 else if (IS_I85X(dev_priv))
15982 dev_priv->display.get_display_clock_speed =
15983 i85x_get_display_clock_speed;
15984 else { /* 830 */
15985 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15986 dev_priv->display.get_display_clock_speed =
15987 i830_get_display_clock_speed;
15988 }
15989
15990 if (IS_GEN5(dev_priv)) {
15991 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15992 } else if (IS_GEN6(dev_priv)) {
15993 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15994 } else if (IS_IVYBRIDGE(dev_priv)) {
15995 /* FIXME: detect B0+ stepping and use auto training */
15996 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15997 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15998 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15999 }
16000
16001 if (IS_BROADWELL(dev_priv)) {
16002 dev_priv->display.modeset_commit_cdclk =
16003 broadwell_modeset_commit_cdclk;
16004 dev_priv->display.modeset_calc_cdclk =
16005 broadwell_modeset_calc_cdclk;
16006 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16007 dev_priv->display.modeset_commit_cdclk =
16008 valleyview_modeset_commit_cdclk;
16009 dev_priv->display.modeset_calc_cdclk =
16010 valleyview_modeset_calc_cdclk;
16011 } else if (IS_BROXTON(dev_priv)) {
16012 dev_priv->display.modeset_commit_cdclk =
16013 bxt_modeset_commit_cdclk;
16014 dev_priv->display.modeset_calc_cdclk =
16015 bxt_modeset_calc_cdclk;
16016 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16017 dev_priv->display.modeset_commit_cdclk =
16018 skl_modeset_commit_cdclk;
16019 dev_priv->display.modeset_calc_cdclk =
16020 skl_modeset_calc_cdclk;
16021 }
16022
16023 if (dev_priv->info.gen >= 9)
16024 dev_priv->display.update_crtcs = skl_update_crtcs;
16025 else
16026 dev_priv->display.update_crtcs = intel_update_crtcs;
16027
16028 switch (INTEL_INFO(dev_priv)->gen) {
16029 case 2:
16030 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16031 break;
16032
16033 case 3:
16034 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16035 break;
16036
16037 case 4:
16038 case 5:
16039 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16040 break;
16041
16042 case 6:
16043 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16044 break;
16045 case 7:
16046 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16047 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16048 break;
16049 case 9:
16050 /* Drop through - unsupported since execlist only. */
16051 default:
16052 /* Default just returns -ENODEV to indicate unsupported */
16053 dev_priv->display.queue_flip = intel_default_queue_flip;
16054 }
16055 }
16056
16057 /*
16058 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16059 * resume, or other times. This quirk makes sure that's the case for
16060 * affected systems.
16061 */
16062 static void quirk_pipea_force(struct drm_device *dev)
16063 {
16064 struct drm_i915_private *dev_priv = to_i915(dev);
16065
16066 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16067 DRM_INFO("applying pipe a force quirk\n");
16068 }
16069
16070 static void quirk_pipeb_force(struct drm_device *dev)
16071 {
16072 struct drm_i915_private *dev_priv = to_i915(dev);
16073
16074 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16075 DRM_INFO("applying pipe b force quirk\n");
16076 }
16077
16078 /*
16079 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16080 */
16081 static void quirk_ssc_force_disable(struct drm_device *dev)
16082 {
16083 struct drm_i915_private *dev_priv = to_i915(dev);
16084 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16085 DRM_INFO("applying lvds SSC disable quirk\n");
16086 }
16087
16088 /*
16089 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16090 * brightness value
16091 */
16092 static void quirk_invert_brightness(struct drm_device *dev)
16093 {
16094 struct drm_i915_private *dev_priv = to_i915(dev);
16095 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16096 DRM_INFO("applying inverted panel brightness quirk\n");
16097 }
16098
16099 /* Some VBT's incorrectly indicate no backlight is present */
16100 static void quirk_backlight_present(struct drm_device *dev)
16101 {
16102 struct drm_i915_private *dev_priv = to_i915(dev);
16103 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16104 DRM_INFO("applying backlight present quirk\n");
16105 }
16106
16107 struct intel_quirk {
16108 int device;
16109 int subsystem_vendor;
16110 int subsystem_device;
16111 void (*hook)(struct drm_device *dev);
16112 };
16113
16114 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16115 struct intel_dmi_quirk {
16116 void (*hook)(struct drm_device *dev);
16117 const struct dmi_system_id (*dmi_id_list)[];
16118 };
16119
16120 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16121 {
16122 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16123 return 1;
16124 }
16125
16126 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16127 {
16128 .dmi_id_list = &(const struct dmi_system_id[]) {
16129 {
16130 .callback = intel_dmi_reverse_brightness,
16131 .ident = "NCR Corporation",
16132 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16133 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16134 },
16135 },
16136 { } /* terminating entry */
16137 },
16138 .hook = quirk_invert_brightness,
16139 },
16140 };
16141
16142 static struct intel_quirk intel_quirks[] = {
16143 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16144 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16145
16146 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16147 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16148
16149 /* 830 needs to leave pipe A & dpll A up */
16150 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16151
16152 /* 830 needs to leave pipe B & dpll B up */
16153 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16154
16155 /* Lenovo U160 cannot use SSC on LVDS */
16156 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16157
16158 /* Sony Vaio Y cannot use SSC on LVDS */
16159 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16160
16161 /* Acer Aspire 5734Z must invert backlight brightness */
16162 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16163
16164 /* Acer/eMachines G725 */
16165 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16166
16167 /* Acer/eMachines e725 */
16168 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16169
16170 /* Acer/Packard Bell NCL20 */
16171 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16172
16173 /* Acer Aspire 4736Z */
16174 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16175
16176 /* Acer Aspire 5336 */
16177 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16178
16179 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16180 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16181
16182 /* Acer C720 Chromebook (Core i3 4005U) */
16183 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16184
16185 /* Apple Macbook 2,1 (Core 2 T7400) */
16186 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16187
16188 /* Apple Macbook 4,1 */
16189 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16190
16191 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16192 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16193
16194 /* HP Chromebook 14 (Celeron 2955U) */
16195 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16196
16197 /* Dell Chromebook 11 */
16198 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16199
16200 /* Dell Chromebook 11 (2015 version) */
16201 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16202 };
16203
16204 static void intel_init_quirks(struct drm_device *dev)
16205 {
16206 struct pci_dev *d = dev->pdev;
16207 int i;
16208
16209 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16210 struct intel_quirk *q = &intel_quirks[i];
16211
16212 if (d->device == q->device &&
16213 (d->subsystem_vendor == q->subsystem_vendor ||
16214 q->subsystem_vendor == PCI_ANY_ID) &&
16215 (d->subsystem_device == q->subsystem_device ||
16216 q->subsystem_device == PCI_ANY_ID))
16217 q->hook(dev);
16218 }
16219 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16220 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16221 intel_dmi_quirks[i].hook(dev);
16222 }
16223 }
16224
16225 /* Disable the VGA plane that we never use */
16226 static void i915_disable_vga(struct drm_device *dev)
16227 {
16228 struct drm_i915_private *dev_priv = to_i915(dev);
16229 struct pci_dev *pdev = dev_priv->drm.pdev;
16230 u8 sr1;
16231 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16232
16233 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16234 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16235 outb(SR01, VGA_SR_INDEX);
16236 sr1 = inb(VGA_SR_DATA);
16237 outb(sr1 | 1<<5, VGA_SR_DATA);
16238 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16239 udelay(300);
16240
16241 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16242 POSTING_READ(vga_reg);
16243 }
16244
16245 void intel_modeset_init_hw(struct drm_device *dev)
16246 {
16247 struct drm_i915_private *dev_priv = to_i915(dev);
16248
16249 intel_update_cdclk(dev);
16250
16251 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16252
16253 intel_init_clock_gating(dev);
16254 }
16255
16256 /*
16257 * Calculate what we think the watermarks should be for the state we've read
16258 * out of the hardware and then immediately program those watermarks so that
16259 * we ensure the hardware settings match our internal state.
16260 *
16261 * We can calculate what we think WM's should be by creating a duplicate of the
16262 * current state (which was constructed during hardware readout) and running it
16263 * through the atomic check code to calculate new watermark values in the
16264 * state object.
16265 */
16266 static void sanitize_watermarks(struct drm_device *dev)
16267 {
16268 struct drm_i915_private *dev_priv = to_i915(dev);
16269 struct drm_atomic_state *state;
16270 struct drm_crtc *crtc;
16271 struct drm_crtc_state *cstate;
16272 struct drm_modeset_acquire_ctx ctx;
16273 int ret;
16274 int i;
16275
16276 /* Only supported on platforms that use atomic watermark design */
16277 if (!dev_priv->display.optimize_watermarks)
16278 return;
16279
16280 /*
16281 * We need to hold connection_mutex before calling duplicate_state so
16282 * that the connector loop is protected.
16283 */
16284 drm_modeset_acquire_init(&ctx, 0);
16285 retry:
16286 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16287 if (ret == -EDEADLK) {
16288 drm_modeset_backoff(&ctx);
16289 goto retry;
16290 } else if (WARN_ON(ret)) {
16291 goto fail;
16292 }
16293
16294 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16295 if (WARN_ON(IS_ERR(state)))
16296 goto fail;
16297
16298 /*
16299 * Hardware readout is the only time we don't want to calculate
16300 * intermediate watermarks (since we don't trust the current
16301 * watermarks).
16302 */
16303 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16304
16305 ret = intel_atomic_check(dev, state);
16306 if (ret) {
16307 /*
16308 * If we fail here, it means that the hardware appears to be
16309 * programmed in a way that shouldn't be possible, given our
16310 * understanding of watermark requirements. This might mean a
16311 * mistake in the hardware readout code or a mistake in the
16312 * watermark calculations for a given platform. Raise a WARN
16313 * so that this is noticeable.
16314 *
16315 * If this actually happens, we'll have to just leave the
16316 * BIOS-programmed watermarks untouched and hope for the best.
16317 */
16318 WARN(true, "Could not determine valid watermarks for inherited state\n");
16319 goto fail;
16320 }
16321
16322 /* Write calculated watermark values back */
16323 for_each_crtc_in_state(state, crtc, cstate, i) {
16324 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16325
16326 cs->wm.need_postvbl_update = true;
16327 dev_priv->display.optimize_watermarks(cs);
16328 }
16329
16330 drm_atomic_state_free(state);
16331 fail:
16332 drm_modeset_drop_locks(&ctx);
16333 drm_modeset_acquire_fini(&ctx);
16334 }
16335
16336 void intel_modeset_init(struct drm_device *dev)
16337 {
16338 struct drm_i915_private *dev_priv = to_i915(dev);
16339 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16340 int sprite, ret;
16341 enum pipe pipe;
16342 struct intel_crtc *crtc;
16343
16344 drm_mode_config_init(dev);
16345
16346 dev->mode_config.min_width = 0;
16347 dev->mode_config.min_height = 0;
16348
16349 dev->mode_config.preferred_depth = 24;
16350 dev->mode_config.prefer_shadow = 1;
16351
16352 dev->mode_config.allow_fb_modifiers = true;
16353
16354 dev->mode_config.funcs = &intel_mode_funcs;
16355
16356 intel_init_quirks(dev);
16357
16358 intel_init_pm(dev);
16359
16360 if (INTEL_INFO(dev)->num_pipes == 0)
16361 return;
16362
16363 /*
16364 * There may be no VBT; and if the BIOS enabled SSC we can
16365 * just keep using it to avoid unnecessary flicker. Whereas if the
16366 * BIOS isn't using it, don't assume it will work even if the VBT
16367 * indicates as much.
16368 */
16369 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16370 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16371 DREF_SSC1_ENABLE);
16372
16373 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16374 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16375 bios_lvds_use_ssc ? "en" : "dis",
16376 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16377 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16378 }
16379 }
16380
16381 if (IS_GEN2(dev)) {
16382 dev->mode_config.max_width = 2048;
16383 dev->mode_config.max_height = 2048;
16384 } else if (IS_GEN3(dev)) {
16385 dev->mode_config.max_width = 4096;
16386 dev->mode_config.max_height = 4096;
16387 } else {
16388 dev->mode_config.max_width = 8192;
16389 dev->mode_config.max_height = 8192;
16390 }
16391
16392 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16393 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16394 dev->mode_config.cursor_height = 1023;
16395 } else if (IS_GEN2(dev)) {
16396 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16397 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16398 } else {
16399 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16400 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16401 }
16402
16403 dev->mode_config.fb_base = ggtt->mappable_base;
16404
16405 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16406 INTEL_INFO(dev)->num_pipes,
16407 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16408
16409 for_each_pipe(dev_priv, pipe) {
16410 intel_crtc_init(dev, pipe);
16411 for_each_sprite(dev_priv, pipe, sprite) {
16412 ret = intel_plane_init(dev, pipe, sprite);
16413 if (ret)
16414 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16415 pipe_name(pipe), sprite_name(pipe, sprite), ret);
16416 }
16417 }
16418
16419 intel_update_czclk(dev_priv);
16420 intel_update_cdclk(dev);
16421
16422 intel_shared_dpll_init(dev);
16423
16424 if (dev_priv->max_cdclk_freq == 0)
16425 intel_update_max_cdclk(dev);
16426
16427 /* Just disable it once at startup */
16428 i915_disable_vga(dev);
16429 intel_setup_outputs(dev);
16430
16431 drm_modeset_lock_all(dev);
16432 intel_modeset_setup_hw_state(dev);
16433 drm_modeset_unlock_all(dev);
16434
16435 for_each_intel_crtc(dev, crtc) {
16436 struct intel_initial_plane_config plane_config = {};
16437
16438 if (!crtc->active)
16439 continue;
16440
16441 /*
16442 * Note that reserving the BIOS fb up front prevents us
16443 * from stuffing other stolen allocations like the ring
16444 * on top. This prevents some ugliness at boot time, and
16445 * can even allow for smooth boot transitions if the BIOS
16446 * fb is large enough for the active pipe configuration.
16447 */
16448 dev_priv->display.get_initial_plane_config(crtc,
16449 &plane_config);
16450
16451 /*
16452 * If the fb is shared between multiple heads, we'll
16453 * just get the first one.
16454 */
16455 intel_find_initial_plane_obj(crtc, &plane_config);
16456 }
16457
16458 /*
16459 * Make sure hardware watermarks really match the state we read out.
16460 * Note that we need to do this after reconstructing the BIOS fb's
16461 * since the watermark calculation done here will use pstate->fb.
16462 */
16463 sanitize_watermarks(dev);
16464 }
16465
16466 static void intel_enable_pipe_a(struct drm_device *dev)
16467 {
16468 struct intel_connector *connector;
16469 struct drm_connector *crt = NULL;
16470 struct intel_load_detect_pipe load_detect_temp;
16471 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16472
16473 /* We can't just switch on the pipe A, we need to set things up with a
16474 * proper mode and output configuration. As a gross hack, enable pipe A
16475 * by enabling the load detect pipe once. */
16476 for_each_intel_connector(dev, connector) {
16477 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16478 crt = &connector->base;
16479 break;
16480 }
16481 }
16482
16483 if (!crt)
16484 return;
16485
16486 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16487 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16488 }
16489
16490 static bool
16491 intel_check_plane_mapping(struct intel_crtc *crtc)
16492 {
16493 struct drm_device *dev = crtc->base.dev;
16494 struct drm_i915_private *dev_priv = to_i915(dev);
16495 u32 val;
16496
16497 if (INTEL_INFO(dev)->num_pipes == 1)
16498 return true;
16499
16500 val = I915_READ(DSPCNTR(!crtc->plane));
16501
16502 if ((val & DISPLAY_PLANE_ENABLE) &&
16503 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16504 return false;
16505
16506 return true;
16507 }
16508
16509 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16510 {
16511 struct drm_device *dev = crtc->base.dev;
16512 struct intel_encoder *encoder;
16513
16514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16515 return true;
16516
16517 return false;
16518 }
16519
16520 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16521 {
16522 struct drm_device *dev = encoder->base.dev;
16523 struct intel_connector *connector;
16524
16525 for_each_connector_on_encoder(dev, &encoder->base, connector)
16526 return connector;
16527
16528 return NULL;
16529 }
16530
16531 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16532 enum transcoder pch_transcoder)
16533 {
16534 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16535 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16536 }
16537
16538 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16539 {
16540 struct drm_device *dev = crtc->base.dev;
16541 struct drm_i915_private *dev_priv = to_i915(dev);
16542 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16543
16544 /* Clear any frame start delays used for debugging left by the BIOS */
16545 if (!transcoder_is_dsi(cpu_transcoder)) {
16546 i915_reg_t reg = PIPECONF(cpu_transcoder);
16547
16548 I915_WRITE(reg,
16549 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16550 }
16551
16552 /* restore vblank interrupts to correct state */
16553 drm_crtc_vblank_reset(&crtc->base);
16554 if (crtc->active) {
16555 struct intel_plane *plane;
16556
16557 drm_crtc_vblank_on(&crtc->base);
16558
16559 /* Disable everything but the primary plane */
16560 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16561 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16562 continue;
16563
16564 plane->disable_plane(&plane->base, &crtc->base);
16565 }
16566 }
16567
16568 /* We need to sanitize the plane -> pipe mapping first because this will
16569 * disable the crtc (and hence change the state) if it is wrong. Note
16570 * that gen4+ has a fixed plane -> pipe mapping. */
16571 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16572 bool plane;
16573
16574 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16575 crtc->base.base.id, crtc->base.name);
16576
16577 /* Pipe has the wrong plane attached and the plane is active.
16578 * Temporarily change the plane mapping and disable everything
16579 * ... */
16580 plane = crtc->plane;
16581 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16582 crtc->plane = !plane;
16583 intel_crtc_disable_noatomic(&crtc->base);
16584 crtc->plane = plane;
16585 }
16586
16587 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16588 crtc->pipe == PIPE_A && !crtc->active) {
16589 /* BIOS forgot to enable pipe A, this mostly happens after
16590 * resume. Force-enable the pipe to fix this, the update_dpms
16591 * call below we restore the pipe to the right state, but leave
16592 * the required bits on. */
16593 intel_enable_pipe_a(dev);
16594 }
16595
16596 /* Adjust the state of the output pipe according to whether we
16597 * have active connectors/encoders. */
16598 if (crtc->active && !intel_crtc_has_encoders(crtc))
16599 intel_crtc_disable_noatomic(&crtc->base);
16600
16601 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16602 /*
16603 * We start out with underrun reporting disabled to avoid races.
16604 * For correct bookkeeping mark this on active crtcs.
16605 *
16606 * Also on gmch platforms we dont have any hardware bits to
16607 * disable the underrun reporting. Which means we need to start
16608 * out with underrun reporting disabled also on inactive pipes,
16609 * since otherwise we'll complain about the garbage we read when
16610 * e.g. coming up after runtime pm.
16611 *
16612 * No protection against concurrent access is required - at
16613 * worst a fifo underrun happens which also sets this to false.
16614 */
16615 crtc->cpu_fifo_underrun_disabled = true;
16616 /*
16617 * We track the PCH trancoder underrun reporting state
16618 * within the crtc. With crtc for pipe A housing the underrun
16619 * reporting state for PCH transcoder A, crtc for pipe B housing
16620 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16621 * and marking underrun reporting as disabled for the non-existing
16622 * PCH transcoders B and C would prevent enabling the south
16623 * error interrupt (see cpt_can_enable_serr_int()).
16624 */
16625 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16626 crtc->pch_fifo_underrun_disabled = true;
16627 }
16628 }
16629
16630 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16631 {
16632 struct intel_connector *connector;
16633
16634 /* We need to check both for a crtc link (meaning that the
16635 * encoder is active and trying to read from a pipe) and the
16636 * pipe itself being active. */
16637 bool has_active_crtc = encoder->base.crtc &&
16638 to_intel_crtc(encoder->base.crtc)->active;
16639
16640 connector = intel_encoder_find_connector(encoder);
16641 if (connector && !has_active_crtc) {
16642 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16643 encoder->base.base.id,
16644 encoder->base.name);
16645
16646 /* Connector is active, but has no active pipe. This is
16647 * fallout from our resume register restoring. Disable
16648 * the encoder manually again. */
16649 if (encoder->base.crtc) {
16650 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16651
16652 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16653 encoder->base.base.id,
16654 encoder->base.name);
16655 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16656 if (encoder->post_disable)
16657 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16658 }
16659 encoder->base.crtc = NULL;
16660
16661 /* Inconsistent output/port/pipe state happens presumably due to
16662 * a bug in one of the get_hw_state functions. Or someplace else
16663 * in our code, like the register restore mess on resume. Clamp
16664 * things to off as a safer default. */
16665
16666 connector->base.dpms = DRM_MODE_DPMS_OFF;
16667 connector->base.encoder = NULL;
16668 }
16669 /* Enabled encoders without active connectors will be fixed in
16670 * the crtc fixup. */
16671 }
16672
16673 void i915_redisable_vga_power_on(struct drm_device *dev)
16674 {
16675 struct drm_i915_private *dev_priv = to_i915(dev);
16676 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16677
16678 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16679 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16680 i915_disable_vga(dev);
16681 }
16682 }
16683
16684 void i915_redisable_vga(struct drm_device *dev)
16685 {
16686 struct drm_i915_private *dev_priv = to_i915(dev);
16687
16688 /* This function can be called both from intel_modeset_setup_hw_state or
16689 * at a very early point in our resume sequence, where the power well
16690 * structures are not yet restored. Since this function is at a very
16691 * paranoid "someone might have enabled VGA while we were not looking"
16692 * level, just check if the power well is enabled instead of trying to
16693 * follow the "don't touch the power well if we don't need it" policy
16694 * the rest of the driver uses. */
16695 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16696 return;
16697
16698 i915_redisable_vga_power_on(dev);
16699
16700 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16701 }
16702
16703 static bool primary_get_hw_state(struct intel_plane *plane)
16704 {
16705 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16706
16707 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16708 }
16709
16710 /* FIXME read out full plane state for all planes */
16711 static void readout_plane_state(struct intel_crtc *crtc)
16712 {
16713 struct drm_plane *primary = crtc->base.primary;
16714 struct intel_plane_state *plane_state =
16715 to_intel_plane_state(primary->state);
16716
16717 plane_state->base.visible = crtc->active &&
16718 primary_get_hw_state(to_intel_plane(primary));
16719
16720 if (plane_state->base.visible)
16721 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16722 }
16723
16724 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16725 {
16726 struct drm_i915_private *dev_priv = to_i915(dev);
16727 enum pipe pipe;
16728 struct intel_crtc *crtc;
16729 struct intel_encoder *encoder;
16730 struct intel_connector *connector;
16731 int i;
16732
16733 dev_priv->active_crtcs = 0;
16734
16735 for_each_intel_crtc(dev, crtc) {
16736 struct intel_crtc_state *crtc_state = crtc->config;
16737 int pixclk = 0;
16738
16739 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16740 memset(crtc_state, 0, sizeof(*crtc_state));
16741 crtc_state->base.crtc = &crtc->base;
16742
16743 crtc_state->base.active = crtc_state->base.enable =
16744 dev_priv->display.get_pipe_config(crtc, crtc_state);
16745
16746 crtc->base.enabled = crtc_state->base.enable;
16747 crtc->active = crtc_state->base.active;
16748
16749 if (crtc_state->base.active) {
16750 dev_priv->active_crtcs |= 1 << crtc->pipe;
16751
16752 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16753 pixclk = ilk_pipe_pixel_rate(crtc_state);
16754 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16755 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16756 else
16757 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16758
16759 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16760 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16761 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16762 }
16763
16764 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16765
16766 readout_plane_state(crtc);
16767
16768 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16769 crtc->base.base.id, crtc->base.name,
16770 crtc->active ? "enabled" : "disabled");
16771 }
16772
16773 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16774 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16775
16776 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16777 &pll->config.hw_state);
16778 pll->config.crtc_mask = 0;
16779 for_each_intel_crtc(dev, crtc) {
16780 if (crtc->active && crtc->config->shared_dpll == pll)
16781 pll->config.crtc_mask |= 1 << crtc->pipe;
16782 }
16783 pll->active_mask = pll->config.crtc_mask;
16784
16785 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16786 pll->name, pll->config.crtc_mask, pll->on);
16787 }
16788
16789 for_each_intel_encoder(dev, encoder) {
16790 pipe = 0;
16791
16792 if (encoder->get_hw_state(encoder, &pipe)) {
16793 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16794 encoder->base.crtc = &crtc->base;
16795 crtc->config->output_types |= 1 << encoder->type;
16796 encoder->get_config(encoder, crtc->config);
16797 } else {
16798 encoder->base.crtc = NULL;
16799 }
16800
16801 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16802 encoder->base.base.id,
16803 encoder->base.name,
16804 encoder->base.crtc ? "enabled" : "disabled",
16805 pipe_name(pipe));
16806 }
16807
16808 for_each_intel_connector(dev, connector) {
16809 if (connector->get_hw_state(connector)) {
16810 connector->base.dpms = DRM_MODE_DPMS_ON;
16811
16812 encoder = connector->encoder;
16813 connector->base.encoder = &encoder->base;
16814
16815 if (encoder->base.crtc &&
16816 encoder->base.crtc->state->active) {
16817 /*
16818 * This has to be done during hardware readout
16819 * because anything calling .crtc_disable may
16820 * rely on the connector_mask being accurate.
16821 */
16822 encoder->base.crtc->state->connector_mask |=
16823 1 << drm_connector_index(&connector->base);
16824 encoder->base.crtc->state->encoder_mask |=
16825 1 << drm_encoder_index(&encoder->base);
16826 }
16827
16828 } else {
16829 connector->base.dpms = DRM_MODE_DPMS_OFF;
16830 connector->base.encoder = NULL;
16831 }
16832 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16833 connector->base.base.id,
16834 connector->base.name,
16835 connector->base.encoder ? "enabled" : "disabled");
16836 }
16837
16838 for_each_intel_crtc(dev, crtc) {
16839 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16840
16841 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16842 if (crtc->base.state->active) {
16843 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16844 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16845 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16846
16847 /*
16848 * The initial mode needs to be set in order to keep
16849 * the atomic core happy. It wants a valid mode if the
16850 * crtc's enabled, so we do the above call.
16851 *
16852 * At this point some state updated by the connectors
16853 * in their ->detect() callback has not run yet, so
16854 * no recalculation can be done yet.
16855 *
16856 * Even if we could do a recalculation and modeset
16857 * right now it would cause a double modeset if
16858 * fbdev or userspace chooses a different initial mode.
16859 *
16860 * If that happens, someone indicated they wanted a
16861 * mode change, which means it's safe to do a full
16862 * recalculation.
16863 */
16864 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16865
16866 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16867 update_scanline_offset(crtc);
16868 }
16869
16870 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16871 }
16872 }
16873
16874 /* Scan out the current hw modeset state,
16875 * and sanitizes it to the current state
16876 */
16877 static void
16878 intel_modeset_setup_hw_state(struct drm_device *dev)
16879 {
16880 struct drm_i915_private *dev_priv = to_i915(dev);
16881 enum pipe pipe;
16882 struct intel_crtc *crtc;
16883 struct intel_encoder *encoder;
16884 int i;
16885
16886 intel_modeset_readout_hw_state(dev);
16887
16888 /* HW state is read out, now we need to sanitize this mess. */
16889 for_each_intel_encoder(dev, encoder) {
16890 intel_sanitize_encoder(encoder);
16891 }
16892
16893 for_each_pipe(dev_priv, pipe) {
16894 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16895 intel_sanitize_crtc(crtc);
16896 intel_dump_pipe_config(crtc, crtc->config,
16897 "[setup_hw_state]");
16898 }
16899
16900 intel_modeset_update_connector_atomic_state(dev);
16901
16902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16903 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16904
16905 if (!pll->on || pll->active_mask)
16906 continue;
16907
16908 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16909
16910 pll->funcs.disable(dev_priv, pll);
16911 pll->on = false;
16912 }
16913
16914 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16915 vlv_wm_get_hw_state(dev);
16916 else if (IS_GEN9(dev))
16917 skl_wm_get_hw_state(dev);
16918 else if (HAS_PCH_SPLIT(dev_priv))
16919 ilk_wm_get_hw_state(dev);
16920
16921 for_each_intel_crtc(dev, crtc) {
16922 unsigned long put_domains;
16923
16924 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16925 if (WARN_ON(put_domains))
16926 modeset_put_power_domains(dev_priv, put_domains);
16927 }
16928 intel_display_set_init_power(dev_priv, false);
16929
16930 intel_fbc_init_pipe_state(dev_priv);
16931 }
16932
16933 void intel_display_resume(struct drm_device *dev)
16934 {
16935 struct drm_i915_private *dev_priv = to_i915(dev);
16936 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16937 struct drm_modeset_acquire_ctx ctx;
16938 int ret;
16939
16940 dev_priv->modeset_restore_state = NULL;
16941 if (state)
16942 state->acquire_ctx = &ctx;
16943
16944 /*
16945 * This is a cludge because with real atomic modeset mode_config.mutex
16946 * won't be taken. Unfortunately some probed state like
16947 * audio_codec_enable is still protected by mode_config.mutex, so lock
16948 * it here for now.
16949 */
16950 mutex_lock(&dev->mode_config.mutex);
16951 drm_modeset_acquire_init(&ctx, 0);
16952
16953 while (1) {
16954 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16955 if (ret != -EDEADLK)
16956 break;
16957
16958 drm_modeset_backoff(&ctx);
16959 }
16960
16961 if (!ret)
16962 ret = __intel_display_resume(dev, state);
16963
16964 drm_modeset_drop_locks(&ctx);
16965 drm_modeset_acquire_fini(&ctx);
16966 mutex_unlock(&dev->mode_config.mutex);
16967
16968 if (ret) {
16969 DRM_ERROR("Restoring old state failed with %i\n", ret);
16970 drm_atomic_state_free(state);
16971 }
16972 }
16973
16974 void intel_modeset_gem_init(struct drm_device *dev)
16975 {
16976 struct drm_i915_private *dev_priv = to_i915(dev);
16977 struct drm_crtc *c;
16978 struct drm_i915_gem_object *obj;
16979
16980 intel_init_gt_powersave(dev_priv);
16981
16982 intel_modeset_init_hw(dev);
16983
16984 intel_setup_overlay(dev_priv);
16985
16986 /*
16987 * Make sure any fbs we allocated at startup are properly
16988 * pinned & fenced. When we do the allocation it's too early
16989 * for this.
16990 */
16991 for_each_crtc(dev, c) {
16992 struct i915_vma *vma;
16993
16994 obj = intel_fb_obj(c->primary->fb);
16995 if (obj == NULL)
16996 continue;
16997
16998 mutex_lock(&dev->struct_mutex);
16999 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17000 c->primary->state->rotation);
17001 mutex_unlock(&dev->struct_mutex);
17002 if (IS_ERR(vma)) {
17003 DRM_ERROR("failed to pin boot fb on pipe %d\n",
17004 to_intel_crtc(c)->pipe);
17005 drm_framebuffer_unreference(c->primary->fb);
17006 c->primary->fb = NULL;
17007 c->primary->crtc = c->primary->state->crtc = NULL;
17008 update_state_fb(c->primary);
17009 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17010 }
17011 }
17012 }
17013
17014 int intel_connector_register(struct drm_connector *connector)
17015 {
17016 struct intel_connector *intel_connector = to_intel_connector(connector);
17017 int ret;
17018
17019 ret = intel_backlight_device_register(intel_connector);
17020 if (ret)
17021 goto err;
17022
17023 return 0;
17024
17025 err:
17026 return ret;
17027 }
17028
17029 void intel_connector_unregister(struct drm_connector *connector)
17030 {
17031 struct intel_connector *intel_connector = to_intel_connector(connector);
17032
17033 intel_backlight_device_unregister(intel_connector);
17034 intel_panel_destroy_backlight(connector);
17035 }
17036
17037 void intel_modeset_cleanup(struct drm_device *dev)
17038 {
17039 struct drm_i915_private *dev_priv = to_i915(dev);
17040
17041 intel_disable_gt_powersave(dev_priv);
17042
17043 /*
17044 * Interrupts and polling as the first thing to avoid creating havoc.
17045 * Too much stuff here (turning of connectors, ...) would
17046 * experience fancy races otherwise.
17047 */
17048 intel_irq_uninstall(dev_priv);
17049
17050 /*
17051 * Due to the hpd irq storm handling the hotplug work can re-arm the
17052 * poll handlers. Hence disable polling after hpd handling is shut down.
17053 */
17054 drm_kms_helper_poll_fini(dev);
17055
17056 intel_unregister_dsm_handler();
17057
17058 intel_fbc_global_disable(dev_priv);
17059
17060 /* flush any delayed tasks or pending work */
17061 flush_scheduled_work();
17062
17063 drm_mode_config_cleanup(dev);
17064
17065 intel_cleanup_overlay(dev_priv);
17066
17067 intel_cleanup_gt_powersave(dev_priv);
17068
17069 intel_teardown_gmbus(dev);
17070 }
17071
17072 void intel_connector_attach_encoder(struct intel_connector *connector,
17073 struct intel_encoder *encoder)
17074 {
17075 connector->encoder = encoder;
17076 drm_mode_connector_attach_encoder(&connector->base,
17077 &encoder->base);
17078 }
17079
17080 /*
17081 * set vga decode state - true == enable VGA decode
17082 */
17083 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17084 {
17085 struct drm_i915_private *dev_priv = to_i915(dev);
17086 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17087 u16 gmch_ctrl;
17088
17089 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17090 DRM_ERROR("failed to read control word\n");
17091 return -EIO;
17092 }
17093
17094 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17095 return 0;
17096
17097 if (state)
17098 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17099 else
17100 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17101
17102 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17103 DRM_ERROR("failed to write control word\n");
17104 return -EIO;
17105 }
17106
17107 return 0;
17108 }
17109
17110 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17111
17112 struct intel_display_error_state {
17113
17114 u32 power_well_driver;
17115
17116 int num_transcoders;
17117
17118 struct intel_cursor_error_state {
17119 u32 control;
17120 u32 position;
17121 u32 base;
17122 u32 size;
17123 } cursor[I915_MAX_PIPES];
17124
17125 struct intel_pipe_error_state {
17126 bool power_domain_on;
17127 u32 source;
17128 u32 stat;
17129 } pipe[I915_MAX_PIPES];
17130
17131 struct intel_plane_error_state {
17132 u32 control;
17133 u32 stride;
17134 u32 size;
17135 u32 pos;
17136 u32 addr;
17137 u32 surface;
17138 u32 tile_offset;
17139 } plane[I915_MAX_PIPES];
17140
17141 struct intel_transcoder_error_state {
17142 bool power_domain_on;
17143 enum transcoder cpu_transcoder;
17144
17145 u32 conf;
17146
17147 u32 htotal;
17148 u32 hblank;
17149 u32 hsync;
17150 u32 vtotal;
17151 u32 vblank;
17152 u32 vsync;
17153 } transcoder[4];
17154 };
17155
17156 struct intel_display_error_state *
17157 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17158 {
17159 struct intel_display_error_state *error;
17160 int transcoders[] = {
17161 TRANSCODER_A,
17162 TRANSCODER_B,
17163 TRANSCODER_C,
17164 TRANSCODER_EDP,
17165 };
17166 int i;
17167
17168 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17169 return NULL;
17170
17171 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17172 if (error == NULL)
17173 return NULL;
17174
17175 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17176 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17177
17178 for_each_pipe(dev_priv, i) {
17179 error->pipe[i].power_domain_on =
17180 __intel_display_power_is_enabled(dev_priv,
17181 POWER_DOMAIN_PIPE(i));
17182 if (!error->pipe[i].power_domain_on)
17183 continue;
17184
17185 error->cursor[i].control = I915_READ(CURCNTR(i));
17186 error->cursor[i].position = I915_READ(CURPOS(i));
17187 error->cursor[i].base = I915_READ(CURBASE(i));
17188
17189 error->plane[i].control = I915_READ(DSPCNTR(i));
17190 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17191 if (INTEL_GEN(dev_priv) <= 3) {
17192 error->plane[i].size = I915_READ(DSPSIZE(i));
17193 error->plane[i].pos = I915_READ(DSPPOS(i));
17194 }
17195 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17196 error->plane[i].addr = I915_READ(DSPADDR(i));
17197 if (INTEL_GEN(dev_priv) >= 4) {
17198 error->plane[i].surface = I915_READ(DSPSURF(i));
17199 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17200 }
17201
17202 error->pipe[i].source = I915_READ(PIPESRC(i));
17203
17204 if (HAS_GMCH_DISPLAY(dev_priv))
17205 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17206 }
17207
17208 /* Note: this does not include DSI transcoders. */
17209 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17210 if (HAS_DDI(dev_priv))
17211 error->num_transcoders++; /* Account for eDP. */
17212
17213 for (i = 0; i < error->num_transcoders; i++) {
17214 enum transcoder cpu_transcoder = transcoders[i];
17215
17216 error->transcoder[i].power_domain_on =
17217 __intel_display_power_is_enabled(dev_priv,
17218 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17219 if (!error->transcoder[i].power_domain_on)
17220 continue;
17221
17222 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17223
17224 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17225 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17226 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17227 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17228 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17229 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17230 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17231 }
17232
17233 return error;
17234 }
17235
17236 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17237
17238 void
17239 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17240 struct drm_device *dev,
17241 struct intel_display_error_state *error)
17242 {
17243 struct drm_i915_private *dev_priv = to_i915(dev);
17244 int i;
17245
17246 if (!error)
17247 return;
17248
17249 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17250 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17251 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17252 error->power_well_driver);
17253 for_each_pipe(dev_priv, i) {
17254 err_printf(m, "Pipe [%d]:\n", i);
17255 err_printf(m, " Power: %s\n",
17256 onoff(error->pipe[i].power_domain_on));
17257 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17258 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17259
17260 err_printf(m, "Plane [%d]:\n", i);
17261 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17262 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17263 if (INTEL_INFO(dev)->gen <= 3) {
17264 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17265 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17266 }
17267 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17268 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17269 if (INTEL_INFO(dev)->gen >= 4) {
17270 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17271 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17272 }
17273
17274 err_printf(m, "Cursor [%d]:\n", i);
17275 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17276 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17277 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17278 }
17279
17280 for (i = 0; i < error->num_transcoders; i++) {
17281 err_printf(m, "CPU transcoder: %s\n",
17282 transcoder_name(error->transcoder[i].cpu_transcoder));
17283 err_printf(m, " Power: %s\n",
17284 onoff(error->transcoder[i].power_domain_on));
17285 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17286 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17287 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17288 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17289 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17290 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17291 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17292 }
17293 }
17294
17295 #endif
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