2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
196 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
197 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
198 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
199 int max_dotclk
= dev_priv
->max_dotclk_freq
;
202 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
204 if (type
!= DP_DS_PORT_TYPE_VGA
)
207 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
208 intel_dp
->downstream_ports
);
210 if (ds_max_dotclk
!= 0)
211 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
216 static enum drm_mode_status
217 intel_dp_mode_valid(struct drm_connector
*connector
,
218 struct drm_display_mode
*mode
)
220 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
222 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
223 int target_clock
= mode
->clock
;
224 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
227 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
229 if (is_edp(intel_dp
) && fixed_mode
) {
230 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
233 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
236 target_clock
= fixed_mode
->clock
;
239 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
240 max_lanes
= intel_dp_max_lane_count(intel_dp
);
242 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
243 mode_rate
= intel_dp_link_required(target_clock
, 18);
245 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
246 return MODE_CLOCK_HIGH
;
248 if (mode
->clock
< 10000)
249 return MODE_CLOCK_LOW
;
251 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
252 return MODE_H_ILLEGAL
;
257 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
264 for (i
= 0; i
< src_bytes
; i
++)
265 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
269 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
274 for (i
= 0; i
< dst_bytes
; i
++)
275 dst
[i
] = src
>> ((3-i
) * 8);
279 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
280 struct intel_dp
*intel_dp
);
282 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
283 struct intel_dp
*intel_dp
);
285 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
287 static void pps_lock(struct intel_dp
*intel_dp
)
289 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
290 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
291 struct drm_device
*dev
= encoder
->base
.dev
;
292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
293 enum intel_display_power_domain power_domain
;
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
299 power_domain
= intel_display_port_aux_power_domain(encoder
);
300 intel_display_power_get(dev_priv
, power_domain
);
302 mutex_lock(&dev_priv
->pps_mutex
);
305 static void pps_unlock(struct intel_dp
*intel_dp
)
307 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
308 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
309 struct drm_device
*dev
= encoder
->base
.dev
;
310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
311 enum intel_display_power_domain power_domain
;
313 mutex_unlock(&dev_priv
->pps_mutex
);
315 power_domain
= intel_display_port_aux_power_domain(encoder
);
316 intel_display_power_put(dev_priv
, power_domain
);
320 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
325 enum pipe pipe
= intel_dp
->pps_pipe
;
326 bool pll_enabled
, release_cl_override
= false;
327 enum dpio_phy phy
= DPIO_PHY(pipe
);
328 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
331 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
));
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
342 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
343 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
344 DP
|= DP_PORT_WIDTH(1);
345 DP
|= DP_LINK_TRAIN_PAT_1
;
347 if (IS_CHERRYVIEW(dev
))
348 DP
|= DP_PIPE_SELECT_CHV(pipe
);
349 else if (pipe
== PIPE_B
)
350 DP
|= DP_PIPEB_SELECT
;
352 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
359 release_cl_override
= IS_CHERRYVIEW(dev
) &&
360 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
362 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
376 I915_WRITE(intel_dp
->output_reg
, DP
);
377 POSTING_READ(intel_dp
->output_reg
);
379 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
386 vlv_force_pll_off(dev
, pipe
);
388 if (release_cl_override
)
389 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
394 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
396 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
397 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
398 struct drm_i915_private
*dev_priv
= to_i915(dev
);
399 struct intel_encoder
*encoder
;
400 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
403 lockdep_assert_held(&dev_priv
->pps_mutex
);
405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp
));
408 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
409 return intel_dp
->pps_pipe
;
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
415 for_each_intel_encoder(dev
, encoder
) {
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
457 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
459 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
460 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
463 lockdep_assert_held(&dev_priv
->pps_mutex
);
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp
));
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
473 if (!intel_dp
->pps_reset
)
476 intel_dp
->pps_reset
= false;
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
482 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
487 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
490 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
493 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
499 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
502 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
509 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
511 vlv_pipe_check pipe_check
)
515 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
516 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
517 PANEL_PORT_SELECT_MASK
;
519 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
522 if (!pipe_check(dev_priv
, pipe
))
532 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
534 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
535 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
536 struct drm_i915_private
*dev_priv
= to_i915(dev
);
537 enum port port
= intel_dig_port
->port
;
539 lockdep_assert_held(&dev_priv
->pps_mutex
);
541 /* try to find a pipe with this port selected */
542 /* first pick one where the panel is on */
543 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
547 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
548 vlv_pipe_has_vdd_on
);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
551 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
564 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
565 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
568 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
570 struct drm_device
*dev
= &dev_priv
->drm
;
571 struct intel_encoder
*encoder
;
573 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
587 for_each_intel_encoder(dev
, encoder
) {
588 struct intel_dp
*intel_dp
;
590 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
593 intel_dp
= enc_to_intel_dp(&encoder
->base
);
595 intel_dp
->pps_reset
= true;
597 intel_dp
->pps_pipe
= INVALID_PIPE
;
601 struct pps_registers
{
609 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
610 struct intel_dp
*intel_dp
,
611 struct pps_registers
*regs
)
615 memset(regs
, 0, sizeof(*regs
));
617 if (IS_BROXTON(dev_priv
))
618 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
619 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
620 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
622 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
623 regs
->pp_stat
= PP_STATUS(pps_idx
);
624 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
625 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
626 if (!IS_BROXTON(dev_priv
))
627 regs
->pp_div
= PP_DIVISOR(pps_idx
);
631 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
633 struct pps_registers regs
;
635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
642 _pp_stat_reg(struct intel_dp
*intel_dp
)
644 struct pps_registers regs
;
646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
657 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
659 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
662 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
667 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
668 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
669 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
672 pp_ctrl_reg
= PP_CONTROL(pipe
);
673 pp_div_reg
= PP_DIVISOR(pipe
);
674 pp_div
= I915_READ(pp_div_reg
);
675 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
679 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
680 msleep(intel_dp
->panel_power_cycle_delay
);
683 pps_unlock(intel_dp
);
688 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
693 lockdep_assert_held(&dev_priv
->pps_mutex
);
695 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
696 intel_dp
->pps_pipe
== INVALID_PIPE
)
699 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
702 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
704 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
705 struct drm_i915_private
*dev_priv
= to_i915(dev
);
707 lockdep_assert_held(&dev_priv
->pps_mutex
);
709 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
710 intel_dp
->pps_pipe
== INVALID_PIPE
)
713 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
717 intel_dp_check_edp(struct intel_dp
*intel_dp
)
719 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
722 if (!is_edp(intel_dp
))
725 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
728 I915_READ(_pp_stat_reg(intel_dp
)),
729 I915_READ(_pp_ctrl_reg(intel_dp
)));
734 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
739 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
746 msecs_to_jiffies_timeout(10));
748 done
= wait_for(C
, 10) == 0;
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
759 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
760 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
766 * The clock divider is based off the hrawclk, and would like to run at
767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
769 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
774 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
775 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
785 if (intel_dig_port
->port
== PORT_A
)
786 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
788 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
794 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
796 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
797 /* Workaround for non-ULT HSW */
805 return ilk_get_aux_clock_divider(intel_dp
, index
);
808 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
815 return index
? 0 : 1;
818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
821 uint32_t aux_clock_divider
)
823 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
824 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
825 uint32_t precharge
, timeout
;
832 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
833 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
835 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
837 return DP_AUX_CH_CTL_SEND_BUSY
|
839 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
840 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
842 DP_AUX_CH_CTL_RECEIVE_ERROR
|
843 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
844 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
845 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
848 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
853 return DP_AUX_CH_CTL_SEND_BUSY
|
855 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
856 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
857 DP_AUX_CH_CTL_TIME_OUT_1600us
|
858 DP_AUX_CH_CTL_RECEIVE_ERROR
|
859 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
860 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
861 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
865 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
866 const uint8_t *send
, int send_bytes
,
867 uint8_t *recv
, int recv_size
)
869 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
870 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
871 struct drm_i915_private
*dev_priv
= to_i915(dev
);
872 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
873 uint32_t aux_clock_divider
;
874 int i
, ret
, recv_bytes
;
877 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
883 * We will be called with VDD already enabled for dpcd/edid/oui reads.
884 * In such cases we want to leave VDD enabled and it's up to upper layers
885 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
888 vdd
= edp_panel_vdd_on(intel_dp
);
890 /* dp aux is extremely sensitive to irq latency, hence request the
891 * lowest possible wakeup latency and so prevent the cpu from going into
894 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
896 intel_dp_check_edp(intel_dp
);
898 /* Try to wait for any previous AUX channel activity */
899 for (try = 0; try < 3; try++) {
900 status
= I915_READ_NOTRACE(ch_ctl
);
901 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
907 static u32 last_status
= -1;
908 const u32 status
= I915_READ(ch_ctl
);
910 if (status
!= last_status
) {
911 WARN(1, "dp_aux_ch not started status 0x%08x\n",
913 last_status
= status
;
920 /* Only 5 data registers! */
921 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
926 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
927 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
932 /* Must try at least 3 times according to DP spec */
933 for (try = 0; try < 5; try++) {
934 /* Load the send data into the aux channel data registers */
935 for (i
= 0; i
< send_bytes
; i
+= 4)
936 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
937 intel_dp_pack_aux(send
+ i
,
940 /* Send the command and wait for it to complete */
941 I915_WRITE(ch_ctl
, send_ctl
);
943 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
945 /* Clear done status and any errors */
949 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
950 DP_AUX_CH_CTL_RECEIVE_ERROR
);
952 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
955 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
956 * 400us delay required for errors and timeouts
957 * Timeout errors from the HW already meet this
958 * requirement so skip to next iteration
960 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
961 usleep_range(400, 500);
964 if (status
& DP_AUX_CH_CTL_DONE
)
969 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
970 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
976 /* Check for timeout or receive error.
977 * Timeouts occur when the sink is not connected
979 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
980 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
985 /* Timeouts occur when the device isn't connected, so they're
986 * "normal" -- don't fill the kernel log with these */
987 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
988 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
993 /* Unload any bytes sent back from the other side */
994 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
995 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
998 * By BSpec: "Message sizes of 0 or >20 are not allowed."
999 * We have no idea of what happened so we return -EBUSY so
1000 * drm layer takes care for the necessary retries.
1002 if (recv_bytes
== 0 || recv_bytes
> 20) {
1003 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1006 * FIXME: This patch was created on top of a series that
1007 * organize the retries at drm level. There EBUSY should
1008 * also take care for 1ms wait before retrying.
1009 * That aux retries re-org is still needed and after that is
1010 * merged we remove this sleep from here.
1012 usleep_range(1000, 1500);
1017 if (recv_bytes
> recv_size
)
1018 recv_bytes
= recv_size
;
1020 for (i
= 0; i
< recv_bytes
; i
+= 4)
1021 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1022 recv
+ i
, recv_bytes
- i
);
1026 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1029 edp_panel_vdd_off(intel_dp
, false);
1031 pps_unlock(intel_dp
);
1036 #define BARE_ADDRESS_SIZE 3
1037 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1039 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1041 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1042 uint8_t txbuf
[20], rxbuf
[20];
1043 size_t txsize
, rxsize
;
1046 txbuf
[0] = (msg
->request
<< 4) |
1047 ((msg
->address
>> 16) & 0xf);
1048 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1049 txbuf
[2] = msg
->address
& 0xff;
1050 txbuf
[3] = msg
->size
- 1;
1052 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1053 case DP_AUX_NATIVE_WRITE
:
1054 case DP_AUX_I2C_WRITE
:
1055 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1056 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1057 rxsize
= 2; /* 0 or 1 data bytes */
1059 if (WARN_ON(txsize
> 20))
1062 WARN_ON(!msg
->buffer
!= !msg
->size
);
1065 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1067 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1069 msg
->reply
= rxbuf
[0] >> 4;
1072 /* Number of bytes written in a short write. */
1073 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1075 /* Return payload size. */
1081 case DP_AUX_NATIVE_READ
:
1082 case DP_AUX_I2C_READ
:
1083 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1084 rxsize
= msg
->size
+ 1;
1086 if (WARN_ON(rxsize
> 20))
1089 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1091 msg
->reply
= rxbuf
[0] >> 4;
1093 * Assume happy day, and copy the data. The caller is
1094 * expected to check msg->reply before touching it.
1096 * Return payload size.
1099 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1111 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1118 return DP_AUX_CH_CTL(port
);
1121 return DP_AUX_CH_CTL(PORT_B
);
1125 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1126 enum port port
, int index
)
1132 return DP_AUX_CH_DATA(port
, index
);
1135 return DP_AUX_CH_DATA(PORT_B
, index
);
1139 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1144 return DP_AUX_CH_CTL(port
);
1148 return PCH_DP_AUX_CH_CTL(port
);
1151 return DP_AUX_CH_CTL(PORT_A
);
1155 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1156 enum port port
, int index
)
1160 return DP_AUX_CH_DATA(port
, index
);
1164 return PCH_DP_AUX_CH_DATA(port
, index
);
1167 return DP_AUX_CH_DATA(PORT_A
, index
);
1172 * On SKL we don't have Aux for port E so we rely
1173 * on VBT to set a proper alternate aux channel.
1175 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1177 const struct ddi_vbt_port_info
*info
=
1178 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1180 switch (info
->alternate_aux_channel
) {
1190 MISSING_CASE(info
->alternate_aux_channel
);
1195 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1199 port
= skl_porte_aux_port(dev_priv
);
1206 return DP_AUX_CH_CTL(port
);
1209 return DP_AUX_CH_CTL(PORT_A
);
1213 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1214 enum port port
, int index
)
1217 port
= skl_porte_aux_port(dev_priv
);
1224 return DP_AUX_CH_DATA(port
, index
);
1227 return DP_AUX_CH_DATA(PORT_A
, index
);
1231 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1234 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1235 return skl_aux_ctl_reg(dev_priv
, port
);
1236 else if (HAS_PCH_SPLIT(dev_priv
))
1237 return ilk_aux_ctl_reg(dev_priv
, port
);
1239 return g4x_aux_ctl_reg(dev_priv
, port
);
1242 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1243 enum port port
, int index
)
1245 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1246 return skl_aux_data_reg(dev_priv
, port
, index
);
1247 else if (HAS_PCH_SPLIT(dev_priv
))
1248 return ilk_aux_data_reg(dev_priv
, port
, index
);
1250 return g4x_aux_data_reg(dev_priv
, port
, index
);
1253 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1255 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1256 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1259 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1260 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1261 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1265 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1267 kfree(intel_dp
->aux
.name
);
1271 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1273 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1274 enum port port
= intel_dig_port
->port
;
1276 intel_aux_reg_init(intel_dp
);
1277 drm_dp_aux_init(&intel_dp
->aux
);
1279 /* Failure to allocate our preferred name is not critical */
1280 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1281 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1285 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1287 if (intel_dp
->num_sink_rates
) {
1288 *sink_rates
= intel_dp
->sink_rates
;
1289 return intel_dp
->num_sink_rates
;
1292 *sink_rates
= default_rates
;
1294 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1297 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1299 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1300 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1302 /* WaDisableHBR2:skl */
1303 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1306 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1307 (INTEL_INFO(dev
)->gen
>= 9))
1314 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1316 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1317 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1320 if (IS_BROXTON(dev
)) {
1321 *source_rates
= bxt_rates
;
1322 size
= ARRAY_SIZE(bxt_rates
);
1323 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1324 *source_rates
= skl_rates
;
1325 size
= ARRAY_SIZE(skl_rates
);
1327 *source_rates
= default_rates
;
1328 size
= ARRAY_SIZE(default_rates
);
1331 /* This depends on the fact that 5.4 is last value in the array */
1332 if (!intel_dp_source_supports_hbr2(intel_dp
))
1339 intel_dp_set_clock(struct intel_encoder
*encoder
,
1340 struct intel_crtc_state
*pipe_config
)
1342 struct drm_device
*dev
= encoder
->base
.dev
;
1343 const struct dp_link_dpll
*divisor
= NULL
;
1347 divisor
= gen4_dpll
;
1348 count
= ARRAY_SIZE(gen4_dpll
);
1349 } else if (HAS_PCH_SPLIT(dev
)) {
1351 count
= ARRAY_SIZE(pch_dpll
);
1352 } else if (IS_CHERRYVIEW(dev
)) {
1354 count
= ARRAY_SIZE(chv_dpll
);
1355 } else if (IS_VALLEYVIEW(dev
)) {
1357 count
= ARRAY_SIZE(vlv_dpll
);
1360 if (divisor
&& count
) {
1361 for (i
= 0; i
< count
; i
++) {
1362 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1363 pipe_config
->dpll
= divisor
[i
].dpll
;
1364 pipe_config
->clock_set
= true;
1371 static int intersect_rates(const int *source_rates
, int source_len
,
1372 const int *sink_rates
, int sink_len
,
1375 int i
= 0, j
= 0, k
= 0;
1377 while (i
< source_len
&& j
< sink_len
) {
1378 if (source_rates
[i
] == sink_rates
[j
]) {
1379 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1381 common_rates
[k
] = source_rates
[i
];
1385 } else if (source_rates
[i
] < sink_rates
[j
]) {
1394 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1397 const int *source_rates
, *sink_rates
;
1398 int source_len
, sink_len
;
1400 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1401 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1403 return intersect_rates(source_rates
, source_len
,
1404 sink_rates
, sink_len
,
1408 static void snprintf_int_array(char *str
, size_t len
,
1409 const int *array
, int nelem
)
1415 for (i
= 0; i
< nelem
; i
++) {
1416 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1424 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1426 const int *source_rates
, *sink_rates
;
1427 int source_len
, sink_len
, common_len
;
1428 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1429 char str
[128]; /* FIXME: too big for stack? */
1431 if ((drm_debug
& DRM_UT_KMS
) == 0)
1434 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1435 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1436 DRM_DEBUG_KMS("source rates: %s\n", str
);
1438 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1439 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1440 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1442 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1443 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1444 DRM_DEBUG_KMS("common rates: %s\n", str
);
1447 static void intel_dp_print_hw_revision(struct intel_dp
*intel_dp
)
1452 if ((drm_debug
& DRM_UT_KMS
) == 0)
1455 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1456 DP_DWN_STRM_PORT_PRESENT
))
1459 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_HW_REV
, &rev
, 1);
1463 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev
& 0xf0) >> 4, rev
& 0xf);
1466 static void intel_dp_print_sw_revision(struct intel_dp
*intel_dp
)
1471 if ((drm_debug
& DRM_UT_KMS
) == 0)
1474 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1475 DP_DWN_STRM_PORT_PRESENT
))
1478 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_SW_REV
, &rev
, 2);
1482 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev
[0], rev
[1]);
1485 static int rate_to_index(int find
, const int *rates
)
1489 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1490 if (find
== rates
[i
])
1497 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1499 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1502 len
= intel_dp_common_rates(intel_dp
, rates
);
1503 if (WARN_ON(len
<= 0))
1506 return rates
[len
- 1];
1509 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1511 return rate_to_index(rate
, intel_dp
->sink_rates
);
1514 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1515 uint8_t *link_bw
, uint8_t *rate_select
)
1517 if (intel_dp
->num_sink_rates
) {
1520 intel_dp_rate_select(intel_dp
, port_clock
);
1522 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1527 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1528 struct intel_crtc_state
*pipe_config
)
1532 bpp
= pipe_config
->pipe_bpp
;
1533 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1536 bpp
= min(bpp
, 3*bpc
);
1542 intel_dp_compute_config(struct intel_encoder
*encoder
,
1543 struct intel_crtc_state
*pipe_config
,
1544 struct drm_connector_state
*conn_state
)
1546 struct drm_device
*dev
= encoder
->base
.dev
;
1547 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1548 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1549 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1550 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1551 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1552 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1553 int lane_count
, clock
;
1554 int min_lane_count
= 1;
1555 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1556 /* Conveniently, the link BW constants become indices with a shift...*/
1560 int link_avail
, link_clock
;
1561 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1563 uint8_t link_bw
, rate_select
;
1565 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1567 /* No common link rates between source and sink */
1568 WARN_ON(common_len
<= 0);
1570 max_clock
= common_len
- 1;
1572 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1573 pipe_config
->has_pch_encoder
= true;
1575 pipe_config
->has_drrs
= false;
1576 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1578 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1579 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1582 if (INTEL_INFO(dev
)->gen
>= 9) {
1584 ret
= skl_update_scaler_crtc(pipe_config
);
1589 if (HAS_GMCH_DISPLAY(dev
))
1590 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1591 intel_connector
->panel
.fitting_mode
);
1593 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1594 intel_connector
->panel
.fitting_mode
);
1597 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1600 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1601 "max bw %d pixel clock %iKHz\n",
1602 max_lane_count
, common_rates
[max_clock
],
1603 adjusted_mode
->crtc_clock
);
1605 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1606 * bpc in between. */
1607 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1608 if (is_edp(intel_dp
)) {
1610 /* Get bpp from vbt only for panels that dont have bpp in edid */
1611 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1612 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1613 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1614 dev_priv
->vbt
.edp
.bpp
);
1615 bpp
= dev_priv
->vbt
.edp
.bpp
;
1619 * Use the maximum clock and number of lanes the eDP panel
1620 * advertizes being capable of. The panels are generally
1621 * designed to support only a single clock and lane
1622 * configuration, and typically these values correspond to the
1623 * native resolution of the panel.
1625 min_lane_count
= max_lane_count
;
1626 min_clock
= max_clock
;
1629 for (; bpp
>= 6*3; bpp
-= 2*3) {
1630 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1633 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1634 for (lane_count
= min_lane_count
;
1635 lane_count
<= max_lane_count
;
1638 link_clock
= common_rates
[clock
];
1639 link_avail
= intel_dp_max_data_rate(link_clock
,
1642 if (mode_rate
<= link_avail
) {
1652 if (intel_dp
->color_range_auto
) {
1655 * CEA-861-E - 5.1 Default Encoding Parameters
1656 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1658 pipe_config
->limited_color_range
=
1659 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1661 pipe_config
->limited_color_range
=
1662 intel_dp
->limited_color_range
;
1665 pipe_config
->lane_count
= lane_count
;
1667 pipe_config
->pipe_bpp
= bpp
;
1668 pipe_config
->port_clock
= common_rates
[clock
];
1670 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1671 &link_bw
, &rate_select
);
1673 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1674 link_bw
, rate_select
, pipe_config
->lane_count
,
1675 pipe_config
->port_clock
, bpp
);
1676 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1677 mode_rate
, link_avail
);
1679 intel_link_compute_m_n(bpp
, lane_count
,
1680 adjusted_mode
->crtc_clock
,
1681 pipe_config
->port_clock
,
1682 &pipe_config
->dp_m_n
);
1684 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1685 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1686 pipe_config
->has_drrs
= true;
1687 intel_link_compute_m_n(bpp
, lane_count
,
1688 intel_connector
->panel
.downclock_mode
->clock
,
1689 pipe_config
->port_clock
,
1690 &pipe_config
->dp_m2_n2
);
1694 * DPLL0 VCO may need to be adjusted to get the correct
1695 * clock for eDP. This will affect cdclk as well.
1697 if (is_edp(intel_dp
) &&
1698 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1701 switch (pipe_config
->port_clock
/ 2) {
1711 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1715 intel_dp_set_clock(encoder
, pipe_config
);
1720 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1721 int link_rate
, uint8_t lane_count
,
1724 intel_dp
->link_rate
= link_rate
;
1725 intel_dp
->lane_count
= lane_count
;
1726 intel_dp
->link_mst
= link_mst
;
1729 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1730 struct intel_crtc_state
*pipe_config
)
1732 struct drm_device
*dev
= encoder
->base
.dev
;
1733 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1734 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1735 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1736 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1737 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1739 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1740 pipe_config
->lane_count
,
1741 intel_crtc_has_type(pipe_config
,
1742 INTEL_OUTPUT_DP_MST
));
1745 * There are four kinds of DP registers:
1752 * IBX PCH and CPU are the same for almost everything,
1753 * except that the CPU DP PLL is configured in this
1756 * CPT PCH is quite different, having many bits moved
1757 * to the TRANS_DP_CTL register instead. That
1758 * configuration happens (oddly) in ironlake_pch_enable
1761 /* Preserve the BIOS-computed detected bit. This is
1762 * supposed to be read-only.
1764 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1766 /* Handle DP bits in common between all three register formats */
1767 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1768 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1770 /* Split out the IBX/CPU vs CPT settings */
1772 if (IS_GEN7(dev
) && port
== PORT_A
) {
1773 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1774 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1775 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1776 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1777 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1779 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1780 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1782 intel_dp
->DP
|= crtc
->pipe
<< 29;
1783 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1786 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1788 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1789 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1790 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1792 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1793 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1795 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1796 !IS_CHERRYVIEW(dev
) && pipe_config
->limited_color_range
)
1797 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1799 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1800 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1801 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1802 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1803 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1805 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1806 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1808 if (IS_CHERRYVIEW(dev
))
1809 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1810 else if (crtc
->pipe
== PIPE_B
)
1811 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1815 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1816 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1818 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1819 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1821 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1822 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1824 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1825 struct intel_dp
*intel_dp
);
1827 static void wait_panel_status(struct intel_dp
*intel_dp
,
1831 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1832 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1833 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1835 lockdep_assert_held(&dev_priv
->pps_mutex
);
1837 intel_pps_verify_state(dev_priv
, intel_dp
);
1839 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1840 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1842 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1844 I915_READ(pp_stat_reg
),
1845 I915_READ(pp_ctrl_reg
));
1847 if (intel_wait_for_register(dev_priv
,
1848 pp_stat_reg
, mask
, value
,
1850 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1851 I915_READ(pp_stat_reg
),
1852 I915_READ(pp_ctrl_reg
));
1854 DRM_DEBUG_KMS("Wait complete\n");
1857 static void wait_panel_on(struct intel_dp
*intel_dp
)
1859 DRM_DEBUG_KMS("Wait for panel power on\n");
1860 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1863 static void wait_panel_off(struct intel_dp
*intel_dp
)
1865 DRM_DEBUG_KMS("Wait for panel power off time\n");
1866 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1869 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1871 ktime_t panel_power_on_time
;
1872 s64 panel_power_off_duration
;
1874 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1876 /* take the difference of currrent time and panel power off time
1877 * and then make panel wait for t11_t12 if needed. */
1878 panel_power_on_time
= ktime_get_boottime();
1879 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1881 /* When we disable the VDD override bit last we have to do the manual
1883 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1884 wait_remaining_ms_from_jiffies(jiffies
,
1885 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1887 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1890 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1892 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1893 intel_dp
->backlight_on_delay
);
1896 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1898 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1899 intel_dp
->backlight_off_delay
);
1902 /* Read the current pp_control value, unlocking the register if it
1906 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1908 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1909 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1912 lockdep_assert_held(&dev_priv
->pps_mutex
);
1914 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1915 if (WARN_ON(!HAS_DDI(dev_priv
) &&
1916 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
1917 control
&= ~PANEL_UNLOCK_MASK
;
1918 control
|= PANEL_UNLOCK_REGS
;
1924 * Must be paired with edp_panel_vdd_off().
1925 * Must hold pps_mutex around the whole on/off sequence.
1926 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1928 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1930 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1931 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1932 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1933 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1934 enum intel_display_power_domain power_domain
;
1936 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1937 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1939 lockdep_assert_held(&dev_priv
->pps_mutex
);
1941 if (!is_edp(intel_dp
))
1944 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1945 intel_dp
->want_panel_vdd
= true;
1947 if (edp_have_panel_vdd(intel_dp
))
1948 return need_to_disable
;
1950 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1951 intel_display_power_get(dev_priv
, power_domain
);
1953 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1954 port_name(intel_dig_port
->port
));
1956 if (!edp_have_panel_power(intel_dp
))
1957 wait_panel_power_cycle(intel_dp
);
1959 pp
= ironlake_get_pp_control(intel_dp
);
1960 pp
|= EDP_FORCE_VDD
;
1962 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1963 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1965 I915_WRITE(pp_ctrl_reg
, pp
);
1966 POSTING_READ(pp_ctrl_reg
);
1967 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1968 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1970 * If the panel wasn't on, delay before accessing aux channel
1972 if (!edp_have_panel_power(intel_dp
)) {
1973 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1974 port_name(intel_dig_port
->port
));
1975 msleep(intel_dp
->panel_power_up_delay
);
1978 return need_to_disable
;
1982 * Must be paired with intel_edp_panel_vdd_off() or
1983 * intel_edp_panel_off().
1984 * Nested calls to these functions are not allowed since
1985 * we drop the lock. Caller must use some higher level
1986 * locking to prevent nested calls from other threads.
1988 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1992 if (!is_edp(intel_dp
))
1996 vdd
= edp_panel_vdd_on(intel_dp
);
1997 pps_unlock(intel_dp
);
1999 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2000 port_name(dp_to_dig_port(intel_dp
)->port
));
2003 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2005 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2006 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2007 struct intel_digital_port
*intel_dig_port
=
2008 dp_to_dig_port(intel_dp
);
2009 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2010 enum intel_display_power_domain power_domain
;
2012 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2014 lockdep_assert_held(&dev_priv
->pps_mutex
);
2016 WARN_ON(intel_dp
->want_panel_vdd
);
2018 if (!edp_have_panel_vdd(intel_dp
))
2021 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2022 port_name(intel_dig_port
->port
));
2024 pp
= ironlake_get_pp_control(intel_dp
);
2025 pp
&= ~EDP_FORCE_VDD
;
2027 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2028 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2030 I915_WRITE(pp_ctrl_reg
, pp
);
2031 POSTING_READ(pp_ctrl_reg
);
2033 /* Make sure sequencer is idle before allowing subsequent activity */
2034 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2035 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2037 if ((pp
& PANEL_POWER_ON
) == 0)
2038 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2040 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2041 intel_display_power_put(dev_priv
, power_domain
);
2044 static void edp_panel_vdd_work(struct work_struct
*__work
)
2046 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2047 struct intel_dp
, panel_vdd_work
);
2050 if (!intel_dp
->want_panel_vdd
)
2051 edp_panel_vdd_off_sync(intel_dp
);
2052 pps_unlock(intel_dp
);
2055 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2057 unsigned long delay
;
2060 * Queue the timer to fire a long time from now (relative to the power
2061 * down delay) to keep the panel power up across a sequence of
2064 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2065 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2069 * Must be paired with edp_panel_vdd_on().
2070 * Must hold pps_mutex around the whole on/off sequence.
2071 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2073 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2075 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2077 lockdep_assert_held(&dev_priv
->pps_mutex
);
2079 if (!is_edp(intel_dp
))
2082 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2083 port_name(dp_to_dig_port(intel_dp
)->port
));
2085 intel_dp
->want_panel_vdd
= false;
2088 edp_panel_vdd_off_sync(intel_dp
);
2090 edp_panel_vdd_schedule_off(intel_dp
);
2093 static void edp_panel_on(struct intel_dp
*intel_dp
)
2095 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2096 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2098 i915_reg_t pp_ctrl_reg
;
2100 lockdep_assert_held(&dev_priv
->pps_mutex
);
2102 if (!is_edp(intel_dp
))
2105 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2106 port_name(dp_to_dig_port(intel_dp
)->port
));
2108 if (WARN(edp_have_panel_power(intel_dp
),
2109 "eDP port %c panel power already on\n",
2110 port_name(dp_to_dig_port(intel_dp
)->port
)))
2113 wait_panel_power_cycle(intel_dp
);
2115 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2116 pp
= ironlake_get_pp_control(intel_dp
);
2118 /* ILK workaround: disable reset around power sequence */
2119 pp
&= ~PANEL_POWER_RESET
;
2120 I915_WRITE(pp_ctrl_reg
, pp
);
2121 POSTING_READ(pp_ctrl_reg
);
2124 pp
|= PANEL_POWER_ON
;
2126 pp
|= PANEL_POWER_RESET
;
2128 I915_WRITE(pp_ctrl_reg
, pp
);
2129 POSTING_READ(pp_ctrl_reg
);
2131 wait_panel_on(intel_dp
);
2132 intel_dp
->last_power_on
= jiffies
;
2135 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2136 I915_WRITE(pp_ctrl_reg
, pp
);
2137 POSTING_READ(pp_ctrl_reg
);
2141 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2143 if (!is_edp(intel_dp
))
2147 edp_panel_on(intel_dp
);
2148 pps_unlock(intel_dp
);
2152 static void edp_panel_off(struct intel_dp
*intel_dp
)
2154 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2155 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2156 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2157 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2158 enum intel_display_power_domain power_domain
;
2160 i915_reg_t pp_ctrl_reg
;
2162 lockdep_assert_held(&dev_priv
->pps_mutex
);
2164 if (!is_edp(intel_dp
))
2167 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2168 port_name(dp_to_dig_port(intel_dp
)->port
));
2170 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2171 port_name(dp_to_dig_port(intel_dp
)->port
));
2173 pp
= ironlake_get_pp_control(intel_dp
);
2174 /* We need to switch off panel power _and_ force vdd, for otherwise some
2175 * panels get very unhappy and cease to work. */
2176 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2179 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2181 intel_dp
->want_panel_vdd
= false;
2183 I915_WRITE(pp_ctrl_reg
, pp
);
2184 POSTING_READ(pp_ctrl_reg
);
2186 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2187 wait_panel_off(intel_dp
);
2189 /* We got a reference when we enabled the VDD. */
2190 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2191 intel_display_power_put(dev_priv
, power_domain
);
2194 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2196 if (!is_edp(intel_dp
))
2200 edp_panel_off(intel_dp
);
2201 pps_unlock(intel_dp
);
2204 /* Enable backlight in the panel power control. */
2205 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2207 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2208 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2209 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2211 i915_reg_t pp_ctrl_reg
;
2214 * If we enable the backlight right away following a panel power
2215 * on, we may see slight flicker as the panel syncs with the eDP
2216 * link. So delay a bit to make sure the image is solid before
2217 * allowing it to appear.
2219 wait_backlight_on(intel_dp
);
2223 pp
= ironlake_get_pp_control(intel_dp
);
2224 pp
|= EDP_BLC_ENABLE
;
2226 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2228 I915_WRITE(pp_ctrl_reg
, pp
);
2229 POSTING_READ(pp_ctrl_reg
);
2231 pps_unlock(intel_dp
);
2234 /* Enable backlight PWM and backlight PP control. */
2235 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2237 if (!is_edp(intel_dp
))
2240 DRM_DEBUG_KMS("\n");
2242 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2243 _intel_edp_backlight_on(intel_dp
);
2246 /* Disable backlight in the panel power control. */
2247 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2249 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2250 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2252 i915_reg_t pp_ctrl_reg
;
2254 if (!is_edp(intel_dp
))
2259 pp
= ironlake_get_pp_control(intel_dp
);
2260 pp
&= ~EDP_BLC_ENABLE
;
2262 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2264 I915_WRITE(pp_ctrl_reg
, pp
);
2265 POSTING_READ(pp_ctrl_reg
);
2267 pps_unlock(intel_dp
);
2269 intel_dp
->last_backlight_off
= jiffies
;
2270 edp_wait_backlight_off(intel_dp
);
2273 /* Disable backlight PP control and backlight PWM. */
2274 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2276 if (!is_edp(intel_dp
))
2279 DRM_DEBUG_KMS("\n");
2281 _intel_edp_backlight_off(intel_dp
);
2282 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2286 * Hook for controlling the panel power control backlight through the bl_power
2287 * sysfs attribute. Take care to handle multiple calls.
2289 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2292 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2296 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2297 pps_unlock(intel_dp
);
2299 if (is_enabled
== enable
)
2302 DRM_DEBUG_KMS("panel power control backlight %s\n",
2303 enable
? "enable" : "disable");
2306 _intel_edp_backlight_on(intel_dp
);
2308 _intel_edp_backlight_off(intel_dp
);
2311 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2313 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2314 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2315 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2317 I915_STATE_WARN(cur_state
!= state
,
2318 "DP port %c state assertion failure (expected %s, current %s)\n",
2319 port_name(dig_port
->port
),
2320 onoff(state
), onoff(cur_state
));
2322 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2324 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2326 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2328 I915_STATE_WARN(cur_state
!= state
,
2329 "eDP PLL state assertion failure (expected %s, current %s)\n",
2330 onoff(state
), onoff(cur_state
));
2332 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2333 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2335 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2336 struct intel_crtc_state
*pipe_config
)
2338 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2339 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2341 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2342 assert_dp_port_disabled(intel_dp
);
2343 assert_edp_pll_disabled(dev_priv
);
2345 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2346 pipe_config
->port_clock
);
2348 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2350 if (pipe_config
->port_clock
== 162000)
2351 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2353 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2355 I915_WRITE(DP_A
, intel_dp
->DP
);
2360 * [DevILK] Work around required when enabling DP PLL
2361 * while a pipe is enabled going to FDI:
2362 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2363 * 2. Program DP PLL enable
2365 if (IS_GEN5(dev_priv
))
2366 intel_wait_for_vblank_if_active(&dev_priv
->drm
, !crtc
->pipe
);
2368 intel_dp
->DP
|= DP_PLL_ENABLE
;
2370 I915_WRITE(DP_A
, intel_dp
->DP
);
2375 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2377 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2378 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2379 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2381 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2382 assert_dp_port_disabled(intel_dp
);
2383 assert_edp_pll_enabled(dev_priv
);
2385 DRM_DEBUG_KMS("disabling eDP PLL\n");
2387 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2389 I915_WRITE(DP_A
, intel_dp
->DP
);
2394 /* If the sink supports it, try to set the power state appropriately */
2395 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2399 /* Should have a valid DPCD by this point */
2400 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2403 if (mode
!= DRM_MODE_DPMS_ON
) {
2404 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2408 * When turning on, we need to retry for 1ms to give the sink
2411 for (i
= 0; i
< 3; i
++) {
2412 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2421 DRM_DEBUG_KMS("failed to %s sink power state\n",
2422 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2425 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2428 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2429 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2430 struct drm_device
*dev
= encoder
->base
.dev
;
2431 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2432 enum intel_display_power_domain power_domain
;
2436 power_domain
= intel_display_port_power_domain(encoder
);
2437 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2442 tmp
= I915_READ(intel_dp
->output_reg
);
2444 if (!(tmp
& DP_PORT_EN
))
2447 if (IS_GEN7(dev
) && port
== PORT_A
) {
2448 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2449 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2452 for_each_pipe(dev_priv
, p
) {
2453 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2454 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2462 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2463 i915_mmio_reg_offset(intel_dp
->output_reg
));
2464 } else if (IS_CHERRYVIEW(dev
)) {
2465 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2467 *pipe
= PORT_TO_PIPE(tmp
);
2473 intel_display_power_put(dev_priv
, power_domain
);
2478 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2479 struct intel_crtc_state
*pipe_config
)
2481 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2483 struct drm_device
*dev
= encoder
->base
.dev
;
2484 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2485 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2486 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2488 tmp
= I915_READ(intel_dp
->output_reg
);
2490 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2492 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2493 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2495 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2496 flags
|= DRM_MODE_FLAG_PHSYNC
;
2498 flags
|= DRM_MODE_FLAG_NHSYNC
;
2500 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2501 flags
|= DRM_MODE_FLAG_PVSYNC
;
2503 flags
|= DRM_MODE_FLAG_NVSYNC
;
2505 if (tmp
& DP_SYNC_HS_HIGH
)
2506 flags
|= DRM_MODE_FLAG_PHSYNC
;
2508 flags
|= DRM_MODE_FLAG_NHSYNC
;
2510 if (tmp
& DP_SYNC_VS_HIGH
)
2511 flags
|= DRM_MODE_FLAG_PVSYNC
;
2513 flags
|= DRM_MODE_FLAG_NVSYNC
;
2516 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2518 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2519 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2520 pipe_config
->limited_color_range
= true;
2522 pipe_config
->lane_count
=
2523 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2525 intel_dp_get_m_n(crtc
, pipe_config
);
2527 if (port
== PORT_A
) {
2528 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2529 pipe_config
->port_clock
= 162000;
2531 pipe_config
->port_clock
= 270000;
2534 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2535 intel_dotclock_calculate(pipe_config
->port_clock
,
2536 &pipe_config
->dp_m_n
);
2538 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2539 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2541 * This is a big fat ugly hack.
2543 * Some machines in UEFI boot mode provide us a VBT that has 18
2544 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2545 * unknown we fail to light up. Yet the same BIOS boots up with
2546 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2547 * max, not what it tells us to use.
2549 * Note: This will still be broken if the eDP panel is not lit
2550 * up by the BIOS, and thus we can't get the mode at module
2553 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2554 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2555 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2559 static void intel_disable_dp(struct intel_encoder
*encoder
,
2560 struct intel_crtc_state
*old_crtc_state
,
2561 struct drm_connector_state
*old_conn_state
)
2563 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2564 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2566 if (old_crtc_state
->has_audio
)
2567 intel_audio_codec_disable(encoder
);
2569 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2570 intel_psr_disable(intel_dp
);
2572 /* Make sure the panel is off before trying to change the mode. But also
2573 * ensure that we have vdd while we switch off the panel. */
2574 intel_edp_panel_vdd_on(intel_dp
);
2575 intel_edp_backlight_off(intel_dp
);
2576 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2577 intel_edp_panel_off(intel_dp
);
2579 /* disable the port before the pipe on g4x */
2580 if (INTEL_GEN(dev_priv
) < 5)
2581 intel_dp_link_down(intel_dp
);
2584 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2585 struct intel_crtc_state
*old_crtc_state
,
2586 struct drm_connector_state
*old_conn_state
)
2588 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2589 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2591 intel_dp_link_down(intel_dp
);
2593 /* Only ilk+ has port A */
2595 ironlake_edp_pll_off(intel_dp
);
2598 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2599 struct intel_crtc_state
*old_crtc_state
,
2600 struct drm_connector_state
*old_conn_state
)
2602 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2604 intel_dp_link_down(intel_dp
);
2607 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2608 struct intel_crtc_state
*old_crtc_state
,
2609 struct drm_connector_state
*old_conn_state
)
2611 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2612 struct drm_device
*dev
= encoder
->base
.dev
;
2613 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2615 intel_dp_link_down(intel_dp
);
2617 mutex_lock(&dev_priv
->sb_lock
);
2619 /* Assert data lane reset */
2620 chv_data_lane_soft_reset(encoder
, true);
2622 mutex_unlock(&dev_priv
->sb_lock
);
2626 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2628 uint8_t dp_train_pat
)
2630 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2631 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2632 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2633 enum port port
= intel_dig_port
->port
;
2635 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2636 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2637 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2640 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2642 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2643 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2645 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2647 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2648 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2649 case DP_TRAINING_PATTERN_DISABLE
:
2650 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2653 case DP_TRAINING_PATTERN_1
:
2654 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2656 case DP_TRAINING_PATTERN_2
:
2657 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2659 case DP_TRAINING_PATTERN_3
:
2660 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2663 I915_WRITE(DP_TP_CTL(port
), temp
);
2665 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2666 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2667 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2669 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2670 case DP_TRAINING_PATTERN_DISABLE
:
2671 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2673 case DP_TRAINING_PATTERN_1
:
2674 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2676 case DP_TRAINING_PATTERN_2
:
2677 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2679 case DP_TRAINING_PATTERN_3
:
2680 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2681 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2686 if (IS_CHERRYVIEW(dev
))
2687 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2689 *DP
&= ~DP_LINK_TRAIN_MASK
;
2691 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2692 case DP_TRAINING_PATTERN_DISABLE
:
2693 *DP
|= DP_LINK_TRAIN_OFF
;
2695 case DP_TRAINING_PATTERN_1
:
2696 *DP
|= DP_LINK_TRAIN_PAT_1
;
2698 case DP_TRAINING_PATTERN_2
:
2699 *DP
|= DP_LINK_TRAIN_PAT_2
;
2701 case DP_TRAINING_PATTERN_3
:
2702 if (IS_CHERRYVIEW(dev
)) {
2703 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2705 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2706 *DP
|= DP_LINK_TRAIN_PAT_2
;
2713 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2714 struct intel_crtc_state
*old_crtc_state
)
2716 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2717 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2719 /* enable with pattern 1 (as per spec) */
2721 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2724 * Magic for VLV/CHV. We _must_ first set up the register
2725 * without actually enabling the port, and then do another
2726 * write to enable the port. Otherwise link training will
2727 * fail when the power sequencer is freshly used for this port.
2729 intel_dp
->DP
|= DP_PORT_EN
;
2730 if (old_crtc_state
->has_audio
)
2731 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2733 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2734 POSTING_READ(intel_dp
->output_reg
);
2737 static void intel_enable_dp(struct intel_encoder
*encoder
,
2738 struct intel_crtc_state
*pipe_config
)
2740 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2741 struct drm_device
*dev
= encoder
->base
.dev
;
2742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2743 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2744 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2745 enum pipe pipe
= crtc
->pipe
;
2747 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2752 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2753 vlv_init_panel_power_sequencer(intel_dp
);
2755 intel_dp_enable_port(intel_dp
, pipe_config
);
2757 edp_panel_vdd_on(intel_dp
);
2758 edp_panel_on(intel_dp
);
2759 edp_panel_vdd_off(intel_dp
, true);
2761 pps_unlock(intel_dp
);
2763 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2764 unsigned int lane_mask
= 0x0;
2766 if (IS_CHERRYVIEW(dev
))
2767 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2769 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2773 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2774 intel_dp_start_link_train(intel_dp
);
2775 intel_dp_stop_link_train(intel_dp
);
2777 if (pipe_config
->has_audio
) {
2778 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2780 intel_audio_codec_enable(encoder
);
2784 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2785 struct intel_crtc_state
*pipe_config
,
2786 struct drm_connector_state
*conn_state
)
2788 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2790 intel_enable_dp(encoder
, pipe_config
);
2791 intel_edp_backlight_on(intel_dp
);
2794 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2795 struct intel_crtc_state
*pipe_config
,
2796 struct drm_connector_state
*conn_state
)
2798 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2800 intel_edp_backlight_on(intel_dp
);
2801 intel_psr_enable(intel_dp
);
2804 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2805 struct intel_crtc_state
*pipe_config
,
2806 struct drm_connector_state
*conn_state
)
2808 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2809 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2811 intel_dp_prepare(encoder
, pipe_config
);
2813 /* Only ilk+ has port A */
2815 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2818 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2820 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2821 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2822 enum pipe pipe
= intel_dp
->pps_pipe
;
2823 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2825 edp_panel_vdd_off_sync(intel_dp
);
2828 * VLV seems to get confused when multiple power seqeuencers
2829 * have the same port selected (even if only one has power/vdd
2830 * enabled). The failure manifests as vlv_wait_port_ready() failing
2831 * CHV on the other hand doesn't seem to mind having the same port
2832 * selected in multiple power seqeuencers, but let's clear the
2833 * port select always when logically disconnecting a power sequencer
2836 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2837 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2838 I915_WRITE(pp_on_reg
, 0);
2839 POSTING_READ(pp_on_reg
);
2841 intel_dp
->pps_pipe
= INVALID_PIPE
;
2844 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2847 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2848 struct intel_encoder
*encoder
;
2850 lockdep_assert_held(&dev_priv
->pps_mutex
);
2852 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2855 for_each_intel_encoder(dev
, encoder
) {
2856 struct intel_dp
*intel_dp
;
2859 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2862 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2863 port
= dp_to_dig_port(intel_dp
)->port
;
2865 if (intel_dp
->pps_pipe
!= pipe
)
2868 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2869 pipe_name(pipe
), port_name(port
));
2871 WARN(encoder
->base
.crtc
,
2872 "stealing pipe %c power sequencer from active eDP port %c\n",
2873 pipe_name(pipe
), port_name(port
));
2875 /* make sure vdd is off before we steal it */
2876 vlv_detach_power_sequencer(intel_dp
);
2880 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2882 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2883 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2884 struct drm_device
*dev
= encoder
->base
.dev
;
2885 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2886 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2888 lockdep_assert_held(&dev_priv
->pps_mutex
);
2890 if (!is_edp(intel_dp
))
2893 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2897 * If another power sequencer was being used on this
2898 * port previously make sure to turn off vdd there while
2899 * we still have control of it.
2901 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2902 vlv_detach_power_sequencer(intel_dp
);
2905 * We may be stealing the power
2906 * sequencer from another port.
2908 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2910 /* now it's all ours */
2911 intel_dp
->pps_pipe
= crtc
->pipe
;
2913 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2914 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2916 /* init power sequencer on this pipe and port */
2917 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2918 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2921 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
2922 struct intel_crtc_state
*pipe_config
,
2923 struct drm_connector_state
*conn_state
)
2925 vlv_phy_pre_encoder_enable(encoder
);
2927 intel_enable_dp(encoder
, pipe_config
);
2930 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2931 struct intel_crtc_state
*pipe_config
,
2932 struct drm_connector_state
*conn_state
)
2934 intel_dp_prepare(encoder
, pipe_config
);
2936 vlv_phy_pre_pll_enable(encoder
);
2939 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
2940 struct intel_crtc_state
*pipe_config
,
2941 struct drm_connector_state
*conn_state
)
2943 chv_phy_pre_encoder_enable(encoder
);
2945 intel_enable_dp(encoder
, pipe_config
);
2947 /* Second common lane will stay alive on its own now */
2948 chv_phy_release_cl2_override(encoder
);
2951 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2952 struct intel_crtc_state
*pipe_config
,
2953 struct drm_connector_state
*conn_state
)
2955 intel_dp_prepare(encoder
, pipe_config
);
2957 chv_phy_pre_pll_enable(encoder
);
2960 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
2961 struct intel_crtc_state
*pipe_config
,
2962 struct drm_connector_state
*conn_state
)
2964 chv_phy_post_pll_disable(encoder
);
2968 * Fetch AUX CH registers 0x202 - 0x207 which contain
2969 * link status information
2972 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2974 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2975 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2978 /* These are source-specific values. */
2980 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2982 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2983 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2984 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2986 if (IS_BROXTON(dev
))
2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2988 else if (INTEL_INFO(dev
)->gen
>= 9) {
2989 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2990 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2992 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2994 else if (IS_GEN7(dev
) && port
== PORT_A
)
2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2996 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2997 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2999 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3003 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3005 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3006 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3008 if (INTEL_INFO(dev
)->gen
>= 9) {
3009 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3011 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3017 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3019 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3021 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3022 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3026 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3028 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3031 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3033 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
3034 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3038 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3039 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3040 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3043 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3045 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3046 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3048 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3051 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3053 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3056 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3060 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3062 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3065 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3070 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3072 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3073 unsigned long demph_reg_value
, preemph_reg_value
,
3074 uniqtranscale_reg_value
;
3075 uint8_t train_set
= intel_dp
->train_set
[0];
3077 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3078 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3079 preemph_reg_value
= 0x0004000;
3080 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3082 demph_reg_value
= 0x2B405555;
3083 uniqtranscale_reg_value
= 0x552AB83A;
3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3086 demph_reg_value
= 0x2B404040;
3087 uniqtranscale_reg_value
= 0x5548B83A;
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3090 demph_reg_value
= 0x2B245555;
3091 uniqtranscale_reg_value
= 0x5560B83A;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3094 demph_reg_value
= 0x2B405555;
3095 uniqtranscale_reg_value
= 0x5598DA3A;
3101 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3102 preemph_reg_value
= 0x0002000;
3103 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3105 demph_reg_value
= 0x2B404040;
3106 uniqtranscale_reg_value
= 0x5552B83A;
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3109 demph_reg_value
= 0x2B404848;
3110 uniqtranscale_reg_value
= 0x5580B83A;
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3113 demph_reg_value
= 0x2B404040;
3114 uniqtranscale_reg_value
= 0x55ADDA3A;
3120 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3121 preemph_reg_value
= 0x0000000;
3122 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3124 demph_reg_value
= 0x2B305555;
3125 uniqtranscale_reg_value
= 0x5570B83A;
3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3128 demph_reg_value
= 0x2B2B4040;
3129 uniqtranscale_reg_value
= 0x55ADDA3A;
3135 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3136 preemph_reg_value
= 0x0006000;
3137 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3139 demph_reg_value
= 0x1B405555;
3140 uniqtranscale_reg_value
= 0x55ADDA3A;
3150 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3151 uniqtranscale_reg_value
, 0);
3156 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3158 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3159 u32 deemph_reg_value
, margin_reg_value
;
3160 bool uniq_trans_scale
= false;
3161 uint8_t train_set
= intel_dp
->train_set
[0];
3163 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3164 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3165 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3167 deemph_reg_value
= 128;
3168 margin_reg_value
= 52;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3171 deemph_reg_value
= 128;
3172 margin_reg_value
= 77;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3175 deemph_reg_value
= 128;
3176 margin_reg_value
= 102;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3179 deemph_reg_value
= 128;
3180 margin_reg_value
= 154;
3181 uniq_trans_scale
= true;
3187 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3188 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3190 deemph_reg_value
= 85;
3191 margin_reg_value
= 78;
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3194 deemph_reg_value
= 85;
3195 margin_reg_value
= 116;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3198 deemph_reg_value
= 85;
3199 margin_reg_value
= 154;
3205 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3206 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3208 deemph_reg_value
= 64;
3209 margin_reg_value
= 104;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3212 deemph_reg_value
= 64;
3213 margin_reg_value
= 154;
3219 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3220 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3222 deemph_reg_value
= 43;
3223 margin_reg_value
= 154;
3233 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3234 margin_reg_value
, uniq_trans_scale
);
3240 gen4_signal_levels(uint8_t train_set
)
3242 uint32_t signal_levels
= 0;
3244 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3247 signal_levels
|= DP_VOLTAGE_0_4
;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3250 signal_levels
|= DP_VOLTAGE_0_6
;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3253 signal_levels
|= DP_VOLTAGE_0_8
;
3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3256 signal_levels
|= DP_VOLTAGE_1_2
;
3259 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3260 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3262 signal_levels
|= DP_PRE_EMPHASIS_0
;
3264 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3265 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3267 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3268 signal_levels
|= DP_PRE_EMPHASIS_6
;
3270 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3271 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3274 return signal_levels
;
3277 /* Gen6's DP voltage swing and pre-emphasis control */
3279 gen6_edp_signal_levels(uint8_t train_set
)
3281 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3282 DP_TRAIN_PRE_EMPHASIS_MASK
);
3283 switch (signal_levels
) {
3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3286 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3288 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3291 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3294 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3297 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3299 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3300 "0x%x\n", signal_levels
);
3301 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3305 /* Gen7's DP voltage swing and pre-emphasis control */
3307 gen7_edp_signal_levels(uint8_t train_set
)
3309 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3310 DP_TRAIN_PRE_EMPHASIS_MASK
);
3311 switch (signal_levels
) {
3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3313 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3315 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3317 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3319 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3320 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3322 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3325 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3327 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3330 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3331 "0x%x\n", signal_levels
);
3332 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3337 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3339 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3340 enum port port
= intel_dig_port
->port
;
3341 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3342 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3343 uint32_t signal_levels
, mask
= 0;
3344 uint8_t train_set
= intel_dp
->train_set
[0];
3347 signal_levels
= ddi_signal_levels(intel_dp
);
3349 if (IS_BROXTON(dev
))
3352 mask
= DDI_BUF_EMP_MASK
;
3353 } else if (IS_CHERRYVIEW(dev
)) {
3354 signal_levels
= chv_signal_levels(intel_dp
);
3355 } else if (IS_VALLEYVIEW(dev
)) {
3356 signal_levels
= vlv_signal_levels(intel_dp
);
3357 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3358 signal_levels
= gen7_edp_signal_levels(train_set
);
3359 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3360 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3361 signal_levels
= gen6_edp_signal_levels(train_set
);
3362 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3364 signal_levels
= gen4_signal_levels(train_set
);
3365 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3369 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3371 DRM_DEBUG_KMS("Using vswing level %d\n",
3372 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3373 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3374 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3375 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3377 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3379 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3380 POSTING_READ(intel_dp
->output_reg
);
3384 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3385 uint8_t dp_train_pat
)
3387 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3388 struct drm_i915_private
*dev_priv
=
3389 to_i915(intel_dig_port
->base
.base
.dev
);
3391 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3393 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3394 POSTING_READ(intel_dp
->output_reg
);
3397 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3399 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3400 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3401 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3402 enum port port
= intel_dig_port
->port
;
3408 val
= I915_READ(DP_TP_CTL(port
));
3409 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3410 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3411 I915_WRITE(DP_TP_CTL(port
), val
);
3414 * On PORT_A we can have only eDP in SST mode. There the only reason
3415 * we need to set idle transmission mode is to work around a HW issue
3416 * where we enable the pipe while not in idle link-training mode.
3417 * In this case there is requirement to wait for a minimum number of
3418 * idle patterns to be sent.
3423 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3424 DP_TP_STATUS_IDLE_DONE
,
3425 DP_TP_STATUS_IDLE_DONE
,
3427 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3431 intel_dp_link_down(struct intel_dp
*intel_dp
)
3433 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3434 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3435 enum port port
= intel_dig_port
->port
;
3436 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3437 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3438 uint32_t DP
= intel_dp
->DP
;
3440 if (WARN_ON(HAS_DDI(dev
)))
3443 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3446 DRM_DEBUG_KMS("\n");
3448 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3449 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3450 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3451 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3453 if (IS_CHERRYVIEW(dev
))
3454 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3456 DP
&= ~DP_LINK_TRAIN_MASK
;
3457 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3459 I915_WRITE(intel_dp
->output_reg
, DP
);
3460 POSTING_READ(intel_dp
->output_reg
);
3462 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3463 I915_WRITE(intel_dp
->output_reg
, DP
);
3464 POSTING_READ(intel_dp
->output_reg
);
3467 * HW workaround for IBX, we need to move the port
3468 * to transcoder A after disabling it to allow the
3469 * matching HDMI port to be enabled on transcoder A.
3471 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3473 * We get CPU/PCH FIFO underruns on the other pipe when
3474 * doing the workaround. Sweep them under the rug.
3476 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3477 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3479 /* always enable with pattern 1 (as per spec) */
3480 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3481 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3482 I915_WRITE(intel_dp
->output_reg
, DP
);
3483 POSTING_READ(intel_dp
->output_reg
);
3486 I915_WRITE(intel_dp
->output_reg
, DP
);
3487 POSTING_READ(intel_dp
->output_reg
);
3489 intel_wait_for_vblank_if_active(&dev_priv
->drm
, PIPE_A
);
3490 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3491 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3494 msleep(intel_dp
->panel_power_down_delay
);
3500 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3502 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3503 sizeof(intel_dp
->dpcd
)) < 0)
3504 return false; /* aux transfer failed */
3506 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3508 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3512 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3514 struct drm_i915_private
*dev_priv
=
3515 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3517 /* this function is meant to be called only once */
3518 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3520 if (!intel_dp_read_dpcd(intel_dp
))
3523 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3524 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3525 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3527 /* Check if the panel supports PSR */
3528 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3530 sizeof(intel_dp
->psr_dpcd
));
3531 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3532 dev_priv
->psr
.sink_support
= true;
3533 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3536 if (INTEL_GEN(dev_priv
) >= 9 &&
3537 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3538 uint8_t frame_sync_cap
;
3540 dev_priv
->psr
.sink_support
= true;
3541 drm_dp_dpcd_read(&intel_dp
->aux
,
3542 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3543 &frame_sync_cap
, 1);
3544 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3545 /* PSR2 needs frame sync as well */
3546 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3547 DRM_DEBUG_KMS("PSR2 %s on sink",
3548 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3551 /* Read the eDP Display control capabilities registers */
3552 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3553 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3554 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
) ==
3555 sizeof(intel_dp
->edp_dpcd
)))
3556 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3557 intel_dp
->edp_dpcd
);
3559 /* Intermediate frequency support */
3560 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3561 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3564 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3565 sink_rates
, sizeof(sink_rates
));
3567 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3568 int val
= le16_to_cpu(sink_rates
[i
]);
3573 /* Value read is in kHz while drm clock is saved in deca-kHz */
3574 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3576 intel_dp
->num_sink_rates
= i
;
3584 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3586 if (!intel_dp_read_dpcd(intel_dp
))
3589 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3590 &intel_dp
->sink_count
, 1) < 0)
3594 * Sink count can change between short pulse hpd hence
3595 * a member variable in intel_dp will track any changes
3596 * between short pulse interrupts.
3598 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3601 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3602 * a dongle is present but no display. Unless we require to know
3603 * if a dongle is present or not, we don't need to update
3604 * downstream port information. So, an early return here saves
3605 * time from performing other operations which are not required.
3607 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3610 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3611 DP_DWN_STRM_PORT_PRESENT
))
3612 return true; /* native DP sink */
3614 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3615 return true; /* no per-port downstream info */
3617 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3618 intel_dp
->downstream_ports
,
3619 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3620 return false; /* downstream port status fetch failed */
3626 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3630 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3633 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3634 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3635 buf
[0], buf
[1], buf
[2]);
3637 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3638 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3639 buf
[0], buf
[1], buf
[2]);
3643 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3647 if (!i915
.enable_dp_mst
)
3650 if (!intel_dp
->can_mst
)
3653 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3656 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3659 return buf
[0] & DP_MST_CAP
;
3663 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3665 if (!i915
.enable_dp_mst
)
3668 if (!intel_dp
->can_mst
)
3671 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3673 if (intel_dp
->is_mst
)
3674 DRM_DEBUG_KMS("Sink is MST capable\n");
3676 DRM_DEBUG_KMS("Sink is not MST capable\n");
3678 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3682 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3684 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3685 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3686 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3692 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3693 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3698 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3699 buf
& ~DP_TEST_SINK_START
) < 0) {
3700 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3706 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3708 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3709 DP_TEST_SINK_MISC
, &buf
) < 0) {
3713 count
= buf
& DP_TEST_COUNT_MASK
;
3714 } while (--attempts
&& count
);
3716 if (attempts
== 0) {
3717 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3722 hsw_enable_ips(intel_crtc
);
3726 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3728 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3729 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3730 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3734 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3737 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3740 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3743 if (buf
& DP_TEST_SINK_START
) {
3744 ret
= intel_dp_sink_crc_stop(intel_dp
);
3749 hsw_disable_ips(intel_crtc
);
3751 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3752 buf
| DP_TEST_SINK_START
) < 0) {
3753 hsw_enable_ips(intel_crtc
);
3757 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3761 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3763 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3764 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3765 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3770 ret
= intel_dp_sink_crc_start(intel_dp
);
3775 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3777 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3778 DP_TEST_SINK_MISC
, &buf
) < 0) {
3782 count
= buf
& DP_TEST_COUNT_MASK
;
3784 } while (--attempts
&& count
== 0);
3786 if (attempts
== 0) {
3787 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3792 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3798 intel_dp_sink_crc_stop(intel_dp
);
3803 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3805 return drm_dp_dpcd_read(&intel_dp
->aux
,
3806 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3807 sink_irq_vector
, 1) == 1;
3811 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3815 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3817 sink_irq_vector
, 14);
3824 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3826 uint8_t test_result
= DP_TEST_ACK
;
3830 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3832 uint8_t test_result
= DP_TEST_NAK
;
3836 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3838 uint8_t test_result
= DP_TEST_NAK
;
3839 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3840 struct drm_connector
*connector
= &intel_connector
->base
;
3842 if (intel_connector
->detect_edid
== NULL
||
3843 connector
->edid_corrupt
||
3844 intel_dp
->aux
.i2c_defer_count
> 6) {
3845 /* Check EDID read for NACKs, DEFERs and corruption
3846 * (DP CTS 1.2 Core r1.1)
3847 * 4.2.2.4 : Failed EDID read, I2C_NAK
3848 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3849 * 4.2.2.6 : EDID corruption detected
3850 * Use failsafe mode for all cases
3852 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3853 intel_dp
->aux
.i2c_defer_count
> 0)
3854 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3855 intel_dp
->aux
.i2c_nack_count
,
3856 intel_dp
->aux
.i2c_defer_count
);
3857 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3859 struct edid
*block
= intel_connector
->detect_edid
;
3861 /* We have to write the checksum
3862 * of the last block read
3864 block
+= intel_connector
->detect_edid
->extensions
;
3866 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3867 DP_TEST_EDID_CHECKSUM
,
3870 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3872 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3873 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3876 /* Set test active flag here so userspace doesn't interrupt things */
3877 intel_dp
->compliance_test_active
= 1;
3882 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3884 uint8_t test_result
= DP_TEST_NAK
;
3888 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3890 uint8_t response
= DP_TEST_NAK
;
3894 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3896 DRM_DEBUG_KMS("Could not read test request from sink\n");
3901 case DP_TEST_LINK_TRAINING
:
3902 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3903 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3904 response
= intel_dp_autotest_link_training(intel_dp
);
3906 case DP_TEST_LINK_VIDEO_PATTERN
:
3907 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3908 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3909 response
= intel_dp_autotest_video_pattern(intel_dp
);
3911 case DP_TEST_LINK_EDID_READ
:
3912 DRM_DEBUG_KMS("EDID test requested\n");
3913 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3914 response
= intel_dp_autotest_edid(intel_dp
);
3916 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3917 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3918 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3919 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3922 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3927 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3931 DRM_DEBUG_KMS("Could not write test response to sink\n");
3935 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3939 if (intel_dp
->is_mst
) {
3944 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3948 /* check link status - esi[10] = 0x200c */
3949 if (intel_dp
->active_mst_links
&&
3950 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3951 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3952 intel_dp_start_link_train(intel_dp
);
3953 intel_dp_stop_link_train(intel_dp
);
3956 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3957 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3960 for (retry
= 0; retry
< 3; retry
++) {
3962 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3963 DP_SINK_COUNT_ESI
+1,
3970 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3972 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3980 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3981 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3982 intel_dp
->is_mst
= false;
3983 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3984 /* send a hotplug event */
3985 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3992 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3994 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3995 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3996 u8 link_status
[DP_LINK_STATUS_SIZE
];
3998 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4000 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4001 DRM_ERROR("Failed to get link status\n");
4005 if (!intel_encoder
->base
.crtc
)
4008 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4011 /* if link training is requested we should perform it always */
4012 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4013 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4014 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4015 intel_encoder
->base
.name
);
4016 intel_dp_start_link_train(intel_dp
);
4017 intel_dp_stop_link_train(intel_dp
);
4022 * According to DP spec
4025 * 2. Configure link according to Receiver Capabilities
4026 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4027 * 4. Check link status on receipt of hot-plug interrupt
4029 * intel_dp_short_pulse - handles short pulse interrupts
4030 * when full detection is not required.
4031 * Returns %true if short pulse is handled and full detection
4032 * is NOT required and %false otherwise.
4035 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4037 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4038 u8 sink_irq_vector
= 0;
4039 u8 old_sink_count
= intel_dp
->sink_count
;
4043 * Clearing compliance test variables to allow capturing
4044 * of values for next automated test request.
4046 intel_dp
->compliance_test_active
= 0;
4047 intel_dp
->compliance_test_type
= 0;
4048 intel_dp
->compliance_test_data
= 0;
4051 * Now read the DPCD to see if it's actually running
4052 * If the current value of sink count doesn't match with
4053 * the value that was stored earlier or dpcd read failed
4054 * we need to do full detection
4056 ret
= intel_dp_get_dpcd(intel_dp
);
4058 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4059 /* No need to proceed if we are going to do full detect */
4063 /* Try to read the source of the interrupt */
4064 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4065 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4066 sink_irq_vector
!= 0) {
4067 /* Clear interrupt source */
4068 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4069 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4072 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4073 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4074 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4075 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4078 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4079 intel_dp_check_link_status(intel_dp
);
4080 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4085 /* XXX this is probably wrong for multiple downstream ports */
4086 static enum drm_connector_status
4087 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4089 uint8_t *dpcd
= intel_dp
->dpcd
;
4092 if (!intel_dp_get_dpcd(intel_dp
))
4093 return connector_status_disconnected
;
4095 if (is_edp(intel_dp
))
4096 return connector_status_connected
;
4098 /* if there's no downstream port, we're done */
4099 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4100 return connector_status_connected
;
4102 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4103 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4104 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4106 return intel_dp
->sink_count
?
4107 connector_status_connected
: connector_status_disconnected
;
4110 if (intel_dp_can_mst(intel_dp
))
4111 return connector_status_connected
;
4113 /* If no HPD, poke DDC gently */
4114 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4115 return connector_status_connected
;
4117 /* Well we tried, say unknown for unreliable port types */
4118 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4119 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4120 if (type
== DP_DS_PORT_TYPE_VGA
||
4121 type
== DP_DS_PORT_TYPE_NON_EDID
)
4122 return connector_status_unknown
;
4124 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4125 DP_DWN_STRM_PORT_TYPE_MASK
;
4126 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4127 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4128 return connector_status_unknown
;
4131 /* Anything else is out of spec, warn and ignore */
4132 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4133 return connector_status_disconnected
;
4136 static enum drm_connector_status
4137 edp_detect(struct intel_dp
*intel_dp
)
4139 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4140 enum drm_connector_status status
;
4142 status
= intel_panel_detect(dev
);
4143 if (status
== connector_status_unknown
)
4144 status
= connector_status_connected
;
4149 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4150 struct intel_digital_port
*port
)
4154 switch (port
->port
) {
4158 bit
= SDE_PORTB_HOTPLUG
;
4161 bit
= SDE_PORTC_HOTPLUG
;
4164 bit
= SDE_PORTD_HOTPLUG
;
4167 MISSING_CASE(port
->port
);
4171 return I915_READ(SDEISR
) & bit
;
4174 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4175 struct intel_digital_port
*port
)
4179 switch (port
->port
) {
4183 bit
= SDE_PORTB_HOTPLUG_CPT
;
4186 bit
= SDE_PORTC_HOTPLUG_CPT
;
4189 bit
= SDE_PORTD_HOTPLUG_CPT
;
4192 bit
= SDE_PORTE_HOTPLUG_SPT
;
4195 MISSING_CASE(port
->port
);
4199 return I915_READ(SDEISR
) & bit
;
4202 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4203 struct intel_digital_port
*port
)
4207 switch (port
->port
) {
4209 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4212 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4215 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4218 MISSING_CASE(port
->port
);
4222 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4225 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4226 struct intel_digital_port
*port
)
4230 switch (port
->port
) {
4232 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4235 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4238 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4241 MISSING_CASE(port
->port
);
4245 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4248 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4249 struct intel_digital_port
*intel_dig_port
)
4251 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4255 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4258 bit
= BXT_DE_PORT_HP_DDIA
;
4261 bit
= BXT_DE_PORT_HP_DDIB
;
4264 bit
= BXT_DE_PORT_HP_DDIC
;
4271 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4275 * intel_digital_port_connected - is the specified port connected?
4276 * @dev_priv: i915 private structure
4277 * @port: the port to test
4279 * Return %true if @port is connected, %false otherwise.
4281 static bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4282 struct intel_digital_port
*port
)
4284 if (HAS_PCH_IBX(dev_priv
))
4285 return ibx_digital_port_connected(dev_priv
, port
);
4286 else if (HAS_PCH_SPLIT(dev_priv
))
4287 return cpt_digital_port_connected(dev_priv
, port
);
4288 else if (IS_BROXTON(dev_priv
))
4289 return bxt_digital_port_connected(dev_priv
, port
);
4290 else if (IS_GM45(dev_priv
))
4291 return gm45_digital_port_connected(dev_priv
, port
);
4293 return g4x_digital_port_connected(dev_priv
, port
);
4296 static struct edid
*
4297 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4299 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4301 /* use cached edid if we have one */
4302 if (intel_connector
->edid
) {
4304 if (IS_ERR(intel_connector
->edid
))
4307 return drm_edid_duplicate(intel_connector
->edid
);
4309 return drm_get_edid(&intel_connector
->base
,
4310 &intel_dp
->aux
.ddc
);
4314 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4316 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4319 intel_dp_unset_edid(intel_dp
);
4320 edid
= intel_dp_get_edid(intel_dp
);
4321 intel_connector
->detect_edid
= edid
;
4323 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4324 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4326 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4330 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4332 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4334 kfree(intel_connector
->detect_edid
);
4335 intel_connector
->detect_edid
= NULL
;
4337 intel_dp
->has_audio
= false;
4340 static enum drm_connector_status
4341 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4343 struct drm_connector
*connector
= &intel_connector
->base
;
4344 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4345 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4346 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4347 struct drm_device
*dev
= connector
->dev
;
4348 enum drm_connector_status status
;
4349 enum intel_display_power_domain power_domain
;
4350 u8 sink_irq_vector
= 0;
4352 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4353 intel_display_power_get(to_i915(dev
), power_domain
);
4355 /* Can't disconnect eDP, but you can close the lid... */
4356 if (is_edp(intel_dp
))
4357 status
= edp_detect(intel_dp
);
4358 else if (intel_digital_port_connected(to_i915(dev
),
4359 dp_to_dig_port(intel_dp
)))
4360 status
= intel_dp_detect_dpcd(intel_dp
);
4362 status
= connector_status_disconnected
;
4364 if (status
== connector_status_disconnected
) {
4365 intel_dp
->compliance_test_active
= 0;
4366 intel_dp
->compliance_test_type
= 0;
4367 intel_dp
->compliance_test_data
= 0;
4369 if (intel_dp
->is_mst
) {
4370 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4372 intel_dp
->mst_mgr
.mst_state
);
4373 intel_dp
->is_mst
= false;
4374 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4381 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4382 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4384 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4385 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4386 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4388 intel_dp_print_rates(intel_dp
);
4390 intel_dp_probe_oui(intel_dp
);
4392 intel_dp_print_hw_revision(intel_dp
);
4393 intel_dp_print_sw_revision(intel_dp
);
4395 intel_dp_configure_mst(intel_dp
);
4397 if (intel_dp
->is_mst
) {
4399 * If we are in MST mode then this connector
4400 * won't appear connected or have anything
4403 status
= connector_status_disconnected
;
4405 } else if (connector
->status
== connector_status_connected
) {
4407 * If display was connected already and is still connected
4408 * check links status, there has been known issues of
4409 * link loss triggerring long pulse!!!!
4411 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4412 intel_dp_check_link_status(intel_dp
);
4413 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4418 * Clearing NACK and defer counts to get their exact values
4419 * while reading EDID which are required by Compliance tests
4420 * 4.2.2.4 and 4.2.2.5
4422 intel_dp
->aux
.i2c_nack_count
= 0;
4423 intel_dp
->aux
.i2c_defer_count
= 0;
4425 intel_dp_set_edid(intel_dp
);
4426 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4427 status
= connector_status_connected
;
4428 intel_dp
->detect_done
= true;
4430 /* Try to read the source of the interrupt */
4431 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4432 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4433 sink_irq_vector
!= 0) {
4434 /* Clear interrupt source */
4435 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4436 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4439 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4440 intel_dp_handle_test_request(intel_dp
);
4441 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4442 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4446 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4447 intel_dp_unset_edid(intel_dp
);
4449 intel_display_power_put(to_i915(dev
), power_domain
);
4453 static enum drm_connector_status
4454 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4456 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4457 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4458 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4459 enum drm_connector_status status
= connector
->status
;
4461 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4462 connector
->base
.id
, connector
->name
);
4464 if (intel_dp
->is_mst
) {
4465 /* MST devices are disconnected from a monitor POV */
4466 intel_dp_unset_edid(intel_dp
);
4467 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4468 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4469 return connector_status_disconnected
;
4472 /* If full detect is not performed yet, do a full detect */
4473 if (!intel_dp
->detect_done
)
4474 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4476 intel_dp
->detect_done
= false;
4482 intel_dp_force(struct drm_connector
*connector
)
4484 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4485 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4486 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4487 enum intel_display_power_domain power_domain
;
4489 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4490 connector
->base
.id
, connector
->name
);
4491 intel_dp_unset_edid(intel_dp
);
4493 if (connector
->status
!= connector_status_connected
)
4496 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4497 intel_display_power_get(dev_priv
, power_domain
);
4499 intel_dp_set_edid(intel_dp
);
4501 intel_display_power_put(dev_priv
, power_domain
);
4503 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4504 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4507 static int intel_dp_get_modes(struct drm_connector
*connector
)
4509 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4512 edid
= intel_connector
->detect_edid
;
4514 int ret
= intel_connector_update_modes(connector
, edid
);
4519 /* if eDP has no EDID, fall back to fixed mode */
4520 if (is_edp(intel_attached_dp(connector
)) &&
4521 intel_connector
->panel
.fixed_mode
) {
4522 struct drm_display_mode
*mode
;
4524 mode
= drm_mode_duplicate(connector
->dev
,
4525 intel_connector
->panel
.fixed_mode
);
4527 drm_mode_probed_add(connector
, mode
);
4536 intel_dp_detect_audio(struct drm_connector
*connector
)
4538 bool has_audio
= false;
4541 edid
= to_intel_connector(connector
)->detect_edid
;
4543 has_audio
= drm_detect_monitor_audio(edid
);
4549 intel_dp_set_property(struct drm_connector
*connector
,
4550 struct drm_property
*property
,
4553 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4554 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4555 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4556 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4559 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4563 if (property
== dev_priv
->force_audio_property
) {
4567 if (i
== intel_dp
->force_audio
)
4570 intel_dp
->force_audio
= i
;
4572 if (i
== HDMI_AUDIO_AUTO
)
4573 has_audio
= intel_dp_detect_audio(connector
);
4575 has_audio
= (i
== HDMI_AUDIO_ON
);
4577 if (has_audio
== intel_dp
->has_audio
)
4580 intel_dp
->has_audio
= has_audio
;
4584 if (property
== dev_priv
->broadcast_rgb_property
) {
4585 bool old_auto
= intel_dp
->color_range_auto
;
4586 bool old_range
= intel_dp
->limited_color_range
;
4589 case INTEL_BROADCAST_RGB_AUTO
:
4590 intel_dp
->color_range_auto
= true;
4592 case INTEL_BROADCAST_RGB_FULL
:
4593 intel_dp
->color_range_auto
= false;
4594 intel_dp
->limited_color_range
= false;
4596 case INTEL_BROADCAST_RGB_LIMITED
:
4597 intel_dp
->color_range_auto
= false;
4598 intel_dp
->limited_color_range
= true;
4604 if (old_auto
== intel_dp
->color_range_auto
&&
4605 old_range
== intel_dp
->limited_color_range
)
4611 if (is_edp(intel_dp
) &&
4612 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4613 if (val
== DRM_MODE_SCALE_NONE
) {
4614 DRM_DEBUG_KMS("no scaling not supported\n");
4617 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4618 val
== DRM_MODE_SCALE_CENTER
) {
4619 DRM_DEBUG_KMS("centering not supported\n");
4623 if (intel_connector
->panel
.fitting_mode
== val
) {
4624 /* the eDP scaling property is not changed */
4627 intel_connector
->panel
.fitting_mode
= val
;
4635 if (intel_encoder
->base
.crtc
)
4636 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4642 intel_dp_connector_register(struct drm_connector
*connector
)
4644 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4647 ret
= intel_connector_register(connector
);
4651 i915_debugfs_connector_add(connector
);
4653 DRM_DEBUG_KMS("registering %s bus for %s\n",
4654 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4656 intel_dp
->aux
.dev
= connector
->kdev
;
4657 return drm_dp_aux_register(&intel_dp
->aux
);
4661 intel_dp_connector_unregister(struct drm_connector
*connector
)
4663 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4664 intel_connector_unregister(connector
);
4668 intel_dp_connector_destroy(struct drm_connector
*connector
)
4670 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4672 kfree(intel_connector
->detect_edid
);
4674 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4675 kfree(intel_connector
->edid
);
4677 /* Can't call is_edp() since the encoder may have been destroyed
4679 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4680 intel_panel_fini(&intel_connector
->panel
);
4682 drm_connector_cleanup(connector
);
4686 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4688 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4689 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4691 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4692 if (is_edp(intel_dp
)) {
4693 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4695 * vdd might still be enabled do to the delayed vdd off.
4696 * Make sure vdd is actually turned off here.
4699 edp_panel_vdd_off_sync(intel_dp
);
4700 pps_unlock(intel_dp
);
4702 if (intel_dp
->edp_notifier
.notifier_call
) {
4703 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4704 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4708 intel_dp_aux_fini(intel_dp
);
4710 drm_encoder_cleanup(encoder
);
4711 kfree(intel_dig_port
);
4714 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4716 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4718 if (!is_edp(intel_dp
))
4722 * vdd might still be enabled do to the delayed vdd off.
4723 * Make sure vdd is actually turned off here.
4725 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4727 edp_panel_vdd_off_sync(intel_dp
);
4728 pps_unlock(intel_dp
);
4731 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4733 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4734 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4735 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4736 enum intel_display_power_domain power_domain
;
4738 lockdep_assert_held(&dev_priv
->pps_mutex
);
4740 if (!edp_have_panel_vdd(intel_dp
))
4744 * The VDD bit needs a power domain reference, so if the bit is
4745 * already enabled when we boot or resume, grab this reference and
4746 * schedule a vdd off, so we don't hold on to the reference
4749 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4750 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4751 intel_display_power_get(dev_priv
, power_domain
);
4753 edp_panel_vdd_schedule_off(intel_dp
);
4756 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4758 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4759 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4761 if (!HAS_DDI(dev_priv
))
4762 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4764 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4769 /* Reinit the power sequencer, in case BIOS did something with it. */
4770 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4771 intel_edp_panel_vdd_sanitize(intel_dp
);
4773 pps_unlock(intel_dp
);
4776 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4777 .dpms
= drm_atomic_helper_connector_dpms
,
4778 .detect
= intel_dp_detect
,
4779 .force
= intel_dp_force
,
4780 .fill_modes
= drm_helper_probe_single_connector_modes
,
4781 .set_property
= intel_dp_set_property
,
4782 .atomic_get_property
= intel_connector_atomic_get_property
,
4783 .late_register
= intel_dp_connector_register
,
4784 .early_unregister
= intel_dp_connector_unregister
,
4785 .destroy
= intel_dp_connector_destroy
,
4786 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4787 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4790 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4791 .get_modes
= intel_dp_get_modes
,
4792 .mode_valid
= intel_dp_mode_valid
,
4795 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4796 .reset
= intel_dp_encoder_reset
,
4797 .destroy
= intel_dp_encoder_destroy
,
4801 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4803 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4804 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4805 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4806 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4807 enum intel_display_power_domain power_domain
;
4808 enum irqreturn ret
= IRQ_NONE
;
4810 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4811 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4812 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
4814 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4816 * vdd off can generate a long pulse on eDP which
4817 * would require vdd on to handle it, and thus we
4818 * would end up in an endless cycle of
4819 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4821 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4822 port_name(intel_dig_port
->port
));
4826 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4827 port_name(intel_dig_port
->port
),
4828 long_hpd
? "long" : "short");
4831 intel_dp
->detect_done
= false;
4835 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4836 intel_display_power_get(dev_priv
, power_domain
);
4838 if (intel_dp
->is_mst
) {
4839 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4841 * If we were in MST mode, and device is not
4842 * there, get out of MST mode
4844 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4845 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4846 intel_dp
->is_mst
= false;
4847 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4849 intel_dp
->detect_done
= false;
4854 if (!intel_dp
->is_mst
) {
4855 if (!intel_dp_short_pulse(intel_dp
)) {
4856 intel_dp
->detect_done
= false;
4864 intel_display_power_put(dev_priv
, power_domain
);
4869 /* check the VBT to see whether the eDP is on another port */
4870 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4875 * eDP not supported on g4x. so bail out early just
4876 * for a bit extra safety in case the VBT is bonkers.
4878 if (INTEL_INFO(dev
)->gen
< 5)
4884 return intel_bios_is_port_edp(dev_priv
, port
);
4888 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4890 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4892 intel_attach_force_audio_property(connector
);
4893 intel_attach_broadcast_rgb_property(connector
);
4894 intel_dp
->color_range_auto
= true;
4896 if (is_edp(intel_dp
)) {
4897 drm_mode_create_scaling_mode_property(connector
->dev
);
4898 drm_object_attach_property(
4900 connector
->dev
->mode_config
.scaling_mode_property
,
4901 DRM_MODE_SCALE_ASPECT
);
4902 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4906 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4908 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4909 intel_dp
->last_power_on
= jiffies
;
4910 intel_dp
->last_backlight_off
= jiffies
;
4914 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4915 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4917 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4918 struct pps_registers regs
;
4920 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4922 /* Workaround: Need to write PP_CONTROL with the unlock key as
4923 * the very first thing. */
4924 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4926 pp_on
= I915_READ(regs
.pp_on
);
4927 pp_off
= I915_READ(regs
.pp_off
);
4928 if (!IS_BROXTON(dev_priv
)) {
4929 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4930 pp_div
= I915_READ(regs
.pp_div
);
4933 /* Pull timing values out of registers */
4934 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4935 PANEL_POWER_UP_DELAY_SHIFT
;
4937 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4938 PANEL_LIGHT_ON_DELAY_SHIFT
;
4940 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4941 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4943 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4944 PANEL_POWER_DOWN_DELAY_SHIFT
;
4946 if (IS_BROXTON(dev_priv
)) {
4947 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4948 BXT_POWER_CYCLE_DELAY_SHIFT
;
4950 seq
->t11_t12
= (tmp
- 1) * 1000;
4954 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4955 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4960 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
4962 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4964 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
4968 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
4969 struct intel_dp
*intel_dp
)
4971 struct edp_power_seq hw
;
4972 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
4974 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
4976 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
4977 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
4978 DRM_ERROR("PPS state mismatch\n");
4979 intel_pps_dump_state("sw", sw
);
4980 intel_pps_dump_state("hw", &hw
);
4985 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4986 struct intel_dp
*intel_dp
)
4988 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4989 struct edp_power_seq cur
, vbt
, spec
,
4990 *final
= &intel_dp
->pps_delays
;
4992 lockdep_assert_held(&dev_priv
->pps_mutex
);
4994 /* already initialized? */
4995 if (final
->t11_t12
!= 0)
4998 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5000 intel_pps_dump_state("cur", &cur
);
5002 vbt
= dev_priv
->vbt
.edp
.pps
;
5004 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5005 * our hw here, which are all in 100usec. */
5006 spec
.t1_t3
= 210 * 10;
5007 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5008 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5009 spec
.t10
= 500 * 10;
5010 /* This one is special and actually in units of 100ms, but zero
5011 * based in the hw (so we need to add 100 ms). But the sw vbt
5012 * table multiplies it with 1000 to make it in units of 100usec,
5014 spec
.t11_t12
= (510 + 100) * 10;
5016 intel_pps_dump_state("vbt", &vbt
);
5018 /* Use the max of the register settings and vbt. If both are
5019 * unset, fall back to the spec limits. */
5020 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5022 max(cur.field, vbt.field))
5023 assign_final(t1_t3
);
5027 assign_final(t11_t12
);
5030 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5031 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5032 intel_dp
->backlight_on_delay
= get_delay(t8
);
5033 intel_dp
->backlight_off_delay
= get_delay(t9
);
5034 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5035 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5038 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5039 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5040 intel_dp
->panel_power_cycle_delay
);
5042 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5043 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5046 * We override the HW backlight delays to 1 because we do manual waits
5047 * on them. For T8, even BSpec recommends doing it. For T9, if we
5048 * don't do this, we'll end up waiting for the backlight off delay
5049 * twice: once when we do the manual sleep, and once when we disable
5050 * the panel and wait for the PP_STATUS bit to become zero.
5057 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5058 struct intel_dp
*intel_dp
)
5060 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5061 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5062 int div
= dev_priv
->rawclk_freq
/ 1000;
5063 struct pps_registers regs
;
5064 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5065 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5067 lockdep_assert_held(&dev_priv
->pps_mutex
);
5069 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5071 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5072 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5073 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5074 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5075 /* Compute the divisor for the pp clock, simply match the Bspec
5077 if (IS_BROXTON(dev
)) {
5078 pp_div
= I915_READ(regs
.pp_ctrl
);
5079 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5080 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5081 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5083 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5084 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5085 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5088 /* Haswell doesn't have any port selection bits for the panel
5089 * power sequencer any more. */
5090 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5091 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5092 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5094 port_sel
= PANEL_PORT_SELECT_DPA
;
5096 port_sel
= PANEL_PORT_SELECT_DPD
;
5101 I915_WRITE(regs
.pp_on
, pp_on
);
5102 I915_WRITE(regs
.pp_off
, pp_off
);
5103 if (IS_BROXTON(dev
))
5104 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5106 I915_WRITE(regs
.pp_div
, pp_div
);
5108 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5109 I915_READ(regs
.pp_on
),
5110 I915_READ(regs
.pp_off
),
5112 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5113 I915_READ(regs
.pp_div
));
5116 static void intel_dp_pps_init(struct drm_device
*dev
,
5117 struct intel_dp
*intel_dp
)
5119 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5120 vlv_initial_power_sequencer_setup(intel_dp
);
5122 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5123 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5128 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5129 * @dev_priv: i915 device
5130 * @crtc_state: a pointer to the active intel_crtc_state
5131 * @refresh_rate: RR to be programmed
5133 * This function gets called when refresh rate (RR) has to be changed from
5134 * one frequency to another. Switches can be between high and low RR
5135 * supported by the panel or to any other RR based on media playback (in
5136 * this case, RR value needs to be passed from user space).
5138 * The caller of this function needs to take a lock on dev_priv->drrs.
5140 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5141 struct intel_crtc_state
*crtc_state
,
5144 struct intel_encoder
*encoder
;
5145 struct intel_digital_port
*dig_port
= NULL
;
5146 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5148 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5150 if (refresh_rate
<= 0) {
5151 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5155 if (intel_dp
== NULL
) {
5156 DRM_DEBUG_KMS("DRRS not supported.\n");
5161 * FIXME: This needs proper synchronization with psr state for some
5162 * platforms that cannot have PSR and DRRS enabled at the same time.
5165 dig_port
= dp_to_dig_port(intel_dp
);
5166 encoder
= &dig_port
->base
;
5167 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5170 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5174 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5175 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5179 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5181 index
= DRRS_LOW_RR
;
5183 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5185 "DRRS requested for previously set RR...ignoring\n");
5189 if (!crtc_state
->base
.active
) {
5190 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5194 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5197 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5200 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5204 DRM_ERROR("Unsupported refreshrate type\n");
5206 } else if (INTEL_GEN(dev_priv
) > 6) {
5207 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5210 val
= I915_READ(reg
);
5211 if (index
> DRRS_HIGH_RR
) {
5212 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5213 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5215 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5217 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5218 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5220 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5222 I915_WRITE(reg
, val
);
5225 dev_priv
->drrs
.refresh_rate_type
= index
;
5227 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5231 * intel_edp_drrs_enable - init drrs struct if supported
5232 * @intel_dp: DP struct
5233 * @crtc_state: A pointer to the active crtc state.
5235 * Initializes frontbuffer_bits and drrs.dp
5237 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5238 struct intel_crtc_state
*crtc_state
)
5240 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5241 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5243 if (!crtc_state
->has_drrs
) {
5244 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5248 mutex_lock(&dev_priv
->drrs
.mutex
);
5249 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5250 DRM_ERROR("DRRS already enabled\n");
5254 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5256 dev_priv
->drrs
.dp
= intel_dp
;
5259 mutex_unlock(&dev_priv
->drrs
.mutex
);
5263 * intel_edp_drrs_disable - Disable DRRS
5264 * @intel_dp: DP struct
5265 * @old_crtc_state: Pointer to old crtc_state.
5268 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5269 struct intel_crtc_state
*old_crtc_state
)
5271 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5272 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5274 if (!old_crtc_state
->has_drrs
)
5277 mutex_lock(&dev_priv
->drrs
.mutex
);
5278 if (!dev_priv
->drrs
.dp
) {
5279 mutex_unlock(&dev_priv
->drrs
.mutex
);
5283 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5284 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5285 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5287 dev_priv
->drrs
.dp
= NULL
;
5288 mutex_unlock(&dev_priv
->drrs
.mutex
);
5290 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5293 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5295 struct drm_i915_private
*dev_priv
=
5296 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5297 struct intel_dp
*intel_dp
;
5299 mutex_lock(&dev_priv
->drrs
.mutex
);
5301 intel_dp
= dev_priv
->drrs
.dp
;
5307 * The delayed work can race with an invalidate hence we need to
5311 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5314 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5315 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5317 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5318 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5322 mutex_unlock(&dev_priv
->drrs
.mutex
);
5326 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5327 * @dev_priv: i915 device
5328 * @frontbuffer_bits: frontbuffer plane tracking bits
5330 * This function gets called everytime rendering on the given planes start.
5331 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5333 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5335 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5336 unsigned int frontbuffer_bits
)
5338 struct drm_crtc
*crtc
;
5341 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5344 cancel_delayed_work(&dev_priv
->drrs
.work
);
5346 mutex_lock(&dev_priv
->drrs
.mutex
);
5347 if (!dev_priv
->drrs
.dp
) {
5348 mutex_unlock(&dev_priv
->drrs
.mutex
);
5352 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5353 pipe
= to_intel_crtc(crtc
)->pipe
;
5355 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5356 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5358 /* invalidate means busy screen hence upclock */
5359 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5360 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5361 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5363 mutex_unlock(&dev_priv
->drrs
.mutex
);
5367 * intel_edp_drrs_flush - Restart Idleness DRRS
5368 * @dev_priv: i915 device
5369 * @frontbuffer_bits: frontbuffer plane tracking bits
5371 * This function gets called every time rendering on the given planes has
5372 * completed or flip on a crtc is completed. So DRRS should be upclocked
5373 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5374 * if no other planes are dirty.
5376 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5378 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5379 unsigned int frontbuffer_bits
)
5381 struct drm_crtc
*crtc
;
5384 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5387 cancel_delayed_work(&dev_priv
->drrs
.work
);
5389 mutex_lock(&dev_priv
->drrs
.mutex
);
5390 if (!dev_priv
->drrs
.dp
) {
5391 mutex_unlock(&dev_priv
->drrs
.mutex
);
5395 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5396 pipe
= to_intel_crtc(crtc
)->pipe
;
5398 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5399 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5401 /* flush means busy screen hence upclock */
5402 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5403 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5404 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5407 * flush also means no more activity hence schedule downclock, if all
5408 * other fbs are quiescent too
5410 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5411 schedule_delayed_work(&dev_priv
->drrs
.work
,
5412 msecs_to_jiffies(1000));
5413 mutex_unlock(&dev_priv
->drrs
.mutex
);
5417 * DOC: Display Refresh Rate Switching (DRRS)
5419 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5420 * which enables swtching between low and high refresh rates,
5421 * dynamically, based on the usage scenario. This feature is applicable
5422 * for internal panels.
5424 * Indication that the panel supports DRRS is given by the panel EDID, which
5425 * would list multiple refresh rates for one resolution.
5427 * DRRS is of 2 types - static and seamless.
5428 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5429 * (may appear as a blink on screen) and is used in dock-undock scenario.
5430 * Seamless DRRS involves changing RR without any visual effect to the user
5431 * and can be used during normal system usage. This is done by programming
5432 * certain registers.
5434 * Support for static/seamless DRRS may be indicated in the VBT based on
5435 * inputs from the panel spec.
5437 * DRRS saves power by switching to low RR based on usage scenarios.
5439 * The implementation is based on frontbuffer tracking implementation. When
5440 * there is a disturbance on the screen triggered by user activity or a periodic
5441 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5442 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5445 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5446 * and intel_edp_drrs_flush() are called.
5448 * DRRS can be further extended to support other internal panels and also
5449 * the scenario of video playback wherein RR is set based on the rate
5450 * requested by userspace.
5454 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5455 * @intel_connector: eDP connector
5456 * @fixed_mode: preferred mode of panel
5458 * This function is called only once at driver load to initialize basic
5462 * Downclock mode if panel supports it, else return NULL.
5463 * DRRS support is determined by the presence of downclock mode (apart
5464 * from VBT setting).
5466 static struct drm_display_mode
*
5467 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5468 struct drm_display_mode
*fixed_mode
)
5470 struct drm_connector
*connector
= &intel_connector
->base
;
5471 struct drm_device
*dev
= connector
->dev
;
5472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5473 struct drm_display_mode
*downclock_mode
= NULL
;
5475 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5476 mutex_init(&dev_priv
->drrs
.mutex
);
5478 if (INTEL_INFO(dev
)->gen
<= 6) {
5479 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5483 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5484 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5488 downclock_mode
= intel_find_panel_downclock
5489 (dev
, fixed_mode
, connector
);
5491 if (!downclock_mode
) {
5492 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5496 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5498 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5499 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5500 return downclock_mode
;
5503 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5504 struct intel_connector
*intel_connector
)
5506 struct drm_connector
*connector
= &intel_connector
->base
;
5507 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5508 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5509 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5510 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5511 struct drm_display_mode
*fixed_mode
= NULL
;
5512 struct drm_display_mode
*downclock_mode
= NULL
;
5514 struct drm_display_mode
*scan
;
5516 enum pipe pipe
= INVALID_PIPE
;
5518 if (!is_edp(intel_dp
))
5522 * On IBX/CPT we may get here with LVDS already registered. Since the
5523 * driver uses the only internal power sequencer available for both
5524 * eDP and LVDS bail out early in this case to prevent interfering
5525 * with an already powered-on LVDS power sequencer.
5527 if (intel_get_lvds_encoder(dev
)) {
5528 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5529 DRM_INFO("LVDS was detected, not registering eDP\n");
5536 intel_dp_init_panel_power_timestamps(intel_dp
);
5537 intel_dp_pps_init(dev
, intel_dp
);
5538 intel_edp_panel_vdd_sanitize(intel_dp
);
5540 pps_unlock(intel_dp
);
5542 /* Cache DPCD and EDID for edp. */
5543 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5546 /* if this fails, presume the device is a ghost */
5547 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5551 mutex_lock(&dev
->mode_config
.mutex
);
5552 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5554 if (drm_add_edid_modes(connector
, edid
)) {
5555 drm_mode_connector_update_edid_property(connector
,
5557 drm_edid_to_eld(connector
, edid
);
5560 edid
= ERR_PTR(-EINVAL
);
5563 edid
= ERR_PTR(-ENOENT
);
5565 intel_connector
->edid
= edid
;
5567 /* prefer fixed mode from EDID if available */
5568 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5569 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5570 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5571 downclock_mode
= intel_dp_drrs_init(
5572 intel_connector
, fixed_mode
);
5577 /* fallback to VBT if available for eDP */
5578 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5579 fixed_mode
= drm_mode_duplicate(dev
,
5580 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5582 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5583 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5584 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5587 mutex_unlock(&dev
->mode_config
.mutex
);
5589 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5590 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5591 register_reboot_notifier(&intel_dp
->edp_notifier
);
5594 * Figure out the current pipe for the initial backlight setup.
5595 * If the current pipe isn't valid, try the PPS pipe, and if that
5596 * fails just assume pipe A.
5598 if (IS_CHERRYVIEW(dev
))
5599 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5601 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5603 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5604 pipe
= intel_dp
->pps_pipe
;
5606 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5609 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5613 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5614 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5615 intel_panel_setup_backlight(connector
, pipe
);
5620 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5622 * vdd might still be enabled do to the delayed vdd off.
5623 * Make sure vdd is actually turned off here.
5626 edp_panel_vdd_off_sync(intel_dp
);
5627 pps_unlock(intel_dp
);
5633 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5634 struct intel_connector
*intel_connector
)
5636 struct drm_connector
*connector
= &intel_connector
->base
;
5637 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5638 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5639 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5640 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5641 enum port port
= intel_dig_port
->port
;
5644 if (WARN(intel_dig_port
->max_lanes
< 1,
5645 "Not enough lanes (%d) for DP on port %c\n",
5646 intel_dig_port
->max_lanes
, port_name(port
)))
5649 intel_dp
->pps_pipe
= INVALID_PIPE
;
5651 /* intel_dp vfuncs */
5652 if (INTEL_INFO(dev
)->gen
>= 9)
5653 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5654 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5655 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5656 else if (HAS_PCH_SPLIT(dev
))
5657 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5659 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5661 if (INTEL_INFO(dev
)->gen
>= 9)
5662 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5664 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5667 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5669 /* Preserve the current hw state. */
5670 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5671 intel_dp
->attached_connector
= intel_connector
;
5673 if (intel_dp_is_edp(dev
, port
))
5674 type
= DRM_MODE_CONNECTOR_eDP
;
5676 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5679 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5680 * for DP the encoder type can be set by the caller to
5681 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5683 if (type
== DRM_MODE_CONNECTOR_eDP
)
5684 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5686 /* eDP only on port B and/or C on vlv/chv */
5687 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5688 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5691 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5692 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5695 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5696 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5698 connector
->interlace_allowed
= true;
5699 connector
->doublescan_allowed
= 0;
5701 intel_dp_aux_init(intel_dp
);
5703 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5704 edp_panel_vdd_work
);
5706 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5709 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5711 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5713 /* Set up the hotplug pin. */
5716 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5719 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5720 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5721 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5724 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5727 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5730 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5736 /* init MST on ports that can support it */
5737 if (HAS_DP_MST(dev
) && !is_edp(intel_dp
) &&
5738 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5739 intel_dp_mst_encoder_init(intel_dig_port
,
5740 intel_connector
->base
.base
.id
);
5742 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5743 intel_dp_aux_fini(intel_dp
);
5744 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5748 intel_dp_add_properties(intel_dp
, connector
);
5750 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5751 * 0xd. Failure to do so will result in spurious interrupts being
5752 * generated on the port when a cable is not attached.
5754 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5755 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5756 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5762 drm_connector_cleanup(connector
);
5767 bool intel_dp_init(struct drm_device
*dev
,
5768 i915_reg_t output_reg
,
5771 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5772 struct intel_digital_port
*intel_dig_port
;
5773 struct intel_encoder
*intel_encoder
;
5774 struct drm_encoder
*encoder
;
5775 struct intel_connector
*intel_connector
;
5777 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5778 if (!intel_dig_port
)
5781 intel_connector
= intel_connector_alloc();
5782 if (!intel_connector
)
5783 goto err_connector_alloc
;
5785 intel_encoder
= &intel_dig_port
->base
;
5786 encoder
= &intel_encoder
->base
;
5788 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5789 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5790 goto err_encoder_init
;
5792 intel_encoder
->compute_config
= intel_dp_compute_config
;
5793 intel_encoder
->disable
= intel_disable_dp
;
5794 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5795 intel_encoder
->get_config
= intel_dp_get_config
;
5796 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5797 if (IS_CHERRYVIEW(dev
)) {
5798 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5799 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5800 intel_encoder
->enable
= vlv_enable_dp
;
5801 intel_encoder
->post_disable
= chv_post_disable_dp
;
5802 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5803 } else if (IS_VALLEYVIEW(dev
)) {
5804 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5805 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5806 intel_encoder
->enable
= vlv_enable_dp
;
5807 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5809 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5810 intel_encoder
->enable
= g4x_enable_dp
;
5811 if (INTEL_INFO(dev
)->gen
>= 5)
5812 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5815 intel_dig_port
->port
= port
;
5816 intel_dig_port
->dp
.output_reg
= output_reg
;
5817 intel_dig_port
->max_lanes
= 4;
5819 intel_encoder
->type
= INTEL_OUTPUT_DP
;
5820 if (IS_CHERRYVIEW(dev
)) {
5822 intel_encoder
->crtc_mask
= 1 << 2;
5824 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5826 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5828 intel_encoder
->cloneable
= 0;
5830 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5831 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5833 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5834 goto err_init_connector
;
5839 drm_encoder_cleanup(encoder
);
5841 kfree(intel_connector
);
5842 err_connector_alloc
:
5843 kfree(intel_dig_port
);
5847 void intel_dp_mst_suspend(struct drm_device
*dev
)
5849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5853 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5854 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5856 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5859 if (intel_dig_port
->dp
.is_mst
)
5860 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5864 void intel_dp_mst_resume(struct drm_device
*dev
)
5866 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5869 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5870 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5873 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5876 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5878 intel_dp_check_mst_status(&intel_dig_port
->dp
);