2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
196 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
197 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
198 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
199 int max_dotclk
= dev_priv
->max_dotclk_freq
;
202 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
204 if (type
!= DP_DS_PORT_TYPE_VGA
)
207 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
208 intel_dp
->downstream_ports
);
210 if (ds_max_dotclk
!= 0)
211 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
216 static enum drm_mode_status
217 intel_dp_mode_valid(struct drm_connector
*connector
,
218 struct drm_display_mode
*mode
)
220 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
222 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
223 int target_clock
= mode
->clock
;
224 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
227 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
229 if (is_edp(intel_dp
) && fixed_mode
) {
230 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
233 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
236 target_clock
= fixed_mode
->clock
;
239 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
240 max_lanes
= intel_dp_max_lane_count(intel_dp
);
242 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
243 mode_rate
= intel_dp_link_required(target_clock
, 18);
245 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
246 return MODE_CLOCK_HIGH
;
248 if (mode
->clock
< 10000)
249 return MODE_CLOCK_LOW
;
251 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
252 return MODE_H_ILLEGAL
;
257 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
264 for (i
= 0; i
< src_bytes
; i
++)
265 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
269 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
274 for (i
= 0; i
< dst_bytes
; i
++)
275 dst
[i
] = src
>> ((3-i
) * 8);
279 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
280 struct intel_dp
*intel_dp
);
282 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
283 struct intel_dp
*intel_dp
);
285 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
287 static void pps_lock(struct intel_dp
*intel_dp
)
289 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
290 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
291 struct drm_device
*dev
= encoder
->base
.dev
;
292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
293 enum intel_display_power_domain power_domain
;
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
299 power_domain
= intel_display_port_aux_power_domain(encoder
);
300 intel_display_power_get(dev_priv
, power_domain
);
302 mutex_lock(&dev_priv
->pps_mutex
);
305 static void pps_unlock(struct intel_dp
*intel_dp
)
307 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
308 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
309 struct drm_device
*dev
= encoder
->base
.dev
;
310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
311 enum intel_display_power_domain power_domain
;
313 mutex_unlock(&dev_priv
->pps_mutex
);
315 power_domain
= intel_display_port_aux_power_domain(encoder
);
316 intel_display_power_put(dev_priv
, power_domain
);
320 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
325 enum pipe pipe
= intel_dp
->pps_pipe
;
326 bool pll_enabled
, release_cl_override
= false;
327 enum dpio_phy phy
= DPIO_PHY(pipe
);
328 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
331 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
));
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
342 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
343 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
344 DP
|= DP_PORT_WIDTH(1);
345 DP
|= DP_LINK_TRAIN_PAT_1
;
347 if (IS_CHERRYVIEW(dev_priv
))
348 DP
|= DP_PIPE_SELECT_CHV(pipe
);
349 else if (pipe
== PIPE_B
)
350 DP
|= DP_PIPEB_SELECT
;
352 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
359 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
360 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
362 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
376 I915_WRITE(intel_dp
->output_reg
, DP
);
377 POSTING_READ(intel_dp
->output_reg
);
379 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
386 vlv_force_pll_off(dev
, pipe
);
388 if (release_cl_override
)
389 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
394 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
396 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
397 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
398 struct drm_i915_private
*dev_priv
= to_i915(dev
);
399 struct intel_encoder
*encoder
;
400 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
403 lockdep_assert_held(&dev_priv
->pps_mutex
);
405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp
));
408 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
409 return intel_dp
->pps_pipe
;
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
415 for_each_intel_encoder(dev
, encoder
) {
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
457 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
459 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
460 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
463 lockdep_assert_held(&dev_priv
->pps_mutex
);
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp
));
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
473 if (!intel_dp
->pps_reset
)
476 intel_dp
->pps_reset
= false;
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
482 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
487 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
490 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
493 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
499 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
502 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
509 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
511 vlv_pipe_check pipe_check
)
515 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
516 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
517 PANEL_PORT_SELECT_MASK
;
519 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
522 if (!pipe_check(dev_priv
, pipe
))
532 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
534 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
535 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
536 struct drm_i915_private
*dev_priv
= to_i915(dev
);
537 enum port port
= intel_dig_port
->port
;
539 lockdep_assert_held(&dev_priv
->pps_mutex
);
541 /* try to find a pipe with this port selected */
542 /* first pick one where the panel is on */
543 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
547 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
548 vlv_pipe_has_vdd_on
);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
551 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
564 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
565 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
568 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
570 struct drm_device
*dev
= &dev_priv
->drm
;
571 struct intel_encoder
*encoder
;
573 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
574 !IS_BROXTON(dev_priv
)))
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
587 for_each_intel_encoder(dev
, encoder
) {
588 struct intel_dp
*intel_dp
;
590 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
593 intel_dp
= enc_to_intel_dp(&encoder
->base
);
594 if (IS_BROXTON(dev_priv
))
595 intel_dp
->pps_reset
= true;
597 intel_dp
->pps_pipe
= INVALID_PIPE
;
601 struct pps_registers
{
609 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
610 struct intel_dp
*intel_dp
,
611 struct pps_registers
*regs
)
615 memset(regs
, 0, sizeof(*regs
));
617 if (IS_BROXTON(dev_priv
))
618 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
619 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
620 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
622 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
623 regs
->pp_stat
= PP_STATUS(pps_idx
);
624 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
625 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
626 if (!IS_BROXTON(dev_priv
))
627 regs
->pp_div
= PP_DIVISOR(pps_idx
);
631 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
633 struct pps_registers regs
;
635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
642 _pp_stat_reg(struct intel_dp
*intel_dp
)
644 struct pps_registers regs
;
646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
657 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
659 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
662 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
667 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
668 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
669 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
672 pp_ctrl_reg
= PP_CONTROL(pipe
);
673 pp_div_reg
= PP_DIVISOR(pipe
);
674 pp_div
= I915_READ(pp_div_reg
);
675 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
679 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
680 msleep(intel_dp
->panel_power_cycle_delay
);
683 pps_unlock(intel_dp
);
688 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
693 lockdep_assert_held(&dev_priv
->pps_mutex
);
695 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
696 intel_dp
->pps_pipe
== INVALID_PIPE
)
699 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
702 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
704 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
705 struct drm_i915_private
*dev_priv
= to_i915(dev
);
707 lockdep_assert_held(&dev_priv
->pps_mutex
);
709 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
710 intel_dp
->pps_pipe
== INVALID_PIPE
)
713 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
717 intel_dp_check_edp(struct intel_dp
*intel_dp
)
719 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
722 if (!is_edp(intel_dp
))
725 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
728 I915_READ(_pp_stat_reg(intel_dp
)),
729 I915_READ(_pp_ctrl_reg(intel_dp
)));
734 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
739 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
746 msecs_to_jiffies_timeout(10));
748 done
= wait_for(C
, 10) == 0;
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
759 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
760 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
766 * The clock divider is based off the hrawclk, and would like to run at
767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
769 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
774 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
775 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
785 if (intel_dig_port
->port
== PORT_A
)
786 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
788 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
794 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
796 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
797 /* Workaround for non-ULT HSW */
805 return ilk_get_aux_clock_divider(intel_dp
, index
);
808 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
815 return index
? 0 : 1;
818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
821 uint32_t aux_clock_divider
)
823 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
824 struct drm_i915_private
*dev_priv
=
825 to_i915(intel_dig_port
->base
.base
.dev
);
826 uint32_t precharge
, timeout
;
828 if (IS_GEN6(dev_priv
))
833 if (IS_BROADWELL(dev_priv
) && intel_dig_port
->port
== PORT_A
)
834 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
836 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
838 return DP_AUX_CH_CTL_SEND_BUSY
|
840 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
841 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
843 DP_AUX_CH_CTL_RECEIVE_ERROR
|
844 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
845 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
846 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
849 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
854 return DP_AUX_CH_CTL_SEND_BUSY
|
856 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
857 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
858 DP_AUX_CH_CTL_TIME_OUT_1600us
|
859 DP_AUX_CH_CTL_RECEIVE_ERROR
|
860 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
861 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
862 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
866 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
867 const uint8_t *send
, int send_bytes
,
868 uint8_t *recv
, int recv_size
)
870 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
871 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
873 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
874 uint32_t aux_clock_divider
;
875 int i
, ret
, recv_bytes
;
878 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
884 * We will be called with VDD already enabled for dpcd/edid/oui reads.
885 * In such cases we want to leave VDD enabled and it's up to upper layers
886 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
889 vdd
= edp_panel_vdd_on(intel_dp
);
891 /* dp aux is extremely sensitive to irq latency, hence request the
892 * lowest possible wakeup latency and so prevent the cpu from going into
895 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
897 intel_dp_check_edp(intel_dp
);
899 /* Try to wait for any previous AUX channel activity */
900 for (try = 0; try < 3; try++) {
901 status
= I915_READ_NOTRACE(ch_ctl
);
902 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
908 static u32 last_status
= -1;
909 const u32 status
= I915_READ(ch_ctl
);
911 if (status
!= last_status
) {
912 WARN(1, "dp_aux_ch not started status 0x%08x\n",
914 last_status
= status
;
921 /* Only 5 data registers! */
922 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
927 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
928 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
933 /* Must try at least 3 times according to DP spec */
934 for (try = 0; try < 5; try++) {
935 /* Load the send data into the aux channel data registers */
936 for (i
= 0; i
< send_bytes
; i
+= 4)
937 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
938 intel_dp_pack_aux(send
+ i
,
941 /* Send the command and wait for it to complete */
942 I915_WRITE(ch_ctl
, send_ctl
);
944 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
946 /* Clear done status and any errors */
950 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
951 DP_AUX_CH_CTL_RECEIVE_ERROR
);
953 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
956 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
957 * 400us delay required for errors and timeouts
958 * Timeout errors from the HW already meet this
959 * requirement so skip to next iteration
961 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
962 usleep_range(400, 500);
965 if (status
& DP_AUX_CH_CTL_DONE
)
970 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
971 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
977 /* Check for timeout or receive error.
978 * Timeouts occur when the sink is not connected
980 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
981 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
986 /* Timeouts occur when the device isn't connected, so they're
987 * "normal" -- don't fill the kernel log with these */
988 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
989 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
994 /* Unload any bytes sent back from the other side */
995 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
996 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
999 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1000 * We have no idea of what happened so we return -EBUSY so
1001 * drm layer takes care for the necessary retries.
1003 if (recv_bytes
== 0 || recv_bytes
> 20) {
1004 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1007 * FIXME: This patch was created on top of a series that
1008 * organize the retries at drm level. There EBUSY should
1009 * also take care for 1ms wait before retrying.
1010 * That aux retries re-org is still needed and after that is
1011 * merged we remove this sleep from here.
1013 usleep_range(1000, 1500);
1018 if (recv_bytes
> recv_size
)
1019 recv_bytes
= recv_size
;
1021 for (i
= 0; i
< recv_bytes
; i
+= 4)
1022 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1023 recv
+ i
, recv_bytes
- i
);
1027 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1030 edp_panel_vdd_off(intel_dp
, false);
1032 pps_unlock(intel_dp
);
1037 #define BARE_ADDRESS_SIZE 3
1038 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1040 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1042 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1043 uint8_t txbuf
[20], rxbuf
[20];
1044 size_t txsize
, rxsize
;
1047 txbuf
[0] = (msg
->request
<< 4) |
1048 ((msg
->address
>> 16) & 0xf);
1049 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1050 txbuf
[2] = msg
->address
& 0xff;
1051 txbuf
[3] = msg
->size
- 1;
1053 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1054 case DP_AUX_NATIVE_WRITE
:
1055 case DP_AUX_I2C_WRITE
:
1056 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1057 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1058 rxsize
= 2; /* 0 or 1 data bytes */
1060 if (WARN_ON(txsize
> 20))
1063 WARN_ON(!msg
->buffer
!= !msg
->size
);
1066 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1068 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1070 msg
->reply
= rxbuf
[0] >> 4;
1073 /* Number of bytes written in a short write. */
1074 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1076 /* Return payload size. */
1082 case DP_AUX_NATIVE_READ
:
1083 case DP_AUX_I2C_READ
:
1084 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1085 rxsize
= msg
->size
+ 1;
1087 if (WARN_ON(rxsize
> 20))
1090 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1092 msg
->reply
= rxbuf
[0] >> 4;
1094 * Assume happy day, and copy the data. The caller is
1095 * expected to check msg->reply before touching it.
1097 * Return payload size.
1100 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1112 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1115 const struct ddi_vbt_port_info
*info
=
1116 &dev_priv
->vbt
.ddi_port_info
[port
];
1119 if (!info
->alternate_aux_channel
) {
1120 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1121 port_name(port
), port_name(port
));
1125 switch (info
->alternate_aux_channel
) {
1139 MISSING_CASE(info
->alternate_aux_channel
);
1144 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1145 port_name(aux_port
), port_name(port
));
1150 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1157 return DP_AUX_CH_CTL(port
);
1160 return DP_AUX_CH_CTL(PORT_B
);
1164 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1165 enum port port
, int index
)
1171 return DP_AUX_CH_DATA(port
, index
);
1174 return DP_AUX_CH_DATA(PORT_B
, index
);
1178 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1183 return DP_AUX_CH_CTL(port
);
1187 return PCH_DP_AUX_CH_CTL(port
);
1190 return DP_AUX_CH_CTL(PORT_A
);
1194 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1195 enum port port
, int index
)
1199 return DP_AUX_CH_DATA(port
, index
);
1203 return PCH_DP_AUX_CH_DATA(port
, index
);
1206 return DP_AUX_CH_DATA(PORT_A
, index
);
1210 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1218 return DP_AUX_CH_CTL(port
);
1221 return DP_AUX_CH_CTL(PORT_A
);
1225 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1226 enum port port
, int index
)
1233 return DP_AUX_CH_DATA(port
, index
);
1236 return DP_AUX_CH_DATA(PORT_A
, index
);
1240 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1243 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1244 return skl_aux_ctl_reg(dev_priv
, port
);
1245 else if (HAS_PCH_SPLIT(dev_priv
))
1246 return ilk_aux_ctl_reg(dev_priv
, port
);
1248 return g4x_aux_ctl_reg(dev_priv
, port
);
1251 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1252 enum port port
, int index
)
1254 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1255 return skl_aux_data_reg(dev_priv
, port
, index
);
1256 else if (HAS_PCH_SPLIT(dev_priv
))
1257 return ilk_aux_data_reg(dev_priv
, port
, index
);
1259 return g4x_aux_data_reg(dev_priv
, port
, index
);
1262 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1264 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1265 enum port port
= intel_aux_port(dev_priv
,
1266 dp_to_dig_port(intel_dp
)->port
);
1269 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1270 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1271 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1275 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1277 kfree(intel_dp
->aux
.name
);
1281 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1283 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1284 enum port port
= intel_dig_port
->port
;
1286 intel_aux_reg_init(intel_dp
);
1287 drm_dp_aux_init(&intel_dp
->aux
);
1289 /* Failure to allocate our preferred name is not critical */
1290 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1291 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1295 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1297 if (intel_dp
->num_sink_rates
) {
1298 *sink_rates
= intel_dp
->sink_rates
;
1299 return intel_dp
->num_sink_rates
;
1302 *sink_rates
= default_rates
;
1304 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1307 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1309 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1310 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1312 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1313 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1320 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1322 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1323 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1326 if (IS_BROXTON(dev_priv
)) {
1327 *source_rates
= bxt_rates
;
1328 size
= ARRAY_SIZE(bxt_rates
);
1329 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1330 *source_rates
= skl_rates
;
1331 size
= ARRAY_SIZE(skl_rates
);
1333 *source_rates
= default_rates
;
1334 size
= ARRAY_SIZE(default_rates
);
1337 /* This depends on the fact that 5.4 is last value in the array */
1338 if (!intel_dp_source_supports_hbr2(intel_dp
))
1345 intel_dp_set_clock(struct intel_encoder
*encoder
,
1346 struct intel_crtc_state
*pipe_config
)
1348 struct drm_device
*dev
= encoder
->base
.dev
;
1349 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1350 const struct dp_link_dpll
*divisor
= NULL
;
1353 if (IS_G4X(dev_priv
)) {
1354 divisor
= gen4_dpll
;
1355 count
= ARRAY_SIZE(gen4_dpll
);
1356 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1358 count
= ARRAY_SIZE(pch_dpll
);
1359 } else if (IS_CHERRYVIEW(dev_priv
)) {
1361 count
= ARRAY_SIZE(chv_dpll
);
1362 } else if (IS_VALLEYVIEW(dev_priv
)) {
1364 count
= ARRAY_SIZE(vlv_dpll
);
1367 if (divisor
&& count
) {
1368 for (i
= 0; i
< count
; i
++) {
1369 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1370 pipe_config
->dpll
= divisor
[i
].dpll
;
1371 pipe_config
->clock_set
= true;
1378 static int intersect_rates(const int *source_rates
, int source_len
,
1379 const int *sink_rates
, int sink_len
,
1382 int i
= 0, j
= 0, k
= 0;
1384 while (i
< source_len
&& j
< sink_len
) {
1385 if (source_rates
[i
] == sink_rates
[j
]) {
1386 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1388 common_rates
[k
] = source_rates
[i
];
1392 } else if (source_rates
[i
] < sink_rates
[j
]) {
1401 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1404 const int *source_rates
, *sink_rates
;
1405 int source_len
, sink_len
;
1407 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1408 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1410 return intersect_rates(source_rates
, source_len
,
1411 sink_rates
, sink_len
,
1415 static void snprintf_int_array(char *str
, size_t len
,
1416 const int *array
, int nelem
)
1422 for (i
= 0; i
< nelem
; i
++) {
1423 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1431 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1433 const int *source_rates
, *sink_rates
;
1434 int source_len
, sink_len
, common_len
;
1435 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1436 char str
[128]; /* FIXME: too big for stack? */
1438 if ((drm_debug
& DRM_UT_KMS
) == 0)
1441 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1442 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1443 DRM_DEBUG_KMS("source rates: %s\n", str
);
1445 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1446 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1447 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1449 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1450 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1451 DRM_DEBUG_KMS("common rates: %s\n", str
);
1454 static void intel_dp_print_hw_revision(struct intel_dp
*intel_dp
)
1459 if ((drm_debug
& DRM_UT_KMS
) == 0)
1462 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1463 DP_DWN_STRM_PORT_PRESENT
))
1466 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_HW_REV
, &rev
, 1);
1470 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev
& 0xf0) >> 4, rev
& 0xf);
1473 static void intel_dp_print_sw_revision(struct intel_dp
*intel_dp
)
1478 if ((drm_debug
& DRM_UT_KMS
) == 0)
1481 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1482 DP_DWN_STRM_PORT_PRESENT
))
1485 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_SW_REV
, &rev
, 2);
1489 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev
[0], rev
[1]);
1492 static int rate_to_index(int find
, const int *rates
)
1496 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1497 if (find
== rates
[i
])
1504 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1506 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1509 len
= intel_dp_common_rates(intel_dp
, rates
);
1510 if (WARN_ON(len
<= 0))
1513 return rates
[len
- 1];
1516 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1518 return rate_to_index(rate
, intel_dp
->sink_rates
);
1521 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1522 uint8_t *link_bw
, uint8_t *rate_select
)
1524 if (intel_dp
->num_sink_rates
) {
1527 intel_dp_rate_select(intel_dp
, port_clock
);
1529 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1534 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1535 struct intel_crtc_state
*pipe_config
)
1539 bpp
= pipe_config
->pipe_bpp
;
1540 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1543 bpp
= min(bpp
, 3*bpc
);
1549 intel_dp_compute_config(struct intel_encoder
*encoder
,
1550 struct intel_crtc_state
*pipe_config
,
1551 struct drm_connector_state
*conn_state
)
1553 struct drm_device
*dev
= encoder
->base
.dev
;
1554 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1555 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1556 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1557 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1558 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1559 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1560 int lane_count
, clock
;
1561 int min_lane_count
= 1;
1562 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1563 /* Conveniently, the link BW constants become indices with a shift...*/
1567 int link_avail
, link_clock
;
1568 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1570 uint8_t link_bw
, rate_select
;
1572 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1574 /* No common link rates between source and sink */
1575 WARN_ON(common_len
<= 0);
1577 max_clock
= common_len
- 1;
1579 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1580 pipe_config
->has_pch_encoder
= true;
1582 pipe_config
->has_drrs
= false;
1583 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1585 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1586 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1589 if (INTEL_INFO(dev
)->gen
>= 9) {
1591 ret
= skl_update_scaler_crtc(pipe_config
);
1596 if (HAS_GMCH_DISPLAY(dev_priv
))
1597 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1598 intel_connector
->panel
.fitting_mode
);
1600 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1601 intel_connector
->panel
.fitting_mode
);
1604 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1607 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1608 "max bw %d pixel clock %iKHz\n",
1609 max_lane_count
, common_rates
[max_clock
],
1610 adjusted_mode
->crtc_clock
);
1612 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1613 * bpc in between. */
1614 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1615 if (is_edp(intel_dp
)) {
1617 /* Get bpp from vbt only for panels that dont have bpp in edid */
1618 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1619 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1620 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1621 dev_priv
->vbt
.edp
.bpp
);
1622 bpp
= dev_priv
->vbt
.edp
.bpp
;
1626 * Use the maximum clock and number of lanes the eDP panel
1627 * advertizes being capable of. The panels are generally
1628 * designed to support only a single clock and lane
1629 * configuration, and typically these values correspond to the
1630 * native resolution of the panel.
1632 min_lane_count
= max_lane_count
;
1633 min_clock
= max_clock
;
1636 for (; bpp
>= 6*3; bpp
-= 2*3) {
1637 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1640 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1641 for (lane_count
= min_lane_count
;
1642 lane_count
<= max_lane_count
;
1645 link_clock
= common_rates
[clock
];
1646 link_avail
= intel_dp_max_data_rate(link_clock
,
1649 if (mode_rate
<= link_avail
) {
1659 if (intel_dp
->color_range_auto
) {
1662 * CEA-861-E - 5.1 Default Encoding Parameters
1663 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1665 pipe_config
->limited_color_range
=
1666 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1668 pipe_config
->limited_color_range
=
1669 intel_dp
->limited_color_range
;
1672 pipe_config
->lane_count
= lane_count
;
1674 pipe_config
->pipe_bpp
= bpp
;
1675 pipe_config
->port_clock
= common_rates
[clock
];
1677 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1678 &link_bw
, &rate_select
);
1680 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1681 link_bw
, rate_select
, pipe_config
->lane_count
,
1682 pipe_config
->port_clock
, bpp
);
1683 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1684 mode_rate
, link_avail
);
1686 intel_link_compute_m_n(bpp
, lane_count
,
1687 adjusted_mode
->crtc_clock
,
1688 pipe_config
->port_clock
,
1689 &pipe_config
->dp_m_n
);
1691 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1692 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1693 pipe_config
->has_drrs
= true;
1694 intel_link_compute_m_n(bpp
, lane_count
,
1695 intel_connector
->panel
.downclock_mode
->clock
,
1696 pipe_config
->port_clock
,
1697 &pipe_config
->dp_m2_n2
);
1701 * DPLL0 VCO may need to be adjusted to get the correct
1702 * clock for eDP. This will affect cdclk as well.
1704 if (is_edp(intel_dp
) &&
1705 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1708 switch (pipe_config
->port_clock
/ 2) {
1718 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1721 if (!HAS_DDI(dev_priv
))
1722 intel_dp_set_clock(encoder
, pipe_config
);
1727 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1728 int link_rate
, uint8_t lane_count
,
1731 intel_dp
->link_rate
= link_rate
;
1732 intel_dp
->lane_count
= lane_count
;
1733 intel_dp
->link_mst
= link_mst
;
1736 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1737 struct intel_crtc_state
*pipe_config
)
1739 struct drm_device
*dev
= encoder
->base
.dev
;
1740 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1741 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1742 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1743 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1744 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1746 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1747 pipe_config
->lane_count
,
1748 intel_crtc_has_type(pipe_config
,
1749 INTEL_OUTPUT_DP_MST
));
1752 * There are four kinds of DP registers:
1759 * IBX PCH and CPU are the same for almost everything,
1760 * except that the CPU DP PLL is configured in this
1763 * CPT PCH is quite different, having many bits moved
1764 * to the TRANS_DP_CTL register instead. That
1765 * configuration happens (oddly) in ironlake_pch_enable
1768 /* Preserve the BIOS-computed detected bit. This is
1769 * supposed to be read-only.
1771 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1773 /* Handle DP bits in common between all three register formats */
1774 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1775 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1777 /* Split out the IBX/CPU vs CPT settings */
1779 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1780 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1781 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1782 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1783 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1784 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1786 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1787 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1789 intel_dp
->DP
|= crtc
->pipe
<< 29;
1790 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1793 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1795 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1796 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1797 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1799 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1800 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1802 if (!HAS_PCH_SPLIT(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
1803 !IS_CHERRYVIEW(dev_priv
) &&
1804 pipe_config
->limited_color_range
)
1805 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1807 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1808 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1809 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1810 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1811 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1813 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1814 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1816 if (IS_CHERRYVIEW(dev_priv
))
1817 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1818 else if (crtc
->pipe
== PIPE_B
)
1819 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1823 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1824 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1826 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1827 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1829 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1830 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1832 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1833 struct intel_dp
*intel_dp
);
1835 static void wait_panel_status(struct intel_dp
*intel_dp
,
1839 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1840 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1841 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1843 lockdep_assert_held(&dev_priv
->pps_mutex
);
1845 intel_pps_verify_state(dev_priv
, intel_dp
);
1847 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1848 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1850 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1852 I915_READ(pp_stat_reg
),
1853 I915_READ(pp_ctrl_reg
));
1855 if (intel_wait_for_register(dev_priv
,
1856 pp_stat_reg
, mask
, value
,
1858 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1859 I915_READ(pp_stat_reg
),
1860 I915_READ(pp_ctrl_reg
));
1862 DRM_DEBUG_KMS("Wait complete\n");
1865 static void wait_panel_on(struct intel_dp
*intel_dp
)
1867 DRM_DEBUG_KMS("Wait for panel power on\n");
1868 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1871 static void wait_panel_off(struct intel_dp
*intel_dp
)
1873 DRM_DEBUG_KMS("Wait for panel power off time\n");
1874 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1877 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1879 ktime_t panel_power_on_time
;
1880 s64 panel_power_off_duration
;
1882 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1884 /* take the difference of currrent time and panel power off time
1885 * and then make panel wait for t11_t12 if needed. */
1886 panel_power_on_time
= ktime_get_boottime();
1887 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1889 /* When we disable the VDD override bit last we have to do the manual
1891 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1892 wait_remaining_ms_from_jiffies(jiffies
,
1893 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1895 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1898 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1900 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1901 intel_dp
->backlight_on_delay
);
1904 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1906 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1907 intel_dp
->backlight_off_delay
);
1910 /* Read the current pp_control value, unlocking the register if it
1914 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1916 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1917 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1920 lockdep_assert_held(&dev_priv
->pps_mutex
);
1922 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1923 if (WARN_ON(!HAS_DDI(dev_priv
) &&
1924 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
1925 control
&= ~PANEL_UNLOCK_MASK
;
1926 control
|= PANEL_UNLOCK_REGS
;
1932 * Must be paired with edp_panel_vdd_off().
1933 * Must hold pps_mutex around the whole on/off sequence.
1934 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1936 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1938 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1939 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1940 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1941 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1942 enum intel_display_power_domain power_domain
;
1944 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1945 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1947 lockdep_assert_held(&dev_priv
->pps_mutex
);
1949 if (!is_edp(intel_dp
))
1952 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1953 intel_dp
->want_panel_vdd
= true;
1955 if (edp_have_panel_vdd(intel_dp
))
1956 return need_to_disable
;
1958 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1959 intel_display_power_get(dev_priv
, power_domain
);
1961 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1962 port_name(intel_dig_port
->port
));
1964 if (!edp_have_panel_power(intel_dp
))
1965 wait_panel_power_cycle(intel_dp
);
1967 pp
= ironlake_get_pp_control(intel_dp
);
1968 pp
|= EDP_FORCE_VDD
;
1970 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1971 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1973 I915_WRITE(pp_ctrl_reg
, pp
);
1974 POSTING_READ(pp_ctrl_reg
);
1975 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1976 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1978 * If the panel wasn't on, delay before accessing aux channel
1980 if (!edp_have_panel_power(intel_dp
)) {
1981 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1982 port_name(intel_dig_port
->port
));
1983 msleep(intel_dp
->panel_power_up_delay
);
1986 return need_to_disable
;
1990 * Must be paired with intel_edp_panel_vdd_off() or
1991 * intel_edp_panel_off().
1992 * Nested calls to these functions are not allowed since
1993 * we drop the lock. Caller must use some higher level
1994 * locking to prevent nested calls from other threads.
1996 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2000 if (!is_edp(intel_dp
))
2004 vdd
= edp_panel_vdd_on(intel_dp
);
2005 pps_unlock(intel_dp
);
2007 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2008 port_name(dp_to_dig_port(intel_dp
)->port
));
2011 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2013 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2014 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2015 struct intel_digital_port
*intel_dig_port
=
2016 dp_to_dig_port(intel_dp
);
2017 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2018 enum intel_display_power_domain power_domain
;
2020 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2022 lockdep_assert_held(&dev_priv
->pps_mutex
);
2024 WARN_ON(intel_dp
->want_panel_vdd
);
2026 if (!edp_have_panel_vdd(intel_dp
))
2029 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2030 port_name(intel_dig_port
->port
));
2032 pp
= ironlake_get_pp_control(intel_dp
);
2033 pp
&= ~EDP_FORCE_VDD
;
2035 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2036 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2038 I915_WRITE(pp_ctrl_reg
, pp
);
2039 POSTING_READ(pp_ctrl_reg
);
2041 /* Make sure sequencer is idle before allowing subsequent activity */
2042 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2043 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2045 if ((pp
& PANEL_POWER_ON
) == 0)
2046 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2048 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2049 intel_display_power_put(dev_priv
, power_domain
);
2052 static void edp_panel_vdd_work(struct work_struct
*__work
)
2054 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2055 struct intel_dp
, panel_vdd_work
);
2058 if (!intel_dp
->want_panel_vdd
)
2059 edp_panel_vdd_off_sync(intel_dp
);
2060 pps_unlock(intel_dp
);
2063 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2065 unsigned long delay
;
2068 * Queue the timer to fire a long time from now (relative to the power
2069 * down delay) to keep the panel power up across a sequence of
2072 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2073 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2077 * Must be paired with edp_panel_vdd_on().
2078 * Must hold pps_mutex around the whole on/off sequence.
2079 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2081 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2083 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2085 lockdep_assert_held(&dev_priv
->pps_mutex
);
2087 if (!is_edp(intel_dp
))
2090 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2091 port_name(dp_to_dig_port(intel_dp
)->port
));
2093 intel_dp
->want_panel_vdd
= false;
2096 edp_panel_vdd_off_sync(intel_dp
);
2098 edp_panel_vdd_schedule_off(intel_dp
);
2101 static void edp_panel_on(struct intel_dp
*intel_dp
)
2103 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2104 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2106 i915_reg_t pp_ctrl_reg
;
2108 lockdep_assert_held(&dev_priv
->pps_mutex
);
2110 if (!is_edp(intel_dp
))
2113 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2114 port_name(dp_to_dig_port(intel_dp
)->port
));
2116 if (WARN(edp_have_panel_power(intel_dp
),
2117 "eDP port %c panel power already on\n",
2118 port_name(dp_to_dig_port(intel_dp
)->port
)))
2121 wait_panel_power_cycle(intel_dp
);
2123 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2124 pp
= ironlake_get_pp_control(intel_dp
);
2125 if (IS_GEN5(dev_priv
)) {
2126 /* ILK workaround: disable reset around power sequence */
2127 pp
&= ~PANEL_POWER_RESET
;
2128 I915_WRITE(pp_ctrl_reg
, pp
);
2129 POSTING_READ(pp_ctrl_reg
);
2132 pp
|= PANEL_POWER_ON
;
2133 if (!IS_GEN5(dev_priv
))
2134 pp
|= PANEL_POWER_RESET
;
2136 I915_WRITE(pp_ctrl_reg
, pp
);
2137 POSTING_READ(pp_ctrl_reg
);
2139 wait_panel_on(intel_dp
);
2140 intel_dp
->last_power_on
= jiffies
;
2142 if (IS_GEN5(dev_priv
)) {
2143 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2144 I915_WRITE(pp_ctrl_reg
, pp
);
2145 POSTING_READ(pp_ctrl_reg
);
2149 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2151 if (!is_edp(intel_dp
))
2155 edp_panel_on(intel_dp
);
2156 pps_unlock(intel_dp
);
2160 static void edp_panel_off(struct intel_dp
*intel_dp
)
2162 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2163 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2164 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2165 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2166 enum intel_display_power_domain power_domain
;
2168 i915_reg_t pp_ctrl_reg
;
2170 lockdep_assert_held(&dev_priv
->pps_mutex
);
2172 if (!is_edp(intel_dp
))
2175 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2176 port_name(dp_to_dig_port(intel_dp
)->port
));
2178 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2179 port_name(dp_to_dig_port(intel_dp
)->port
));
2181 pp
= ironlake_get_pp_control(intel_dp
);
2182 /* We need to switch off panel power _and_ force vdd, for otherwise some
2183 * panels get very unhappy and cease to work. */
2184 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2187 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2189 intel_dp
->want_panel_vdd
= false;
2191 I915_WRITE(pp_ctrl_reg
, pp
);
2192 POSTING_READ(pp_ctrl_reg
);
2194 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2195 wait_panel_off(intel_dp
);
2197 /* We got a reference when we enabled the VDD. */
2198 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2199 intel_display_power_put(dev_priv
, power_domain
);
2202 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2204 if (!is_edp(intel_dp
))
2208 edp_panel_off(intel_dp
);
2209 pps_unlock(intel_dp
);
2212 /* Enable backlight in the panel power control. */
2213 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2215 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2216 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2217 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2219 i915_reg_t pp_ctrl_reg
;
2222 * If we enable the backlight right away following a panel power
2223 * on, we may see slight flicker as the panel syncs with the eDP
2224 * link. So delay a bit to make sure the image is solid before
2225 * allowing it to appear.
2227 wait_backlight_on(intel_dp
);
2231 pp
= ironlake_get_pp_control(intel_dp
);
2232 pp
|= EDP_BLC_ENABLE
;
2234 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2236 I915_WRITE(pp_ctrl_reg
, pp
);
2237 POSTING_READ(pp_ctrl_reg
);
2239 pps_unlock(intel_dp
);
2242 /* Enable backlight PWM and backlight PP control. */
2243 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2245 if (!is_edp(intel_dp
))
2248 DRM_DEBUG_KMS("\n");
2250 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2251 _intel_edp_backlight_on(intel_dp
);
2254 /* Disable backlight in the panel power control. */
2255 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2257 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2258 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2260 i915_reg_t pp_ctrl_reg
;
2262 if (!is_edp(intel_dp
))
2267 pp
= ironlake_get_pp_control(intel_dp
);
2268 pp
&= ~EDP_BLC_ENABLE
;
2270 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2272 I915_WRITE(pp_ctrl_reg
, pp
);
2273 POSTING_READ(pp_ctrl_reg
);
2275 pps_unlock(intel_dp
);
2277 intel_dp
->last_backlight_off
= jiffies
;
2278 edp_wait_backlight_off(intel_dp
);
2281 /* Disable backlight PP control and backlight PWM. */
2282 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2284 if (!is_edp(intel_dp
))
2287 DRM_DEBUG_KMS("\n");
2289 _intel_edp_backlight_off(intel_dp
);
2290 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2294 * Hook for controlling the panel power control backlight through the bl_power
2295 * sysfs attribute. Take care to handle multiple calls.
2297 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2300 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2304 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2305 pps_unlock(intel_dp
);
2307 if (is_enabled
== enable
)
2310 DRM_DEBUG_KMS("panel power control backlight %s\n",
2311 enable
? "enable" : "disable");
2314 _intel_edp_backlight_on(intel_dp
);
2316 _intel_edp_backlight_off(intel_dp
);
2319 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2321 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2322 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2323 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2325 I915_STATE_WARN(cur_state
!= state
,
2326 "DP port %c state assertion failure (expected %s, current %s)\n",
2327 port_name(dig_port
->port
),
2328 onoff(state
), onoff(cur_state
));
2330 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2332 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2334 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2336 I915_STATE_WARN(cur_state
!= state
,
2337 "eDP PLL state assertion failure (expected %s, current %s)\n",
2338 onoff(state
), onoff(cur_state
));
2340 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2341 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2343 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2344 struct intel_crtc_state
*pipe_config
)
2346 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2347 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2349 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2350 assert_dp_port_disabled(intel_dp
);
2351 assert_edp_pll_disabled(dev_priv
);
2353 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2354 pipe_config
->port_clock
);
2356 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2358 if (pipe_config
->port_clock
== 162000)
2359 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2361 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2363 I915_WRITE(DP_A
, intel_dp
->DP
);
2368 * [DevILK] Work around required when enabling DP PLL
2369 * while a pipe is enabled going to FDI:
2370 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2371 * 2. Program DP PLL enable
2373 if (IS_GEN5(dev_priv
))
2374 intel_wait_for_vblank_if_active(&dev_priv
->drm
, !crtc
->pipe
);
2376 intel_dp
->DP
|= DP_PLL_ENABLE
;
2378 I915_WRITE(DP_A
, intel_dp
->DP
);
2383 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2385 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2386 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2387 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2389 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2390 assert_dp_port_disabled(intel_dp
);
2391 assert_edp_pll_enabled(dev_priv
);
2393 DRM_DEBUG_KMS("disabling eDP PLL\n");
2395 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2397 I915_WRITE(DP_A
, intel_dp
->DP
);
2402 /* If the sink supports it, try to set the power state appropriately */
2403 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2407 /* Should have a valid DPCD by this point */
2408 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2411 if (mode
!= DRM_MODE_DPMS_ON
) {
2412 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2416 * When turning on, we need to retry for 1ms to give the sink
2419 for (i
= 0; i
< 3; i
++) {
2420 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2429 DRM_DEBUG_KMS("failed to %s sink power state\n",
2430 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2433 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2436 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2437 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2438 struct drm_device
*dev
= encoder
->base
.dev
;
2439 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2440 enum intel_display_power_domain power_domain
;
2444 power_domain
= intel_display_port_power_domain(encoder
);
2445 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2450 tmp
= I915_READ(intel_dp
->output_reg
);
2452 if (!(tmp
& DP_PORT_EN
))
2455 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2456 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2457 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2460 for_each_pipe(dev_priv
, p
) {
2461 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2462 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2470 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2471 i915_mmio_reg_offset(intel_dp
->output_reg
));
2472 } else if (IS_CHERRYVIEW(dev_priv
)) {
2473 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2475 *pipe
= PORT_TO_PIPE(tmp
);
2481 intel_display_power_put(dev_priv
, power_domain
);
2486 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2487 struct intel_crtc_state
*pipe_config
)
2489 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2491 struct drm_device
*dev
= encoder
->base
.dev
;
2492 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2493 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2494 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2496 tmp
= I915_READ(intel_dp
->output_reg
);
2498 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2500 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2501 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2503 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2504 flags
|= DRM_MODE_FLAG_PHSYNC
;
2506 flags
|= DRM_MODE_FLAG_NHSYNC
;
2508 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2509 flags
|= DRM_MODE_FLAG_PVSYNC
;
2511 flags
|= DRM_MODE_FLAG_NVSYNC
;
2513 if (tmp
& DP_SYNC_HS_HIGH
)
2514 flags
|= DRM_MODE_FLAG_PHSYNC
;
2516 flags
|= DRM_MODE_FLAG_NHSYNC
;
2518 if (tmp
& DP_SYNC_VS_HIGH
)
2519 flags
|= DRM_MODE_FLAG_PVSYNC
;
2521 flags
|= DRM_MODE_FLAG_NVSYNC
;
2524 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2526 if (!HAS_PCH_SPLIT(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
2527 !IS_CHERRYVIEW(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2528 pipe_config
->limited_color_range
= true;
2530 pipe_config
->lane_count
=
2531 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2533 intel_dp_get_m_n(crtc
, pipe_config
);
2535 if (port
== PORT_A
) {
2536 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2537 pipe_config
->port_clock
= 162000;
2539 pipe_config
->port_clock
= 270000;
2542 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2543 intel_dotclock_calculate(pipe_config
->port_clock
,
2544 &pipe_config
->dp_m_n
);
2546 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2547 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2549 * This is a big fat ugly hack.
2551 * Some machines in UEFI boot mode provide us a VBT that has 18
2552 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2553 * unknown we fail to light up. Yet the same BIOS boots up with
2554 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2555 * max, not what it tells us to use.
2557 * Note: This will still be broken if the eDP panel is not lit
2558 * up by the BIOS, and thus we can't get the mode at module
2561 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2562 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2563 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2567 static void intel_disable_dp(struct intel_encoder
*encoder
,
2568 struct intel_crtc_state
*old_crtc_state
,
2569 struct drm_connector_state
*old_conn_state
)
2571 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2572 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2574 if (old_crtc_state
->has_audio
)
2575 intel_audio_codec_disable(encoder
);
2577 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2578 intel_psr_disable(intel_dp
);
2580 /* Make sure the panel is off before trying to change the mode. But also
2581 * ensure that we have vdd while we switch off the panel. */
2582 intel_edp_panel_vdd_on(intel_dp
);
2583 intel_edp_backlight_off(intel_dp
);
2584 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2585 intel_edp_panel_off(intel_dp
);
2587 /* disable the port before the pipe on g4x */
2588 if (INTEL_GEN(dev_priv
) < 5)
2589 intel_dp_link_down(intel_dp
);
2592 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2593 struct intel_crtc_state
*old_crtc_state
,
2594 struct drm_connector_state
*old_conn_state
)
2596 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2597 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2599 intel_dp_link_down(intel_dp
);
2601 /* Only ilk+ has port A */
2603 ironlake_edp_pll_off(intel_dp
);
2606 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2607 struct intel_crtc_state
*old_crtc_state
,
2608 struct drm_connector_state
*old_conn_state
)
2610 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2612 intel_dp_link_down(intel_dp
);
2615 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2616 struct intel_crtc_state
*old_crtc_state
,
2617 struct drm_connector_state
*old_conn_state
)
2619 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2620 struct drm_device
*dev
= encoder
->base
.dev
;
2621 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2623 intel_dp_link_down(intel_dp
);
2625 mutex_lock(&dev_priv
->sb_lock
);
2627 /* Assert data lane reset */
2628 chv_data_lane_soft_reset(encoder
, true);
2630 mutex_unlock(&dev_priv
->sb_lock
);
2634 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2636 uint8_t dp_train_pat
)
2638 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2639 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2640 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2641 enum port port
= intel_dig_port
->port
;
2643 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2644 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2645 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2647 if (HAS_DDI(dev_priv
)) {
2648 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2650 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2651 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2653 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2655 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2656 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2657 case DP_TRAINING_PATTERN_DISABLE
:
2658 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2661 case DP_TRAINING_PATTERN_1
:
2662 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2664 case DP_TRAINING_PATTERN_2
:
2665 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2667 case DP_TRAINING_PATTERN_3
:
2668 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2671 I915_WRITE(DP_TP_CTL(port
), temp
);
2673 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2674 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2675 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2677 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2678 case DP_TRAINING_PATTERN_DISABLE
:
2679 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2681 case DP_TRAINING_PATTERN_1
:
2682 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2684 case DP_TRAINING_PATTERN_2
:
2685 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2687 case DP_TRAINING_PATTERN_3
:
2688 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2689 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2694 if (IS_CHERRYVIEW(dev_priv
))
2695 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2697 *DP
&= ~DP_LINK_TRAIN_MASK
;
2699 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2700 case DP_TRAINING_PATTERN_DISABLE
:
2701 *DP
|= DP_LINK_TRAIN_OFF
;
2703 case DP_TRAINING_PATTERN_1
:
2704 *DP
|= DP_LINK_TRAIN_PAT_1
;
2706 case DP_TRAINING_PATTERN_2
:
2707 *DP
|= DP_LINK_TRAIN_PAT_2
;
2709 case DP_TRAINING_PATTERN_3
:
2710 if (IS_CHERRYVIEW(dev_priv
)) {
2711 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2713 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2714 *DP
|= DP_LINK_TRAIN_PAT_2
;
2721 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2722 struct intel_crtc_state
*old_crtc_state
)
2724 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2725 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2727 /* enable with pattern 1 (as per spec) */
2729 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2732 * Magic for VLV/CHV. We _must_ first set up the register
2733 * without actually enabling the port, and then do another
2734 * write to enable the port. Otherwise link training will
2735 * fail when the power sequencer is freshly used for this port.
2737 intel_dp
->DP
|= DP_PORT_EN
;
2738 if (old_crtc_state
->has_audio
)
2739 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2741 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2742 POSTING_READ(intel_dp
->output_reg
);
2745 static void intel_enable_dp(struct intel_encoder
*encoder
,
2746 struct intel_crtc_state
*pipe_config
)
2748 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2749 struct drm_device
*dev
= encoder
->base
.dev
;
2750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2751 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2752 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2753 enum pipe pipe
= crtc
->pipe
;
2755 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2760 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2761 vlv_init_panel_power_sequencer(intel_dp
);
2763 intel_dp_enable_port(intel_dp
, pipe_config
);
2765 edp_panel_vdd_on(intel_dp
);
2766 edp_panel_on(intel_dp
);
2767 edp_panel_vdd_off(intel_dp
, true);
2769 pps_unlock(intel_dp
);
2771 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2772 unsigned int lane_mask
= 0x0;
2774 if (IS_CHERRYVIEW(dev_priv
))
2775 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2777 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2781 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2782 intel_dp_start_link_train(intel_dp
);
2783 intel_dp_stop_link_train(intel_dp
);
2785 if (pipe_config
->has_audio
) {
2786 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2788 intel_audio_codec_enable(encoder
);
2792 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2793 struct intel_crtc_state
*pipe_config
,
2794 struct drm_connector_state
*conn_state
)
2796 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2798 intel_enable_dp(encoder
, pipe_config
);
2799 intel_edp_backlight_on(intel_dp
);
2802 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2803 struct intel_crtc_state
*pipe_config
,
2804 struct drm_connector_state
*conn_state
)
2806 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2808 intel_edp_backlight_on(intel_dp
);
2809 intel_psr_enable(intel_dp
);
2812 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2813 struct intel_crtc_state
*pipe_config
,
2814 struct drm_connector_state
*conn_state
)
2816 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2817 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2819 intel_dp_prepare(encoder
, pipe_config
);
2821 /* Only ilk+ has port A */
2823 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2826 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2828 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2829 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2830 enum pipe pipe
= intel_dp
->pps_pipe
;
2831 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2833 edp_panel_vdd_off_sync(intel_dp
);
2836 * VLV seems to get confused when multiple power seqeuencers
2837 * have the same port selected (even if only one has power/vdd
2838 * enabled). The failure manifests as vlv_wait_port_ready() failing
2839 * CHV on the other hand doesn't seem to mind having the same port
2840 * selected in multiple power seqeuencers, but let's clear the
2841 * port select always when logically disconnecting a power sequencer
2844 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2845 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2846 I915_WRITE(pp_on_reg
, 0);
2847 POSTING_READ(pp_on_reg
);
2849 intel_dp
->pps_pipe
= INVALID_PIPE
;
2852 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2855 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2856 struct intel_encoder
*encoder
;
2858 lockdep_assert_held(&dev_priv
->pps_mutex
);
2860 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2863 for_each_intel_encoder(dev
, encoder
) {
2864 struct intel_dp
*intel_dp
;
2867 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2870 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2871 port
= dp_to_dig_port(intel_dp
)->port
;
2873 if (intel_dp
->pps_pipe
!= pipe
)
2876 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2877 pipe_name(pipe
), port_name(port
));
2879 WARN(encoder
->base
.crtc
,
2880 "stealing pipe %c power sequencer from active eDP port %c\n",
2881 pipe_name(pipe
), port_name(port
));
2883 /* make sure vdd is off before we steal it */
2884 vlv_detach_power_sequencer(intel_dp
);
2888 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2890 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2891 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2892 struct drm_device
*dev
= encoder
->base
.dev
;
2893 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2894 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2896 lockdep_assert_held(&dev_priv
->pps_mutex
);
2898 if (!is_edp(intel_dp
))
2901 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2905 * If another power sequencer was being used on this
2906 * port previously make sure to turn off vdd there while
2907 * we still have control of it.
2909 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2910 vlv_detach_power_sequencer(intel_dp
);
2913 * We may be stealing the power
2914 * sequencer from another port.
2916 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2918 /* now it's all ours */
2919 intel_dp
->pps_pipe
= crtc
->pipe
;
2921 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2922 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2924 /* init power sequencer on this pipe and port */
2925 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2926 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2929 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
2930 struct intel_crtc_state
*pipe_config
,
2931 struct drm_connector_state
*conn_state
)
2933 vlv_phy_pre_encoder_enable(encoder
);
2935 intel_enable_dp(encoder
, pipe_config
);
2938 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2939 struct intel_crtc_state
*pipe_config
,
2940 struct drm_connector_state
*conn_state
)
2942 intel_dp_prepare(encoder
, pipe_config
);
2944 vlv_phy_pre_pll_enable(encoder
);
2947 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
2948 struct intel_crtc_state
*pipe_config
,
2949 struct drm_connector_state
*conn_state
)
2951 chv_phy_pre_encoder_enable(encoder
);
2953 intel_enable_dp(encoder
, pipe_config
);
2955 /* Second common lane will stay alive on its own now */
2956 chv_phy_release_cl2_override(encoder
);
2959 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2960 struct intel_crtc_state
*pipe_config
,
2961 struct drm_connector_state
*conn_state
)
2963 intel_dp_prepare(encoder
, pipe_config
);
2965 chv_phy_pre_pll_enable(encoder
);
2968 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
2969 struct intel_crtc_state
*pipe_config
,
2970 struct drm_connector_state
*conn_state
)
2972 chv_phy_post_pll_disable(encoder
);
2976 * Fetch AUX CH registers 0x202 - 0x207 which contain
2977 * link status information
2980 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2982 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2983 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2986 /* These are source-specific values. */
2988 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2990 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2991 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2992 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2994 if (IS_BROXTON(dev_priv
))
2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2996 else if (INTEL_INFO(dev
)->gen
>= 9) {
2997 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2998 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2999 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3000 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3001 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3002 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3003 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3004 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3005 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3007 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3011 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3013 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3014 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3016 if (INTEL_GEN(dev_priv
) >= 9) {
3017 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3019 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3027 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3029 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3030 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3041 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3042 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3046 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3048 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3051 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3053 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3054 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3061 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3064 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3066 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3068 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3070 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3073 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3078 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3080 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3081 unsigned long demph_reg_value
, preemph_reg_value
,
3082 uniqtranscale_reg_value
;
3083 uint8_t train_set
= intel_dp
->train_set
[0];
3085 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3086 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3087 preemph_reg_value
= 0x0004000;
3088 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3090 demph_reg_value
= 0x2B405555;
3091 uniqtranscale_reg_value
= 0x552AB83A;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3094 demph_reg_value
= 0x2B404040;
3095 uniqtranscale_reg_value
= 0x5548B83A;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3098 demph_reg_value
= 0x2B245555;
3099 uniqtranscale_reg_value
= 0x5560B83A;
3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3102 demph_reg_value
= 0x2B405555;
3103 uniqtranscale_reg_value
= 0x5598DA3A;
3109 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3110 preemph_reg_value
= 0x0002000;
3111 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3113 demph_reg_value
= 0x2B404040;
3114 uniqtranscale_reg_value
= 0x5552B83A;
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3117 demph_reg_value
= 0x2B404848;
3118 uniqtranscale_reg_value
= 0x5580B83A;
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3121 demph_reg_value
= 0x2B404040;
3122 uniqtranscale_reg_value
= 0x55ADDA3A;
3128 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3129 preemph_reg_value
= 0x0000000;
3130 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3132 demph_reg_value
= 0x2B305555;
3133 uniqtranscale_reg_value
= 0x5570B83A;
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3136 demph_reg_value
= 0x2B2B4040;
3137 uniqtranscale_reg_value
= 0x55ADDA3A;
3143 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3144 preemph_reg_value
= 0x0006000;
3145 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3146 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3147 demph_reg_value
= 0x1B405555;
3148 uniqtranscale_reg_value
= 0x55ADDA3A;
3158 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3159 uniqtranscale_reg_value
, 0);
3164 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3166 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3167 u32 deemph_reg_value
, margin_reg_value
;
3168 bool uniq_trans_scale
= false;
3169 uint8_t train_set
= intel_dp
->train_set
[0];
3171 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3172 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3173 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3175 deemph_reg_value
= 128;
3176 margin_reg_value
= 52;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3179 deemph_reg_value
= 128;
3180 margin_reg_value
= 77;
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3183 deemph_reg_value
= 128;
3184 margin_reg_value
= 102;
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3187 deemph_reg_value
= 128;
3188 margin_reg_value
= 154;
3189 uniq_trans_scale
= true;
3195 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3196 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3198 deemph_reg_value
= 85;
3199 margin_reg_value
= 78;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3202 deemph_reg_value
= 85;
3203 margin_reg_value
= 116;
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3206 deemph_reg_value
= 85;
3207 margin_reg_value
= 154;
3213 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3214 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3216 deemph_reg_value
= 64;
3217 margin_reg_value
= 104;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3220 deemph_reg_value
= 64;
3221 margin_reg_value
= 154;
3227 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3228 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3230 deemph_reg_value
= 43;
3231 margin_reg_value
= 154;
3241 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3242 margin_reg_value
, uniq_trans_scale
);
3248 gen4_signal_levels(uint8_t train_set
)
3250 uint32_t signal_levels
= 0;
3252 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3255 signal_levels
|= DP_VOLTAGE_0_4
;
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3258 signal_levels
|= DP_VOLTAGE_0_6
;
3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3261 signal_levels
|= DP_VOLTAGE_0_8
;
3263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3264 signal_levels
|= DP_VOLTAGE_1_2
;
3267 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3268 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3270 signal_levels
|= DP_PRE_EMPHASIS_0
;
3272 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3273 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3275 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3276 signal_levels
|= DP_PRE_EMPHASIS_6
;
3278 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3279 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3282 return signal_levels
;
3285 /* Gen6's DP voltage swing and pre-emphasis control */
3287 gen6_edp_signal_levels(uint8_t train_set
)
3289 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3290 DP_TRAIN_PRE_EMPHASIS_MASK
);
3291 switch (signal_levels
) {
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3294 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3296 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3299 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3302 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3305 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3307 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3308 "0x%x\n", signal_levels
);
3309 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3313 /* Gen7's DP voltage swing and pre-emphasis control */
3315 gen7_edp_signal_levels(uint8_t train_set
)
3317 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3318 DP_TRAIN_PRE_EMPHASIS_MASK
);
3319 switch (signal_levels
) {
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3321 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3323 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3325 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3328 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3330 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3333 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3335 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3338 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3339 "0x%x\n", signal_levels
);
3340 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3345 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3347 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3348 enum port port
= intel_dig_port
->port
;
3349 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3350 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3351 uint32_t signal_levels
, mask
= 0;
3352 uint8_t train_set
= intel_dp
->train_set
[0];
3354 if (HAS_DDI(dev_priv
)) {
3355 signal_levels
= ddi_signal_levels(intel_dp
);
3357 if (IS_BROXTON(dev_priv
))
3360 mask
= DDI_BUF_EMP_MASK
;
3361 } else if (IS_CHERRYVIEW(dev_priv
)) {
3362 signal_levels
= chv_signal_levels(intel_dp
);
3363 } else if (IS_VALLEYVIEW(dev_priv
)) {
3364 signal_levels
= vlv_signal_levels(intel_dp
);
3365 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3366 signal_levels
= gen7_edp_signal_levels(train_set
);
3367 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3368 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3369 signal_levels
= gen6_edp_signal_levels(train_set
);
3370 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3372 signal_levels
= gen4_signal_levels(train_set
);
3373 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3377 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3379 DRM_DEBUG_KMS("Using vswing level %d\n",
3380 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3381 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3382 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3383 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3385 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3387 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3388 POSTING_READ(intel_dp
->output_reg
);
3392 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3393 uint8_t dp_train_pat
)
3395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3396 struct drm_i915_private
*dev_priv
=
3397 to_i915(intel_dig_port
->base
.base
.dev
);
3399 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3401 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3402 POSTING_READ(intel_dp
->output_reg
);
3405 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3407 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3408 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3409 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3410 enum port port
= intel_dig_port
->port
;
3413 if (!HAS_DDI(dev_priv
))
3416 val
= I915_READ(DP_TP_CTL(port
));
3417 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3418 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3419 I915_WRITE(DP_TP_CTL(port
), val
);
3422 * On PORT_A we can have only eDP in SST mode. There the only reason
3423 * we need to set idle transmission mode is to work around a HW issue
3424 * where we enable the pipe while not in idle link-training mode.
3425 * In this case there is requirement to wait for a minimum number of
3426 * idle patterns to be sent.
3431 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3432 DP_TP_STATUS_IDLE_DONE
,
3433 DP_TP_STATUS_IDLE_DONE
,
3435 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3439 intel_dp_link_down(struct intel_dp
*intel_dp
)
3441 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3442 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3443 enum port port
= intel_dig_port
->port
;
3444 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3445 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3446 uint32_t DP
= intel_dp
->DP
;
3448 if (WARN_ON(HAS_DDI(dev_priv
)))
3451 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3454 DRM_DEBUG_KMS("\n");
3456 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3457 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3458 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3459 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3461 if (IS_CHERRYVIEW(dev_priv
))
3462 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3464 DP
&= ~DP_LINK_TRAIN_MASK
;
3465 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3467 I915_WRITE(intel_dp
->output_reg
, DP
);
3468 POSTING_READ(intel_dp
->output_reg
);
3470 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3471 I915_WRITE(intel_dp
->output_reg
, DP
);
3472 POSTING_READ(intel_dp
->output_reg
);
3475 * HW workaround for IBX, we need to move the port
3476 * to transcoder A after disabling it to allow the
3477 * matching HDMI port to be enabled on transcoder A.
3479 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3481 * We get CPU/PCH FIFO underruns on the other pipe when
3482 * doing the workaround. Sweep them under the rug.
3484 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3485 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3487 /* always enable with pattern 1 (as per spec) */
3488 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3489 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3490 I915_WRITE(intel_dp
->output_reg
, DP
);
3491 POSTING_READ(intel_dp
->output_reg
);
3494 I915_WRITE(intel_dp
->output_reg
, DP
);
3495 POSTING_READ(intel_dp
->output_reg
);
3497 intel_wait_for_vblank_if_active(&dev_priv
->drm
, PIPE_A
);
3498 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3499 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3502 msleep(intel_dp
->panel_power_down_delay
);
3508 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3510 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3511 sizeof(intel_dp
->dpcd
)) < 0)
3512 return false; /* aux transfer failed */
3514 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3516 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3520 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3522 struct drm_i915_private
*dev_priv
=
3523 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3525 /* this function is meant to be called only once */
3526 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3528 if (!intel_dp_read_dpcd(intel_dp
))
3531 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3532 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3533 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3535 /* Check if the panel supports PSR */
3536 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3538 sizeof(intel_dp
->psr_dpcd
));
3539 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3540 dev_priv
->psr
.sink_support
= true;
3541 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3544 if (INTEL_GEN(dev_priv
) >= 9 &&
3545 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3546 uint8_t frame_sync_cap
;
3548 dev_priv
->psr
.sink_support
= true;
3549 drm_dp_dpcd_read(&intel_dp
->aux
,
3550 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3551 &frame_sync_cap
, 1);
3552 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3553 /* PSR2 needs frame sync as well */
3554 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3555 DRM_DEBUG_KMS("PSR2 %s on sink",
3556 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3559 /* Read the eDP Display control capabilities registers */
3560 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3561 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3562 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3563 sizeof(intel_dp
->edp_dpcd
))
3564 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3565 intel_dp
->edp_dpcd
);
3567 /* Intermediate frequency support */
3568 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3569 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3572 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3573 sink_rates
, sizeof(sink_rates
));
3575 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3576 int val
= le16_to_cpu(sink_rates
[i
]);
3581 /* Value read is in kHz while drm clock is saved in deca-kHz */
3582 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3584 intel_dp
->num_sink_rates
= i
;
3592 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3594 if (!intel_dp_read_dpcd(intel_dp
))
3597 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3598 &intel_dp
->sink_count
, 1) < 0)
3602 * Sink count can change between short pulse hpd hence
3603 * a member variable in intel_dp will track any changes
3604 * between short pulse interrupts.
3606 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3609 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3610 * a dongle is present but no display. Unless we require to know
3611 * if a dongle is present or not, we don't need to update
3612 * downstream port information. So, an early return here saves
3613 * time from performing other operations which are not required.
3615 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3618 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3619 DP_DWN_STRM_PORT_PRESENT
))
3620 return true; /* native DP sink */
3622 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3623 return true; /* no per-port downstream info */
3625 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3626 intel_dp
->downstream_ports
,
3627 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3628 return false; /* downstream port status fetch failed */
3634 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3638 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3641 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3642 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3643 buf
[0], buf
[1], buf
[2]);
3645 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3646 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3647 buf
[0], buf
[1], buf
[2]);
3651 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3655 if (!i915
.enable_dp_mst
)
3658 if (!intel_dp
->can_mst
)
3661 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3664 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3667 return buf
[0] & DP_MST_CAP
;
3671 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3673 if (!i915
.enable_dp_mst
)
3676 if (!intel_dp
->can_mst
)
3679 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3681 if (intel_dp
->is_mst
)
3682 DRM_DEBUG_KMS("Sink is MST capable\n");
3684 DRM_DEBUG_KMS("Sink is not MST capable\n");
3686 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3690 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3692 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3693 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3694 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3700 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3701 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3706 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3707 buf
& ~DP_TEST_SINK_START
) < 0) {
3708 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3714 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3716 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3717 DP_TEST_SINK_MISC
, &buf
) < 0) {
3721 count
= buf
& DP_TEST_COUNT_MASK
;
3722 } while (--attempts
&& count
);
3724 if (attempts
== 0) {
3725 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3730 hsw_enable_ips(intel_crtc
);
3734 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3736 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3737 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3738 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3742 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3745 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3748 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3751 if (buf
& DP_TEST_SINK_START
) {
3752 ret
= intel_dp_sink_crc_stop(intel_dp
);
3757 hsw_disable_ips(intel_crtc
);
3759 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3760 buf
| DP_TEST_SINK_START
) < 0) {
3761 hsw_enable_ips(intel_crtc
);
3765 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3769 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3771 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3772 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3773 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3778 ret
= intel_dp_sink_crc_start(intel_dp
);
3783 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3785 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3786 DP_TEST_SINK_MISC
, &buf
) < 0) {
3790 count
= buf
& DP_TEST_COUNT_MASK
;
3792 } while (--attempts
&& count
== 0);
3794 if (attempts
== 0) {
3795 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3800 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3806 intel_dp_sink_crc_stop(intel_dp
);
3811 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3813 return drm_dp_dpcd_read(&intel_dp
->aux
,
3814 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3815 sink_irq_vector
, 1) == 1;
3819 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3823 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3825 sink_irq_vector
, 14);
3832 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3834 uint8_t test_result
= DP_TEST_ACK
;
3838 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3840 uint8_t test_result
= DP_TEST_NAK
;
3844 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3846 uint8_t test_result
= DP_TEST_NAK
;
3847 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3848 struct drm_connector
*connector
= &intel_connector
->base
;
3850 if (intel_connector
->detect_edid
== NULL
||
3851 connector
->edid_corrupt
||
3852 intel_dp
->aux
.i2c_defer_count
> 6) {
3853 /* Check EDID read for NACKs, DEFERs and corruption
3854 * (DP CTS 1.2 Core r1.1)
3855 * 4.2.2.4 : Failed EDID read, I2C_NAK
3856 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3857 * 4.2.2.6 : EDID corruption detected
3858 * Use failsafe mode for all cases
3860 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3861 intel_dp
->aux
.i2c_defer_count
> 0)
3862 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3863 intel_dp
->aux
.i2c_nack_count
,
3864 intel_dp
->aux
.i2c_defer_count
);
3865 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3867 struct edid
*block
= intel_connector
->detect_edid
;
3869 /* We have to write the checksum
3870 * of the last block read
3872 block
+= intel_connector
->detect_edid
->extensions
;
3874 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3875 DP_TEST_EDID_CHECKSUM
,
3878 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3880 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3881 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3884 /* Set test active flag here so userspace doesn't interrupt things */
3885 intel_dp
->compliance_test_active
= 1;
3890 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3892 uint8_t test_result
= DP_TEST_NAK
;
3896 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3898 uint8_t response
= DP_TEST_NAK
;
3902 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3904 DRM_DEBUG_KMS("Could not read test request from sink\n");
3909 case DP_TEST_LINK_TRAINING
:
3910 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3911 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3912 response
= intel_dp_autotest_link_training(intel_dp
);
3914 case DP_TEST_LINK_VIDEO_PATTERN
:
3915 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3916 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3917 response
= intel_dp_autotest_video_pattern(intel_dp
);
3919 case DP_TEST_LINK_EDID_READ
:
3920 DRM_DEBUG_KMS("EDID test requested\n");
3921 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3922 response
= intel_dp_autotest_edid(intel_dp
);
3924 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3925 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3926 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3927 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3930 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3935 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3939 DRM_DEBUG_KMS("Could not write test response to sink\n");
3943 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3947 if (intel_dp
->is_mst
) {
3952 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3956 /* check link status - esi[10] = 0x200c */
3957 if (intel_dp
->active_mst_links
&&
3958 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3959 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3960 intel_dp_start_link_train(intel_dp
);
3961 intel_dp_stop_link_train(intel_dp
);
3964 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3965 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3968 for (retry
= 0; retry
< 3; retry
++) {
3970 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3971 DP_SINK_COUNT_ESI
+1,
3978 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3980 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3988 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3989 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3990 intel_dp
->is_mst
= false;
3991 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3992 /* send a hotplug event */
3993 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4000 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4002 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4003 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4004 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4006 /* Suppress underruns caused by re-training */
4007 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4008 if (crtc
->config
->has_pch_encoder
)
4009 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4010 intel_crtc_pch_transcoder(crtc
), false);
4012 intel_dp_start_link_train(intel_dp
);
4013 intel_dp_stop_link_train(intel_dp
);
4015 /* Keep underrun reporting disabled until things are stable */
4016 intel_wait_for_vblank(&dev_priv
->drm
, crtc
->pipe
);
4018 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4019 if (crtc
->config
->has_pch_encoder
)
4020 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4021 intel_crtc_pch_transcoder(crtc
), true);
4025 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4027 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4028 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4029 u8 link_status
[DP_LINK_STATUS_SIZE
];
4031 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4033 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4034 DRM_ERROR("Failed to get link status\n");
4038 if (!intel_encoder
->base
.crtc
)
4041 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4044 /* if link training is requested we should perform it always */
4045 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4046 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4047 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4048 intel_encoder
->base
.name
);
4050 intel_dp_retrain_link(intel_dp
);
4055 * According to DP spec
4058 * 2. Configure link according to Receiver Capabilities
4059 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4060 * 4. Check link status on receipt of hot-plug interrupt
4062 * intel_dp_short_pulse - handles short pulse interrupts
4063 * when full detection is not required.
4064 * Returns %true if short pulse is handled and full detection
4065 * is NOT required and %false otherwise.
4068 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4070 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4071 u8 sink_irq_vector
= 0;
4072 u8 old_sink_count
= intel_dp
->sink_count
;
4076 * Clearing compliance test variables to allow capturing
4077 * of values for next automated test request.
4079 intel_dp
->compliance_test_active
= 0;
4080 intel_dp
->compliance_test_type
= 0;
4081 intel_dp
->compliance_test_data
= 0;
4084 * Now read the DPCD to see if it's actually running
4085 * If the current value of sink count doesn't match with
4086 * the value that was stored earlier or dpcd read failed
4087 * we need to do full detection
4089 ret
= intel_dp_get_dpcd(intel_dp
);
4091 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4092 /* No need to proceed if we are going to do full detect */
4096 /* Try to read the source of the interrupt */
4097 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4098 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4099 sink_irq_vector
!= 0) {
4100 /* Clear interrupt source */
4101 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4102 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4105 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4106 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4107 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4108 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4111 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4112 intel_dp_check_link_status(intel_dp
);
4113 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4118 /* XXX this is probably wrong for multiple downstream ports */
4119 static enum drm_connector_status
4120 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4122 uint8_t *dpcd
= intel_dp
->dpcd
;
4125 if (!intel_dp_get_dpcd(intel_dp
))
4126 return connector_status_disconnected
;
4128 if (is_edp(intel_dp
))
4129 return connector_status_connected
;
4131 /* if there's no downstream port, we're done */
4132 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4133 return connector_status_connected
;
4135 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4136 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4137 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4139 return intel_dp
->sink_count
?
4140 connector_status_connected
: connector_status_disconnected
;
4143 if (intel_dp_can_mst(intel_dp
))
4144 return connector_status_connected
;
4146 /* If no HPD, poke DDC gently */
4147 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4148 return connector_status_connected
;
4150 /* Well we tried, say unknown for unreliable port types */
4151 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4152 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4153 if (type
== DP_DS_PORT_TYPE_VGA
||
4154 type
== DP_DS_PORT_TYPE_NON_EDID
)
4155 return connector_status_unknown
;
4157 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4158 DP_DWN_STRM_PORT_TYPE_MASK
;
4159 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4160 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4161 return connector_status_unknown
;
4164 /* Anything else is out of spec, warn and ignore */
4165 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4166 return connector_status_disconnected
;
4169 static enum drm_connector_status
4170 edp_detect(struct intel_dp
*intel_dp
)
4172 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4173 enum drm_connector_status status
;
4175 status
= intel_panel_detect(dev
);
4176 if (status
== connector_status_unknown
)
4177 status
= connector_status_connected
;
4182 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4183 struct intel_digital_port
*port
)
4187 switch (port
->port
) {
4191 bit
= SDE_PORTB_HOTPLUG
;
4194 bit
= SDE_PORTC_HOTPLUG
;
4197 bit
= SDE_PORTD_HOTPLUG
;
4200 MISSING_CASE(port
->port
);
4204 return I915_READ(SDEISR
) & bit
;
4207 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4208 struct intel_digital_port
*port
)
4212 switch (port
->port
) {
4216 bit
= SDE_PORTB_HOTPLUG_CPT
;
4219 bit
= SDE_PORTC_HOTPLUG_CPT
;
4222 bit
= SDE_PORTD_HOTPLUG_CPT
;
4225 bit
= SDE_PORTE_HOTPLUG_SPT
;
4228 MISSING_CASE(port
->port
);
4232 return I915_READ(SDEISR
) & bit
;
4235 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4236 struct intel_digital_port
*port
)
4240 switch (port
->port
) {
4242 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4245 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4248 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4251 MISSING_CASE(port
->port
);
4255 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4258 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4259 struct intel_digital_port
*port
)
4263 switch (port
->port
) {
4265 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4268 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4271 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4274 MISSING_CASE(port
->port
);
4278 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4281 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4282 struct intel_digital_port
*intel_dig_port
)
4284 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4288 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4291 bit
= BXT_DE_PORT_HP_DDIA
;
4294 bit
= BXT_DE_PORT_HP_DDIB
;
4297 bit
= BXT_DE_PORT_HP_DDIC
;
4304 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4308 * intel_digital_port_connected - is the specified port connected?
4309 * @dev_priv: i915 private structure
4310 * @port: the port to test
4312 * Return %true if @port is connected, %false otherwise.
4314 static bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4315 struct intel_digital_port
*port
)
4317 if (HAS_PCH_IBX(dev_priv
))
4318 return ibx_digital_port_connected(dev_priv
, port
);
4319 else if (HAS_PCH_SPLIT(dev_priv
))
4320 return cpt_digital_port_connected(dev_priv
, port
);
4321 else if (IS_BROXTON(dev_priv
))
4322 return bxt_digital_port_connected(dev_priv
, port
);
4323 else if (IS_GM45(dev_priv
))
4324 return gm45_digital_port_connected(dev_priv
, port
);
4326 return g4x_digital_port_connected(dev_priv
, port
);
4329 static struct edid
*
4330 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4332 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4334 /* use cached edid if we have one */
4335 if (intel_connector
->edid
) {
4337 if (IS_ERR(intel_connector
->edid
))
4340 return drm_edid_duplicate(intel_connector
->edid
);
4342 return drm_get_edid(&intel_connector
->base
,
4343 &intel_dp
->aux
.ddc
);
4347 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4349 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4352 intel_dp_unset_edid(intel_dp
);
4353 edid
= intel_dp_get_edid(intel_dp
);
4354 intel_connector
->detect_edid
= edid
;
4356 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4357 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4359 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4363 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4365 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4367 kfree(intel_connector
->detect_edid
);
4368 intel_connector
->detect_edid
= NULL
;
4370 intel_dp
->has_audio
= false;
4373 static enum drm_connector_status
4374 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4376 struct drm_connector
*connector
= &intel_connector
->base
;
4377 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4378 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4379 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4380 struct drm_device
*dev
= connector
->dev
;
4381 enum drm_connector_status status
;
4382 enum intel_display_power_domain power_domain
;
4383 u8 sink_irq_vector
= 0;
4385 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4386 intel_display_power_get(to_i915(dev
), power_domain
);
4388 /* Can't disconnect eDP, but you can close the lid... */
4389 if (is_edp(intel_dp
))
4390 status
= edp_detect(intel_dp
);
4391 else if (intel_digital_port_connected(to_i915(dev
),
4392 dp_to_dig_port(intel_dp
)))
4393 status
= intel_dp_detect_dpcd(intel_dp
);
4395 status
= connector_status_disconnected
;
4397 if (status
== connector_status_disconnected
) {
4398 intel_dp
->compliance_test_active
= 0;
4399 intel_dp
->compliance_test_type
= 0;
4400 intel_dp
->compliance_test_data
= 0;
4402 if (intel_dp
->is_mst
) {
4403 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4405 intel_dp
->mst_mgr
.mst_state
);
4406 intel_dp
->is_mst
= false;
4407 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4414 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4415 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4417 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4418 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4419 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4421 intel_dp_print_rates(intel_dp
);
4423 intel_dp_probe_oui(intel_dp
);
4425 intel_dp_print_hw_revision(intel_dp
);
4426 intel_dp_print_sw_revision(intel_dp
);
4428 intel_dp_configure_mst(intel_dp
);
4430 if (intel_dp
->is_mst
) {
4432 * If we are in MST mode then this connector
4433 * won't appear connected or have anything
4436 status
= connector_status_disconnected
;
4438 } else if (connector
->status
== connector_status_connected
) {
4440 * If display was connected already and is still connected
4441 * check links status, there has been known issues of
4442 * link loss triggerring long pulse!!!!
4444 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4445 intel_dp_check_link_status(intel_dp
);
4446 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4451 * Clearing NACK and defer counts to get their exact values
4452 * while reading EDID which are required by Compliance tests
4453 * 4.2.2.4 and 4.2.2.5
4455 intel_dp
->aux
.i2c_nack_count
= 0;
4456 intel_dp
->aux
.i2c_defer_count
= 0;
4458 intel_dp_set_edid(intel_dp
);
4459 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4460 status
= connector_status_connected
;
4461 intel_dp
->detect_done
= true;
4463 /* Try to read the source of the interrupt */
4464 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4465 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4466 sink_irq_vector
!= 0) {
4467 /* Clear interrupt source */
4468 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4469 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4472 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4473 intel_dp_handle_test_request(intel_dp
);
4474 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4475 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4479 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4480 intel_dp_unset_edid(intel_dp
);
4482 intel_display_power_put(to_i915(dev
), power_domain
);
4486 static enum drm_connector_status
4487 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4489 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4490 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4491 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4492 enum drm_connector_status status
= connector
->status
;
4494 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4495 connector
->base
.id
, connector
->name
);
4497 if (intel_dp
->is_mst
) {
4498 /* MST devices are disconnected from a monitor POV */
4499 intel_dp_unset_edid(intel_dp
);
4500 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4501 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4502 return connector_status_disconnected
;
4505 /* If full detect is not performed yet, do a full detect */
4506 if (!intel_dp
->detect_done
)
4507 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4509 intel_dp
->detect_done
= false;
4515 intel_dp_force(struct drm_connector
*connector
)
4517 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4518 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4519 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4520 enum intel_display_power_domain power_domain
;
4522 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4523 connector
->base
.id
, connector
->name
);
4524 intel_dp_unset_edid(intel_dp
);
4526 if (connector
->status
!= connector_status_connected
)
4529 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4530 intel_display_power_get(dev_priv
, power_domain
);
4532 intel_dp_set_edid(intel_dp
);
4534 intel_display_power_put(dev_priv
, power_domain
);
4536 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4537 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4540 static int intel_dp_get_modes(struct drm_connector
*connector
)
4542 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4545 edid
= intel_connector
->detect_edid
;
4547 int ret
= intel_connector_update_modes(connector
, edid
);
4552 /* if eDP has no EDID, fall back to fixed mode */
4553 if (is_edp(intel_attached_dp(connector
)) &&
4554 intel_connector
->panel
.fixed_mode
) {
4555 struct drm_display_mode
*mode
;
4557 mode
= drm_mode_duplicate(connector
->dev
,
4558 intel_connector
->panel
.fixed_mode
);
4560 drm_mode_probed_add(connector
, mode
);
4569 intel_dp_detect_audio(struct drm_connector
*connector
)
4571 bool has_audio
= false;
4574 edid
= to_intel_connector(connector
)->detect_edid
;
4576 has_audio
= drm_detect_monitor_audio(edid
);
4582 intel_dp_set_property(struct drm_connector
*connector
,
4583 struct drm_property
*property
,
4586 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4587 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4588 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4589 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4592 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4596 if (property
== dev_priv
->force_audio_property
) {
4600 if (i
== intel_dp
->force_audio
)
4603 intel_dp
->force_audio
= i
;
4605 if (i
== HDMI_AUDIO_AUTO
)
4606 has_audio
= intel_dp_detect_audio(connector
);
4608 has_audio
= (i
== HDMI_AUDIO_ON
);
4610 if (has_audio
== intel_dp
->has_audio
)
4613 intel_dp
->has_audio
= has_audio
;
4617 if (property
== dev_priv
->broadcast_rgb_property
) {
4618 bool old_auto
= intel_dp
->color_range_auto
;
4619 bool old_range
= intel_dp
->limited_color_range
;
4622 case INTEL_BROADCAST_RGB_AUTO
:
4623 intel_dp
->color_range_auto
= true;
4625 case INTEL_BROADCAST_RGB_FULL
:
4626 intel_dp
->color_range_auto
= false;
4627 intel_dp
->limited_color_range
= false;
4629 case INTEL_BROADCAST_RGB_LIMITED
:
4630 intel_dp
->color_range_auto
= false;
4631 intel_dp
->limited_color_range
= true;
4637 if (old_auto
== intel_dp
->color_range_auto
&&
4638 old_range
== intel_dp
->limited_color_range
)
4644 if (is_edp(intel_dp
) &&
4645 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4646 if (val
== DRM_MODE_SCALE_NONE
) {
4647 DRM_DEBUG_KMS("no scaling not supported\n");
4650 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4651 val
== DRM_MODE_SCALE_CENTER
) {
4652 DRM_DEBUG_KMS("centering not supported\n");
4656 if (intel_connector
->panel
.fitting_mode
== val
) {
4657 /* the eDP scaling property is not changed */
4660 intel_connector
->panel
.fitting_mode
= val
;
4668 if (intel_encoder
->base
.crtc
)
4669 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4675 intel_dp_connector_register(struct drm_connector
*connector
)
4677 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4680 ret
= intel_connector_register(connector
);
4684 i915_debugfs_connector_add(connector
);
4686 DRM_DEBUG_KMS("registering %s bus for %s\n",
4687 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4689 intel_dp
->aux
.dev
= connector
->kdev
;
4690 return drm_dp_aux_register(&intel_dp
->aux
);
4694 intel_dp_connector_unregister(struct drm_connector
*connector
)
4696 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4697 intel_connector_unregister(connector
);
4701 intel_dp_connector_destroy(struct drm_connector
*connector
)
4703 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4705 kfree(intel_connector
->detect_edid
);
4707 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4708 kfree(intel_connector
->edid
);
4710 /* Can't call is_edp() since the encoder may have been destroyed
4712 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4713 intel_panel_fini(&intel_connector
->panel
);
4715 drm_connector_cleanup(connector
);
4719 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4721 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4722 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4724 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4725 if (is_edp(intel_dp
)) {
4726 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4728 * vdd might still be enabled do to the delayed vdd off.
4729 * Make sure vdd is actually turned off here.
4732 edp_panel_vdd_off_sync(intel_dp
);
4733 pps_unlock(intel_dp
);
4735 if (intel_dp
->edp_notifier
.notifier_call
) {
4736 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4737 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4741 intel_dp_aux_fini(intel_dp
);
4743 drm_encoder_cleanup(encoder
);
4744 kfree(intel_dig_port
);
4747 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4749 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4751 if (!is_edp(intel_dp
))
4755 * vdd might still be enabled do to the delayed vdd off.
4756 * Make sure vdd is actually turned off here.
4758 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4760 edp_panel_vdd_off_sync(intel_dp
);
4761 pps_unlock(intel_dp
);
4764 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4766 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4767 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4769 enum intel_display_power_domain power_domain
;
4771 lockdep_assert_held(&dev_priv
->pps_mutex
);
4773 if (!edp_have_panel_vdd(intel_dp
))
4777 * The VDD bit needs a power domain reference, so if the bit is
4778 * already enabled when we boot or resume, grab this reference and
4779 * schedule a vdd off, so we don't hold on to the reference
4782 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4783 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4784 intel_display_power_get(dev_priv
, power_domain
);
4786 edp_panel_vdd_schedule_off(intel_dp
);
4789 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4791 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4792 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4793 struct intel_lspcon
*lspcon
= &intel_dig_port
->lspcon
;
4794 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4796 if (!HAS_DDI(dev_priv
))
4797 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4799 if (IS_GEN9(dev_priv
) && lspcon
->active
)
4800 lspcon_resume(lspcon
);
4802 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4807 /* Reinit the power sequencer, in case BIOS did something with it. */
4808 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4809 intel_edp_panel_vdd_sanitize(intel_dp
);
4811 pps_unlock(intel_dp
);
4814 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4815 .dpms
= drm_atomic_helper_connector_dpms
,
4816 .detect
= intel_dp_detect
,
4817 .force
= intel_dp_force
,
4818 .fill_modes
= drm_helper_probe_single_connector_modes
,
4819 .set_property
= intel_dp_set_property
,
4820 .atomic_get_property
= intel_connector_atomic_get_property
,
4821 .late_register
= intel_dp_connector_register
,
4822 .early_unregister
= intel_dp_connector_unregister
,
4823 .destroy
= intel_dp_connector_destroy
,
4824 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4825 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4828 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4829 .get_modes
= intel_dp_get_modes
,
4830 .mode_valid
= intel_dp_mode_valid
,
4833 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4834 .reset
= intel_dp_encoder_reset
,
4835 .destroy
= intel_dp_encoder_destroy
,
4839 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4841 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4842 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4843 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4844 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4845 enum intel_display_power_domain power_domain
;
4846 enum irqreturn ret
= IRQ_NONE
;
4848 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4849 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4850 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
4852 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4854 * vdd off can generate a long pulse on eDP which
4855 * would require vdd on to handle it, and thus we
4856 * would end up in an endless cycle of
4857 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4859 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4860 port_name(intel_dig_port
->port
));
4864 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4865 port_name(intel_dig_port
->port
),
4866 long_hpd
? "long" : "short");
4869 intel_dp
->detect_done
= false;
4873 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4874 intel_display_power_get(dev_priv
, power_domain
);
4876 if (intel_dp
->is_mst
) {
4877 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4879 * If we were in MST mode, and device is not
4880 * there, get out of MST mode
4882 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4883 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4884 intel_dp
->is_mst
= false;
4885 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4887 intel_dp
->detect_done
= false;
4892 if (!intel_dp
->is_mst
) {
4893 if (!intel_dp_short_pulse(intel_dp
)) {
4894 intel_dp
->detect_done
= false;
4902 intel_display_power_put(dev_priv
, power_domain
);
4907 /* check the VBT to see whether the eDP is on another port */
4908 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4910 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4913 * eDP not supported on g4x. so bail out early just
4914 * for a bit extra safety in case the VBT is bonkers.
4916 if (INTEL_INFO(dev
)->gen
< 5)
4922 return intel_bios_is_port_edp(dev_priv
, port
);
4926 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4928 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4930 intel_attach_force_audio_property(connector
);
4931 intel_attach_broadcast_rgb_property(connector
);
4932 intel_dp
->color_range_auto
= true;
4934 if (is_edp(intel_dp
)) {
4935 drm_mode_create_scaling_mode_property(connector
->dev
);
4936 drm_object_attach_property(
4938 connector
->dev
->mode_config
.scaling_mode_property
,
4939 DRM_MODE_SCALE_ASPECT
);
4940 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4944 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4946 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4947 intel_dp
->last_power_on
= jiffies
;
4948 intel_dp
->last_backlight_off
= jiffies
;
4952 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4953 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4955 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4956 struct pps_registers regs
;
4958 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4960 /* Workaround: Need to write PP_CONTROL with the unlock key as
4961 * the very first thing. */
4962 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4964 pp_on
= I915_READ(regs
.pp_on
);
4965 pp_off
= I915_READ(regs
.pp_off
);
4966 if (!IS_BROXTON(dev_priv
)) {
4967 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4968 pp_div
= I915_READ(regs
.pp_div
);
4971 /* Pull timing values out of registers */
4972 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4973 PANEL_POWER_UP_DELAY_SHIFT
;
4975 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4976 PANEL_LIGHT_ON_DELAY_SHIFT
;
4978 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4979 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4981 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4982 PANEL_POWER_DOWN_DELAY_SHIFT
;
4984 if (IS_BROXTON(dev_priv
)) {
4985 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4986 BXT_POWER_CYCLE_DELAY_SHIFT
;
4988 seq
->t11_t12
= (tmp
- 1) * 1000;
4992 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4993 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4998 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5000 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5002 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5006 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
5007 struct intel_dp
*intel_dp
)
5009 struct edp_power_seq hw
;
5010 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5012 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
5014 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5015 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5016 DRM_ERROR("PPS state mismatch\n");
5017 intel_pps_dump_state("sw", sw
);
5018 intel_pps_dump_state("hw", &hw
);
5023 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5024 struct intel_dp
*intel_dp
)
5026 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5027 struct edp_power_seq cur
, vbt
, spec
,
5028 *final
= &intel_dp
->pps_delays
;
5030 lockdep_assert_held(&dev_priv
->pps_mutex
);
5032 /* already initialized? */
5033 if (final
->t11_t12
!= 0)
5036 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5038 intel_pps_dump_state("cur", &cur
);
5040 vbt
= dev_priv
->vbt
.edp
.pps
;
5042 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5043 * our hw here, which are all in 100usec. */
5044 spec
.t1_t3
= 210 * 10;
5045 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5046 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5047 spec
.t10
= 500 * 10;
5048 /* This one is special and actually in units of 100ms, but zero
5049 * based in the hw (so we need to add 100 ms). But the sw vbt
5050 * table multiplies it with 1000 to make it in units of 100usec,
5052 spec
.t11_t12
= (510 + 100) * 10;
5054 intel_pps_dump_state("vbt", &vbt
);
5056 /* Use the max of the register settings and vbt. If both are
5057 * unset, fall back to the spec limits. */
5058 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5060 max(cur.field, vbt.field))
5061 assign_final(t1_t3
);
5065 assign_final(t11_t12
);
5068 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5069 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5070 intel_dp
->backlight_on_delay
= get_delay(t8
);
5071 intel_dp
->backlight_off_delay
= get_delay(t9
);
5072 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5073 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5076 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5077 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5078 intel_dp
->panel_power_cycle_delay
);
5080 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5081 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5084 * We override the HW backlight delays to 1 because we do manual waits
5085 * on them. For T8, even BSpec recommends doing it. For T9, if we
5086 * don't do this, we'll end up waiting for the backlight off delay
5087 * twice: once when we do the manual sleep, and once when we disable
5088 * the panel and wait for the PP_STATUS bit to become zero.
5095 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5096 struct intel_dp
*intel_dp
)
5098 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5099 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5100 int div
= dev_priv
->rawclk_freq
/ 1000;
5101 struct pps_registers regs
;
5102 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5103 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5105 lockdep_assert_held(&dev_priv
->pps_mutex
);
5107 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5109 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5110 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5111 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5112 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5113 /* Compute the divisor for the pp clock, simply match the Bspec
5115 if (IS_BROXTON(dev_priv
)) {
5116 pp_div
= I915_READ(regs
.pp_ctrl
);
5117 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5118 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5119 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5121 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5122 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5123 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5126 /* Haswell doesn't have any port selection bits for the panel
5127 * power sequencer any more. */
5128 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5129 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5130 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5132 port_sel
= PANEL_PORT_SELECT_DPA
;
5134 port_sel
= PANEL_PORT_SELECT_DPD
;
5139 I915_WRITE(regs
.pp_on
, pp_on
);
5140 I915_WRITE(regs
.pp_off
, pp_off
);
5141 if (IS_BROXTON(dev_priv
))
5142 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5144 I915_WRITE(regs
.pp_div
, pp_div
);
5146 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5147 I915_READ(regs
.pp_on
),
5148 I915_READ(regs
.pp_off
),
5149 IS_BROXTON(dev_priv
) ?
5150 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5151 I915_READ(regs
.pp_div
));
5154 static void intel_dp_pps_init(struct drm_device
*dev
,
5155 struct intel_dp
*intel_dp
)
5157 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5159 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5160 vlv_initial_power_sequencer_setup(intel_dp
);
5162 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5163 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5168 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5169 * @dev_priv: i915 device
5170 * @crtc_state: a pointer to the active intel_crtc_state
5171 * @refresh_rate: RR to be programmed
5173 * This function gets called when refresh rate (RR) has to be changed from
5174 * one frequency to another. Switches can be between high and low RR
5175 * supported by the panel or to any other RR based on media playback (in
5176 * this case, RR value needs to be passed from user space).
5178 * The caller of this function needs to take a lock on dev_priv->drrs.
5180 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5181 struct intel_crtc_state
*crtc_state
,
5184 struct intel_encoder
*encoder
;
5185 struct intel_digital_port
*dig_port
= NULL
;
5186 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5188 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5190 if (refresh_rate
<= 0) {
5191 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5195 if (intel_dp
== NULL
) {
5196 DRM_DEBUG_KMS("DRRS not supported.\n");
5201 * FIXME: This needs proper synchronization with psr state for some
5202 * platforms that cannot have PSR and DRRS enabled at the same time.
5205 dig_port
= dp_to_dig_port(intel_dp
);
5206 encoder
= &dig_port
->base
;
5207 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5210 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5214 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5215 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5219 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5221 index
= DRRS_LOW_RR
;
5223 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5225 "DRRS requested for previously set RR...ignoring\n");
5229 if (!crtc_state
->base
.active
) {
5230 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5234 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5237 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5240 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5244 DRM_ERROR("Unsupported refreshrate type\n");
5246 } else if (INTEL_GEN(dev_priv
) > 6) {
5247 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5250 val
= I915_READ(reg
);
5251 if (index
> DRRS_HIGH_RR
) {
5252 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5253 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5255 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5257 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5258 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5260 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5262 I915_WRITE(reg
, val
);
5265 dev_priv
->drrs
.refresh_rate_type
= index
;
5267 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5271 * intel_edp_drrs_enable - init drrs struct if supported
5272 * @intel_dp: DP struct
5273 * @crtc_state: A pointer to the active crtc state.
5275 * Initializes frontbuffer_bits and drrs.dp
5277 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5278 struct intel_crtc_state
*crtc_state
)
5280 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5281 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5283 if (!crtc_state
->has_drrs
) {
5284 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5288 mutex_lock(&dev_priv
->drrs
.mutex
);
5289 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5290 DRM_ERROR("DRRS already enabled\n");
5294 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5296 dev_priv
->drrs
.dp
= intel_dp
;
5299 mutex_unlock(&dev_priv
->drrs
.mutex
);
5303 * intel_edp_drrs_disable - Disable DRRS
5304 * @intel_dp: DP struct
5305 * @old_crtc_state: Pointer to old crtc_state.
5308 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5309 struct intel_crtc_state
*old_crtc_state
)
5311 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5312 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5314 if (!old_crtc_state
->has_drrs
)
5317 mutex_lock(&dev_priv
->drrs
.mutex
);
5318 if (!dev_priv
->drrs
.dp
) {
5319 mutex_unlock(&dev_priv
->drrs
.mutex
);
5323 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5324 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5325 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5327 dev_priv
->drrs
.dp
= NULL
;
5328 mutex_unlock(&dev_priv
->drrs
.mutex
);
5330 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5333 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5335 struct drm_i915_private
*dev_priv
=
5336 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5337 struct intel_dp
*intel_dp
;
5339 mutex_lock(&dev_priv
->drrs
.mutex
);
5341 intel_dp
= dev_priv
->drrs
.dp
;
5347 * The delayed work can race with an invalidate hence we need to
5351 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5354 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5355 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5357 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5358 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5362 mutex_unlock(&dev_priv
->drrs
.mutex
);
5366 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5367 * @dev_priv: i915 device
5368 * @frontbuffer_bits: frontbuffer plane tracking bits
5370 * This function gets called everytime rendering on the given planes start.
5371 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5373 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5375 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5376 unsigned int frontbuffer_bits
)
5378 struct drm_crtc
*crtc
;
5381 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5384 cancel_delayed_work(&dev_priv
->drrs
.work
);
5386 mutex_lock(&dev_priv
->drrs
.mutex
);
5387 if (!dev_priv
->drrs
.dp
) {
5388 mutex_unlock(&dev_priv
->drrs
.mutex
);
5392 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5393 pipe
= to_intel_crtc(crtc
)->pipe
;
5395 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5396 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5398 /* invalidate means busy screen hence upclock */
5399 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5400 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5401 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5403 mutex_unlock(&dev_priv
->drrs
.mutex
);
5407 * intel_edp_drrs_flush - Restart Idleness DRRS
5408 * @dev_priv: i915 device
5409 * @frontbuffer_bits: frontbuffer plane tracking bits
5411 * This function gets called every time rendering on the given planes has
5412 * completed or flip on a crtc is completed. So DRRS should be upclocked
5413 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5414 * if no other planes are dirty.
5416 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5418 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5419 unsigned int frontbuffer_bits
)
5421 struct drm_crtc
*crtc
;
5424 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5427 cancel_delayed_work(&dev_priv
->drrs
.work
);
5429 mutex_lock(&dev_priv
->drrs
.mutex
);
5430 if (!dev_priv
->drrs
.dp
) {
5431 mutex_unlock(&dev_priv
->drrs
.mutex
);
5435 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5436 pipe
= to_intel_crtc(crtc
)->pipe
;
5438 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5439 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5441 /* flush means busy screen hence upclock */
5442 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5443 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5444 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5447 * flush also means no more activity hence schedule downclock, if all
5448 * other fbs are quiescent too
5450 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5451 schedule_delayed_work(&dev_priv
->drrs
.work
,
5452 msecs_to_jiffies(1000));
5453 mutex_unlock(&dev_priv
->drrs
.mutex
);
5457 * DOC: Display Refresh Rate Switching (DRRS)
5459 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5460 * which enables swtching between low and high refresh rates,
5461 * dynamically, based on the usage scenario. This feature is applicable
5462 * for internal panels.
5464 * Indication that the panel supports DRRS is given by the panel EDID, which
5465 * would list multiple refresh rates for one resolution.
5467 * DRRS is of 2 types - static and seamless.
5468 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5469 * (may appear as a blink on screen) and is used in dock-undock scenario.
5470 * Seamless DRRS involves changing RR without any visual effect to the user
5471 * and can be used during normal system usage. This is done by programming
5472 * certain registers.
5474 * Support for static/seamless DRRS may be indicated in the VBT based on
5475 * inputs from the panel spec.
5477 * DRRS saves power by switching to low RR based on usage scenarios.
5479 * The implementation is based on frontbuffer tracking implementation. When
5480 * there is a disturbance on the screen triggered by user activity or a periodic
5481 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5482 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5485 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5486 * and intel_edp_drrs_flush() are called.
5488 * DRRS can be further extended to support other internal panels and also
5489 * the scenario of video playback wherein RR is set based on the rate
5490 * requested by userspace.
5494 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5495 * @intel_connector: eDP connector
5496 * @fixed_mode: preferred mode of panel
5498 * This function is called only once at driver load to initialize basic
5502 * Downclock mode if panel supports it, else return NULL.
5503 * DRRS support is determined by the presence of downclock mode (apart
5504 * from VBT setting).
5506 static struct drm_display_mode
*
5507 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5508 struct drm_display_mode
*fixed_mode
)
5510 struct drm_connector
*connector
= &intel_connector
->base
;
5511 struct drm_device
*dev
= connector
->dev
;
5512 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5513 struct drm_display_mode
*downclock_mode
= NULL
;
5515 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5516 mutex_init(&dev_priv
->drrs
.mutex
);
5518 if (INTEL_INFO(dev
)->gen
<= 6) {
5519 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5523 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5524 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5528 downclock_mode
= intel_find_panel_downclock
5529 (dev
, fixed_mode
, connector
);
5531 if (!downclock_mode
) {
5532 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5536 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5538 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5539 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5540 return downclock_mode
;
5543 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5544 struct intel_connector
*intel_connector
)
5546 struct drm_connector
*connector
= &intel_connector
->base
;
5547 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5548 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5549 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5550 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5551 struct drm_display_mode
*fixed_mode
= NULL
;
5552 struct drm_display_mode
*downclock_mode
= NULL
;
5554 struct drm_display_mode
*scan
;
5556 enum pipe pipe
= INVALID_PIPE
;
5558 if (!is_edp(intel_dp
))
5562 * On IBX/CPT we may get here with LVDS already registered. Since the
5563 * driver uses the only internal power sequencer available for both
5564 * eDP and LVDS bail out early in this case to prevent interfering
5565 * with an already powered-on LVDS power sequencer.
5567 if (intel_get_lvds_encoder(dev
)) {
5568 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5569 DRM_INFO("LVDS was detected, not registering eDP\n");
5576 intel_dp_init_panel_power_timestamps(intel_dp
);
5577 intel_dp_pps_init(dev
, intel_dp
);
5578 intel_edp_panel_vdd_sanitize(intel_dp
);
5580 pps_unlock(intel_dp
);
5582 /* Cache DPCD and EDID for edp. */
5583 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5586 /* if this fails, presume the device is a ghost */
5587 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5591 mutex_lock(&dev
->mode_config
.mutex
);
5592 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5594 if (drm_add_edid_modes(connector
, edid
)) {
5595 drm_mode_connector_update_edid_property(connector
,
5597 drm_edid_to_eld(connector
, edid
);
5600 edid
= ERR_PTR(-EINVAL
);
5603 edid
= ERR_PTR(-ENOENT
);
5605 intel_connector
->edid
= edid
;
5607 /* prefer fixed mode from EDID if available */
5608 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5609 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5610 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5611 downclock_mode
= intel_dp_drrs_init(
5612 intel_connector
, fixed_mode
);
5617 /* fallback to VBT if available for eDP */
5618 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5619 fixed_mode
= drm_mode_duplicate(dev
,
5620 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5622 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5623 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5624 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5627 mutex_unlock(&dev
->mode_config
.mutex
);
5629 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5630 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5631 register_reboot_notifier(&intel_dp
->edp_notifier
);
5634 * Figure out the current pipe for the initial backlight setup.
5635 * If the current pipe isn't valid, try the PPS pipe, and if that
5636 * fails just assume pipe A.
5638 if (IS_CHERRYVIEW(dev_priv
))
5639 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5641 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5643 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5644 pipe
= intel_dp
->pps_pipe
;
5646 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5649 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5653 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5654 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5655 intel_panel_setup_backlight(connector
, pipe
);
5660 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5662 * vdd might still be enabled do to the delayed vdd off.
5663 * Make sure vdd is actually turned off here.
5666 edp_panel_vdd_off_sync(intel_dp
);
5667 pps_unlock(intel_dp
);
5673 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5674 struct intel_connector
*intel_connector
)
5676 struct drm_connector
*connector
= &intel_connector
->base
;
5677 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5678 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5679 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5680 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5681 enum port port
= intel_dig_port
->port
;
5684 if (WARN(intel_dig_port
->max_lanes
< 1,
5685 "Not enough lanes (%d) for DP on port %c\n",
5686 intel_dig_port
->max_lanes
, port_name(port
)))
5689 intel_dp
->pps_pipe
= INVALID_PIPE
;
5691 /* intel_dp vfuncs */
5692 if (INTEL_INFO(dev
)->gen
>= 9)
5693 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5694 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5695 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5696 else if (HAS_PCH_SPLIT(dev_priv
))
5697 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5699 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5701 if (INTEL_INFO(dev
)->gen
>= 9)
5702 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5704 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5706 if (HAS_DDI(dev_priv
))
5707 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5709 /* Preserve the current hw state. */
5710 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5711 intel_dp
->attached_connector
= intel_connector
;
5713 if (intel_dp_is_edp(dev
, port
))
5714 type
= DRM_MODE_CONNECTOR_eDP
;
5716 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5719 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5720 * for DP the encoder type can be set by the caller to
5721 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5723 if (type
== DRM_MODE_CONNECTOR_eDP
)
5724 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5726 /* eDP only on port B and/or C on vlv/chv */
5727 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
5728 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5731 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5732 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5735 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5736 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5738 connector
->interlace_allowed
= true;
5739 connector
->doublescan_allowed
= 0;
5741 intel_dp_aux_init(intel_dp
);
5743 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5744 edp_panel_vdd_work
);
5746 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5748 if (HAS_DDI(dev_priv
))
5749 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5751 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5753 /* Set up the hotplug pin. */
5756 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5759 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5760 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
5761 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5764 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5767 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5770 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5776 /* init MST on ports that can support it */
5777 if (HAS_DP_MST(dev
) && !is_edp(intel_dp
) &&
5778 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5779 intel_dp_mst_encoder_init(intel_dig_port
,
5780 intel_connector
->base
.base
.id
);
5782 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5783 intel_dp_aux_fini(intel_dp
);
5784 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5788 intel_dp_add_properties(intel_dp
, connector
);
5790 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5791 * 0xd. Failure to do so will result in spurious interrupts being
5792 * generated on the port when a cable is not attached.
5794 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
5795 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5796 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5802 drm_connector_cleanup(connector
);
5807 bool intel_dp_init(struct drm_device
*dev
,
5808 i915_reg_t output_reg
,
5811 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5812 struct intel_digital_port
*intel_dig_port
;
5813 struct intel_encoder
*intel_encoder
;
5814 struct drm_encoder
*encoder
;
5815 struct intel_connector
*intel_connector
;
5817 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5818 if (!intel_dig_port
)
5821 intel_connector
= intel_connector_alloc();
5822 if (!intel_connector
)
5823 goto err_connector_alloc
;
5825 intel_encoder
= &intel_dig_port
->base
;
5826 encoder
= &intel_encoder
->base
;
5828 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5829 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5830 goto err_encoder_init
;
5832 intel_encoder
->compute_config
= intel_dp_compute_config
;
5833 intel_encoder
->disable
= intel_disable_dp
;
5834 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5835 intel_encoder
->get_config
= intel_dp_get_config
;
5836 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5837 if (IS_CHERRYVIEW(dev_priv
)) {
5838 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5839 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5840 intel_encoder
->enable
= vlv_enable_dp
;
5841 intel_encoder
->post_disable
= chv_post_disable_dp
;
5842 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5843 } else if (IS_VALLEYVIEW(dev_priv
)) {
5844 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5845 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5846 intel_encoder
->enable
= vlv_enable_dp
;
5847 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5849 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5850 intel_encoder
->enable
= g4x_enable_dp
;
5851 if (INTEL_INFO(dev
)->gen
>= 5)
5852 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5855 intel_dig_port
->port
= port
;
5856 intel_dig_port
->dp
.output_reg
= output_reg
;
5857 intel_dig_port
->max_lanes
= 4;
5859 intel_encoder
->type
= INTEL_OUTPUT_DP
;
5860 if (IS_CHERRYVIEW(dev_priv
)) {
5862 intel_encoder
->crtc_mask
= 1 << 2;
5864 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5866 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5868 intel_encoder
->cloneable
= 0;
5869 intel_encoder
->port
= port
;
5871 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5872 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5874 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5875 goto err_init_connector
;
5880 drm_encoder_cleanup(encoder
);
5882 kfree(intel_connector
);
5883 err_connector_alloc
:
5884 kfree(intel_dig_port
);
5888 void intel_dp_mst_suspend(struct drm_device
*dev
)
5890 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5894 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5895 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5897 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5900 if (intel_dig_port
->dp
.is_mst
)
5901 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5905 void intel_dp_mst_resume(struct drm_device
*dev
)
5907 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5910 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5911 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5914 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5917 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5919 intel_dp_check_mst_status(&intel_dig_port
->dp
);