2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
196 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
197 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
198 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
199 int max_dotclk
= dev_priv
->max_dotclk_freq
;
202 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
204 if (type
!= DP_DS_PORT_TYPE_VGA
)
207 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
208 intel_dp
->downstream_ports
);
210 if (ds_max_dotclk
!= 0)
211 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
216 static enum drm_mode_status
217 intel_dp_mode_valid(struct drm_connector
*connector
,
218 struct drm_display_mode
*mode
)
220 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
222 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
223 int target_clock
= mode
->clock
;
224 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
227 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
229 if (is_edp(intel_dp
) && fixed_mode
) {
230 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
233 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
236 target_clock
= fixed_mode
->clock
;
239 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
240 max_lanes
= intel_dp_max_lane_count(intel_dp
);
242 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
243 mode_rate
= intel_dp_link_required(target_clock
, 18);
245 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
246 return MODE_CLOCK_HIGH
;
248 if (mode
->clock
< 10000)
249 return MODE_CLOCK_LOW
;
251 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
252 return MODE_H_ILLEGAL
;
257 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
264 for (i
= 0; i
< src_bytes
; i
++)
265 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
269 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
274 for (i
= 0; i
< dst_bytes
; i
++)
275 dst
[i
] = src
>> ((3-i
) * 8);
279 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
280 struct intel_dp
*intel_dp
);
282 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
283 struct intel_dp
*intel_dp
);
285 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
287 static void pps_lock(struct intel_dp
*intel_dp
)
289 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
290 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
291 struct drm_device
*dev
= encoder
->base
.dev
;
292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
293 enum intel_display_power_domain power_domain
;
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
299 power_domain
= intel_display_port_aux_power_domain(encoder
);
300 intel_display_power_get(dev_priv
, power_domain
);
302 mutex_lock(&dev_priv
->pps_mutex
);
305 static void pps_unlock(struct intel_dp
*intel_dp
)
307 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
308 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
309 struct drm_device
*dev
= encoder
->base
.dev
;
310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
311 enum intel_display_power_domain power_domain
;
313 mutex_unlock(&dev_priv
->pps_mutex
);
315 power_domain
= intel_display_port_aux_power_domain(encoder
);
316 intel_display_power_put(dev_priv
, power_domain
);
320 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
325 enum pipe pipe
= intel_dp
->pps_pipe
;
326 bool pll_enabled
, release_cl_override
= false;
327 enum dpio_phy phy
= DPIO_PHY(pipe
);
328 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
331 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
));
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
342 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
343 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
344 DP
|= DP_PORT_WIDTH(1);
345 DP
|= DP_LINK_TRAIN_PAT_1
;
347 if (IS_CHERRYVIEW(dev_priv
))
348 DP
|= DP_PIPE_SELECT_CHV(pipe
);
349 else if (pipe
== PIPE_B
)
350 DP
|= DP_PIPEB_SELECT
;
352 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
359 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
360 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
362 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
376 I915_WRITE(intel_dp
->output_reg
, DP
);
377 POSTING_READ(intel_dp
->output_reg
);
379 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
386 vlv_force_pll_off(dev
, pipe
);
388 if (release_cl_override
)
389 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
394 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
396 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
397 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
398 struct drm_i915_private
*dev_priv
= to_i915(dev
);
399 struct intel_encoder
*encoder
;
400 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
403 lockdep_assert_held(&dev_priv
->pps_mutex
);
405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp
));
408 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
409 return intel_dp
->pps_pipe
;
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
415 for_each_intel_encoder(dev
, encoder
) {
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
457 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
459 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
460 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
463 lockdep_assert_held(&dev_priv
->pps_mutex
);
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp
));
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
473 if (!intel_dp
->pps_reset
)
476 intel_dp
->pps_reset
= false;
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
482 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
487 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
490 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
493 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
499 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
502 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
509 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
511 vlv_pipe_check pipe_check
)
515 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
516 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
517 PANEL_PORT_SELECT_MASK
;
519 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
522 if (!pipe_check(dev_priv
, pipe
))
532 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
534 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
535 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
536 struct drm_i915_private
*dev_priv
= to_i915(dev
);
537 enum port port
= intel_dig_port
->port
;
539 lockdep_assert_held(&dev_priv
->pps_mutex
);
541 /* try to find a pipe with this port selected */
542 /* first pick one where the panel is on */
543 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
547 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
548 vlv_pipe_has_vdd_on
);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
551 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
564 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
565 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
568 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
570 struct drm_device
*dev
= &dev_priv
->drm
;
571 struct intel_encoder
*encoder
;
573 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
574 !IS_BROXTON(dev_priv
)))
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
587 for_each_intel_encoder(dev
, encoder
) {
588 struct intel_dp
*intel_dp
;
590 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
593 intel_dp
= enc_to_intel_dp(&encoder
->base
);
594 if (IS_BROXTON(dev_priv
))
595 intel_dp
->pps_reset
= true;
597 intel_dp
->pps_pipe
= INVALID_PIPE
;
601 struct pps_registers
{
609 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
610 struct intel_dp
*intel_dp
,
611 struct pps_registers
*regs
)
615 memset(regs
, 0, sizeof(*regs
));
617 if (IS_BROXTON(dev_priv
))
618 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
619 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
620 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
622 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
623 regs
->pp_stat
= PP_STATUS(pps_idx
);
624 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
625 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
626 if (!IS_BROXTON(dev_priv
))
627 regs
->pp_div
= PP_DIVISOR(pps_idx
);
631 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
633 struct pps_registers regs
;
635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
642 _pp_stat_reg(struct intel_dp
*intel_dp
)
644 struct pps_registers regs
;
646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
657 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
659 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
662 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
667 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
668 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
669 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
672 pp_ctrl_reg
= PP_CONTROL(pipe
);
673 pp_div_reg
= PP_DIVISOR(pipe
);
674 pp_div
= I915_READ(pp_div_reg
);
675 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
679 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
680 msleep(intel_dp
->panel_power_cycle_delay
);
683 pps_unlock(intel_dp
);
688 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
693 lockdep_assert_held(&dev_priv
->pps_mutex
);
695 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
696 intel_dp
->pps_pipe
== INVALID_PIPE
)
699 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
702 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
704 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
705 struct drm_i915_private
*dev_priv
= to_i915(dev
);
707 lockdep_assert_held(&dev_priv
->pps_mutex
);
709 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
710 intel_dp
->pps_pipe
== INVALID_PIPE
)
713 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
717 intel_dp_check_edp(struct intel_dp
*intel_dp
)
719 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
722 if (!is_edp(intel_dp
))
725 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
728 I915_READ(_pp_stat_reg(intel_dp
)),
729 I915_READ(_pp_ctrl_reg(intel_dp
)));
734 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
739 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
746 msecs_to_jiffies_timeout(10));
748 done
= wait_for(C
, 10) == 0;
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
759 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
760 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
766 * The clock divider is based off the hrawclk, and would like to run at
767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
769 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
774 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
775 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
785 if (intel_dig_port
->port
== PORT_A
)
786 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
788 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
794 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
796 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
797 /* Workaround for non-ULT HSW */
805 return ilk_get_aux_clock_divider(intel_dp
, index
);
808 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
815 return index
? 0 : 1;
818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
821 uint32_t aux_clock_divider
)
823 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
824 struct drm_i915_private
*dev_priv
=
825 to_i915(intel_dig_port
->base
.base
.dev
);
826 uint32_t precharge
, timeout
;
828 if (IS_GEN6(dev_priv
))
833 if (IS_BROADWELL(dev_priv
) && intel_dig_port
->port
== PORT_A
)
834 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
836 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
838 return DP_AUX_CH_CTL_SEND_BUSY
|
840 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
841 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
843 DP_AUX_CH_CTL_RECEIVE_ERROR
|
844 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
845 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
846 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
849 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
854 return DP_AUX_CH_CTL_SEND_BUSY
|
856 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
857 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
858 DP_AUX_CH_CTL_TIME_OUT_1600us
|
859 DP_AUX_CH_CTL_RECEIVE_ERROR
|
860 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
861 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
862 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
866 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
867 const uint8_t *send
, int send_bytes
,
868 uint8_t *recv
, int recv_size
)
870 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
871 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
873 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
874 uint32_t aux_clock_divider
;
875 int i
, ret
, recv_bytes
;
878 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
884 * We will be called with VDD already enabled for dpcd/edid/oui reads.
885 * In such cases we want to leave VDD enabled and it's up to upper layers
886 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
889 vdd
= edp_panel_vdd_on(intel_dp
);
891 /* dp aux is extremely sensitive to irq latency, hence request the
892 * lowest possible wakeup latency and so prevent the cpu from going into
895 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
897 intel_dp_check_edp(intel_dp
);
899 /* Try to wait for any previous AUX channel activity */
900 for (try = 0; try < 3; try++) {
901 status
= I915_READ_NOTRACE(ch_ctl
);
902 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
908 static u32 last_status
= -1;
909 const u32 status
= I915_READ(ch_ctl
);
911 if (status
!= last_status
) {
912 WARN(1, "dp_aux_ch not started status 0x%08x\n",
914 last_status
= status
;
921 /* Only 5 data registers! */
922 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
927 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
928 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
933 /* Must try at least 3 times according to DP spec */
934 for (try = 0; try < 5; try++) {
935 /* Load the send data into the aux channel data registers */
936 for (i
= 0; i
< send_bytes
; i
+= 4)
937 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
938 intel_dp_pack_aux(send
+ i
,
941 /* Send the command and wait for it to complete */
942 I915_WRITE(ch_ctl
, send_ctl
);
944 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
946 /* Clear done status and any errors */
950 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
951 DP_AUX_CH_CTL_RECEIVE_ERROR
);
953 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
956 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
957 * 400us delay required for errors and timeouts
958 * Timeout errors from the HW already meet this
959 * requirement so skip to next iteration
961 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
962 usleep_range(400, 500);
965 if (status
& DP_AUX_CH_CTL_DONE
)
970 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
971 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
977 /* Check for timeout or receive error.
978 * Timeouts occur when the sink is not connected
980 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
981 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
986 /* Timeouts occur when the device isn't connected, so they're
987 * "normal" -- don't fill the kernel log with these */
988 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
989 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
994 /* Unload any bytes sent back from the other side */
995 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
996 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
999 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1000 * We have no idea of what happened so we return -EBUSY so
1001 * drm layer takes care for the necessary retries.
1003 if (recv_bytes
== 0 || recv_bytes
> 20) {
1004 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1007 * FIXME: This patch was created on top of a series that
1008 * organize the retries at drm level. There EBUSY should
1009 * also take care for 1ms wait before retrying.
1010 * That aux retries re-org is still needed and after that is
1011 * merged we remove this sleep from here.
1013 usleep_range(1000, 1500);
1018 if (recv_bytes
> recv_size
)
1019 recv_bytes
= recv_size
;
1021 for (i
= 0; i
< recv_bytes
; i
+= 4)
1022 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1023 recv
+ i
, recv_bytes
- i
);
1027 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1030 edp_panel_vdd_off(intel_dp
, false);
1032 pps_unlock(intel_dp
);
1037 #define BARE_ADDRESS_SIZE 3
1038 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1040 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1042 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1043 uint8_t txbuf
[20], rxbuf
[20];
1044 size_t txsize
, rxsize
;
1047 txbuf
[0] = (msg
->request
<< 4) |
1048 ((msg
->address
>> 16) & 0xf);
1049 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1050 txbuf
[2] = msg
->address
& 0xff;
1051 txbuf
[3] = msg
->size
- 1;
1053 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1054 case DP_AUX_NATIVE_WRITE
:
1055 case DP_AUX_I2C_WRITE
:
1056 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1057 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1058 rxsize
= 2; /* 0 or 1 data bytes */
1060 if (WARN_ON(txsize
> 20))
1063 WARN_ON(!msg
->buffer
!= !msg
->size
);
1066 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1068 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1070 msg
->reply
= rxbuf
[0] >> 4;
1073 /* Number of bytes written in a short write. */
1074 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1076 /* Return payload size. */
1082 case DP_AUX_NATIVE_READ
:
1083 case DP_AUX_I2C_READ
:
1084 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1085 rxsize
= msg
->size
+ 1;
1087 if (WARN_ON(rxsize
> 20))
1090 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1092 msg
->reply
= rxbuf
[0] >> 4;
1094 * Assume happy day, and copy the data. The caller is
1095 * expected to check msg->reply before touching it.
1097 * Return payload size.
1100 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1112 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1115 const struct ddi_vbt_port_info
*info
=
1116 &dev_priv
->vbt
.ddi_port_info
[port
];
1119 if (!info
->alternate_aux_channel
) {
1120 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1121 port_name(port
), port_name(port
));
1125 switch (info
->alternate_aux_channel
) {
1139 MISSING_CASE(info
->alternate_aux_channel
);
1144 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1145 port_name(aux_port
), port_name(port
));
1150 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1157 return DP_AUX_CH_CTL(port
);
1160 return DP_AUX_CH_CTL(PORT_B
);
1164 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1165 enum port port
, int index
)
1171 return DP_AUX_CH_DATA(port
, index
);
1174 return DP_AUX_CH_DATA(PORT_B
, index
);
1178 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1183 return DP_AUX_CH_CTL(port
);
1187 return PCH_DP_AUX_CH_CTL(port
);
1190 return DP_AUX_CH_CTL(PORT_A
);
1194 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1195 enum port port
, int index
)
1199 return DP_AUX_CH_DATA(port
, index
);
1203 return PCH_DP_AUX_CH_DATA(port
, index
);
1206 return DP_AUX_CH_DATA(PORT_A
, index
);
1210 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1218 return DP_AUX_CH_CTL(port
);
1221 return DP_AUX_CH_CTL(PORT_A
);
1225 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1226 enum port port
, int index
)
1233 return DP_AUX_CH_DATA(port
, index
);
1236 return DP_AUX_CH_DATA(PORT_A
, index
);
1240 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1243 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1244 return skl_aux_ctl_reg(dev_priv
, port
);
1245 else if (HAS_PCH_SPLIT(dev_priv
))
1246 return ilk_aux_ctl_reg(dev_priv
, port
);
1248 return g4x_aux_ctl_reg(dev_priv
, port
);
1251 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1252 enum port port
, int index
)
1254 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1255 return skl_aux_data_reg(dev_priv
, port
, index
);
1256 else if (HAS_PCH_SPLIT(dev_priv
))
1257 return ilk_aux_data_reg(dev_priv
, port
, index
);
1259 return g4x_aux_data_reg(dev_priv
, port
, index
);
1262 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1264 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1265 enum port port
= intel_aux_port(dev_priv
,
1266 dp_to_dig_port(intel_dp
)->port
);
1269 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1270 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1271 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1275 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1277 kfree(intel_dp
->aux
.name
);
1281 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1283 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1284 enum port port
= intel_dig_port
->port
;
1286 intel_aux_reg_init(intel_dp
);
1287 drm_dp_aux_init(&intel_dp
->aux
);
1289 /* Failure to allocate our preferred name is not critical */
1290 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1291 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1295 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1297 if (intel_dp
->num_sink_rates
) {
1298 *sink_rates
= intel_dp
->sink_rates
;
1299 return intel_dp
->num_sink_rates
;
1302 *sink_rates
= default_rates
;
1304 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1307 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1309 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1310 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1312 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1313 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1320 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1322 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1323 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1326 if (IS_BROXTON(dev_priv
)) {
1327 *source_rates
= bxt_rates
;
1328 size
= ARRAY_SIZE(bxt_rates
);
1329 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1330 *source_rates
= skl_rates
;
1331 size
= ARRAY_SIZE(skl_rates
);
1333 *source_rates
= default_rates
;
1334 size
= ARRAY_SIZE(default_rates
);
1337 /* This depends on the fact that 5.4 is last value in the array */
1338 if (!intel_dp_source_supports_hbr2(intel_dp
))
1345 intel_dp_set_clock(struct intel_encoder
*encoder
,
1346 struct intel_crtc_state
*pipe_config
)
1348 struct drm_device
*dev
= encoder
->base
.dev
;
1349 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1350 const struct dp_link_dpll
*divisor
= NULL
;
1353 if (IS_G4X(dev_priv
)) {
1354 divisor
= gen4_dpll
;
1355 count
= ARRAY_SIZE(gen4_dpll
);
1356 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1358 count
= ARRAY_SIZE(pch_dpll
);
1359 } else if (IS_CHERRYVIEW(dev_priv
)) {
1361 count
= ARRAY_SIZE(chv_dpll
);
1362 } else if (IS_VALLEYVIEW(dev_priv
)) {
1364 count
= ARRAY_SIZE(vlv_dpll
);
1367 if (divisor
&& count
) {
1368 for (i
= 0; i
< count
; i
++) {
1369 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1370 pipe_config
->dpll
= divisor
[i
].dpll
;
1371 pipe_config
->clock_set
= true;
1378 static int intersect_rates(const int *source_rates
, int source_len
,
1379 const int *sink_rates
, int sink_len
,
1382 int i
= 0, j
= 0, k
= 0;
1384 while (i
< source_len
&& j
< sink_len
) {
1385 if (source_rates
[i
] == sink_rates
[j
]) {
1386 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1388 common_rates
[k
] = source_rates
[i
];
1392 } else if (source_rates
[i
] < sink_rates
[j
]) {
1401 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1404 const int *source_rates
, *sink_rates
;
1405 int source_len
, sink_len
;
1407 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1408 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1410 return intersect_rates(source_rates
, source_len
,
1411 sink_rates
, sink_len
,
1415 static void snprintf_int_array(char *str
, size_t len
,
1416 const int *array
, int nelem
)
1422 for (i
= 0; i
< nelem
; i
++) {
1423 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1431 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1433 const int *source_rates
, *sink_rates
;
1434 int source_len
, sink_len
, common_len
;
1435 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1436 char str
[128]; /* FIXME: too big for stack? */
1438 if ((drm_debug
& DRM_UT_KMS
) == 0)
1441 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1442 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1443 DRM_DEBUG_KMS("source rates: %s\n", str
);
1445 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1446 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1447 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1449 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1450 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1451 DRM_DEBUG_KMS("common rates: %s\n", str
);
1454 static void intel_dp_print_hw_revision(struct intel_dp
*intel_dp
)
1459 if ((drm_debug
& DRM_UT_KMS
) == 0)
1462 if (!drm_dp_is_branch(intel_dp
->dpcd
))
1465 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_HW_REV
, &rev
, 1);
1469 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev
& 0xf0) >> 4, rev
& 0xf);
1472 static void intel_dp_print_sw_revision(struct intel_dp
*intel_dp
)
1477 if ((drm_debug
& DRM_UT_KMS
) == 0)
1480 if (!drm_dp_is_branch(intel_dp
->dpcd
))
1483 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_SW_REV
, &rev
, 2);
1487 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev
[0], rev
[1]);
1490 static int rate_to_index(int find
, const int *rates
)
1494 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1495 if (find
== rates
[i
])
1502 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1504 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1507 len
= intel_dp_common_rates(intel_dp
, rates
);
1508 if (WARN_ON(len
<= 0))
1511 return rates
[len
- 1];
1514 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1516 return rate_to_index(rate
, intel_dp
->sink_rates
);
1519 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1520 uint8_t *link_bw
, uint8_t *rate_select
)
1522 if (intel_dp
->num_sink_rates
) {
1525 intel_dp_rate_select(intel_dp
, port_clock
);
1527 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1532 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1533 struct intel_crtc_state
*pipe_config
)
1537 bpp
= pipe_config
->pipe_bpp
;
1538 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1541 bpp
= min(bpp
, 3*bpc
);
1547 intel_dp_compute_config(struct intel_encoder
*encoder
,
1548 struct intel_crtc_state
*pipe_config
,
1549 struct drm_connector_state
*conn_state
)
1551 struct drm_device
*dev
= encoder
->base
.dev
;
1552 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1553 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1554 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1555 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1556 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1557 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1558 int lane_count
, clock
;
1559 int min_lane_count
= 1;
1560 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1561 /* Conveniently, the link BW constants become indices with a shift...*/
1565 int link_avail
, link_clock
;
1566 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1568 uint8_t link_bw
, rate_select
;
1570 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1572 /* No common link rates between source and sink */
1573 WARN_ON(common_len
<= 0);
1575 max_clock
= common_len
- 1;
1577 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1578 pipe_config
->has_pch_encoder
= true;
1580 pipe_config
->has_drrs
= false;
1581 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1583 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1584 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1587 if (INTEL_INFO(dev
)->gen
>= 9) {
1589 ret
= skl_update_scaler_crtc(pipe_config
);
1594 if (HAS_GMCH_DISPLAY(dev_priv
))
1595 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1596 intel_connector
->panel
.fitting_mode
);
1598 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1599 intel_connector
->panel
.fitting_mode
);
1602 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1605 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1606 "max bw %d pixel clock %iKHz\n",
1607 max_lane_count
, common_rates
[max_clock
],
1608 adjusted_mode
->crtc_clock
);
1610 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1611 * bpc in between. */
1612 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1613 if (is_edp(intel_dp
)) {
1615 /* Get bpp from vbt only for panels that dont have bpp in edid */
1616 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1617 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1618 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1619 dev_priv
->vbt
.edp
.bpp
);
1620 bpp
= dev_priv
->vbt
.edp
.bpp
;
1624 * Use the maximum clock and number of lanes the eDP panel
1625 * advertizes being capable of. The panels are generally
1626 * designed to support only a single clock and lane
1627 * configuration, and typically these values correspond to the
1628 * native resolution of the panel.
1630 min_lane_count
= max_lane_count
;
1631 min_clock
= max_clock
;
1634 for (; bpp
>= 6*3; bpp
-= 2*3) {
1635 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1638 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1639 for (lane_count
= min_lane_count
;
1640 lane_count
<= max_lane_count
;
1643 link_clock
= common_rates
[clock
];
1644 link_avail
= intel_dp_max_data_rate(link_clock
,
1647 if (mode_rate
<= link_avail
) {
1657 if (intel_dp
->color_range_auto
) {
1660 * CEA-861-E - 5.1 Default Encoding Parameters
1661 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1663 pipe_config
->limited_color_range
=
1664 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1666 pipe_config
->limited_color_range
=
1667 intel_dp
->limited_color_range
;
1670 pipe_config
->lane_count
= lane_count
;
1672 pipe_config
->pipe_bpp
= bpp
;
1673 pipe_config
->port_clock
= common_rates
[clock
];
1675 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1676 &link_bw
, &rate_select
);
1678 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1679 link_bw
, rate_select
, pipe_config
->lane_count
,
1680 pipe_config
->port_clock
, bpp
);
1681 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1682 mode_rate
, link_avail
);
1684 intel_link_compute_m_n(bpp
, lane_count
,
1685 adjusted_mode
->crtc_clock
,
1686 pipe_config
->port_clock
,
1687 &pipe_config
->dp_m_n
);
1689 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1690 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1691 pipe_config
->has_drrs
= true;
1692 intel_link_compute_m_n(bpp
, lane_count
,
1693 intel_connector
->panel
.downclock_mode
->clock
,
1694 pipe_config
->port_clock
,
1695 &pipe_config
->dp_m2_n2
);
1699 * DPLL0 VCO may need to be adjusted to get the correct
1700 * clock for eDP. This will affect cdclk as well.
1702 if (is_edp(intel_dp
) &&
1703 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1706 switch (pipe_config
->port_clock
/ 2) {
1716 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1719 if (!HAS_DDI(dev_priv
))
1720 intel_dp_set_clock(encoder
, pipe_config
);
1725 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1726 int link_rate
, uint8_t lane_count
,
1729 intel_dp
->link_rate
= link_rate
;
1730 intel_dp
->lane_count
= lane_count
;
1731 intel_dp
->link_mst
= link_mst
;
1734 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1735 struct intel_crtc_state
*pipe_config
)
1737 struct drm_device
*dev
= encoder
->base
.dev
;
1738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1739 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1740 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1741 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1742 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1744 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1745 pipe_config
->lane_count
,
1746 intel_crtc_has_type(pipe_config
,
1747 INTEL_OUTPUT_DP_MST
));
1750 * There are four kinds of DP registers:
1757 * IBX PCH and CPU are the same for almost everything,
1758 * except that the CPU DP PLL is configured in this
1761 * CPT PCH is quite different, having many bits moved
1762 * to the TRANS_DP_CTL register instead. That
1763 * configuration happens (oddly) in ironlake_pch_enable
1766 /* Preserve the BIOS-computed detected bit. This is
1767 * supposed to be read-only.
1769 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1771 /* Handle DP bits in common between all three register formats */
1772 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1773 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1775 /* Split out the IBX/CPU vs CPT settings */
1777 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1778 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1779 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1780 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1781 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1782 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1784 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1785 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1787 intel_dp
->DP
|= crtc
->pipe
<< 29;
1788 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1791 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1793 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1794 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1795 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1797 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1798 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1800 if (!HAS_PCH_SPLIT(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
1801 !IS_CHERRYVIEW(dev_priv
) &&
1802 pipe_config
->limited_color_range
)
1803 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1805 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1806 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1807 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1808 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1809 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1811 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1812 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1814 if (IS_CHERRYVIEW(dev_priv
))
1815 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1816 else if (crtc
->pipe
== PIPE_B
)
1817 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1821 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1822 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1824 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1825 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1827 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1828 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1830 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1831 struct intel_dp
*intel_dp
);
1833 static void wait_panel_status(struct intel_dp
*intel_dp
,
1837 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1838 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1839 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1841 lockdep_assert_held(&dev_priv
->pps_mutex
);
1843 intel_pps_verify_state(dev_priv
, intel_dp
);
1845 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1846 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1848 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1850 I915_READ(pp_stat_reg
),
1851 I915_READ(pp_ctrl_reg
));
1853 if (intel_wait_for_register(dev_priv
,
1854 pp_stat_reg
, mask
, value
,
1856 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1857 I915_READ(pp_stat_reg
),
1858 I915_READ(pp_ctrl_reg
));
1860 DRM_DEBUG_KMS("Wait complete\n");
1863 static void wait_panel_on(struct intel_dp
*intel_dp
)
1865 DRM_DEBUG_KMS("Wait for panel power on\n");
1866 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1869 static void wait_panel_off(struct intel_dp
*intel_dp
)
1871 DRM_DEBUG_KMS("Wait for panel power off time\n");
1872 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1875 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1877 ktime_t panel_power_on_time
;
1878 s64 panel_power_off_duration
;
1880 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1882 /* take the difference of currrent time and panel power off time
1883 * and then make panel wait for t11_t12 if needed. */
1884 panel_power_on_time
= ktime_get_boottime();
1885 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1887 /* When we disable the VDD override bit last we have to do the manual
1889 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1890 wait_remaining_ms_from_jiffies(jiffies
,
1891 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1893 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1896 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1898 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1899 intel_dp
->backlight_on_delay
);
1902 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1904 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1905 intel_dp
->backlight_off_delay
);
1908 /* Read the current pp_control value, unlocking the register if it
1912 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1914 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1915 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1918 lockdep_assert_held(&dev_priv
->pps_mutex
);
1920 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1921 if (WARN_ON(!HAS_DDI(dev_priv
) &&
1922 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
1923 control
&= ~PANEL_UNLOCK_MASK
;
1924 control
|= PANEL_UNLOCK_REGS
;
1930 * Must be paired with edp_panel_vdd_off().
1931 * Must hold pps_mutex around the whole on/off sequence.
1932 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1934 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1936 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1937 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1938 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1939 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1940 enum intel_display_power_domain power_domain
;
1942 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1943 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1945 lockdep_assert_held(&dev_priv
->pps_mutex
);
1947 if (!is_edp(intel_dp
))
1950 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1951 intel_dp
->want_panel_vdd
= true;
1953 if (edp_have_panel_vdd(intel_dp
))
1954 return need_to_disable
;
1956 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1957 intel_display_power_get(dev_priv
, power_domain
);
1959 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1960 port_name(intel_dig_port
->port
));
1962 if (!edp_have_panel_power(intel_dp
))
1963 wait_panel_power_cycle(intel_dp
);
1965 pp
= ironlake_get_pp_control(intel_dp
);
1966 pp
|= EDP_FORCE_VDD
;
1968 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1969 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1971 I915_WRITE(pp_ctrl_reg
, pp
);
1972 POSTING_READ(pp_ctrl_reg
);
1973 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1974 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1976 * If the panel wasn't on, delay before accessing aux channel
1978 if (!edp_have_panel_power(intel_dp
)) {
1979 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1980 port_name(intel_dig_port
->port
));
1981 msleep(intel_dp
->panel_power_up_delay
);
1984 return need_to_disable
;
1988 * Must be paired with intel_edp_panel_vdd_off() or
1989 * intel_edp_panel_off().
1990 * Nested calls to these functions are not allowed since
1991 * we drop the lock. Caller must use some higher level
1992 * locking to prevent nested calls from other threads.
1994 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1998 if (!is_edp(intel_dp
))
2002 vdd
= edp_panel_vdd_on(intel_dp
);
2003 pps_unlock(intel_dp
);
2005 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2006 port_name(dp_to_dig_port(intel_dp
)->port
));
2009 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2011 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2012 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2013 struct intel_digital_port
*intel_dig_port
=
2014 dp_to_dig_port(intel_dp
);
2015 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2016 enum intel_display_power_domain power_domain
;
2018 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2020 lockdep_assert_held(&dev_priv
->pps_mutex
);
2022 WARN_ON(intel_dp
->want_panel_vdd
);
2024 if (!edp_have_panel_vdd(intel_dp
))
2027 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2028 port_name(intel_dig_port
->port
));
2030 pp
= ironlake_get_pp_control(intel_dp
);
2031 pp
&= ~EDP_FORCE_VDD
;
2033 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2034 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2036 I915_WRITE(pp_ctrl_reg
, pp
);
2037 POSTING_READ(pp_ctrl_reg
);
2039 /* Make sure sequencer is idle before allowing subsequent activity */
2040 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2041 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2043 if ((pp
& PANEL_POWER_ON
) == 0)
2044 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2046 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2047 intel_display_power_put(dev_priv
, power_domain
);
2050 static void edp_panel_vdd_work(struct work_struct
*__work
)
2052 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2053 struct intel_dp
, panel_vdd_work
);
2056 if (!intel_dp
->want_panel_vdd
)
2057 edp_panel_vdd_off_sync(intel_dp
);
2058 pps_unlock(intel_dp
);
2061 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2063 unsigned long delay
;
2066 * Queue the timer to fire a long time from now (relative to the power
2067 * down delay) to keep the panel power up across a sequence of
2070 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2071 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2075 * Must be paired with edp_panel_vdd_on().
2076 * Must hold pps_mutex around the whole on/off sequence.
2077 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2079 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2081 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2083 lockdep_assert_held(&dev_priv
->pps_mutex
);
2085 if (!is_edp(intel_dp
))
2088 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2089 port_name(dp_to_dig_port(intel_dp
)->port
));
2091 intel_dp
->want_panel_vdd
= false;
2094 edp_panel_vdd_off_sync(intel_dp
);
2096 edp_panel_vdd_schedule_off(intel_dp
);
2099 static void edp_panel_on(struct intel_dp
*intel_dp
)
2101 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2102 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2104 i915_reg_t pp_ctrl_reg
;
2106 lockdep_assert_held(&dev_priv
->pps_mutex
);
2108 if (!is_edp(intel_dp
))
2111 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2112 port_name(dp_to_dig_port(intel_dp
)->port
));
2114 if (WARN(edp_have_panel_power(intel_dp
),
2115 "eDP port %c panel power already on\n",
2116 port_name(dp_to_dig_port(intel_dp
)->port
)))
2119 wait_panel_power_cycle(intel_dp
);
2121 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2122 pp
= ironlake_get_pp_control(intel_dp
);
2123 if (IS_GEN5(dev_priv
)) {
2124 /* ILK workaround: disable reset around power sequence */
2125 pp
&= ~PANEL_POWER_RESET
;
2126 I915_WRITE(pp_ctrl_reg
, pp
);
2127 POSTING_READ(pp_ctrl_reg
);
2130 pp
|= PANEL_POWER_ON
;
2131 if (!IS_GEN5(dev_priv
))
2132 pp
|= PANEL_POWER_RESET
;
2134 I915_WRITE(pp_ctrl_reg
, pp
);
2135 POSTING_READ(pp_ctrl_reg
);
2137 wait_panel_on(intel_dp
);
2138 intel_dp
->last_power_on
= jiffies
;
2140 if (IS_GEN5(dev_priv
)) {
2141 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2142 I915_WRITE(pp_ctrl_reg
, pp
);
2143 POSTING_READ(pp_ctrl_reg
);
2147 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2149 if (!is_edp(intel_dp
))
2153 edp_panel_on(intel_dp
);
2154 pps_unlock(intel_dp
);
2158 static void edp_panel_off(struct intel_dp
*intel_dp
)
2160 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2161 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2162 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2163 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2164 enum intel_display_power_domain power_domain
;
2166 i915_reg_t pp_ctrl_reg
;
2168 lockdep_assert_held(&dev_priv
->pps_mutex
);
2170 if (!is_edp(intel_dp
))
2173 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2174 port_name(dp_to_dig_port(intel_dp
)->port
));
2176 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2177 port_name(dp_to_dig_port(intel_dp
)->port
));
2179 pp
= ironlake_get_pp_control(intel_dp
);
2180 /* We need to switch off panel power _and_ force vdd, for otherwise some
2181 * panels get very unhappy and cease to work. */
2182 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2185 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2187 intel_dp
->want_panel_vdd
= false;
2189 I915_WRITE(pp_ctrl_reg
, pp
);
2190 POSTING_READ(pp_ctrl_reg
);
2192 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2193 wait_panel_off(intel_dp
);
2195 /* We got a reference when we enabled the VDD. */
2196 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2197 intel_display_power_put(dev_priv
, power_domain
);
2200 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2202 if (!is_edp(intel_dp
))
2206 edp_panel_off(intel_dp
);
2207 pps_unlock(intel_dp
);
2210 /* Enable backlight in the panel power control. */
2211 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2213 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2214 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2215 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2217 i915_reg_t pp_ctrl_reg
;
2220 * If we enable the backlight right away following a panel power
2221 * on, we may see slight flicker as the panel syncs with the eDP
2222 * link. So delay a bit to make sure the image is solid before
2223 * allowing it to appear.
2225 wait_backlight_on(intel_dp
);
2229 pp
= ironlake_get_pp_control(intel_dp
);
2230 pp
|= EDP_BLC_ENABLE
;
2232 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2234 I915_WRITE(pp_ctrl_reg
, pp
);
2235 POSTING_READ(pp_ctrl_reg
);
2237 pps_unlock(intel_dp
);
2240 /* Enable backlight PWM and backlight PP control. */
2241 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2243 if (!is_edp(intel_dp
))
2246 DRM_DEBUG_KMS("\n");
2248 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2249 _intel_edp_backlight_on(intel_dp
);
2252 /* Disable backlight in the panel power control. */
2253 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2255 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2256 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2258 i915_reg_t pp_ctrl_reg
;
2260 if (!is_edp(intel_dp
))
2265 pp
= ironlake_get_pp_control(intel_dp
);
2266 pp
&= ~EDP_BLC_ENABLE
;
2268 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2270 I915_WRITE(pp_ctrl_reg
, pp
);
2271 POSTING_READ(pp_ctrl_reg
);
2273 pps_unlock(intel_dp
);
2275 intel_dp
->last_backlight_off
= jiffies
;
2276 edp_wait_backlight_off(intel_dp
);
2279 /* Disable backlight PP control and backlight PWM. */
2280 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2282 if (!is_edp(intel_dp
))
2285 DRM_DEBUG_KMS("\n");
2287 _intel_edp_backlight_off(intel_dp
);
2288 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2292 * Hook for controlling the panel power control backlight through the bl_power
2293 * sysfs attribute. Take care to handle multiple calls.
2295 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2298 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2302 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2303 pps_unlock(intel_dp
);
2305 if (is_enabled
== enable
)
2308 DRM_DEBUG_KMS("panel power control backlight %s\n",
2309 enable
? "enable" : "disable");
2312 _intel_edp_backlight_on(intel_dp
);
2314 _intel_edp_backlight_off(intel_dp
);
2317 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2319 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2320 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2321 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2323 I915_STATE_WARN(cur_state
!= state
,
2324 "DP port %c state assertion failure (expected %s, current %s)\n",
2325 port_name(dig_port
->port
),
2326 onoff(state
), onoff(cur_state
));
2328 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2330 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2332 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2334 I915_STATE_WARN(cur_state
!= state
,
2335 "eDP PLL state assertion failure (expected %s, current %s)\n",
2336 onoff(state
), onoff(cur_state
));
2338 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2339 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2341 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2342 struct intel_crtc_state
*pipe_config
)
2344 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2345 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2347 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2348 assert_dp_port_disabled(intel_dp
);
2349 assert_edp_pll_disabled(dev_priv
);
2351 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2352 pipe_config
->port_clock
);
2354 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2356 if (pipe_config
->port_clock
== 162000)
2357 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2359 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2361 I915_WRITE(DP_A
, intel_dp
->DP
);
2366 * [DevILK] Work around required when enabling DP PLL
2367 * while a pipe is enabled going to FDI:
2368 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2369 * 2. Program DP PLL enable
2371 if (IS_GEN5(dev_priv
))
2372 intel_wait_for_vblank_if_active(&dev_priv
->drm
, !crtc
->pipe
);
2374 intel_dp
->DP
|= DP_PLL_ENABLE
;
2376 I915_WRITE(DP_A
, intel_dp
->DP
);
2381 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2383 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2384 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2385 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2387 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2388 assert_dp_port_disabled(intel_dp
);
2389 assert_edp_pll_enabled(dev_priv
);
2391 DRM_DEBUG_KMS("disabling eDP PLL\n");
2393 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2395 I915_WRITE(DP_A
, intel_dp
->DP
);
2400 /* If the sink supports it, try to set the power state appropriately */
2401 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2405 /* Should have a valid DPCD by this point */
2406 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2409 if (mode
!= DRM_MODE_DPMS_ON
) {
2410 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2414 * When turning on, we need to retry for 1ms to give the sink
2417 for (i
= 0; i
< 3; i
++) {
2418 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2427 DRM_DEBUG_KMS("failed to %s sink power state\n",
2428 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2431 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2434 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2435 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2436 struct drm_device
*dev
= encoder
->base
.dev
;
2437 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2438 enum intel_display_power_domain power_domain
;
2442 power_domain
= intel_display_port_power_domain(encoder
);
2443 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2448 tmp
= I915_READ(intel_dp
->output_reg
);
2450 if (!(tmp
& DP_PORT_EN
))
2453 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2454 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2455 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2458 for_each_pipe(dev_priv
, p
) {
2459 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2460 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2468 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2469 i915_mmio_reg_offset(intel_dp
->output_reg
));
2470 } else if (IS_CHERRYVIEW(dev_priv
)) {
2471 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2473 *pipe
= PORT_TO_PIPE(tmp
);
2479 intel_display_power_put(dev_priv
, power_domain
);
2484 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2485 struct intel_crtc_state
*pipe_config
)
2487 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2489 struct drm_device
*dev
= encoder
->base
.dev
;
2490 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2491 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2492 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2494 tmp
= I915_READ(intel_dp
->output_reg
);
2496 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2498 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2499 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2501 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2502 flags
|= DRM_MODE_FLAG_PHSYNC
;
2504 flags
|= DRM_MODE_FLAG_NHSYNC
;
2506 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2507 flags
|= DRM_MODE_FLAG_PVSYNC
;
2509 flags
|= DRM_MODE_FLAG_NVSYNC
;
2511 if (tmp
& DP_SYNC_HS_HIGH
)
2512 flags
|= DRM_MODE_FLAG_PHSYNC
;
2514 flags
|= DRM_MODE_FLAG_NHSYNC
;
2516 if (tmp
& DP_SYNC_VS_HIGH
)
2517 flags
|= DRM_MODE_FLAG_PVSYNC
;
2519 flags
|= DRM_MODE_FLAG_NVSYNC
;
2522 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2524 if (!HAS_PCH_SPLIT(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
2525 !IS_CHERRYVIEW(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2526 pipe_config
->limited_color_range
= true;
2528 pipe_config
->lane_count
=
2529 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2531 intel_dp_get_m_n(crtc
, pipe_config
);
2533 if (port
== PORT_A
) {
2534 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2535 pipe_config
->port_clock
= 162000;
2537 pipe_config
->port_clock
= 270000;
2540 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2541 intel_dotclock_calculate(pipe_config
->port_clock
,
2542 &pipe_config
->dp_m_n
);
2544 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2545 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2547 * This is a big fat ugly hack.
2549 * Some machines in UEFI boot mode provide us a VBT that has 18
2550 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2551 * unknown we fail to light up. Yet the same BIOS boots up with
2552 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2553 * max, not what it tells us to use.
2555 * Note: This will still be broken if the eDP panel is not lit
2556 * up by the BIOS, and thus we can't get the mode at module
2559 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2560 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2561 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2565 static void intel_disable_dp(struct intel_encoder
*encoder
,
2566 struct intel_crtc_state
*old_crtc_state
,
2567 struct drm_connector_state
*old_conn_state
)
2569 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2570 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2572 if (old_crtc_state
->has_audio
)
2573 intel_audio_codec_disable(encoder
);
2575 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2576 intel_psr_disable(intel_dp
);
2578 /* Make sure the panel is off before trying to change the mode. But also
2579 * ensure that we have vdd while we switch off the panel. */
2580 intel_edp_panel_vdd_on(intel_dp
);
2581 intel_edp_backlight_off(intel_dp
);
2582 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2583 intel_edp_panel_off(intel_dp
);
2585 /* disable the port before the pipe on g4x */
2586 if (INTEL_GEN(dev_priv
) < 5)
2587 intel_dp_link_down(intel_dp
);
2590 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2591 struct intel_crtc_state
*old_crtc_state
,
2592 struct drm_connector_state
*old_conn_state
)
2594 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2595 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2597 intel_dp_link_down(intel_dp
);
2599 /* Only ilk+ has port A */
2601 ironlake_edp_pll_off(intel_dp
);
2604 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2605 struct intel_crtc_state
*old_crtc_state
,
2606 struct drm_connector_state
*old_conn_state
)
2608 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2610 intel_dp_link_down(intel_dp
);
2613 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2614 struct intel_crtc_state
*old_crtc_state
,
2615 struct drm_connector_state
*old_conn_state
)
2617 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2618 struct drm_device
*dev
= encoder
->base
.dev
;
2619 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2621 intel_dp_link_down(intel_dp
);
2623 mutex_lock(&dev_priv
->sb_lock
);
2625 /* Assert data lane reset */
2626 chv_data_lane_soft_reset(encoder
, true);
2628 mutex_unlock(&dev_priv
->sb_lock
);
2632 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2634 uint8_t dp_train_pat
)
2636 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2637 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2638 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2639 enum port port
= intel_dig_port
->port
;
2641 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2642 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2643 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2645 if (HAS_DDI(dev_priv
)) {
2646 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2648 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2649 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2651 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2653 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2654 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2655 case DP_TRAINING_PATTERN_DISABLE
:
2656 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2659 case DP_TRAINING_PATTERN_1
:
2660 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2662 case DP_TRAINING_PATTERN_2
:
2663 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2665 case DP_TRAINING_PATTERN_3
:
2666 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2669 I915_WRITE(DP_TP_CTL(port
), temp
);
2671 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2672 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2673 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2675 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2676 case DP_TRAINING_PATTERN_DISABLE
:
2677 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2679 case DP_TRAINING_PATTERN_1
:
2680 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2682 case DP_TRAINING_PATTERN_2
:
2683 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2685 case DP_TRAINING_PATTERN_3
:
2686 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2687 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2692 if (IS_CHERRYVIEW(dev_priv
))
2693 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2695 *DP
&= ~DP_LINK_TRAIN_MASK
;
2697 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2698 case DP_TRAINING_PATTERN_DISABLE
:
2699 *DP
|= DP_LINK_TRAIN_OFF
;
2701 case DP_TRAINING_PATTERN_1
:
2702 *DP
|= DP_LINK_TRAIN_PAT_1
;
2704 case DP_TRAINING_PATTERN_2
:
2705 *DP
|= DP_LINK_TRAIN_PAT_2
;
2707 case DP_TRAINING_PATTERN_3
:
2708 if (IS_CHERRYVIEW(dev_priv
)) {
2709 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2711 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2712 *DP
|= DP_LINK_TRAIN_PAT_2
;
2719 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2720 struct intel_crtc_state
*old_crtc_state
)
2722 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2723 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2725 /* enable with pattern 1 (as per spec) */
2727 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2730 * Magic for VLV/CHV. We _must_ first set up the register
2731 * without actually enabling the port, and then do another
2732 * write to enable the port. Otherwise link training will
2733 * fail when the power sequencer is freshly used for this port.
2735 intel_dp
->DP
|= DP_PORT_EN
;
2736 if (old_crtc_state
->has_audio
)
2737 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2739 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2740 POSTING_READ(intel_dp
->output_reg
);
2743 static void intel_enable_dp(struct intel_encoder
*encoder
,
2744 struct intel_crtc_state
*pipe_config
)
2746 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2747 struct drm_device
*dev
= encoder
->base
.dev
;
2748 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2749 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2750 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2751 enum pipe pipe
= crtc
->pipe
;
2753 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2758 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2759 vlv_init_panel_power_sequencer(intel_dp
);
2761 intel_dp_enable_port(intel_dp
, pipe_config
);
2763 edp_panel_vdd_on(intel_dp
);
2764 edp_panel_on(intel_dp
);
2765 edp_panel_vdd_off(intel_dp
, true);
2767 pps_unlock(intel_dp
);
2769 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2770 unsigned int lane_mask
= 0x0;
2772 if (IS_CHERRYVIEW(dev_priv
))
2773 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2775 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2779 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2780 intel_dp_start_link_train(intel_dp
);
2781 intel_dp_stop_link_train(intel_dp
);
2783 if (pipe_config
->has_audio
) {
2784 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2786 intel_audio_codec_enable(encoder
);
2790 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2791 struct intel_crtc_state
*pipe_config
,
2792 struct drm_connector_state
*conn_state
)
2794 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2796 intel_enable_dp(encoder
, pipe_config
);
2797 intel_edp_backlight_on(intel_dp
);
2800 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2801 struct intel_crtc_state
*pipe_config
,
2802 struct drm_connector_state
*conn_state
)
2804 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2806 intel_edp_backlight_on(intel_dp
);
2807 intel_psr_enable(intel_dp
);
2810 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2811 struct intel_crtc_state
*pipe_config
,
2812 struct drm_connector_state
*conn_state
)
2814 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2815 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2817 intel_dp_prepare(encoder
, pipe_config
);
2819 /* Only ilk+ has port A */
2821 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2824 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2826 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2827 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2828 enum pipe pipe
= intel_dp
->pps_pipe
;
2829 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2831 edp_panel_vdd_off_sync(intel_dp
);
2834 * VLV seems to get confused when multiple power seqeuencers
2835 * have the same port selected (even if only one has power/vdd
2836 * enabled). The failure manifests as vlv_wait_port_ready() failing
2837 * CHV on the other hand doesn't seem to mind having the same port
2838 * selected in multiple power seqeuencers, but let's clear the
2839 * port select always when logically disconnecting a power sequencer
2842 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2843 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2844 I915_WRITE(pp_on_reg
, 0);
2845 POSTING_READ(pp_on_reg
);
2847 intel_dp
->pps_pipe
= INVALID_PIPE
;
2850 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2853 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2854 struct intel_encoder
*encoder
;
2856 lockdep_assert_held(&dev_priv
->pps_mutex
);
2858 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2861 for_each_intel_encoder(dev
, encoder
) {
2862 struct intel_dp
*intel_dp
;
2865 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2868 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2869 port
= dp_to_dig_port(intel_dp
)->port
;
2871 if (intel_dp
->pps_pipe
!= pipe
)
2874 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2875 pipe_name(pipe
), port_name(port
));
2877 WARN(encoder
->base
.crtc
,
2878 "stealing pipe %c power sequencer from active eDP port %c\n",
2879 pipe_name(pipe
), port_name(port
));
2881 /* make sure vdd is off before we steal it */
2882 vlv_detach_power_sequencer(intel_dp
);
2886 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2888 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2889 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2890 struct drm_device
*dev
= encoder
->base
.dev
;
2891 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2892 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2894 lockdep_assert_held(&dev_priv
->pps_mutex
);
2896 if (!is_edp(intel_dp
))
2899 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2903 * If another power sequencer was being used on this
2904 * port previously make sure to turn off vdd there while
2905 * we still have control of it.
2907 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2908 vlv_detach_power_sequencer(intel_dp
);
2911 * We may be stealing the power
2912 * sequencer from another port.
2914 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2916 /* now it's all ours */
2917 intel_dp
->pps_pipe
= crtc
->pipe
;
2919 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2920 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2922 /* init power sequencer on this pipe and port */
2923 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2924 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2927 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
2928 struct intel_crtc_state
*pipe_config
,
2929 struct drm_connector_state
*conn_state
)
2931 vlv_phy_pre_encoder_enable(encoder
);
2933 intel_enable_dp(encoder
, pipe_config
);
2936 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2937 struct intel_crtc_state
*pipe_config
,
2938 struct drm_connector_state
*conn_state
)
2940 intel_dp_prepare(encoder
, pipe_config
);
2942 vlv_phy_pre_pll_enable(encoder
);
2945 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
2946 struct intel_crtc_state
*pipe_config
,
2947 struct drm_connector_state
*conn_state
)
2949 chv_phy_pre_encoder_enable(encoder
);
2951 intel_enable_dp(encoder
, pipe_config
);
2953 /* Second common lane will stay alive on its own now */
2954 chv_phy_release_cl2_override(encoder
);
2957 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2958 struct intel_crtc_state
*pipe_config
,
2959 struct drm_connector_state
*conn_state
)
2961 intel_dp_prepare(encoder
, pipe_config
);
2963 chv_phy_pre_pll_enable(encoder
);
2966 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
2967 struct intel_crtc_state
*pipe_config
,
2968 struct drm_connector_state
*conn_state
)
2970 chv_phy_post_pll_disable(encoder
);
2974 * Fetch AUX CH registers 0x202 - 0x207 which contain
2975 * link status information
2978 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2980 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2981 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2984 /* These are source-specific values. */
2986 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2988 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2989 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2990 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2992 if (IS_BROXTON(dev_priv
))
2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2994 else if (INTEL_INFO(dev
)->gen
>= 9) {
2995 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2997 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2998 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2999 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3000 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3001 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3002 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3003 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3005 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3009 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3011 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3012 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3014 if (INTEL_GEN(dev_priv
) >= 9) {
3015 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3017 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3019 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3025 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3027 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3028 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3030 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3039 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3040 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3042 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3046 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3049 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3051 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3052 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3054 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3057 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3059 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3062 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3064 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3066 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3068 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3071 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3076 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3078 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3079 unsigned long demph_reg_value
, preemph_reg_value
,
3080 uniqtranscale_reg_value
;
3081 uint8_t train_set
= intel_dp
->train_set
[0];
3083 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3084 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3085 preemph_reg_value
= 0x0004000;
3086 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3088 demph_reg_value
= 0x2B405555;
3089 uniqtranscale_reg_value
= 0x552AB83A;
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3092 demph_reg_value
= 0x2B404040;
3093 uniqtranscale_reg_value
= 0x5548B83A;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3096 demph_reg_value
= 0x2B245555;
3097 uniqtranscale_reg_value
= 0x5560B83A;
3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3100 demph_reg_value
= 0x2B405555;
3101 uniqtranscale_reg_value
= 0x5598DA3A;
3107 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3108 preemph_reg_value
= 0x0002000;
3109 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3111 demph_reg_value
= 0x2B404040;
3112 uniqtranscale_reg_value
= 0x5552B83A;
3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3115 demph_reg_value
= 0x2B404848;
3116 uniqtranscale_reg_value
= 0x5580B83A;
3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3119 demph_reg_value
= 0x2B404040;
3120 uniqtranscale_reg_value
= 0x55ADDA3A;
3126 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3127 preemph_reg_value
= 0x0000000;
3128 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3130 demph_reg_value
= 0x2B305555;
3131 uniqtranscale_reg_value
= 0x5570B83A;
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3134 demph_reg_value
= 0x2B2B4040;
3135 uniqtranscale_reg_value
= 0x55ADDA3A;
3141 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3142 preemph_reg_value
= 0x0006000;
3143 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3145 demph_reg_value
= 0x1B405555;
3146 uniqtranscale_reg_value
= 0x55ADDA3A;
3156 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3157 uniqtranscale_reg_value
, 0);
3162 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3164 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3165 u32 deemph_reg_value
, margin_reg_value
;
3166 bool uniq_trans_scale
= false;
3167 uint8_t train_set
= intel_dp
->train_set
[0];
3169 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3170 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3171 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3173 deemph_reg_value
= 128;
3174 margin_reg_value
= 52;
3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3177 deemph_reg_value
= 128;
3178 margin_reg_value
= 77;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3181 deemph_reg_value
= 128;
3182 margin_reg_value
= 102;
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3185 deemph_reg_value
= 128;
3186 margin_reg_value
= 154;
3187 uniq_trans_scale
= true;
3193 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3194 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3196 deemph_reg_value
= 85;
3197 margin_reg_value
= 78;
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3200 deemph_reg_value
= 85;
3201 margin_reg_value
= 116;
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3204 deemph_reg_value
= 85;
3205 margin_reg_value
= 154;
3211 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3212 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3214 deemph_reg_value
= 64;
3215 margin_reg_value
= 104;
3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3218 deemph_reg_value
= 64;
3219 margin_reg_value
= 154;
3225 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3226 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3228 deemph_reg_value
= 43;
3229 margin_reg_value
= 154;
3239 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3240 margin_reg_value
, uniq_trans_scale
);
3246 gen4_signal_levels(uint8_t train_set
)
3248 uint32_t signal_levels
= 0;
3250 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3253 signal_levels
|= DP_VOLTAGE_0_4
;
3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3256 signal_levels
|= DP_VOLTAGE_0_6
;
3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3259 signal_levels
|= DP_VOLTAGE_0_8
;
3261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3262 signal_levels
|= DP_VOLTAGE_1_2
;
3265 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3266 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3268 signal_levels
|= DP_PRE_EMPHASIS_0
;
3270 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3271 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3273 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3274 signal_levels
|= DP_PRE_EMPHASIS_6
;
3276 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3277 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3280 return signal_levels
;
3283 /* Gen6's DP voltage swing and pre-emphasis control */
3285 gen6_edp_signal_levels(uint8_t train_set
)
3287 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3288 DP_TRAIN_PRE_EMPHASIS_MASK
);
3289 switch (signal_levels
) {
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3292 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3294 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3297 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3300 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3303 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3305 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3306 "0x%x\n", signal_levels
);
3307 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3311 /* Gen7's DP voltage swing and pre-emphasis control */
3313 gen7_edp_signal_levels(uint8_t train_set
)
3315 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3316 DP_TRAIN_PRE_EMPHASIS_MASK
);
3317 switch (signal_levels
) {
3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3319 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3321 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3323 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3326 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3328 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3331 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3333 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3336 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3337 "0x%x\n", signal_levels
);
3338 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3343 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3345 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3346 enum port port
= intel_dig_port
->port
;
3347 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3348 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3349 uint32_t signal_levels
, mask
= 0;
3350 uint8_t train_set
= intel_dp
->train_set
[0];
3352 if (HAS_DDI(dev_priv
)) {
3353 signal_levels
= ddi_signal_levels(intel_dp
);
3355 if (IS_BROXTON(dev_priv
))
3358 mask
= DDI_BUF_EMP_MASK
;
3359 } else if (IS_CHERRYVIEW(dev_priv
)) {
3360 signal_levels
= chv_signal_levels(intel_dp
);
3361 } else if (IS_VALLEYVIEW(dev_priv
)) {
3362 signal_levels
= vlv_signal_levels(intel_dp
);
3363 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3364 signal_levels
= gen7_edp_signal_levels(train_set
);
3365 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3366 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3367 signal_levels
= gen6_edp_signal_levels(train_set
);
3368 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3370 signal_levels
= gen4_signal_levels(train_set
);
3371 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3375 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3377 DRM_DEBUG_KMS("Using vswing level %d\n",
3378 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3379 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3380 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3381 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3383 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3385 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3386 POSTING_READ(intel_dp
->output_reg
);
3390 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3391 uint8_t dp_train_pat
)
3393 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3394 struct drm_i915_private
*dev_priv
=
3395 to_i915(intel_dig_port
->base
.base
.dev
);
3397 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3399 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3400 POSTING_READ(intel_dp
->output_reg
);
3403 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3405 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3406 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3407 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3408 enum port port
= intel_dig_port
->port
;
3411 if (!HAS_DDI(dev_priv
))
3414 val
= I915_READ(DP_TP_CTL(port
));
3415 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3416 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3417 I915_WRITE(DP_TP_CTL(port
), val
);
3420 * On PORT_A we can have only eDP in SST mode. There the only reason
3421 * we need to set idle transmission mode is to work around a HW issue
3422 * where we enable the pipe while not in idle link-training mode.
3423 * In this case there is requirement to wait for a minimum number of
3424 * idle patterns to be sent.
3429 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3430 DP_TP_STATUS_IDLE_DONE
,
3431 DP_TP_STATUS_IDLE_DONE
,
3433 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3437 intel_dp_link_down(struct intel_dp
*intel_dp
)
3439 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3440 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3441 enum port port
= intel_dig_port
->port
;
3442 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3443 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3444 uint32_t DP
= intel_dp
->DP
;
3446 if (WARN_ON(HAS_DDI(dev_priv
)))
3449 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3452 DRM_DEBUG_KMS("\n");
3454 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3455 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3456 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3457 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3459 if (IS_CHERRYVIEW(dev_priv
))
3460 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3462 DP
&= ~DP_LINK_TRAIN_MASK
;
3463 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3465 I915_WRITE(intel_dp
->output_reg
, DP
);
3466 POSTING_READ(intel_dp
->output_reg
);
3468 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3469 I915_WRITE(intel_dp
->output_reg
, DP
);
3470 POSTING_READ(intel_dp
->output_reg
);
3473 * HW workaround for IBX, we need to move the port
3474 * to transcoder A after disabling it to allow the
3475 * matching HDMI port to be enabled on transcoder A.
3477 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3479 * We get CPU/PCH FIFO underruns on the other pipe when
3480 * doing the workaround. Sweep them under the rug.
3482 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3483 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3485 /* always enable with pattern 1 (as per spec) */
3486 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3487 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3488 I915_WRITE(intel_dp
->output_reg
, DP
);
3489 POSTING_READ(intel_dp
->output_reg
);
3492 I915_WRITE(intel_dp
->output_reg
, DP
);
3493 POSTING_READ(intel_dp
->output_reg
);
3495 intel_wait_for_vblank_if_active(&dev_priv
->drm
, PIPE_A
);
3496 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3497 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3500 msleep(intel_dp
->panel_power_down_delay
);
3506 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3508 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3509 sizeof(intel_dp
->dpcd
)) < 0)
3510 return false; /* aux transfer failed */
3512 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3514 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3518 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3520 struct drm_i915_private
*dev_priv
=
3521 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3523 /* this function is meant to be called only once */
3524 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3526 if (!intel_dp_read_dpcd(intel_dp
))
3529 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3530 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3531 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3533 /* Check if the panel supports PSR */
3534 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3536 sizeof(intel_dp
->psr_dpcd
));
3537 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3538 dev_priv
->psr
.sink_support
= true;
3539 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3542 if (INTEL_GEN(dev_priv
) >= 9 &&
3543 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3544 uint8_t frame_sync_cap
;
3546 dev_priv
->psr
.sink_support
= true;
3547 drm_dp_dpcd_read(&intel_dp
->aux
,
3548 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3549 &frame_sync_cap
, 1);
3550 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3551 /* PSR2 needs frame sync as well */
3552 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3553 DRM_DEBUG_KMS("PSR2 %s on sink",
3554 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3557 /* Read the eDP Display control capabilities registers */
3558 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3559 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3560 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3561 sizeof(intel_dp
->edp_dpcd
))
3562 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3563 intel_dp
->edp_dpcd
);
3565 /* Intermediate frequency support */
3566 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3567 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3570 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3571 sink_rates
, sizeof(sink_rates
));
3573 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3574 int val
= le16_to_cpu(sink_rates
[i
]);
3579 /* Value read is in kHz while drm clock is saved in deca-kHz */
3580 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3582 intel_dp
->num_sink_rates
= i
;
3590 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3592 if (!intel_dp_read_dpcd(intel_dp
))
3595 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3596 &intel_dp
->sink_count
, 1) < 0)
3600 * Sink count can change between short pulse hpd hence
3601 * a member variable in intel_dp will track any changes
3602 * between short pulse interrupts.
3604 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3607 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3608 * a dongle is present but no display. Unless we require to know
3609 * if a dongle is present or not, we don't need to update
3610 * downstream port information. So, an early return here saves
3611 * time from performing other operations which are not required.
3613 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3616 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3617 return true; /* native DP sink */
3619 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3620 return true; /* no per-port downstream info */
3622 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3623 intel_dp
->downstream_ports
,
3624 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3625 return false; /* downstream port status fetch failed */
3631 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3635 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3638 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3639 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3640 buf
[0], buf
[1], buf
[2]);
3642 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3643 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3644 buf
[0], buf
[1], buf
[2]);
3648 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3652 if (!i915
.enable_dp_mst
)
3655 if (!intel_dp
->can_mst
)
3658 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3661 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3664 return buf
[0] & DP_MST_CAP
;
3668 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3670 if (!i915
.enable_dp_mst
)
3673 if (!intel_dp
->can_mst
)
3676 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3678 if (intel_dp
->is_mst
)
3679 DRM_DEBUG_KMS("Sink is MST capable\n");
3681 DRM_DEBUG_KMS("Sink is not MST capable\n");
3683 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3687 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3689 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3690 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3691 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3697 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3698 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3703 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3704 buf
& ~DP_TEST_SINK_START
) < 0) {
3705 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3711 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3713 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3714 DP_TEST_SINK_MISC
, &buf
) < 0) {
3718 count
= buf
& DP_TEST_COUNT_MASK
;
3719 } while (--attempts
&& count
);
3721 if (attempts
== 0) {
3722 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3727 hsw_enable_ips(intel_crtc
);
3731 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3733 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3734 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3735 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3739 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3742 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3745 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3748 if (buf
& DP_TEST_SINK_START
) {
3749 ret
= intel_dp_sink_crc_stop(intel_dp
);
3754 hsw_disable_ips(intel_crtc
);
3756 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3757 buf
| DP_TEST_SINK_START
) < 0) {
3758 hsw_enable_ips(intel_crtc
);
3762 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3766 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3768 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3769 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3770 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3775 ret
= intel_dp_sink_crc_start(intel_dp
);
3780 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3782 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3783 DP_TEST_SINK_MISC
, &buf
) < 0) {
3787 count
= buf
& DP_TEST_COUNT_MASK
;
3789 } while (--attempts
&& count
== 0);
3791 if (attempts
== 0) {
3792 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3797 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3803 intel_dp_sink_crc_stop(intel_dp
);
3808 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3810 return drm_dp_dpcd_read(&intel_dp
->aux
,
3811 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3812 sink_irq_vector
, 1) == 1;
3816 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3820 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3822 sink_irq_vector
, 14);
3829 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3831 uint8_t test_result
= DP_TEST_ACK
;
3835 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3837 uint8_t test_result
= DP_TEST_NAK
;
3841 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3843 uint8_t test_result
= DP_TEST_NAK
;
3844 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3845 struct drm_connector
*connector
= &intel_connector
->base
;
3847 if (intel_connector
->detect_edid
== NULL
||
3848 connector
->edid_corrupt
||
3849 intel_dp
->aux
.i2c_defer_count
> 6) {
3850 /* Check EDID read for NACKs, DEFERs and corruption
3851 * (DP CTS 1.2 Core r1.1)
3852 * 4.2.2.4 : Failed EDID read, I2C_NAK
3853 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3854 * 4.2.2.6 : EDID corruption detected
3855 * Use failsafe mode for all cases
3857 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3858 intel_dp
->aux
.i2c_defer_count
> 0)
3859 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3860 intel_dp
->aux
.i2c_nack_count
,
3861 intel_dp
->aux
.i2c_defer_count
);
3862 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3864 struct edid
*block
= intel_connector
->detect_edid
;
3866 /* We have to write the checksum
3867 * of the last block read
3869 block
+= intel_connector
->detect_edid
->extensions
;
3871 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3872 DP_TEST_EDID_CHECKSUM
,
3875 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3877 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3878 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3881 /* Set test active flag here so userspace doesn't interrupt things */
3882 intel_dp
->compliance_test_active
= 1;
3887 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3889 uint8_t test_result
= DP_TEST_NAK
;
3893 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3895 uint8_t response
= DP_TEST_NAK
;
3899 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3901 DRM_DEBUG_KMS("Could not read test request from sink\n");
3906 case DP_TEST_LINK_TRAINING
:
3907 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3908 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3909 response
= intel_dp_autotest_link_training(intel_dp
);
3911 case DP_TEST_LINK_VIDEO_PATTERN
:
3912 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3913 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3914 response
= intel_dp_autotest_video_pattern(intel_dp
);
3916 case DP_TEST_LINK_EDID_READ
:
3917 DRM_DEBUG_KMS("EDID test requested\n");
3918 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3919 response
= intel_dp_autotest_edid(intel_dp
);
3921 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3922 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3923 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3924 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3927 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3932 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3936 DRM_DEBUG_KMS("Could not write test response to sink\n");
3940 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3944 if (intel_dp
->is_mst
) {
3949 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3953 /* check link status - esi[10] = 0x200c */
3954 if (intel_dp
->active_mst_links
&&
3955 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3956 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3957 intel_dp_start_link_train(intel_dp
);
3958 intel_dp_stop_link_train(intel_dp
);
3961 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3962 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3965 for (retry
= 0; retry
< 3; retry
++) {
3967 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3968 DP_SINK_COUNT_ESI
+1,
3975 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3977 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3985 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3986 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3987 intel_dp
->is_mst
= false;
3988 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3989 /* send a hotplug event */
3990 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3997 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
3999 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4000 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4001 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4003 /* Suppress underruns caused by re-training */
4004 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4005 if (crtc
->config
->has_pch_encoder
)
4006 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4007 intel_crtc_pch_transcoder(crtc
), false);
4009 intel_dp_start_link_train(intel_dp
);
4010 intel_dp_stop_link_train(intel_dp
);
4012 /* Keep underrun reporting disabled until things are stable */
4013 intel_wait_for_vblank(&dev_priv
->drm
, crtc
->pipe
);
4015 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4016 if (crtc
->config
->has_pch_encoder
)
4017 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4018 intel_crtc_pch_transcoder(crtc
), true);
4022 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4024 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4025 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4026 u8 link_status
[DP_LINK_STATUS_SIZE
];
4028 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4030 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4031 DRM_ERROR("Failed to get link status\n");
4035 if (!intel_encoder
->base
.crtc
)
4038 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4041 /* FIXME: we need to synchronize this sort of stuff with hardware
4043 if (WARN_ON_ONCE(!intel_dp
->lane_count
))
4046 /* if link training is requested we should perform it always */
4047 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4048 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4049 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4050 intel_encoder
->base
.name
);
4052 intel_dp_retrain_link(intel_dp
);
4057 * According to DP spec
4060 * 2. Configure link according to Receiver Capabilities
4061 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4062 * 4. Check link status on receipt of hot-plug interrupt
4064 * intel_dp_short_pulse - handles short pulse interrupts
4065 * when full detection is not required.
4066 * Returns %true if short pulse is handled and full detection
4067 * is NOT required and %false otherwise.
4070 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4072 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4073 u8 sink_irq_vector
= 0;
4074 u8 old_sink_count
= intel_dp
->sink_count
;
4078 * Clearing compliance test variables to allow capturing
4079 * of values for next automated test request.
4081 intel_dp
->compliance_test_active
= 0;
4082 intel_dp
->compliance_test_type
= 0;
4083 intel_dp
->compliance_test_data
= 0;
4086 * Now read the DPCD to see if it's actually running
4087 * If the current value of sink count doesn't match with
4088 * the value that was stored earlier or dpcd read failed
4089 * we need to do full detection
4091 ret
= intel_dp_get_dpcd(intel_dp
);
4093 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4094 /* No need to proceed if we are going to do full detect */
4098 /* Try to read the source of the interrupt */
4099 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4100 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4101 sink_irq_vector
!= 0) {
4102 /* Clear interrupt source */
4103 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4104 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4107 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4108 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4109 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4110 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4113 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4114 intel_dp_check_link_status(intel_dp
);
4115 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4120 /* XXX this is probably wrong for multiple downstream ports */
4121 static enum drm_connector_status
4122 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4124 uint8_t *dpcd
= intel_dp
->dpcd
;
4127 if (!intel_dp_get_dpcd(intel_dp
))
4128 return connector_status_disconnected
;
4130 if (is_edp(intel_dp
))
4131 return connector_status_connected
;
4133 /* if there's no downstream port, we're done */
4134 if (!drm_dp_is_branch(dpcd
))
4135 return connector_status_connected
;
4137 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4138 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4139 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4141 return intel_dp
->sink_count
?
4142 connector_status_connected
: connector_status_disconnected
;
4145 if (intel_dp_can_mst(intel_dp
))
4146 return connector_status_connected
;
4148 /* If no HPD, poke DDC gently */
4149 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4150 return connector_status_connected
;
4152 /* Well we tried, say unknown for unreliable port types */
4153 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4154 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4155 if (type
== DP_DS_PORT_TYPE_VGA
||
4156 type
== DP_DS_PORT_TYPE_NON_EDID
)
4157 return connector_status_unknown
;
4159 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4160 DP_DWN_STRM_PORT_TYPE_MASK
;
4161 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4162 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4163 return connector_status_unknown
;
4166 /* Anything else is out of spec, warn and ignore */
4167 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4168 return connector_status_disconnected
;
4171 static enum drm_connector_status
4172 edp_detect(struct intel_dp
*intel_dp
)
4174 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4175 enum drm_connector_status status
;
4177 status
= intel_panel_detect(dev
);
4178 if (status
== connector_status_unknown
)
4179 status
= connector_status_connected
;
4184 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4185 struct intel_digital_port
*port
)
4189 switch (port
->port
) {
4193 bit
= SDE_PORTB_HOTPLUG
;
4196 bit
= SDE_PORTC_HOTPLUG
;
4199 bit
= SDE_PORTD_HOTPLUG
;
4202 MISSING_CASE(port
->port
);
4206 return I915_READ(SDEISR
) & bit
;
4209 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4210 struct intel_digital_port
*port
)
4214 switch (port
->port
) {
4218 bit
= SDE_PORTB_HOTPLUG_CPT
;
4221 bit
= SDE_PORTC_HOTPLUG_CPT
;
4224 bit
= SDE_PORTD_HOTPLUG_CPT
;
4227 bit
= SDE_PORTE_HOTPLUG_SPT
;
4230 MISSING_CASE(port
->port
);
4234 return I915_READ(SDEISR
) & bit
;
4237 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4238 struct intel_digital_port
*port
)
4242 switch (port
->port
) {
4244 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4247 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4250 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4253 MISSING_CASE(port
->port
);
4257 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4260 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4261 struct intel_digital_port
*port
)
4265 switch (port
->port
) {
4267 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4270 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4273 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4276 MISSING_CASE(port
->port
);
4280 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4283 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4284 struct intel_digital_port
*intel_dig_port
)
4286 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4290 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4293 bit
= BXT_DE_PORT_HP_DDIA
;
4296 bit
= BXT_DE_PORT_HP_DDIB
;
4299 bit
= BXT_DE_PORT_HP_DDIC
;
4306 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4310 * intel_digital_port_connected - is the specified port connected?
4311 * @dev_priv: i915 private structure
4312 * @port: the port to test
4314 * Return %true if @port is connected, %false otherwise.
4316 static bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4317 struct intel_digital_port
*port
)
4319 if (HAS_PCH_IBX(dev_priv
))
4320 return ibx_digital_port_connected(dev_priv
, port
);
4321 else if (HAS_PCH_SPLIT(dev_priv
))
4322 return cpt_digital_port_connected(dev_priv
, port
);
4323 else if (IS_BROXTON(dev_priv
))
4324 return bxt_digital_port_connected(dev_priv
, port
);
4325 else if (IS_GM45(dev_priv
))
4326 return gm45_digital_port_connected(dev_priv
, port
);
4328 return g4x_digital_port_connected(dev_priv
, port
);
4331 static struct edid
*
4332 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4334 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4336 /* use cached edid if we have one */
4337 if (intel_connector
->edid
) {
4339 if (IS_ERR(intel_connector
->edid
))
4342 return drm_edid_duplicate(intel_connector
->edid
);
4344 return drm_get_edid(&intel_connector
->base
,
4345 &intel_dp
->aux
.ddc
);
4349 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4351 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4354 intel_dp_unset_edid(intel_dp
);
4355 edid
= intel_dp_get_edid(intel_dp
);
4356 intel_connector
->detect_edid
= edid
;
4358 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4359 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4361 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4365 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4367 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4369 kfree(intel_connector
->detect_edid
);
4370 intel_connector
->detect_edid
= NULL
;
4372 intel_dp
->has_audio
= false;
4375 static enum drm_connector_status
4376 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4378 struct drm_connector
*connector
= &intel_connector
->base
;
4379 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4380 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4381 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4382 struct drm_device
*dev
= connector
->dev
;
4383 enum drm_connector_status status
;
4384 enum intel_display_power_domain power_domain
;
4385 u8 sink_irq_vector
= 0;
4387 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4388 intel_display_power_get(to_i915(dev
), power_domain
);
4390 /* Can't disconnect eDP, but you can close the lid... */
4391 if (is_edp(intel_dp
))
4392 status
= edp_detect(intel_dp
);
4393 else if (intel_digital_port_connected(to_i915(dev
),
4394 dp_to_dig_port(intel_dp
)))
4395 status
= intel_dp_detect_dpcd(intel_dp
);
4397 status
= connector_status_disconnected
;
4399 if (status
== connector_status_disconnected
) {
4400 intel_dp
->compliance_test_active
= 0;
4401 intel_dp
->compliance_test_type
= 0;
4402 intel_dp
->compliance_test_data
= 0;
4404 if (intel_dp
->is_mst
) {
4405 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4407 intel_dp
->mst_mgr
.mst_state
);
4408 intel_dp
->is_mst
= false;
4409 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4416 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4417 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4419 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4420 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4421 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4423 intel_dp_print_rates(intel_dp
);
4425 intel_dp_probe_oui(intel_dp
);
4427 intel_dp_print_hw_revision(intel_dp
);
4428 intel_dp_print_sw_revision(intel_dp
);
4430 intel_dp_configure_mst(intel_dp
);
4432 if (intel_dp
->is_mst
) {
4434 * If we are in MST mode then this connector
4435 * won't appear connected or have anything
4438 status
= connector_status_disconnected
;
4440 } else if (connector
->status
== connector_status_connected
) {
4442 * If display was connected already and is still connected
4443 * check links status, there has been known issues of
4444 * link loss triggerring long pulse!!!!
4446 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4447 intel_dp_check_link_status(intel_dp
);
4448 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4453 * Clearing NACK and defer counts to get their exact values
4454 * while reading EDID which are required by Compliance tests
4455 * 4.2.2.4 and 4.2.2.5
4457 intel_dp
->aux
.i2c_nack_count
= 0;
4458 intel_dp
->aux
.i2c_defer_count
= 0;
4460 intel_dp_set_edid(intel_dp
);
4461 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4462 status
= connector_status_connected
;
4463 intel_dp
->detect_done
= true;
4465 /* Try to read the source of the interrupt */
4466 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4467 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4468 sink_irq_vector
!= 0) {
4469 /* Clear interrupt source */
4470 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4471 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4474 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4475 intel_dp_handle_test_request(intel_dp
);
4476 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4477 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4481 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4482 intel_dp_unset_edid(intel_dp
);
4484 intel_display_power_put(to_i915(dev
), power_domain
);
4488 static enum drm_connector_status
4489 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4491 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4492 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4493 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4494 enum drm_connector_status status
= connector
->status
;
4496 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4497 connector
->base
.id
, connector
->name
);
4499 if (intel_dp
->is_mst
) {
4500 /* MST devices are disconnected from a monitor POV */
4501 intel_dp_unset_edid(intel_dp
);
4502 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4503 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4504 return connector_status_disconnected
;
4507 /* If full detect is not performed yet, do a full detect */
4508 if (!intel_dp
->detect_done
)
4509 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4511 intel_dp
->detect_done
= false;
4517 intel_dp_force(struct drm_connector
*connector
)
4519 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4520 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4521 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4522 enum intel_display_power_domain power_domain
;
4524 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4525 connector
->base
.id
, connector
->name
);
4526 intel_dp_unset_edid(intel_dp
);
4528 if (connector
->status
!= connector_status_connected
)
4531 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4532 intel_display_power_get(dev_priv
, power_domain
);
4534 intel_dp_set_edid(intel_dp
);
4536 intel_display_power_put(dev_priv
, power_domain
);
4538 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4539 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4542 static int intel_dp_get_modes(struct drm_connector
*connector
)
4544 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4547 edid
= intel_connector
->detect_edid
;
4549 int ret
= intel_connector_update_modes(connector
, edid
);
4554 /* if eDP has no EDID, fall back to fixed mode */
4555 if (is_edp(intel_attached_dp(connector
)) &&
4556 intel_connector
->panel
.fixed_mode
) {
4557 struct drm_display_mode
*mode
;
4559 mode
= drm_mode_duplicate(connector
->dev
,
4560 intel_connector
->panel
.fixed_mode
);
4562 drm_mode_probed_add(connector
, mode
);
4571 intel_dp_detect_audio(struct drm_connector
*connector
)
4573 bool has_audio
= false;
4576 edid
= to_intel_connector(connector
)->detect_edid
;
4578 has_audio
= drm_detect_monitor_audio(edid
);
4584 intel_dp_set_property(struct drm_connector
*connector
,
4585 struct drm_property
*property
,
4588 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4589 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4590 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4591 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4594 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4598 if (property
== dev_priv
->force_audio_property
) {
4602 if (i
== intel_dp
->force_audio
)
4605 intel_dp
->force_audio
= i
;
4607 if (i
== HDMI_AUDIO_AUTO
)
4608 has_audio
= intel_dp_detect_audio(connector
);
4610 has_audio
= (i
== HDMI_AUDIO_ON
);
4612 if (has_audio
== intel_dp
->has_audio
)
4615 intel_dp
->has_audio
= has_audio
;
4619 if (property
== dev_priv
->broadcast_rgb_property
) {
4620 bool old_auto
= intel_dp
->color_range_auto
;
4621 bool old_range
= intel_dp
->limited_color_range
;
4624 case INTEL_BROADCAST_RGB_AUTO
:
4625 intel_dp
->color_range_auto
= true;
4627 case INTEL_BROADCAST_RGB_FULL
:
4628 intel_dp
->color_range_auto
= false;
4629 intel_dp
->limited_color_range
= false;
4631 case INTEL_BROADCAST_RGB_LIMITED
:
4632 intel_dp
->color_range_auto
= false;
4633 intel_dp
->limited_color_range
= true;
4639 if (old_auto
== intel_dp
->color_range_auto
&&
4640 old_range
== intel_dp
->limited_color_range
)
4646 if (is_edp(intel_dp
) &&
4647 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4648 if (val
== DRM_MODE_SCALE_NONE
) {
4649 DRM_DEBUG_KMS("no scaling not supported\n");
4652 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4653 val
== DRM_MODE_SCALE_CENTER
) {
4654 DRM_DEBUG_KMS("centering not supported\n");
4658 if (intel_connector
->panel
.fitting_mode
== val
) {
4659 /* the eDP scaling property is not changed */
4662 intel_connector
->panel
.fitting_mode
= val
;
4670 if (intel_encoder
->base
.crtc
)
4671 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4677 intel_dp_connector_register(struct drm_connector
*connector
)
4679 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4682 ret
= intel_connector_register(connector
);
4686 i915_debugfs_connector_add(connector
);
4688 DRM_DEBUG_KMS("registering %s bus for %s\n",
4689 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4691 intel_dp
->aux
.dev
= connector
->kdev
;
4692 return drm_dp_aux_register(&intel_dp
->aux
);
4696 intel_dp_connector_unregister(struct drm_connector
*connector
)
4698 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4699 intel_connector_unregister(connector
);
4703 intel_dp_connector_destroy(struct drm_connector
*connector
)
4705 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4707 kfree(intel_connector
->detect_edid
);
4709 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4710 kfree(intel_connector
->edid
);
4712 /* Can't call is_edp() since the encoder may have been destroyed
4714 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4715 intel_panel_fini(&intel_connector
->panel
);
4717 drm_connector_cleanup(connector
);
4721 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4723 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4724 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4726 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4727 if (is_edp(intel_dp
)) {
4728 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4730 * vdd might still be enabled do to the delayed vdd off.
4731 * Make sure vdd is actually turned off here.
4734 edp_panel_vdd_off_sync(intel_dp
);
4735 pps_unlock(intel_dp
);
4737 if (intel_dp
->edp_notifier
.notifier_call
) {
4738 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4739 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4743 intel_dp_aux_fini(intel_dp
);
4745 drm_encoder_cleanup(encoder
);
4746 kfree(intel_dig_port
);
4749 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4751 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4753 if (!is_edp(intel_dp
))
4757 * vdd might still be enabled do to the delayed vdd off.
4758 * Make sure vdd is actually turned off here.
4760 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4762 edp_panel_vdd_off_sync(intel_dp
);
4763 pps_unlock(intel_dp
);
4766 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4768 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4769 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4771 enum intel_display_power_domain power_domain
;
4773 lockdep_assert_held(&dev_priv
->pps_mutex
);
4775 if (!edp_have_panel_vdd(intel_dp
))
4779 * The VDD bit needs a power domain reference, so if the bit is
4780 * already enabled when we boot or resume, grab this reference and
4781 * schedule a vdd off, so we don't hold on to the reference
4784 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4785 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4786 intel_display_power_get(dev_priv
, power_domain
);
4788 edp_panel_vdd_schedule_off(intel_dp
);
4791 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4793 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4794 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4795 struct intel_lspcon
*lspcon
= &intel_dig_port
->lspcon
;
4796 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4798 if (!HAS_DDI(dev_priv
))
4799 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4801 if (IS_GEN9(dev_priv
) && lspcon
->active
)
4802 lspcon_resume(lspcon
);
4804 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4809 /* Reinit the power sequencer, in case BIOS did something with it. */
4810 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4811 intel_edp_panel_vdd_sanitize(intel_dp
);
4813 pps_unlock(intel_dp
);
4816 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4817 .dpms
= drm_atomic_helper_connector_dpms
,
4818 .detect
= intel_dp_detect
,
4819 .force
= intel_dp_force
,
4820 .fill_modes
= drm_helper_probe_single_connector_modes
,
4821 .set_property
= intel_dp_set_property
,
4822 .atomic_get_property
= intel_connector_atomic_get_property
,
4823 .late_register
= intel_dp_connector_register
,
4824 .early_unregister
= intel_dp_connector_unregister
,
4825 .destroy
= intel_dp_connector_destroy
,
4826 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4827 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4830 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4831 .get_modes
= intel_dp_get_modes
,
4832 .mode_valid
= intel_dp_mode_valid
,
4835 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4836 .reset
= intel_dp_encoder_reset
,
4837 .destroy
= intel_dp_encoder_destroy
,
4841 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4843 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4844 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4845 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4846 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4847 enum intel_display_power_domain power_domain
;
4848 enum irqreturn ret
= IRQ_NONE
;
4850 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4851 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4852 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
4854 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4856 * vdd off can generate a long pulse on eDP which
4857 * would require vdd on to handle it, and thus we
4858 * would end up in an endless cycle of
4859 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4861 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4862 port_name(intel_dig_port
->port
));
4866 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4867 port_name(intel_dig_port
->port
),
4868 long_hpd
? "long" : "short");
4871 intel_dp
->detect_done
= false;
4875 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4876 intel_display_power_get(dev_priv
, power_domain
);
4878 if (intel_dp
->is_mst
) {
4879 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4881 * If we were in MST mode, and device is not
4882 * there, get out of MST mode
4884 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4885 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4886 intel_dp
->is_mst
= false;
4887 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4889 intel_dp
->detect_done
= false;
4894 if (!intel_dp
->is_mst
) {
4895 if (!intel_dp_short_pulse(intel_dp
)) {
4896 intel_dp
->detect_done
= false;
4904 intel_display_power_put(dev_priv
, power_domain
);
4909 /* check the VBT to see whether the eDP is on another port */
4910 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4912 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4915 * eDP not supported on g4x. so bail out early just
4916 * for a bit extra safety in case the VBT is bonkers.
4918 if (INTEL_INFO(dev
)->gen
< 5)
4924 return intel_bios_is_port_edp(dev_priv
, port
);
4928 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4930 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4932 intel_attach_force_audio_property(connector
);
4933 intel_attach_broadcast_rgb_property(connector
);
4934 intel_dp
->color_range_auto
= true;
4936 if (is_edp(intel_dp
)) {
4937 drm_mode_create_scaling_mode_property(connector
->dev
);
4938 drm_object_attach_property(
4940 connector
->dev
->mode_config
.scaling_mode_property
,
4941 DRM_MODE_SCALE_ASPECT
);
4942 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4946 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4948 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4949 intel_dp
->last_power_on
= jiffies
;
4950 intel_dp
->last_backlight_off
= jiffies
;
4954 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4955 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4957 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4958 struct pps_registers regs
;
4960 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4962 /* Workaround: Need to write PP_CONTROL with the unlock key as
4963 * the very first thing. */
4964 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4966 pp_on
= I915_READ(regs
.pp_on
);
4967 pp_off
= I915_READ(regs
.pp_off
);
4968 if (!IS_BROXTON(dev_priv
)) {
4969 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4970 pp_div
= I915_READ(regs
.pp_div
);
4973 /* Pull timing values out of registers */
4974 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4975 PANEL_POWER_UP_DELAY_SHIFT
;
4977 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4978 PANEL_LIGHT_ON_DELAY_SHIFT
;
4980 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4981 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4983 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4984 PANEL_POWER_DOWN_DELAY_SHIFT
;
4986 if (IS_BROXTON(dev_priv
)) {
4987 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4988 BXT_POWER_CYCLE_DELAY_SHIFT
;
4990 seq
->t11_t12
= (tmp
- 1) * 1000;
4994 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4995 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5000 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5002 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5004 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5008 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
5009 struct intel_dp
*intel_dp
)
5011 struct edp_power_seq hw
;
5012 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5014 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
5016 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5017 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5018 DRM_ERROR("PPS state mismatch\n");
5019 intel_pps_dump_state("sw", sw
);
5020 intel_pps_dump_state("hw", &hw
);
5025 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5026 struct intel_dp
*intel_dp
)
5028 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5029 struct edp_power_seq cur
, vbt
, spec
,
5030 *final
= &intel_dp
->pps_delays
;
5032 lockdep_assert_held(&dev_priv
->pps_mutex
);
5034 /* already initialized? */
5035 if (final
->t11_t12
!= 0)
5038 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5040 intel_pps_dump_state("cur", &cur
);
5042 vbt
= dev_priv
->vbt
.edp
.pps
;
5044 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5045 * our hw here, which are all in 100usec. */
5046 spec
.t1_t3
= 210 * 10;
5047 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5048 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5049 spec
.t10
= 500 * 10;
5050 /* This one is special and actually in units of 100ms, but zero
5051 * based in the hw (so we need to add 100 ms). But the sw vbt
5052 * table multiplies it with 1000 to make it in units of 100usec,
5054 spec
.t11_t12
= (510 + 100) * 10;
5056 intel_pps_dump_state("vbt", &vbt
);
5058 /* Use the max of the register settings and vbt. If both are
5059 * unset, fall back to the spec limits. */
5060 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5062 max(cur.field, vbt.field))
5063 assign_final(t1_t3
);
5067 assign_final(t11_t12
);
5070 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5071 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5072 intel_dp
->backlight_on_delay
= get_delay(t8
);
5073 intel_dp
->backlight_off_delay
= get_delay(t9
);
5074 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5075 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5078 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5079 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5080 intel_dp
->panel_power_cycle_delay
);
5082 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5083 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5086 * We override the HW backlight delays to 1 because we do manual waits
5087 * on them. For T8, even BSpec recommends doing it. For T9, if we
5088 * don't do this, we'll end up waiting for the backlight off delay
5089 * twice: once when we do the manual sleep, and once when we disable
5090 * the panel and wait for the PP_STATUS bit to become zero.
5097 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5098 struct intel_dp
*intel_dp
)
5100 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5101 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5102 int div
= dev_priv
->rawclk_freq
/ 1000;
5103 struct pps_registers regs
;
5104 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5105 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5107 lockdep_assert_held(&dev_priv
->pps_mutex
);
5109 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5111 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5112 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5113 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5114 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5115 /* Compute the divisor for the pp clock, simply match the Bspec
5117 if (IS_BROXTON(dev_priv
)) {
5118 pp_div
= I915_READ(regs
.pp_ctrl
);
5119 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5120 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5121 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5123 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5124 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5125 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5128 /* Haswell doesn't have any port selection bits for the panel
5129 * power sequencer any more. */
5130 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5131 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5132 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5134 port_sel
= PANEL_PORT_SELECT_DPA
;
5136 port_sel
= PANEL_PORT_SELECT_DPD
;
5141 I915_WRITE(regs
.pp_on
, pp_on
);
5142 I915_WRITE(regs
.pp_off
, pp_off
);
5143 if (IS_BROXTON(dev_priv
))
5144 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5146 I915_WRITE(regs
.pp_div
, pp_div
);
5148 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5149 I915_READ(regs
.pp_on
),
5150 I915_READ(regs
.pp_off
),
5151 IS_BROXTON(dev_priv
) ?
5152 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5153 I915_READ(regs
.pp_div
));
5156 static void intel_dp_pps_init(struct drm_device
*dev
,
5157 struct intel_dp
*intel_dp
)
5159 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5161 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5162 vlv_initial_power_sequencer_setup(intel_dp
);
5164 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5165 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5170 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5171 * @dev_priv: i915 device
5172 * @crtc_state: a pointer to the active intel_crtc_state
5173 * @refresh_rate: RR to be programmed
5175 * This function gets called when refresh rate (RR) has to be changed from
5176 * one frequency to another. Switches can be between high and low RR
5177 * supported by the panel or to any other RR based on media playback (in
5178 * this case, RR value needs to be passed from user space).
5180 * The caller of this function needs to take a lock on dev_priv->drrs.
5182 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5183 struct intel_crtc_state
*crtc_state
,
5186 struct intel_encoder
*encoder
;
5187 struct intel_digital_port
*dig_port
= NULL
;
5188 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5190 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5192 if (refresh_rate
<= 0) {
5193 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5197 if (intel_dp
== NULL
) {
5198 DRM_DEBUG_KMS("DRRS not supported.\n");
5203 * FIXME: This needs proper synchronization with psr state for some
5204 * platforms that cannot have PSR and DRRS enabled at the same time.
5207 dig_port
= dp_to_dig_port(intel_dp
);
5208 encoder
= &dig_port
->base
;
5209 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5212 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5216 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5217 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5221 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5223 index
= DRRS_LOW_RR
;
5225 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5227 "DRRS requested for previously set RR...ignoring\n");
5231 if (!crtc_state
->base
.active
) {
5232 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5236 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5239 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5242 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5246 DRM_ERROR("Unsupported refreshrate type\n");
5248 } else if (INTEL_GEN(dev_priv
) > 6) {
5249 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5252 val
= I915_READ(reg
);
5253 if (index
> DRRS_HIGH_RR
) {
5254 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5255 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5257 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5259 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5260 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5262 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5264 I915_WRITE(reg
, val
);
5267 dev_priv
->drrs
.refresh_rate_type
= index
;
5269 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5273 * intel_edp_drrs_enable - init drrs struct if supported
5274 * @intel_dp: DP struct
5275 * @crtc_state: A pointer to the active crtc state.
5277 * Initializes frontbuffer_bits and drrs.dp
5279 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5280 struct intel_crtc_state
*crtc_state
)
5282 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5283 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5285 if (!crtc_state
->has_drrs
) {
5286 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5290 mutex_lock(&dev_priv
->drrs
.mutex
);
5291 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5292 DRM_ERROR("DRRS already enabled\n");
5296 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5298 dev_priv
->drrs
.dp
= intel_dp
;
5301 mutex_unlock(&dev_priv
->drrs
.mutex
);
5305 * intel_edp_drrs_disable - Disable DRRS
5306 * @intel_dp: DP struct
5307 * @old_crtc_state: Pointer to old crtc_state.
5310 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5311 struct intel_crtc_state
*old_crtc_state
)
5313 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5314 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5316 if (!old_crtc_state
->has_drrs
)
5319 mutex_lock(&dev_priv
->drrs
.mutex
);
5320 if (!dev_priv
->drrs
.dp
) {
5321 mutex_unlock(&dev_priv
->drrs
.mutex
);
5325 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5326 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5327 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5329 dev_priv
->drrs
.dp
= NULL
;
5330 mutex_unlock(&dev_priv
->drrs
.mutex
);
5332 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5335 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5337 struct drm_i915_private
*dev_priv
=
5338 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5339 struct intel_dp
*intel_dp
;
5341 mutex_lock(&dev_priv
->drrs
.mutex
);
5343 intel_dp
= dev_priv
->drrs
.dp
;
5349 * The delayed work can race with an invalidate hence we need to
5353 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5356 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5357 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5359 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5360 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5364 mutex_unlock(&dev_priv
->drrs
.mutex
);
5368 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5369 * @dev_priv: i915 device
5370 * @frontbuffer_bits: frontbuffer plane tracking bits
5372 * This function gets called everytime rendering on the given planes start.
5373 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5375 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5377 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5378 unsigned int frontbuffer_bits
)
5380 struct drm_crtc
*crtc
;
5383 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5386 cancel_delayed_work(&dev_priv
->drrs
.work
);
5388 mutex_lock(&dev_priv
->drrs
.mutex
);
5389 if (!dev_priv
->drrs
.dp
) {
5390 mutex_unlock(&dev_priv
->drrs
.mutex
);
5394 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5395 pipe
= to_intel_crtc(crtc
)->pipe
;
5397 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5398 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5400 /* invalidate means busy screen hence upclock */
5401 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5402 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5403 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5405 mutex_unlock(&dev_priv
->drrs
.mutex
);
5409 * intel_edp_drrs_flush - Restart Idleness DRRS
5410 * @dev_priv: i915 device
5411 * @frontbuffer_bits: frontbuffer plane tracking bits
5413 * This function gets called every time rendering on the given planes has
5414 * completed or flip on a crtc is completed. So DRRS should be upclocked
5415 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5416 * if no other planes are dirty.
5418 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5420 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5421 unsigned int frontbuffer_bits
)
5423 struct drm_crtc
*crtc
;
5426 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5429 cancel_delayed_work(&dev_priv
->drrs
.work
);
5431 mutex_lock(&dev_priv
->drrs
.mutex
);
5432 if (!dev_priv
->drrs
.dp
) {
5433 mutex_unlock(&dev_priv
->drrs
.mutex
);
5437 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5438 pipe
= to_intel_crtc(crtc
)->pipe
;
5440 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5441 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5443 /* flush means busy screen hence upclock */
5444 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5445 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5446 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5449 * flush also means no more activity hence schedule downclock, if all
5450 * other fbs are quiescent too
5452 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5453 schedule_delayed_work(&dev_priv
->drrs
.work
,
5454 msecs_to_jiffies(1000));
5455 mutex_unlock(&dev_priv
->drrs
.mutex
);
5459 * DOC: Display Refresh Rate Switching (DRRS)
5461 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5462 * which enables swtching between low and high refresh rates,
5463 * dynamically, based on the usage scenario. This feature is applicable
5464 * for internal panels.
5466 * Indication that the panel supports DRRS is given by the panel EDID, which
5467 * would list multiple refresh rates for one resolution.
5469 * DRRS is of 2 types - static and seamless.
5470 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5471 * (may appear as a blink on screen) and is used in dock-undock scenario.
5472 * Seamless DRRS involves changing RR without any visual effect to the user
5473 * and can be used during normal system usage. This is done by programming
5474 * certain registers.
5476 * Support for static/seamless DRRS may be indicated in the VBT based on
5477 * inputs from the panel spec.
5479 * DRRS saves power by switching to low RR based on usage scenarios.
5481 * The implementation is based on frontbuffer tracking implementation. When
5482 * there is a disturbance on the screen triggered by user activity or a periodic
5483 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5484 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5487 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5488 * and intel_edp_drrs_flush() are called.
5490 * DRRS can be further extended to support other internal panels and also
5491 * the scenario of video playback wherein RR is set based on the rate
5492 * requested by userspace.
5496 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5497 * @intel_connector: eDP connector
5498 * @fixed_mode: preferred mode of panel
5500 * This function is called only once at driver load to initialize basic
5504 * Downclock mode if panel supports it, else return NULL.
5505 * DRRS support is determined by the presence of downclock mode (apart
5506 * from VBT setting).
5508 static struct drm_display_mode
*
5509 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5510 struct drm_display_mode
*fixed_mode
)
5512 struct drm_connector
*connector
= &intel_connector
->base
;
5513 struct drm_device
*dev
= connector
->dev
;
5514 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5515 struct drm_display_mode
*downclock_mode
= NULL
;
5517 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5518 mutex_init(&dev_priv
->drrs
.mutex
);
5520 if (INTEL_INFO(dev
)->gen
<= 6) {
5521 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5525 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5526 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5530 downclock_mode
= intel_find_panel_downclock
5531 (dev
, fixed_mode
, connector
);
5533 if (!downclock_mode
) {
5534 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5538 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5540 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5541 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5542 return downclock_mode
;
5545 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5546 struct intel_connector
*intel_connector
)
5548 struct drm_connector
*connector
= &intel_connector
->base
;
5549 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5550 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5551 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5552 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5553 struct drm_display_mode
*fixed_mode
= NULL
;
5554 struct drm_display_mode
*downclock_mode
= NULL
;
5556 struct drm_display_mode
*scan
;
5558 enum pipe pipe
= INVALID_PIPE
;
5560 if (!is_edp(intel_dp
))
5564 * On IBX/CPT we may get here with LVDS already registered. Since the
5565 * driver uses the only internal power sequencer available for both
5566 * eDP and LVDS bail out early in this case to prevent interfering
5567 * with an already powered-on LVDS power sequencer.
5569 if (intel_get_lvds_encoder(dev
)) {
5570 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5571 DRM_INFO("LVDS was detected, not registering eDP\n");
5578 intel_dp_init_panel_power_timestamps(intel_dp
);
5579 intel_dp_pps_init(dev
, intel_dp
);
5580 intel_edp_panel_vdd_sanitize(intel_dp
);
5582 pps_unlock(intel_dp
);
5584 /* Cache DPCD and EDID for edp. */
5585 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5588 /* if this fails, presume the device is a ghost */
5589 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5593 mutex_lock(&dev
->mode_config
.mutex
);
5594 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5596 if (drm_add_edid_modes(connector
, edid
)) {
5597 drm_mode_connector_update_edid_property(connector
,
5599 drm_edid_to_eld(connector
, edid
);
5602 edid
= ERR_PTR(-EINVAL
);
5605 edid
= ERR_PTR(-ENOENT
);
5607 intel_connector
->edid
= edid
;
5609 /* prefer fixed mode from EDID if available */
5610 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5611 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5612 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5613 downclock_mode
= intel_dp_drrs_init(
5614 intel_connector
, fixed_mode
);
5619 /* fallback to VBT if available for eDP */
5620 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5621 fixed_mode
= drm_mode_duplicate(dev
,
5622 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5624 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5625 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5626 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5629 mutex_unlock(&dev
->mode_config
.mutex
);
5631 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5632 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5633 register_reboot_notifier(&intel_dp
->edp_notifier
);
5636 * Figure out the current pipe for the initial backlight setup.
5637 * If the current pipe isn't valid, try the PPS pipe, and if that
5638 * fails just assume pipe A.
5640 if (IS_CHERRYVIEW(dev_priv
))
5641 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5643 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5645 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5646 pipe
= intel_dp
->pps_pipe
;
5648 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5651 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5655 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5656 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5657 intel_panel_setup_backlight(connector
, pipe
);
5662 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5664 * vdd might still be enabled do to the delayed vdd off.
5665 * Make sure vdd is actually turned off here.
5668 edp_panel_vdd_off_sync(intel_dp
);
5669 pps_unlock(intel_dp
);
5675 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5676 struct intel_connector
*intel_connector
)
5678 struct drm_connector
*connector
= &intel_connector
->base
;
5679 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5680 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5681 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5682 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5683 enum port port
= intel_dig_port
->port
;
5686 if (WARN(intel_dig_port
->max_lanes
< 1,
5687 "Not enough lanes (%d) for DP on port %c\n",
5688 intel_dig_port
->max_lanes
, port_name(port
)))
5691 intel_dp
->pps_pipe
= INVALID_PIPE
;
5693 /* intel_dp vfuncs */
5694 if (INTEL_INFO(dev
)->gen
>= 9)
5695 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5696 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5697 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5698 else if (HAS_PCH_SPLIT(dev_priv
))
5699 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5701 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5703 if (INTEL_INFO(dev
)->gen
>= 9)
5704 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5706 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5708 if (HAS_DDI(dev_priv
))
5709 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5711 /* Preserve the current hw state. */
5712 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5713 intel_dp
->attached_connector
= intel_connector
;
5715 if (intel_dp_is_edp(dev
, port
))
5716 type
= DRM_MODE_CONNECTOR_eDP
;
5718 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5721 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5722 * for DP the encoder type can be set by the caller to
5723 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5725 if (type
== DRM_MODE_CONNECTOR_eDP
)
5726 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5728 /* eDP only on port B and/or C on vlv/chv */
5729 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
5730 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5733 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5734 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5737 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5738 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5740 connector
->interlace_allowed
= true;
5741 connector
->doublescan_allowed
= 0;
5743 intel_dp_aux_init(intel_dp
);
5745 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5746 edp_panel_vdd_work
);
5748 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5750 if (HAS_DDI(dev_priv
))
5751 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5753 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5755 /* Set up the hotplug pin. */
5758 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5761 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5762 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
5763 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5766 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5769 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5772 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5778 /* init MST on ports that can support it */
5779 if (HAS_DP_MST(dev
) && !is_edp(intel_dp
) &&
5780 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5781 intel_dp_mst_encoder_init(intel_dig_port
,
5782 intel_connector
->base
.base
.id
);
5784 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5785 intel_dp_aux_fini(intel_dp
);
5786 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5790 intel_dp_add_properties(intel_dp
, connector
);
5792 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5793 * 0xd. Failure to do so will result in spurious interrupts being
5794 * generated on the port when a cable is not attached.
5796 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
5797 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5798 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5804 drm_connector_cleanup(connector
);
5809 bool intel_dp_init(struct drm_device
*dev
,
5810 i915_reg_t output_reg
,
5813 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5814 struct intel_digital_port
*intel_dig_port
;
5815 struct intel_encoder
*intel_encoder
;
5816 struct drm_encoder
*encoder
;
5817 struct intel_connector
*intel_connector
;
5819 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5820 if (!intel_dig_port
)
5823 intel_connector
= intel_connector_alloc();
5824 if (!intel_connector
)
5825 goto err_connector_alloc
;
5827 intel_encoder
= &intel_dig_port
->base
;
5828 encoder
= &intel_encoder
->base
;
5830 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5831 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5832 goto err_encoder_init
;
5834 intel_encoder
->compute_config
= intel_dp_compute_config
;
5835 intel_encoder
->disable
= intel_disable_dp
;
5836 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5837 intel_encoder
->get_config
= intel_dp_get_config
;
5838 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5839 if (IS_CHERRYVIEW(dev_priv
)) {
5840 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5841 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5842 intel_encoder
->enable
= vlv_enable_dp
;
5843 intel_encoder
->post_disable
= chv_post_disable_dp
;
5844 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5845 } else if (IS_VALLEYVIEW(dev_priv
)) {
5846 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5847 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5848 intel_encoder
->enable
= vlv_enable_dp
;
5849 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5851 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5852 intel_encoder
->enable
= g4x_enable_dp
;
5853 if (INTEL_INFO(dev
)->gen
>= 5)
5854 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5857 intel_dig_port
->port
= port
;
5858 intel_dig_port
->dp
.output_reg
= output_reg
;
5859 intel_dig_port
->max_lanes
= 4;
5861 intel_encoder
->type
= INTEL_OUTPUT_DP
;
5862 if (IS_CHERRYVIEW(dev_priv
)) {
5864 intel_encoder
->crtc_mask
= 1 << 2;
5866 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5868 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5870 intel_encoder
->cloneable
= 0;
5871 intel_encoder
->port
= port
;
5873 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5874 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5876 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5877 goto err_init_connector
;
5882 drm_encoder_cleanup(encoder
);
5884 kfree(intel_connector
);
5885 err_connector_alloc
:
5886 kfree(intel_dig_port
);
5890 void intel_dp_mst_suspend(struct drm_device
*dev
)
5892 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5896 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5897 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5899 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5902 if (intel_dig_port
->dp
.is_mst
)
5903 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5907 void intel_dp_mst_resume(struct drm_device
*dev
)
5909 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5912 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5913 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5916 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5919 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5921 intel_dp_check_mst_status(&intel_dig_port
->dp
);