2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
26 struct intel_shared_dpll
*
27 skl_find_link_pll(struct drm_i915_private
*dev_priv
, int clock
)
29 struct intel_shared_dpll
*pll
= NULL
;
30 struct intel_dpll_hw_state dpll_hw_state
;
34 if (!skl_ddi_dp_set_dpll_hw_state(clock
, &dpll_hw_state
))
37 for (i
= DPLL_ID_SKL_DPLL1
; i
<= DPLL_ID_SKL_DPLL3
; i
++) {
38 pll
= &dev_priv
->shared_dplls
[i
];
40 /* Only want to check enabled timings first */
41 if (pll
->config
.crtc_mask
== 0)
44 if (memcmp(&dpll_hw_state
, &pll
->config
.hw_state
,
45 sizeof(pll
->config
.hw_state
)) == 0) {
51 /* Ok no matching timings, maybe there's a free one? */
52 for (i
= DPLL_ID_SKL_DPLL1
;
53 ((found
== false) && (i
<= DPLL_ID_SKL_DPLL3
)); i
++) {
54 pll
= &dev_priv
->shared_dplls
[i
];
55 if (pll
->config
.crtc_mask
== 0) {
56 pll
->config
.hw_state
= dpll_hw_state
;
64 struct intel_shared_dpll
*
65 intel_get_shared_dpll_by_id(struct drm_i915_private
*dev_priv
,
66 enum intel_dpll_id id
)
68 return &dev_priv
->shared_dplls
[id
];
72 intel_get_shared_dpll_id(struct drm_i915_private
*dev_priv
,
73 struct intel_shared_dpll
*pll
)
75 if (WARN_ON(pll
< dev_priv
->shared_dplls
||
76 pll
> &dev_priv
->shared_dplls
[dev_priv
->num_shared_dpll
]))
79 return (enum intel_dpll_id
) (pll
- dev_priv
->shared_dplls
);
83 intel_shared_dpll_config_get(struct intel_shared_dpll_config
*config
,
84 struct intel_shared_dpll
*pll
,
85 struct intel_crtc
*crtc
)
87 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
88 enum intel_dpll_id id
= intel_get_shared_dpll_id(dev_priv
, pll
);
90 config
[id
].crtc_mask
|= 1 << crtc
->pipe
;
94 intel_shared_dpll_config_put(struct intel_shared_dpll_config
*config
,
95 struct intel_shared_dpll
*pll
,
96 struct intel_crtc
*crtc
)
98 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
99 enum intel_dpll_id id
= intel_get_shared_dpll_id(dev_priv
, pll
);
101 config
[id
].crtc_mask
&= ~(1 << crtc
->pipe
);
105 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
106 struct intel_shared_dpll
*pll
,
110 struct intel_dpll_hw_state hw_state
;
112 if (WARN(!pll
, "asserting DPLL %s with no DPLL\n", onoff(state
)))
115 cur_state
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &hw_state
);
116 I915_STATE_WARN(cur_state
!= state
,
117 "%s assertion failure (expected %s, current %s)\n",
118 pll
->name
, onoff(state
), onoff(cur_state
));
121 void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
123 struct drm_device
*dev
= crtc
->base
.dev
;
124 struct drm_i915_private
*dev_priv
= to_i915(dev
);
125 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
127 if (WARN_ON(pll
== NULL
))
130 mutex_lock(&dev_priv
->dpll_lock
);
131 WARN_ON(!pll
->config
.crtc_mask
);
132 if (!pll
->active_mask
) {
133 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
135 assert_shared_dpll_disabled(dev_priv
, pll
);
137 pll
->funcs
.mode_set(dev_priv
, pll
);
139 mutex_unlock(&dev_priv
->dpll_lock
);
143 * intel_enable_shared_dpll - enable PCH PLL
144 * @dev_priv: i915 private structure
145 * @pipe: pipe PLL to enable
147 * The PCH PLL needs to be enabled before the PCH transcoder, since it
148 * drives the transcoder clock.
150 void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
152 struct drm_device
*dev
= crtc
->base
.dev
;
153 struct drm_i915_private
*dev_priv
= to_i915(dev
);
154 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
155 unsigned crtc_mask
= 1 << drm_crtc_index(&crtc
->base
);
158 if (WARN_ON(pll
== NULL
))
161 mutex_lock(&dev_priv
->dpll_lock
);
162 old_mask
= pll
->active_mask
;
164 if (WARN_ON(!(pll
->config
.crtc_mask
& crtc_mask
)) ||
165 WARN_ON(pll
->active_mask
& crtc_mask
))
168 pll
->active_mask
|= crtc_mask
;
170 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
171 pll
->name
, pll
->active_mask
, pll
->on
,
176 assert_shared_dpll_enabled(dev_priv
, pll
);
181 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
182 pll
->funcs
.enable(dev_priv
, pll
);
186 mutex_unlock(&dev_priv
->dpll_lock
);
189 void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
191 struct drm_device
*dev
= crtc
->base
.dev
;
192 struct drm_i915_private
*dev_priv
= to_i915(dev
);
193 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
194 unsigned crtc_mask
= 1 << drm_crtc_index(&crtc
->base
);
196 /* PCH only available on ILK+ */
197 if (INTEL_INFO(dev
)->gen
< 5)
203 mutex_lock(&dev_priv
->dpll_lock
);
204 if (WARN_ON(!(pll
->active_mask
& crtc_mask
)))
207 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
208 pll
->name
, pll
->active_mask
, pll
->on
,
211 assert_shared_dpll_enabled(dev_priv
, pll
);
214 pll
->active_mask
&= ~crtc_mask
;
215 if (pll
->active_mask
)
218 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
219 pll
->funcs
.disable(dev_priv
, pll
);
223 mutex_unlock(&dev_priv
->dpll_lock
);
226 static struct intel_shared_dpll
*
227 intel_find_shared_dpll(struct intel_crtc
*crtc
,
228 struct intel_crtc_state
*crtc_state
,
229 enum intel_dpll_id range_min
,
230 enum intel_dpll_id range_max
)
232 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
233 struct intel_shared_dpll
*pll
;
234 struct intel_shared_dpll_config
*shared_dpll
;
235 enum intel_dpll_id i
;
237 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
239 for (i
= range_min
; i
<= range_max
; i
++) {
240 pll
= &dev_priv
->shared_dplls
[i
];
242 /* Only want to check enabled timings first */
243 if (shared_dpll
[i
].crtc_mask
== 0)
246 if (memcmp(&crtc_state
->dpll_hw_state
,
247 &shared_dpll
[i
].hw_state
,
248 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
249 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
250 crtc
->base
.base
.id
, crtc
->base
.name
, pll
->name
,
251 shared_dpll
[i
].crtc_mask
,
257 /* Ok no matching timings, maybe there's a free one? */
258 for (i
= range_min
; i
<= range_max
; i
++) {
259 pll
= &dev_priv
->shared_dplls
[i
];
260 if (shared_dpll
[i
].crtc_mask
== 0) {
261 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
262 crtc
->base
.base
.id
, crtc
->base
.name
, pll
->name
);
271 intel_reference_shared_dpll(struct intel_shared_dpll
*pll
,
272 struct intel_crtc_state
*crtc_state
)
274 struct intel_shared_dpll_config
*shared_dpll
;
275 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
276 enum intel_dpll_id i
= pll
->id
;
278 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
280 if (shared_dpll
[i
].crtc_mask
== 0)
281 shared_dpll
[i
].hw_state
=
282 crtc_state
->dpll_hw_state
;
284 crtc_state
->shared_dpll
= pll
;
285 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
286 pipe_name(crtc
->pipe
));
288 intel_shared_dpll_config_get(shared_dpll
, pll
, crtc
);
291 void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
293 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
294 struct intel_shared_dpll_config
*shared_dpll
;
295 struct intel_shared_dpll
*pll
;
296 enum intel_dpll_id i
;
298 if (!to_intel_atomic_state(state
)->dpll_set
)
301 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
302 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
303 pll
= &dev_priv
->shared_dplls
[i
];
304 pll
->config
= shared_dpll
[i
];
308 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
309 struct intel_shared_dpll
*pll
,
310 struct intel_dpll_hw_state
*hw_state
)
314 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
317 val
= I915_READ(PCH_DPLL(pll
->id
));
318 hw_state
->dpll
= val
;
319 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
320 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
322 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
324 return val
& DPLL_VCO_ENABLE
;
327 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
328 struct intel_shared_dpll
*pll
)
330 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
331 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
334 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
339 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
341 val
= I915_READ(PCH_DREF_CONTROL
);
342 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
343 DREF_SUPERSPREAD_SOURCE_MASK
));
344 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
347 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
348 struct intel_shared_dpll
*pll
)
350 /* PCH refclock must be enabled first */
351 ibx_assert_pch_refclk_enabled(dev_priv
);
353 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
355 /* Wait for the clocks to stabilize. */
356 POSTING_READ(PCH_DPLL(pll
->id
));
359 /* The pixel multiplier can only be updated once the
360 * DPLL is enabled and the clocks are stable.
364 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
365 POSTING_READ(PCH_DPLL(pll
->id
));
369 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
370 struct intel_shared_dpll
*pll
)
372 struct drm_device
*dev
= &dev_priv
->drm
;
373 struct intel_crtc
*crtc
;
375 /* Make sure no transcoder isn't still depending on us. */
376 for_each_intel_crtc(dev
, crtc
) {
377 if (crtc
->config
->shared_dpll
== pll
)
378 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
381 I915_WRITE(PCH_DPLL(pll
->id
), 0);
382 POSTING_READ(PCH_DPLL(pll
->id
));
386 static struct intel_shared_dpll
*
387 ibx_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
388 struct intel_encoder
*encoder
)
390 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
391 struct intel_shared_dpll
*pll
;
392 enum intel_dpll_id i
;
394 if (HAS_PCH_IBX(dev_priv
)) {
395 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
396 i
= (enum intel_dpll_id
) crtc
->pipe
;
397 pll
= &dev_priv
->shared_dplls
[i
];
399 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
400 crtc
->base
.base
.id
, crtc
->base
.name
, pll
->name
);
402 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
410 /* reference the pll */
411 intel_reference_shared_dpll(pll
, crtc_state
);
416 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs
= {
417 .mode_set
= ibx_pch_dpll_mode_set
,
418 .enable
= ibx_pch_dpll_enable
,
419 .disable
= ibx_pch_dpll_disable
,
420 .get_hw_state
= ibx_pch_dpll_get_hw_state
,
423 static void hsw_ddi_wrpll_enable(struct drm_i915_private
*dev_priv
,
424 struct intel_shared_dpll
*pll
)
426 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
427 POSTING_READ(WRPLL_CTL(pll
->id
));
431 static void hsw_ddi_spll_enable(struct drm_i915_private
*dev_priv
,
432 struct intel_shared_dpll
*pll
)
434 I915_WRITE(SPLL_CTL
, pll
->config
.hw_state
.spll
);
435 POSTING_READ(SPLL_CTL
);
439 static void hsw_ddi_wrpll_disable(struct drm_i915_private
*dev_priv
,
440 struct intel_shared_dpll
*pll
)
444 val
= I915_READ(WRPLL_CTL(pll
->id
));
445 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
446 POSTING_READ(WRPLL_CTL(pll
->id
));
449 static void hsw_ddi_spll_disable(struct drm_i915_private
*dev_priv
,
450 struct intel_shared_dpll
*pll
)
454 val
= I915_READ(SPLL_CTL
);
455 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
456 POSTING_READ(SPLL_CTL
);
459 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private
*dev_priv
,
460 struct intel_shared_dpll
*pll
,
461 struct intel_dpll_hw_state
*hw_state
)
465 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
468 val
= I915_READ(WRPLL_CTL(pll
->id
));
469 hw_state
->wrpll
= val
;
471 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
473 return val
& WRPLL_PLL_ENABLE
;
476 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private
*dev_priv
,
477 struct intel_shared_dpll
*pll
,
478 struct intel_dpll_hw_state
*hw_state
)
482 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
485 val
= I915_READ(SPLL_CTL
);
486 hw_state
->spll
= val
;
488 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
490 return val
& SPLL_PLL_ENABLE
;
494 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
500 /* Constraints for PLL good behavior */
506 struct hsw_wrpll_rnp
{
510 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
584 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
585 unsigned r2
, unsigned n2
, unsigned p
,
586 struct hsw_wrpll_rnp
*best
)
588 uint64_t a
, b
, c
, d
, diff
, diff_best
;
590 /* No best (r,n,p) yet */
599 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
603 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
606 * and we would like delta <= budget.
608 * If the discrepancy is above the PPM-based budget, always prefer to
609 * improve upon the previous solution. However, if you're within the
610 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
612 a
= freq2k
* budget
* p
* r2
;
613 b
= freq2k
* budget
* best
->p
* best
->r2
;
614 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
615 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
616 LC_FREQ_2K
* best
->n2
);
618 d
= 1000000 * diff_best
;
620 if (a
< c
&& b
< d
) {
621 /* If both are above the budget, pick the closer */
622 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
627 } else if (a
>= c
&& b
< d
) {
628 /* If A is below the threshold but B is above it? Update. */
632 } else if (a
>= c
&& b
>= d
) {
633 /* Both are below the limit, so pick the higher n2/(r2*r2) */
634 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
640 /* Otherwise a < c && b >= d, do nothing */
644 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
645 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
649 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
652 freq2k
= clock
/ 100;
654 budget
= hsw_wrpll_get_budget_for_freq(clock
);
656 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
657 * and directly pass the LC PLL to it. */
658 if (freq2k
== 5400000) {
666 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
669 * We want R so that REF_MIN <= Ref <= REF_MAX.
670 * Injecting R2 = 2 * R gives:
671 * REF_MAX * r2 > LC_FREQ * 2 and
672 * REF_MIN * r2 < LC_FREQ * 2
674 * Which means the desired boundaries for r2 are:
675 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
678 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
679 r2
<= LC_FREQ
* 2 / REF_MIN
;
683 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
685 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
686 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
687 * VCO_MAX * r2 > n2 * LC_FREQ and
688 * VCO_MIN * r2 < n2 * LC_FREQ)
690 * Which means the desired boundaries for n2 are:
691 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
693 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
694 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
697 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
698 hsw_wrpll_update_rnp(freq2k
, budget
,
708 static struct intel_shared_dpll
*hsw_ddi_hdmi_get_dpll(int clock
,
709 struct intel_crtc
*crtc
,
710 struct intel_crtc_state
*crtc_state
)
712 struct intel_shared_dpll
*pll
;
714 unsigned int p
, n2
, r2
;
716 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
718 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
719 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
720 WRPLL_DIVIDER_POST(p
);
722 crtc_state
->dpll_hw_state
.wrpll
= val
;
724 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
725 DPLL_ID_WRPLL1
, DPLL_ID_WRPLL2
);
733 struct intel_shared_dpll
*hsw_ddi_dp_get_dpll(struct intel_encoder
*encoder
,
736 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
737 struct intel_shared_dpll
*pll
;
738 enum intel_dpll_id pll_id
;
742 pll_id
= DPLL_ID_LCPLL_810
;
745 pll_id
= DPLL_ID_LCPLL_1350
;
748 pll_id
= DPLL_ID_LCPLL_2700
;
751 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock
);
755 pll
= intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
763 static struct intel_shared_dpll
*
764 hsw_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
765 struct intel_encoder
*encoder
)
767 struct intel_shared_dpll
*pll
;
768 int clock
= crtc_state
->port_clock
;
770 memset(&crtc_state
->dpll_hw_state
, 0,
771 sizeof(crtc_state
->dpll_hw_state
));
773 if (encoder
->type
== INTEL_OUTPUT_HDMI
) {
774 pll
= hsw_ddi_hdmi_get_dpll(clock
, crtc
, crtc_state
);
776 } else if (encoder
->type
== INTEL_OUTPUT_DP
||
777 encoder
->type
== INTEL_OUTPUT_DP_MST
||
778 encoder
->type
== INTEL_OUTPUT_EDP
) {
779 pll
= hsw_ddi_dp_get_dpll(encoder
, clock
);
781 } else if (encoder
->type
== INTEL_OUTPUT_ANALOG
) {
782 if (WARN_ON(crtc_state
->port_clock
/ 2 != 135000))
785 crtc_state
->dpll_hw_state
.spll
=
786 SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
788 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
789 DPLL_ID_SPLL
, DPLL_ID_SPLL
);
797 intel_reference_shared_dpll(pll
, crtc_state
);
802 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs
= {
803 .enable
= hsw_ddi_wrpll_enable
,
804 .disable
= hsw_ddi_wrpll_disable
,
805 .get_hw_state
= hsw_ddi_wrpll_get_hw_state
,
808 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs
= {
809 .enable
= hsw_ddi_spll_enable
,
810 .disable
= hsw_ddi_spll_disable
,
811 .get_hw_state
= hsw_ddi_spll_get_hw_state
,
814 static void hsw_ddi_lcpll_enable(struct drm_i915_private
*dev_priv
,
815 struct intel_shared_dpll
*pll
)
819 static void hsw_ddi_lcpll_disable(struct drm_i915_private
*dev_priv
,
820 struct intel_shared_dpll
*pll
)
824 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private
*dev_priv
,
825 struct intel_shared_dpll
*pll
,
826 struct intel_dpll_hw_state
*hw_state
)
831 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs
= {
832 .enable
= hsw_ddi_lcpll_enable
,
833 .disable
= hsw_ddi_lcpll_disable
,
834 .get_hw_state
= hsw_ddi_lcpll_get_hw_state
,
837 struct skl_dpll_regs
{
838 i915_reg_t ctl
, cfgcr1
, cfgcr2
;
841 /* this array is indexed by the *shared* pll id */
842 static const struct skl_dpll_regs skl_dpll_regs
[4] = {
846 /* DPLL 0 doesn't support HDMI mode */
851 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL1
),
852 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL1
),
857 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL2
),
858 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL2
),
863 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL3
),
864 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL3
),
868 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private
*dev_priv
,
869 struct intel_shared_dpll
*pll
)
873 val
= I915_READ(DPLL_CTRL1
);
875 val
&= ~(DPLL_CTRL1_HDMI_MODE(pll
->id
) | DPLL_CTRL1_SSC(pll
->id
) |
876 DPLL_CTRL1_LINK_RATE_MASK(pll
->id
));
877 val
|= pll
->config
.hw_state
.ctrl1
<< (pll
->id
* 6);
879 I915_WRITE(DPLL_CTRL1
, val
);
880 POSTING_READ(DPLL_CTRL1
);
883 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
884 struct intel_shared_dpll
*pll
)
886 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
888 skl_ddi_pll_write_ctrl1(dev_priv
, pll
);
890 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
891 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
892 POSTING_READ(regs
[pll
->id
].cfgcr1
);
893 POSTING_READ(regs
[pll
->id
].cfgcr2
);
895 /* the enable bit is always bit 31 */
896 I915_WRITE(regs
[pll
->id
].ctl
,
897 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
899 if (intel_wait_for_register(dev_priv
,
904 DRM_ERROR("DPLL %d not locked\n", pll
->id
);
907 static void skl_ddi_dpll0_enable(struct drm_i915_private
*dev_priv
,
908 struct intel_shared_dpll
*pll
)
910 skl_ddi_pll_write_ctrl1(dev_priv
, pll
);
913 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
914 struct intel_shared_dpll
*pll
)
916 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
918 /* the enable bit is always bit 31 */
919 I915_WRITE(regs
[pll
->id
].ctl
,
920 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
921 POSTING_READ(regs
[pll
->id
].ctl
);
924 static void skl_ddi_dpll0_disable(struct drm_i915_private
*dev_priv
,
925 struct intel_shared_dpll
*pll
)
929 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
930 struct intel_shared_dpll
*pll
,
931 struct intel_dpll_hw_state
*hw_state
)
934 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
937 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
942 val
= I915_READ(regs
[pll
->id
].ctl
);
943 if (!(val
& LCPLL_PLL_ENABLE
))
946 val
= I915_READ(DPLL_CTRL1
);
947 hw_state
->ctrl1
= (val
>> (pll
->id
* 6)) & 0x3f;
949 /* avoid reading back stale values if HDMI mode is not enabled */
950 if (val
& DPLL_CTRL1_HDMI_MODE(pll
->id
)) {
951 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
952 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
957 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
962 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private
*dev_priv
,
963 struct intel_shared_dpll
*pll
,
964 struct intel_dpll_hw_state
*hw_state
)
967 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
970 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
975 /* DPLL0 is always enabled since it drives CDCLK */
976 val
= I915_READ(regs
[pll
->id
].ctl
);
977 if (WARN_ON(!(val
& LCPLL_PLL_ENABLE
)))
980 val
= I915_READ(DPLL_CTRL1
);
981 hw_state
->ctrl1
= (val
>> (pll
->id
* 6)) & 0x3f;
986 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
991 struct skl_wrpll_context
{
992 uint64_t min_deviation
; /* current minimal deviation */
993 uint64_t central_freq
; /* chosen central freq */
994 uint64_t dco_freq
; /* chosen dco freq */
995 unsigned int p
; /* chosen divider */
998 static void skl_wrpll_context_init(struct skl_wrpll_context
*ctx
)
1000 memset(ctx
, 0, sizeof(*ctx
));
1002 ctx
->min_deviation
= U64_MAX
;
1005 /* DCO freq must be within +1%/-6% of the DCO central freq */
1006 #define SKL_DCO_MAX_PDEVIATION 100
1007 #define SKL_DCO_MAX_NDEVIATION 600
1009 static void skl_wrpll_try_divider(struct skl_wrpll_context
*ctx
,
1010 uint64_t central_freq
,
1012 unsigned int divider
)
1016 deviation
= div64_u64(10000 * abs_diff(dco_freq
, central_freq
),
1019 /* positive deviation */
1020 if (dco_freq
>= central_freq
) {
1021 if (deviation
< SKL_DCO_MAX_PDEVIATION
&&
1022 deviation
< ctx
->min_deviation
) {
1023 ctx
->min_deviation
= deviation
;
1024 ctx
->central_freq
= central_freq
;
1025 ctx
->dco_freq
= dco_freq
;
1028 /* negative deviation */
1029 } else if (deviation
< SKL_DCO_MAX_NDEVIATION
&&
1030 deviation
< ctx
->min_deviation
) {
1031 ctx
->min_deviation
= deviation
;
1032 ctx
->central_freq
= central_freq
;
1033 ctx
->dco_freq
= dco_freq
;
1038 static void skl_wrpll_get_multipliers(unsigned int p
,
1039 unsigned int *p0
/* out */,
1040 unsigned int *p1
/* out */,
1041 unsigned int *p2
/* out */)
1045 unsigned int half
= p
/ 2;
1047 if (half
== 1 || half
== 2 || half
== 3 || half
== 5) {
1051 } else if (half
% 2 == 0) {
1055 } else if (half
% 3 == 0) {
1059 } else if (half
% 7 == 0) {
1064 } else if (p
== 3 || p
== 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1068 } else if (p
== 5 || p
== 7) {
1072 } else if (p
== 15) {
1076 } else if (p
== 21) {
1080 } else if (p
== 35) {
1087 struct skl_wrpll_params
{
1088 uint32_t dco_fraction
;
1089 uint32_t dco_integer
;
1090 uint32_t qdiv_ratio
;
1094 uint32_t central_freq
;
1097 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1099 uint64_t central_freq
,
1100 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1104 switch (central_freq
) {
1106 params
->central_freq
= 0;
1109 params
->central_freq
= 1;
1112 params
->central_freq
= 3;
1129 WARN(1, "Incorrect PDiv\n");
1146 WARN(1, "Incorrect KDiv\n");
1149 params
->qdiv_ratio
= p1
;
1150 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1152 dco_freq
= p0
* p1
* p2
* afe_clock
;
1155 * Intermediate values are in Hz.
1156 * Divide by MHz to match bsepc
1158 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1159 params
->dco_fraction
=
1160 div_u64((div_u64(dco_freq
, 24) -
1161 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1165 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1166 struct skl_wrpll_params
*wrpll_params
)
1168 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1169 uint64_t dco_central_freq
[3] = {8400000000ULL,
1172 static const int even_dividers
[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1173 24, 28, 30, 32, 36, 40, 42, 44,
1174 48, 52, 54, 56, 60, 64, 66, 68,
1175 70, 72, 76, 78, 80, 84, 88, 90,
1177 static const int odd_dividers
[] = { 3, 5, 7, 9, 15, 21, 35 };
1178 static const struct {
1182 { even_dividers
, ARRAY_SIZE(even_dividers
) },
1183 { odd_dividers
, ARRAY_SIZE(odd_dividers
) },
1185 struct skl_wrpll_context ctx
;
1186 unsigned int dco
, d
, i
;
1187 unsigned int p0
, p1
, p2
;
1189 skl_wrpll_context_init(&ctx
);
1191 for (d
= 0; d
< ARRAY_SIZE(dividers
); d
++) {
1192 for (dco
= 0; dco
< ARRAY_SIZE(dco_central_freq
); dco
++) {
1193 for (i
= 0; i
< dividers
[d
].n_dividers
; i
++) {
1194 unsigned int p
= dividers
[d
].list
[i
];
1195 uint64_t dco_freq
= p
* afe_clock
;
1197 skl_wrpll_try_divider(&ctx
,
1198 dco_central_freq
[dco
],
1202 * Skip the remaining dividers if we're sure to
1203 * have found the definitive divider, we can't
1204 * improve a 0 deviation.
1206 if (ctx
.min_deviation
== 0)
1207 goto skip_remaining_dividers
;
1211 skip_remaining_dividers
:
1213 * If a solution is found with an even divider, prefer
1216 if (d
== 0 && ctx
.p
)
1221 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock
);
1226 * gcc incorrectly analyses that these can be used without being
1227 * initialized. To be fair, it's hard to guess.
1230 skl_wrpll_get_multipliers(ctx
.p
, &p0
, &p1
, &p2
);
1231 skl_wrpll_params_populate(wrpll_params
, afe_clock
, ctx
.central_freq
,
1237 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc
*crtc
,
1238 struct intel_crtc_state
*crtc_state
,
1241 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1242 struct skl_wrpll_params wrpll_params
= { 0, };
1245 * See comment in intel_dpll_hw_state to understand why we always use 0
1246 * as the DPLL id in this function.
1248 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1250 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1252 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1255 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1256 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1257 wrpll_params
.dco_integer
;
1259 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1260 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1261 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1262 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1263 wrpll_params
.central_freq
;
1265 memset(&crtc_state
->dpll_hw_state
, 0,
1266 sizeof(crtc_state
->dpll_hw_state
));
1268 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1269 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1270 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1275 bool skl_ddi_dp_set_dpll_hw_state(int clock
,
1276 struct intel_dpll_hw_state
*dpll_hw_state
)
1281 * See comment in intel_dpll_hw_state to understand why we always use 0
1282 * as the DPLL id in this function.
1284 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1285 switch (clock
/ 2) {
1287 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1290 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1293 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1297 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, 0);
1300 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, 0);
1303 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, 0);
1307 dpll_hw_state
->ctrl1
= ctrl1
;
1311 static struct intel_shared_dpll
*
1312 skl_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
1313 struct intel_encoder
*encoder
)
1315 struct intel_shared_dpll
*pll
;
1316 int clock
= crtc_state
->port_clock
;
1318 struct intel_dpll_hw_state dpll_hw_state
;
1320 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
1322 if (encoder
->type
== INTEL_OUTPUT_HDMI
) {
1323 bret
= skl_ddi_hdmi_pll_dividers(crtc
, crtc_state
, clock
);
1325 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1328 } else if (encoder
->type
== INTEL_OUTPUT_DP
||
1329 encoder
->type
== INTEL_OUTPUT_DP_MST
||
1330 encoder
->type
== INTEL_OUTPUT_EDP
) {
1331 bret
= skl_ddi_dp_set_dpll_hw_state(clock
, &dpll_hw_state
);
1333 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1336 crtc_state
->dpll_hw_state
= dpll_hw_state
;
1341 if (encoder
->type
== INTEL_OUTPUT_EDP
)
1342 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
1346 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
1352 intel_reference_shared_dpll(pll
, crtc_state
);
1357 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs
= {
1358 .enable
= skl_ddi_pll_enable
,
1359 .disable
= skl_ddi_pll_disable
,
1360 .get_hw_state
= skl_ddi_pll_get_hw_state
,
1363 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs
= {
1364 .enable
= skl_ddi_dpll0_enable
,
1365 .disable
= skl_ddi_dpll0_disable
,
1366 .get_hw_state
= skl_ddi_dpll0_get_hw_state
,
1369 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1370 struct intel_shared_dpll
*pll
)
1373 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
1375 enum dpio_channel ch
;
1377 bxt_port_to_phy_channel(port
, &phy
, &ch
);
1379 /* Non-SSC reference */
1380 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1381 temp
|= PORT_PLL_REF_SEL
;
1382 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
1384 /* Disable 10 bit clock */
1385 temp
= I915_READ(BXT_PORT_PLL_EBB_4(phy
, ch
));
1386 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
1387 I915_WRITE(BXT_PORT_PLL_EBB_4(phy
, ch
), temp
);
1390 temp
= I915_READ(BXT_PORT_PLL_EBB_0(phy
, ch
));
1391 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
1392 temp
|= pll
->config
.hw_state
.ebb0
;
1393 I915_WRITE(BXT_PORT_PLL_EBB_0(phy
, ch
), temp
);
1395 /* Write M2 integer */
1396 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 0));
1397 temp
&= ~PORT_PLL_M2_MASK
;
1398 temp
|= pll
->config
.hw_state
.pll0
;
1399 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 0), temp
);
1402 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 1));
1403 temp
&= ~PORT_PLL_N_MASK
;
1404 temp
|= pll
->config
.hw_state
.pll1
;
1405 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 1), temp
);
1407 /* Write M2 fraction */
1408 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 2));
1409 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
1410 temp
|= pll
->config
.hw_state
.pll2
;
1411 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 2), temp
);
1413 /* Write M2 fraction enable */
1414 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 3));
1415 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
1416 temp
|= pll
->config
.hw_state
.pll3
;
1417 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 3), temp
);
1420 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 6));
1421 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
1422 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
1423 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
1424 temp
|= pll
->config
.hw_state
.pll6
;
1425 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 6), temp
);
1427 /* Write calibration val */
1428 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 8));
1429 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
1430 temp
|= pll
->config
.hw_state
.pll8
;
1431 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 8), temp
);
1433 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 9));
1434 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
1435 temp
|= pll
->config
.hw_state
.pll9
;
1436 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 9), temp
);
1438 temp
= I915_READ(BXT_PORT_PLL(phy
, ch
, 10));
1439 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
1440 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
1441 temp
|= pll
->config
.hw_state
.pll10
;
1442 I915_WRITE(BXT_PORT_PLL(phy
, ch
, 10), temp
);
1444 /* Recalibrate with new settings */
1445 temp
= I915_READ(BXT_PORT_PLL_EBB_4(phy
, ch
));
1446 temp
|= PORT_PLL_RECALIBRATE
;
1447 I915_WRITE(BXT_PORT_PLL_EBB_4(phy
, ch
), temp
);
1448 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
1449 temp
|= pll
->config
.hw_state
.ebb4
;
1450 I915_WRITE(BXT_PORT_PLL_EBB_4(phy
, ch
), temp
);
1453 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1454 temp
|= PORT_PLL_ENABLE
;
1455 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
1456 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
1458 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) & PORT_PLL_LOCK
),
1460 DRM_ERROR("PLL %d not locked\n", port
);
1463 * While we write to the group register to program all lanes at once we
1464 * can read only lane registers and we pick lanes 0/1 for that.
1466 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(phy
, ch
));
1467 temp
&= ~LANE_STAGGER_MASK
;
1468 temp
&= ~LANESTAGGER_STRAP_OVRD
;
1469 temp
|= pll
->config
.hw_state
.pcsdw12
;
1470 I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy
, ch
), temp
);
1473 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1474 struct intel_shared_dpll
*pll
)
1476 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
1479 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1480 temp
&= ~PORT_PLL_ENABLE
;
1481 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
1482 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
1485 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1486 struct intel_shared_dpll
*pll
,
1487 struct intel_dpll_hw_state
*hw_state
)
1489 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
1493 enum dpio_channel ch
;
1495 bxt_port_to_phy_channel(port
, &phy
, &ch
);
1497 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1502 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1503 if (!(val
& PORT_PLL_ENABLE
))
1506 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(phy
, ch
));
1507 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
1509 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(phy
, ch
));
1510 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
1512 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(phy
, ch
, 0));
1513 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
1515 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(phy
, ch
, 1));
1516 hw_state
->pll1
&= PORT_PLL_N_MASK
;
1518 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(phy
, ch
, 2));
1519 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
1521 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(phy
, ch
, 3));
1522 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
1524 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(phy
, ch
, 6));
1525 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
1526 PORT_PLL_INT_COEFF_MASK
|
1527 PORT_PLL_GAIN_CTL_MASK
;
1529 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(phy
, ch
, 8));
1530 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
1532 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(phy
, ch
, 9));
1533 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
1535 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(phy
, ch
, 10));
1536 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
1537 PORT_PLL_DCO_AMP_MASK
;
1540 * While we write to the group register to program all lanes at once we
1541 * can read only lane registers. We configure all lanes the same way, so
1542 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1544 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(phy
, ch
));
1545 if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy
, ch
)) != hw_state
->pcsdw12
)
1546 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1548 I915_READ(BXT_PORT_PCS_DW12_LN23(phy
, ch
)));
1549 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
1554 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1559 /* bxt clock parameters */
1560 struct bxt_clk_div
{
1572 /* pre-calculated values for DP linkrates */
1573 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1574 {162000, 4, 2, 32, 1677722, 1, 1},
1575 {270000, 4, 1, 27, 0, 0, 1},
1576 {540000, 2, 1, 27, 0, 0, 1},
1577 {216000, 3, 2, 32, 1677722, 1, 1},
1578 {243000, 4, 1, 24, 1258291, 1, 1},
1579 {324000, 4, 1, 32, 1677722, 1, 1},
1580 {432000, 3, 1, 32, 1677722, 1, 1}
1584 bxt_ddi_hdmi_pll_dividers(struct intel_crtc
*intel_crtc
,
1585 struct intel_crtc_state
*crtc_state
, int clock
,
1586 struct bxt_clk_div
*clk_div
)
1588 struct dpll best_clock
;
1590 /* Calculate HDMI div */
1592 * FIXME: tie the following calculation into
1593 * i9xx_crtc_compute_clock
1595 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1596 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1597 clock
, pipe_name(intel_crtc
->pipe
));
1601 clk_div
->p1
= best_clock
.p1
;
1602 clk_div
->p2
= best_clock
.p2
;
1603 WARN_ON(best_clock
.m1
!= 2);
1604 clk_div
->n
= best_clock
.n
;
1605 clk_div
->m2_int
= best_clock
.m2
>> 22;
1606 clk_div
->m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1607 clk_div
->m2_frac_en
= clk_div
->m2_frac
!= 0;
1609 clk_div
->vco
= best_clock
.vco
;
1614 static void bxt_ddi_dp_pll_dividers(int clock
, struct bxt_clk_div
*clk_div
)
1618 *clk_div
= bxt_dp_clk_val
[0];
1619 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1620 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1621 *clk_div
= bxt_dp_clk_val
[i
];
1626 clk_div
->vco
= clock
* 10 / 2 * clk_div
->p1
* clk_div
->p2
;
1629 static bool bxt_ddi_set_dpll_hw_state(int clock
,
1630 struct bxt_clk_div
*clk_div
,
1631 struct intel_dpll_hw_state
*dpll_hw_state
)
1633 int vco
= clk_div
->vco
;
1634 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1635 uint32_t lanestagger
;
1637 if (vco
>= 6200000 && vco
<= 6700000) {
1642 } else if ((vco
> 5400000 && vco
< 6200000) ||
1643 (vco
>= 4800000 && vco
< 5400000)) {
1648 } else if (vco
== 5400000) {
1654 DRM_ERROR("Invalid VCO\n");
1660 else if (clock
> 135000)
1662 else if (clock
> 67000)
1664 else if (clock
> 33000)
1669 dpll_hw_state
->ebb0
= PORT_PLL_P1(clk_div
->p1
) | PORT_PLL_P2(clk_div
->p2
);
1670 dpll_hw_state
->pll0
= clk_div
->m2_int
;
1671 dpll_hw_state
->pll1
= PORT_PLL_N(clk_div
->n
);
1672 dpll_hw_state
->pll2
= clk_div
->m2_frac
;
1674 if (clk_div
->m2_frac_en
)
1675 dpll_hw_state
->pll3
= PORT_PLL_M2_FRAC_ENABLE
;
1677 dpll_hw_state
->pll6
= prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1678 dpll_hw_state
->pll6
|= PORT_PLL_GAIN_CTL(gain_ctl
);
1680 dpll_hw_state
->pll8
= targ_cnt
;
1682 dpll_hw_state
->pll9
= 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT
;
1684 dpll_hw_state
->pll10
=
1685 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT
)
1686 | PORT_PLL_DCO_AMP_OVR_EN_H
;
1688 dpll_hw_state
->ebb4
= PORT_PLL_10BIT_CLK_ENABLE
;
1690 dpll_hw_state
->pcsdw12
= LANESTAGGER_STRAP_OVRD
| lanestagger
;
1695 bool bxt_ddi_dp_set_dpll_hw_state(int clock
,
1696 struct intel_dpll_hw_state
*dpll_hw_state
)
1698 struct bxt_clk_div clk_div
= {0};
1700 bxt_ddi_dp_pll_dividers(clock
, &clk_div
);
1702 return bxt_ddi_set_dpll_hw_state(clock
, &clk_div
, dpll_hw_state
);
1706 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc
*intel_crtc
,
1707 struct intel_crtc_state
*crtc_state
, int clock
,
1708 struct intel_dpll_hw_state
*dpll_hw_state
)
1710 struct bxt_clk_div clk_div
= { };
1712 bxt_ddi_hdmi_pll_dividers(intel_crtc
, crtc_state
, clock
, &clk_div
);
1714 return bxt_ddi_set_dpll_hw_state(clock
, &clk_div
, dpll_hw_state
);
1717 static struct intel_shared_dpll
*
1718 bxt_get_dpll(struct intel_crtc
*crtc
,
1719 struct intel_crtc_state
*crtc_state
,
1720 struct intel_encoder
*encoder
)
1722 struct intel_dpll_hw_state dpll_hw_state
= { };
1723 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1724 struct intel_digital_port
*intel_dig_port
;
1725 struct intel_shared_dpll
*pll
;
1726 int i
, clock
= crtc_state
->port_clock
;
1728 if (encoder
->type
== INTEL_OUTPUT_HDMI
&&
1729 !bxt_ddi_hdmi_set_dpll_hw_state(crtc
, crtc_state
, clock
,
1733 if ((encoder
->type
== INTEL_OUTPUT_DP
||
1734 encoder
->type
== INTEL_OUTPUT_EDP
) &&
1735 !bxt_ddi_dp_set_dpll_hw_state(clock
, &dpll_hw_state
))
1738 memset(&crtc_state
->dpll_hw_state
, 0,
1739 sizeof(crtc_state
->dpll_hw_state
));
1741 crtc_state
->dpll_hw_state
= dpll_hw_state
;
1743 if (encoder
->type
== INTEL_OUTPUT_DP_MST
) {
1744 struct intel_dp_mst_encoder
*intel_mst
= enc_to_mst(&encoder
->base
);
1746 intel_dig_port
= intel_mst
->primary
;
1748 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
1750 /* 1:1 mapping between ports and PLLs */
1751 i
= (enum intel_dpll_id
) intel_dig_port
->port
;
1752 pll
= intel_get_shared_dpll_by_id(dev_priv
, i
);
1754 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1755 crtc
->base
.base
.id
, crtc
->base
.name
, pll
->name
);
1757 intel_reference_shared_dpll(pll
, crtc_state
);
1762 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs
= {
1763 .enable
= bxt_ddi_pll_enable
,
1764 .disable
= bxt_ddi_pll_disable
,
1765 .get_hw_state
= bxt_ddi_pll_get_hw_state
,
1768 static void intel_ddi_pll_init(struct drm_device
*dev
)
1770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1772 if (INTEL_GEN(dev_priv
) < 9) {
1773 uint32_t val
= I915_READ(LCPLL_CTL
);
1776 * The LCPLL register should be turned on by the BIOS. For now
1777 * let's just check its state and print errors in case
1778 * something is wrong. Don't even try to turn it on.
1781 if (val
& LCPLL_CD_SOURCE_FCLK
)
1782 DRM_ERROR("CDCLK source is not LCPLL\n");
1784 if (val
& LCPLL_PLL_DISABLE
)
1785 DRM_ERROR("LCPLL is disabled\n");
1792 const struct intel_shared_dpll_funcs
*funcs
;
1796 struct intel_dpll_mgr
{
1797 const struct dpll_info
*dpll_info
;
1799 struct intel_shared_dpll
*(*get_dpll
)(struct intel_crtc
*crtc
,
1800 struct intel_crtc_state
*crtc_state
,
1801 struct intel_encoder
*encoder
);
1804 static const struct dpll_info pch_plls
[] = {
1805 { "PCH DPLL A", DPLL_ID_PCH_PLL_A
, &ibx_pch_dpll_funcs
, 0 },
1806 { "PCH DPLL B", DPLL_ID_PCH_PLL_B
, &ibx_pch_dpll_funcs
, 0 },
1807 { NULL
, -1, NULL
, 0 },
1810 static const struct intel_dpll_mgr pch_pll_mgr
= {
1811 .dpll_info
= pch_plls
,
1812 .get_dpll
= ibx_get_dpll
,
1815 static const struct dpll_info hsw_plls
[] = {
1816 { "WRPLL 1", DPLL_ID_WRPLL1
, &hsw_ddi_wrpll_funcs
, 0 },
1817 { "WRPLL 2", DPLL_ID_WRPLL2
, &hsw_ddi_wrpll_funcs
, 0 },
1818 { "SPLL", DPLL_ID_SPLL
, &hsw_ddi_spll_funcs
, 0 },
1819 { "LCPLL 810", DPLL_ID_LCPLL_810
, &hsw_ddi_lcpll_funcs
, INTEL_DPLL_ALWAYS_ON
},
1820 { "LCPLL 1350", DPLL_ID_LCPLL_1350
, &hsw_ddi_lcpll_funcs
, INTEL_DPLL_ALWAYS_ON
},
1821 { "LCPLL 2700", DPLL_ID_LCPLL_2700
, &hsw_ddi_lcpll_funcs
, INTEL_DPLL_ALWAYS_ON
},
1822 { NULL
, -1, NULL
, },
1825 static const struct intel_dpll_mgr hsw_pll_mgr
= {
1826 .dpll_info
= hsw_plls
,
1827 .get_dpll
= hsw_get_dpll
,
1830 static const struct dpll_info skl_plls
[] = {
1831 { "DPLL 0", DPLL_ID_SKL_DPLL0
, &skl_ddi_dpll0_funcs
, INTEL_DPLL_ALWAYS_ON
},
1832 { "DPLL 1", DPLL_ID_SKL_DPLL1
, &skl_ddi_pll_funcs
, 0 },
1833 { "DPLL 2", DPLL_ID_SKL_DPLL2
, &skl_ddi_pll_funcs
, 0 },
1834 { "DPLL 3", DPLL_ID_SKL_DPLL3
, &skl_ddi_pll_funcs
, 0 },
1835 { NULL
, -1, NULL
, },
1838 static const struct intel_dpll_mgr skl_pll_mgr
= {
1839 .dpll_info
= skl_plls
,
1840 .get_dpll
= skl_get_dpll
,
1843 static const struct dpll_info bxt_plls
[] = {
1844 { "PORT PLL A", DPLL_ID_SKL_DPLL0
, &bxt_ddi_pll_funcs
, 0 },
1845 { "PORT PLL B", DPLL_ID_SKL_DPLL1
, &bxt_ddi_pll_funcs
, 0 },
1846 { "PORT PLL C", DPLL_ID_SKL_DPLL2
, &bxt_ddi_pll_funcs
, 0 },
1847 { NULL
, -1, NULL
, },
1850 static const struct intel_dpll_mgr bxt_pll_mgr
= {
1851 .dpll_info
= bxt_plls
,
1852 .get_dpll
= bxt_get_dpll
,
1855 void intel_shared_dpll_init(struct drm_device
*dev
)
1857 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1858 const struct intel_dpll_mgr
*dpll_mgr
= NULL
;
1859 const struct dpll_info
*dpll_info
;
1862 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
1863 dpll_mgr
= &skl_pll_mgr
;
1864 else if (IS_BROXTON(dev_priv
))
1865 dpll_mgr
= &bxt_pll_mgr
;
1866 else if (HAS_DDI(dev_priv
))
1867 dpll_mgr
= &hsw_pll_mgr
;
1868 else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
1869 dpll_mgr
= &pch_pll_mgr
;
1872 dev_priv
->num_shared_dpll
= 0;
1876 dpll_info
= dpll_mgr
->dpll_info
;
1878 for (i
= 0; dpll_info
[i
].id
>= 0; i
++) {
1879 WARN_ON(i
!= dpll_info
[i
].id
);
1881 dev_priv
->shared_dplls
[i
].id
= dpll_info
[i
].id
;
1882 dev_priv
->shared_dplls
[i
].name
= dpll_info
[i
].name
;
1883 dev_priv
->shared_dplls
[i
].funcs
= *dpll_info
[i
].funcs
;
1884 dev_priv
->shared_dplls
[i
].flags
= dpll_info
[i
].flags
;
1887 dev_priv
->dpll_mgr
= dpll_mgr
;
1888 dev_priv
->num_shared_dpll
= i
;
1889 mutex_init(&dev_priv
->dpll_lock
);
1891 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
1893 /* FIXME: Move this to a more suitable place */
1894 if (HAS_DDI(dev_priv
))
1895 intel_ddi_pll_init(dev
);
1898 struct intel_shared_dpll
*
1899 intel_get_shared_dpll(struct intel_crtc
*crtc
,
1900 struct intel_crtc_state
*crtc_state
,
1901 struct intel_encoder
*encoder
)
1903 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1904 const struct intel_dpll_mgr
*dpll_mgr
= dev_priv
->dpll_mgr
;
1906 if (WARN_ON(!dpll_mgr
))
1909 return dpll_mgr
->get_dpll(crtc
, crtc_state
, encoder
);