2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 ADVANCED_CONTEXT
= 0,
205 #define GEN8_CTX_MODE_SHIFT 3
208 FAULT_AND_HALT
, /* Debug only */
210 FAULT_AND_CONTINUE
/* Unsupported */
212 #define GEN8_CTX_ID_SHIFT 32
213 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
215 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
218 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
220 * @enable_execlists: value of i915.enable_execlists module parameter.
222 * Only certain platforms support Execlists (the prerequisites being
223 * support for Logical Ring Contexts and Aliasing PPGTT or better).
225 * Return: 1 if Execlists is supported and has to be enabled.
227 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
229 WARN_ON(i915
.enable_ppgtt
== -1);
231 if (INTEL_INFO(dev
)->gen
>= 9)
234 if (enable_execlists
== 0)
237 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
238 i915
.use_mmio_flip
>= 0)
245 * intel_execlists_ctx_id() - get the Execlists Context ID
246 * @ctx_obj: Logical Ring Context backing object.
248 * Do not confuse with ctx->id! Unfortunately we have a name overload
249 * here: the old context ID we pass to userspace as a handler so that
250 * they can refer to a context, and the new context ID we pass to the
251 * ELSP so that the GPU can inform us of the context status via
254 * Return: 20-bits globally unique context ID.
256 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
258 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
260 /* LRCA is required to be 4K aligned so the more significant 20 bits
261 * are globally unique */
265 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request
*rq
)
267 struct intel_engine_cs
*ring
= rq
->ring
;
268 struct drm_device
*dev
= ring
->dev
;
269 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
271 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
273 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
275 desc
= GEN8_CTX_VALID
;
276 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
277 if (IS_GEN8(ctx_obj
->base
.dev
))
278 desc
|= GEN8_CTX_L3LLC_COHERENT
;
279 desc
|= GEN8_CTX_PRIVILEGE
;
281 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
283 /* TODO: WaDisableLiteRestore when we start using semaphore
284 * signalling between Command Streamers */
285 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
290 (ring
->id
== BCS
|| ring
->id
== VCS
||
291 ring
->id
== VECS
|| ring
->id
== VCS2
))
292 desc
|= GEN8_CTX_FORCE_RESTORE
;
297 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
298 struct drm_i915_gem_request
*rq1
)
301 struct intel_engine_cs
*ring
= rq0
->ring
;
302 struct drm_device
*dev
= ring
->dev
;
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
307 desc
[1] = execlists_ctx_descriptor(rq1
);
308 rq1
->elsp_submitted
++;
313 desc
[0] = execlists_ctx_descriptor(rq0
);
314 rq0
->elsp_submitted
++;
316 /* You must always write both descriptors in the order below. */
317 spin_lock(&dev_priv
->uncore
.lock
);
318 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
319 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
320 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
322 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
323 /* The context is automatically loaded after the following */
324 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
326 /* ELSP is a wo register, use another nearby reg for posting */
327 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
328 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
329 spin_unlock(&dev_priv
->uncore
.lock
);
332 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
334 struct intel_engine_cs
*ring
= rq
->ring
;
335 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
336 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
337 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
342 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
343 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
345 page
= i915_gem_object_get_page(ctx_obj
, 1);
346 reg_state
= kmap_atomic(page
);
348 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
349 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
351 /* True PPGTT with dynamic page allocation: update PDP registers and
352 * point the unallocated PDPs to the scratch page
355 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
356 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
357 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
358 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
361 kunmap_atomic(reg_state
);
366 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
367 struct drm_i915_gem_request
*rq1
)
369 execlists_update_context(rq0
);
372 execlists_update_context(rq1
);
374 execlists_elsp_write(rq0
, rq1
);
377 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
379 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
380 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
382 assert_spin_locked(&ring
->execlist_lock
);
385 * If irqs are not active generate a warning as batches that finish
386 * without the irqs may get lost and a GPU Hang may occur.
388 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
390 if (list_empty(&ring
->execlist_queue
))
393 /* Try to read in pairs */
394 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
398 } else if (req0
->ctx
== cursor
->ctx
) {
399 /* Same ctx: ignore first request, as second request
400 * will update tail past first request's workload */
401 cursor
->elsp_submitted
= req0
->elsp_submitted
;
402 list_del(&req0
->execlist_link
);
403 list_add_tail(&req0
->execlist_link
,
404 &ring
->execlist_retired_req_list
);
412 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
414 * WaIdleLiteRestore: make sure we never cause a lite
415 * restore with HEAD==TAIL
417 if (req0
->elsp_submitted
) {
419 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
420 * as we resubmit the request. See gen8_emit_request()
421 * for where we prepare the padding after the end of the
424 struct intel_ringbuffer
*ringbuf
;
426 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
428 req0
->tail
&= ringbuf
->size
- 1;
432 WARN_ON(req1
&& req1
->elsp_submitted
);
434 execlists_submit_requests(req0
, req1
);
437 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
440 struct drm_i915_gem_request
*head_req
;
442 assert_spin_locked(&ring
->execlist_lock
);
444 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
445 struct drm_i915_gem_request
,
448 if (head_req
!= NULL
) {
449 struct drm_i915_gem_object
*ctx_obj
=
450 head_req
->ctx
->engine
[ring
->id
].state
;
451 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
452 WARN(head_req
->elsp_submitted
== 0,
453 "Never submitted head request\n");
455 if (--head_req
->elsp_submitted
<= 0) {
456 list_del(&head_req
->execlist_link
);
457 list_add_tail(&head_req
->execlist_link
,
458 &ring
->execlist_retired_req_list
);
468 * intel_lrc_irq_handler() - handle Context Switch interrupts
469 * @ring: Engine Command Streamer to handle.
471 * Check the unread Context Status Buffers and manage the submission of new
472 * contexts to the ELSP accordingly.
474 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
476 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
482 u32 submit_contexts
= 0;
484 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
486 read_pointer
= ring
->next_context_status_buffer
;
487 write_pointer
= status_pointer
& 0x07;
488 if (read_pointer
> write_pointer
)
491 spin_lock(&ring
->execlist_lock
);
493 while (read_pointer
< write_pointer
) {
495 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
496 (read_pointer
% 6) * 8);
497 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
498 (read_pointer
% 6) * 8 + 4);
500 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
503 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
504 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
505 if (execlists_check_remove_request(ring
, status_id
))
506 WARN(1, "Lite Restored request removed from queue\n");
508 WARN(1, "Preemption without Lite Restore\n");
511 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
512 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
513 if (execlists_check_remove_request(ring
, status_id
))
518 if (submit_contexts
!= 0)
519 execlists_context_unqueue(ring
);
521 spin_unlock(&ring
->execlist_lock
);
523 WARN(submit_contexts
> 2, "More than two context complete events?\n");
524 ring
->next_context_status_buffer
= write_pointer
% 6;
526 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
527 _MASKED_FIELD(0x07 << 8, ((u32
)ring
->next_context_status_buffer
& 0x07) << 8));
530 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
532 struct intel_engine_cs
*ring
= request
->ring
;
533 struct drm_i915_gem_request
*cursor
;
534 int num_elements
= 0;
536 if (request
->ctx
!= ring
->default_context
)
537 intel_lr_context_pin(request
);
539 i915_gem_request_reference(request
);
541 request
->tail
= request
->ringbuf
->tail
;
543 spin_lock_irq(&ring
->execlist_lock
);
545 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
546 if (++num_elements
> 2)
549 if (num_elements
> 2) {
550 struct drm_i915_gem_request
*tail_req
;
552 tail_req
= list_last_entry(&ring
->execlist_queue
,
553 struct drm_i915_gem_request
,
556 if (request
->ctx
== tail_req
->ctx
) {
557 WARN(tail_req
->elsp_submitted
!= 0,
558 "More than 2 already-submitted reqs queued\n");
559 list_del(&tail_req
->execlist_link
);
560 list_add_tail(&tail_req
->execlist_link
,
561 &ring
->execlist_retired_req_list
);
565 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
566 if (num_elements
== 0)
567 execlists_context_unqueue(ring
);
569 spin_unlock_irq(&ring
->execlist_lock
);
574 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
576 struct intel_engine_cs
*ring
= req
->ring
;
577 uint32_t flush_domains
;
581 if (ring
->gpu_caches_dirty
)
582 flush_domains
= I915_GEM_GPU_DOMAINS
;
584 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
588 ring
->gpu_caches_dirty
= false;
592 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
593 struct list_head
*vmas
)
595 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
596 struct i915_vma
*vma
;
597 uint32_t flush_domains
= 0;
598 bool flush_chipset
= false;
601 list_for_each_entry(vma
, vmas
, exec_list
) {
602 struct drm_i915_gem_object
*obj
= vma
->obj
;
604 if (obj
->active
& other_rings
) {
605 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
610 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
611 flush_chipset
|= i915_gem_clflush_object(obj
, false);
613 flush_domains
|= obj
->base
.write_domain
;
616 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
619 /* Unconditionally invalidate gpu caches and ensure that we do flush
620 * any residual writes from the previous batch.
622 return logical_ring_invalidate_all_caches(req
);
625 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
629 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
631 if (request
->ctx
!= request
->ring
->default_context
) {
632 ret
= intel_lr_context_pin(request
);
640 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
643 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
644 struct intel_engine_cs
*ring
= req
->ring
;
645 struct drm_i915_gem_request
*target
;
649 if (intel_ring_space(ringbuf
) >= bytes
)
652 /* The whole point of reserving space is to not wait! */
653 WARN_ON(ringbuf
->reserved_in_use
);
655 list_for_each_entry(target
, &ring
->request_list
, list
) {
657 * The request queue is per-engine, so can contain requests
658 * from multiple ringbuffers. Here, we must ignore any that
659 * aren't from the ringbuffer we're considering.
661 if (target
->ringbuf
!= ringbuf
)
664 /* Would completion of this request free enough space? */
665 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
671 if (WARN_ON(&target
->list
== &ring
->request_list
))
674 ret
= i915_wait_request(target
);
678 ringbuf
->space
= space
;
683 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
684 * @request: Request to advance the logical ringbuffer of.
686 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
687 * really happens during submission is that the context and current tail will be placed
688 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
689 * point, the tail *inside* the context is updated and the ELSP written to.
692 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
694 struct intel_engine_cs
*ring
= request
->ring
;
696 intel_logical_ring_advance(request
->ringbuf
);
698 if (intel_ring_stopped(ring
))
701 execlists_context_queue(request
);
704 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
706 uint32_t __iomem
*virt
;
707 int rem
= ringbuf
->size
- ringbuf
->tail
;
709 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
712 iowrite32(MI_NOOP
, virt
++);
715 intel_ring_update_space(ringbuf
);
718 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
720 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
721 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
722 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
723 int ret
, total_bytes
, wait_bytes
= 0;
724 bool need_wrap
= false;
726 if (ringbuf
->reserved_in_use
)
729 total_bytes
= bytes
+ ringbuf
->reserved_size
;
731 if (unlikely(bytes
> remain_usable
)) {
733 * Not enough space for the basic request. So need to flush
734 * out the remainder and then wait for base + reserved.
736 wait_bytes
= remain_actual
+ total_bytes
;
739 if (unlikely(total_bytes
> remain_usable
)) {
741 * The base request will fit but the reserved space
742 * falls off the end. So only need to to wait for the
743 * reserved size after flushing out the remainder.
745 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
747 } else if (total_bytes
> ringbuf
->space
) {
748 /* No wrapping required, just waiting. */
749 wait_bytes
= total_bytes
;
754 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
759 __wrap_ring_buffer(ringbuf
);
766 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
768 * @request: The request to start some new work for
769 * @ctx: Logical ring context whose ringbuffer is being prepared.
770 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
772 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
773 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
774 * and also preallocates a request (every workload submission is still mediated through
775 * requests, same as it did with legacy ringbuffer submission).
777 * Return: non-zero if the ringbuffer is not ready to be written to.
779 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
781 struct drm_i915_private
*dev_priv
;
784 WARN_ON(req
== NULL
);
785 dev_priv
= req
->ring
->dev
->dev_private
;
787 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
788 dev_priv
->mm
.interruptible
);
792 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
796 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
800 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
803 * The first call merely notes the reserve request and is common for
804 * all back ends. The subsequent localised _begin() call actually
805 * ensures that the reservation is available. Without the begin, if
806 * the request creator immediately submitted the request without
807 * adding any commands to it then there might not actually be
808 * sufficient room for the submission commands.
810 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
812 return intel_logical_ring_begin(request
, 0);
816 * execlists_submission() - submit a batchbuffer for execution, Execlists style
819 * @ring: Engine Command Streamer to submit to.
820 * @ctx: Context to employ for this submission.
821 * @args: execbuffer call arguments.
822 * @vmas: list of vmas.
823 * @batch_obj: the batchbuffer to submit.
824 * @exec_start: batchbuffer start virtual address pointer.
825 * @dispatch_flags: translated execbuffer call flags.
827 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
828 * away the submission details of the execbuffer ioctl call.
830 * Return: non-zero if the submission fails.
832 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
833 struct drm_i915_gem_execbuffer2
*args
,
834 struct list_head
*vmas
)
836 struct drm_device
*dev
= params
->dev
;
837 struct intel_engine_cs
*ring
= params
->ring
;
838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
839 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
845 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
846 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
847 switch (instp_mode
) {
848 case I915_EXEC_CONSTANTS_REL_GENERAL
:
849 case I915_EXEC_CONSTANTS_ABSOLUTE
:
850 case I915_EXEC_CONSTANTS_REL_SURFACE
:
851 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
852 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
856 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
857 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
858 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
862 /* The HW changed the meaning on this bit on gen6 */
863 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
867 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
871 if (args
->num_cliprects
!= 0) {
872 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
875 if (args
->DR4
== 0xffffffff) {
876 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
880 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
881 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
886 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
887 DRM_DEBUG("sol reset is gen7 only\n");
891 ret
= execlists_move_to_gpu(params
->request
, vmas
);
895 if (ring
== &dev_priv
->ring
[RCS
] &&
896 instp_mode
!= dev_priv
->relative_constants_mode
) {
897 ret
= intel_logical_ring_begin(params
->request
, 4);
901 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
902 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
903 intel_logical_ring_emit(ringbuf
, INSTPM
);
904 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
905 intel_logical_ring_advance(ringbuf
);
907 dev_priv
->relative_constants_mode
= instp_mode
;
910 exec_start
= params
->batch_obj_vm_offset
+
911 args
->batch_start_offset
;
913 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
917 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
919 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
920 i915_gem_execbuffer_retire_commands(params
);
925 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
927 struct drm_i915_gem_request
*req
, *tmp
;
928 struct list_head retired_list
;
930 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
931 if (list_empty(&ring
->execlist_retired_req_list
))
934 INIT_LIST_HEAD(&retired_list
);
935 spin_lock_irq(&ring
->execlist_lock
);
936 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
937 spin_unlock_irq(&ring
->execlist_lock
);
939 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
940 struct intel_context
*ctx
= req
->ctx
;
941 struct drm_i915_gem_object
*ctx_obj
=
942 ctx
->engine
[ring
->id
].state
;
944 if (ctx_obj
&& (ctx
!= ring
->default_context
))
945 intel_lr_context_unpin(req
);
946 list_del(&req
->execlist_link
);
947 i915_gem_request_unreference(req
);
951 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
953 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
956 if (!intel_ring_initialized(ring
))
959 ret
= intel_ring_idle(ring
);
960 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
961 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
964 /* TODO: Is this correct with Execlists enabled? */
965 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
966 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
967 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
970 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
973 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
975 struct intel_engine_cs
*ring
= req
->ring
;
978 if (!ring
->gpu_caches_dirty
)
981 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
985 ring
->gpu_caches_dirty
= false;
989 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
991 struct intel_engine_cs
*ring
= rq
->ring
;
992 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
993 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
996 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
997 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
998 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
999 GEN8_LR_CONTEXT_ALIGN
, 0);
1001 goto reset_pin_count
;
1003 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1011 i915_gem_object_ggtt_unpin(ctx_obj
);
1013 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1018 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1020 struct intel_engine_cs
*ring
= rq
->ring
;
1021 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1022 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1025 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1026 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1027 intel_unpin_ringbuffer_obj(ringbuf
);
1028 i915_gem_object_ggtt_unpin(ctx_obj
);
1033 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1036 struct intel_engine_cs
*ring
= req
->ring
;
1037 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1038 struct drm_device
*dev
= ring
->dev
;
1039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1042 if (WARN_ON_ONCE(w
->count
== 0))
1045 ring
->gpu_caches_dirty
= true;
1046 ret
= logical_ring_flush_all_caches(req
);
1050 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1054 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1055 for (i
= 0; i
< w
->count
; i
++) {
1056 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1057 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1059 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1061 intel_logical_ring_advance(ringbuf
);
1063 ring
->gpu_caches_dirty
= true;
1064 ret
= logical_ring_flush_all_caches(req
);
1071 #define wa_ctx_emit(batch, index, cmd) \
1073 int __index = (index)++; \
1074 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1077 batch[__index] = (cmd); \
1082 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1083 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1084 * but there is a slight complication as this is applied in WA batch where the
1085 * values are only initialized once so we cannot take register value at the
1086 * beginning and reuse it further; hence we save its value to memory, upload a
1087 * constant value with bit21 set and then we restore it back with the saved value.
1088 * To simplify the WA, a constant value is formed by using the default value
1089 * of this register. This shouldn't be a problem because we are only modifying
1090 * it for a short period and this batch in non-premptible. We can ofcourse
1091 * use additional instructions that read the actual value of the register
1092 * at that time and set our bit of interest but it makes the WA complicated.
1094 * This WA is also required for Gen9 so extracting as a function avoids
1097 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1098 uint32_t *const batch
,
1101 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1104 * WaDisableLSQCROPERFforOCL:skl
1105 * This WA is implemented in skl_init_clock_gating() but since
1106 * this batch updates GEN8_L3SQCREG4 with default value we need to
1107 * set this bit here to retain the WA during flush.
1109 if (IS_SKYLAKE(ring
->dev
) && INTEL_REVID(ring
->dev
) <= SKL_REVID_E0
)
1110 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1112 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8(1) |
1113 MI_SRM_LRM_GLOBAL_GTT
));
1114 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1115 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1116 wa_ctx_emit(batch
, index
, 0);
1118 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1119 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1120 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1122 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1123 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1124 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1125 wa_ctx_emit(batch
, index
, 0);
1126 wa_ctx_emit(batch
, index
, 0);
1127 wa_ctx_emit(batch
, index
, 0);
1128 wa_ctx_emit(batch
, index
, 0);
1130 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8(1) |
1131 MI_SRM_LRM_GLOBAL_GTT
));
1132 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1133 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1134 wa_ctx_emit(batch
, index
, 0);
1139 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1141 uint32_t start_alignment
)
1143 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1146 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1148 uint32_t size_alignment
)
1150 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1152 WARN(wa_ctx
->size
% size_alignment
,
1153 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1154 wa_ctx
->size
, size_alignment
);
1159 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1161 * @ring: only applicable for RCS
1162 * @wa_ctx: structure representing wa_ctx
1163 * offset: specifies start of the batch, should be cache-aligned. This is updated
1164 * with the offset value received as input.
1165 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1166 * @batch: page in which WA are loaded
1167 * @offset: This field specifies the start of the batch, it should be
1168 * cache-aligned otherwise it is adjusted accordingly.
1169 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1170 * initialized at the beginning and shared across all contexts but this field
1171 * helps us to have multiple batches at different offsets and select them based
1172 * on a criteria. At the moment this batch always start at the beginning of the page
1173 * and at this point we don't have multiple wa_ctx batch buffers.
1175 * The number of WA applied are not known at the beginning; we use this field
1176 * to return the no of DWORDS written.
1178 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1179 * so it adds NOOPs as padding to make it cacheline aligned.
1180 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1181 * makes a complete batch buffer.
1183 * Return: non-zero if we exceed the PAGE_SIZE limit.
1186 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1187 struct i915_wa_ctx_bb
*wa_ctx
,
1188 uint32_t *const batch
,
1191 uint32_t scratch_addr
;
1192 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1194 /* WaDisableCtxRestoreArbitration:bdw,chv */
1195 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1197 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1198 if (IS_BROADWELL(ring
->dev
)) {
1199 index
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1204 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1205 /* Actual scratch location is at 128 bytes offset */
1206 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1208 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1209 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1210 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1211 PIPE_CONTROL_CS_STALL
|
1212 PIPE_CONTROL_QW_WRITE
));
1213 wa_ctx_emit(batch
, index
, scratch_addr
);
1214 wa_ctx_emit(batch
, index
, 0);
1215 wa_ctx_emit(batch
, index
, 0);
1216 wa_ctx_emit(batch
, index
, 0);
1218 /* Pad to end of cacheline */
1219 while (index
% CACHELINE_DWORDS
)
1220 wa_ctx_emit(batch
, index
, MI_NOOP
);
1223 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1224 * execution depends on the length specified in terms of cache lines
1225 * in the register CTX_RCS_INDIRECT_CTX
1228 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1232 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1234 * @ring: only applicable for RCS
1235 * @wa_ctx: structure representing wa_ctx
1236 * offset: specifies start of the batch, should be cache-aligned.
1237 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1238 * @batch: page in which WA are loaded
1239 * @offset: This field specifies the start of this batch.
1240 * This batch is started immediately after indirect_ctx batch. Since we ensure
1241 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1243 * The number of DWORDS written are returned using this field.
1245 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1246 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1248 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1249 struct i915_wa_ctx_bb
*wa_ctx
,
1250 uint32_t *const batch
,
1253 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1255 /* WaDisableCtxRestoreArbitration:bdw,chv */
1256 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1258 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1260 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1263 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1264 struct i915_wa_ctx_bb
*wa_ctx
,
1265 uint32_t *const batch
,
1269 struct drm_device
*dev
= ring
->dev
;
1270 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1272 /* WaDisableCtxRestoreArbitration:skl,bxt */
1273 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1274 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1275 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1277 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1278 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1283 /* Pad to end of cacheline */
1284 while (index
% CACHELINE_DWORDS
)
1285 wa_ctx_emit(batch
, index
, MI_NOOP
);
1287 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1290 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1291 struct i915_wa_ctx_bb
*wa_ctx
,
1292 uint32_t *const batch
,
1295 struct drm_device
*dev
= ring
->dev
;
1296 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1298 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1299 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_B0
)) ||
1300 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
))) {
1301 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1302 wa_ctx_emit(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1303 wa_ctx_emit(batch
, index
,
1304 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1305 wa_ctx_emit(batch
, index
, MI_NOOP
);
1308 /* WaDisableCtxRestoreArbitration:skl,bxt */
1309 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1310 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1311 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1313 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1315 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1318 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1322 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1323 if (!ring
->wa_ctx
.obj
) {
1324 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1328 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1330 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1332 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1339 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1341 if (ring
->wa_ctx
.obj
) {
1342 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1343 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1344 ring
->wa_ctx
.obj
= NULL
;
1348 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1354 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1356 WARN_ON(ring
->id
!= RCS
);
1358 /* update this when WA for higher Gen are added */
1359 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1360 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1361 INTEL_INFO(ring
->dev
)->gen
);
1365 /* some WA perform writes to scratch page, ensure it is valid */
1366 if (ring
->scratch
.obj
== NULL
) {
1367 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1371 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1373 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1377 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1378 batch
= kmap_atomic(page
);
1381 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1382 ret
= gen8_init_indirectctx_bb(ring
,
1383 &wa_ctx
->indirect_ctx
,
1389 ret
= gen8_init_perctx_bb(ring
,
1395 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1396 ret
= gen9_init_indirectctx_bb(ring
,
1397 &wa_ctx
->indirect_ctx
,
1403 ret
= gen9_init_perctx_bb(ring
,
1412 kunmap_atomic(batch
);
1414 lrc_destroy_wa_ctx_obj(ring
);
1419 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1421 struct drm_device
*dev
= ring
->dev
;
1422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1424 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1425 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1427 if (ring
->status_page
.obj
) {
1428 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1429 (u32
)ring
->status_page
.gfx_addr
);
1430 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1433 I915_WRITE(RING_MODE_GEN7(ring
),
1434 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1435 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1436 POSTING_READ(RING_MODE_GEN7(ring
));
1437 ring
->next_context_status_buffer
= 0;
1438 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1440 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1445 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1447 struct drm_device
*dev
= ring
->dev
;
1448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 ret
= gen8_init_common_ring(ring
);
1455 /* We need to disable the AsyncFlip performance optimisations in order
1456 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1457 * programmed to '1' on all products.
1459 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1461 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1463 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1465 return init_workarounds_ring(ring
);
1468 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1472 ret
= gen8_init_common_ring(ring
);
1476 return init_workarounds_ring(ring
);
1479 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1481 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1482 struct intel_engine_cs
*ring
= req
->ring
;
1483 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1484 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1487 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1491 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1492 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1493 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1495 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1496 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1497 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1498 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1501 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1502 intel_logical_ring_advance(ringbuf
);
1507 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1508 u64 offset
, unsigned dispatch_flags
)
1510 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1511 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1514 /* Don't rely in hw updating PDPs, specially in lite-restore.
1515 * Ideally, we should set Force PD Restore in ctx descriptor,
1516 * but we can't. Force Restore would be a second option, but
1517 * it is unsafe in case of lite-restore (because the ctx is
1519 if (req
->ctx
->ppgtt
&&
1520 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1521 ret
= intel_logical_ring_emit_pdps(req
);
1525 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1528 ret
= intel_logical_ring_begin(req
, 4);
1532 /* FIXME(BDW): Address space and security selectors. */
1533 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1535 (dispatch_flags
& I915_DISPATCH_RS
?
1536 MI_BATCH_RESOURCE_STREAMER
: 0));
1537 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1538 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1539 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1540 intel_logical_ring_advance(ringbuf
);
1545 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1547 struct drm_device
*dev
= ring
->dev
;
1548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1549 unsigned long flags
;
1551 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1554 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1555 if (ring
->irq_refcount
++ == 0) {
1556 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1557 POSTING_READ(RING_IMR(ring
->mmio_base
));
1559 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1564 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1566 struct drm_device
*dev
= ring
->dev
;
1567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1568 unsigned long flags
;
1570 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1571 if (--ring
->irq_refcount
== 0) {
1572 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1573 POSTING_READ(RING_IMR(ring
->mmio_base
));
1575 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1578 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1579 u32 invalidate_domains
,
1582 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1583 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1584 struct drm_device
*dev
= ring
->dev
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1589 ret
= intel_logical_ring_begin(request
, 4);
1593 cmd
= MI_FLUSH_DW
+ 1;
1595 /* We always require a command barrier so that subsequent
1596 * commands, such as breadcrumb interrupts, are strictly ordered
1597 * wrt the contents of the write cache being flushed to memory
1598 * (and thus being coherent from the CPU).
1600 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1602 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1603 cmd
|= MI_INVALIDATE_TLB
;
1604 if (ring
== &dev_priv
->ring
[VCS
])
1605 cmd
|= MI_INVALIDATE_BSD
;
1608 intel_logical_ring_emit(ringbuf
, cmd
);
1609 intel_logical_ring_emit(ringbuf
,
1610 I915_GEM_HWS_SCRATCH_ADDR
|
1611 MI_FLUSH_DW_USE_GTT
);
1612 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1613 intel_logical_ring_emit(ringbuf
, 0); /* value */
1614 intel_logical_ring_advance(ringbuf
);
1619 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1620 u32 invalidate_domains
,
1623 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1624 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1625 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1630 flags
|= PIPE_CONTROL_CS_STALL
;
1632 if (flush_domains
) {
1633 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1634 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1637 if (invalidate_domains
) {
1638 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1639 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1640 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1641 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1642 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1643 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1644 flags
|= PIPE_CONTROL_QW_WRITE
;
1645 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1649 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1652 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1653 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1655 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1660 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1661 intel_logical_ring_emit(ringbuf
, 0);
1662 intel_logical_ring_emit(ringbuf
, 0);
1663 intel_logical_ring_emit(ringbuf
, 0);
1664 intel_logical_ring_emit(ringbuf
, 0);
1665 intel_logical_ring_emit(ringbuf
, 0);
1668 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1669 intel_logical_ring_emit(ringbuf
, flags
);
1670 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1671 intel_logical_ring_emit(ringbuf
, 0);
1672 intel_logical_ring_emit(ringbuf
, 0);
1673 intel_logical_ring_emit(ringbuf
, 0);
1674 intel_logical_ring_advance(ringbuf
);
1679 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1681 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1684 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1686 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1689 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1691 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1692 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1697 * Reserve space for 2 NOOPs at the end of each request to be
1698 * used as a workaround for not being allowed to do lite
1699 * restore with HEAD==TAIL (WaIdleLiteRestore).
1701 ret
= intel_logical_ring_begin(request
, 8);
1705 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1706 cmd
|= MI_GLOBAL_GTT
;
1708 intel_logical_ring_emit(ringbuf
, cmd
);
1709 intel_logical_ring_emit(ringbuf
,
1710 (ring
->status_page
.gfx_addr
+
1711 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1712 intel_logical_ring_emit(ringbuf
, 0);
1713 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1714 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1715 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1716 intel_logical_ring_advance_and_submit(request
);
1719 * Here we add two extra NOOPs as padding to avoid
1720 * lite restore of a context with HEAD==TAIL.
1722 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1723 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1724 intel_logical_ring_advance(ringbuf
);
1729 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1731 struct render_state so
;
1734 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1738 if (so
.rodata
== NULL
)
1741 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1742 I915_DISPATCH_SECURE
);
1746 ret
= req
->ring
->emit_bb_start(req
,
1747 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1748 I915_DISPATCH_SECURE
);
1752 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1755 i915_gem_render_state_fini(&so
);
1759 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1763 ret
= intel_logical_ring_workarounds_emit(req
);
1767 ret
= intel_rcs_context_init_mocs(req
);
1769 * Failing to program the MOCS is non-fatal.The system will not
1770 * run at peak performance. So generate an error and carry on.
1773 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1775 return intel_lr_context_render_state_init(req
);
1779 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1781 * @ring: Engine Command Streamer.
1784 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1786 struct drm_i915_private
*dev_priv
;
1788 if (!intel_ring_initialized(ring
))
1791 dev_priv
= ring
->dev
->dev_private
;
1793 intel_logical_ring_stop(ring
);
1794 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1797 ring
->cleanup(ring
);
1799 i915_cmd_parser_fini_ring(ring
);
1800 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1802 if (ring
->status_page
.obj
) {
1803 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1804 ring
->status_page
.obj
= NULL
;
1807 lrc_destroy_wa_ctx_obj(ring
);
1810 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1814 /* Intentionally left blank. */
1815 ring
->buffer
= NULL
;
1818 INIT_LIST_HEAD(&ring
->active_list
);
1819 INIT_LIST_HEAD(&ring
->request_list
);
1820 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1821 init_waitqueue_head(&ring
->irq_queue
);
1823 INIT_LIST_HEAD(&ring
->execlist_queue
);
1824 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1825 spin_lock_init(&ring
->execlist_lock
);
1827 ret
= i915_cmd_parser_init_ring(ring
);
1831 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1836 static int logical_render_ring_init(struct drm_device
*dev
)
1838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1839 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1842 ring
->name
= "render ring";
1844 ring
->mmio_base
= RENDER_RING_BASE
;
1845 ring
->irq_enable_mask
=
1846 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1847 ring
->irq_keep_mask
=
1848 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1849 if (HAS_L3_DPF(dev
))
1850 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1852 if (INTEL_INFO(dev
)->gen
>= 9)
1853 ring
->init_hw
= gen9_init_render_ring
;
1855 ring
->init_hw
= gen8_init_render_ring
;
1856 ring
->init_context
= gen8_init_rcs_context
;
1857 ring
->cleanup
= intel_fini_pipe_control
;
1858 ring
->get_seqno
= gen8_get_seqno
;
1859 ring
->set_seqno
= gen8_set_seqno
;
1860 ring
->emit_request
= gen8_emit_request
;
1861 ring
->emit_flush
= gen8_emit_flush_render
;
1862 ring
->irq_get
= gen8_logical_ring_get_irq
;
1863 ring
->irq_put
= gen8_logical_ring_put_irq
;
1864 ring
->emit_bb_start
= gen8_emit_bb_start
;
1868 ret
= intel_init_pipe_control(ring
);
1872 ret
= intel_init_workaround_bb(ring
);
1875 * We continue even if we fail to initialize WA batch
1876 * because we only expect rare glitches but nothing
1877 * critical to prevent us from using GPU
1879 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1883 ret
= logical_ring_init(dev
, ring
);
1885 lrc_destroy_wa_ctx_obj(ring
);
1891 static int logical_bsd_ring_init(struct drm_device
*dev
)
1893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1894 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1896 ring
->name
= "bsd ring";
1898 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1899 ring
->irq_enable_mask
=
1900 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1901 ring
->irq_keep_mask
=
1902 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1904 ring
->init_hw
= gen8_init_common_ring
;
1905 ring
->get_seqno
= gen8_get_seqno
;
1906 ring
->set_seqno
= gen8_set_seqno
;
1907 ring
->emit_request
= gen8_emit_request
;
1908 ring
->emit_flush
= gen8_emit_flush
;
1909 ring
->irq_get
= gen8_logical_ring_get_irq
;
1910 ring
->irq_put
= gen8_logical_ring_put_irq
;
1911 ring
->emit_bb_start
= gen8_emit_bb_start
;
1913 return logical_ring_init(dev
, ring
);
1916 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1919 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1921 ring
->name
= "bds2 ring";
1923 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1924 ring
->irq_enable_mask
=
1925 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1926 ring
->irq_keep_mask
=
1927 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1929 ring
->init_hw
= gen8_init_common_ring
;
1930 ring
->get_seqno
= gen8_get_seqno
;
1931 ring
->set_seqno
= gen8_set_seqno
;
1932 ring
->emit_request
= gen8_emit_request
;
1933 ring
->emit_flush
= gen8_emit_flush
;
1934 ring
->irq_get
= gen8_logical_ring_get_irq
;
1935 ring
->irq_put
= gen8_logical_ring_put_irq
;
1936 ring
->emit_bb_start
= gen8_emit_bb_start
;
1938 return logical_ring_init(dev
, ring
);
1941 static int logical_blt_ring_init(struct drm_device
*dev
)
1943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1944 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1946 ring
->name
= "blitter ring";
1948 ring
->mmio_base
= BLT_RING_BASE
;
1949 ring
->irq_enable_mask
=
1950 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1951 ring
->irq_keep_mask
=
1952 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1954 ring
->init_hw
= gen8_init_common_ring
;
1955 ring
->get_seqno
= gen8_get_seqno
;
1956 ring
->set_seqno
= gen8_set_seqno
;
1957 ring
->emit_request
= gen8_emit_request
;
1958 ring
->emit_flush
= gen8_emit_flush
;
1959 ring
->irq_get
= gen8_logical_ring_get_irq
;
1960 ring
->irq_put
= gen8_logical_ring_put_irq
;
1961 ring
->emit_bb_start
= gen8_emit_bb_start
;
1963 return logical_ring_init(dev
, ring
);
1966 static int logical_vebox_ring_init(struct drm_device
*dev
)
1968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1969 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1971 ring
->name
= "video enhancement ring";
1973 ring
->mmio_base
= VEBOX_RING_BASE
;
1974 ring
->irq_enable_mask
=
1975 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1976 ring
->irq_keep_mask
=
1977 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1979 ring
->init_hw
= gen8_init_common_ring
;
1980 ring
->get_seqno
= gen8_get_seqno
;
1981 ring
->set_seqno
= gen8_set_seqno
;
1982 ring
->emit_request
= gen8_emit_request
;
1983 ring
->emit_flush
= gen8_emit_flush
;
1984 ring
->irq_get
= gen8_logical_ring_get_irq
;
1985 ring
->irq_put
= gen8_logical_ring_put_irq
;
1986 ring
->emit_bb_start
= gen8_emit_bb_start
;
1988 return logical_ring_init(dev
, ring
);
1992 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1995 * This function inits the engines for an Execlists submission style (the equivalent in the
1996 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1997 * those engines that are present in the hardware.
1999 * Return: non-zero if the initialization failed.
2001 int intel_logical_rings_init(struct drm_device
*dev
)
2003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2006 ret
= logical_render_ring_init(dev
);
2011 ret
= logical_bsd_ring_init(dev
);
2013 goto cleanup_render_ring
;
2017 ret
= logical_blt_ring_init(dev
);
2019 goto cleanup_bsd_ring
;
2022 if (HAS_VEBOX(dev
)) {
2023 ret
= logical_vebox_ring_init(dev
);
2025 goto cleanup_blt_ring
;
2028 if (HAS_BSD2(dev
)) {
2029 ret
= logical_bsd2_ring_init(dev
);
2031 goto cleanup_vebox_ring
;
2034 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
2036 goto cleanup_bsd2_ring
;
2041 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
2043 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2045 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2047 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2048 cleanup_render_ring
:
2049 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2055 make_rpcs(struct drm_device
*dev
)
2060 * No explicit RPCS request is needed to ensure full
2061 * slice/subslice/EU enablement prior to Gen9.
2063 if (INTEL_INFO(dev
)->gen
< 9)
2067 * Starting in Gen9, render power gating can leave
2068 * slice/subslice/EU in a partially enabled state. We
2069 * must make an explicit request through RPCS for full
2072 if (INTEL_INFO(dev
)->has_slice_pg
) {
2073 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2074 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2075 GEN8_RPCS_S_CNT_SHIFT
;
2076 rpcs
|= GEN8_RPCS_ENABLE
;
2079 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2080 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2081 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2082 GEN8_RPCS_SS_CNT_SHIFT
;
2083 rpcs
|= GEN8_RPCS_ENABLE
;
2086 if (INTEL_INFO(dev
)->has_eu_pg
) {
2087 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2088 GEN8_RPCS_EU_MIN_SHIFT
;
2089 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2090 GEN8_RPCS_EU_MAX_SHIFT
;
2091 rpcs
|= GEN8_RPCS_ENABLE
;
2098 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2099 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2101 struct drm_device
*dev
= ring
->dev
;
2102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2103 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2105 uint32_t *reg_state
;
2109 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2111 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2113 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2117 ret
= i915_gem_object_get_pages(ctx_obj
);
2119 DRM_DEBUG_DRIVER("Could not get object pages\n");
2123 i915_gem_object_pin_pages(ctx_obj
);
2125 /* The second page of the context object contains some fields which must
2126 * be set up prior to the first execution. */
2127 page
= i915_gem_object_get_page(ctx_obj
, 1);
2128 reg_state
= kmap_atomic(page
);
2130 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2131 * commands followed by (reg, value) pairs. The values we are setting here are
2132 * only for the first context restore: on a subsequent save, the GPU will
2133 * recreate this batchbuffer with new values (including all the missing
2134 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2135 if (ring
->id
== RCS
)
2136 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
2138 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
2139 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
2140 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
2141 reg_state
[CTX_CONTEXT_CONTROL
+1] =
2142 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2143 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2144 CTX_CTRL_RS_CTX_ENABLE
);
2145 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
2146 reg_state
[CTX_RING_HEAD
+1] = 0;
2147 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
2148 reg_state
[CTX_RING_TAIL
+1] = 0;
2149 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
2150 /* Ring buffer start address is not known until the buffer is pinned.
2151 * It is written to the context image in execlists_update_context()
2153 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
2154 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
2155 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
2156 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
2157 reg_state
[CTX_BB_HEAD_U
+1] = 0;
2158 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2159 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2160 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2161 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2162 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2163 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2164 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2165 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2166 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2167 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2168 if (ring
->id
== RCS
) {
2169 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2170 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2171 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2172 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2173 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2174 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2175 if (ring
->wa_ctx
.obj
) {
2176 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2177 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2179 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2180 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2181 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2183 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2184 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2186 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2187 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2191 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2192 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2193 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2194 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2195 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2196 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2197 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2198 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2199 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2200 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2201 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2202 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2204 /* With dynamic page allocation, PDPs may not be allocated at this point,
2205 * Point the unallocated PDPs to the scratch page
2207 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2208 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2209 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2210 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2211 if (ring
->id
== RCS
) {
2212 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2213 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2214 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2217 kunmap_atomic(reg_state
);
2220 set_page_dirty(page
);
2221 i915_gem_object_unpin_pages(ctx_obj
);
2227 * intel_lr_context_free() - free the LRC specific bits of a context
2228 * @ctx: the LR context to free.
2230 * The real context freeing is done in i915_gem_context_free: this only
2231 * takes care of the bits that are LRC related: the per-engine backing
2232 * objects and the logical ringbuffer.
2234 void intel_lr_context_free(struct intel_context
*ctx
)
2238 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2239 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2242 struct intel_ringbuffer
*ringbuf
=
2243 ctx
->engine
[i
].ringbuf
;
2244 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2246 if (ctx
== ring
->default_context
) {
2247 intel_unpin_ringbuffer_obj(ringbuf
);
2248 i915_gem_object_ggtt_unpin(ctx_obj
);
2250 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2251 intel_destroy_ringbuffer_obj(ringbuf
);
2253 drm_gem_object_unreference(&ctx_obj
->base
);
2258 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2262 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2266 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2267 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2269 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2275 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2282 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2283 struct drm_i915_gem_object
*default_ctx_obj
)
2285 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2287 /* The status page is offset 0 from the default context object
2289 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
2290 ring
->status_page
.page_addr
=
2291 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
2292 ring
->status_page
.obj
= default_ctx_obj
;
2294 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2295 (u32
)ring
->status_page
.gfx_addr
);
2296 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2300 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2301 * @ctx: LR context to create.
2302 * @ring: engine to be used with the context.
2304 * This function can be called more than once, with different engines, if we plan
2305 * to use the context with them. The context backing objects and the ringbuffers
2306 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2307 * the creation is a deferred call: it's better to make sure first that we need to use
2308 * a given ring with the context.
2310 * Return: non-zero on error.
2312 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
2313 struct intel_engine_cs
*ring
)
2315 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
2316 struct drm_device
*dev
= ring
->dev
;
2317 struct drm_i915_gem_object
*ctx_obj
;
2318 uint32_t context_size
;
2319 struct intel_ringbuffer
*ringbuf
;
2322 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2323 WARN_ON(ctx
->engine
[ring
->id
].state
);
2325 context_size
= round_up(get_lr_context_size(ring
), 4096);
2327 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2329 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2333 if (is_global_default_ctx
) {
2334 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
2336 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2338 drm_gem_object_unreference(&ctx_obj
->base
);
2343 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2345 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2348 goto error_unpin_ctx
;
2351 ringbuf
->ring
= ring
;
2353 ringbuf
->size
= 32 * PAGE_SIZE
;
2354 ringbuf
->effective_size
= ringbuf
->size
;
2357 ringbuf
->last_retired_head
= -1;
2358 intel_ring_update_space(ringbuf
);
2360 if (ringbuf
->obj
== NULL
) {
2361 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2364 "Failed to allocate ringbuffer obj %s: %d\n",
2366 goto error_free_rbuf
;
2369 if (is_global_default_ctx
) {
2370 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2373 "Failed to pin and map ringbuffer %s: %d\n",
2375 goto error_destroy_rbuf
;
2381 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2383 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2387 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2388 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2390 if (ctx
== ring
->default_context
)
2391 lrc_setup_hardware_status_page(ring
, ctx_obj
);
2392 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
2393 if (ring
->init_context
) {
2394 struct drm_i915_gem_request
*req
;
2396 ret
= i915_gem_request_alloc(ring
, ctx
, &req
);
2400 ret
= ring
->init_context(req
);
2402 DRM_ERROR("ring init context: %d\n", ret
);
2403 i915_gem_request_cancel(req
);
2404 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2405 ctx
->engine
[ring
->id
].state
= NULL
;
2409 i915_add_request_no_flush(req
);
2412 ctx
->rcs_initialized
= true;
2418 if (is_global_default_ctx
)
2419 intel_unpin_ringbuffer_obj(ringbuf
);
2421 intel_destroy_ringbuffer_obj(ringbuf
);
2425 if (is_global_default_ctx
)
2426 i915_gem_object_ggtt_unpin(ctx_obj
);
2427 drm_gem_object_unreference(&ctx_obj
->base
);
2431 void intel_lr_context_reset(struct drm_device
*dev
,
2432 struct intel_context
*ctx
)
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct intel_engine_cs
*ring
;
2438 for_each_ring(ring
, dev_priv
, i
) {
2439 struct drm_i915_gem_object
*ctx_obj
=
2440 ctx
->engine
[ring
->id
].state
;
2441 struct intel_ringbuffer
*ringbuf
=
2442 ctx
->engine
[ring
->id
].ringbuf
;
2443 uint32_t *reg_state
;
2449 if (i915_gem_object_get_pages(ctx_obj
)) {
2450 WARN(1, "Failed get_pages for context obj\n");
2453 page
= i915_gem_object_get_page(ctx_obj
, 1);
2454 reg_state
= kmap_atomic(page
);
2456 reg_state
[CTX_RING_HEAD
+1] = 0;
2457 reg_state
[CTX_RING_TAIL
+1] = 0;
2459 kunmap_atomic(reg_state
);