2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- tail
;
58 return space
- I915_RING_FREE_SPACE
;
61 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
63 if (ringbuf
->last_retired_head
!= -1) {
64 ringbuf
->head
= ringbuf
->last_retired_head
;
65 ringbuf
->last_retired_head
= -1;
68 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
69 ringbuf
->tail
, ringbuf
->size
);
72 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
74 intel_ring_update_space(ringbuf
);
75 return ringbuf
->space
;
78 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
80 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
81 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
84 static void __intel_ring_advance(struct intel_engine_cs
*ring
)
86 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
87 ringbuf
->tail
&= ringbuf
->size
- 1;
88 if (intel_ring_stopped(ring
))
90 ring
->write_tail(ring
, ringbuf
->tail
);
94 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
95 u32 invalidate_domains
,
98 struct intel_engine_cs
*ring
= req
->ring
;
103 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
104 cmd
|= MI_NO_WRITE_FLUSH
;
106 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
107 cmd
|= MI_READ_FLUSH
;
109 ret
= intel_ring_begin(req
, 2);
113 intel_ring_emit(ring
, cmd
);
114 intel_ring_emit(ring
, MI_NOOP
);
115 intel_ring_advance(ring
);
121 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
122 u32 invalidate_domains
,
125 struct intel_engine_cs
*ring
= req
->ring
;
126 struct drm_device
*dev
= ring
->dev
;
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
142 * I915_GEM_DOMAIN_COMMAND may not exist?
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
158 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
159 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
160 cmd
&= ~MI_NO_WRITE_FLUSH
;
161 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
164 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
165 (IS_G4X(dev
) || IS_GEN5(dev
)))
166 cmd
|= MI_INVALIDATE_ISP
;
168 ret
= intel_ring_begin(req
, 2);
172 intel_ring_emit(ring
, cmd
);
173 intel_ring_emit(ring
, MI_NOOP
);
174 intel_ring_advance(ring
);
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
192 * And the workaround for these two requires this workaround first:
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
219 struct intel_engine_cs
*ring
= req
->ring
;
220 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
223 ret
= intel_ring_begin(req
, 6);
227 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
229 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
230 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
231 intel_ring_emit(ring
, 0); /* low dword */
232 intel_ring_emit(ring
, 0); /* high dword */
233 intel_ring_emit(ring
, MI_NOOP
);
234 intel_ring_advance(ring
);
236 ret
= intel_ring_begin(req
, 6);
240 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
242 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
243 intel_ring_emit(ring
, 0);
244 intel_ring_emit(ring
, 0);
245 intel_ring_emit(ring
, MI_NOOP
);
246 intel_ring_advance(ring
);
252 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
253 u32 invalidate_domains
, u32 flush_domains
)
255 struct intel_engine_cs
*ring
= req
->ring
;
257 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret
= intel_emit_post_sync_nonzero_flush(req
);
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
270 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
271 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
276 flags
|= PIPE_CONTROL_CS_STALL
;
278 if (invalidate_domains
) {
279 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
280 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
281 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
282 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
283 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
284 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
286 * TLB invalidate requires a post-sync write.
288 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
291 ret
= intel_ring_begin(req
, 4);
295 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring
, flags
);
297 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
298 intel_ring_emit(ring
, 0);
299 intel_ring_advance(ring
);
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
307 struct intel_engine_cs
*ring
= req
->ring
;
310 ret
= intel_ring_begin(req
, 4);
314 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
316 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
317 intel_ring_emit(ring
, 0);
318 intel_ring_emit(ring
, 0);
319 intel_ring_advance(ring
);
325 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
326 u32 invalidate_domains
, u32 flush_domains
)
328 struct intel_engine_cs
*ring
= req
->ring
;
330 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
341 flags
|= PIPE_CONTROL_CS_STALL
;
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
348 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
349 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
351 if (invalidate_domains
) {
352 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
353 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
354 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
355 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
356 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
357 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
358 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
360 * TLB invalidate requires a post-sync write.
362 flags
|= PIPE_CONTROL_QW_WRITE
;
363 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
365 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req
);
373 ret
= intel_ring_begin(req
, 4);
377 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring
, flags
);
379 intel_ring_emit(ring
, scratch_addr
);
380 intel_ring_emit(ring
, 0);
381 intel_ring_advance(ring
);
387 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
388 u32 flags
, u32 scratch_addr
)
390 struct intel_engine_cs
*ring
= req
->ring
;
393 ret
= intel_ring_begin(req
, 6);
397 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring
, flags
);
399 intel_ring_emit(ring
, scratch_addr
);
400 intel_ring_emit(ring
, 0);
401 intel_ring_emit(ring
, 0);
402 intel_ring_emit(ring
, 0);
403 intel_ring_advance(ring
);
409 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
410 u32 invalidate_domains
, u32 flush_domains
)
413 u32 scratch_addr
= req
->ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
416 flags
|= PIPE_CONTROL_CS_STALL
;
419 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
420 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
422 if (invalidate_domains
) {
423 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
424 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
425 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
426 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
427 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
428 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
429 flags
|= PIPE_CONTROL_QW_WRITE
;
430 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret
= gen8_emit_pipe_control(req
,
434 PIPE_CONTROL_CS_STALL
|
435 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
441 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
444 static void ring_write_tail(struct intel_engine_cs
*ring
,
447 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
448 I915_WRITE_TAIL(ring
, value
);
451 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
453 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
456 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
457 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
458 RING_ACTHD_UDW(ring
->mmio_base
));
459 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
460 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
462 acthd
= I915_READ(ACTHD
);
467 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
469 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 addr
= dev_priv
->status_page_dmah
->busaddr
;
473 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
474 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
475 I915_WRITE(HWS_PGA
, addr
);
478 static void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
480 struct drm_device
*dev
= ring
->dev
;
481 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
490 mmio
= RENDER_HWS_PGA_GEN7
;
493 mmio
= BLT_HWS_PGA_GEN7
;
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
501 mmio
= BSD_HWS_PGA_GEN7
;
504 mmio
= VEBOX_HWS_PGA_GEN7
;
507 } else if (IS_GEN6(ring
->dev
)) {
508 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
510 /* XXX: gen8 returns to sanity */
511 mmio
= RING_HWS_PGA(ring
->mmio_base
);
514 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
518 * Flush the TLB for this page
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
524 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
525 i915_reg_t reg
= RING_INSTPM(ring
->mmio_base
);
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
533 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
540 static bool stop_ring(struct intel_engine_cs
*ring
)
542 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
544 if (!IS_GEN2(ring
->dev
)) {
545 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
546 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
552 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
557 I915_WRITE_CTL(ring
, 0);
558 I915_WRITE_HEAD(ring
, 0);
559 ring
->write_tail(ring
, 0);
561 if (!IS_GEN2(ring
->dev
)) {
562 (void)I915_READ_CTL(ring
);
563 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
566 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
569 static int init_ring_common(struct intel_engine_cs
*ring
)
571 struct drm_device
*dev
= ring
->dev
;
572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
573 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
574 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
577 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
579 if (!stop_ring(ring
)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
585 I915_READ_HEAD(ring
),
586 I915_READ_TAIL(ring
),
587 I915_READ_START(ring
));
589 if (!stop_ring(ring
)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
594 I915_READ_HEAD(ring
),
595 I915_READ_TAIL(ring
),
596 I915_READ_START(ring
));
602 if (I915_NEED_GFX_HWS(dev
))
603 intel_ring_setup_status_page(ring
);
605 ring_setup_phys_status_page(ring
);
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring
);
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring
))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring
->name
, I915_READ_HEAD(ring
));
620 I915_WRITE_HEAD(ring
, 0);
621 (void)I915_READ_HEAD(ring
);
624 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
629 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
630 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
634 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
635 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
636 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
641 ringbuf
->last_retired_head
= -1;
642 ringbuf
->head
= I915_READ_HEAD(ring
);
643 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
644 intel_ring_update_space(ringbuf
);
646 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
649 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
655 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
657 struct drm_device
*dev
= ring
->dev
;
659 if (ring
->scratch
.obj
== NULL
)
662 if (INTEL_INFO(dev
)->gen
>= 5) {
663 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
664 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
667 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
668 ring
->scratch
.obj
= NULL
;
672 intel_init_pipe_control(struct intel_engine_cs
*ring
)
676 WARN_ON(ring
->scratch
.obj
);
678 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
679 if (ring
->scratch
.obj
== NULL
) {
680 DRM_ERROR("Failed to allocate seqno page\n");
685 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
689 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
693 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
694 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
695 if (ring
->scratch
.cpu_page
== NULL
) {
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring
->name
, ring
->scratch
.gtt_offset
);
705 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
707 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
715 struct intel_engine_cs
*ring
= req
->ring
;
716 struct drm_device
*dev
= ring
->dev
;
717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
718 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
723 ring
->gpu_caches_dirty
= true;
724 ret
= intel_ring_flush_all_caches(req
);
728 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
732 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
733 for (i
= 0; i
< w
->count
; i
++) {
734 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
735 intel_ring_emit(ring
, w
->reg
[i
].value
);
737 intel_ring_emit(ring
, MI_NOOP
);
739 intel_ring_advance(ring
);
741 ring
->gpu_caches_dirty
= true;
742 ret
= intel_ring_flush_all_caches(req
);
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
755 ret
= intel_ring_workarounds_emit(req
);
759 ret
= i915_gem_render_state_init(req
);
761 DRM_ERROR("init render state: %d\n", ret
);
766 static int wa_add(struct drm_i915_private
*dev_priv
,
768 const u32 mask
, const u32 val
)
770 const u32 idx
= dev_priv
->workarounds
.count
;
772 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
775 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
776 dev_priv
->workarounds
.reg
[idx
].value
= val
;
777 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
779 dev_priv
->workarounds
.count
++;
784 #define WA_REG(addr, mask, val) do { \
785 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
790 #define WA_SET_BIT_MASKED(addr, mask) \
791 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
793 #define WA_CLR_BIT_MASKED(addr, mask) \
794 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
796 #define WA_SET_FIELD_MASKED(addr, mask, value) \
797 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
799 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
800 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
802 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
804 static int gen8_init_workarounds(struct intel_engine_cs
*ring
)
806 struct drm_device
*dev
= ring
->dev
;
807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
809 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
811 /* WaDisableAsyncFlipPerfMode:bdw,chv */
812 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
814 /* WaDisablePartialInstShootdown:bdw,chv */
815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
818 /* Use Force Non-Coherent whenever executing a 3D context. This is a
819 * workaround for for a possible hang in the unlikely event a TLB
820 * invalidation occurs during a PSD flush.
822 /* WaForceEnableNonCoherent:bdw,chv */
823 /* WaHdcDisableFetchWhenMasked:bdw,chv */
824 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
825 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
826 HDC_FORCE_NON_COHERENT
);
828 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
829 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
830 * polygons in the same 8x4 pixel/sample area to be processed without
831 * stalling waiting for the earlier ones to write to Hierarchical Z
834 * This optimization is off by default for BDW and CHV; turn it on.
836 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
838 /* Wa4x4STCOptimizationDisable:bdw,chv */
839 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
842 * BSpec recommends 8x4 when MSAA is used,
843 * however in practice 16x4 seems fastest.
845 * Note that PS/WM thread counts depend on the WIZ hashing
846 * disable bit, which we don't touch here, but it's good
847 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
849 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
850 GEN6_WIZ_HASHING_MASK
,
851 GEN6_WIZ_HASHING_16x4
);
856 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
859 struct drm_device
*dev
= ring
->dev
;
860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
862 ret
= gen8_init_workarounds(ring
);
866 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
867 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
869 /* WaDisableDopClockGating:bdw */
870 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
871 DOP_CLOCK_GATING_DISABLE
);
873 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
874 GEN8_SAMPLER_POWER_BYPASS_DIS
);
876 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
877 /* WaForceContextSaveRestoreNonCoherent:bdw */
878 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
879 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
880 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
885 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
888 struct drm_device
*dev
= ring
->dev
;
889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
891 ret
= gen8_init_workarounds(ring
);
895 /* WaDisableThreadStallDopClockGating:chv */
896 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
898 /* Improve HiZ throughput on CHV. */
899 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
904 static int gen9_init_workarounds(struct intel_engine_cs
*ring
)
906 struct drm_device
*dev
= ring
->dev
;
907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
910 /* WaEnableLbsSlaRetryTimerDecrement:skl */
911 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
912 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
914 /* WaDisableKillLogic:bxt,skl */
915 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
918 /* WaDisablePartialInstShootdown:skl,bxt */
919 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
920 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
922 /* Syncing dependencies between camera and graphics:skl,bxt */
923 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
924 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
926 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
927 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
928 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
929 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
930 GEN9_DG_MIRROR_FIX_ENABLE
);
932 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
933 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
934 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
935 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
936 GEN9_RHWO_OPTIMIZATION_DISABLE
);
938 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
939 * but we do that in per ctx batchbuffer as there is an issue
940 * with this register not getting restored on ctx restore
944 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
945 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
) || IS_BROXTON(dev
))
946 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
947 GEN9_ENABLE_YV12_BUGFIX
);
949 /* Wa4x4STCOptimizationDisable:skl,bxt */
950 /* WaDisablePartialResolveInVc:skl,bxt */
951 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
952 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
954 /* WaCcsTlbPrefetchDisable:skl,bxt */
955 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
956 GEN9_CCS_TLB_PREFETCH_ENABLE
);
958 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
959 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_C0
) ||
960 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
961 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
962 PIXEL_MASK_CAMMING_DISABLE
);
964 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
965 tmp
= HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
;
966 if (IS_SKL_REVID(dev
, SKL_REVID_F0
, SKL_REVID_F0
) ||
967 IS_BXT_REVID(dev
, BXT_REVID_B0
, REVID_FOREVER
))
968 tmp
|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
;
969 WA_SET_BIT_MASKED(HDC_CHICKEN0
, tmp
);
971 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
972 if (IS_SKYLAKE(dev
) || IS_BXT_REVID(dev
, 0, BXT_REVID_B0
))
973 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
974 GEN8_SAMPLER_POWER_BYPASS_DIS
);
976 /* WaDisableSTUnitPowerOptimization:skl,bxt */
977 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
982 static int skl_tune_iz_hashing(struct intel_engine_cs
*ring
)
984 struct drm_device
*dev
= ring
->dev
;
985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
986 u8 vals
[3] = { 0, 0, 0 };
989 for (i
= 0; i
< 3; i
++) {
993 * Only consider slices where one, and only one, subslice has 7
996 if (hweight8(dev_priv
->info
.subslice_7eu
[i
]) != 1)
1000 * subslice_7eu[i] != 0 (because of the check above) and
1001 * ss_max == 4 (maximum number of subslices possible per slice)
1005 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1009 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1012 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1013 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1014 GEN9_IZ_HASHING_MASK(2) |
1015 GEN9_IZ_HASHING_MASK(1) |
1016 GEN9_IZ_HASHING_MASK(0),
1017 GEN9_IZ_HASHING(2, vals
[2]) |
1018 GEN9_IZ_HASHING(1, vals
[1]) |
1019 GEN9_IZ_HASHING(0, vals
[0]));
1024 static int skl_init_workarounds(struct intel_engine_cs
*ring
)
1027 struct drm_device
*dev
= ring
->dev
;
1028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1030 ret
= gen9_init_workarounds(ring
);
1034 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
)) {
1035 /* WaDisableHDCInvalidation:skl */
1036 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
1037 BDW_DISABLE_HDC_INVALIDATION
);
1039 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1040 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1041 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1044 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1045 * involving this register should also be added to WA batch as required.
1047 if (IS_SKL_REVID(dev
, 0, SKL_REVID_E0
))
1048 /* WaDisableLSQCROPERFforOCL:skl */
1049 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1050 GEN8_LQSC_RO_PERF_DIS
);
1052 /* WaEnableGapsTsvCreditFix:skl */
1053 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
)) {
1054 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1055 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1058 /* WaDisablePowerCompilerClockGating:skl */
1059 if (IS_SKL_REVID(dev
, SKL_REVID_B0
, SKL_REVID_B0
))
1060 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1061 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1063 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
)) {
1065 *Use Force Non-Coherent whenever executing a 3D context. This
1066 * is a workaround for a possible hang in the unlikely event
1067 * a TLB invalidation occurs during a PSD flush.
1069 /* WaForceEnableNonCoherent:skl */
1070 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1071 HDC_FORCE_NON_COHERENT
);
1074 /* WaBarrierPerformanceFixDisable:skl */
1075 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_D0
))
1076 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1077 HDC_FENCE_DEST_SLM_DISABLE
|
1078 HDC_BARRIER_PERFORMANCE_DISABLE
);
1080 /* WaDisableSbeCacheDispatchPortSharing:skl */
1081 if (IS_SKL_REVID(dev
, 0, SKL_REVID_F0
))
1083 GEN7_HALF_SLICE_CHICKEN1
,
1084 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1086 return skl_tune_iz_hashing(ring
);
1089 static int bxt_init_workarounds(struct intel_engine_cs
*ring
)
1092 struct drm_device
*dev
= ring
->dev
;
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1095 ret
= gen9_init_workarounds(ring
);
1099 /* WaStoreMultiplePTEenable:bxt */
1100 /* This is a requirement according to Hardware specification */
1101 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1102 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1104 /* WaSetClckGatingDisableMedia:bxt */
1105 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1106 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1107 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1110 /* WaDisableThreadStallDopClockGating:bxt */
1111 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1112 STALL_DOP_GATING_DISABLE
);
1114 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1115 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1117 GEN7_HALF_SLICE_CHICKEN1
,
1118 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1124 int init_workarounds_ring(struct intel_engine_cs
*ring
)
1126 struct drm_device
*dev
= ring
->dev
;
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1129 WARN_ON(ring
->id
!= RCS
);
1131 dev_priv
->workarounds
.count
= 0;
1133 if (IS_BROADWELL(dev
))
1134 return bdw_init_workarounds(ring
);
1136 if (IS_CHERRYVIEW(dev
))
1137 return chv_init_workarounds(ring
);
1139 if (IS_SKYLAKE(dev
))
1140 return skl_init_workarounds(ring
);
1142 if (IS_BROXTON(dev
))
1143 return bxt_init_workarounds(ring
);
1148 static int init_render_ring(struct intel_engine_cs
*ring
)
1150 struct drm_device
*dev
= ring
->dev
;
1151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1152 int ret
= init_ring_common(ring
);
1156 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1157 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1158 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1160 /* We need to disable the AsyncFlip performance optimisations in order
1161 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1162 * programmed to '1' on all products.
1164 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1166 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1167 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1169 /* Required for the hardware to program scanline values for waiting */
1170 /* WaEnableFlushTlbInvalidationMode:snb */
1171 if (INTEL_INFO(dev
)->gen
== 6)
1172 I915_WRITE(GFX_MODE
,
1173 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1175 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1177 I915_WRITE(GFX_MODE_GEN7
,
1178 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1179 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1182 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1183 * "If this bit is set, STCunit will have LRA as replacement
1184 * policy. [...] This bit must be reset. LRA replacement
1185 * policy is not supported."
1187 I915_WRITE(CACHE_MODE_0
,
1188 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1191 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1192 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1194 if (HAS_L3_DPF(dev
))
1195 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1197 return init_workarounds_ring(ring
);
1200 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
1202 struct drm_device
*dev
= ring
->dev
;
1203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1205 if (dev_priv
->semaphore_obj
) {
1206 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1207 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1208 dev_priv
->semaphore_obj
= NULL
;
1211 intel_fini_pipe_control(ring
);
1214 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1215 unsigned int num_dwords
)
1217 #define MBOX_UPDATE_DWORDS 8
1218 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1219 struct drm_device
*dev
= signaller
->dev
;
1220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 struct intel_engine_cs
*waiter
;
1222 int i
, ret
, num_rings
;
1224 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1225 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1226 #undef MBOX_UPDATE_DWORDS
1228 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1232 for_each_ring(waiter
, dev_priv
, i
) {
1234 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1235 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1238 seqno
= i915_gem_request_get_seqno(signaller_req
);
1239 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1240 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1241 PIPE_CONTROL_QW_WRITE
|
1242 PIPE_CONTROL_FLUSH_ENABLE
);
1243 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1244 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1245 intel_ring_emit(signaller
, seqno
);
1246 intel_ring_emit(signaller
, 0);
1247 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1248 MI_SEMAPHORE_TARGET(waiter
->id
));
1249 intel_ring_emit(signaller
, 0);
1255 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1256 unsigned int num_dwords
)
1258 #define MBOX_UPDATE_DWORDS 6
1259 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1260 struct drm_device
*dev
= signaller
->dev
;
1261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1262 struct intel_engine_cs
*waiter
;
1263 int i
, ret
, num_rings
;
1265 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1266 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1267 #undef MBOX_UPDATE_DWORDS
1269 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1273 for_each_ring(waiter
, dev_priv
, i
) {
1275 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1276 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1279 seqno
= i915_gem_request_get_seqno(signaller_req
);
1280 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1281 MI_FLUSH_DW_OP_STOREDW
);
1282 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1283 MI_FLUSH_DW_USE_GTT
);
1284 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1285 intel_ring_emit(signaller
, seqno
);
1286 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1287 MI_SEMAPHORE_TARGET(waiter
->id
));
1288 intel_ring_emit(signaller
, 0);
1294 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1295 unsigned int num_dwords
)
1297 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1298 struct drm_device
*dev
= signaller
->dev
;
1299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1300 struct intel_engine_cs
*useless
;
1301 int i
, ret
, num_rings
;
1303 #define MBOX_UPDATE_DWORDS 3
1304 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1305 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1306 #undef MBOX_UPDATE_DWORDS
1308 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1312 for_each_ring(useless
, dev_priv
, i
) {
1313 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1315 if (i915_mmio_reg_valid(mbox_reg
)) {
1316 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1318 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1319 intel_ring_emit_reg(signaller
, mbox_reg
);
1320 intel_ring_emit(signaller
, seqno
);
1324 /* If num_dwords was rounded, make sure the tail pointer is correct */
1325 if (num_rings
% 2 == 0)
1326 intel_ring_emit(signaller
, MI_NOOP
);
1332 * gen6_add_request - Update the semaphore mailbox registers
1334 * @request - request to write to the ring
1336 * Update the mailbox registers in the *other* rings with the current seqno.
1337 * This acts like a signal in the canonical semaphore.
1340 gen6_add_request(struct drm_i915_gem_request
*req
)
1342 struct intel_engine_cs
*ring
= req
->ring
;
1345 if (ring
->semaphore
.signal
)
1346 ret
= ring
->semaphore
.signal(req
, 4);
1348 ret
= intel_ring_begin(req
, 4);
1353 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1354 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1355 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1356 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1357 __intel_ring_advance(ring
);
1362 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1366 return dev_priv
->last_seqno
< seqno
;
1370 * intel_ring_sync - sync the waiter to the signaller on seqno
1372 * @waiter - ring that is waiting
1373 * @signaller - ring which has, or will signal
1374 * @seqno - seqno which the waiter will block on
1378 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1379 struct intel_engine_cs
*signaller
,
1382 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1383 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1386 ret
= intel_ring_begin(waiter_req
, 4);
1390 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1391 MI_SEMAPHORE_GLOBAL_GTT
|
1393 MI_SEMAPHORE_SAD_GTE_SDD
);
1394 intel_ring_emit(waiter
, seqno
);
1395 intel_ring_emit(waiter
,
1396 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1397 intel_ring_emit(waiter
,
1398 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1399 intel_ring_advance(waiter
);
1404 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1405 struct intel_engine_cs
*signaller
,
1408 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1409 u32 dw1
= MI_SEMAPHORE_MBOX
|
1410 MI_SEMAPHORE_COMPARE
|
1411 MI_SEMAPHORE_REGISTER
;
1412 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1415 /* Throughout all of the GEM code, seqno passed implies our current
1416 * seqno is >= the last seqno executed. However for hardware the
1417 * comparison is strictly greater than.
1421 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1423 ret
= intel_ring_begin(waiter_req
, 4);
1427 /* If seqno wrap happened, omit the wait with no-ops */
1428 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1429 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1430 intel_ring_emit(waiter
, seqno
);
1431 intel_ring_emit(waiter
, 0);
1432 intel_ring_emit(waiter
, MI_NOOP
);
1434 intel_ring_emit(waiter
, MI_NOOP
);
1435 intel_ring_emit(waiter
, MI_NOOP
);
1436 intel_ring_emit(waiter
, MI_NOOP
);
1437 intel_ring_emit(waiter
, MI_NOOP
);
1439 intel_ring_advance(waiter
);
1444 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1446 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1447 PIPE_CONTROL_DEPTH_STALL); \
1448 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1449 intel_ring_emit(ring__, 0); \
1450 intel_ring_emit(ring__, 0); \
1454 pc_render_add_request(struct drm_i915_gem_request
*req
)
1456 struct intel_engine_cs
*ring
= req
->ring
;
1457 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1460 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1461 * incoherent with writes to memory, i.e. completely fubar,
1462 * so we need to use PIPE_NOTIFY instead.
1464 * However, we also need to workaround the qword write
1465 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1466 * memory before requesting an interrupt.
1468 ret
= intel_ring_begin(req
, 32);
1472 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1473 PIPE_CONTROL_WRITE_FLUSH
|
1474 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1475 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1476 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1477 intel_ring_emit(ring
, 0);
1478 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1479 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1480 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1481 scratch_addr
+= 2 * CACHELINE_BYTES
;
1482 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1483 scratch_addr
+= 2 * CACHELINE_BYTES
;
1484 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1485 scratch_addr
+= 2 * CACHELINE_BYTES
;
1486 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1487 scratch_addr
+= 2 * CACHELINE_BYTES
;
1488 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1490 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1491 PIPE_CONTROL_WRITE_FLUSH
|
1492 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1493 PIPE_CONTROL_NOTIFY
);
1494 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1495 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1496 intel_ring_emit(ring
, 0);
1497 __intel_ring_advance(ring
);
1503 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1505 /* Workaround to force correct ordering between irq and seqno writes on
1506 * ivb (and maybe also on snb) by reading from a CS register (like
1507 * ACTHD) before reading the status page. */
1508 if (!lazy_coherency
) {
1509 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1510 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1513 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1517 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1519 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1523 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1525 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1529 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1531 return ring
->scratch
.cpu_page
[0];
1535 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1537 ring
->scratch
.cpu_page
[0] = seqno
;
1541 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1543 struct drm_device
*dev
= ring
->dev
;
1544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1545 unsigned long flags
;
1547 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1550 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1551 if (ring
->irq_refcount
++ == 0)
1552 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1553 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1559 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1561 struct drm_device
*dev
= ring
->dev
;
1562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1563 unsigned long flags
;
1565 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1566 if (--ring
->irq_refcount
== 0)
1567 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1568 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1572 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1574 struct drm_device
*dev
= ring
->dev
;
1575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1576 unsigned long flags
;
1578 if (!intel_irqs_enabled(dev_priv
))
1581 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1582 if (ring
->irq_refcount
++ == 0) {
1583 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1584 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1587 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1593 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1595 struct drm_device
*dev
= ring
->dev
;
1596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1597 unsigned long flags
;
1599 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1600 if (--ring
->irq_refcount
== 0) {
1601 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1602 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1605 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1609 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1611 struct drm_device
*dev
= ring
->dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 unsigned long flags
;
1615 if (!intel_irqs_enabled(dev_priv
))
1618 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1619 if (ring
->irq_refcount
++ == 0) {
1620 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1621 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1622 POSTING_READ16(IMR
);
1624 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1630 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1632 struct drm_device
*dev
= ring
->dev
;
1633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1634 unsigned long flags
;
1636 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1637 if (--ring
->irq_refcount
== 0) {
1638 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1639 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1640 POSTING_READ16(IMR
);
1642 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1646 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1647 u32 invalidate_domains
,
1650 struct intel_engine_cs
*ring
= req
->ring
;
1653 ret
= intel_ring_begin(req
, 2);
1657 intel_ring_emit(ring
, MI_FLUSH
);
1658 intel_ring_emit(ring
, MI_NOOP
);
1659 intel_ring_advance(ring
);
1664 i9xx_add_request(struct drm_i915_gem_request
*req
)
1666 struct intel_engine_cs
*ring
= req
->ring
;
1669 ret
= intel_ring_begin(req
, 4);
1673 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1674 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1675 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1676 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1677 __intel_ring_advance(ring
);
1683 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1685 struct drm_device
*dev
= ring
->dev
;
1686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1687 unsigned long flags
;
1689 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1692 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1693 if (ring
->irq_refcount
++ == 0) {
1694 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1695 I915_WRITE_IMR(ring
,
1696 ~(ring
->irq_enable_mask
|
1697 GT_PARITY_ERROR(dev
)));
1699 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1700 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1702 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1708 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1710 struct drm_device
*dev
= ring
->dev
;
1711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1712 unsigned long flags
;
1714 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1715 if (--ring
->irq_refcount
== 0) {
1716 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1717 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1719 I915_WRITE_IMR(ring
, ~0);
1720 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1722 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1726 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1728 struct drm_device
*dev
= ring
->dev
;
1729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1730 unsigned long flags
;
1732 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1735 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1736 if (ring
->irq_refcount
++ == 0) {
1737 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1738 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1740 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1746 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1748 struct drm_device
*dev
= ring
->dev
;
1749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1750 unsigned long flags
;
1752 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1753 if (--ring
->irq_refcount
== 0) {
1754 I915_WRITE_IMR(ring
, ~0);
1755 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1757 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1761 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1763 struct drm_device
*dev
= ring
->dev
;
1764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1765 unsigned long flags
;
1767 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1770 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1771 if (ring
->irq_refcount
++ == 0) {
1772 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1773 I915_WRITE_IMR(ring
,
1774 ~(ring
->irq_enable_mask
|
1775 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1777 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1779 POSTING_READ(RING_IMR(ring
->mmio_base
));
1781 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1787 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1789 struct drm_device
*dev
= ring
->dev
;
1790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1791 unsigned long flags
;
1793 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1794 if (--ring
->irq_refcount
== 0) {
1795 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1796 I915_WRITE_IMR(ring
,
1797 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1799 I915_WRITE_IMR(ring
, ~0);
1801 POSTING_READ(RING_IMR(ring
->mmio_base
));
1803 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1807 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1808 u64 offset
, u32 length
,
1809 unsigned dispatch_flags
)
1811 struct intel_engine_cs
*ring
= req
->ring
;
1814 ret
= intel_ring_begin(req
, 2);
1818 intel_ring_emit(ring
,
1819 MI_BATCH_BUFFER_START
|
1821 (dispatch_flags
& I915_DISPATCH_SECURE
?
1822 0 : MI_BATCH_NON_SECURE_I965
));
1823 intel_ring_emit(ring
, offset
);
1824 intel_ring_advance(ring
);
1829 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1830 #define I830_BATCH_LIMIT (256*1024)
1831 #define I830_TLB_ENTRIES (2)
1832 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1834 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1835 u64 offset
, u32 len
,
1836 unsigned dispatch_flags
)
1838 struct intel_engine_cs
*ring
= req
->ring
;
1839 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1842 ret
= intel_ring_begin(req
, 6);
1846 /* Evict the invalid PTE TLBs */
1847 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1848 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1849 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1850 intel_ring_emit(ring
, cs_offset
);
1851 intel_ring_emit(ring
, 0xdeadbeef);
1852 intel_ring_emit(ring
, MI_NOOP
);
1853 intel_ring_advance(ring
);
1855 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1856 if (len
> I830_BATCH_LIMIT
)
1859 ret
= intel_ring_begin(req
, 6 + 2);
1863 /* Blit the batch (which has now all relocs applied) to the
1864 * stable batch scratch bo area (so that the CS never
1865 * stumbles over its tlb invalidation bug) ...
1867 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1868 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1869 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1870 intel_ring_emit(ring
, cs_offset
);
1871 intel_ring_emit(ring
, 4096);
1872 intel_ring_emit(ring
, offset
);
1874 intel_ring_emit(ring
, MI_FLUSH
);
1875 intel_ring_emit(ring
, MI_NOOP
);
1876 intel_ring_advance(ring
);
1878 /* ... and execute it. */
1882 ret
= intel_ring_begin(req
, 4);
1886 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1887 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1888 0 : MI_BATCH_NON_SECURE
));
1889 intel_ring_emit(ring
, offset
+ len
- 8);
1890 intel_ring_emit(ring
, MI_NOOP
);
1891 intel_ring_advance(ring
);
1897 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1898 u64 offset
, u32 len
,
1899 unsigned dispatch_flags
)
1901 struct intel_engine_cs
*ring
= req
->ring
;
1904 ret
= intel_ring_begin(req
, 2);
1908 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1909 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1910 0 : MI_BATCH_NON_SECURE
));
1911 intel_ring_advance(ring
);
1916 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1918 struct drm_i915_gem_object
*obj
;
1920 obj
= ring
->status_page
.obj
;
1924 kunmap(sg_page(obj
->pages
->sgl
));
1925 i915_gem_object_ggtt_unpin(obj
);
1926 drm_gem_object_unreference(&obj
->base
);
1927 ring
->status_page
.obj
= NULL
;
1930 static int init_status_page(struct intel_engine_cs
*ring
)
1932 struct drm_i915_gem_object
*obj
;
1934 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1938 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1940 DRM_ERROR("Failed to allocate status page\n");
1944 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1949 if (!HAS_LLC(ring
->dev
))
1950 /* On g33, we cannot place HWS above 256MiB, so
1951 * restrict its pinning to the low mappable arena.
1952 * Though this restriction is not documented for
1953 * gen4, gen5, or byt, they also behave similarly
1954 * and hang if the HWS is placed at the top of the
1955 * GTT. To generalise, it appears that all !llc
1956 * platforms have issues with us placing the HWS
1957 * above the mappable region (even though we never
1960 flags
|= PIN_MAPPABLE
;
1961 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1964 drm_gem_object_unreference(&obj
->base
);
1968 ring
->status_page
.obj
= obj
;
1971 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1972 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1973 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1975 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1976 ring
->name
, ring
->status_page
.gfx_addr
);
1981 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1983 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1985 if (!dev_priv
->status_page_dmah
) {
1986 dev_priv
->status_page_dmah
=
1987 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1988 if (!dev_priv
->status_page_dmah
)
1992 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1993 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1998 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2000 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
2001 vunmap(ringbuf
->virtual_start
);
2003 iounmap(ringbuf
->virtual_start
);
2004 ringbuf
->virtual_start
= NULL
;
2005 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2008 static u32
*vmap_obj(struct drm_i915_gem_object
*obj
)
2010 struct sg_page_iter sg_iter
;
2011 struct page
**pages
;
2015 pages
= drm_malloc_ab(obj
->base
.size
>> PAGE_SHIFT
, sizeof(*pages
));
2020 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0)
2021 pages
[i
++] = sg_page_iter_page(&sg_iter
);
2023 addr
= vmap(pages
, i
, 0, PAGE_KERNEL
);
2024 drm_free_large(pages
);
2029 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
2030 struct intel_ringbuffer
*ringbuf
)
2032 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2033 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2036 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2037 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, 0);
2041 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2043 i915_gem_object_ggtt_unpin(obj
);
2047 ringbuf
->virtual_start
= vmap_obj(obj
);
2048 if (ringbuf
->virtual_start
== NULL
) {
2049 i915_gem_object_ggtt_unpin(obj
);
2053 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
2057 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2059 i915_gem_object_ggtt_unpin(obj
);
2063 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
2064 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
2065 if (ringbuf
->virtual_start
== NULL
) {
2066 i915_gem_object_ggtt_unpin(obj
);
2074 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2076 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2077 ringbuf
->obj
= NULL
;
2080 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2081 struct intel_ringbuffer
*ringbuf
)
2083 struct drm_i915_gem_object
*obj
;
2087 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2089 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
2093 /* mark ring buffers as read-only from GPU side by default */
2101 struct intel_ringbuffer
*
2102 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2104 struct intel_ringbuffer
*ring
;
2107 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2109 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2111 return ERR_PTR(-ENOMEM
);
2114 ring
->ring
= engine
;
2115 list_add(&ring
->link
, &engine
->buffers
);
2118 /* Workaround an erratum on the i830 which causes a hang if
2119 * the TAIL pointer points to within the last 2 cachelines
2122 ring
->effective_size
= size
;
2123 if (IS_I830(engine
->dev
) || IS_845G(engine
->dev
))
2124 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2126 ring
->last_retired_head
= -1;
2127 intel_ring_update_space(ring
);
2129 ret
= intel_alloc_ringbuffer_obj(engine
->dev
, ring
);
2131 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2133 list_del(&ring
->link
);
2135 return ERR_PTR(ret
);
2142 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2144 intel_destroy_ringbuffer_obj(ring
);
2145 list_del(&ring
->link
);
2149 static int intel_init_ring_buffer(struct drm_device
*dev
,
2150 struct intel_engine_cs
*ring
)
2152 struct intel_ringbuffer
*ringbuf
;
2155 WARN_ON(ring
->buffer
);
2158 INIT_LIST_HEAD(&ring
->active_list
);
2159 INIT_LIST_HEAD(&ring
->request_list
);
2160 INIT_LIST_HEAD(&ring
->execlist_queue
);
2161 INIT_LIST_HEAD(&ring
->buffers
);
2162 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2163 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
2165 init_waitqueue_head(&ring
->irq_queue
);
2167 ringbuf
= intel_engine_create_ringbuffer(ring
, 32 * PAGE_SIZE
);
2168 if (IS_ERR(ringbuf
))
2169 return PTR_ERR(ringbuf
);
2170 ring
->buffer
= ringbuf
;
2172 if (I915_NEED_GFX_HWS(dev
)) {
2173 ret
= init_status_page(ring
);
2177 BUG_ON(ring
->id
!= RCS
);
2178 ret
= init_phys_status_page(ring
);
2183 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2185 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2187 intel_destroy_ringbuffer_obj(ringbuf
);
2191 ret
= i915_cmd_parser_init_ring(ring
);
2198 intel_ringbuffer_free(ringbuf
);
2199 ring
->buffer
= NULL
;
2203 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
2205 struct drm_i915_private
*dev_priv
;
2207 if (!intel_ring_initialized(ring
))
2210 dev_priv
= to_i915(ring
->dev
);
2212 intel_stop_ring_buffer(ring
);
2213 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
2215 intel_unpin_ringbuffer_obj(ring
->buffer
);
2216 intel_ringbuffer_free(ring
->buffer
);
2217 ring
->buffer
= NULL
;
2220 ring
->cleanup(ring
);
2222 cleanup_status_page(ring
);
2224 i915_cmd_parser_fini_ring(ring
);
2225 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2228 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
2230 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2231 struct drm_i915_gem_request
*request
;
2235 if (intel_ring_space(ringbuf
) >= n
)
2238 /* The whole point of reserving space is to not wait! */
2239 WARN_ON(ringbuf
->reserved_in_use
);
2241 list_for_each_entry(request
, &ring
->request_list
, list
) {
2242 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
2248 if (WARN_ON(&request
->list
== &ring
->request_list
))
2251 ret
= i915_wait_request(request
);
2255 ringbuf
->space
= space
;
2259 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
2261 uint32_t __iomem
*virt
;
2262 int rem
= ringbuf
->size
- ringbuf
->tail
;
2264 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2267 iowrite32(MI_NOOP
, virt
++);
2270 intel_ring_update_space(ringbuf
);
2273 int intel_ring_idle(struct intel_engine_cs
*ring
)
2275 struct drm_i915_gem_request
*req
;
2277 /* Wait upon the last request to be completed */
2278 if (list_empty(&ring
->request_list
))
2281 req
= list_entry(ring
->request_list
.prev
,
2282 struct drm_i915_gem_request
,
2285 /* Make sure we do not trigger any retires */
2286 return __i915_wait_request(req
,
2287 atomic_read(&to_i915(ring
->dev
)->gpu_error
.reset_counter
),
2288 to_i915(ring
->dev
)->mm
.interruptible
,
2292 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2294 request
->ringbuf
= request
->ring
->buffer
;
2298 int intel_ring_reserve_space(struct drm_i915_gem_request
*request
)
2301 * The first call merely notes the reserve request and is common for
2302 * all back ends. The subsequent localised _begin() call actually
2303 * ensures that the reservation is available. Without the begin, if
2304 * the request creator immediately submitted the request without
2305 * adding any commands to it then there might not actually be
2306 * sufficient room for the submission commands.
2308 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
2310 return intel_ring_begin(request
, 0);
2313 void intel_ring_reserved_space_reserve(struct intel_ringbuffer
*ringbuf
, int size
)
2315 WARN_ON(ringbuf
->reserved_size
);
2316 WARN_ON(ringbuf
->reserved_in_use
);
2318 ringbuf
->reserved_size
= size
;
2321 void intel_ring_reserved_space_cancel(struct intel_ringbuffer
*ringbuf
)
2323 WARN_ON(ringbuf
->reserved_in_use
);
2325 ringbuf
->reserved_size
= 0;
2326 ringbuf
->reserved_in_use
= false;
2329 void intel_ring_reserved_space_use(struct intel_ringbuffer
*ringbuf
)
2331 WARN_ON(ringbuf
->reserved_in_use
);
2333 ringbuf
->reserved_in_use
= true;
2334 ringbuf
->reserved_tail
= ringbuf
->tail
;
2337 void intel_ring_reserved_space_end(struct intel_ringbuffer
*ringbuf
)
2339 WARN_ON(!ringbuf
->reserved_in_use
);
2340 if (ringbuf
->tail
> ringbuf
->reserved_tail
) {
2341 WARN(ringbuf
->tail
> ringbuf
->reserved_tail
+ ringbuf
->reserved_size
,
2342 "request reserved size too small: %d vs %d!\n",
2343 ringbuf
->tail
- ringbuf
->reserved_tail
, ringbuf
->reserved_size
);
2346 * The ring was wrapped while the reserved space was in use.
2347 * That means that some unknown amount of the ring tail was
2348 * no-op filled and skipped. Thus simply adding the ring size
2349 * to the tail and doing the above space check will not work.
2350 * Rather than attempt to track how much tail was skipped,
2351 * it is much simpler to say that also skipping the sanity
2352 * check every once in a while is not a big issue.
2356 ringbuf
->reserved_size
= 0;
2357 ringbuf
->reserved_in_use
= false;
2360 static int __intel_ring_prepare(struct intel_engine_cs
*ring
, int bytes
)
2362 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2363 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2364 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2365 int ret
, total_bytes
, wait_bytes
= 0;
2366 bool need_wrap
= false;
2368 if (ringbuf
->reserved_in_use
)
2369 total_bytes
= bytes
;
2371 total_bytes
= bytes
+ ringbuf
->reserved_size
;
2373 if (unlikely(bytes
> remain_usable
)) {
2375 * Not enough space for the basic request. So need to flush
2376 * out the remainder and then wait for base + reserved.
2378 wait_bytes
= remain_actual
+ total_bytes
;
2381 if (unlikely(total_bytes
> remain_usable
)) {
2383 * The base request will fit but the reserved space
2384 * falls off the end. So only need to to wait for the
2385 * reserved size after flushing out the remainder.
2387 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
2389 } else if (total_bytes
> ringbuf
->space
) {
2390 /* No wrapping required, just waiting. */
2391 wait_bytes
= total_bytes
;
2396 ret
= ring_wait_for_space(ring
, wait_bytes
);
2401 __wrap_ring_buffer(ringbuf
);
2407 int intel_ring_begin(struct drm_i915_gem_request
*req
,
2410 struct intel_engine_cs
*ring
;
2411 struct drm_i915_private
*dev_priv
;
2414 WARN_ON(req
== NULL
);
2416 dev_priv
= ring
->dev
->dev_private
;
2418 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2419 dev_priv
->mm
.interruptible
);
2423 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2427 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2431 /* Align the ring tail to a cacheline boundary */
2432 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2434 struct intel_engine_cs
*ring
= req
->ring
;
2435 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2438 if (num_dwords
== 0)
2441 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2442 ret
= intel_ring_begin(req
, num_dwords
);
2446 while (num_dwords
--)
2447 intel_ring_emit(ring
, MI_NOOP
);
2449 intel_ring_advance(ring
);
2454 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2456 struct drm_device
*dev
= ring
->dev
;
2457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2459 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2460 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2461 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2463 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2466 ring
->set_seqno(ring
, seqno
);
2467 ring
->hangcheck
.seqno
= seqno
;
2470 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2473 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2475 /* Every tail move must follow the sequence below */
2477 /* Disable notification that the ring is IDLE. The GT
2478 * will then assume that it is busy and bring it out of rc6.
2480 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2481 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2483 /* Clear the context id. Here be magic! */
2484 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2486 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2487 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2488 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2490 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2492 /* Now that the ring is fully powered up, update the tail */
2493 I915_WRITE_TAIL(ring
, value
);
2494 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2496 /* Let the ring send IDLE messages to the GT again,
2497 * and so let it sleep to conserve power when idle.
2499 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2500 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2503 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2504 u32 invalidate
, u32 flush
)
2506 struct intel_engine_cs
*ring
= req
->ring
;
2510 ret
= intel_ring_begin(req
, 4);
2515 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2518 /* We always require a command barrier so that subsequent
2519 * commands, such as breadcrumb interrupts, are strictly ordered
2520 * wrt the contents of the write cache being flushed to memory
2521 * (and thus being coherent from the CPU).
2523 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2526 * Bspec vol 1c.5 - video engine command streamer:
2527 * "If ENABLED, all TLBs will be invalidated once the flush
2528 * operation is complete. This bit is only valid when the
2529 * Post-Sync Operation field is a value of 1h or 3h."
2531 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2532 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2534 intel_ring_emit(ring
, cmd
);
2535 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2536 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2537 intel_ring_emit(ring
, 0); /* upper addr */
2538 intel_ring_emit(ring
, 0); /* value */
2540 intel_ring_emit(ring
, 0);
2541 intel_ring_emit(ring
, MI_NOOP
);
2543 intel_ring_advance(ring
);
2548 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2549 u64 offset
, u32 len
,
2550 unsigned dispatch_flags
)
2552 struct intel_engine_cs
*ring
= req
->ring
;
2553 bool ppgtt
= USES_PPGTT(ring
->dev
) &&
2554 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2557 ret
= intel_ring_begin(req
, 4);
2561 /* FIXME(BDW): Address space and security selectors. */
2562 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2563 (dispatch_flags
& I915_DISPATCH_RS
?
2564 MI_BATCH_RESOURCE_STREAMER
: 0));
2565 intel_ring_emit(ring
, lower_32_bits(offset
));
2566 intel_ring_emit(ring
, upper_32_bits(offset
));
2567 intel_ring_emit(ring
, MI_NOOP
);
2568 intel_ring_advance(ring
);
2574 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2575 u64 offset
, u32 len
,
2576 unsigned dispatch_flags
)
2578 struct intel_engine_cs
*ring
= req
->ring
;
2581 ret
= intel_ring_begin(req
, 2);
2585 intel_ring_emit(ring
,
2586 MI_BATCH_BUFFER_START
|
2587 (dispatch_flags
& I915_DISPATCH_SECURE
?
2588 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2589 (dispatch_flags
& I915_DISPATCH_RS
?
2590 MI_BATCH_RESOURCE_STREAMER
: 0));
2591 /* bit0-7 is the length on GEN6+ */
2592 intel_ring_emit(ring
, offset
);
2593 intel_ring_advance(ring
);
2599 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2600 u64 offset
, u32 len
,
2601 unsigned dispatch_flags
)
2603 struct intel_engine_cs
*ring
= req
->ring
;
2606 ret
= intel_ring_begin(req
, 2);
2610 intel_ring_emit(ring
,
2611 MI_BATCH_BUFFER_START
|
2612 (dispatch_flags
& I915_DISPATCH_SECURE
?
2613 0 : MI_BATCH_NON_SECURE_I965
));
2614 /* bit0-7 is the length on GEN6+ */
2615 intel_ring_emit(ring
, offset
);
2616 intel_ring_advance(ring
);
2621 /* Blitter support (SandyBridge+) */
2623 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2624 u32 invalidate
, u32 flush
)
2626 struct intel_engine_cs
*ring
= req
->ring
;
2627 struct drm_device
*dev
= ring
->dev
;
2631 ret
= intel_ring_begin(req
, 4);
2636 if (INTEL_INFO(dev
)->gen
>= 8)
2639 /* We always require a command barrier so that subsequent
2640 * commands, such as breadcrumb interrupts, are strictly ordered
2641 * wrt the contents of the write cache being flushed to memory
2642 * (and thus being coherent from the CPU).
2644 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2647 * Bspec vol 1c.3 - blitter engine command streamer:
2648 * "If ENABLED, all TLBs will be invalidated once the flush
2649 * operation is complete. This bit is only valid when the
2650 * Post-Sync Operation field is a value of 1h or 3h."
2652 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2653 cmd
|= MI_INVALIDATE_TLB
;
2654 intel_ring_emit(ring
, cmd
);
2655 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2656 if (INTEL_INFO(dev
)->gen
>= 8) {
2657 intel_ring_emit(ring
, 0); /* upper addr */
2658 intel_ring_emit(ring
, 0); /* value */
2660 intel_ring_emit(ring
, 0);
2661 intel_ring_emit(ring
, MI_NOOP
);
2663 intel_ring_advance(ring
);
2668 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2671 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2672 struct drm_i915_gem_object
*obj
;
2675 ring
->name
= "render ring";
2677 ring
->mmio_base
= RENDER_RING_BASE
;
2679 if (INTEL_INFO(dev
)->gen
>= 8) {
2680 if (i915_semaphore_is_enabled(dev
)) {
2681 obj
= i915_gem_alloc_object(dev
, 4096);
2683 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2684 i915
.semaphores
= 0;
2686 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2687 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2689 drm_gem_object_unreference(&obj
->base
);
2690 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2691 i915
.semaphores
= 0;
2693 dev_priv
->semaphore_obj
= obj
;
2697 ring
->init_context
= intel_rcs_ctx_init
;
2698 ring
->add_request
= gen6_add_request
;
2699 ring
->flush
= gen8_render_ring_flush
;
2700 ring
->irq_get
= gen8_ring_get_irq
;
2701 ring
->irq_put
= gen8_ring_put_irq
;
2702 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2703 ring
->get_seqno
= gen6_ring_get_seqno
;
2704 ring
->set_seqno
= ring_set_seqno
;
2705 if (i915_semaphore_is_enabled(dev
)) {
2706 WARN_ON(!dev_priv
->semaphore_obj
);
2707 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2708 ring
->semaphore
.signal
= gen8_rcs_signal
;
2709 GEN8_RING_SEMAPHORE_INIT
;
2711 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2712 ring
->init_context
= intel_rcs_ctx_init
;
2713 ring
->add_request
= gen6_add_request
;
2714 ring
->flush
= gen7_render_ring_flush
;
2715 if (INTEL_INFO(dev
)->gen
== 6)
2716 ring
->flush
= gen6_render_ring_flush
;
2717 ring
->irq_get
= gen6_ring_get_irq
;
2718 ring
->irq_put
= gen6_ring_put_irq
;
2719 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2720 ring
->get_seqno
= gen6_ring_get_seqno
;
2721 ring
->set_seqno
= ring_set_seqno
;
2722 if (i915_semaphore_is_enabled(dev
)) {
2723 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2724 ring
->semaphore
.signal
= gen6_signal
;
2726 * The current semaphore is only applied on pre-gen8
2727 * platform. And there is no VCS2 ring on the pre-gen8
2728 * platform. So the semaphore between RCS and VCS2 is
2729 * initialized as INVALID. Gen8 will initialize the
2730 * sema between VCS2 and RCS later.
2732 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2733 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2734 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2735 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2736 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2737 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2738 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2739 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2740 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2741 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2743 } else if (IS_GEN5(dev
)) {
2744 ring
->add_request
= pc_render_add_request
;
2745 ring
->flush
= gen4_render_ring_flush
;
2746 ring
->get_seqno
= pc_render_get_seqno
;
2747 ring
->set_seqno
= pc_render_set_seqno
;
2748 ring
->irq_get
= gen5_ring_get_irq
;
2749 ring
->irq_put
= gen5_ring_put_irq
;
2750 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2751 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2753 ring
->add_request
= i9xx_add_request
;
2754 if (INTEL_INFO(dev
)->gen
< 4)
2755 ring
->flush
= gen2_render_ring_flush
;
2757 ring
->flush
= gen4_render_ring_flush
;
2758 ring
->get_seqno
= ring_get_seqno
;
2759 ring
->set_seqno
= ring_set_seqno
;
2761 ring
->irq_get
= i8xx_ring_get_irq
;
2762 ring
->irq_put
= i8xx_ring_put_irq
;
2764 ring
->irq_get
= i9xx_ring_get_irq
;
2765 ring
->irq_put
= i9xx_ring_put_irq
;
2767 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2769 ring
->write_tail
= ring_write_tail
;
2771 if (IS_HASWELL(dev
))
2772 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2773 else if (IS_GEN8(dev
))
2774 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2775 else if (INTEL_INFO(dev
)->gen
>= 6)
2776 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2777 else if (INTEL_INFO(dev
)->gen
>= 4)
2778 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2779 else if (IS_I830(dev
) || IS_845G(dev
))
2780 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2782 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2783 ring
->init_hw
= init_render_ring
;
2784 ring
->cleanup
= render_ring_cleanup
;
2786 /* Workaround batchbuffer to combat CS tlb bug. */
2787 if (HAS_BROKEN_CS_TLB(dev
)) {
2788 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2790 DRM_ERROR("Failed to allocate batch bo\n");
2794 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2796 drm_gem_object_unreference(&obj
->base
);
2797 DRM_ERROR("Failed to ping batch bo\n");
2801 ring
->scratch
.obj
= obj
;
2802 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2805 ret
= intel_init_ring_buffer(dev
, ring
);
2809 if (INTEL_INFO(dev
)->gen
>= 5) {
2810 ret
= intel_init_pipe_control(ring
);
2818 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2821 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2823 ring
->name
= "bsd ring";
2826 ring
->write_tail
= ring_write_tail
;
2827 if (INTEL_INFO(dev
)->gen
>= 6) {
2828 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2829 /* gen6 bsd needs a special wa for tail updates */
2831 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2832 ring
->flush
= gen6_bsd_ring_flush
;
2833 ring
->add_request
= gen6_add_request
;
2834 ring
->get_seqno
= gen6_ring_get_seqno
;
2835 ring
->set_seqno
= ring_set_seqno
;
2836 if (INTEL_INFO(dev
)->gen
>= 8) {
2837 ring
->irq_enable_mask
=
2838 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2839 ring
->irq_get
= gen8_ring_get_irq
;
2840 ring
->irq_put
= gen8_ring_put_irq
;
2841 ring
->dispatch_execbuffer
=
2842 gen8_ring_dispatch_execbuffer
;
2843 if (i915_semaphore_is_enabled(dev
)) {
2844 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2845 ring
->semaphore
.signal
= gen8_xcs_signal
;
2846 GEN8_RING_SEMAPHORE_INIT
;
2849 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2850 ring
->irq_get
= gen6_ring_get_irq
;
2851 ring
->irq_put
= gen6_ring_put_irq
;
2852 ring
->dispatch_execbuffer
=
2853 gen6_ring_dispatch_execbuffer
;
2854 if (i915_semaphore_is_enabled(dev
)) {
2855 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2856 ring
->semaphore
.signal
= gen6_signal
;
2857 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2858 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2859 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2860 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2861 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2862 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2863 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2864 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2865 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2866 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2870 ring
->mmio_base
= BSD_RING_BASE
;
2871 ring
->flush
= bsd_ring_flush
;
2872 ring
->add_request
= i9xx_add_request
;
2873 ring
->get_seqno
= ring_get_seqno
;
2874 ring
->set_seqno
= ring_set_seqno
;
2876 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2877 ring
->irq_get
= gen5_ring_get_irq
;
2878 ring
->irq_put
= gen5_ring_put_irq
;
2880 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2881 ring
->irq_get
= i9xx_ring_get_irq
;
2882 ring
->irq_put
= i9xx_ring_put_irq
;
2884 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2886 ring
->init_hw
= init_ring_common
;
2888 return intel_init_ring_buffer(dev
, ring
);
2892 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2894 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2897 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2899 ring
->name
= "bsd2 ring";
2902 ring
->write_tail
= ring_write_tail
;
2903 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2904 ring
->flush
= gen6_bsd_ring_flush
;
2905 ring
->add_request
= gen6_add_request
;
2906 ring
->get_seqno
= gen6_ring_get_seqno
;
2907 ring
->set_seqno
= ring_set_seqno
;
2908 ring
->irq_enable_mask
=
2909 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2910 ring
->irq_get
= gen8_ring_get_irq
;
2911 ring
->irq_put
= gen8_ring_put_irq
;
2912 ring
->dispatch_execbuffer
=
2913 gen8_ring_dispatch_execbuffer
;
2914 if (i915_semaphore_is_enabled(dev
)) {
2915 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2916 ring
->semaphore
.signal
= gen8_xcs_signal
;
2917 GEN8_RING_SEMAPHORE_INIT
;
2919 ring
->init_hw
= init_ring_common
;
2921 return intel_init_ring_buffer(dev
, ring
);
2924 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2927 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2929 ring
->name
= "blitter ring";
2932 ring
->mmio_base
= BLT_RING_BASE
;
2933 ring
->write_tail
= ring_write_tail
;
2934 ring
->flush
= gen6_ring_flush
;
2935 ring
->add_request
= gen6_add_request
;
2936 ring
->get_seqno
= gen6_ring_get_seqno
;
2937 ring
->set_seqno
= ring_set_seqno
;
2938 if (INTEL_INFO(dev
)->gen
>= 8) {
2939 ring
->irq_enable_mask
=
2940 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2941 ring
->irq_get
= gen8_ring_get_irq
;
2942 ring
->irq_put
= gen8_ring_put_irq
;
2943 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2944 if (i915_semaphore_is_enabled(dev
)) {
2945 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2946 ring
->semaphore
.signal
= gen8_xcs_signal
;
2947 GEN8_RING_SEMAPHORE_INIT
;
2950 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2951 ring
->irq_get
= gen6_ring_get_irq
;
2952 ring
->irq_put
= gen6_ring_put_irq
;
2953 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2954 if (i915_semaphore_is_enabled(dev
)) {
2955 ring
->semaphore
.signal
= gen6_signal
;
2956 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2958 * The current semaphore is only applied on pre-gen8
2959 * platform. And there is no VCS2 ring on the pre-gen8
2960 * platform. So the semaphore between BCS and VCS2 is
2961 * initialized as INVALID. Gen8 will initialize the
2962 * sema between BCS and VCS2 later.
2964 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2965 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2966 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2967 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2968 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2969 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2970 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2971 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2972 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2973 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2976 ring
->init_hw
= init_ring_common
;
2978 return intel_init_ring_buffer(dev
, ring
);
2981 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2984 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2986 ring
->name
= "video enhancement ring";
2989 ring
->mmio_base
= VEBOX_RING_BASE
;
2990 ring
->write_tail
= ring_write_tail
;
2991 ring
->flush
= gen6_ring_flush
;
2992 ring
->add_request
= gen6_add_request
;
2993 ring
->get_seqno
= gen6_ring_get_seqno
;
2994 ring
->set_seqno
= ring_set_seqno
;
2996 if (INTEL_INFO(dev
)->gen
>= 8) {
2997 ring
->irq_enable_mask
=
2998 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2999 ring
->irq_get
= gen8_ring_get_irq
;
3000 ring
->irq_put
= gen8_ring_put_irq
;
3001 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3002 if (i915_semaphore_is_enabled(dev
)) {
3003 ring
->semaphore
.sync_to
= gen8_ring_sync
;
3004 ring
->semaphore
.signal
= gen8_xcs_signal
;
3005 GEN8_RING_SEMAPHORE_INIT
;
3008 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3009 ring
->irq_get
= hsw_vebox_get_irq
;
3010 ring
->irq_put
= hsw_vebox_put_irq
;
3011 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3012 if (i915_semaphore_is_enabled(dev
)) {
3013 ring
->semaphore
.sync_to
= gen6_ring_sync
;
3014 ring
->semaphore
.signal
= gen6_signal
;
3015 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
3016 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
3017 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
3018 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
3019 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3020 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
3021 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
3022 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
3023 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
3024 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3027 ring
->init_hw
= init_ring_common
;
3029 return intel_init_ring_buffer(dev
, ring
);
3033 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3035 struct intel_engine_cs
*ring
= req
->ring
;
3038 if (!ring
->gpu_caches_dirty
)
3041 ret
= ring
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3045 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3047 ring
->gpu_caches_dirty
= false;
3052 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3054 struct intel_engine_cs
*ring
= req
->ring
;
3055 uint32_t flush_domains
;
3059 if (ring
->gpu_caches_dirty
)
3060 flush_domains
= I915_GEM_GPU_DOMAINS
;
3062 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3066 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3068 ring
->gpu_caches_dirty
= false;
3073 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
3077 if (!intel_ring_initialized(ring
))
3080 ret
= intel_ring_idle(ring
);
3081 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
3082 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",